DDC232CGXGR_技术文档

B

u

r

Ć

B

r

o

w

n

P

r

o

d

u

c

t

s

f

r

o

m

T

e

x

a

s

I

n

s

t

r

u

m

e

n

t

s

DDC232

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

32-Channel, Current-Input

Analog-to-Digital Converter

The DDC232 has a serial interface designed for

FEATURES

daisy-chaining in multi-device systems. Simply

connect the output of one device to the input of the

next to create the chain. Common clocking feeds all

the devices in the chain so that the digital overhead

in a multi-DDC232 system is minimal.

•

SINGLE-CHIP SOLUTION TO DIRECTLY

MEASURE 32 LOW-LEVEL CURRENTS

HIGH-PRECISION, TRUE INTEGRATING

FUNCTION

INTEGRAL LINEARITY:

The DDC232 uses a +5V analog supply and a +2.7V

to +3.6V digital supply. Operating over the

temperature range of 0°C to +70°C, the DDC232 is

offered in a BGA-64 package.

±0.025% of Reading ±1.0ppm of FSR

•

VERY LOW NOISE: 5.3ppm of FSR

LOW POWER: 7mW/channel

ADJUSTABLE FULL-SCALE RANGE

ADJUSTABLE DATA RATE: Up to 6kSPS

– Integration Times Down to 166.5µs

DAISY-CHAINABLE SERIAL INTERFACE

AVDD

VREF

DVDD

CLK

Dual

Switched

Integrator

IN1

IN2

•

CONV

∆Σ

Modulator

Digital

Filter

Configuration

and

Control

DIN_CFG

CLK_CFG

RESET

APPLICATIONS

Dual

Switched

Integrator

•

CT SCANNER DAS

PHOTODIODE SENSORS

X-RAY DETECTION SYSTEMS

Protected by US Patent #5841310

Dual

Switched

Integrator

IN3

IN4

∆Σ

Modulator

Digital

Filter

DESCRIPTION

DVALID

DCLK

DOUT

DIN

Dual

Switched

Integrator

The DDC232 is a 20-bit, 32-channel, current-input

analog-to-digital (A/D) converter. It combines both

current-to-voltage and A/D conversion so that 32

separate low-level current output devices, such as

photodiodes, can be directly connected to its inputs

and digitized.

Dual

Switched

Integrator

IN29

IN30

Serial

Interface

∆Σ

Modulator

Digital

Filter

Dual

Switched

Integrator

For each of the 32 inputs, the DDC232 provides a

dual-switched integrator front-end. This configuration

allows for continuous current integration: while one

integrator is being digitized by the onboard A/D

converter, the other is integrating the input current.

Adjustable integration times range from 166µs to 1s,

allowing currents from fAs to µAs to be continuously

measured with outstanding precision.

Dual

Switched

Integrator

IN31

IN32

∆Σ

Modulator

Digital

Filter

Dual

Switched

Integrator

AGND

DGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

AVDD to AGND

–0.3V to +6V

–0.3V to +3.6V

±0.2V

DVDD to DGND

AGND to DGND

VREF Input to AGND

Analog Input to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature

Storage Temperature

Junction Temperature (T_J)

2.0V to AVDD + 0.3V

–0.3V to +0.7V

–0.3V to DVDD + 0.3V

–0.3V to AVDD + 0.3V

0°C to +70°C

–60°C to +150°C

+150°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

2

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS

At T_A= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, t_INT= 333µs in Low-Power mode (CLK = 5MHz),

Range = 7, and continuous mode operation, unless otherwise noted.

DDC232C

TYP

DDC232CK

TYP

PARAMETER

ANALOG INPUT RANGE

Range 1

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

45

50

55

45

50

55

pC

Range 2

90

100

150

200

250

300

350

110

165

220

275

330

385

90

100

150

200

250

300

350

110

165

220

275

330

385

Range 3

135

180

225

270

315

135

180

225

270

315

Range 4

Range 5

Range 6

Range 7

Negative Full-Scale Range

DYNAMIC CHARACTERISTICS

Data Rate

–0.4% of Positive Full-Scale Range

Low-Power Mode

High-Speed Mode

3

3.125

3

6

3.125

6.2

kSPS

µs

Not Supported

Integration Time, t_INT

System Clock (CLK)

Continuous Mode, Low-Power Mode

Continuous Mode, High-Speed Mode

Non-Continuous Mode

320

1,000,000

320

162

50

1

1,000,000

Not Supported

µs

50

1

µs

Low-Power Mode, Clk_4x = 0

High-Speed Mode, Clk_4x = 0

Low-Power Mode, Clk_4x = 1

High-Speed Mode, Clk_4x = 1

5

MHz

1

10

20

40

20

1

10

20

40

20

4

Data Clock (DCLK)

Configuration Clock (CLK_CFG)

ACCURACY

Noise, Low-Level Input⁽¹⁾

Integral Linearity Error⁽⁴⁾

C_SENSOR⁽²⁾= 50pF

5.3

7

ppm of FSR⁽³⁾, rms

±0.025% Reading ± 1.0ppm FSR, typ

±0.05% Reading ± 1.5ppm FSR, max

Resolution

Format = 1

Format = 0

20

16

20

16

Bits

Input Bias Current

±0.1

0.1

±10

0.5

±0.1

0.1

±10

0.5

pA

Range Error Match⁽⁵⁾

Range Sensitivity to VREF

Offset Error

% of FSR

VREF = 4.096 ±0.1V

1:1

±200

±100

±0.1

100

±1000

±200

±100

±0.1

100

±1000

ppm of FSR

mV

Offset Error Match⁽⁵⁾

DC Bias Voltage⁽⁶⁾

Low-Level Input (< 1% FSR)

at DC

±2

Power-Supply Rejection Ratio

±800

ppm of FSR/V

(1) Input is less than 1% of full-scale.

(2) C_SENSORis the capacitance seen at the DDC232 inputs from wiring, photodiode, etc.

(3) FSR is Full-Scale Range.

(4) A best-fit line is used in measuring nonlinearity.

(5) Matching between side A and side B of the same input.

(6) Voltage produced by the DDC232 at its input that is applied to the sensor.

3

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

At T_A= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, t_INT= 333µs in Low-Power mode (CLK = 5MHz),

Range = 7, and continuous mode operation, unless otherwise noted.

DDC232C

TYP

DDC232CK

TYP

PARAMETER

PERFORMANCE OVER TEMPERATURE

Offset Drift

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

±0.5

±0.2

±3

5⁽⁷⁾

2⁽⁷⁾

±0.5

±0.2

±3

5⁽⁷⁾

2⁽⁷⁾

ppm of FSR/°C

ppm of FSR/minute

µV/°C

Offset Drift Stability

DC Bias Voltage Drift⁽⁸⁾

Input Bias Current Drift

Range Drift⁽⁹⁾

T_A= +25°C to +45°C

0.01

25

1⁽⁷⁾

50

0.01

25

1⁽⁷⁾

50

pA/°C

ppm/°C

Range Drift Match⁽¹⁰⁾

REFERENCE

±5

ppm/°C

Voltage

4.000

4.096

325

4.200

4.000

4.096

325

4.200

V

Input Current⁽¹¹⁾

Average Value with t_INT= 333µs

Average Value with t_INT= 166.5µs

µA

650

DIGITAL INPUT/OUTPUT

Logic Levels

V_IH

V_IL

(0.8)DVDD

–0.1

DVDD + 0.1

(0.2)DVDD

(0.8)DVDD

–0.1

DVDD + 0.1

(0.2)DVDD

V

V_OH

V_OL

I_OH= –500µA

I_OL= 500µA

DVDD – 0.4

V

0.4

V

Input Current (I_IN

)

0 < V_IN< DVDD

±10

µA

Data Format⁽¹²⁾

Straight Binary

POWER-SUPPLY REQUIREMENTS

Analog Power-Supply Voltage (AVDD)

Digital Power-Supply Voltage (DVDD)

Supply Current

4.75

2.7

5.0

3.0

5.25

3.6

4.75

2.7

5.0

3.0

5.25

3.6

V

Analog Current

Low-Power Mode

High-Speed Mode

Low-Power Mode

High-Speed Mode

Low-Power Mode

High-Speed Mode

Low-Power Mode

High-Speed Mode

41

Not Supported

3.7

41

60

mA

Digital Current

3.7

7.0

224

320

7

mA

Not Supported

224

mA

Total Power Dissipation

Per Channel Power Dissipation

288

9

288

9

mW

Not Supported

7

mW

mW/Channel

Not Supported

10

(7) Ensured by design, not production tested.

(8) Voltage produced by the DDC232 at its input that is applied to the sensor.

(9) Range drift does not include external reference drift.

(10) Matching between side A and side B of the same input.

(11) Input reference current decreases with increasing t_INT(see the Voltage Reference section, page 10).

(12) Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit.

4

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

PIN CONFIGURATION

Top View

BGA

Columns

H

G

F

E

D

C

B

A

IN21

IN22

IN23

IN24

IN25

IN26

IN27

IN28

1

2

3

4

5

6

7

8

IN5

IN17

IN6

IN18

IN2

IN7

IN19

IN8

IN20

IN4

IN9

IN10

IN30

IN11

IN31

IN12

IN32

IN29

IN1

IN3

IN13

IN14

IN15

IN16

QGND

AGND

AVDD

AGND

AVDD

AGND

AVDD

AGND

DGND

DOUT

AGND

DGND

RESET

DGND

AGND

VREF

DVDD

DIN

AGND

VREF

DGND

CONV

DVALID DIN_CFG CLK_CFG DGND

DCLK

DGND

CLK

NC

PIN DESCRIPTIONS

IN1–32

QGND

AGND

DGND

AVDD

VREF

LOCATION

Rows 1–4

H5

FUNCTION

Analog Input

Analog

DESCRIPTION

Analog Inputs for Channels 1 to 32

Quiet Analog Ground

G5, F5, E5, D5, C5, B5, A5, D6, H6

Analog

Analog Ground

A7, C6, D7, E7, C8, G8

Digital

Digital Ground

E6, F6, G6

A6, B6

H7

Analog

Analog Power Supply, +5V Nominal

Analog Input

Digital Output

Digital Input

Digital

External Voltage Reference Input, +4.096V Nominal

Data Valid Output, Active Low

DVALID

DIN_CFG

CLK_CFG

RESET

DVDD

CONV

DIN

G7

Configuration Register Data Input

Configuration Register Clock Input

Digital Reset, Active Low

F7

C7

B7

Digital Power Supply, 3.3V Nominal

Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A

Serial Data Input

A8

Digital Input

Digital Output

No Connect

Digital Input

B8

DOUT

NC

D8

Serial Data Output

E8

Do not connect; must be left floating.

Master Clock Input

CLK

F8

DCLK

H8

Serial Data Clock Input

5

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

At T_A= 25°C, unless otherwise indicated.

NOISE vs C_SENSOR

20

18

16

14

12

10

8

Noise (ppm of FSR, rms)

Low−Power Mode

C_SENSOR

or

Range

5

Range

7

Range Range Range Range

Range

6

High−Speed Mode

(pF)

1

2

3

4

Range 1

5.0

5.4

6.0

4.8

5.0

5.3

0

9.3

6.3

8.0

9.7

5.5

6.4

7.6

5.2

5.8

6.5

4.9

5.1

5.6

22

47

12.4

15.0

Range 2

6

4

Range 7

40

2

0

10

20

30

50

C_SENSOR(pF)

Figure 1.

6

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

THEORY OF OPERATION

digitized while the other 32 integrators are in the

integration mode. This integration and A/D

conversion process is controlled by the system clock,

CLK. The results from side A and side B of each

signal input are stored in a serial output shift register.

The DVALID output goes low when the shift register

contains valid data.

The block diagram of the DDC232 is shown in

Figure 2. The device contains 32 identical input

channels

that

perform

the

function

of

a

current-to-voltage integration followed by

multiplexed A/D conversion. Each input has two

integrators so that the current-to-voltage integration

can be continuous in time. The output of the 64

integrators are switched to 16 delta-sigma (∆Σ)

converters via multiplexers. With the DDC232 in the

continuous integration mode, the output of the

integrators from one side of the inputs will be

AVDD

VREF

DVDD

CLK

Dual

Switched

Integrator

IN1

CONV

∆Σ

Configuration

Digital

Modulator

and

DIN_CFG

CLK_CFG

RESET

Filter

Control

Dual

Switched

Integrator

IN2

IN3

Dual

Switched

Integrator

∆Σ

Digital

Filter

Modulator

Dual

Switched

Integrator

DVALID

DCLK

DOUT

DIN

IN4

Dual

Switched

Integrator

IN29

Serial

∆Σ

Interface

Digital

Filter

Modulator

Dual

Switched

Integrator

IN30

IN31

Dual

Switched

Integrator

∆Σ

Digital

Filter

Modulator

Dual

Switched

Integrator

IN32

AGND

DGND

Figure 2. DDC232 Block Diagram

7

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

DEVICE OPERATION

At the completion of an A/D conversion, the charge

on the integration capacitor (C_F) is reset with S_REF1

and S_RESET(see Figure 4 and Figure 5a). This is

done during reset. In this manner, the selected

capacitor is charged to the reference voltage, VREF.

Once the integration capacitor is charged, S_REF1and

S_RESETare switched so that VREF is no longer

connected to the amplifier circuit while it waits to

begin integrating (see Figure 5b). With the rising

edge of CONV, S_INTAcloses, which begins the

integration of side A. This process puts the integrator

stage into its integrate mode (see Figure 5c).

Basic Integration Cycle

The topology of the front end of the DDC232 is an

analog integrator as shown in Figure 3. In this

diagram, only input IN1 is shown. The input stage

consists of an operational amplifier, a selectable

feedback capacitor network (C_F), and several

switches that implement the integration cycle. The

timing relationships of all of the switches shown in

Figure 3 are illustrated in Figure 4. Figure 4

conceptualizes the operation of the integrator input

stage of the DDC232 and should not be used as an

exact timing tool for design.

Charge from the input signal is collected on the

integration capacitor, causing the voltage output of

the amplifier to decrease. The falling edge of CONV

stops the integration by switching the input signal

from side A to side B (S_INTAand S_INTB). Prior to the

falling edge of CONV, the signal on side B was

converted by the A/D converter and reset during the

time that side A was integrating. With the falling edge

of CONV, side B starts integrating the input signal. At

See Figure 5 for the block diagrams of the reset,

integrate, wait, and convert states of the integrator

section of the DDC232. This internal switching

network is controlled externally with the convert pin

(CONV), and the system clock (CLK). For the best

noise performance, CONV must be synchronized

with the rising edge of CLK. It is recommended that

CONV toggle within ±10ns of the rising edge of CLK.

this point, the output voltage of the side

operational amplifier is presented to the input of the

∆Σ A/D converter (see Figure 5d).

A

The noninverting inputs of the integrators are

connected to ground. Consequently, the DDC232

analog ground should be as clean as possible. The

internal and external capacitors (C_F), are shown in

parallel between the inverting input and output of the

operational amplifier. At the beginning of

conversion, the switches S_A/D, S_INTA, S_INTB, S_REF1

a

,

S_REF2, and S_RESETare set (see Figure 4).

S_REF1

VREF

3pF

50pF

Range[2] Bit

25pF

Range[1] Bit

12.5pF

Range[0] Bit

S_INTA

Input

Current

S_REF2

S_ADC1A

IN1

S_RESET

To Converter

ESD

Protection

Diodes

Integrator A

S_INTB

Photodiode

Integrator B (same as A)

Figure 3. Basic Integration Configuration for Input 1

8

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

CONV

CLK

S_INTA

S_INTB

S_REF1

S_REF2

S_RESET

S_A/D1A

Configuration of

Integrator A

Convert

Wait

Integrate

Convert

Wait

VREF

Integrator A

Voltage Output

Figure 4. Integration Timing Diagram (see Figure 3)

S_REF1

C_F

VREF

S_INT

S_REF2

S_REF1

C_F

IN

VREF

To Converter

S_RESET

S_A/D

S_INT

S_REF2

IN

To Converter

S_RESET

S_A/D

a) Reset Configuration

S_REF1

C_F

b) Wait Configuration

VREF

S_INT

S_REF2

S_REF1

C_F

IN

VREF

To Converter

S_RESET

S_A/D

S_INT

S_REF2

IN

To Converter

S_RESET

S_A/D

c) Integrate Configuration

d) Convert Configuration

Figure 5. Diagrams for the Four Configurations of the Front-End Integrators

9

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

average VREF current of approximately 325µA. The

amount of charge needed by the ∆Σ converter is

independent of the integration time; therefore,

increasing the integration time lowers the average

current. For example, an integration time of 800µs

lowers the average VREF current to TBDµA.

Integration Capacitors

There are seven different capacitors available

on-chip for both sides of every channel in the

DDC232. These internal capacitors are trimmed in

production to achieve the specified performance for

range error of the DDC232. The range control bits

(Range[2:0]) change the capacitor value for all

integrators. Consequently, all inputs and both sides

of each input will always have the same full-scale

range. Table 1 shows the capacitor value selected

for each range selection.

It is critical that VREF be stable during the different

modes of operation (see Figure 5). The ∆Σ converter

measures the voltage on the integrator with respect

to VREF. Since the integrator capacitors are initially

reset to VREF, any drop in VREF from the time the

capacitors are reset to the time when the converter

measures the integrator output will introduce an

offset. It is also important that VREF be stable over

longer periods of time because changes in VREF

correspond directly to changes in the full-scale

range. Finally, VREF should introduce as little

additional noise as possible.

Table 1. Range Selection

INPUT

RANGE

(pC, typ)

C_F

(pF, typ)

Range[2] Range[1] Range[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

–0.04 to 12.5

–0.2 to 50

12.5

25

For these reasons, it is strongly recommended that

the external reference source be buffered with an

operational amplifier, as shown in Figure 6. In this

circuit, the voltage reference is generated by a

+4.096V reference. A low-pass filter to reduce noise

connects the reference to an operational amplifier

configured as a buffer. This amplifier should have

low noise and input/output common-mode ranges

that support VREF. Even though the circuit in

Figure 6 might appear to be unstable due to the

large output capacitors, it works well for most

operational amplifiers. It is not recommended that

series resistance be placed in the output lead to

improve stability since this can cause a drop in

VREF, which produces large offsets.

–0.4 to 100

–0.6 to 150

–0.8 to 200

–0.1 to 250

–1.2 to 300

–1.4 to 350

37.5

50

62.5

75

87.5

Voltage Reference

The external voltage reference is used to reset the

integration capacitors before an integration cycle

begins. It is also used by the ∆Σ converter while the

converter is measuring the voltage stored on the

integrators after an integration cycle ends. During

this sampling, the external reference must supply the

charge needed by the ∆Σ converter. For an

integration time of 333µs, this charge translates to an

+5V

µ

0.10 F

µ

0.47 F

7

2

3

1

6

To VREF Pin on

the DDC232

OPA350

Ω

10k

2

REF3140

3

+

µ

10

F

+

µ

0.10 F

10

F

4

Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation

10

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Frequency Response

CONFIGURATION REGISTER

The frequency response of the DDC232 is set by the

front end integrators and is that of a traditional

continuous time integrator, as shown in Figure 7. By

Some aspects of device operation are controlled by

the onboard configuration register. The DIN_CFG,

CLK_CFG, and RESET pins are used to write to this

register. When beginning a write operation, hold

CONV low and strobe RESET; see Figure 8. Then

begin shifting in the configuration data on DIN_CFG.

Data is written to the configuration register most

significant bit first. The data is internally latched on

the falling edge of CLK_CFG. Partial writes to the

configuration register are not allowed—make sure to

send all 12 bits when updating the register.

adjusting t_INT

, the user can change the 3dB

bandwidth and the location of the notches in the

response. The frequency response of the ∆Σ

converter that follows the front end integrator is of no

consequence because the converter samples a held

signal from the integrators. That is, the input to the

∆Σ converter is always a DC signal. Since the output

of the front end integrators are sampled, aliasing can

occur. Whenever the frequency of the input signal

exceeds one-half of the sampling rate, the signal will

fold back down to lower frequencies.

Optional readback of the configuration register is

available immediately after the write sequence.

During readback, the 12-bit configuration data

followed by a 4-bit revision id and the test pattern are

shifted out on the DOUT pin on the rising edge of

DCLK.

0

NOTE: with Format = 1, the test pattern is 304 bits

with only the last 72 bits non-zero. This sequence of

outputs is repeated twice for each DDC232 and

daisy-chaining is supported in configuration

−

10

20

30

40

50

readback. Table

2

shows the test pattern

configuration during readback. Table 3 shows the

timing for the configuration register read and write

operations. Strobe CONV to begin normal operation.

Table 2. Test Pattern During Readback

TEST PATTERN

(Hex)

TOTAL

READBACK BITS

1

t _INT

0.1

10

t _INT

100

t _INT

Format BIT

t _INT

0

1

30F066012480F6h

512

640

Frequency

30F066012480F69055h

Figure 7. TFrequency Response

11

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

t_RST

RESET

Configuration Register Operations

t_WTWR

Normal Operation

t_WTRST

CLK_CFG

t_STCF

t_HDCF

MSB

LSB

DIN_CFG

Read Configuration Register

and Test Pattern

Write Configuration Register Data

DCLK

DOUT

MSB

LSB

Configuration

Register

Data

Test Pattern

CONV

Figure 8. Configuration Register Write and Read Operations

Table 3. Timing for the Configuration Register Read/Write

SYMBOL

t_WTRST

t_WTWR

DESCRIPTION

MIN

2

TYP

MAX

UNITS

µs

Wait Required from Reset High to First Rising Edge of CLK_CFG

Wait Required from Last CLK-CFG of Write Operation to

First CLK_CFG of Read Operation

2

µs

t_STCF

t_HDCF

t_RST

Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG

Hold Time for DIN_CFG After Falling Edge of CLK_CFG

Pulse Width for RESET Active

10

1

ns

µs

12

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Configuration Register

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Range[2] Range[1] Range[0]

Format

Pwr/Spd

Clk_4x

0

Test

Bits 11–9

Range[2:0] Analog Input Range

000: 12.5pC

001: 50pC

010: 100pC

011: 150pC

100: 200pC

101: 250pC

110: 300pC

111: 350pC (default)

Bit 8

Bit 7

Format

0 = 16-Bit Output

1 = 20-Bit Output (default)

Format selects how many bits are used in the data output word.

Pwr/Spd

0 = Low-Power Mode (default)

1 = High-Speed Mode (DDC232CK Only)

TYPICAL

POWER/CHANNEL (mW)

MAXIMUM CLK

MAXIMUM

DATA RATE (kHz)

Pwr/Spd BIT

MODE

FREQUENCY (MHz)⁽¹⁾

0

1⁽²⁾

Low-Power

High-Speed⁽²⁾

7

5

3.125

6

10

(1) Assumes Clk_4x = 0.

(2) Only the DDC232CK supports High-Speed mode.

Bit 6

Clk_4x (System Clock Divider)

0 = Internal Clock Divider = 1 (default)

1 = Internal Clock Divider = 4

The Clk_4x input enables an internal divider on the system clock. When Clk_4x = 1, the system

clock is divided by 4. This allows a 4X faster system clock, which in turn provides a finer

quantization of the integration time because the CONV signal needs to be synchronized with the

system clock for the best performance.

Clk_4x BIT

CLK DIVIDER VALUE

CLK FREQUENCY

5MHz

INTERNAL CLOCK FREQUENCY

0

1

4

5MHz

20MHz

Bits 5–1

Bit 0

00000

Test Mode

0 = Test Mode Off (default)

1 = Test Mode On

When Test Mode is used, the inputs (IN1 through IN32) are disconnected from the DDC232

integrators to enable the user to measure a zero input signal regardless of the current supplied

to the inputs. The test mode works with both the continuous and non-continuous modes.

13

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

DIGITAL INTERFACE

with CONV. This uncertainty is ± 1/f_CLK. Polling

DVALID eliminates any concern about this

relationship. If data read back is timed from CONV,

wait the maximum value of t₇or t₈to insure data is

valid.

The digital interface of the DDC232 outputs the

digital results via a synchronous serial interface

consisting of a data clock (DCLK), a valid data pin

(DVALID), a serial data output pin (DOUT), and a

serial data input pin (DIN). The integration and

conversion process is fundamentally independent of

the data retrieval process. Consequently, the CLK

and DCLK frequencies need not be the same,

though for best performance, it is highly

recommended that they be derived from the same

clocking source to keep their phase relationship

constant. DIN is only used when multiple converters

are cascaded and should be tied to DGND

otherwise. Depending on t_INT, CLK, and DCLK, it is

possible to daisy-chain multiple converters. This

greatly simplifies the interconnection and routing of

the digital outputs in those applications where a large

number of converters are needed. Configuration of

the DDC232 is set by a dedicated register addressed

using the DIN_CFG and CLK_CFG pins.

Reset (RESET)

The DDC232 is reset asynchronously by taking the

RESET input low, as shown in Figure 9. Make sure

the release pulse is at least 1µs wide. After resetting

the DDC232, wait at least four conversions before

using the data. It is very important that RESET is

glitch-free to avoid unintentional resets.

µ

> 1

s

RESET

Figure 9. Reset Timing

System and Data Clocks (CLK and CONV)

Conversion Rate

The system clock is supplied to CLK and the data

clock is supplied to DCLK. Make sure the clock

signals are clean—avoid overshoot or ringing. For

best performance, generate both clocks from the

same clock source. DCLK should be disabled by

taking it low after the data has been shifted out or

while CONV is transitioning.

The conversion rate of the DDC232 is set by a

combination of the integration time (determined by

the user) and the speed of the A/D conversion

process. The A/D conversion time is primarily a

function of the system clock (CLK) speed. One A/D

conversion cycle encompasses the conversion of two

signals (one side of each dual integrator feeding the

modulator) and the reset time for each of the

integrators involved in the two conversions. In most

situations, the A/D conversion time is shorter than

the integration time. If this condition exists, the

DDC232 will operate in the continuous mode. When

the DDC232 is in the continuous mode, the sensor

output is continuously integrated by one of the two

sides of each input.

When using multiple DDC232s, pay close attention

to the DCLK distribution on the printed circuit board

(PCB). In particular, make sure to minimize skew in

the DCLK signal because this can lead to timing

violations in the serial interface specifications. See

the Cascading Multiple Converters section for more

details.

Data Valid (DVALID)

In the event that the A/D conversion takes longer

than the integration time, the DDC232 will switch into

a non-continuous mode. In non-continuous mode,

the A/D converter is not able to keep pace with the

speed of the integration process. Consequently, the

integration process is periodically halted until the

digitizing process catches up. These two basic

modes of operation for the DDC232—continuous and

non-continuous modes—are described below.

The DVALID signal indicates that data is ready. Data

retrieval may begin after DVALID goes low. This

signal is generated using an internal clock divided

down from the system clock, CLK. The phase

relationship between this internal clock and CLK is

set when power is first applied and is random. Since

the user must synchronize CONV with CLK, the

DVALID signal will have a random phase relationship

14

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Continuous and Non-Continuous Operational

Modes

Four signals are used to control progression around

the state diagram: CONV, mbsy, and their

complements. The state machine uses the level as

opposed to the edges of CONV to control the

progression. mbsy is an internally-generated signal

not available to the user. It is active whenever a

measurement/reset/auto-zero (m/r/az) cycle is in

progress.

Figure 10 shows the state diagram of the DDC232.

In all, there are eight states. Table 4 provides a brief

explanation of each state.

During the continuous (cont) mode, mbsy is not

active when CONV toggles. The non-integrating side

is always ready to begin integrating when the other

side finishes its integration. Consequently, monitoring

the current status of CONV is all that is needed to

know the current state. Cont mode operation

corresponds to states 3–6. Two of the states, 3 and

6, only perform an integration (no m/r/az cycle).

CONV|mbsy

1

2

•

CONV mbsy

Ncont

CONV

3

•

CONV mbsy

Int A

Cont

mbsy becomes important when operating in the

non-continuous (ncont) mode (states 1, 2, 7, and 8).

Whenever CONV is toggled while mbsy is active, the

DDC232 will enter or remain in either ncont state 1

(or 8). After mbsy goes inactive, state 2 (or 7) is

entered. This state prepares the appropriate side for

integration. In the ncont states, the inputs to the

DDC232 are grounded.

CONV

4

5

•

CONV mbsy

Int B/Meas A

Cont

Int A/Meas B

Cont

•

CONV mbsy

CONV

6

•

CONV mbsy

Int B

Cont

One interesting observation from the state diagram is

that the integrations always alternate between sides

A and B. This relationship holds for any CONV

pattern and is independent of the mode. States 2

and 7 insure this relationship during the ncont mode.

CONV

7

8

Ncont

•

CONV mbsy

When power is first applied to the DDC232, the

beginning state is either 1 or 8, depending on the

initial level of CONV. For CONV held high at

power-up, the beginning state is 1. Conversely, for

CONV held low at power-up, the beginning state is 8.

In general, there is a symmetry in the state diagram

between states 1–8, 2–7, 3–6, and 4–5. Inverting

CONV results in the states progressing through their

symmetrical match.

CONV|mbsy

State Diagram Notation:

•

CONV mbsy = CONV high AND mbsy active.

CONV|mbsy = CONV high OR mbsy active.

Figure 10. Integrate/Measure State Diagram

Table 4. State Descriptions

STATE

MODE

DESCRIPTION

1

Ncont

Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state

when CONV is initially held High.

2

3

4

5

6

7

8

Ncont

Cont

Prepare side A for integration.

Integrate on side A.

Cont

Integrate on side B; m/r/az on side A.

Integrate on side A; m/r/az on side B.

Integrate on side B.

Cont

Ncont

Prepare side B for integration.

Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state

when CONV is initially held Low.

15

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

TIMING EXAMPLES

diagram. The following two traces show when

integrations and measurement cycles are underway.

The internal signal mbsy is shown next. Finally,

DVALID is given. As described in the data sheet,

DVALID goes active low when data is ready to be

retrieved from the DDC232. It stays low until DCLK is

taken high and then back low by the user. The text

below the DVALID pulse indicates the side of the

data available to be read and arrows help match the

data to the corresponding integration.

Continuous Mode

A few timing diagrams help illustrate the operation of

the integrate/measure state machine. These

diagrams are shown in Figure 11 through Figure 16.

Table 5 gives generalized timing specifications in

units of CLK periods for Clk_4x = 0. If Clk_4x = 1,

these values increase by a factor of 4 because of the

internal clock divider. Values (in µs) for Table 5 can

be easily found for a given CLK.

Figure 11 shows a few integration cycles beginning

with initial power-up for a cont mode example. The

top signal is CONV and is supplied by the user. The

next line indicates the current state in the state

CONV

State

8

7

6

5

4

5

Integration

Status

Integrate B

Integrate A

Integrate B

Integrate A

m/r/az

Status

m/r/az

t_MRAZ

B

m/r/az

A

m/r/az B

mbsy

DVALID

t_CMDR

t = 0

Power−Up

Side B

Data

Side A

Data

Side B

Data

Figure 11. Continuous Mode Timing

Table 5. Timing Specifications Generalized in CLK Periods

VALUE

(CLK periods with Clk_4x = 0)

SYMBOL

t_MRAZ

t_CMDR

DESCRIPTION

Low-Power Mode

1552 ± 2

1382 ± 2

TBD

High-Speed Mode

1612 ± 2

1382 ± 2

TBD

Cont mode m/r/az cycle

Cont mode data ready

1st ncont mode data ready

2nd ncont mode data ready

Ncont mode m/r/az cycle

t_NCDR1

t_NCDR2

t_NCMRAZ

TBD

16

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

In Figure 11, the first state is ncont state 8. The

DDC232 always powers up in the ncont mode. In this

case, the first state is 8 because CONV is initially

low. After the first two states, cont mode operation is

reached and the states begin toggling between 4 and

5. From now on, the input is being continuously

integrated, either on side A or side B. The time

needed for the m/r/az cycle, t_MRAZ, is the same time

that determines the boundary between the cont and

ncont modes described earlier in the Overview

section. DVALID goes low after CONV toggles in

time t_CMDR, indicating that data is ready to be

retrieved.

See Figure 12 for the timing diagram of the internal

operations occurring during continuous mode

operation. Table 6 gives the timing specifications of

the internal operations occurring during continuous

mode operation.

End Integration Side A

Start Integration Side B

End Integration Side B

Start Integration Side A

End Integration Side A

Start Integration Side B

t_INT

CONV

t_INT

Side A

Side B

Side A

A/D Conversion

t_ADCONV

Odd Channels (Internal)

t_ADRST

Side A

Side B

A/D Conversion

t_ADCONV

Even Channels (Internal)

t_IRST

t_ADRST

DVALID

Side A

Data Ready

Side B

Data Ready

Figure 12. Timing Diagram for DDC232 Internal Operation in Continuous Mode

Table 6. Timing for the Internal Operation in Continuous Mode

Low-Power Mode

(CLK = 5MHz)

High-Speed Mode

(CLK = 9.6MHz)

SYMBOL DESCRIPTION

MIN

TYP

MAX

1,000,000

MIN

TYP

MAX

1,000,000

UNITS

µs

t_INT

t_ADCONV

t_ADRST

t_IRST

Integration Period (continuous mode)

320

162

A/D Conversion Time (internally controlled)

A/D Conversion Reset Time (internally controlled)

Integrator Reset Time (internally controlled)

135.6

3.2

TBD

µs

36

µs

17

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Non-Continuous Mode

Figure 13 and Figure 14 illustrate operation in non-continuous mode.

Start Integration Side A

End Integration Side A

Start Integration Side B

Start Integration Side A

End Integration Side B

Wait State

Release

State

t_INT

CONV

t_INT

t_NCRL

A/D Conversion

Odd Channels

t_ADCONV

A/D Conversion

Even Channels

t_ADCONV

t_ADRST

t_NCIRST

DVALID

Side A Data Ready

t_NCDR1

Side B Data Ready

t_NCDR2

Figure 13. Conversion Detail for the Internal Operation of Non-Continuous Mode

with Side A Integrated First

Table 7. DDC232 Internal Timing in Non-Continuous Mode

CLK = 5MHz, Clk_4x = 0

SYMBOL DESCRIPTION

MIN

TYP

MAX

UNITS

µs

t_INT

Integration Time (non-continuous mode)

TBD

1,000,000

t_ADCONV

t_ADRST

t_NCIRST

t_NCRL

A/D Conversion Time (internally controlled)

A/D Conversion Reset Time (internally controlled)

Non-Continuous Mode Integrator Reset Time (internally controlled)

Release Time

135.6

3.2

µs

TBD

µs

TBD

µs

t_NCDR1

t_NCDR2

1st Non-Continuous Mode Data Ready

2nd Non-Continuous Mode Data Ready

TBD

Start Integration Side B

End Integration Side B

Start Integration Side A

Release

State

End Integration Side A

Wait State

t_INT

CONV

t_INT

t_NCRL

A/D Conversion

Odd Channels

t_ADCONV

A/D Conversion

Even Channels

t_ADCONV

t_ADRST

t_NCIRST

DVALID

Side B

Data Ready

Side A

Data Ready

Figure 14. Internal Operation Timing Diagram Non-Continuous Mode with Side B Integrated First

18

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Changing Between Modes

is increased so that t_INTis always ≥ t_MRAZas shown

in Figure 16 (see Figure 13 and Table 7, page 18).

With a longer t_INT, the m/r/az cycle has enough time

to finish before the next integration begins and

continuous integration of the input signal is possible.

For the special case of the very first integration when

changing to the cont mode, t_INTcan be < t_MRAZ. This

is allowed because there is no simultaneous m/r/az

cycle on the side B during state 3—therefore, there

is no need to wait for it to finish before ending the

integration on side A.

Changing from cont to ncont mode occurs whenever

t_INT< t_MRAZ. Figure 15 shows an example of this

transition. In this figure, cont mode is entered when

the integration on side A is completed before the

m/r/az cycle on side B is complete. The DDC232

completes the measurement on sides B and A during

states 8 and 7 with the input signal shorted to

ground. Ncont integration begins with state 6.

Changing from ncont to cont mode occurs when t_INT

CONV

State

5

4

5

8

7

6

5

Continuous

Integrate B

Non−Continuous

Integration

Status

Integrate A

Int A

Int B Int A

m/r/az

Status

m/r/az

B

m/r/az

A

m/r/az

B

m/r/az

A

m/r/az B

mbsy

Figure 15. Changing from Continuous Mode to Non-Continuous Mode

CONV

State

3

4

1

2

3

4

Non−Continuous

Continuous

Integrate A

Integration

Int A

Int B

Integrate B

Status

m/r/az

Status

m/r/az

A

m/r/az

B

m/r/az A

mbsy

Figure 16. Changing from Non-Continuous Mode to Continuous Mode

19

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Table 8. Ideal Output Code⁽¹⁾vs Input Signal

DATA FORMAT

INPUT

SIGNAL

IDEAL OUTPUT CODE

FORMAT = 1

IDEAL OUTPUT CODE

FORMAT = 0

The serial output data is provided in an offset binary

code as shown in Table 8. The Format bit in the

configuration register selects how many bits are used

in the output word. When Format = 1, 20 bits are

used. When Format = 0, the lower 4 bits are

truncated so that only 16 bits are used. Note that the

LSB size is 16 times bigger when Format = 0. An

offset is included in the output to allow slightly

negative inputs (for example, from board leakages)

from clipping the reading. This offset is

approximately 0.4% of the positive full-scale.

≥ 100% FS

0.001531% FS

0.001436% FS

0.000191% FS

0.000096% FS

0% FS

1111 1111 1111 1111 1111

0000 0001 0000 0001 0000

0000 0001 0000 0000 1111

0000 0001 0000 0000 0010

0000 0001 0000 0000 0001

0000 0001 0000 0000 0000

0000 0000 0000 0000 0000

1111 1111 1111 1111

0000 0001 0000 0001

0000 0001 0000 0000

0000 0000 0000 0000

–0.3955% FS

(1) Excludes the effects of noise, INL, offset, and gain errors.

DATA RETRIEVAL

Setting the Format bit = 0 (16-bit output word) will

reduce the time needed to retrieve data by 20%

since there are fewer bits to shift out. This can be

useful in multichannel systems requiring only 16 bits

of resolution.

In both the continuous and non-continuous modes of

operation, the data from the last conversion is

available for retrieval on the falling edge of DVALID

(see Figure 17 and Table 9). Data is shifted out on

the falling edge of the data clock, DCLK.

Make sure not to retrieve data around changes in

CONV because this can introduce noise. Stop

activity on DCLK at least 10µs before or after a

CONV transition.

CLK

t_PDCDV

DVALID

t_PDDCDV

t_HDDODV

DCLK

t_HDDODC

Input

t_PDDCDO

Input

31

MSB

Input 32

MSB

Input 5 Input 4

LSB MSB

Input 2 Input 1

LSB MSB

Input 1

LSB

Input 32

MSB

DOUT

32

LSB

Figure 17. Digital Interface Timing Diagram for Data Retrieval From a Single DDC232

Table 9. Timing for DDC232 Data Retrieval

SYMBOL DESCRIPTION

MIN

10

5

TYP

MAX

UNITS

ns

t_PDCDV

t_PDDCDV

t_HDDODV

t_HDDODC

Propagation Delay from Falling Edge of CLK to DVALID Low

Propagation Delay from Falling Edge of DCLK to DVALID High

Hold Time that DOUT is Valid Before the Falling Edge of DVALID

Hold Time that DOUT is Valid After Falling Edge of DCLK

Propagation Delay from Falling Edge of DCLK to Valid DOUT

ns

400

ns

4

ns

(1)

t_PDDCDO

25

ns

(1) With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF.

20

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

Figure 19 shows the timing diagram when the DIN

input is used to daisy-chain several devices.

Table 10 gives the timing specification for data

retrieval using DIN.

Cascading Multiple Converters

Multiple DDC232 units can be connected in serial

configuration; see Figure 18.

DOUT can be used with DIN to daisy-chain multiple

DDC232 devices together to minimize wiring. In this

mode of operation, the serial data output is shifted

through multiple DDC232s; see Figure 18.

Data Clock

Data

Retrieval

Output

DOUT

DDC232

DOUT

DDC232

DOUT

DDC232

DOUT

DDC232

DIN

Sensor

Figure 18. Daisy-Chained DDC232s

CLK

DVALID

DCLK

DIN

t_STDIDC

t_HDDIDC

Input

128

MSB

Input

128

LSB

Input

127

MSB

Input

128

MSB

Input 3 Input 2

LSB MSB

Input 2 Input 1

LSB MSB

Input 1

LSB

DOUT

Figure 19. Timing Diagram When Using DDC232 DIN Function; See Figure 18

Table 10. Timing for DDC232 Data Retrieval Using DIN

SYMBOL DESCRIPTION

t_STDIDCSet-Up Time from DIN to Falling Edge of DCLK

t_HDDIDCHold Time for DIN After Falling Edge of DCLK

MIN

10

TYP

MAX

UNITS

ns

10

21

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

ǒ

Ǔ

t_INT* t_CMDR) t_SDCV

RETRIEVAL BEFORE CONV TOGGLES

(CONTINUOUS MODE)

(

)

20 32 t_DCLK

(1)

NOTE: (16 × 32)τ_DCLKis used for FORMAT = 0,

where t_DCLKis the period of the data clock. For

example, if t_INT= 1000µs and DCLK = 10MHz, the

maximum number of DDC232s with FORMAT = 1 is

shown in Equation 2:

Data retrieval before CONV toggles is the most

straightforward method. Data retrieval begins soon

after DVALID goes low and finishes before CONV

toggles, as shown in Figure 20. For best

performance, data retrieval must stop t_SDCVbefore

CONV toggles. This method is most appropriate for

longer integration times. The maximum time

available for readback is t_INT– t_CMDR– t_SDCV. For

DCLK = 10MHz and CLK = 5MHz, the maximum

number of DDC232s that can be daisy-chained

together (FORMAT = 1) is calculated by Equation 1:

1000ms * 286.8ms

+ 11.14 ³ 11 DDC232

(

)( )

640 100ns

(2)

(or 13 for FORMAT = 0)

CONV

t_INT

DVALID

DCLK

t_CMDR

t_SDCV

…

DOUT

Side B

Data

Side A

Data

Figure 20. Readback Before CONV Toggles

Table 11. Timing for Readback

CLK = 5MHz, Clk_4x = 0

SYMBOL DESCRIPTION

MIN

TYP

MAX

UNITS

t_SDCV

Data Retrieval Shutdown Before or After Edge of CONV

10

µs

22

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

266ms

RETRIEVAL AFTER CONV TOGGLES

(CONTINUOUS MODE)

(

)

20 32 t_DCLK

(3)

For shorter integration times, more time is available if

data retrieval begins after CONV toggles and ends

before the new data is ready. Data retrieval must

wait t_SDCVafter CONV toggles before beginning. See

Figure 21 for an example of this. The maximum time

available for retrieval is t_CMDR– (t_SDCV+ t_HDDODV),

NOTE: (16 × 32)τ_DCLKis for FORMAT = 0.

For DCLK = 10MHz, the maximum number of

DDC232s is 4 (or 5 for FORMAT = 0).

regardless of t_INT

.

The maximum number of

DDC232s that can be daisy-chained together with

FORMAT = 1 is calculated by Equation 3:

t_INT

CONV

DVALID

t_CMDR

t_SDCV

t_HDDODV

…

DCLK

…

DOUT

Side A

Data

Side B

Data

Side A

Data

Figure 21. Readback After CONV Toggles

23

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

ǒ

Ǔ

RETRIEVAL BEFORE AND AFTER CONV

t_INT* t_SDCV) t_SDCV) t_HDDODV

TOGGLES (CONTINUOUS MODE)

(

)

20 32 t_DCLK

NOTE: (16 × 32)τ_DCLKis used for FORMAT = 0.

For t_INT= 400µs and DCLK = 10MHz, the maximum

number

FORMAT = 0).

(4)

For the absolute maximum time for data retrieval,

data can be retrieved before and after CONV

toggles. Nearly all of t_INTis available for data

retrieval. Figure 22 illustrates how this is done by

combining the two previous methods. Pause the

retrieval during CONV toggling to prevent digital

noise, as discussed previously, and finish before the

next data is ready. The maximum number of

DDC232s that can be daisy-chained together with

FORMAT = 1 is:

of

DDC232s

is

5

(or

7

for

CONV

DVALID

DCLK

t_INT

t_SDCV

t_HDDODV

t_SDCV

…

DOUT

Side B

Data

Side A

Data

Figure 22. Readback Before and After CONV Toggles

24

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

RETRIEVAL: NON-CONTINUOUS MODE

The time available is t_NCDR2– (t_INT– t_NCDR1). Data

from the second integration must be retrieved before

the next round of integration begins. This time is

highly dependent on the pattern used to generate

CONV. As with the continuous mode, data retrieval

must halt before and after CONV toggles (t_SDCV) and

be completed before new data is ready (t_HDDODV).

Retrieving in non-continuous mode is slightly

different as compared with the continuous mode. As

illustrated in Figure 23, DVALID goes low in time

t_NCDR1after the first integration completes. If t_INTis

shorter than this time, all of t_NCDR2is available to

retrieve data before the other side data is ready. For

t_INT> t_NCDR1, the first integration data is ready before

the second integration completes. Data retrieval

must be delayed until the second integration

completes, leaving less time available for retrieval.

t_INT

CONV

t_INT

DVALID

t_{NCDR 1}

t_{NC DR2}

…

DCLK

DOUT

…

Side A

Data

Side B

Data

Figure 23. Readback in Non-Continuous Mode

25

Submit Documentation Feedback

DDC232

www.ti.com

SBAS331C–AUGUST 2004–REVISED SEPTEMBER 2006

POWER-UP SEQUENCING

LAYOUT

Prior to power-up, all digital and analog inputs must

be low. At the time of power-up, all of these signals

should remain low until the power supplies have

stabilized, as shown in Figure 24. At this time, begin

supplying the master clock signal to the CLK pin.

Wait for time t_POR, then give a RESET pulse. After

releasing RESET, the configuration register must be

programmed. Table 12 shows the timing for the

power-up sequence.

POWER SUPPLIES AND GROUNDING

Both AVDD and DVDD should be as quiet as

possible. It is particularly important to eliminate noise

from AVDD that is non-synchronous with the

DDC232 operation. Figure 25 illustrates how to

supply power to the DDC232. Each supply of the

DDC232 should be bypassed with 10µF solid

tantalum capacitors. It is recommended that both the

analog and digital grounds (AGND and DGND) be

connected to a single ground plane on the printed

circuit board (PCB).

t_POR

VA

Power Supplies

t_RST

AVDD

AGND

DGND

µ

10

F

RESET

DDC232

VD

DVDD

µ

10

F

Figure 24. DDC232 Timing Diagram at Power-Up

Table 12. Timing for DDC232 Power-Up Sequence

Figure 25. Power-Supply Connections

SYMBOL DESCRIPTION

MIN TYP MAX UNITS

Wait After Power-Up

Until Reset

t_POR

t_RST

250

1

ms

µs

Shielding Analog Signal Paths

Reset Low Width

As with any precision circuit, careful PCB layout will

ensure the best performance. It is essential to make

short, direct interconnections and avoid stray wiring

capacitance—particularly at the analog input pins

and QGND. These analog input pins are

high-impedance and extremely sensitive to

extraneous noise. The QGND pin should be treated

as a sensitive analog signal and connected directly

to the supply ground with proper shielding. Leakage

currents between the PCB traces can exceed the

input bias current of the DDC232 if shielding is not

implemented. Digital signals should be kept as far as

possible from the analog input signals on the PCB.

26

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

BGA

Drawing

DDC232CGXGR

DDC232CGXGT

ACTIVE

GXG

64

1000

250

TBD

SN/PB

Level-3-240C-168 HR

GXG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DDC232CGXGR
厂家：	TEXAS INSTRUMENTS
描述：	32-Channel, Current-Input Analog-to-Digital Converter 转换器
文件：	总29页 (文件大小：384K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DDC232CGXGR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E