DLP2010NIRAFQJ [TI]
DLP® 0.2 WVGA NIR DMD | FQJ | 40 | 0 to 70;
| 型号： | DLP2010NIRAFQJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® 0.2 WVGA NIR DMD | FQJ | 40 | 0 to 70 商用集成电路 |
| 文件： | 总41页 (文件大小：1558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP2010NIR
DLPS119B – DECEMBER 2018 – REVISED MAY 2022
DLP2010NIR (.2 WVGA Near-Infrared DMD)
1 Features
2 Applications
•
0.2-inch (5.29-mm) Diagonal Micromirror Array
– 854 × 480 Array of Aluminum Micrometer-Sized
Mirrors, in an Orthogonal Layout
– 5.4-µm Micromirror Pitch
– ±17° Micromirror Tilt (Relative to Flat Surface)
– Side Illumination for Optimal Efficiency and
Optical Engine Size
Highly Efficient Steering of NIR light
– Window Transmission Efficiency 96% Nominal
(700 to 2000 nm, Single Pass Through Two
Window Surfaces)
•
Spectrometers (Chemical Analysis):
– Portable Process Analyzers
– Portable Equipment
Compressive Sensing (Single Pixel NIR Cameras)
3D Biometrics
Machine Vision
Infrared Scene Projection
Microscopes
•
•
•
•
•
•
•
•
•
Laser Marking
Optical Choppers
Optical Networking
– Window Transmission Efficiency 90% Nominal
(2000 to 2500 nm, Single Pass Through Two
Window Surfaces)
– Polarization Independent Aluminum
Micromirrors
Dedicated DLPC150/DLPC3470 Controllers for
Reliable Operation
– Binary Pattern Rates up to 2880 Hz
– Pattern Sequence Mode for Control over Each
Micromirror in Array
Dedicated Power Management Integrated Circuit
(PMIC) DLPA2000 or DLPA2005 for Reliable
Operation
15.9-mm × 5.3-mm × 4-mm Body Size for Portable
Instruments
3 Description
The DLP2010NIR digital micromirror device (DMD)
acts as a spatial light modulator (SLM) to steer near-
infrared (NIR) light and create patterns with speed,
precision, and efficiency. Featuring high resolution
in a compact form factor, the DLP2010NIR DMD
is often combined with a grating single element
detector to replace expensive InGaAs linear array-
based detector designs, leading to high performance,
cost-effective portable NIR Spectroscopy solutions.
The DLP2010NIR DMD enables wavelength control
and programmable spectrum and is well suited for
low power mobile applications such as 3D biometrics,
facial recognition, skin analysis, material identification
and chemical sensing. ™
•
•
•
PART NUMBER(1)
PACKAGE
FQJ (40)
BODY SIZE (NOM)
DLP2010NIR
15.9-mm × 5.3- mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
D_P(0)
D_N(0)
DLPC150
Display
Controller
VOFFSET
VBIAS
D_P(1)
D_N(1)
DLPA2000
VRESET
DLPA2005
600-MHz
SubLVDS
DDR
(PMIC and LED
Driver)
D_P(2)
D_N(2)
DLP2010 DMD
or
DLP2010NIR DMD
Interface
D_P(3)
D_N(3)
Digital
Micromirror
Device
DCLK_P
DCLK_N
VDDI
VDD
VSS
LS_WDATA
LS_CLK
120-MHz
SDR
Interface
LS_RDATA
DMD_DEN_ARSTZ
(System signal routing omitted for clarity)
Figure 3-1. Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP2010NIR
DLPS119B – DECEMBER 2018 – REVISED MAY 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 Storage Conditions..................................................... 6
6.3 ESD Ratings............................................................... 7
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information....................................................9
6.6 Electrical Characteristics.............................................9
6.7 Timing Requirements................................................10
6.8 Switching Characteristics .........................................15
6.9 System Mounting Interface Loads............................ 15
6.10 Physical Characteristics of the Micromirror Array...17
6.11 Micromirror Array Optical Characteristics............... 18
6.12 Window Characteristics.......................................... 19
6.13 Chipset Component Usage Specification............... 19
6.14 Typical Characteristics............................................20
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................22
7.5 Optical Interface and System Image Quality
Considerations............................................................ 22
7.6 Micromirror Array Temperature Calculation.............. 23
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................29
9.1 Power Supply Power-Up Procedure ........................ 29
9.2 Power Supply Power-Down Procedure ....................29
9.3 Power Supply Sequencing Requirements................ 30
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................34
11.1 Device Support........................................................34
11.2 Related Links.......................................................... 34
11.3 Receiving Notification of Documentation Updates..34
11.4 Support Resources................................................. 35
11.5 Trademarks............................................................. 35
11.6 Electrostatic Discharge Caution..............................35
11.7 Glossary..................................................................35
12 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
•
•
•
Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6
Updated Micromirror Array Optical Characteristics ......................................................................................... 18
Added Third-Party Products Disclaimer ...........................................................................................................34
Changes from Revision * (December 2018) to Revision A (November 2021)
Page
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................7
•
•
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5 Pin Configuration and Functions
Figure 5-1. FQJ Package. 40-Pin CLGA. Bottom View.
PIN
NAME
DATA INPUTS, SUBLVDS INTERFACE
PACKAGE NET TRACE
TYPE
SIGNAL
DATA RATE
DESCRIPTION
LENGTH(2) (mm)
NO.
D_N(0)
D_P(0)
D_N(1)
D_P(1)
D_N(2)
D_P(2)
D_N(3)
D_P(3)
DCLK_N
DCLK_P
G4
G3
G8
G7
H5
H6
H1
H2
H9
H10
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Input data pair 0, negative
Input data pair 0, positive
Input data pair 1, negative
Input data pair 1, positive
Input data pair 2, negative
Input data pair 2, positive
Input data pair 3, negative
Input data pair 3, positive
Clock, negative
7.03
7.03
7.03
7.03
7.02
7.02
7.00
7.00
7.03
7.03
Clock, positive
CONTROL INPUTS, LPSDR INTERFACE
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PIN
PACKAGE NET TRACE
LENGTH(2) (mm)
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
NO.
Active low asynchronous DMD reset
signal. A low signal places the DMD in
reset. A high signal releases the DMD from
reset and places it in active mode.
DMD_DEN_ARSTZ
G12
I
LPSDR (1)
5.72
LS_CLK
G19
G18
G11
I
I
LPSDR
LPSDR
LPSDR
Single
Single
Single
Clock for low-speed interface
3.54
3.54
8.11
LS_WDATA
LS_RDATA
POWER
Write data for low-speed interface
Read data for low-speed interface
O
Supply voltage for micromirror positive bias
level
(3)
VBIAS
H17 Power
H13 Power
H18 Power
Supply voltage for high voltage CMOS
(HVCMOS) core logic.
Includes: Supply voltage for stepped high
level at micromirror address electrodes
and supply voltage for offset level at
micromirrors.
(3)
VOFFSET
Supply voltage for micromirror negative
reset level
(3)
VRESET
(3)
VDD
G20 Power
H14 Power
H15 Power
H16 Power
H19 Power
H20 Power
VDD
VDD
VDD
VDD
VDD
Supply voltage for low voltage CMOS
(LVCMOS) core logic. Includes supply
voltage for LPSDR inputs and supply
voltage for normal high level at micromirror
address electrodes.
(3)
VDDI
G1
G2
G5
G6
G9
Power
Power
Power
Power
Power
VDDI
VDDI
VDDI
Supply voltage for SubLVDS receivers
(3)
VSS
VSS
G10 Power
G13 Power
G14 Power
G15 Power
G16 Power
G17 Power
VSS
VSS
VSS
VSS
VSS
Ground. Common return for all power.
VSS
H3
H4
H7
H8
Power
Power
Power
Power
VSS
VSS
VSS
VSS
H11 Power
H12 Power
VSS
RESERVED
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PIN
NAME
PACKAGE NET TRACE
TYPE
SIGNAL
DATA RATE
DESCRIPTION
LENGTH(2) (mm)
NO.
A2,
A3,
A4,
A5, A6
A7,
A8,
A9,
A10,
A11,
A12,
A13,
A14,
A15,
A16,
A17,
A18,
A19
Reserved pins. For proper device
operation, leave these pins unconnected.
No connect
B2,
B3,
B17,
B18
Reserved pins. For proper device
operation, leave these pins unconnected.
No connect
No connect
No connect
No connect
C2,
C3,
C17,
C18
Reserved pins. For proper device
operation, leave these pins unconnected.
D2,
D3,
D17,
D18
Reserved pins. For proper device
operation, leave these pins unconnected.
E2,
E3,
E17,
E18
Reserved pins. For proper device
operation, leave these pins unconnected.
F1,
F2,
F3,
F4,
F5,
F6,
F7,
F8,
F9,
Reserved pins. For proper device
No connect
F10,
F11,
F12,
F13,
F14,
F15,
F16,
F17,
F18,
F19
operation, leave these pins unconnected.
(1) Low speed interface is LPSDR and adheres to the electrical characteristics and AC/DC operating conditions table in JEDEC Standard
No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQJ ceramic package is 9.8.
Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET
.
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6 Specifications
6.1 Absolute Maximum Ratings
(see (1)
)
MIN
–0.5
–0.5
–0.5
MAX
2.3
UNIT
Supply voltage for LVCMOS core logic and LPSDR
low speed interface(2)
VDD
V
V
V
VDDI
Supply voltage for SubLVDS receivers(2)
2.3
Supply voltage for HVCMOS and micromirror
electrode(2) (3)
VOFFSET
10.6
Supply voltage for micromirror electrode bias circuits
VBIAS
–0.5
–15
19
V
V
Supply voltage
(2)
Supply voltage for micromirror electrode reset circuit
VRESET
0.3
(2)
|VDDI–VDD
|
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
0.3
11
V
V
V
|VBIAS–VOFFSET
|
|VBIAS–VRESET
|
34
Input voltage for other
inputs LPSDR(2)
–0.5
–0.5
VDD + 0.5
VDDI + 0.5
V
V
Input voltage
Input pins
Input voltage for other
inputs SubLVDS(2) (7)
|VID|
IID
SubLVDS input differential voltage (absolute value)(7)
SubLVDS input differential current
810
8.1
130
620
90
mV
mA
MHz
MHz
°C
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK
Clock frequency for high speed interface DCLK
Temperature – operational (8)
Clock
frequency
–20
–40
TARRAY and TWINDOW
Temperature – non-operational (8)
90
°C
Environmental
TDP
|TDELTA
Dew point (operating and non-operating)
81
°C
|
Absolute Temperature delta between any point on the
window edge and the ceramic test point TP1 (9)
30
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET
.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated by the Section 7.6), or of any point along the Window Edge as defined
in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/>. The locations of thermal
test points TP2 and TP3 in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/> are
intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be
at a higher temperature, that test point should be used.
(9) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure
19. The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
UNIT
TDMD
DMD storage temperature
–40
85
°C
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MIN
MAX
24
UNIT
°C
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature, (non-condensing)(1)
Elevated dew point temperature range, (non-condensing)(2)
Cumulative time in elevated dew point temperature range
28
36
°C
6
Months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
±1000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE(3)
VDD
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
1.65
1.65
9.5
1.8
1.8
10
1.95
1.95
10.5
V
V
V
VDDI
Supply voltage for SubLVDS receivers
VOFFSET
Supply voltage for HVCMOS and micromirror
electrode(4)
VBIAS
Supply voltage for mirror electrode
17.5
18
18.5
–13.5
0.3
V
V
V
V
V
VRESET
|VDDI–VDD
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
Supply voltage delta (absolute value)(7)
–14.5
–14
|
|VBIAS–VOFFSET
|
10.5
33
|VBIAS–VRESET
|
OUTPUT TERMINALS
IOH
High-level output current at Voh = 0.8 × VDD
Low-level output current at Vol = 0.2 × VDD
–30
30
mA
mA
IOL
CLOCK FREQUENCY
ƒclock
ƒclock
Clock frequency for low speed interface LS_CLK(8)
Clock frequency for high speed interface DCLK(9)
Duty cycle distortion DCLK
108
300
120
600
MHz
MHz
44%
56%
SUBLVDS INTERFACE(9)
|VID|
SubLVDS input differential voltage (absolute value)
Figure 6-8, Figure 6-9
150
250
900
350
mV
VCM
Common mode voltage Figure 6-8, Figure 6-9
SubLVDS voltage Figure 6-8, Figure 6-9
Line differential impedance (PWB/trace)
Internal differential termination resistance Figure 6-10
100-Ω differential PCB trace
700
575
90
1100
1225
110
mV
mV
Ω
VSUBLVDS
ZLINE
ZIN
100
100
80
120
Ω
6.35
152.4
mm
LPSDR INTERFACE(10)
ZLINE
Line differential impedance (PWB/trace)
61.2
68
74.8
Ω
ENVIRONMENTAL
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UNIT
MIN
NOM
MAX
TARRAY
Array temperature – long-term operational(11) (12) (13)
0
40 to 70(11)
Array temperature – short-term operational, 25 hr
max(13) (14)
–20
-10
70
-10
0
°C
Array temperature – short-term operational, 500hr max
(13) (14)
Array temperature – short-term operational, 500hr max
75
90
15
(13) (14)
TWINDOW
Window temperature – operational(15) (17)
°C
°C
|TDELTA
|
Absolute temperature difference between any point on
the window edge and the ceramic test point TP1(16)
CTELR
Cumulative time in elevated dew point temperature
range
6
Months
ILLUV
ILLVIS
Illumination, wavelength < 420 nm
0.68 mW/cm2
Thermally
limited
Illumination wavelengths between 420 nm and 700 nm
ILLNIR
ILLIR
ILLθ
Illumination, wavelength 700 - 2500 nm
Illumination, wavelength > 2500 nm
Illumination marginal ray angle(17)
2000 mW/cm2
10 mW/cm2
55
deg
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined
by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in Section 6.7.
(10) Refer to the LPSDR timing requirements in Section 6.7.
(11) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.
(12) Long-term is defined as the usable life of the device.
(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 7-1 and the package thermal resistance using Section 7.6.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and
TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on
the window edge to be at a higher temperature, a test point should be added to that location.
(16) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure
7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(17) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
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80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45
100/0 95/5
D001
Micromirror Landed Duty Cycle
Figure 6-1. Maximum Recommended Array Temperature – Derating Curve
6.5 Thermal Information
DLP2010NIR
FQJ (CLGA)
40 PINS
THERMAL METRIC (1)
UNIT
MIN
TYP
MAX
7.9 °C/W
Thermal resistance Active area to test point TP1(1)
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on
the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed
by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy
falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the
device.
Over operating free-air temperature range (unless otherwise noted)(10)
6.6 Electrical Characteristics
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
MAX UNIT
CURRENT
VDD = 1.95 V
34.7
mA
IDD
Supply current: VDD(3) (5)
Supply current: VDDI(3) (5)
Supply current: VOFFSET(4) (6)
Supply current: VBIAS(4) (6)
Supply current: VRESET(6)
VDD = 1.8 V
27.5
6.6
0.9
0.2
1.2
VDDI = 1.95 V
VDD = 1.8 V
9.4
mA
IDDI
VOFFSET = 10.5 V
VOFFSET = 10 V
VBIAS = 18.5 V
VBIAS = 18 V
1.7
mA
IOFFSET
0.4
mA
IBIAS
VRESET = –14.5 V
VRESET = –14 V
2
IRESET
mA
POWER(1)
PDD
VDD = 1.95 V
VDD = 1.8 V
67.7
mW
Supply power dissipation: VDD(3) (5)
Supply power dissipation: VDDI(3) (5)
49.5
11.9
9
VDDI = 1.95 V
VDD = 1.8 V
18.3
mW
PDDI
VOFFSET = 10.5 V
VOFFSET = 10 V
17.9
mW
Supply power dissipation:
VOFFSET(4) (6)
POFFSET
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MAX UNIT
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6.6 Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS(2)
MIN
TYP
VBIAS = 18.5 V
7.4
PBIAS
Supply power dissipation: VBIAS(4) (6)
mW
VBIAS = 18 V
3.6
VRESET = –14.5 V
VRESET = –14 V
29
PRESET
Supply power dissipation: VRESET(6)
Supply power dissipation: Total
mW
16.8
90.8
PTOTAL
LPSDR INPUT(7)
140.3
mW
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
∆VT
DC input high voltage(9)
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
VDD + 0.3
0.2 × VDD
0.4 × VDD
V
V
DC input low voltage(9)
AC input high voltage(9)
AC input low voltage(9)
0.8 × VDD
–0.3
V
V
Hysteresis ( VT+ – VT–
)
Figure 6-10
0.1 × VDD
–100
V
IIL
Low–level input current
High–level input current
VDD = 1.95 V; VI = 0 V
VDD = 1.95 V; VI = 1.95 V
nA
nA
IIH
100
LPSDR OUTPUT(8)
VOH
VOL
DC output high voltage
DC output low voltage
IOH = –2 mA
IOL = 2 mA
0.8 × VDD
V
V
0.2 × VDD
CAPACITANCE
Input capacitance LPSDR
ƒ = 1 MHz
10
20
pF
pF
pF
pF
CIN
Input capacitance SubLVDS
Output capacitance
ƒ = 1 MHz
COUT
ƒ = 1 MHz
10
CRESET
Reset group capacitance
ƒ = 1 MHz; (480 × 108) micromirrors
95
113
(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(5) Supply power dissipation based on non–compressed commands and data.
(6) Supply power dissipation based on 3 global resets in 200 µs.
(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(8) LPSDR specification is for pin LS_RDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) Device electrical characteristics are over Section 6.4 unless otherwise noted.
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
6.7 Timing Requirements
MIN
NOM
MAX UNIT
LPSDR
tR
Rise slew rate(1)
Fall slew rate(1)
Rise slew rate(2)
Fall slew rate(2)
Cycle time LS_CLK,
(30% to 80%) × VDD, Figure 6-3
(70% to 20%) × VDD, Figure 6-3
(20% to 80%) × VDD, Figure 6-3
(80% to 20%) × VDD, Figure 6-3
Figure 6-2
1
1
3
3
V/ns
V/ns
V/ns
V/ns
ns
tV
tR
0.25
0.25
7.7
3.1
tF
tC
8.3
tW(H)
Pulse duration LS_CLK
high
ns
50% to 50% reference points,Figure 6-2
50% to 50% reference points, Figure 6-2
tW(L)
Pulse duration LS_CLK
low
3.1
ns
tSU
Setup time
LS_WDATA valid before LS_CLK ↑, Figure 6-2
LS_WDATA valid after LS_CLK ↑, Figure 6-2
Setup time + Hold time, Figure 6-2
1.5
1.5
3
ns
ns
ns
t H
Hold time
tWINDOW
Window time(1) (4)
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6.7 Timing Requirements (continued)
MIN
NOM
MAX UNIT
tDERATING
For each 0.25 V/ns reduction in slew rate below
1 V/ns, Figure 6-5
0.35
ns
Window time derating(1) (4)
SubLVDS
tR
Rise slew rate
20% to 80% reference points, Figure 6-4
80% to 20% reference points, Figure 6-4
Figure 6-6
0.7
0.7
1
1
V/ns
V/ns
ns
tF
Fall slew rate
tC
Cycle time LS_CLK,
1.61
0.71
0.71
1.67
tW(H)
tW(L)
Pulse duration DCLK high 50% to 50% reference points, Figure 6-6
Pulse duration DCLK low 50% to 50% reference points, Figure 6-6
ns
ns
D(0:3) valid before
Setup time
tSU
DCLK ↑ or DCLK ↓, Figure 6-6
D(0:3) valid after
Hold time
t H
DCLK ↑ or DCLK ↓, Figure 6-6
tWINDOW
Window time
Setup time + Hold time, Figure 6-6,Figure 6-7
3
ns
ns
tLVDS-
Power-up receiver(3)
2000
ENABLE+REFGEN
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.
(3) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
(4) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
t
c
t
t
w(L)
w(H)
LS_CLK
50%
50%
50%
t
h
t
su
LS_WDATA
50%
50%
t
window
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Figure 6-2. LPSDR Switching Parameters
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LS_CLK, LS_WDATA
1.0 * VDD
DMD_DEN_ARSTZ
1.0 * VDD
0.8 * VDD
VIH(AC)
VIH(DC)
0.8 * VDD
0.7 * VDD
VIL(DC)
VIL(AC)
0.3 * VDD
0.2 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
Figure 6-3. LPSDR Input Rise and Fall Slew Rate
VDCLK_P , VDCLK_N
VD_P(0:3) , VD_N(0:3)
1.0 * V
0.8 * V
ID
ID
V
CM
0.2 * V
0.0 * V
ID
ID
tr
tf
Figure 6-4. SubLVDS Input Rise and Fall Slew Rate
VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tH
tSU
VIH MIN
Midpoint
VIL MAX
LS_WDATA
tWINDOW
Figure 6-5. Window Time Derating Concept
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t
c
t
t
w(H)
w(L)
DCLK_P
DCLK_N
50%
50%
50%
t
h
t
su
D_P(0:3)
D_N(0:3)
50%
50%
t
window
Figure 6-6. SubLVDS Switching Parameters
High Speed Training Scan Window
t
c
DCLK_P
DCLK_N
¼ t
c
¼ t
c
D_P(0:3)
D_N(0:3)
Note: Refer to High-Speed Interface for details.
Figure 6-7. High-Speed Training Scan Window
(V + V ) / 2
IP IN
DCLK_P , D_P(0:3)
SubLVDS
Receiver
V
ID
DCLK_N , D_N(0:3)
V
IP
V
CM
V
IN
Figure 6-8. SubLVDS Voltage Parameters
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1.225V
V
= V
+ | 1/2 * V
|
ID max
SubLVDS max
CM max
V
CM
V
ID
V
= V
– | 1/2 * V
|
SubLVDS min
CM min
ID max
0.575V
Figure 6-9. SubLVDS Waveform Parameters
DCLK_P , D_P(0:3)
ESD
Internal
Termination
SubLVDS
Receiver
DCLK_N , D_N(0:3)
ESD
Figure 6-10. SubLVDS Equivalent Input Circuit
Not to Scale
V
IH
V
T+
Δ V
T
V
T-
V
LS_CLK
IL
LS_WDATA
Figure 6-11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
Figure 6-12. LPSDR Read Out
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Data Sheet Timing Reference Point
Device Pin
Tester Channel
Output Under Test
C
L
See Timing for more information.
Figure 6-13. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
Output propagation, Clock to Q, rising
edge of LS_CLK input to LS_RDATA
output. Figure 6-12
CL = 45 pF
tPD
15
Slew rate, LS_RDATA
0.5
V/ns
Output duty cycle distortion, LS_RDATA
40%
60%
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
6.9 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Maximum system mounting interface load to be applied to the:
45
N
N
•
•
Connector area (see Figure 6-14)
100
DMD mounting area uniformly distributed over 4 areas (see Figure 6-14)
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5ꢀšµu Z![ !Œꢁꢀ
(3 places)
5ꢀšµu Z9[ !Œꢁꢀ
(1 place)
DMD Mounting Area
(4 ‰oꢀꢂꢁ• }‰‰}•]šꢁ 5ꢀšµu• Z![ ꢀvꢃ Z9[)
Connector Area
Figure 6-14. System Interface Loads
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6.10 Physical Characteristics of the Micromirror Array
VALUE
854
UNIT
micromirrors
micromirrors
µm
Number of active columns
Number of active rows
Micromirror (pixel) pitch
See Figure 6-15
See Figure 6-15
See Figure 6-16
480
ε
5.4
Micromirror pitch × number of active columns; see Figure
6-15
Micromirror active array width
4.6116
mm
Micromirror active array height
Micromirror active border
Micromirror pitch × number of active rows; see Figure 6-15
Pond of micromirror (POM)(1)
2.592
20
mm
micromirrors/side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
Not To Scale
Width
Mirror 479
Mirror 478
Mirror 477
Mirror 476
Illumination
DMD Active Mirror Array
854 Mirrors * 480 Mirrors
Mirror 3
Mirror 2
Mirror 1
Mirror 0
Figure 6-15. Micromirror Array Physical Characteristics
ε
ε
ε
ε
Figure 6-16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Micromirror tilt angle
DMD landed state(1)
17
degrees
Micromirror tilt angle tolerance(1)
–1.4
1.4
degrees
degrees
(2) (4) (5) (6)
Landed ON state
180
270
1.5
Micromirror tilt direction(3) (7)
Landed OFF state
Typical Performance
Typical Performance
Gray 10 Screen (10)
Gray 10 Screen (10)
Micromirror crossover time
Micromirror switching time
Bright pixel(s) in active area (9)
Bright pixel(s) in the POM (11)
4
6
0
1
4
0
0
μs
Image
Dark pixel(s) in the active area (12) White Screen
micromirrors
performance(8)
Adjacent pixel(s) (13)
Unstable pixel(s) in active area (14) Any Screen
Any Screen
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
(4) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(5) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(6) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(9) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(10) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(11) POM definition: Rectangular border of off-state mirrors surrounding the active area
(12) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(13) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(14) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image
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(0,479)
(853,479)
Incident
Illumination
Light Path
Tilted Axis of
Pixel Rotation
On-State
Landed Edge
Off-State
Landed Edge
(0,0)
(853,0)
Off-State
Light Path
Figure 6-17. Landed Pixel Orientation and Tilt
6.12 Window Characteristics
PARAMETER(3)
MIN
NOM
Corning Eagle XG
1.5119
MAX UNIT
Window material designation
Window refractive index
Window aperture(1)
at wavelength 546.1 nm
See (1)
See (2)
Illumination overfill(2)
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
700 to 2000 nm. at 0° angle of incidence.
92
85
96
90
%
%
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
2000 to 2500 nm. at 0° angle of
incidence.
(1) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(2) The active area of the DLP2010NIR device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using
the DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the
average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of
overfill light on the outside of the active array may cause system performance degradation.
(3) See Optical Interface and System Image Quality Considerations for more information.
6.13 Chipset Component Usage Specification
The DLP2010NIR is a component of one or more DLP chipsets. Reliable function and operation of the
DLP2010NIR requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
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Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
6.13.1 Software Requirements
Note
The DLP2010NIR DMD has mandatory software requirements. Refer to Software Requirements for
TI DLP™Pico™ TRP Digital Micromirror Devices application report for additional information. Failure to
use the specified software will result in failure at power up.
6.14 Typical Characteristics
100
95
90
85
80
75
70
65
60
Nominal
Minimum
700 900 1100 1300 1500 1700 1900 2100 2300 2500
Wavelength (nm)
D001
Figure 6-18. DLP2010NIR DMD Window Transmittance
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7 Detailed Description
7.1 Overview
The DLP2010NIR is a 0.2 inch diagonal spatial light modulator designed for near-infrared applications. Pixel
array size is 854 columns by 480 rows in a square grid pixel arrangement. The electrical interface is Sub Low
Voltage Differential Signaling (SubLVDS) data.
DLP2010NIR is one device in a chipset, which includes the DLP2010NIR DMD, the DLPC150/3470 controller
and the DLPA200X (DLPA2000 or DLPA2005) PMIC. To ensure reliable operation, the DLP2010NIR DMD must
always be used with a DLPC150/3470 controller and a DLPA200X PMIC.
7.2 Functional Block Diagram
High Speed Interface
Misc
Column Write
Control
Bit Lines
(0,0)
Voltages
Word Lines
Voltage
Generators
SRAM
Row
(479, 853)
Control
Column Read
Control
Low Speed Interface
Note
Details omitted for clarity.
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7.3 Feature Description
7.3.1 Power Interface
The power management IC, DLPA200X, contains 3 regulated DC supplies for the DMD reset circuitry: VBIAS,
VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC150/3470 controller.
7.3.2 Low-Speed Interface
The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is
the low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 6-13 shows an equivalent test load circuit for the
output under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS
or other simulation tools to correlate the timing reference load to a system environment. The load capacitance
value stated is only for characterization and measurement of AC timing signals. This load capacitance value
does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC150/3470 controller. See the DLPC150/DLPC3470 controller
data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections:
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from
the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from
any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display’s border and/or active area could occur.
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7.5.1.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Illumination
Direction
Off-state
Light
Figure 7-1. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat
load. The relationship between micromirror array temperature and the reference ceramic temperature is provided
by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (AILLUMINATION × PNIR X DMD absorption factor)
)
(1)
(2)
(3)
where
•
•
TARRAY = Computed DMD array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 7-1
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•
RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in
Section 6.5
•
•
•
•
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics
AILLUMINATION = Illumination area (assumes 83.7% on the active array and 16.3% overfill)
PNIR = Illumination Power Density (W/cm2)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. Refer to the specifications in Electrical Characteristics. Absorbed power from the illumination source
is variable and depends on the operating state of the mirrors and the intensity of the light source.
The DMD
absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the DMD
active array, and 16.3% on the DMD array border and window aperture.
A sample calculation is detailed below:
TCERAMIC = 35 °C, assumed system measurement; see Recommended Operating Conditions for specification limits
PNIR= 2 W/cm2
QELECTRICAL = 0.0908 W; See the table notes in Recommended Operating Conditions for details.
AILLUMINATION = 0.143 cm2
QARRAY = QELECTRICAL + (QILLUMINATION X DMD absoprtion factor) = 0.0908 W + (2 W/cm2 X 0.143 cm2 X 0.42) = 0.211 W
TARRAY = 35 °C + (0.211 W × 7.9°C/W) = 36.67 °C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time and in the OFF state 25% of the time, whereas 25/75 would indicate that the pixel is in the ON state 25%
of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time. Note that
when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF
or ON) is considered negligible and is thus ignored. Since a micromirror can only be landed in one state or the
other (ON or OFF), the two numbers (percentages) nominally add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the
landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example,
a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in Figure 6-1. The importance of this curve is that:
•
•
All points along this curve represent the same usable life.
All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
•
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
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In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in binary pattern display with value '1' or when displaying pure-white on a given pixel for a given
time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, a binary
pattern display with value '0' or when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.
Table 7-1. Binary Pattern
Mode Example: Binary
Value and Landed Duty
Cycle
NOMINAL
BINARY
LANDED DUTY
VALUE
CYCLE
0
1
0/100
100/0
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = ∑{Pattern[i]_Binary_Value} / {Total_Patterns}
where
(4)
•
Pattern[i]_Binary_Value represent a pixel's pattern and its corresponding binary value over all patterns in the
pattern sequence: Total_Patterns.
For example, assume a pattern sequence with three patterns using pixel x. In this sequence the first pattern has
pixel x on, the second pattern has pixel x off, and the third pattern has pixel x off. Thus, the Landed Duty Cycle is
33%.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC150/3470
controller. The new high tilt pixel in the side illuminated DMD increases device efficiency and enables a
compact optical system. The DLP2010NIR DMD can be combined with a grating and single element detector
to replace expensive InGaAs linear array detector designs, leading to high performance, cost-effective portable
NIR Spectroscopy solutions. Applications of interest include machine vision systems, spectrometers, medical
systems, skin analysis, material identification, chemical sensing, infrared projection, and compressive sensing.
DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005. Refer to
Power Supply Recommendations for power-up and power-down specifications. DLP2010NIR DMD reliability is
only specified when used with DLPC150/3470 controller and DLPA2000 or DLPA2005 PMIC/LED Driver.
8.2 Typical Application
A typical embedded system application using the DLPC150/3470 controller and DLP2010NIR is shown in Figure
8-1. In this configuration, the DLPC150/3470 controller supports a 24-bit parallel RGB input, typical of LCD
interfaces, from an external source or processor. The DLPC150/3470 controller processes the digital input image
and converts the data into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting
specific micromirrors to the on position, directing light to the detector, while unwanted micromirrors are set to
"off" position, directing light away from the detector. The microprocessor sends binary images to the DMD to
steer specific wavelengths of light into the detector. The microprocessor uses an analog-to-digital converter to
sample the signal received by the detector into a digital value. By sequentially selecting different wavelengths of
light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light.
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DC_IN
BAT
Charger
2.3 to 5.5 V
Power
Management
1.8 V
1.1 V
Other
Supplies
1.1-V
Reg
VIN
SYSPWR
PROJ_ON
On/Off
VDD
1.8 V
1.8S V
VLED
LS_IN
PROJ_ON
USB
DLPA2000
or
DLPA2005
PROJ_ON
SPI_0
RED
Detector
ADC
4
FLASH
Current
Sense
SPI_1
4
RESETZ
INTZ
FLASH,
SDRAM
Microprocessor
PARKZ
HOST_IRQ
TRIG_IN
Illumination
Optics
BIAS, RST, OFS
3
LED_SEL(2)
CMP_PWM
DLPC150
TRIG_OUT (2)
Keypad
CMP_OUT
Parallel RGB I/F (28)
SD
Card
DLP2010NIR
(WVGA
DMD)
Thermistor
I2C
Sub-LVDS DATA
LPSDR CTRL
1.8S V
1.1 V
VIO
Bluetooth
VCC_INTF
VCC_FLSH
VCORE
Projection
Optics
NIR
Detector
ADC + Amplifier
DLP® Chip Set
Figure 8-1. Typical Application Diagram
8.2.1 Design Requirements
All applications using DLP 0.2-inch WVGA chipset require the DLPC150/3470 controller, DLPA2000 or
DLPA2005 PMIC, and DLP2010NIR DMD components for operation. The system also requires an external
SPI flash memory device loaded with the DLPC150/3470 Configuration and Support Firmware. The chipset has
several system interfaces and requires some support circuitry. The following interfaces and support circuitry are
required for the DLP2010NIR:
•
DMD Interfaces:
– DLPC150/3470 to DLP2010NIR SubLVDS Digital Data
– DLPC150/3470 to DLP2010NIR LPSDR Control Interface
DMD Power:
•
– DLPA2000 or DLPA2005 to DLP2010NIR VBIAS Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VOFFSET Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VRESET Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VDDI Supply
– DLPA2000 or DLPA2005 to DLP2010NIR VDD Supply
The illumination light that is applied to the DMD is typically from an infrared LED or lamp.
8.2.2 Detailed Design Procedure
For connecting together the DLPC150/3470, the DLPA2005, and the DLP2010NIR DMD, see the TI DLP
NIRscan Nano EVM reference design schematic.
8.2.3 Application Curve
In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light
spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150/3470 controls
individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The
microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital
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value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the
microprocessor can then plot a spectral response to the light. This systems allows the measurement of the
collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption
spectrum shown in Figure 8-2.
SPACE
Figure 8-2. Sample DLP2010NIR Based Spectrometer Output
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and
VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device.
Note
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device
reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up
and power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD’s reliability and lifetime. Refer to Figure 9-2. VSS must also be connected.
9.1 Power Supply Power-Up Procedure
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
•
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. Refer to Table 9-1 and the Layout Example for
power-up delay requirements.
•
•
During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow
the requirements listed previously and in Figure 9-1.
9.2 Power Supply Power-Down Procedure
•
Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended
Operating Conditions (Refer to Note 2 for Figure 9-1).
•
•
•
•
During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in
Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 9-1.
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9.3 Power Supply Sequencing Requirements
(4)
Mirror park sequence
VDD / VDDI
VDD and VDDI
VDD and VDDI
VSS
VSS
VBIAS
VBIAS
VBIAS
VDD ≤ VBIAS < 6 V
VBIAS < 4 V
ûV < Specification(2)
VSS
VSS
ûV < Specification(1)(2)
VOFFSET
VOFFSET
VDD ≤ VOFFSET < 6 V
ûV < Specification(3)
VOFFSET
VOFFSET < 4 V
VSS
VSS
VSS
VSS
VRESET < 0.5 V
VRESET > œ4 V
VRESET
VRESET
VDD
VRESET
VDD
DMD_DEN_ARSTZ
VSS
VSS
VSS
VSS
VSS
VSS
Initialization
VDD
VDD
LS_CLK
LS_WDATA
VID
D_P(0:3), D_N(0:3)
DCLK_P, DCLK_N
t
2
t
3
t
4
t
1
A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
B. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating
Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to
remove VBIAS prior to VOFFSET during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.
C. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended
Operating Conditions.
D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after
the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence
through software control.
E. Drawing is not to scale and details are omitted for clarity.
Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
Table 9-1. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
UNIT
ms
V
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
2
VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2)
6
6
VBIAS
Supply voltage level during power–up sequence delay (see Figure 9-2)
V
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12
8
VOFFSET
VDD ≤ VOFFSET ≤ 6 V
4
VSS
0
t
DELAY
20
16
12
8
VBIAS
VDD ≤ VBIAS ≤ 6 V
4
VSS
0
Time
Note
Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 9-2. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board or board-to-
board connector to a flex cable. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
•
•
•
•
•
•
Match lengths for the LS_WDATA and LS_CLK signals.
Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1.
Minimum of 100-nF decoupling capacitor close to VBIAS. Capacitor C4 in Figure 10-2.
Minimum of 100-nF decoupling capacitor close to VRESET. Capacitor C6 in Figure 10-2.
Minimum of 220-nF decoupling capacitor close to VOFFSET. Capacitor C7 in Figure 10-2.
Optional minimum 200- to 220-nF decoupling capacitor to meet the ripple requirements of the DMD. C5 in
Figure 10-2.
•
•
Minimum of 100-nF decoupling capacitor close to VCCI. Capacitor C1 in Figure 10-2.
Minimum of 100-nF decoupling capacitor close to both groups of VCC pins, for a total of 200 nF for VCC.
Capacitor C2/C3 in Figure 10-2.
10.2 Layout Example
Figure 10-1. High-Speed (HS) Bus Connections
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Figure 10-2. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
DLP2010 NIRA FQJ
Package Type
NIR DMD
Device Descriptor
Figure 11-1. Part Number Description
11.1.3 Device Markings
Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector.
GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number
GHJJJJKHVVVV
Figure 11-2. DMD Marking
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DLPC150
DLPC3470
DLPA2000
DLPA2005
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
DLP™, Pico™, and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP2010NIRAFQJ
ACTIVE
CLGA
FQJ
40
120
RoHS & Green
Call TI
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-May-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DLP2010NIRAFQJ
FQJ
CLGA
40
120
10 x 12
150
315 135.9 12190
23
31
16.2
Pack Materials-Page 1
DWG NO.
SH
8
5
3
6
1
7
4
1
2512515
REVISIONS
C
COPYRIGHT 2012 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
DATE
BY
BMH
9/14/2012
ECO 2127544: INITIAL RELEASE
ECO 2129552: ENLARGE APERTURE ON RIGHT SIDE;
MOVE ACTIVE ARRAY Y-LOCATION DIM, SH. 3
ECO 2131252: ENLARGE APERTURE ALONG BOTTOM EDGE
ECO 2135244: CORRECT WINDOW THK TOL, ZONE B6
ECO 2138016: INCREASE WINDOW THK NOMINAL
ECO 2186532: ADD APERTURE SLOTS PICTORIALLY
1
2
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
12/10/2012
B
BMH
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
2/20/2013
8/5/2013
11/21/2013
3/31/2020
C
D
E
F
BMH
BMH
BMH
BMH
3
4
5
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
DMD MARKING TO APPEAR IN CONNECTOR RECESS.
D
C
B
A
D
C
B
A
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
6
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
7
8
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
9
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
1.1760.05
4X (R0.2)
5
5
+
-
0.3
0.1
5.3
5
90° 1°
5
(ILLUMINATION
DIRECTION)
4X R0.4 0.1
5
2X 2.5 0.075
(2.5)
5
C
1.25
5
A
A
5
2.65
8
5
+
0.2
0.1
B
-
+
-
0.2
0.1
1.4
5
5
+
-
0.2
0.1
(1)
0.8
14.1 0.08
+
0.3
-
0.1
15.9
(OFF-STATE
DIRECTION)
6 7
1.0030.077
0.7 0.05
D
2X ENCAPSULANT
(1.783)
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
0.038A
0.02D
1 9
9
A
0.78 0.063
ACTIVE ARRAY
1.40.1
(2.5)
0.05
(1.4)
5
0.4 MIN
TYP.
H
H
(0.88)
(SHEET 3)
(SHEET 3)
0 MIN TYP.
(PANASONIC AXT640124DD1, 40-CONTACT, 0.4 mm
PITCH BOARD-TO-BOARD CONNECTOR HEADER)
MATES WITH PANASONIC AXT540124DD1 OR EQUIVALENT
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
TEXAS
9/14/2012
9/14/2012
9/26/2012
9/26/2012
9/18/2012
9/18/2012
B. HASKETT
INSTRUMENTS
ENGINEER
Dallas Texas
CONNECTOR SOCKET
SECTION A-A
NOTCH OFFSETS
B. HASKETT
QA/CE
ANGLES 1
TITLE
ICD, MECHANICAL, DMD,
.2 WVGA SERIES 244
(FQJ PACKAGE)
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
P. KONRAD
CM
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
F. ARMSTRONG
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
0314DA
USED ON
REMOVE ALL BURRS AND SHARP EDGES
M. DORAK
APPROVED
2512515
F
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
NEXT ASSY
SCALE
SHEET
OF
APPLICATION
M. SOUCEK
20:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2512515
2
2X (1)
A2
2X 1.176
2X (0.8)
2X 14.1
A3
D
C
B
A
D
C
B
A
4X 1.45
1.25
C
2.5
4X (1.2)
B
8
9
(1.1)
E1
A1
VIEW B
DATUMS A, B, C, AND E
1.176
14.1
(FROM SHEET 1)
5.5
(2.5)
C
1.25
2.75
B
6
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
(FROM SHEET 1)
2X 0 MIN
7
VIEW D
ENCAPSULANT MAXIMUM HEIGHT
DWG NO
REV
SIZE
DRAWN
DATE
9/14/2012
TEXAS
2512515
B. HASKETT
F
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2512515
3
(4.6116)
ACTIVE ARRAY
6.454 0.075
3
4X (0.108)
0.940.05
0.1340.0635
D
C
B
A
D
C
B
A
(4.86)
WINDOW
(2.592)
ACTIVE ARRAY
(ILLUMINATION
DIRECTION)
3.0160.0635
(3.15)
APERTURE
3.920.05
F
G
(2.5)
C
1.25
1.102 0.075
B
2
0.424 0.0635
2.9610.05
4.8390.0635
(5.263)
APERTURE
6.505 0.05
(9.466)
WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
53X TEST PADS
0.2ABC
50X 0.6±0.1 X 0.54±0.1
3X Ø0.54±0.1
0.1A
4
(9.8)
3.326
BACK INDEX MARK
0.4ABC
(42°) TYP.
(42°) TYP.
C
B
2.23
1.25
(2.5)
2X (1.86)
0.4ABC
(0.15) TYP.
(0.075) TYP.
2X 0.93
5 X 0.892 = 4.46
(42°) TYP.
(0.068) TYP.
(0.068) TYP.
1.026
18 X 0.8 = 14.4
DETAIL G
APERTURE RIGHT EDGE
DETAIL F
APERTURE LEFT EDGE
VIEW H-H
(POND OF MIRRORS OMITTED FOR CLARITY)
SCALE 60 : 1
SCALE 60 : 1
TEST PADS AND CONNECTOR
(FROM SHEET 1)
DWG NO
REV
SIZE
DRAWN
DATE
9/14/2012
TEXAS
2512515
B. HASKETT
F
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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