DLP2021-Q1 [TI]
汽车类 0.2 英寸 DLP® 数字微镜器件 (DMD);
| 型号： | DLP2021-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 0.2 英寸 DLP® 数字微镜器件 (DMD) |
| 文件： | 总27页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP2021-Q1
ZHCSMH3A –FEBRUARY 2022 –REVISED NOVEMBER 2022
DLP2021-Q1 0.2 英寸16:9 数字微镜器件
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性：
DLP2021-Q1 汽车数字微镜器件 (DMD) 专为汽车外部
照明控制和显示应用而设计。应用包括显示全彩色和动
画及动态内容的地面投影。地面投影有助于实现车辆对
行人 (V2P) 通信，例如倒车和车门打开警告，以及协
调车辆通信系统和汽车个性化选项。由于尺寸小且运行
功耗低，采用 DLP2021-Q1 芯片组的投影仪可以支持
很多投影应用。这类投影仪可以安装在车辆上的很多位
置，例如后视镜、车门、尾灯以及前格栅等等。
– 器件温度等级2：-40°C 至+105°C 环境工作温
度范围
– 人体放电模型(HBM) ESD 分类等级1C
– 充电器件模型(CDM) ESD 分类等级C4B
• 0.2 英寸对角线微镜阵列
– 7.6µm 微镜间距
– ±12° 微镜倾斜角（相对于平面）
– 可减小系统尺寸的侧向照明
• 16:9 (588 × 330) 输入分辨率
• 高达832 × 468 的有效分辨率
• 偏振无关型空间光调制器
• 与LED 或激光光源兼容
• 低功耗：260mW（最大值）
• 工作温度范围：–40°C 至105°C
• 气密封装
器件信息
封装
器件型号(1)
DLP2021-Q1
封装尺寸（标称值）
8.55mm × 16.80mm
FQU (64)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 80MHz 双倍数据速率(DDR) 数字微镜器件(DMD)
接口
2 应用
• 动态地面投影
• 车辆内外视频投影
DCLK
SPI
DATA[0:9]
CONTROL
DMD
MCU
IRQ
BIAS
SPI Flash
(Video and Images,
FPGA Configuration)
SPI
DMD Voltage
Regulator
ENABLE
OFFSET
RESET
DLP2021 Configured
Controller
DRIVE_EN
MUX
RED_PWM
BLUE_PWM
GREEN_PWM
IADJ
LED Driver
PWM_SEL_0
PWM_SEL_1
SHUNT_EN
RED_EN
GREEN_EN
BLUE_EN
GND
DLP2021-Q1 系统方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS207
DLP2021-Q1
ZHCSMH3A –FEBRUARY 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
8.5 DMD Image Performance Specification....................17
8.6 Micromirror Array Temperature Calculation.............. 17
8.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
9.3 Application Mission Profile Consideration.................20
10 Power Supply Recommendations..............................21
10.1 Power Supply Sequencing Requirements.............. 21
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Temperature Diode Pins..........................................23
12 Device and Documentation Support..........................24
12.1 Device Support....................................................... 24
12.2 Documentation Support.......................................... 25
12.3 接收文档更新通知................................................... 25
12.4 支持资源..................................................................25
12.5 Trademarks.............................................................25
12.6 Electrostatic Discharge Caution..............................25
12.7 Device Handling......................................................25
12.8 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 Storage Conditions..................................................... 5
7.3 ESD Ratings............................................................... 5
7.4 Recommended Operating Conditions.........................5
7.5 Thermal Information....................................................6
7.6 Electrical Characteristics.............................................7
7.7 Timing Requirements..................................................7
7.8 System Mounting Interface Loads.............................. 9
7.9 Micromirror Array Physical Characteristics...............10
7.10 Micromirror Array Optical Characteristics............... 12
7.11 Window Characteristics...........................................12
7.12 Chipset Component Usage Specification............... 12
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 System Optical Considerations.................................16
Information.................................................................... 25
13.1 Package Option Addendum....................................26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2022) to Revision A (November 2022)
Page
• 根据最新的德州仪器(TI) 和行业数据表标准对本文档进行了更新.......................................................................1
• Updated Electrostatic discharge HBM value...................................................................................................... 5
• Updated RESET_STROBE Setup and Hold values........................................................................................... 8
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5 说明（续）
该芯片组能够与 LED 或激光器搭配使用，以生成具有 125% 以上国家电视系统委员会(NTSC) 色域的高饱和度颜
色，并且可以与 RGB 或白色光源搭配使用。DLP2021-Q1 具有现场可编程门阵列 (FPGA) 配置，可用于驱动
DLP2021-Q1 汽车 DMD。此控制器架构专为小型投影仪而设计，不需要视频总线或图形处理单元 (GPU) 即可创
建内容。视频和图像内容存储在本地闪存中，上电即可播放，也可根据命令进行播放。
6 Pin Configuration and Functions
16 15 14 13
4
3
12
5
2
1
G
F
E
D
C
B
A
图6-1. FQU Package 64-Pin LGA Bottom View
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Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
A2
A4
B2
B3
B5
C2
C3
B4
C5
D2
F4
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
DATA(8)
DATA(9)
DCLK
Data bus. Synchronous to rising edge and falling edge of DCLK
Data clock
LVCMOS input
Parallel latch load enable. Synchronous to rising edge and
falling edge of DCLK
LOADB
SCTRL
TRC
F3
E4
Serial control (sync). Synchronous to rising edge and falling
edge of DCLK
Toggle rate control. Synchronous to rising edge and falling edge
of DCLK
F2
Reset control serial bus. Synchronous to rising edge of
SAC_CLK
DAD_BUS
B15
RESET_OEZ
C15
B13
Active low. Output enable signal for internal reset driver circuitry
Rising edge on RESET_STROBE latches in the control signals
RESET_STROBE
Stepped address control serial bus. Synchronous to rising edge
of SAC_CLK
SAC_BUS
A15
SAC_CLK
TEMP_MINUS
TEMP_PLUS
VBIAS
A14
G13
G2
Stepped address control clock
Calibrated temperature diode used to assist accurate
temperature measurements of DMD die
Analog input
D15
Power supply for positive bias level of mirror reset signal
Power supply for low voltage CMOS logic. Power supply for
normal high voltage at mirror address electrodes. Power supply
for offset level of mirror reset signal during power down
A5, B12, C14, D12,
F13, G3
VCC
Power supply for high voltage CMOS logic. Power supply for
stepped high voltage at mirror address electrodes. Power
supply for offset level of mirror reset signal
VOFFSET
VRESET
E14
D14
Power
Power supply for negative reset level of mirror reset signal
A3, A13, B14, C4,
C12, C13, D13, E3,
E5, E12, F12, F14,
G4, G12
VSS
Common return for all power
A1, A12, A16,B1,
B16, D3, D4, D5,
E2, E13,E15, F1,
F5, F15, F16, G1,
G5, G14, G15, G16
RESERVED
Reserved
Do not connect.
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7 Specifications
7.1 Absolute Maximum Ratings
See (1)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE
VDD
LVCMOS logic supply voltage
2.3
8.75
17
V
V
V
V
V
V
–0.5
–0.5
–0.5
–11
VOFFSET
VBIAS
Supply voltage for HVCMOS and micromirror electrode
Supply voltage for micromirror electrode
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)
VRESET
0.5
8.75
28
| VBIAS–VOFFSET
|
Supply voltage delta (absolute value)
| VBIAS–VRESET
|
INPUT VOLTAGE
Input voltage for LVCMOS Pins
VDD + 0.5
500
V
–0.5
–40
TEMPERATURE DIODE
ITEMP_DIODE
ENVIRONMENTAL
TARRAY
Max current source into temperature diode
µA
Operating DMD array temperature
105
°C
Illumination overfill maximum heat load in area shown
in Illumination Overfill Diagram
ILLOVERFILL
50 mW/mm2
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
UNIT
Tstg
DMD storage temperature
125
°C
–40
7.3 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±1000
±750
V(ESD) Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE
Supply voltage for LVCMOS core logic
VDD
1.7
1.8
1.95
V
Supply voltage for LPSDR low-speed interface
Supply voltage for HVCMOS and micromirror electrode
Supply voltage for mirror electrode
VOFFSET
VBIAS
8.25
15.5
8.5
16
8.75
16.5
V
V
V
V
V
VRESET
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)
–9.5
–10
–10.5
8.75
| VBIAS–VOFFSET
| VBIAS–VFRESET
|
|
Supply voltage delta (absolute value)
28
LVCMOS Buffers
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7.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
0.7
NOM
MAX
UNIT
VIH
Positive going threshold voltage
Negative going threshold voltage
VDD+0.3 x VDD
VIL
-0.3
0.3
x VDD
CLOCK FREQUENCY
Clock frequency for high speed interface SAC_CLK
Duty Cycle Distortion tolerance SAC_CLK
Clock frequency for high speed interface DCLK
Duty Cycle Distortion tolerance DCLK
20
30
20
30
76.2
76.2
80
70
80
70
MHz
%
ƒmax
DCDIN
MHz
%
ƒmax
DCDIN
TEMPERATURE DIODE
ITEMP_DIODE
ENVIRONMENTAL
TARRAY
Max current source into temperature diode
120
uA
Operating DMD array temperature(3)
Illumination, wavelength < 395 nm (2)
105
°C
–40
ILLUV
2 mW/cm 2
Illumination overfill maximum heat load in area
shown in Illumination Overfill Diagram
ILLOVERFILL
40 mW/mm 2
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.
(3) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.
Limited illumination area
on window apertur
Window
dow
ture
Wi
Window
Aperture
图7-1. Illumination Overfill Diagram
7.5 Thermal Information
DLP2021-Q1
FQU
THERMAL METRIC
UNIT
64 PINS
5
Thermal resistance
Active area-to-test point 1 (TP1) (1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the
DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by
the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy
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falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the
device.
7.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT
IDD
Supply current: VDD
VDD = 1.95 V
30
15
mA
mA
mA
mA
IOFFSET
IBIAS
Supply current: VOFFSET
Supply current: VBIAS
Supply current: VRESET
VOFFSET = 8.75 V
VBIAS = 16.5 V
2.3
3.3
IRESET
POWER
PDD
VRESET = –10.5 V
Supply power dissipation: VDD
Supply power dissipation: VOFFSET
Supply power dissipation: VBIAS
Supply power dissipation: VRESET
Supply power dissipation: Total
VDD = 1.95 V
60
132
38
mW
mW
mW
mW
mW
POFFSET
PBIAS
PRESET
PTOTAL
LVCMOS Buffers
VOFFSET = 8.75 V
VBIAS = 16.5 V
VRESET = –10.5 V
30
260
VOH
VOL
IIL
High level output voltage
0.8 × VDD
–100
–5
V
IOH = –2 mA
Low level output voltage
Low level input current(2)
High level output current(2)
Low level input current(3)
High level output current(3)
IOH = 2 mA
0.2 × VDD
135
V
VDD = 1.95 V; VI = 0 V
VDD = 1.95 V; VI = 1.95 V
VDD = 0.0 V
nA
uA
uA
uA
IIH
IIL2
IIH2
CAPACITANCE
VDD = 1.95 V
785
CIN
Input capacitance
10
15
25
pF
pF
pF
ƒ= 1 MHz
ƒ= 1 MHz
ƒ= 1 MHz
COUT
CTEMP
Output capacitance
Temperature sense diode capacitance
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) Specification is for LVCMOS input pins which do not have pull up or pull down resistors.
(3) Specification is for LVCMOS input pins which do have pull down resistors.
7.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted
MIN
NOM
MAX
UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tsu
th
tsu
th
1
1
1
1
ns
ns
ns
ns
Setup time SAC_BUS low before SAC_CLK↑
Hold time SAC_BUS low after SAC_CLK↑
Setup time DAD_BUS high before SAC_CLK↑
Hold time DAD_BUS high after SAC_CLK↑
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tsu
th
tsu
th
tsu
th
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
ns
Setup time DATA(9:0) before DCLK↑or DCLK↓
Hold time DATA(9:0) after DCLK↑or DCLK↓
Setup time SCTRL before DCLK↑or DCLK↓
Hold time SCTRL after DCLK↑or DCLK↓
Setup time TRC before DCLK↑or DCLK↓
Hold time TRC after DCLK↑or DCLK↓
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7.7 Timing Requirements (continued)
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted
MIN
1.0
1.0
1.5
NOM
MAX
UNIT
ns
Setup time LOADB low before DCLK↑or DCLK
↓
tsu
th
ns
Hold time LOADB low after DCLK↑or DCLK↓
Setup time RESET_STROBE high before DCLK
↑or DCLK↓
tsu
ns
Hold time RESET_STROBE high after DCLK↑
or DCLK↓
th
tw
tw
tw
tr
1.5
5
ns
ns
ns
ns
ns
ns
Pulse width 50% to 50% reference points: DCLK
high or low
pulse width 50% to 50% reference points: LOADB
low
7
pulse width 50% to 50% reference points:
RESET_STROBE high
7
Rise time 20% to 80% reference points: DCLK,
DATA, SCTRL, TRC, LOADB,SAC_CLK
2.5
2.5
Fall time 80% to 20% reference points: DCLK,
DATA, SCTRL, TRC, LOADB,SAC_CLK
tf
tW
tW
50%
50%
50%
50%
50%
50%
50%
SAC_CLK
tH
tSU
50%
50%
SAC_BUS
tSU
tH
50%
50%
DAD_BUS
VCC
80%
20%
SAC_CLK
VSS
tR
tF
图7-2. DMD Mirror and SRAM Control Logic Timing Requirements
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tW
tW
DCLK
50%
50%
50%
50%
50%
tH
tH
tSU
tSU
DATA
SCTRL
TRC
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
tSU
tH
50%
50%
LOADB
tW(L)
tH
tSU
50%
50%
RESET_STROBE
tW(L)
VCC
80%
DCLK
DATA
SCTRL
TRC
LOADB
20%
VSS
tR
tF
图7-3. DMD Data Path and Control Logic Timing Requirements
7.8 System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Uniformly distributed within the Thermal Interface Area shown in
图7-4
Thermal Interface Area
Electrical Interface Area
70
N
Uniformly distributed within the Electrical Interface Area shown
in 图7-4
100
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Thermal Interface Area
Electrical Interface Area
图7-4. System Interface Loads
7.9 Micromirror Array Physical Characteristics
PARAMETER
VALUE
416
UNIT
micromirrors
micromirrors
µm
M
N
Number of active columns(1)
Number of active rows(1)
468
Micromirror Pitch (diagonal)(2)
7.6
ε
P
Micromirror Pitch (horizontal and vertical)(2)
Micromirror active array width
Micromirror active array height
Micromirror active border
10.8
4.498
2.533
10
µm
(P × M) + (P / 2)
mm
(P x N) / 2 + (P / 2)
mm
Pond of micromirrors (POM) (3)
micromirrors/side
(1) See Array Physical Characteristics.
(2) See Pixel Pitch.
(3) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
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(0,0)
Illumination
Border Mirrors (POM) are Omitted for Clarity
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Illumination
On-State
Off-State
Tilt Direction
Tilt Direction
DMD Active Mirror Array
Row 460
Row 461
Row 462
Row 463
Row 464
Row 465
Row 466
Row 467
4.4982 mm
DMD Periphery
图7-5. Micromirror Array Physical Characteristics
x
(
u
m
)
P (um)
图7-6. Mirror (Pixel) Pitch
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7.10 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle
DMD efficiency(2)
TEST CONDITIONS
MIN
NOM
12
MAX
UNIT
DMD landed state(1)
11
13
degree
66%
420 nm –700 nm
(1) Measured relative to the plane formed by the overall micromirror array at 25°C
(2) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection
apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the
efficiency numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or
overfill loss. This number is measured under conditions described above and deviations from these specified conditions could result in
a different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application
include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as
LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. DLPA083A describes the interaction of these
system factors, as well as the DMD efficiency factors that are not system dependent.
7.11 Window Characteristics
PARAMETER
MIN
NOM
Corning Eagle XG
1.5119
MAX
UNIT
Window material designation
Window refractive index
Window aperture (1)
at wavelength 546.1 nm
See (1)
(1) See the mechanical package ICD for details regarding the size and location of the window aperture.
7.12 Chipset Component Usage Specification
The DLP2021-Q1 DMD is a component of a Texas Instruments DLP® chipset including a DLP products
controller. Reliable function and operation of the DMD requires that it be used in conjunction with a DLP products
controller.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
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8 Detailed Description
8.1 Overview
The DLP2021-Q1 DMD has a resolution of 416 × 468 mirrors configured in a diamond format that results in an
aspect ratio of 16:9 which creates an effective resolution of 588 × 330 square pixels. By configuring the pixels in
a diamond format, the illumination input to the DMD enters from the side allowing for smaller mechanical
packaging of the optical system.
8.2 Functional Block Diagram
V
V
CC
SS
DMD Mirror &
SRAM
Control Logic
RESET_OEZ
DAD_BUS
V
CC
RESET_SROBE
SAC_BUS
V
SS
DMD Mirror &
SRAM Voltage
Control
DMD Data
Path and
Logic
SAC_CLK
DATA(9:0)
DCLK
0.2 16:9 Aspect Ratio
SRAM & Micromirror Array
Control
V
V
V
V
V
RESET
BIAS
OFFSET
CC
LOADB
SCTRL
TRC
SS
TEMP_PLUS
TEMP_MINUS
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8.3 Feature Description
To ensure reliable operation, the DLP2021-Q1 DMD must be used with a DLP products controller.
8.3.1 Micromirror Array
The DLP2021-Q1 DMD consists of a two-dimensional array of 1-bit CMOS memory cells that determine the state
of the each of the 416 × 468 micromirrors in the array. Refer to 节 7.9 section for a calculation of how the 416 ×
468 micromirror array represents a 16:9 dimensional aspect ratio to the user. Each micromirror is either ON
(tilted +12°) or OFF (tilted –12°). Combined with appropriate projection optical system the DMD can be used to
create sharp, colorful, and vivid digital images.
8.3.2 Double Data Rate (DDR) Interface
Each DMD micromirror and its associated SRAM memory cell is loaded with data from the DLP controller via the
DDR interface (DATA(9:0), DCLK, LOADB, SCRTL, and TRC). These signals are low voltage CMOS nominally
operating at 1.8-V level to reduce power and switching noise. This high speed data input to the DMD allows for a
maximum update rate of the entire micromirror array to be nearly 5 kHz, enabling the creation of seamless digital
images using Pulse Width Modulation (PWM).
8.3.3 Micromirror Switching Control
Once data is loaded onto the DMD, the mirrors switch position (+12° or –12°) based on the timing signal sent to
the DMD Mirror and SRAM control logic. The DMD mirrors will be switched from OFF to ON or ON to OFF, or
stay in the same position based on control signals DAD_BUS, RESET_STROBE, SAC_BUS, and SAC_CLK,
which are coordinated with the data loading by the DLP controller. In general, the DLP controller loads the DMD
SRAM memory cells over the DDR interface, and then commands to the micromirrors to switch position.
At power down, the DMD Mirrors are commanded by the DLP controller to move to a near flat (0°) position as
shown in 节 10. The flat state position of the DMD mirrors are referred to as the “Parked” state. To maintain
long-term DMD reliability, the DMD must be properly “Parked” prior to every power down of the DMD power
supplies.
8.3.4 DMD Voltage Supplies
The micromirrors switching requires unique voltage levels to control the mechanical switching. These voltages
levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET). The specification values for VBIAS
VOFFSET, and VRESET are shown in 节7.4.
,
8.3.5 Logic Reset
Reset of the DMD is required and controlled by the DLP products controller.
8.3.6 Temperature Sensing Diode
The DMD includes a temperature sensing diode designed to be used with the TMP411-Q1 or equivalent
temperature monitoring device.
图 8-1 shows the typical connection between the DLP products controller, TMP411-Q1, and the DLP2021-Q1
DMD. The signals to the temperature sense diode are sensitive to system noise, and care should be taken in the
routing and implementation of this circuit. See the TMP411-Q1 data sheet for detailed PCB layout
recommendations.
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DLP Products Controller
DMD
50
SCL
SCA
D+
D-
100 pF
50
Temperature
Sense IC
图8-1. Temperature Sense Diode Typical Circuit Configuration
It is recommended that the host controller manage parking of the DMD based on the allowable temperature
specifications and temperature measurements.
8.3.6.1 Temperature Sense Diode Theory
A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.
The diode is formed by connecting the transistor base to the collector. Two different known currents flow through
the diode and the resulting diode voltage is measured in each case. The difference in the base-emitter voltages
is proportional to the absolute temperature of the transistor.
Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.
图8-2 and 图8-3 illustrate the relationship between the current and voltage through the diode.
IE1
IE2
+
VBE 1,2
-
图8-2. Temperature Measurement Theory
100uA
10uA
1uA
Temperature (°C)
Temperature (°C)
图8-3. Example of Delta VBE vs Temperature
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8.4 System Optical Considerations
Optimizing system optical performance and image performance strongly relates to optical system design
parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality
and optical performance is contingent on compliance to the optical system operating conditions described in the
following sections.
8.4.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block flat-state and stray light from passing
through the projection lens. The mirror tilt angle defines DMD capability to separate the "On" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than
the illumination numerical aperture angle, contrast ratio can be reduced and objectionable artifacts in the image
border and/or active area could occur.
8.4.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the image border and/or active area, which may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
8.4.3 Illumination Overfill and Alignment
Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and
other surfaces that surround the active array. These artifacts may be visible in the projected image. The
illumination optical system should be designed to minimize light flux incident outside the active array and on the
window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this
amount of overfill light on the area outside of the active array may still cause artifacts to be visible. Illumination
light and overfill can also induce undesirable thermal conditions on the DMD, especially if illumination light
impinges directly on the DMD window aperture or near the edge of the DMD window. Refer to 节 7.4 for a
specification on this maximum allowable heat load due to illumination overfill.
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8.5 DMD Image Performance Specification
PARAMETER
MIN
NOM
MAX
0
UNIT
Adjacent micromirrors
Non-adjacent micromirrors
Number of non-operational micromirrors(1)
Optical performance
micromirrors
10
See 节8.4
(1) A non-operational micromirror is defined as a micromirror that is unable to transition between the on-state and off-state positions.
8.6 Micromirror Array Temperature Calculation
Active array temperature can be computed analytically from measurement points on the outside of the package,
the package thermal resistance, the electrical power, and the illumination heat load.
Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in
图8-4) is provided by the following equations.
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
(1)
(2)
QARRAY = QELECTRICAL + QILLUMINATION
where
• TARRAY = computed DMD array temperature (°C)
• TCERAMIC = measured ceramic temperature (TP1 location in 图8-4) (°C)
• RARRAY-TO-CERAMIC = DMD package thermal resistance from array to TP1 (°C/watt) (see 节7.5)
• QARRAY = total power, electrical plus absorbed, on the DMD array (watts)
• QELECTRICAL = nominal electrical power dissipation by the DMD (watts)
• QILLUMINATION = (CL2W × SL)
• CL2W = conversion constant for screen lumens to power on the DMD (watts/lumen)
• SL = measured screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies.
Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and
the intensity of the light source.
Equations shown previous are valid for a 1-Chip DMD system with total projection efficiency from DMD to the
screen of 87%.
The constant CL2W is based on the DMD array characteristics. It assumes a spectral efficiency of 300 lumens/
watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array
border.
Sample calculation:
• SL = 50 lm
• CL2W = 0.00293 W/lm
• QELECTRICAL = 0.105 W
• RARRAY-TO-CERAMIC = 5°C/W
• TCERAMIC = 55°C
QARRAY = 0.105 W + (0.00293 × 50 lm) = 0.252 W
(3)
(4)
TARRAY = 55°C + (0.252 W × 5°C/W) = 56.26
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Illuminatio
Direction
Array
TP1
10.00
0
图8-4. Thermocouple Location
8.7 Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, assuming a fully-saturated white pixel, a landed duty cycle of 90/10 indicates that the referenced
pixel is in the ON state 90% of the time (and in the OFF state 10% of the time), whereas 10/90 would indicate
that the pixel is in the OFF state 90% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time
and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The DLP2021-Q1 DMD was designed to be used in automotive applications such as dynamic ground projection.
The information shown in this section describes the dynamic ground projection application.
9.2 Typical Application
The DLP2021-Q1 DMD combined with a DLP products controller are the primary devices that make up the
reference design for a dynamic ground projection system as shown in the block diagram 图9-1.
DCLK
SPI
DATA[0:9]
CONTROL
DMD
MCU
IRQ
SPI
BIAS
SPI Flash
(Video and Images,
FPGA Configuration)
DMD Voltage
Regulator
ENABLE
OFFSET
RESET
DLP2021 Configured
Controller
DRIVE_EN
RED_PWM
BLUE_PWM
GREEN_PWM
IADJ
MUX
LED Driver
PWM_SEL_0
PWM_SEL_1
SHUNT_EN
RED_EN
GREEN_EN
BLUE_EN
GND
图9-1. Dynamic Ground Projection System Block Diagram
In this architecture, video content is compressed and stored in external flash memory. Low speed SPI
commands are sent from a microcontroller or other processor to the DLP products controller to indicate what
video content to read from external memory. Storing the video content in memory removes the need for a high
speed video interface to the module which improves compatibility with typical vehicle infrastructures. It also
decreases overall system size and cost by removing graphics generation and interfaces. The controller
decompresses each bit plane of the video data (416 × 468 resolution) and displays them on the DMD in rapid
succession to create the full video image. Due to the diamond format of the DMD pixels, the output image has an
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effective resolution of 588 × 330. The controller synchronizes the DMD bit plane data with the RGB enable
timing for the LED color controller and driver circuit.
The controller may connect to a TMP411-Q1 to measure the DLP2021-Q1 temperature using the built-in
temperature sensing diode.
The controller combined with the DLP2021-Q1 may be used in RGB LED or laser illumination systems, or in
single-color systems as shown in 图9-2.
DCLK
SPI
DATA[0:9]
CONTROL
DMD
MCU
IRQ
SPI
BIAS
SPI Flash
(Video and Images,
FPGA Configuration)
DMD Voltage
Regulator
ENABLE
OFFSET
RESET
DLP2021 Configured
Controller
DRIVE_EN
LED_PWM
LED Driver
SHUNT_EN
LED_EN
GND
图9-2. Dynamic Ground Projection System Block Diagram - Single Color
9.3 Application Mission Profile Consideration
Each application is anticipated to have different mission profiles, or number of operating hours at different
temperatures. To assist in evaluation, the automotive DMD reliability lifetime estimates Application Report may
be provided. See the TI Application team for more information.
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10 Power Supply Recommendations
10.1 Power Supply Sequencing Requirements
• VBIAS, VCC, VOFFSET, VRESET, VSS are required to operate the DMD.
CAUTION
• For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power up and power down procedures may affect
device reliability.
• The VCC, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power up
and power down operations. Failure to meet any of the following requirements will result in a
significant reduction in the DMD’s reliability and lifetime. Refer to 图10-1. VSS must also be
connected.
DMD Power Supply Power Up Procedure:
• During power up, VCC must always start and settle before VOFFSET, VBIAS and VRESET voltages are applied to
the DMD.
• During power up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta
between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for 图10-1).
• During power up, the DMD’s LVCMOS input pins shall not be driven high until after VCC has settled at
operating voltage.
• During power up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS
• Power supply slew rates during power up are flexible, provided that the transient voltage levels follow the
requirements listed previously in 节7.4 and in 图10-1.
.
DMD Power Supply Power Down Procedure
• VCC must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
• During power down it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that
the delta between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for 图10-1).
• During power down, the DMD’s LVCMOS input pins must be less than VCC + 0.3 V.
• During power down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS
.
• Power supply slew rates during power down are flexible, provided that the transient voltage levels follow the
requirements listed previously in 节7.4 and in 图10-1.
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10.1.1 Power Up and Power Down
Power
Off
VBIAS, VOFFSET, and VRESET
Disabled by DLP Products Controller
VCC
Mirror Park Sequence
RESET_OEZ
VSS
VCC
VCC
VSS
VSS
VBIAS
VBIAS
VBIAS < 4 V
V < 8.75 v
VSS
VSS
VOFFSET
V < 8.75 v
VOFFSET
VSS
VSS
VOFFSET < 4 V
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VCC
LVCMOS
Inputs
VSS
VSS
A. ±8.75-V delta, ∆V, shall be considered the max operating delta between VBIAS and VOFFSET. Customers may find that the most reliable
way to ensure this is to power VOFFSET prior to VBIAS during power up and to remove VBIAS prior to VOFFSET during power down.
图10-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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11 Layout
11.1 Layout Guidelines
For specific DMD PCB guidelines, use the following:
• VCC should have at least 1 × 2.2-µF and 4 × 0.1-µF capacitors evenly distributed among the 6 VCC pins.
• A 0.1-µF, X7R rated capacitor should be placed near every pin for VBIAS, VRSET, and VOFF
.
11.2 Temperature Diode Pins
The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411-Q1 or
equivalent temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411-Q1 are
sensitive to noise. See the TMP411-Q1 data sheet for specific routing recommendations.
Avoid routing the temperature diodes signals near other traces to reduce coupling of noise onto these signals.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
DLP2021 A FQU Q1
Automotive Qualified
Package Type
Temperature Range
Device Descriptor
图12-1. Part Number Description
12.1.2 Device Markings
The device marking is shown in 图 12-2. The marking will include both human-readable information and a 2-
dimensional matrix code.
The human-readable information is described in 图 12-2. The 2-dimensional matrix code is an alpha-numeric
character string that contains the DMD part number and lot trace code.
Two-Dimensional Matrix Code
(DMD part number and lot trace code)
Part Marking
Lot Trace Code
图12-2. DMD Marking
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12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TMP411-Q1 ±1°C Remote and Local Temperature Sensor With N-Factor and Series
Resistance Correction data sheet
• Texas Instruments, DMD Optical Efficiency for Visible Wavelengths application report
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Device Handling
The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see
the DMD Handling application note for instructions on how to properly handle the DMD.
12.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
Packaging Information
Package
Type
Lead/Ball
Finish
Device
Marking
Orderable Device
Status
Package Drawing Pins
FQU 54
Package Qty Eco Plan
126 Green
MSL Peak Temp Op Temp (°C)
XDLP2021AFQUQ1
PREVIEW
CLGA
Call TI
N/A for Pkg Type -40 to 105
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI
has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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