DLP3020-Q1 [TI]
采用小型 S247 封装的汽车类 0.3 英寸 DLP® 数字微镜器件 (DMD);
| 型号： | DLP3020-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用小型 S247 封装的汽车类 0.3 英寸 DLP® 数字微镜器件 (DMD) |
| 文件： | 总39页 (文件大小：1520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP3020-Q1
ZHCSPE1 –FEBRUARY 2022
适用于汽车内部显示的DLP3020-Q1 0.3 英寸WVGA DMD
1 特性
3 说明
• 已通过汽车认证
• 0.3 英寸对角线微镜阵列
DLP3020-Q1 汽车DMD 主要面向具有大视场或增强现
实功能（需要长焦距）的汽车抬头显示 (HUD) 应用。
该芯片组能够与 LED 或激光器搭配使用，以生成具有
125% 以上 NTSC 色域的深度饱和颜色并支持 24 位
RGB 视频输入。此外，该芯片组可以凭借宽动态范围
和快速开关功能（不随温度的变化而变化）实现高亮度
（15,000cd/m2 典型值）HUD 系统。当用于TI 参考设
计中时，能够实现超过 5000:1 的极高动态范围，以满
足汽车 HUD 系统针对明亮的白昼和黑暗的夜晚驾驶条
件的工作范围要求。该器件与 DLP3030-Q1 具有相同
的微镜阵列，但封装尺寸更小，从而可以减小光学系统
设计的整体体积。
– 7.6µm 微镜间距
– ±12° 微镜倾斜角（相对于平面）
– 用于效率优化的侧向照明
• WVGA (864 × 480) 分辨率
• 偏振无关型空间光调制器
– 与LED 或激光光源兼容
– 可通过偏光眼镜看到图像
• 低功耗：105mW（典型值）
• 工作温度范围：–40°C 至105°C
• 具有7.0°C/W 热效率的气密封装
• 可实现系统内验证的JTAG 边界扫描
• 与DLPC120-Q1 汽车DMD 控制器兼容
• 78MHz DDR DMD 接口
器件信息
封装
器件型号(1)
DLP3020-Q1
封装尺寸（标称值）
FQR (64)
8.55 mm × 16.80 mm
• 与DLP3030-Q1 具有相同的微镜阵列，但封装尺寸
更小
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 宽视场和增强现实抬头显示(HUD)
• 数字仪表组、导航和信息娱乐系统挡风玻璃显示
• 车内投影显示和照明
Color & Dimming control
Flash
SPI
I2C
TMS320
F28023
Color
Controller
& Driver
Host
SPI
DLPC120-Q1
LEDs
Illumination
Control
& Feedback
Video
Processing &
DMD
real-time
optical
feedback
loop
24-bit RGB
& Syncs
Formatting
photo diode
LED Enable
Timing Control
Data & Control
Reset
DLP3020-Q1
Power Good
I2C
TMP411
-Q1
Data &
Address
DMD Power
DDR-2 DRAM
frame buffer
TPS65100-Q1
Power Enable
DLP3020-Q1 系统方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS081
DLP3020-Q1
ZHCSPE1 –FEBRUARY 2022
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Table of Contents
7.5 DMD Image Performance Specification....................26
7.6 Micromirror Array Temperature Calculation.............. 26
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 27
8 Application and Implementation..................................28
8.1 Application Information............................................. 28
8.2 Typical Application.................................................... 28
8.3 Application Mission Profile Consideration.................29
9 Power Supply Recommendations................................30
9.1 Power Supply Sequencing Requirements................ 30
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Temperature Diode Pins......................................... 32
11 Device and Documentation Support..........................33
11.1 Device Support........................................................33
11.2 Documentation Support.......................................... 34
11.3 接收文档更新通知................................................... 34
11.4 支持资源..................................................................34
11.5 Trademarks............................................................. 34
11.6 Electrostatic Discharge Caution..............................34
11.7 Device Handling......................................................34
11.8 术语表..................................................................... 34
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 Storage Conditions..................................................... 6
6.3 ESD Ratings............................................................... 6
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information....................................................8
6.6 Electrical Characteristics.............................................9
6.7 Timing Requirements................................................ 11
6.8 Switching Characteristics..........................................15
6.9 System Mounting Interface Loads............................ 15
6.10 Physical Characteristics of the Micromirror Array...16
6.11 Micromirror Array Optical Characteristics............... 18
6.12 Window Characteristics.......................................... 19
6.13 Chipset Component Usage Specification............... 19
7 Detailed Description......................................................20
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................20
7.3 Feature Description...................................................21
7.4 System Optical Considerations.................................25
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
February 2022
*
Initial Release
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5 Pin Configuration and Functions
16 15 14 13 12
4
3
5
2
1
G
F
E
D
C
B
A
图5-1. FQR Package, 64-Pin LGA (Bottom View)
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表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
DATA(0)
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
DATA(8)
DATA(9)
DATA(10)
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DCLK
A2
A4
B2
B3
B5
C2
C3
B4
C5
D2
D3
D4
D5
E2
F5
Data bus. Synchronous to rising edge and falling edge of DCLK.
LVCMOS
input
F4
Data clock.
LOADB
F3
Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK.
Serial control (sync). Synchronous to rising edge and falling edge of DCLK.
Toggle rate control. Synchronous to rising edge and falling edge of DCLK.
Reset control serial bus. Synchronous to rising edge of SAC_CLK.
Active low. Output enable signal for internal reset driver circuitry.
SCTRL
E4
F2
TRC
DAD_BUS
RESET_OEZ
B15
C15
RESET_STROB
E
B13
Rising edge on RESET_STROBE latches in the control signals.
SAC_BUS
SAC_CLK
TCK
A15
A14
F15
Stepped address control serial bus. Synchronous to rising edge of SAC_CLK.
Stepped address control clock.
JTAG clock.
JTAG data input. Synchronous to rising edge of TCK. Bond pad connects to internal pull
up resistor.
TDI
E13
G15
G14
LVCMOS
output
TDO
TMS
JTAG data output. Synchronous to falling edge of TCK. Tri-state fail-safe output buffer.
LVCMOS
input
JTAG mode select. Synchronous to rising edge of TCK. Bond pad connects to internal
pull up resistor.
TEMP_MINUS
TEMP_PLUS
VBIAS
G13
G2
Calibrated temperature diode used to assist accurate temperature measurements of
DMD die.
Analog input
D15
Power supply for positive bias level of mirror reset signal.
Power supply for low voltage CMOS logic. Power supply for normal high voltage at
mirror address electrodes. Power supply for offset level of mirror reset signal during
power down.
Power
A5, B12, C14,
D12, F13, G3
VCC
Power supply for high voltage CMOS logic. Power supply for stepped high voltage at
mirror address electrodes. Power supply for offset level of mirror reset signal.
VOFFSET
E14
VREF
E15
D14
Power supply for low voltage CMOS DDR interface.
VRESET
Power supply for negative reset level of mirror reset signal.
Power
A3, A13, B14,
C4, C12, C13,
D13, E3, E5,
E12, F12, F14,
G4, G12
VSS
Common return for all power.
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
A1, A12,
A16,B1, B16,
F1, F16, G1,
G5, G16
RESERVED
Reserved Do not connect.
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6 Specifications
6.1 Absolute Maximum Ratings
See (2)
MIN
MAX
UNIT
SUPPLY VOLTAGE(1)
VREF
LVCMOS logic supply voltage
LVCMOS logic supply voltage
Mirror electrode and HVCMOS voltage
Mirror electrode voltage
4
4
V
V
–0.5
–0.5
–0.5
–0.5
VCC
VOFFSET
VBIAS
8.75
17
V
V
Supply voltage delta(3)
8.75
0.5
V
|VBIAS –VOFFSET
|
VRESET
Mirror electrode voltage
V
–11
–0.5
60
Input voltage: other inputs
fDCLK
VREF + 0.3
82
V
Clock frequency
MHz
µA
ITEMP_DIODE
Temperature diode current
500
ENVIRONMENTAL
TARRAY
Operating DMD array temperature(4)
105
°C
–40
(1) All voltage values are with respect to the ground pins (VSS).
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Unless otherwise
indicated, these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond
those indicated under Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods
may affect device reliability.
(3) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than or equal to 8.75 V.
(4) See 节7.6.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system. The device is not designed to be exposed to corrosive
environments.
MIN
MAX
UNIT
Tstg
DMD storage temperature
125
°C
–40
6.3 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM) per AEC Q100-011
All Pins
All Pins
±2000
±750
±750
V(ESD) Electrostatic discharge
V
Corner Pins(2)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Corner pins are A1, G1, A16, and G16.
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6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE
VREF
LVCMOS interface power supply voltage
LVCMOS logic power supply voltage
Mirror electrode and HVCMOS voltage
Mirror electrode voltage
1.65
2.25
8.25
15.5
1.8
2.5
8.5
16
1.95
2.75
8.75
16.5
8.75
V
V
VCC
VOFFSET
VBIAS
V
V
Supply voltage delta (2)
V
|VBIAS –VOFFSET
VRESET
VP VT+
VN VT–
VH ∆VT
IOH_TDO
IOL_TDO
|
Mirror electrode voltage
V
–9.5
0.4 × VREF
0.3 × VREF
0.1 × VREF
–10
–10.5
0.7 × VREF
0.6 × VREF
0.4 × VREF
Positive going threshold voltage
Negative going threshold voltage
V
V
V
Hysteresis voltage (Vp –Vn)
High level output current @ Voh = 2.25 V, TDO, Vcc = 2.25 V
Low level output current @ Vol = 0.4 V, TDO, Vcc = 2.25 V
mA
mA
–2
2
TEMPERATURE DIODE
ITEMP_DIODE
Max current source into temperature diode (4)
120
µA
ENVIRONMENTAL
(5)
TARRAY
Operating DMD array temperature - steady state (1)
Illumination, wavelength < 395 nm
105
2.0
°C
–40
(3)
ILLUV
mW/cm2
Illumination overfill maximum heat load in
ILLOVERFILL
ILLOVERFILL
26
20
T
ARRAY ≤75°C
area shown in 图6-1 (6)
mW/mm2
Illumination overfill maximum heat load in
area shown in 图6-1 (6)
TARRAY > 75°C
(1) DMD active array temperature can be calculated as shown in 节7.6 and assumes uniform illumination across the array.
(2) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than or equal to 8.75 V.
(3) The maximum operation conditions for DMD array temperature and illumination UV shall not be implemented simultaneously.
(4) Temperature diode is to assist in the calculation of the DMD array temperature during operation.
(5) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.
(6) The active area of the DLP3020-Q1 device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light
illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the
DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the
particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may
cause system performance degradation. Overfill illumination in excess of this specification may also impact thermal performance.
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Window
Window
Aperture
Window
0.5 mm
Window
Aperture
0.5 mm
Limited illumination area
on window aperture
图6-1. Illumination Overfill Diagram
6.5 Thermal Information
DLP3020-Q1
THERMAL METRIC(1)
FQR (LGA)
64 PINS
7.0
UNIT
Thermal resistance
Active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in 节6.4. The total heat load on the DMD is largely driven by the
incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
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6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
VCC = 2.25 V
IOH = –8 mA
VREF = 1.8 V
IOH = –2 mA
VCC = 2.75 V
IOL = 8 mA
VOH
VOH2
VOL
High level output voltage
1.7
V
High level output voltage(6)
Low level output voltage
Low level output voltage(6)
1.44
V
V
V
0.4
VREF = 1.8 V
IOL = 2 mA
VOL2
0.36
VREF = 1.95 V
VOL = 0 V
–10
–5
IOZ
Output high impedance current
µA
VREF = 1.95 V
VOH = VREF
VREF = 1.95 V
VI = 0 V
10
6
IIL
Low level input current(3)
High level input current(3)
Low level input current(4)
High level input current(4)
Low level input current(5)
High level input current(5)
µA
µA
µA
µA
µA
µA
VREF = 1.95 V
VI = VREF
IIH
VREF = 1.95 V
VI = 0 V
IIL2
IIH2
IIL3
IIH3
–785
–5
VREF = 1.95 V
VI = VREF
6
VREF = 1.95 V
VI = 0 V
VREF = 1.95 V
VI = VREF
785
CURRENT
IREF
Current at VREF = 1.95 V
Current at VCC = 2.75 V
fDCLK = 80 MHz
fDCLK = 80 MHz
2.80
59.90
2.93
mA
mA
mA
mA
mA
Icc
IOFFSET
IBIAS
Current at VOFFSET = 8.75 V
Current at VBIAS = 16.5 V
Current at VRESET = –10.5 V
2.30
IRESET
–2.00
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
POWER
PREF
Power at VREF = 1.95 V
fDCLK = 80 MHz
fDCLK = 80 MHz
5.46
164.73
25.64
mW
mW
mW
mW
mW
mW
PCC
Power at VCC = 2.75 V
POFFSET
PBIAS
Power at VOFFSET = 8.75 V
Power at VBIAS = 16.5 V
Power at VRESET = –10.5 V
Total power at nominal conditions
37.95
PRESET
PTOTAL
CAPACITANCE
CIN
21.00
fDCLK = 80 MHz
254.77
Input pin capacitance
20
65
20
pF
pF
pF
ƒ= 1 MHz
ƒ= 1 MHz
ƒ= 1 MHz
Analog pin capacitance (TEMP_PLUS and
TEMP_MINUS pins)
CA
Co
Output pin capacitance
(1) All voltage values are with respect to the ground pins (VSS).
(2) Device electrical characteristics are over 节6.4 unless otherwise noted.
(3) Specification is for LVCMOS input pins, which do not have pull up or pull down resistors. See 节5.
(4) Specification is for LVCMOS input pins which do have pull up resistors (JTAG: TDI, TMS). See 节5.
(5) Specification is for LVCMOS input pins which do have pull down resistors. See 节5.
(6) Specification is for LVCMOS JTAG output pin TDO.
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6.7 Timing Requirements
Over 节6.4 unless otherwise noted.
MIN
NOM
MAX
UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tSU
tH
tSU
tH
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
Setup time SAC_BUS low before SAC_CLK↑
Hold time SAC_BUS low after SAC_CLK↑
Setup time DAD_BUS high before SAC_CLK↑
Hold time DAD_BUS after SAC_CLK↑
1.0
1.0
tC
Cycle time SAC_CLK
12.5
5.0
16.67
tW
tR
Pulse width 50% to 50% reference points: SAC_CLK high or low
Rise time 20% to 80% reference points: SAC_CLK
Fall time 80% to 20% reference points: SAC_CLK
2.5
2.5
tF
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tSU
tH
tSU
tH
tSU
tH
tSU
tH
tSU
tH
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
3.5
12.5
5.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time DATA(14:0) before DCLK↑or DCLK↓
Hold time DATA(14:0) after DCLK↑or DCLK↓
Setup time SCTRL before DCLK↑or DCLK↓
Hold time SCTRL after DCLK↑or DCLK↓
Setup time TRC before DCLK↑or DCLK↓
Hold time TRC after DCLK↑or DCLK↓
Setup time LOADB low before DCLK↑
Hold time LOADB low after DCLK↓
Setup time RESET_STROBE high before DCLK↑
Hold time RESET_STROBE after DCLK↑
tC
Cycle time DCLK
16.67
tW
Pulse width 50% to 50% reference points: DCLK high or low
Pulse width 50% to 50% reference points: LOADB low
Pulse width 50% to 50% reference points: RESET_STROBE high
Rise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB
Fall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB
tW(L)
tW(H)
tR
2.5
2.5
tF
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
fTCK
tC
Clock frequency TCK
10
MHz
ns
Cycle time TCK
100
10
5
tW
tSU
tH
Pulse width 50% to 50% reference points: TCK high or low
Setup time TDI valid before TCK↑
Hold time TDI valid after TCK↑
ns
ns
25
5
ns
tSU
tH
ns
Setup time TMS valid before TCK↑
Hold time TMS valid after TCK↑
25
ns
tR
Rise time 20% to 80% reference points: TCK, TDI, TMS
Fall time 80% to 20% reference points: TCK, TDI, TMS
2.5
2.5
ns
tR
ns
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tW
tW
tC
50%
50%
50%
50%
50%
50%
50%
SAC_CLK
tH
tSU
50%
50%
SAC_BUS
tSU
tH
50%
50%
DAD_BUS
VREF
80%
20%
SAC_CLK
VSS
tR
tF
图6-2. DMD Mirror and SRAM Control Logic Timing Requirements
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tW
tW
tC
DCLK
50%
50%
50%
50%
50%
tH
tH
tSU
tSU
DATA
SCTRL
TRC
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
tSU
tH
50%
50%
LOADB
tW(L)
tH
tSU
50%
50%
RESET_STROBE
tW(L)
VREF
80%
DCLK
DATA
SCTRL
TRC
LOADB
20%
VSS
tR
tF
图6-3. DMD Data Path and Control Logic Timing Requirements
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tW
tW
tC
50%
50%
50%
50%
TCK
tH
tSU
TDI
50%
50%
TMS
50%
50%
tPD
50%
TDO
VREF
80%
20%
TCK
TDI
TMS
VSS
tR
tF
图6-4. JTAG Boundary Scan Control Logic Timing Requirements
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6.8 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CL = 11 pF, from (Input) falling edge of
TCK to (Output) TDO, see 图6-4
tPD
3
25
ns
Output propagation, clock to Q (see 图6-4)
(1) Device electrical characteristics are over Recommended Operating Characteristics unless otherwise noted.
Data Sheet Timing Reference Point
Device Pin
Tester Channel
Output Under Test
CL
图6-5. Test Load Circuit for Output Propagation Measurement
6.9 System Mounting Interface Loads
PARAMETER
MIN NOM MAX
UNIT
N
70
Uniformly distributed within the Thermal Interface Area shown in 图6-6
Uniformly distributed within the Electrical Interface Area shown in 图6-6
100
N
Thermal Interface Area
Electrical Interface Area
图6-6. System Interface Loads
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UNIT
6.10 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
684
N
Number of active columns
micromirrors
See 图6-7
M Number of active rows
608
micromirrors
See 图6-7
7.6
µm
Micromirror (pixel) pitch –diagonal
Micromirror (pixel) pitch –horizontal and vertical
Micromirror active array width
See 图6-8
ε
P
10.8
6.5718
3.699
10
µm
mm
See 图6-8
P × M + P / 2; see 图6-7
(P × N) / 2 + P / 2; see 图6-7
Pond of micromirror (POM)(1)
Micromirror active array height
mm
Micromirror active border
micromirrors/side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
'/+/(
Hkktlhm`shnm
Anqcdq Lhqqnqr 'ONL( `qd Nlhssdc enq Bk`qhsx
Bnk /
Bnk 0
Bnk 1
Bnk 2
Bnk 3
Bnk 4
Bnk 5
Bnk 6
Hkktlhm`shnm
Nm‚Rs`sd
Nee‚Rs`sd
Shks Chqdbshnm
Shks Chqdbshnm
CLC @bshud Lhqqnq @qq`x
Bnk 565
Bnk 566
Bnk 567
Bnk 568
Bnk 57/
Bnk 570
Bnk 571
Bnk 572
5-4607 ll
CLC Odqhogdqx
图6-7. Micromirror Array Physical Characteristics
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x
(
u
m
)
P (um)
图6-8. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
表6-1. Optical Parameters
PARAMETER
Micromirror tilt angle, landed (on-state or off-state)(1)
Micromirror tilt angle tolerance(1)
MIN
NOM
MAX
UNIT
12
°
°
1
–1
DMD efficiency, 420 nm–680 nm(2)
66%
(1) For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some
optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
(2) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection
apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the
efficiency numbers are measured with 100% electronic mirror duty cycle and do not include system optical efficiency or overfill loss.
Note that this number is measured under conditions described above and deviations from these specified conditions could result in a
different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application
include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as
LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well
as the DMD efficiency factors that are not system dependent are described in detail in DMD Optical Efficiency for Visible Wavelengths.
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6.12 Window Characteristics
PARAMETER
MIN
NOM
MAX UNIT
Window material designation
Window refractive index
Window aperture(1)
Corning Eagle XG
1.5119
at wavelength 546.1 nm
See (1)
(1) See the package mechanical ICD for details regarding the size and location of the window aperture.
6.13 Chipset Component Usage Specification
The DLP3020-Q1 DMD is a component of a DLP® chipset including a DLP products controller. Reliable function
and operation of the DMD requires that it be used in conjunction with a DLP products controller.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously
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7 Detailed Description
7.1 Overview
The DLP3020-Q1 DMD has a resolution of 608 × 684 mirrors configured in a diamond format that results in an
aspect ratio of 16:9 which creates an effective resolution of 864 × 480 square pixels. By configuring the pixels in
a diamond format, the illumination input to the DMD enters from the side allowing for smaller mechanical
packaging of the optical system.
7.2 Functional Block Diagram
V
V
V
REF
CC
TCK
TDI
JTAG
Controller
SS
TDO
TMS
DMD Mirror &
SRAM
Control Logic
RESET_OEZ
DAD_BUS
RESET_SROBE
SAC_BUS
DMD Mirror &
SRAM Voltage
Control
V
CC
SAC_CLK
V
0.3 WVGA 16:9 Aspect Ratio
SRAM & Micromirror Array
REF
V
SS
V
V
V
V
V
RESET
BIAS
OFFSET
CC
DMD Data
Path and
Logic
DATA(14:0)
DCLK
Control
LOADB
SCTRL
SS
TRC
TEMP_PLUS
TEMP_MINUS
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7.3 Feature Description
To ensure reliable operation, the DLP3020-Q1 DMD must be used with a DLP products controller.
7.3.1 Micromirror Array
The DLP3020-Q1 DMD consists of a two-dimensional array of 1-bit CMOS memory cells that determine the state
of the each of the 608 × 684 micromirrors in the array. Refer to 节 6.10 for a calculation of how the 608 × 684
micromirror array represents a 16:9 dimensional aspect ratio to the user. Each micromirror is either “ON”
(tilted +12°) or “OFF” (tilted –12°). Combined with appropriate projection optical system the DMD can be
used to create sharp, colorful, and vivid digital images.
7.3.2 Double Data Rate (DDR) Interface
Each DMD micromirror and its associated SRAM memory cell is loaded with data from the DLP controller via the
DDR interface (DATA(14:0), DCLK, LOADB, SCRTL, and TRC). These signals are low voltage CMOS nominally
operating at 1.8-V level to reduce power and switching noise. This high speed data input to the DMD allows for a
maximum update rate of the entire micromirror array to be nearly 5 kHz, enabling the creation of seamless digital
images using Pulse Width Modulation (PWM).
7.3.3 Micromirror Switching Control
Once data is loaded onto the DMD, the mirrors switch position (+12° or –12°) based on the timing signal sent to
the DMD Mirror and SRAM control logic. The DMD mirrors will be switched from OFF to ON or ON to OFF, or
stay in the same position based on control signals DAD_BUS, RESET_STROBE, SAC_BUS, and SAC_CLK,
which are coordinated with the data loading by the DLP controller. In general, the DLP controller loads the DMD
SRAM memory cells over the DDR interface, and then commands to the micromirrors to switch position.
At power down, the DMD Mirrors are commanded by the DLP controller to move to a near flat (0°) position as
shown in 节 9. The flat state position of the DMD mirrors are referred to as the “Parked” state. To maintain
long-term DMD reliability, the DMD must be properly “Parked” prior to every power down of the DMD power
supplies.
7.3.4 DMD Voltage Supplies
The micromirrors switching requires unique voltage levels to control the mechanical switching. These voltages
levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET). The specification values for VBIAS
,
V
OFFSET, and VRESET are shown in 节6.4.
7.3.5 Logic Reset
Reset of the DMD is required and controlled by the DLP products controller.
7.3.6 Temperature Sensing Diode
The DMD includes a temperature sensing diode designed to be used with the TMP411-Q1 temperature
monitoring device. The DLP products controller may monitor the DMD array temperature via the TMP411-Q1
and temperature sense diode.
图 7-1 shows the typical connection between the DLP products controller, TMP411-Q1, and the DLP3020-Q1
DMD. The signals to the temperature sense diode are sensitive to system noise, and care should be taken in the
routing and implementation of this circuit. See the TMP411-Q1 data sheet for detailed PCB layout
recommendations.
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DLPC120
DLP3020-Q1
50
50
SCL
SCA
D+
D-
100 pF
TMP411-Q1
图7-1. Temperature Sense Diode Typical Circuit Configuration
It is recommended that the host controller manage parking of the DMD based on the allowable temperature
specifications and temperature measurements.
7.3.6.1 Temperature Sense Diode Theory
A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.
The diode is formed by connecting the transistor base to the collector. Two different known currents flow through
the diode and the resulting diode voltage is measured in each case. The difference in the base-emitter voltages
is proportional to the absolute temperature of the transistor.
Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.
图7-2 and 图7-3 illustrate the relationship between the current and voltage through the diode.
IE1
IE2
+
VBE 1,2
-
图7-2. Temperature Measurement Theory
100uA
10uA
1uA
Temperature (°C)
Temperature (°C)
图7-3. Example of Delta VBE vs Temperature
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7.3.7 DMD JTAG Interface
The DMD uses 4 standard JTAG signals for sending and receiving boundary scan test data. TCK is the test
clock used to drive an IEEE 1149.1 TAP state machine and logic. TMS directs the next state of the TAP state
machine. TDI is the scan data input and TDO is the scan data output.
The DMD does not support IEEE 1149.1 signals TRST (Test Logic Reset) and RTCK (Returned Test Clock).
Boundary scan cells on the DMD are Observe-Only. To initiate the JTAG boundary scan operation on the DMD,
a minimum of 6 TCK clock cycles are required after TMS is set to logic high.
Refer to 图7-4 for a JTAG system board routing example.
DLP Products
DLP302X-Q1
Controller
DMD_JTCK
DMD_JTMS
DMD_JTDI
DMD_JTDO
TCK
TMS
TDI
TDO
图7-4. System Interface Connection to DLP Products Controller
The DMD Device ID can be read via the JTAG interface. The ID and 32-bit shift order is shown in 图7-5.
MSB
31
28 27
12 11
1 0
Version (4 Bits)
Part Number (16 Bits)
Manufacturer ID (11 Bits)
LSB
1
TDI
TDO
0000
1011-1011-0001-1011
0000-0010-111
图7-5. DMD Device ID and 32-bit Shift Order
Refer to 图 7-6 for a JTAG boundary scan block diagram for the DMD. These show the pins and the scan order
that are observed during the JTAG boundary scan.
DATA(0)
DATA(1)
DATA(2)
SAC_BUS
DATA(3)
SAC_CLK
DATA(4)
DAD_BUS
DATA(5)
RESET_STROBE
DATA(6)
RESET_OEZ
DATA(7)
DATA(8)
DATA(9)
DMD Active Mirror Array
DATA(10)
DATA(11)
DATA(12)
DATA(13)
DATA(14)
DCLK
LOADB
TCK
Controller
Decoder
Registers
SCTRL
TRC
TMS
TDI
JTAG Boundary Scan Path
TDO
图7-6. JTAG Boundary Scan Path
Refer to 图7-7 for a functional block diagram of the JTAG control logic.
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BSC
BSC
BSC
BSC
BSC
BSC
BSC
Mirror Array & Core Logic
BSC
BSC
Device ID Register
Bypass Register
Instruction Decoder
Instruction Register
TDI
TCK
TMS
TAP Controller
TDO
BSC = Boundary Scan Cell [Observe Only]
TAP = Test Access Port
图7-7. JTAG Functional Block Diagram
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7.4 System Optical Considerations
Optimizing system optical performance and image performance strongly relates to optical system design
parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality
and optical performance is contingent on compliance to the optical system operating conditions described in the
following sections.
7.4.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block flat-state and stray light from passing
through the projection lens. The mirror tilt angle defines DMD capability to separate the "On" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than
the illumination numerical aperture angle, contrast ratio can be reduced and objectionable artifacts in the image
border and/or active area could occur.
7.4.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the image border and/or active area, which may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.4.3 Illumination Overfill and Alignment
Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and
other surfaces that surround the active array. These artifacts may be visible in the projected image. The
illumination optical system should be designed to minimize light flux incident outside the active array and on the
window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this
amount of overfill light on the area outside of the active array may still cause artifacts to be visible. Illumination
light and overfill can also induce undesirable thermal conditions on the DMD, especially if illumination light
impinges directly on the DMD window aperture or near the edge of the DMD window. Refer to 节 6.4 for a
specification on this maximum allowable heat load due to illumination overfill.
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7.5 DMD Image Performance Specification
PARAMETER (1)
Bright Pixels - Viewed on a linear gray 10 screen
Dark Pixels - Viewed on a white screen
Optical performance
MIN
NOM
MAX
UNIT
0
4
micromirrors
micromirrors
See System Optical Considerations
(1) Any artifact that is not specifically called out in this table is acceptable. Viewing distance must be > 60 in. Screen size should be similar
to application image size. All values referenced are in linear gamma. Non-linear gamma curves may be running by default, and it
should be ensured with a TI applications engineer that the equivalent linear gamma value as specified is used to judge artifacts.
7.6 Micromirror Array Temperature Calculation
Active array temperature can be computed analytically from measurement points on the outside of the package,
the package thermal resistance, the electrical power, and the illumination heat load.
Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in
图7-8) is provided by the following equations.
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
(1)
(2)
QARRAY = QELECTRICAL + QILLUMINATION
where
• TARRAY = computed DMD array temperature (°C)
• TCERAMIC = measured ceramic temperature (TP1 location in 图7-8) (°C)
• RARRAY-TO-CERAMIC = DMD package thermal resistance from array to TP1 (°C/watt) (see 节6.5)
• QARRAY = total power, electrical plus absorbed, on the DMD array (watts)
• QELECTRICAL = nominal electrical power dissipation by the DMD (watts)
• QILLUMINATION = (CL2W × SL)
• CL2W = conversion constant for screen lumens to power on the DMD (watts/lumen)
• SL = measured screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies.
Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and
the intensity of the light source.
Equations shown previous are valid for a 1-Chip DMD system with total projection efficiency from DMD to the
screen of 87%.
The constant CL2W is based on the DMD array characteristics. It assumes a spectral efficiency of 300 lumens/
watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array
border.
Sample calculation:
• SL = 50 lm
• CL2W = 0.00293 W/lm
• QELECTRICAL = 0.162 W
• RARRAY-TO-CERAMIC = 7.0°C/W
• TCERAMIC = 55°C
QARRAY = 0.162 W + (0.00293 × 50 lm) = 0.309 W
(3)
(4)
TARRAY = 55°C + (0.309 W × 7.0°C/W) = 57.2°C
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Illumination
Direction
Off-State
Light
Array
TP1
TP1
10.00
0.80
图7-8. Thermocouple Location
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, assuming a fully-saturated white pixel, a landed duty cycle of 90/10 indicates that the referenced
pixel is in the ON state 90% of the time (and in the OFF state 10% of the time), whereas 10/90 would indicate
that the pixel is in the OFF state 90% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time
and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLP3020-Q1 DMD was designed to be used in automotive applications such as head-up display (HUD).
The information shown in this section describes the HUD application based on the TI reference design. Contact
TI application engineer for information on this design.
8.2 Typical Application
The DLP3020-Q1 DMD combined with the DLPC120-Q1 are the primary devices that make up the reference
design for a HUD system as shown in the block diagram 图8-1.
Color & Dimming control
Flash
SPI
I2C
TMS320
F28023
Color
Controller
& Driver
Host
SPI
DLPC120-Q1
LEDs
Illumination
Control
& Feedback
Video
Processing &
DMD
real-time
optical
feedback
loop
24-bit RGB
& Syncs
Formatting
photo diode
LED Enable
Timing Control
Data & Control
Reset
DLP3020-Q1
Power Good
I2C
TMP411
-Q1
Data &
Address
DMD Power
DDR-2 DRAM
frame buffer
TPS65100-Q1
Power Enable
图8-1. HUD Reference Design Block Diagram
The DLPC120-Q1 accepts input video over the parallel RGB data interface up to 8 bits per color from a video
graphics processor. The DLPC120-Q1 then processes the video data (864 × 480 manhattan orientation) by
scaling the image to match the DMD resolution (608 × 684 diamond pixel), applies de-gamma correction, bezel
adjustment, and then formats the data into DMD bit plane information and stores the data into the DDR2 DRAM.
The DMD bit planes are read from DDR2 DRAM, and are then displayed on the DMD using pulse width
modulation (PWM) timing. The DLPC120-Q1 synchronizes the DMD bit plane data with the RGB enable timing
for the LED color controller and Driver circuit. Finally, the DMD accepts the bit plane formatted data from the
DLPC120-Q1 and displays the data according to the timing controlled by the DLPC120-Q1.
Due to the mechanical nature of the micromirrors, the latency of the DLP3020-Q1 and DLPC120-Q1 chipset is
fixed across all temperature and operating conditions. The observed video latency is one frame, or 16.67 ms at
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an input frame rate of 60 Hz. However, please note that the use of the DLPC120-Q1 bezel adjustment feature, if
enabled by the host controller, requires an additional frame of processing.
The DLPC120-Q1 is configured at power up by data stored in the flash file which stores configuration data, DMD
and sequence timing information, LED drive information, and other information related to the system functions.
See the DLPC120-Q1 programmer's guide for information about the this flash configuration data.
The HUD reference design from TI includes the TMS320F28023 microcontroller (Piccolo) which is used to
control the color point by adjusting the RGB flux levels, and drives each RGB LED. This circuit also manages the
dimming function for the HUD system. The dimming level of a HUD system requires very large dynamic range of
over 5000:1. For example, on a bright day, the HUD system may require a brightness level as high as 15,000
cd/m2 and conversely at night time the minimum brightness level desired may only be 3 cd/m2.
8.3 Application Mission Profile Consideration
Each application is anticipated to have different mission profiles, or number of operating hours at different
temperatures. To assist in evaluation, the automotive DMD reliability lifetime estimates Application Report may
be provided. See the TI Application team for more information.
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9 Power Supply Recommendations
9.1 Power Supply Sequencing Requirements
• VBIAS, VCC, VOFFSET, VREF, VRESET, VSS are required to operate the DMD.
CAUTION
• For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power up and power down procedures may affect
device reliability.
• The VCC, VREF, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power
up and power down operations. Failure to meet any of the following requirements will result in a
significant reduction in the DMD’s reliability and lifetime. Refer to 图9-1. VSS must also be
connected.
DMD Power Supply Power Up Procedure:
• During power up, VCC and VREF must always start and settle before VOFFSET, VBIAS and VRESET voltages are
applied to the DMD.
• During power up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta
between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for 图9-1).
• During power up, the DMD’s LVCMOS input pins shall not be driven high until after VCC and VREF have
settled at operating voltage.
• During power up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS
• Power supply slew rates during power up are flexible, provided that the transient voltage levels follow the
requirements listed previously in 节6.4 and in 图9-1.
.
DMD Power Supply Power Down Procedure
• VCC and VREF must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
• During power down it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that
the delta between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for 图9-1).
• During power down, the DMD’s LVCMOS input pins must be less than VREF + 0.3 V.
• During power down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS
.
• Power supply slew rates during power down are flexible, provided that the transient voltage levels follow the
requirements listed previously in 节6.4 and in 图9-1.
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9.1.1 Power Up and Power Down
Power
Off
VBIAS, VOFFSET, and VRESET
Disabled by DLP Products Controller
VCC / VREF
Mirror Park Sequence
RESET_OEZ
VSS
VCC / VREF
VCC
/
VREF
VSS
VSS
VBIAS
VBIAS
VBIAS < 4 V
ûV < 8.75 v
VSS
VSS
VOFFSET
ûV < 8.75 v
VOFFSET
VSS
VSS
VOFFSET < 4 V
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VCC
LVCMOS
Inputs
VSS
VSS
Note 1: ±8.75-V delta, ∆V, shall be considered the max operating delta between VBIAS and VOFFSET. Customers may find that the most
reliable way to ensure this is to power VOFFSET prior to VBIAS during power up and to remove VBIAS prior to VOFFSET during power down.
图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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10 Layout
10.1 Layout Guidelines
For specific DMD PCB guidelines, use the following:
• VCC should have at least 1 × 2.2-µF and 4 × 0.1-µF capacitors evenly distributed among the VCC pins.
• A 0.1-µF, X7R rated capacitor should be placed near every pin for the VREF, VBIAS, VRSET, and VOFF
.
10.2 Temperature Diode Pins
The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411-Q1
temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411-Q1 are sensitive
to noise. See the TMP411-Q1 data sheet for specific routing recommendations.
Avoid routing the temperature diodes signals near other traces to reduce coupling of noise onto these signals.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP3020 A FQR Q1
Automotive
Package
Temperature Range
Device Descriptor
图11-1. Part Number Description
11.1.2 Device Markings
The device marking is shown in 图 11-2. The marking will include both human-readable information and a 2-
dimensional matrix code.
The human-readable information is described in 图 11-2. The 2-dimensional matrix code is an alpha-numeric
character string that contains the DMD part number and lot trace code.
Two-Dimensional Matrix Code
(DMD part number and lot trace code)
Part Marking
Lot Trace Code
图11-2. DMD Marking
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• DLPC120-Q1 product folder for the DLPC120-Q1 data sheet and other documentation
• Texas instruments, TMS320F2802x Microcontrollers (Piccolo™) data sheet
• Texas Instruments, TMP411-Q1 ±1°C Remote and Local Temperature Sensor With N-Factor and Series
Resistance Correction data sheet
• Texas Instruments, DMD Optical Efficiency for Visible Wavelengths application report
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Device Handling
The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see
the DMD Handling application note for instructions on how to properly handle the DMD.
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP3020AFQRQ1
ACTIVE
CLGA
FQR
54
126
RoHS & Green
Call TI
N / A for Pkg Type
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
DWG NO.
SH
8
5
3
6
1
7
4
1
2516663
REVISIONS
C
COPYRIGHT 2019 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
B
DESCRIPTION
ECO 2181963: INITIAL RELEASE
ECO 2184085: ADD FRONT AND BACK SIDE INDEX MARKS
DATE
BY
BMH
BMH
6/25/2019
11/8/2019
1
2
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
3
4
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
C
B
A
D
C
B
A
5
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6
7
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
8
4X (R0.2)
4
1.176 0.05
4
+
-
0.2
3.025
0.1
4
4.275
4
+
-
0.2
0.1
C
4
(ILLUMINATION
DIRECTION)
1.25
2X 2.5 0.075
4
(2.5)
2X R0.4 0.1
+
-
0.3
0.1
4
4
8.55
A
90°1°
4
4
B
7
A
2X FRONT SIDE
INDEX MARKS
4
+
0.8
-
0.2
0.1
(1)
15 0.08
+
-
0.3
0.1
16.8
D
2X ENCAPSULANT
1.10.05
1.610.077
5 6
(2.39)
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
A
0.038A
0.02D
1 8
8
0.780.063
ACTIVE ARRAY
1.6 0.1
(1.6)
(2.5)
4
0.4 MIN
TYP.
H
H
(SHEET 3)
(SHEET 3)
0 MIN TYP.
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
TEXAS
6/25/2019
B. HASKETT
ENGINEER
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
INSTRUMENTS
Dallas Texas
6/24/2019
6/24/2019
6/30/2019
6/24/2019
6/26/2019
B. HASKETT
QA/CE
ANGLES 1
TITLE
SECTION A-A
NOTCH OFFSETS
ICD, MECHANICAL, DMD,
.3 WVGA SERIES 247
(FQR PACKAGE)
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
S. HUDGENS
CM
M. LOPEZ
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
0314DA
USED ON
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
B. RAY
APPROVED
2516663
B
NEXT ASSY
SCALE
SHEET
OF
APPLICATION
J. GRIMMETT
20:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2516663
2
2X (1)
2X 1.176
2X (0.8)
2X 15
A2
A3
D
C
B
A
D
C
B
A
C
4X 1.7
1.25
2.5
B
4X (2.575)
8
E1
1.176
15
(1.1)
7
VIEW B
A1
DATUMS A, B, C, AND E
(FROM SHEET 1)
C
8.75
1.25
(2.5)
B
4.375
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
5
6
2X 0 MIN
(FROM SHEET 1)
VIEW D
DWG NO
REV
SIZE
DRAWN
DATE
6/25/2019
TEXAS
2516663
ENCAPSULANT MAXIMUM HEIGHT
B. HASKETT
B
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2516663
3
(6.5718)
ACTIVE ARRAY
5.850.075
3
4X (0.108)
0.634 0.0635
1.602 0.05
D
C
B
A
D
C
B
A
C
2
2.2230.075
(4.584)
APERTURE
3.95 0.0635
1.25
(ILLUMINATION
DIRECTION)
(7.65)
WINDOW
(3.699)
ACTIVE ARRAY
F
(2.5)
6.048 0.05
B
0.5060.0635
7.090.0635
(7.596)
APERTURE
2.20.05
8.039 0.05
(10.239)
WINDOW
54X LGA PADS
0.75±0.05 X 0.75±0.05
VIEW E
SYMBOLIZATION PAD
(5.75 X 7.65)
0.2ABC
WINDOW AND ACTIVE ARRAY
10X TEST PADS
(Ø0.75)
0.1A
(FROM SHEET 1)
(42°)
TYP.
G
F
B
E
D
C
B
A
(0.15) TYP.
(2.5)
6 X 1 = 6
1.25
C
3
(42°)
TYP.
16
15
14
13
12
DETAIL F
5
4
3
2
1
1.276
15 X 1 = 15
APERTURE LEFT AND RIGHT EDGES
BACK SIDE
INDEX MARK
(WINDOW OMITTED FOR CLARITY)
SCALE 60 : 1
VIEW H-H
BACK SIDE METALLIZATION
(FROM SHEET 1)
DWG NO
REV
SIZE
DRAWN
DATE
6/25/2019
TEXAS
2516663
B. HASKETT
B
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
DLP3020AFQRQ1
Automotive 0.3-inch DLP® digital micromirror device (DMD) in small S247 package | FQR | 54 | -40 to 105
TI
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