DLP3310 [TI]

DLP® 0.33 1080p DMD;


型号：	DLP3310
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.33 1080p DMD
文件：	总46页 (文件大小：1919K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP3310

ZHCSJ26D –NOVEMBER 2018 –REVISED JULY 2023

DLP3310 0.33 1080p DMD

1 特性

3 说明

• 0.33 英寸(8.47mm) 对角线微镜阵列

DLP3310 数字微镜器件 (DMD) 是一款数控微光机电系

统(MOEMS) 空间光调制器(SLM)。当与适当的光学系

统搭配使用时，DLP3310 DMD 可显示非常清晰的高质

量图像或视频。DLP3310 是由 DLP3310 DMD、

– 全高清1920 × 1080 像素屏幕显示

– 5.4 µm 微镜间距

– 17° 微镜倾斜（相对于平坦表面）

– 采用侧面照明，实现最优的效率和光学引擎尺寸

– 偏振无关型铝微镜表面

DLPC3437

控制器和

DLPA3000/DLPA3005

PMIC/LED 驱动器所组成的芯片组的一部分。

DLP3310 外形小巧，与控制器和 PMIC/LED 驱动器共

同组成完整的系统解决方案，从而实现小尺寸、低功耗

和全高清的显示产品。

• 32 位subLVDS 输入数据总线

• 专用DLPC3437 控制器和DLPA3000/DLPA3005

PMIC/LED 驱动器确保可靠运行

器件信息⁽¹⁾

2 应用

封装尺寸（标称值）

器件型号

DLP3310

封装

• 移动智能电视

• 无屏电视

FQM (92)

19.25mm × 7.2mm

• 游戏显示器

• 数字标牌

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 可穿戴显示器

• Pico 投影仪

• 交互式显示器

• 超便携显示器

• 智能家居显示器

• 虚拟助手

DLPA3000/DLPA3005

VRESET

VOFFSET VBIAS

DLPC3437

D_BP(0:7)

D_AP(0:7)

D_AN(0:7)

D_BP(0:7)

540 MHz

SubLVDS

DDR

540 MHz

SubLVDS

DDR

DCLK_AP

DCLK_AN

DCLK_BP

DCLK_BN

Interface

DLP DMD

Digital

Micromirror

Device

LS_WDATA

LS_CLK

120 MHz

SDR

Interface

120 MHz

SDR

Interface

LS_RDATA_B

LS_RDATA_A

DMD_DEN_ARSTZ

Slave

Master

VDDI

VDD

VSS

(System signal routing omitted for clarity)

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS124

DLP3310

www.ti.com.cn

ZHCSJ26D –NOVEMBER 2018 –REVISED JULY 2023

Table of Contents

7.6 Micromirror Array Temperature Calculation.............. 26

7.7 Micromirror Power Density Calculation.....................27

7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 29

8 Application and Implementation..................................32

8.1 Application Information............................................. 32

8.2 Typical Application.................................................... 32

9 Power Supply Recommendations................................35

9.1 Power Supply Power-Up Procedure......................... 35

9.2 Power Supply Power-Down Procedure.....................35

9.3 Power Supply Sequencing Requirements................ 36

10 Layout...........................................................................38

10.1 Layout Guidelines................................................... 38

10.2 Layout Example...................................................... 38

11 Device and Documentation Support..........................39

11.1 第三方产品免责声明................................................39

11.2 Device Support........................................................39

11.3 Documentation Support.......................................... 39

11.4 Receiving Notification of Documentation Updates..39

11.5 支持资源..................................................................39

11.6 Trademarks............................................................. 39

11.7 静电放电警告...........................................................40

11.8 术语表..................................................................... 40

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 7

6.1 Absolute Maximum Ratings........................................ 7

6.2 Storage Conditions..................................................... 7

6.3 ESD Ratings............................................................... 8

6.4 Recommended Operating Conditions.........................8

6.5 Thermal Information..................................................12

6.6 Electrical Characteristics...........................................12

6.7 Timing Requirements................................................13

6.8 Switching Characteristics..........................................19

6.9 System Mounting Interface Loads............................ 19

6.10 Micromirror Array Physical Characteristics.............20

6.11 Micromirror Array Optical Characteristics............... 21

6.12 Window Characteristics.......................................... 23

6.13 Chipset Component Usage Specification............... 23

6.14 Software Requirements.......................................... 23

7 Detailed Description......................................................24

7.1 Overview...................................................................24

7.2 Functional Block Diagram.........................................24

7.3 Feature Description...................................................25

7.4 Device Functional Modes..........................................25

7.5 Optical Interface and System Image Quality

Information.................................................................... 40

Considerations............................................................ 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (May 2022) to Revision D (July 2023)

Page

• Added "ILLUMINATION" to Recommended Operating Conditions ....................................................................8

• Updated Micromirror Array Temperature Calculation ...................................................................................... 26

• Added Micromirror Power Density Calculation ................................................................................................ 27

Changes from Revision B (April 2022) to Revision C (May 2022)

Page

• Updated Micromirror Array Optical Characteristics ......................................................................................... 21

English Data Sheet: DLPS124

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ZHCSJ26D –NOVEMBER 2018 –REVISED JULY 2023

5 Pin Configuration and Functions

18 20

图5-1. FQM Package 92-Pin CLGA Bottom View

表5-1. Pin Functions –Connector Pins

PIN⁽¹⁾

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

DATA INPUTS

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AP(0)

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

SubLVDS

Double

Data, negative

2.83

4.00

1.97

4.03

1.90

3.08

2.23

3.88

2.72

3.89

1.87

3.93

1.79

2.97

2.12

3.78

2.23

3.27

1.27

3.52

1.34

2.55

1.71

3.37

2.13

3.16

1.17

3.42

1.23

Data, negative

Data, positive

Data, negative

Data, positive

C20

D19

D21

F19

F21

G20

H21

H19

C21

D20

D22

F20

F22

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English Data Sheet: DLPS124

DLP3310

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ZHCSJ26D –NOVEMBER 2018 –REVISED JULY 2023

表5-1. Pin Functions –Connector Pins (continued)

PIN⁽¹⁾

PACKAGE NET

TYPE

SIGNAL

DATA RATE

DESCRIPTION

LENGTH⁽²⁾(mm)

NAME

NO.

G21

H22

H20

D_BP(5)

D_BP(6)

D_BP(7)

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

SubLVDS

Double

Data, positive

2.44

1.61

3.27

2.56

2.46

2.05

1.95

Data, positive

Clock, negative

Clock, positive

Clock, negative

Clock, positive

E20

E21

CONTROL INPUTS

LS_WDATA

LPSDR⁽¹⁾

LPSDR

Single

Write data for low speed interface

Clock for low-speed interface

1.78

LS_CLK

Asynchronous reset DMD signal. A low

signal places the DMD in reset. A high

signal releases the DMD from reset

and places it in active mode.

DMD_DEN_ARSTZ

LPSDR

0.85

LS_RDATA_A

LS_RDATA_B

POWER

LPSDR

Single

Read data for low-speed interface

4.19

2.18

(3)

V_BIAS

Power

Supply voltage for positive bias level at

micromirrors

(3)

V_BIAS

A22

B21

(3)

V_OFFSET

Supply voltage for HVCMOS core

logic. Supply voltage for stepped high

level at micromirror address

electrodes.

Supply voltage for offset level at

micromirrors

(3)

V_OFFSET

Power

V_RESET

A23

Power

Supply voltage for negative reset level

at micromirrors

(3)

V_DD

A19

A20

A21

B20

Supply voltage for LVCMOS core logic.

Supply voltage for LPSDR inputs.

Supply voltage for normal high level at

micromirror address electrodes

D23

F23

English Data Sheet: DLPS124

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表5-1. Pin Functions –Connector Pins (continued)

PIN⁽¹⁾

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

V_DDI

V_SS

NO.

Power

B19

Power

C23

Power

Supply voltage for SubLVDS receivers

Power

E23

Power

G23

Power

Ground

A24

B22

B23

B24

C19

C22

Common return

Ground for all power

E19

E22

G19

G22

G24

H23

H24

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQM ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.

Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SSconnections are also

required.

表5-2. Pin Functions –Test Pads

NUMBER

SYSTEM BOARD

Do not connect.

A17

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English Data Sheet: DLPS124

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表5-2. Pin Functions –Test Pads (continued)

NUMBER

A18

SYSTEM BOARD

Do not connect.

B17

B18

English Data Sheet: DLPS124

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6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾

MIN

–0.5

MAX

2.3

UNIT

Supply voltage for LVCMOS core logic⁽²⁾

Supply voltage for LPSDR low speed interface

V_DD

V_DDI

Supply voltage for SubLVDS receivers⁽²⁾

Supply voltage for HVCMOS and micromirror

electrode^{(2) (3)}

V_OFFSET

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

0.5

Supply voltage

V_BIAS

–0.5

–15

V_RESET

0.3

|V_DDI–V_DD

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

Input voltage for other inputs LPSDR⁽²⁾

V_DD+ 0.5

V_DDI+ 0.5

810

–0.5

Input voltage

Input pins

Input voltage for other inputs SubLVDS^{(2) (7)}

|V_ID|

I_ID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

MHz

°C

SubLVDS input differential current

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

Temperature—operational⁽⁸⁾

130

ƒ_clock

Clock

frequency

620

–20

–40

T_ARRAYand T_WINDOW

Temperature—non-operational⁽⁸⁾

Environmental

Absolute temperature delta between any point on the

window edge and the ceramic test point TP1⁽⁹⁾

|T_DELTA

T_DP

°C

Dew point—operating and non-operating

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (V_SS). The following power supplies are all required to operate the DMD:

V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are also required.

(3) V_OFFSETsupply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between V_DDIand V_DDmay result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(6) Exceeding the recommended allowable absolute voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation) or of any point along the

window edge as defined in 图7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the

highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,

that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

6.2 Storage Conditions

applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

°C

T_DMD

DMD storage temperature

–40

T_DP-AVG

T_DP-ELR

Average dew point temperature (non-condensing)⁽¹⁾

Elevated dew point temperature range (non-condensing)⁽²⁾

°C

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applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

CT_ELR

Cumulative time in elevated dew point temperature range

Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

6.3 ESD Ratings

VALUE

UNIT

V_(ESD)Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽³⁾

V_DD

Supply voltage for LVCMOS core logic

1.65

1.8

1.95

Supply voltage for LPSDR low-speed interface

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode⁽⁴⁾

Supply voltage for mirror electrode

V_DDI

1.65

9.5

1.8

1.95

10.5

18.5

–13.5

0.3

V_OFFSET

V_BIAS

17.5

V_RESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

Supply voltage delta (absolute value)⁽⁷⁾

–14.5

–14

|V_DDI–V_DD

10.5

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

CLOCK FREQUENCY

Clock frequency for low speed interface LS_CLK⁽⁸⁾

108

300

120

540

MHz

ƒ_clock

Clock frequency for high speed interface DCLK⁽⁹⁾

Duty cycle distortion DCLK

44%

56%

SUBLVDS INTERFACE⁽⁹⁾

|V_ID|

150

250

900

350

SubLVDS input differential voltage (absolute value). See 图6-8,

图6-9.

V_CM

700

575

1100

1225

110

Common mode voltage. See 图6-8, 图6-9.

SubLVDS voltage. See 图6-8, 图6-9.

Line differential impedance (PWB/trace)

Internal differential termination resistance. See 图6-10.

100-Ωdifferential PCB trace

V_SUBLVDS

Z_LINE

Z_IN

100

Ω

120

6.35

152.4

ENVIRONMENTAL

T_ARRAY

40 to 70⁽¹²⁾

°C

Array temperature –long-term operational^{(10) (11) (12) (13)}

Array temperature –short-term operational, 25 hr max^{(11) (14)}

Array temperature –short-term operational, 500 hr max^{(11) (14)}

Window temperature –operational^{(15) (16)}

–20

–10

T_WINDOW

|T_DELTA

Absolute temperature delta between any point on the window

edge and the ceramic test point TP1⁽¹⁷⁾

T_DP-AVG

T_DP-ELR

Average dew point temperature, non-condensing⁽¹⁸⁾

°C

Elevated dew point temperature range, non-condensing⁽¹⁹⁾

English Data Sheet: DLPS124

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

UNIT

CT_ELR

Cumulative time in elevated dew point temperature range

Months

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UNIT

ZHCSJ26D –NOVEMBER 2018 –REVISED JULY 2023

6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

NOM

MAX

ILLUMINATION

ILL_UV

ILL_VIS

ILL_IR

Illumination power at wavelengths < 410 nm⁽¹⁰⁾

26.1

mW/cm²

W/cm²

mW/cm²

W/cm²

deg

Illumination power at wavelengths ≥410 nm and ≤800 nm⁽²⁰⁾

Illumination power at wavelengths > 800 nm

Illumination power at wavelengths ≥410 nm and ≤475 nm⁽²⁰⁾

Illumination power at wavelengths ≥410 nm and ≤445 nm⁽²⁰⁾

Illumination marginal ray angle⁽¹⁶⁾

ILL_BLU

ILL_BLU1

ILL_θ

8.3

1.5

(1) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SSconnections are also

required.

(2) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(3) All voltage values are with respect to the ground pins (V_SS).

(4) V_OFFSETsupply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |V_DDI–V_DD| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than the specified limit.

(7) To prevent excess current, the supply voltage delta |V_BIAS–V_RESET| must be less than the specified limit.

(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(9) Refer to the SubLVDS timing requirements in Timing Requirements.

(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will

reduce device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.

(12) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to 节7.8 for a definition of micromirror landed duty cycle.

(13) Long-term is defined as the useful life of the device.

(14) Short-term is the total cumulative time over the useful life of the device.

(15) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to measure the highest window edge

temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular

application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(16) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.

The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta temperature. If a

particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

(20) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength

range specified and the micromirror array temperature (T_ARRAY).

English Data Sheet: DLPS124

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0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

100/0 95/5

D001

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature—Derating Curve

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6.5 Thermal Information

DLP3310

FQM (LGA)

92 PINS

6.0

THERMAL METRIC⁽¹⁾

UNIT

Thermal resistance

Active area to test point 1 (TP1)

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by

the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy

falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the

device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

CURRENT

V_DD= 1.95 V

135

(3) (4)

I_DD

Supply current: V_DD

Supply current: V_DDI

V_DD= 1.8 V

123.6

V_DDI= 1.95 V

V_DD= 1.8 V

35.34

I_DDI

V_OFFSET= 10.5 V

V_OFFSET= 10 V

V_BIAS= 18.5 V

V_BIAS= 18 V

2.55

(5) (6)

I_OFFSET

Supply current: V_OFFSET

2.5

1.25

(5) (6)

I_BIAS

Supply current: V_BIAS

Supply current: V_RESET

1.2

V_RESET= –14.5 V

V_RESET= –14 V

–2.55

(6)

I_RESET

–2.5

POWER⁽⁷⁾

P_DD

V_DD= 1.95 V

263.25

(3) (4)

Supply power dissipation: V_DD

Supply power dissipation: V_DDI

V_DD= 1.8 V

222.48

57.6

V_DDI= 1.95 V

V_DD= 1.8 V

68.91

P_DDI

(5)

V_OFFSET= 10.5 V

V_OFFSET= 10 V

V_BIAS= 18.5 V

V_BIAS= 18 V

26.78

Supply power dissipation: V_OFFSET

P_OFFSET

(6)

23.13

(5) (6)

P_BIAS

Supply power dissipation: V_BIAS

21.6

36.98

V_RESET= –14.5 V

V_RESET= –14 V

(6)

P_RESET

Supply power dissipation: V_RESET

Supply power dissipation: Total

P_TOTAL

LPSDR INPUT⁽⁸⁾

361.68

419.05

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽⁹⁾

0.7 × V_DD

–0.3

V_DD+ 0.3

0.3 × V_DD

V_DD+ 0.3

0.2 × V_DD

0.4 × V_DD

DC input low voltage⁽⁹⁾

AC input high voltage⁽⁹⁾

AC input low voltage⁽⁹⁾

Hysteresis ( V_T+–V_T–

Low–level input current

0.8 × V_DD

–0.3

0.1 × V_DD

)

图6-10

I_IL

V_DD= 1.95 V; V_I= 0 V

V_DD= 1.95 V; V_I= 1.95 V

–100

I_IH

100

High–level input current

LPSDR OUTPUT⁽¹⁰⁾

English Data Sheet: DLPS124

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

DC output high voltage

DC output low voltage

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX UNIT

V_OH

V_OL

0.8 × V_DD

I_OH= –2 mA

I_OL= 2 mA

0.2 × V_DD

CAPACITANCE

Input capacitance LPSDR

ƒ= 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

ƒ= 1 MHz

C_OUT

ƒ= 1 MHz

C_RESET

Reset group capacitance

400

500

ƒ= 1 MHz; (768 × 344) micromirrors

(1) Device electrical characteristics are in Recommended Operating Conditions, unless otherwise noted.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta |V_DDI–V_DD| must be less than the specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than the specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SSconnections are also

required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

V/ns

t_r

Rise slew rate⁽¹⁾

Fall slew rate⁽¹⁾

Rise slew rate⁽²⁾

Fall slew rate⁽²⁾

(30% to 80%) × V_DD. See 图6-3.

(70% to 20%) × V_DD. See 图6-3.

(20% to 80%) × V_DD. See 图6-3.

(80% to 20%) × V_DD. See 图6-3.

t_ƒ

t_r

0.25

7.7

t_ƒ

t_c

Cycle time

LS_CLK,

8.3

See 图6-2.

t_W(H)

t_W(L)

Pulse duration

LS_CLK high

3.1

50% to 50% reference points. See 图6-2.

Pulse duration

LS_CLK low

t_su

1.5

Setup time

LS_WDATA valid before LS_CLK ↑. See 图6-2.

LS_WDATA valid after LS_CLK ↑. See 图6-2.

Setup time + Hold time, 图6-2

t _h

Hold time

t_WINDOW

Window time^{(1) (3)}

For each 0.25 V/ns reduction in slew rate below 1

V/ns. See 图6-5.

0.35

Window time

derating^{(1) (3)}

t_DERATING

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6.7 Timing Requirements (continued)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

SubLVDS

t_r

Rise slew rate

Fall slew rate

0.7

V/ns

20% to 80% reference points. See 图6-4.

80% to 20% reference points. See 图6-4.

See 图6-6.

t_ƒ

t_c

Cycle time DCLK

1.79

1.85

t_W(H)

Pulse duration

DCLK high

0.79

50% to 50% reference points. See 图6-6.

t_W(L)

Pulse duration

DCLK low

D(0:7) valid before

DCLK ↑or DCLK ↓. See 图6-6.

t_su

Setup time

D(0:7) valid after

DCLK ↑or DCLK ↓. See 图6-6.

t _h

Hold time

t_WINDOW

Window time

3.0

Setup time + Hold time. See 图6-6, 图6-7.

t_LVDS-

Power-up

receiver⁽⁴⁾

2000

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3.

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

w(L)

w(H)

LS_CLK

50%

LS_WDATA

50%

window

Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

图6-2. LPSDR Switching Parameters

English Data Sheet: DLPS124

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LS_CLK, LS_WDATA

DMD_DEN_ARSTZ

1.0 * VDD

0.8 * VDD

V_IH(AC)

V_IH(DC)

0.8 * VDD

0.7 * VDD

V_IL(DC)

V_IL(AC)

0.3 * VDD

0.2 * VDD

0.0 * VDD

t_r

t_f

t_r

t_f

图6-3. LPSDR Input Rise and Fall Slew Rate

图6-4. SubLVDS Input Rise and Fall Slew Rate

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V_{IH MIN}

LS_CLK Midpoint

V_{IL MAX}

t_SU

t_H

V_{IH MIN}

LS_WDATA Midpoint

V_{IL MAX}

t_WINDOW

V_{IH MIN}

Midpoint

LS_CLK

V_{IL MAX}

t_DERATING

t_H

t_SU

V_{IH MIN}

Midpoint

V_{IL MAX}

LS_WDATA

t_WINDOW

图6-5. Window Time Derating Concept

图6-6. SubLVDS Switching Parameters

English Data Sheet: DLPS124

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Note: Refer to High Speed Interface for details.

图6-7. High-Speed Training Scan Window

图6-8. SubLVDS Voltage Parameters

1.225V

= V

+ | 1/2 * V

ID max

SubLVDS max

CM max

= V

– | 1/2 * V

SubLVDS min

CM min

ID max

0.575V

图6-9. SubLVDS Waveform Parameters

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图6-10. SubLVDS Equivalent Input Circuit

Not to Scale

T+

Δ V

T-

LS_CLK

LS_WDATA

图6-11. LPSDR Input Hysteresis

LS_CLK

LS_WDATA

Stop Start

t_PD

LS_RDATA

Acknowledge

图6-12. LPSDR Read Out

Data Sheet Timing Reference Point

Device Pin

Tester Channel

Output Under Test

See Timing for more information.

图6-13. Test Load Circuit for Output Propagation Measurement

English Data Sheet: DLPS124

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6.8 Switching Characteristics

See⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output propagation, clock to Q, rising

edge of LS_CLK input to LS_RDATA

output (See 图6-12.)

t_PD

C_L= 45 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

(1) Device electrical characteristics are over Recommended Operation Conditions unless otherwise noted.

6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Maximum system mounting interface load to be applied to the:

•

Thermal Interface Area⁽¹⁾

Clamping and Electrical Interface Area⁽¹⁾

110

(1) Uniformly distributed within area shown in 图6-14.

Datum 'A' Areas

(3 Place)

Datum 'E' Area

(1 Place)

Thermal Interface Area

Electrical Interface Area

图6-14. System Interface Loads

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6.10 Micromirror Array Physical Characteristics

PARAMETER

VALUE

1368

768

UNIT

micromirrors

µm

See 图6-15 ⁽²⁾

See 图6-16.

Number of active columns

Number of active rows

Micromirror (pixel) pitch

5.4

Micromirror active array

width

7.387

Micromirror pitch × number of active columns; see 图6-15.

Micromirror active array

height

4.147

Micromirror pitch × number of active rows; see 图6-15.

Micromirror active border Pond of micromirror (POM)⁽¹⁾

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

(2) The fast switching speed of the DMD micromirrors combined with advanced DLP image processing algorithms enable each

micromirror to display two distinct pixels on the screen during every frame, resulting in a full 1920 × 1080 pixel image being displayed.

图6-15. Micromirror Array Physical Characteristics

图6-16. Mirror (Pixel) Pitch

English Data Sheet: DLPS124

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6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

DMD landed state⁽¹⁾

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

1.4

–1.4

Landed ON state

180

270

Micromirror tilt direction^{(6) (7)}

degree

µs

Landed OFF state

Typical performance

Micromirror crossover time⁽⁸⁾

Micromirror switching time⁽⁹⁾

Bright pixel(s) in active

area⁽¹¹⁾

Gray 10 Screen⁽¹²⁾

Bright pixel(s) in the POM⁽¹³⁾Gray 10 Screen⁽¹²⁾

Image

Dark pixel(s) in the active

White Screen

micromirrors

performance⁽¹⁰⁾

area⁽¹⁴⁾

Adjacent pixel(s)⁽¹⁵⁾

Any Screen

Unstable pixel(s) in active

area⁽¹⁶⁾

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state

direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

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图6-17. Landed Pixel Orientation and Tilt

English Data Sheet: DLPS124

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6.12 Window Characteristics

PARAMETER⁽¹⁾

MIN

NOM

Corning Eagle XG

1.5119

MAX UNIT

Window material

Window refractive index

Window aperture⁽²⁾

Illumination overfill⁽³⁾

at wavelength 546.1 nm

See⁽²⁾

See⁽³⁾

Window transmittance, single-pass

through both surfaces and glass

Minimum within the wavelength range

420 to 680 nm. Applies to all angles 0° to

30° AOI.

97%

Window Transmittance, single-pass

through both surfaces and glass

Average over the wavelength range 420

to 680 nm. Applies to all angles 30° to

45° AOI.

(1) See 节7.5 for more information.

(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(3) The active area of the DLP3310 device is surrounded by an aperture on the inside of the DMD window surface that masks structures

of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating

the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The

illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux

level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light

on the outside of the active array may cause system performance degradation.

6.13 Chipset Component Usage Specification

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

The DLP3310 is a component of one or more DLP® chipsets. Reliable function and operation of the DLP3310

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI

technology and devices for operating or controlling a DLP DMD.

6.14 Software Requirements

CAUTION

The DLP3310 DMD has mandatory software requirements. Refer to Software Requirements for TI

DLP^®Pico^™TRP Digital Micromirror Devices application report for additional information. Failure to

use the specified software will result in failure at power up.

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7 Detailed Description

7.1 Overview

The DLP3310 is a 0.33 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 1368

columns by 768 rows in a square grid pixel arrangement. The fast switching speed of the DMD micromirrors

combined with advanced DLP image processing algorithms enables each micromirror to display two distinct

pixels on the screen during every frame, resulting in a full 1920 x 1080 pixel image being displayed. The

electrical interface is Sub Low Voltage Differential Signaling (SubLVDS) data.

The DLP3310 is part of the chipset composed of the DLP3310 DMD, DLPC3437 controller, and DLPA3000/

DLPA3005 PMIC/LED driver. To ensure reliable operation, the DLP3310 DMD must always be used with the

DLPC3437 controller and the DLPA3000/DLPA3005 PMIC/LED drivers.

7.2 Functional Block Diagram

A. Details omitted for clarity.

English Data Sheet: DLPS124

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7.3 Feature Description

7.3.1 Power Interface

The power management IC DLPA3000/DLPA3005 contains three regulated DC supplies for the DMD reset

circuitry: V_BIAS, V_RESET, and V_OFFSET, as well as the two regulated DC supplies for the DLPC3437 controller.

7.3.2 Low-Speed Interface

The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is

the low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface is composed of

differential SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-13 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers should use IBIS or

other simulation tools to correlate the timing reference load to a system environment. The load capacitance

value stated is only for characterization and measurement of AC timing signals. This load capacitance value

does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC3437 controller. For more information, see the DLPC3437

DLPC3437 Display Controller Data Sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border and/or active area could occur.

7.5.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display’s border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

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7.5.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately

10% of the average flux level in the active area. Depending on the particular system’s optical architecture,

overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

图7-1. DMD Thermal Test Points

English Data Sheet: DLPS124

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Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from

measurement points on the outside of the package, the package thermal resistance, the electrical power, and

the illumination heat load. The relationship between array temperature and the reference ceramic temperature

(thermal test TP1 in 图7-1) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

•

T_ARRAY= Computed array temperature (°C)

T_CERAMIC= Measured ceramic temperature (°C) (TP1 location)

R_{ARRAY-TO-CERAMIC}= Thermal resistance of package specified in Thermal Information from array to ceramic TP1 (°C/

Watt)

•

Q_ARRAY= Total DMD power on the array (W) (electrical + absorbed)

Q_ELECTRICAL= Nominal electrical power (W)

Q_INCIDENT= Incident illumination optical power (W)

Q_ILLUMINATION= (DMD average thermal absorptivity × Q_INCIDENT) (W)

DMD average thermal absorptivity = 0.4

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.16 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD

system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.

The sample calculation for a typical projection application is as follows:

Q_INCIDENT= 5.9 W (measured)

T_CERAMIC= 52.0°C (measured)

Q_ELECTRICAL= 0.16 W

Q_ARRAY= 0.16 W + (0.40 × 5.9 W) = 2.52 W

T_ARRAY= 52.0°C + (2.52 W × 6.0°C/W) = 67.1°C

7.7 Micromirror Power Density Calculation

The calculation of the optical power density of the illumination on the DMD in the different wavelength bands

uses the total measured optical power on the DMD, percent illumination overfill, area of the active array, and

ratio of the spectrum in the wavelength band of interest to the total spectral optical power.

• ILL_UV= [OP_UV-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_VIS= [OP_VIS-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• ILL_IR= [OP_IR-RATIO× Q_INCIDENT] × 1000 ÷ A_ILL(mW/cm²)

• ILL_BLU= [OP_BLU-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

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• ILL_BLU1= [OP_BLU1-RATIO× Q_INCIDENT] ÷ A_ILL(W/cm²)

• A_ILL= A_ARRAY÷ (1 - OV_ILL) (cm²)

where:

• ILL_UV= UV illumination power density on the DMD (mW/cm²)

• ILL_VIS= VIS illumination power density on the DMD (W/cm²)

• ILL_IR= IR illumination power density on the DMD (mW/cm²)

• ILL_BLU= BLU illumination power density on the DMD (W/cm²)

• ILL_BLU1= BLU1 illumination power density on the DMD (W/cm²)

• A_ILL= illumination area on the DMD (cm²)

• Q_INCIDENT= total incident optical power on DMD (W) (measured)

• A_ARRAY= area of the array (cm ²) (data sheet)

• OV_ILL= percent of total illumination on the DMD outside the array (%) (optical model)

• OP_UV-RATIO= ratio of the optical power for wavelengths <410 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_VIS-RATIO= ratio of the optical power for wavelengths ≥410 and ≤800 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_IR-RATIO= ratio of the optical power for wavelengths >800 nm to the total optical power in the illumination

spectrum (spectral measurement)

• OP_BLU-RATIO= ratio of the optical power for wavelengths ≥410 and ≤475 nm to the total optical power in the

illumination spectrum (spectral measurement)

• OP_BLU1-RATIO= ratio of the optical power for wavelengths ≥410 and ≤445 nm to the total optical power in the

illumination spectrum (spectral measurement)

The illumination area varies and depends on the illumination overfill. The total illumination area on the DMD is

the array area and overfill area around the array. The optical model is used to determine the percent of the total

illumination on the DMD that is outside the array (OV_ILL) and the percent of the total illumination that is on the

active array. From these values the illumination area (A_ILL) is calculated. The illumination is assumed to be

uniform across the entire array.

From the measured illumination spectrum, the ratio of the optical power in the wavelength bands of interest to

the total optical power is calculated.

Sample calculation:

Q_INCIDENT= 5.9 W (measured)

A_ARRAY= (0.73872 × 0.41472) = 0.3064 cm²(data sheet)

OV_ILL= 16.3% (optical model)

OP_UV-RATIO= 0.00021 (spectral measurement)

OP_VIS-RATIO= 0.99977 (spectral measurement)

OP_IR-RATIO= 0.00002 (spectral measurement)

OP_BLU-RATIO= 0.28100 (spectral measurement)

English Data Sheet: DLPS124

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OP_BLU1-RATIO= 0.03200 (spectral measurement)

A_ILL= 0.3064 ÷ (1 - 0.163) = 0.3660 cm²

ILL_UV= [0.00021 × 5.90W] × 1000 ÷ 0.3660 cm²= 3.385 mW/cm²

ILL_VIS= [0.99977 × 5.90W] ÷ 0.3660 cm²= 16.12 W/cm²

ILL_IR= [0.00002 × 5.90W] × 1000 ÷ 0.3660 cm²= 0.322 mW/cm²

ILL_BLU= [0.28100 × 5.90W] ÷ 0.3660 cm²= 4.53 W/cm²

ILL_BLU1= [0.03200 × 5.90W] ÷ 0.3660 cm²= 0.52 W/cm²

7.8 Micromirror Landed-On/Landed-Off Duty Cycle

7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the

time and in the OFF state 25% of the time, whereas 25/75 would indicate that the pixel is in the ON state 25% of

the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

nominally add to 100.

7.8.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric

landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

It is the symmetry and asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty

cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty

cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.

7.8.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a given long-term average Landed Duty Cycle.

7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the nominal landed duty cycle of a given pixel is determined by the image content

being displayed by that pixel.

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For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience very close to a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-

black, the pixel will experience very close to a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value

and Landed Duty Cycle

Grayscale

Value

Nominal Landed

Duty Cycle

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +

(Blue_Cycle_%×Blue_Scale_Value)

(1)

where

Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that Red,

Green, and Blue are displayed (respectively) to achieve the desired white point.

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

blue color intensities would be as shown in 表7-2.

表7-2. Example Landed Duty Cycle for Full-Color

Pixels

Red Cycle

Percentage

Green Cycle

Percentage

Blue Cycle

Percentage

50%

20%

30%

Nominal

Landed Duty

Cycle

Red Scale

Value

Green Scale

Blue Scale

Value

100%

0/100

50/50

20/80

30/70

100%

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Nominal

Landed Duty

Cycle

Red Scale

Value

Green Scale

Value

Blue Scale

Value

12%

35%

6/94

7/93

60%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

12%

35%

60%

100%

12%

100%

The last factor to account for in estimating the Landed Duty Cycle is any applied image processing. Within the

DLP Controller DLPC3437, the two functions which affect Landed Duty Cycle are Gamma and IntelliBright^™.

Gamma is a power function of the form Output_Level = A × Input_Level^Gamma, where A is a scaling factor that is

typically set to 1.

In the DLPC3430/DLPC3435 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis.

A typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.

100

Gamma = 2.2

Input Level (%)

90 100

D002

图7-2. Example of Gamma = 2.2

From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale

value will be 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact

displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.

The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)

also apply transform functions on the gray scale level of each pixel.

But while the amount of gamma applied to every pixel (of every frame) is constant (the exponent, gamma, is

constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or

compression to every pixel of every frame.

Consideration must also be given to any image processing which occurs before the DLPC3437 controller.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the dual DLPC3437

controllers. The new high tilt pixel in the side-illuminated DMD increases brightness performance and enables a

smaller system footprint for thickness constrained applications. Applications of interest include projection

embedded in display devices like battery powered mobile accessory full HD projectors, battery powered smart

full HD projectors, digital signage, interactive surface projection, low latency gaming displays, interactive

displays, and wearable displays.

DMD power-up and power-down sequencing is strictly controlled by the DLPA3000/DLPA3005. Refer to 节 9 for

power-up and power-down specifications. To ensure reliable operation, the DLP3310 DMD must always be used

with two DLPC3437 controllers and a DLPA3000/DLPA3005 PMIC/LED driver.

8.2 Typical Application

A common application when using a DLP3310 DMD and two DLPC3437s is for creating a pico-projector that can

be used as an accessory to a smartphone, tablet or a laptop. The two DLPC3437s in the pico-projector receive

images from the XC7Z020-1CLG484I4493 FPGA, which receives images from a multimedia front end within the

product as shown in 图8-1.

English Data Sheet: DLPS124

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SYSPWR

LED

PROJ_ON

GPIO_8

I2C_0

SPI1

I C

DLPA300x

RESETZ

PARKZ

LIM

HOST_IRQ

SPI (4)

1.8 V

SPI0

VDDLP12

VDD

Illumination

optics

DLPC3437

OFFSET

Parallel

BIAS

RESET

ACT_SYNC

FPGA_RDY

Parallel

(28)

VCC_18

VCC_INTF

VCC_FLSH

1.8 V

CTRL

Sub-LVDS

I2C_1

1.8 V

I2C_0

DMD

FPGA

XC7Z020-

FPD-Link

I2C_0

1CLG484I4493

I2C_1

CTRL

VCC_18

VCC_INTF

RESETZ

Sub-LVDS

VCC_FLSH

Parallel

SPI

DLPC3437

SPI0

DAC_Data

DAC_CLK

Actuator

Drive

Circuit

RESETZ

PARKZ

SPI (4)

VDDLP12

VDD

图8-1. Typical Application Diagram

8.2.1 Design Requirements

A pico-projector is created by using a DLP chip set comprised a DLP3310 DMD, two DLPC3437 controllers, a

XC7Z020-1CLG484I4493 FPGA, and a DLPA3000/DLPA3005 PMIC/LED driver. The XC7Z020-1CLG484I4493

FPGA and DLPC3437 controllers do the digital image processing, the DLPA3000/DLPA3005 provides the

needed analog functions for the projector, and the DLP3310 DMD is the display device for producing the

projected image.

In addition to the three DLP chips in the chip set, other chips are needed. At a minimum a Flash part is needed

to store the software and firmware to control the XC7Z020-1CLG484I4493 FPGA, and each of the DLPC3437

controllers.

The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often

contained in three separate packages, but sometimes more than one color of LED die may be in the same

package to reduce the overall size of the pico-projector.

For connecting the XC7Z020-1CLG484I4493 FPGA to the multimedia front end for receiving images, either a 24-

bit parallel interface can be used, or the dual FPD-Link interface can be used. An I²C interface should be

connected from the multimedia front end for sending commands to one of the DLPC3437 controllers for

configuring the chipset for different features.

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8.2.2 Detailed Design Procedure

For connecting together the XC7Z020-1CLG484I4493 FPGA, the two DLPC3437 controllers, the DLPA3000/

DLPA3005, and the DLP3310 DMD, see the reference design schematic. When a circuit board layout is created

from this schematic a very small circuit board is possible. An example small board layout is included in the

reference design data base. Layout guidelines should be followed to achieve a reliable projector.

The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical

OEM who specializes in designing optics for DLP projectors.

8.2.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is as shown in 图 8-2. For the LED currents shown, it’s assumed

that the same current amplitude is applied to the red, green, and blue LEDs.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.5

1.5

2.5

3.5

LED CURRENT (A)

4.5

5.5

D001

图8-2. Luminance vs Current

English Data Sheet: DLPS124

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All

V_SSconnections are also required. DMD power-up and power-down sequencing is strictly controlled by the

DLPA3000/DLPA3005 devices.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability.

V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESETpower supplies have to be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the DMD’s reliability and lifetime. Refer to 图9-2. V_SSmust also be connected.

9.1 Power Supply Power-Up Procedure

• During power-up, V_DDand V_DDImust always start and settle before V_OFFSET, V_BIAS, and V_RESETvoltages are

applied to the DMD.

• During power-up, it is a strict requirement that the delta between V_BIASand V_OFFSETmust be within the

specified limit shown in Recommended Operating Conditions. Refer to 表9-1 and the Layout Example for

power-up delay requirements.

• During power-up, the DMD’s LPSDR input pins shall not be driven high until after V_DDand V_DDIhave settled

at operating voltage.

• During power-up, there is no requirement for the relative timing of V_RESETwith respect to V_OFFSETand V_BIAS

Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 图9-1.

9.2 Power Supply Power-Down Procedure

• Power-down sequence is the reverse order of the previous power-up sequence. V_DDand V_DDImust be

supplied until after V_BIAS, V_RESET, and V_OFFSETare discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving V_BIASprior to V_OFFSET, but it is a strict requirement that

the delta between V_BIASand V_OFFSETmust be within the specified limit shown in Recommended Operating

Conditions (Refer to Note 2 for 图9-1).

• During power-down, the DMD’s LPSDR input pins must be less than V_DDI, the specified limit shown in

Recommended Operating Conditions.

• During power-down, there is no requirement for the relative timing of V_RESETwith respect to V_OFFSETand

V_BIAS

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 图9-1.

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9.3 Power Supply Sequencing Requirements

A. Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than specified in Recommended Operating

Conditions. OEMs may find that the most reliable way to ensure this is to power V_OFFSETprior to V_BIASduring power-up and to remove

V_BIASprior to V_OFFSETduring power-down. Refer to 表9-1 and 图9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |V_BIAS–V_RESET| must be less than specified limit shown in 节6.4.

D. When system power is interrupted, the DLPA3000/DLPA3005 initiates hardware power-down that disables V_BIAS, V_RESETand V_OFFSET

after the Micromirror Park Sequence.

E. Drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

表9-1. Power-Up Sequence Delay Requirement

PARAMETER

MIN

MAX UNIT

t_DELAY

Delay requirement from V_OFFSETpower up to V_BIASpower up

Supply voltage level at beginning of power–up sequence delay (see 图9-2)

V_OFFSET

English Data Sheet: DLPS124

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表9-1. Power-Up Sequence Delay Requirement (continued)

PARAMETER

MIN

MAX UNIT

V_BIAS

Supply voltage level at end of power–up sequence delay (see 图9-2)

12 V

VOFFSET

8 V

VDD ≤ VOFFSET < 6 V

4 V

VSS

0 V

t_DELAY

20 V

16 V

12 V

8 V

VBIAS

VDD ≤ VBIAS < 6 V

4 V

VSS

0 V

Refer to 表9-1 for V_OFFSETand V_BIASsupply voltage levels during power-up sequence delay.

图9-2. Power-Up Sequence Delay Requirement

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10 Layout

10.1 Layout Guidelines

The DLP3310 DMD is connected to a PCB or a Flex circuit using an interposer. For additional layout guidelines

regarding length matching, impedance, etc. see the DLPC3437 controller datasheet. For a detailed layout

example refer to the layout design files. Some layout guidelines for routing to the DLP3310 DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals. Refer to 图10-1.

• Minimum of two 220-nF (35 V) capacitors - one close to V_BIASpin. Capacitors C10 and C14 in 图10-1.

• Minimum of two 220-nF (35 V) capacitors - one close to each V_RSTpin. Capacitors C11 and C13 in 图10-1.

• Minimum of two 220-nF (35 V) capacitors - one close to each V_OFSpin. Capacitors C4 and C12 in 图10-1.

• Minimum of four 220-nF (10 V) capacitors - two close to each side of the DMD. Capacitors C1, C3, C2, and

C5 in 图10-1.

10.2 Layout Example

图10-1. Power Supply Connections

English Data Sheet: DLPS124

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP3310A FQM

Package Type

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking includes the legible character string GHJJJJK DLP3310AFQM. GHJJJJK is the lot trace

code. DLP3310AFQM is the device marking.

Two-dimension matrix code

DMD part number and lot

trace code

Lot Trace Code

GHJJJJK

DLP3310AFQM

Part Marking

图11-2. DMD Marking

11.3 Documentation Support

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

Pico^™and TI E2E^™are trademarks of Texas Instruments.

IntelliBright^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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11.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: DLPS124

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP3310AFQM

ACTIVE

CLGA

FQM

100

RoHS & Green

NI/AU

N / A for Pkg Type

0 to 70

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jul-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

DLP3310AFQM

FQM

CLGA

100

10 x 10

150

315 135.9 12190

31.5

16.2

Pack Materials-Page 1

DWG NO.

2512400

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

ECO 2156795: INITIAL RELEASE

ECO 2157307: UPDATE SUBSTRATE THICKNESS

TOLERANCE & SYMBOLIZATION PAD SIZE/SHAPE

ECO 2159285: CORRECT SUBSTRATE BACK SIDE MARKING

IN VIEW H-H (SH. 3) FROM "465" TO "888"

DATE

BMH

3/8/2016

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

4/1/2016

BMH

2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

7/7/2016

BMH

PPC

4/14/2020

ECO: 2187058: ADD APERTURE SLOTS PICTORIALLY

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,

AS SHOWN IN SECTION A-A.

ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

1.176B0.05

0.2

0.1

2.35

0.2

0.1

3.6

(ILLUMINATION

DIRECTION)

1.25

90 B1

2.5B0.075

0.3

0.1

4X R0.4B0.1

7.2

P2.5

FRONT SIDE INDEX MARK

4X (R0.2)

0.2

0.1

17.45B0.08

0.8

0.3

0.1

19.25

(OFF-STATE

DIRECTION)

5 6

2X ENCAPSULANT

1.1B0.05

1.403B0.077

(2.183)

3 SURFACES INDICATED

IN VIEW B (SHEET 2)

1 8

0.038A

0.02D

0.78B0.063

(2.5)

ACTIVE ARRAY

1.6B0.16

(SHEET 3)

(1.6)

0.4 MIN TYP

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TOLERANCES:

TEXAS

0 MIN TYP

3/8/2016

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

Dallas Texas

3/8/2016

ANGLES B1`

TITLE

ICD, MECHANICAL, DMD,

.33 1080p SERIES 315

(FQM PACKAGE)

SECTION A-A

2 PLACE DECIMALS B0.25

1 PLACE DECIMALS B0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

3/8/2016

3/10/2016

3/8/2016

3/10/2016

P. KONRAD

(ROTATED 90)

SCALE 20 : 1

S. SUSI

REV

THIRD ANGLE

PROJECTION

DWG NO

^SD^IZE

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

M. DORAK

APPROVED

2512400

NEXT ASSY

SHEET

SCALE

APPLICATION

E. CARPENTER

20:1

INV11-2006a

DWG NO.

2512400

2X (1.4)

2X 16.85

2X 1.376

2X (1)

4X 1.6

1.25

P2.5

4X (2)

(1.1)

VIEW B

DATUMS A, B, C, AND E

(FROM SHEET 1)

16.85

1.376

3.7

1.25

7.4

P2.5

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

2X 0 MIN

VIEW D

REV

DWG NO

SIZE

DATE

3/8/2016

DRAWN

TEXAS

2512400

B. HASKETT

ENCAPSULANT MAXIMUM HEIGHT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

DWG NO.

2512400

4X (0.108)

(7.3872)

ACTIVE ARRAY

5.98B0.075

0.312B0.0635

1.211B0.05

(6.69)

WINDOW

2.134B0.075

1.25

(ILLUMINATION

DIRECTION)

(4.1472)

ACTIVE ARRAY

(4.904)

APERTURE

P2.5

5.479B0.05

4.592B0.0635

0.448B0.0635

7.614B0.0635

(8.062)

APERTURE

(OFF-STATE

DIRECTION)

2.491B0.05

9.655B0.05

(12.146) WINDOW

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

22 X 0.7424 = 16.3328

1.364

7X CIRCULAR TEST PADS

(0.52)

(17) (18) 19

(1)

(8)

(42)

TYP.

(42)

TYP.

(0.15) TYP.

(0.075) TYP.

2.5984

7 X 0.7424

= 5.1968

(4.64)

P2.5

1.25

(0.068) TYP.

(42)

TYP.

DETAIL G

APERTURE RIGHT EDGE

DETAIL F

APERTURE LEFT EDGE

(7)

SYMBOLIZATION PAD

92X SQUARE LGA PADS

0.520.05 X 0.520.05

SCALE 60 : 1

VIEW H-H

0.2ABC

0.1A

BACK SIDE METALLIZATION

(FROM SHEET 1)

REV

DWG NO

SIZE

DATE

3/8/2016

DRAWN

TEXAS

2512400

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

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