DLP5530AFYKQ1 [TI]

适用于内部显示应用的 DLP® 汽车 0.55" 数字微镜器件 (DMD) | FYK | 149 | -40 to 105;


型号：	DLP5530AFYKQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于内部显示应用的 DLP® 汽车 0.55" 数字微镜器件 (DMD) \| FYK \| 149 \| -40 to 105
文件：	总44页 (文件大小：1027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

适用于汽车内部显示的 DLP5530-Q1 0.55 英寸 130 万像素 DMD

1 特性

3 说明

•

符合汽车类应用要求

DMD 阵列工作温度范围 -40°C 至 105°C

DLP5530-Q1 汽车芯片组包括：

DLP5530-Q1 汽车 DMD 与 DLPC230-Q1 DMD 控制

器、TPS99000-Q1 系统管理和照明控制器结合使用，

能够实现高性能增强现实 HUD。采用 2:1 宽高比，支

持超宽宽高比设计；具有 130 万像素分辨率，可在

HUD 应用中实现视网膜受限显示。DLP5530-Q1 的光

通量是前代 DLP3030-Q1 汽车 DMD 的 3 倍以上，能

够获得更宽广的视场和更大的驾驶员眼动范围，增强用

户的使用体验。该芯片组耦合了 LED 和光学系统，能

够获得更饱满的 125% NTSC 色彩、超过

15,000cd/m²的超高亮度、超过 5000:1 的高动态调光

比以及太阳能高负载容差。DLP5530-Q1 汽车 DMD

微镜阵列针对底部照明而配置，可实现更高效率以及更

紧凑的光学引擎设计。S450 封装针对 DMD 阵列而言

具有低热阻的特点，可获得更高效的热解决方案。

–

•

–

DLP5530-Q1 DMD

DLPC230-Q1 DMD 控制器

系统管理和照明控制器

•

0.55 英寸对角线微镜阵列

–

7.6μm 微镜间距

±12° 微镜倾斜角（相对于平面）

底部照明，实现最优的效率和光学引擎尺寸

支持 1152 × 576 输入分辨率

与 LED 或激光照明兼容

•

600MHz sub-LVDS DMD 接口，可实现低功耗和低

排放

•

温度极值下 DMD 刷新率为 10kHz

DMD 存储器单元的内置自检

”

器件信息⁽¹⁾⁽²⁾

封装

器件型号

DLP5530-Q1

封装尺寸（标称值）

2 应用

FYK (149)

22.30mm × 32.20mm

•

宽视场和增强现实平视显示 (HUD)

波导和全息薄膜显示

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 本数据表包含了有关此 DMD 在平视显示应用中的规格以及应

用。请参阅 DLP5531-Q1 数据表 (DLPS075)，了解有关前照灯

规格和应用的信息。

DLP5530-Q1 DLP^®芯片组系统方框图

Control &

Monitor

TPS99000-Q1

Power

Regulation

VBATT

PROJ_ON

1.1V

Power sequencing

and monitoring

1.8V

3.3V

6.5V

Reset &

Power Good

External

Monitor

SPI

System Diagnostics:

external watchdogs,

over brightness, and

other monitors

DLPC230-Q1

I²

Host

SPI

6.5V

SPI

Internal

Control

Ultra wide

dimming LED

Controller

2-TIA, 12bit ADC

DAC, FET Drive, ...

LED

drive

HOST

IRQ

LED

Control

Illumination

Control

& feedback

MPU

FET

Drive

DMD Power

Regulation

OpenLDI

Image Scaling &

Bezel

adjustment

24-bit RGB

& Syncs

GPIO

(configurable)

Photodiode

DMD Power

eSRAM

frame buffer

Sub-LVDS

TMP411

Flash

SPI

I²

DLP5530-Q1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS073

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

7.4 System Optical Considerations............................... 26

7.5 DMD Image Performance Specification.................. 28

7.6 Micromirror Array Temperature Calculation............ 28

7.7 Micromirror Landed-On/Landed-Off Duty Cycle .... 30

Application and Implementation ........................ 31

8.1 Application Information............................................ 31

8.2 Typical Application .................................................. 31

Power Supply Recommendations...................... 34

9.1 Power Supply Power-Up Procedure ....................... 34

9.2 Power Supply Power-Down Procedure................... 34

9.3 Power Supply Sequencing Requirements .............. 35

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 8

6.1 Absolute Maximum Ratings ..................................... 8

6.2 Storage Conditions.................................................... 8

6.3 ESD Ratings.............................................................. 8

6.4 Recommended Operating Conditions....................... 9

6.5 Thermal Information................................................ 11

6.6 Electrical Characteristics......................................... 11

6.7 Timing Requirements.............................................. 12

6.8 Switching Characteristics ....................................... 16

6.9 System Mounting Interface Loads .......................... 17

6.10 Physical Characteristics of the Micromirror Array. 18

6.11 Micromirror Array Optical Characteristics ............. 20

6.12 Window Characteristics......................................... 20

6.13 Chipset Component Usage Specification ............. 21

Detailed Description ............................................ 22

7.1 Overview ................................................................. 22

7.2 Functional Block Diagram ....................................... 23

7.3 Feature Description................................................. 24

10 Layout................................................................... 36

10.1 Layout Guidelines ................................................. 36

11 器件和文档支持 ..................................................... 37

11.1 器件支持................................................................ 37

11.2 相关链接................................................................ 37

11.3 社区资源................................................................ 38

11.4 商标....................................................................... 38

11.5 静电放电警告......................................................... 38

11.6 DMD 处理.............................................................. 38

11.7 Glossary................................................................ 38

12 机械、封装和可订购信息....................................... 38

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (September 2018) to Revision F

Page

•

Added illumination overfill maximum to Recommended Operating Conditions ..................................................................... 9

Changed ILL_OVERFILLfrom total power (mW) to power density (mW/mm²) in Recommended Operating Conditions ............. 9

Added pulse duration LS_CLK high to Timing Requirements.............................................................................................. 12

Added pulse duration LS_CLK low to Timing Requirements ............................................................................................... 12

Added LPSDR setup time to Timing Requirements ............................................................................................................. 12

Added LPSDR hold time to Timing Requirements ............................................................................................................... 12

Deleted illumination overfill maximum from Window Characteristics ................................................................................... 20

Changes from Revision D (June 2018) to Revision E

Page

•

Changed I_IHfrom 100 nA : to 300 nA ................................................................................................................................... 12

Changed t_WINDOWto be a minimum rather than a maximum ................................................................................................ 12

Changes from Revision C (March 2018) to Revision D

Page

•

已更改将器件状态从“产品预览”更改为“生产数据”.................................................................................................................. 1

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

5 Pin Configuration and Functions

FYK Package

149-Pin CPGA

Bottom View

Pin Functions – Connector Pins

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

DATA INPUTS

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AP(0)

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

D_BP(0)

D_BP(1)

SubLVDS

Double

Data, Negative

Data, Positive

Data, Negative

Data, Positive

K19

J19

H19

G19

E19

D19

C19

B19

K20

J20

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

Pin Functions – Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

H20

G20

E20

D20

C20

B20

D_BP(2)

SubLVDS

Double

Single

Data, Positive

Clock, Negative

Clock, Positive

Clock, Negative

Clock, Positive

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

LS_CLKN

LS_CLKP

LS_WDATAN

LS_WDATAP

CONTROL INPUTS

F19

F20

Clock for Low Speed Interface, Negative

Clock for Low Speed Interface, Positive

Write Data for Low Speed Interface, Negative

Write Data for Low Speed Interface, Positive

Single

Asynchronous Reset Active Low. Logic High

Enables DMD.

DMD_DEN_ARSTZ

T10

LPSDR

LS_RDATA_A

LS_RDATA_B

LPSDR

Single

Read Data for Low Speed Interface

TEMPERATURE SENSE DIODE

TEMP_N

TEMP_P

Calibrated temperature diode used to assist

accurate temperature measurements of DMD

die.

RESERVED PINS

VCCH

Ground

VCCH

A10

Reserved Pin. Connect to Ground.

VCCH

B10

A11

A12

A13

B11

B12

B13

VSSH

Reserved Pin. Connect to Ground.

VSSH

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

Pin Functions – Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

POWER

VBIAS

VOFFSET

VRESET

VDD

NO.

T15

Power

Supply voltage for positive bias level at

micromirrors.

T13

Supply voltage for High Voltage CMOS core

logic. Supply voltage for offset level at

micromirrors

A16

B16

Supply voltage for negative reset level at

micromirrors.

T14

VDD

R10

R11

R20

VDD

M20

VDD

Supply voltage for Low Voltage CMOS core

logic; for LPSDR inputs; for normal high level at

micromirror address electrodes.

VDD

K18

VDD

G18

VDD

D18

VDD

A18

VDDI

L18

VDDI

Supply voltage for SubLVDS receivers.

VDDI

H18

VDDI

E18

VDDI

B18

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

Pin Functions – Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

VSS

NO.

Ground

T16

T19

T20

R13

R14

R15

P20

N19

N20

Common return. Ground for all power.

L19

L20

J18

F18

C18

B15

B17

A15

A17

A19

A20

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

Pin Functions – Test Pads

NUMBER

SYSTEM BOARD

Do not connect

T11

T12

T17

T18

R12

R16

R17

R18

R19

P18

P19

N18

M18

M19

B14

A14

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

(1)

see

MIN

MAX

UNIT

SUPPLY VOLTAGE

Supply voltage for LVCMOS core logic⁽²⁾

VDD

–0.5

2.3

Supply voltage for LPSDR low speed interface

Supply voltage for SubLVDS receivers⁽²⁾

Supply voltage for HVCMOS and micromirror electrode⁽²⁾⁽³⁾

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

VDDI

–0.5

–11

2.3

8.75

VOFFSET

VBIAS

VRESET

0.5

0.3

8.75

| VDDI–VDD |

| VBIAS–VOFFSET |

| VBIAS–VRESET |

INPUT VOLTAGE

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

Input voltage for other inputs LPSDR⁽²⁾

Input voltage for other inputs SubLVDS⁽²⁾⁽⁷⁾

INPUT PINS

–0.5

VDD + 0.5

VDDI + 0.5

| V_ID

I_ID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

810

SubLVDS input differential current

CLOCK FREQUENCY

ƒ_clock

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

130

620

MHz

ƒ_clock

ENVIRONMENTAL

Operating DMD array temperature

T_ARRAY

–40

105

°C

(Monitored by TMP411 via DLPC230-Q1)⁽⁸⁾

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage to the internal termination resistors may result.

(8) See Micromirror Array Temperature Calculation section.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

T_stg

DMD storage temperature (Reference location TP1 in Figure 19)

–40

125

°C

6.3 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), Corner Pins, per JESD22-C101⁽²⁾

Charged-device model (CDM), All Other Pins, per JESD22-C101⁽²⁾

Electrostatic

V_(ESD)

discharge

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽³⁾

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

VDD

1.7

1.8

1.95

VDDI

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode⁽⁴⁾

Supply voltage for mirror electrode

1.7

8.25

15.5

–9.5

1.8

8.5

1.95

8.75

16.5

–10.5

0.3

VOFFSET

VBIAS

VRESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

–10

| VDDI–VDD |

| VBIAS–VOFFSET |

CLOCK FREQUENCY

ƒ_clock

8.75

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK⁽⁷⁾

Duty cycle distortion DCLK

120

600

MHz

ƒ_clock

44%

150

56%

SUBLVDS INTERFACE⁽⁷⁾

SubLVDS input differential voltage (absolute value,

see Figure 6, Figure 7)

| V_ID

V_CM

250

900

350

Common mode voltage (see Figure 6, Figure 7)

SubLVDS voltage (see Figure 6, Figure 7)

700

575

1100

1225

110

V_SUBLVDS

Z_LINE

Line differential impedance (PWB/trace)

100

Z_IN

Internal differential termination resistance (see Figure 8)

120

TEMPERATURE DIODE

I_{TEMP_DIODE}

Max current source into Temperature Diode⁽⁸⁾

120

µA

ENVIRONMENTAL

T_ARRAY

Operating DMD array temperature^(9)(10)(11)

Illumination, wavelength < 395 nm⁽¹⁰⁾

–40

105

°C

mW/cm²

ILL_UV

Illumination overfill maximum

T_ARRAY<= 75°C

ILL_OVERFILL

40 mW/mm²

29 mW/mm²

heat load per side.^(12)(13)

Illumination overfill maximum

T_ARRAY> 75°C

heat load per side.^(12)(13)

(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections

are also required.

(2) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(3) All voltage values are with respect to the ground pins (VSS).

(4) VOFFSET supply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(7) Refer to the SubLVDS timing requirements in Timing Requirements.

(8) Temperature Diode is to allow accurate measurement of the DMD array temperature during operation.

(9) DMD Active Array temperature can be calculated using the TMP411 and DLPC230-Q1 as shown in the Micromirror Array Temperature

Calculation section.

(10) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.

(11) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.

(12) The active area of the DLP5530-Q1 device is surrounded by an aperture on the inside of the DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light

illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the

DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the

particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause

system performance degradation.

(13) Applies to the two regions in Figure 1.

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

Limited illumination area

on window aperture

Window

Aperture

Array

Window

0.5 mm

Window Aperture

0.5 mm

Figure 1. Illumination Overfill Diagram

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

6.5 Thermal Information

DLP5530-Q1

THERMAL METRIC⁽¹⁾

Active area-to-test point 1 (TP1)⁽¹⁾

FYK (CPGA)

149 PINS

1.1

UNIT

Thermal resistance

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the

window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling

outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP⁽³⁾

MAX

369

UNIT

CURRENT

VDD = 1.95 V

I_DD

Supply current: VDD⁽⁴⁾⁽⁵⁾

Supply current: VDDI⁽⁴⁾⁽⁵⁾

Supply current: VOFFSET⁽⁶⁾

Supply current: VBIAS⁽⁶⁾

Supply current: VRESET

VDD = 1.8 V

VDDI = 1.95 V

VDD = 1.8 V

I_DDI

VOFFSET = 8.75 V

VOFFSET = 8.5 V

VBIAS = 16.5 V

VBIAS = 16 V

16.1

1.3

I_OFFSET

I_BIAS

VRESET = –10.5 V

VRESET = –10 V

–10.2

I_RESET

POWER⁽⁷⁾

P_DD

VDD = 1.95 V

720

121

141

Supply power dissipation: VDD⁽⁴⁾⁽⁵⁾

Supply power dissipation: VDDI⁽⁴⁾⁽⁵⁾

Supply power dissipation: VOFFSET⁽⁶⁾

Supply power dissipation: VBIAS⁽⁶⁾

VDD = 1.8 V

VDDI = 1.95 V

VDD = 1.8 V

P_DDI

VOFFSET = 8.75 V

VOFFSET = 8.5 V

VBIAS = 16.5 V

VBIAS = 16 V

P_OFFSET

P_BIAS

VRESET = –10.5 V

VRESET = –10 V

108

1110

P_RESET

P_TOTAL

Supply power dissipation: VRESET

Supply power dissipation: Total

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) Typical current consumption is application and video content dependent. Please see a TI applications engineer for additional

information.

(4) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.

(5) Supply power dissipation based on non–compressed commands and data.

(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(7) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are

also required.

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP⁽³⁾

MAX

UNIT

LPSDR INPUT⁽⁸⁾

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽⁹⁾

DC input low voltage⁽⁹⁾

AC input high voltage⁽⁹⁾

AC input low voltage

0.7 × VDD

–0.3

VDD + 0.3

0.3 × VDD

VDD + 0.3

0.2 × VDD

0.4 × VDD

0.8 × VDD

–0.3

Hysteresis (V_T+– V_T–

)

Figure 9

0.1 × VDD

–100

I_IL

Low–level input current

VDD = 1.95 V; V_I= 0 V

VDD = 1.95 V; V_I= 1.95 V

I_IH

High–level input current

300

LPSDR OUTPUT⁽¹⁰⁾

V_OH

V_OL

DC output high voltage

DC output low voltage

I_OH= –2 mA

I_OL= 2 mA

0.8 × VDD

0.2 × VDD

CAPACITANCE

Input capacitance LPSDR

ƒ = 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

C_OUT

ƒ = 1 MHz; (1152 × 144)

micromirrors

C_RESET

C_TEMP

Reset group capacitance

350

400

450

Temperature sense diode capacitance

ƒ = 1 MHz

(8) LPSDR input specifications are for pin DMD_DEN_ARSTZ.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN NOM

MAX UNIT

LPSDR

t_r

Rise slew rate⁽¹⁾

Fall slew rate⁽¹⁾

(20% to 80%) × VDD, see Figure 2

0.25

0.75

V/ns

t_ƒ

(80% to 20%) × VDD, see Figure 2

t_W(H)

t_W(L)

Pulse duration LS_CLK high

Pulse duration LS_CLK low

50% to 50% reference points, see Figure 4

LS_WDATA valid before LS_CLK ↑ or LS_CLK ↓,

see Figure 4

t_su

t_h

Setup time

Hold time

1.5

LS_WDATA valid after LS_CLK ↑ or LS_CLK ↓,

see Figure 4

SubLVDS

t_r

Rise slew rate

20% to 80% reference points, see Figure 3

80% to 20% reference points, see Figure 3

See Figure 4

0.7

V/ns

t_ƒ

Fall slew rate

t_c

Cycle time DCLK

Pulse duration DCLK high

Pulse duration DCLK low

Window time

1.61

0.75

0.3

1.67

t_W(H)

t_W(L)

t_WINDOW

50% to 50% reference points, see Figure 4

Setup time + Hold time, see Figure 4, Figure 5

t_LVDS-

ENABLE+REFGEN

Power-up receiver⁽²⁾

2000

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 2.

(2) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

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DMD_DEN_ARSTZ

1.0 * VDD

0.8 * VDD

0.2 * VDD

0.0 * VDD

t_r

t_f

Figure 2. LPSDR Input Rise and Fall Slew Rate

V_{LS_CLK_P}, V_{LS_CLK_N}, V_{LS_WDATA_P}, V_{LS_WDATA_N}

V_{DCLK_AP}, V_{DCLK_BP}, V_{DCLK_AN}, V_{DCLK_BN}

V_{D_AP(7:0)}, V_{D_BP(7:0)}, V_{D_AN(7:0)}, V_{D_BN(7:0)}

1.0 * V

0.8 * V

0.2 * V

0.0 * V

t_r

t_f

Figure 3. SubLVDS Input Rise and Fall Slew Rate

(H)

(L)

DCLK_AP , DCLK_BP , LS_CLK_P

DCLK_AN , DCLK_BN , LS_CLK_N

50%

D_AP(7:0) , D_BP(7:0) , LS_WDATA_P

D_AN(7:0) , D_BN(7:0) , LS_WDATA_N

50%

window

Figure 4. SubLVDS Switching Parameters

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High Speed Training Scan Window

DCLK_AP, DCLK_BP

DCLK_AN, DCLK_BN

¼ t

D_AP(7:0), D_BP(7:0)

D_AN(7:0), D_BN(7:0)

Figure 5. High-Speed Training Scan Window

DCLK_AP , D_AP(7:0) ,

DCLK_BP , D_BP(7:0) ,

LS_CLK_P , LS_WDATA_P

V_ID

SubLVDS

Receiver

V_CM= (V_IP+ V_IN) / 2

DCLK_AN , D_AN(7:0) ,

DCLK_BN , D_BN(7:0) ,

LS_CLK_N , LS_WDATA_N

V_IP

V_IN

Figure 6. SubLVDS Voltage Parameters

1.225V

= V

+ | 1/2 * V

SubLVDS max

CM max

ID max

= V

œ | 1/2 * V

SubLVDS min

CM min

ID max

0.575V

Figure 7. SubLVDS Waveform Parameters

DCLK_AP

DCLK_BP

D_AP(7:0)

D_BP(7:0)

ESD

Internal

Termination

(ZIN)

SubLVDS

Receiver

DCLK_AN

DCLK_BN

D_AN(7:0)

D_BN(7:0)

ESD

Figure 8. SubLVDS Equivalent Input Circuit

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T+

û V

T-

DMD_DEN_ARSTZ

Figure 9. LPSDR Input Hysteresis

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6.8 Switching Characteristics⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output propagation, clock to Q, rising edge of LS_CLK

(differential clock signal) input to LS_RDATA output.

See Figure 10, Figure 11

t_PD

C_L= 45 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA_A and

LS_RDATA_B

40%

60%

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

LS_CLK_P

LS_CLK_N

LS_WDATA_P

LS_WDATA_N

Stop(1) Start(0)

t_PD

LS_RDATA

Acknowledge

Figure 10. LPSDR Read Out

Data Sheet Timing Reference Point

Device Pin

Tester Channel

Output Under Test

C_L

See Sub-LVDS Data Interface for more information.

Figure 11. Test Load Circuit for Output Propagation Measurement

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6.9 System Mounting Interface Loads

PARAMETER

Condition 1: Maximum load evenly distributed within each area⁽¹⁾

Thermal Interface Area

MIN NOM

MAX

UNIT

110.8

111.3

Electrical Interface Area

Condition 2: Maximum load evenly distributed within each area⁽¹⁾

Thermal Interface Area

Electrical Interface Area

222.1

(1) See Figure 12.

Figure 12. System Interface Loads

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6.10 Physical Characteristics of the Micromirror Array

PARAMETER

VALUE

1152

7.6

UNIT

micromirrors

Number of active columns

See Figure 13

Number of active rows

See Figure 13

micromirrors

Micromirror (pixel) pitch - diagonal

Micromirror (pixel) pitch - horizontal and vertical

Micromirror active array width

Micromirror active array height

Micromirror active border

See Figure 14

µm

See Figure 14

10.8

µm

P × M + P / 2; see Figure 13

(P × N) / 2 + P / 2; see Figure 13

Pond of micromirrors (POM)⁽¹⁾

12.447

6.226

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

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(0,0)

Illumination

Pond of Micromirrors (POM) are Omitted for Clarity

Row 1151

Row 1150

Row 1149

Row 1148

Row 1147

Row 1146

Row 1145

Row 1144

Off-State

Tilt Direction

On-State

Tilt Direction

DMD Active Mirror Array

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

Width

DMD Periphery

Illumination

Figure 13. Micromirror Array Physical Characteristics

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P (um)

Figure 14. Mirror (Pixel) Pitch

6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

Micromirror tilt angle tolerance⁽²⁾

(1) Measured relative to the plane formed by the overall micromirror array at 25°C.

TEST CONDITIONS

DMD landed state⁽¹⁾

MIN

NOM

MAX

UNIT

degree

–1

(2) For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some

optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result in

colorimetry variations, system efficiency variations, or system contrast variations.

6.12 Window Characteristics

PARAMETER

MIN

NOM

Corning Eagle XG

1.5119

MAX UNIT

Window material designation

Window refractive index

DMD efficiency⁽¹⁾

at wavelength 546.1 nm

420 nm - 700 nm

66%

(2)

Window aperture⁽²⁾

See

(1) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection

apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the efficiency

numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or overfill loss.

This number is measured under conditions described above and deviations from these specified conditions could result in a different

efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application include:

light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as LEDs or

lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well as the

DMD efficiency factors that are not system dependent are described in detail in the DMD Optical Efficiency Application Note.

(2) See the mechanical package ICD for details regarding the size and location of the window aperture.

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6.13 Chipset Component Usage Specification

The DLP5530-Q1 is a component of a chipset. Reliable function and operation of the DLP5530-Q1 requires that

it be used in conjunction with the TPS99000-Q1 and DLPC230-Q1, and includes components that contain or

implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices

used for operating or controlling a DLP DMD.

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously

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7 Detailed Description

7.1 Overview

The DLP5530-Q1 Automotive DMD consists of 1,327,104 highly reflective, digitally switchable, micrometer-sized

mirrors organized in a two-dimensional array. As shown in Figure 15, the micromirror array consists of 1152

micromirror columns × 1152 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio.

Around the perimeter of the 1152 × 1152 array of micromirrors is a uniform band of border micromirrors called

the Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors

land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each

side of the 1152 × 1152 active array.

Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns

of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors

are illuminated from the bottom which allows for compact and efficient system optical design.

Although the native resolution of the DLP5530-Q1 is 1152 × 1152, when paired with the DLPC230-Q1 controller,

the DLP5530-Q1 can be driven with different resolutions to utilize the 2:1 aspect ratio. For example, Head-Up

Display applications typically use a resolution of 1152 × 576. Please see the DLPC230-Q1 automotive DMD

controller data sheet (DLPS054) for a list of supported resolutions. Diamond pixel arrays also have the capability

to increase display resolution beyond native resolution. Future controllers or video formatters may take

advantage of this enhanced resolution.

Pond of Micromirrors (POM) are Omitted for Clarity

Row 1151

Row 1150

Row 1149

Row 1148

Row 1147

Row 1146

Row 1145

Row 1144

Off-State

Tilt Direction

On-State

Tilt Direction

DMD Active Mirror Array

Row 7

Row 6

Row 5

Row 4

Row 3

Row 2

Row 1

Row 0

Width

Illumination

Figure 15. 0.55-in 1.3-MP Micromirror Array

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7.2 Functional Block Diagram

High Speed Data Path &

Training: Bus A

High Speed Data Path &

Training: Bus B

(1151, 1151)

TEMP_P

TEMP_N

1.3 Mega Pixel 2:1 Aspect ratio

SRAM & Micromirror Array

(0,0)

DMD Mirror & SRAM Voltage Control

Low Speed Bus Interface & DMD Mirror

Voltage control

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7.3 Feature Description

The DLP5530-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a sub-LVDS bus

from the DLPC230-Q1 and powered by the TPS99000-Q1. The temperature sensing diode is used to

continuously monitor the DMD array temperature.

To ensure reliable operation the DLP5530-Q1 must be used with the DLPC230-Q1 DMD display controller and

the TPS99000-Q1 system management and illumination controller.

7.3.1 Sub-LVDS Data Interface

The Sub-LVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously

maintaining low power and low emission.

Data is loaded into the SRAM under each micromirror using the sub-LVDS interface from the DLPC230-Q1. This

interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and B

loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data

rate (DDR) interface. The sub-LVDS interface also implements a continuous training algorithm to optimize the

data and clock timing to allow for a more robust interface.

The entire DMD array of 1.3 million pixels can be updated at a rate of less than 100 µs as a result of the high

speed sub-LVDS interface.

7.3.2 Low Speed Interface for Control

The purpose of the low speed interface is to configure the DMD at power up and power down and to control the

micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage

controls the time when the mirrors are mechanically switched. The low speed differential interface includes 2

pairs of signals for write data and clock, and 2 single-ended signals for output (A and B).

7.3.3 DMD Voltage Supplies

The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These

voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by the

TPS99000-Q1.

7.3.4 Asynchronous Reset

Reset of the DMD is required and controlled by the DLPC230-Q1 via the signal DMD_DEN_ARSTZ.

7.3.5 Temperature Sensing Diode

The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring

device. The DLPC230-Q1 monitors the DMD array temperature via the TMP411 and temperature sense diode.

The DLPC230-Q1 operation of the DMD timing is based in part on the DMD array temperature, therefore this

connection is essential to ensure reliable operation of the DMD.

Figure 16 shows the typical connection between the DLPC230-Q1, TMP411, and the DMD.

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Feature Description (continued)

DLPC230-Q1

DLP5530-Q1

TEMP_N

TEMP_P

56 Ω

SCL

D +

SCA

100 pF

THERM1

THERM2

D t

TMP411 œ Q1

Figure 16. Temperature Sense Diode Typical Circuit Configuration

7.3.5.1 Temperature Sense Diode Theory

A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.

The diode is formed by connecting the transistor base to the collector. Three different known currents flow

through the diode and the resulting diode voltage is measured in each case. The difference in their base–emitter

voltages is proportional to the absolute temperature of the transistor.

Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.

Figure 17 and Figure 18 illustrate the relationships between the current and voltage through the diode.

IE1

IE2

TEMP_N

VBE 1,2

TEMP_P

Figure 17. Temperature Measurement Theory

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Feature Description (continued)

100uA

10uA

1uA

Temperature (°C)

Figure 18. Example of Delta VBE Versus Temperature

7.4 System Optical Considerations

Optimizing system optical performance and image performance strongly relates to optical system design

parameter trades. Although it is not possible to anticipate every conceivable application, projector image and

optical performance is contingent on compliance to the optical system operating conditions described in the

following sections.

7.4.1 Numerical Aperture and Stray Light Control

The numerical aperture of the illumination and projection optics at the DMD optical area should be the same.

This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless

appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light

from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from

any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces.

7.4.2 Pupil Match

TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is nominally

centered and located at the entrance pupil position of the projection optics. Misalignment of pupils between the

illumination and projection optics can degrade screen image uniformity and cause objectionable artifacts in the

display’s border and/or active area. These artifacts may require additional system apertures to control, especially

if the numerical aperture of the system exceeds the pixel tilt angle.

7.4.3 Illumination Overfill

Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and

other surfaces that surround the active array. These artifacts may be visible in the projected image. The

illumination optical system should be designed to minimize light flux incident outside the active array and on the

window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this amount

of overfill light on the area outside of the active array may still cause artifacts to be visible.

Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if illumination

light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load on the

aperture in the areas shown in Figure 1 should not exceed the values listed in Window Characteristics. This area

is a 0.5-mm wide area the length of the aperture opening. The values listed in Window Characteristics assume a

uniform distribution. For a non-uniform distribution please contact TI for additional information.

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System Optical Considerations (continued)

NOTE

TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD

FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING

LIMITS DESCRIBED PREVIOUSLY.

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7.5 DMD Image Performance Specification

Table 1. DMD Image Performance⁽¹⁾⁽²⁾

PARAMETER

MIN

NOM

MAX

UNIT

Dark Blemishes - Viewed on a linear blue 60 screen.⁽³⁾

Light Blemishes - Viewed on a linear gray 10 screen.

Bright Pixels - Viewed on a linear gray 10 screen.

Dark Pixels - Viewed on a white screen.

micromirrors

(1) See the System Optical Considerations section.

(2) Blemish counts do not include reflections or shadows of the same artifact. Any artifact that is not specifically called out in this table is

acceptable. Viewing distance must be > 60 in. Screen size should be similar to application image size. All values referenced are in linear

gamma. Non-linear gamma curves may be running by default, and it should be ensured with a TI applications engineer that the

equivalent linear gamma value as specified is used to judge artifacts.

(3) Linear gray 5 may be substituted in monochrome applications.

7.6 Micromirror Array Temperature Calculation

Figure 19. DMD Thermal Test Points

The active array temperature can be computed analytically from measurement points on the outside of the

package, the package thermal resistance, the electrical power, and the illumination heat load.

Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in

Figure 19) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

)

(1)

where

•

T_ARRAY= computed DMD array temperature (°C)

T_CERAMIC= measured ceramic temperature, TP1 location in Figure 19 (°C)

R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from array to thermal test point TP1 (°C/W), see

Thermal Information

•

Q_ARRAY= total power, electrical plus absorbed, on the DMD array (W)

Q_ELECTRICAL= nominal electrical power dissipation by the DMD (W)

Q_ILLUMINATION= (C_L2W× SL)

C_L2W= conversion constant for screen lumens to power on the DMD (W/lm)

SL = measured screen lumens (lm)

(2)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies.

Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and

the intensity of the light source.

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Micromirror Array Temperature Calculation (continued)

Equations shown above are valid for a 1–chip DMD system with a total projection efficiency from DMD to the

screen of 87%.

The constant C_L2Wis based on the DMD array characteristics. It assumes a spectral efficiency of 300 lm/W for

the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array border.

The following is a sample calculation for a typical projection application:

1. SL = 50 lm

2. C_L2W= 0.00293 W/lm

3. Q_ELECTRICAL= 0.4 W (This number does not represent an actual DMD electrical power; for illustration

purposes only)

4. R_{ARRAY–TO–CERAMIC}= 1.1°C/W

5. T_CERAMIC= 55°C

6. Q_ARRAY= 0.4 W + (0.00293 W/lm × 50 lm) = 0.5465 W

7. T_ARRAY= 55°C + (0.5465 W × 1.1°C/W) = 55.6°C

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7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the

time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90%

of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLP5530-Q1 chipset is designed to support projection-based automotive applications such as head-up

display systems.

8.2 Typical Application

The chipset consists of three components—the DLP5530-Q1 automotive DMD, the DLPC230-Q1, and the

TPS99000-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images.

The DLPC230-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD

illumination sources and the DMD in order to display the incoming video. The TPS99000-Q1 is a controller for

the illumination sources (LEDs) and a management IC for the entire chipset. In conjunction, the DLPC230-Q1

and the TPS99000-Q1 can also be used for system-level monitoring, diagnostics, and failure detection features.

Figure 20 is a system level block diagram with these devices in the DLP head-up display configuration and

displays the primary features and functions of each device.

topology and capacity

tailored to specific

system application

TPS62260(3)

or numerous

other options

VLED

6.5 V

SHUTDOWN.

VBATT.

Pre-

regulator

6.5 V

3.3 V

1.1 V

1.8 V

3.3 V

External

regulators

LDO

(optional)

Power sequencing

and monitoring

High-side

current limiting

PROJ_ON.

SPI (4).

up to 42-V tolerance

when pre-regulation

not in use

12 bit

ADC

External ADC inputs

for general usage

LM3409

LED drive

PMIC diagnostics

port

with up to 64 HW timed

samples per frame

AC3

SPI_2

ADC_CTRL (2).

SPI (4).

shu

nt(2)

RED.

GREEN.

MPU

ECC

WD (2).

LED_SEL (4).

SEQ_START.

S_EN.

Ultra wide dimming

LED controller

SPI_1

Low-side current

measurement

HOST_IRQ.

OpenLDI.

TPS99000-Q1

D_EN.

DLPC230-Q1

illumination

optics

External watchdogs /

over brightness / and

other monitors

photo diode

CTRL

COMPOUT.

SEQ_CLK.

Parallel

28.

DATA

24.

eSRAM

frame buffer

General

purpose

PARKZ.

RESETZ.

INTZ.

Photo diode

PD neg

measurement

LDO

I2C (2).

SPI (4).

I2C_0

SPI_0

system

BIAS, RST, OFS

(3).

Eye box

motor ctl

GPIOx

Sys clock

monitor

DMD bias

regulator

VCC_FLASH

VCC_INTF

Spare

GPIO

3.3 V

1.8 V

1.1 V

GPIOx

I2C_1

EEPROM

VIO

TMP411

(2).

DMD die temperature

Calibration data

sub-LVDS DATA.

Control.

VCORE

DLP5530-Q1

DMD

Sub-LVDS

Interface

Figure 20. Head-Up Display System Block Diagram

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Typical Application (continued)

8.2.1 Application Overview

Figure 20 shows the system block diagram for a DLP HUD system. The system uses the DLPC230-Q1,

TPS99000-Q1, and the DLP5530-Q1 automotive DMD to enable a head-up display with high brightness, high

efficiency, and a large virtual image distance. The combination of the DLPC230-Q1 and TPS99000-Q1 removes

the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination control of

LED sources, power sequencing functions, and system management functions. Additionally, the chipset supports

numerous system diagnostic and built-in self test (BIST) features. The following paragraphs describe the

functionality of the chipset used for a HUD system in more detail.

The DLPC230-Q1 is a controller for the DMD and the light sources in the DLP HUD module. It receives input

video from the host and synchronizes DMD and light source timing in order to achieve the desired video. The

DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with

light source timing in order to create a video with a multi-colored display.

The DLPC230-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input

video data. Host commands can be sent using either the I²C bus or SPI bus. The bus that is not being used for

host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an

OpenLDI bus or a parallel 24-bit bus. The SPI flash memory provides the embedded software for the DLPC230-

Q1’s ARM core and default settings. The provides diagnostic and monitoring information to the DLPC230-Q1

using an SPI bus and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up

and power-down sequencing. The TMP411 uses an I²C interface to provide the DMD array temperature to the

DLPC230-Q1.

The outputs of the DLPC230-Q1 are configuration and monitoring commands to the , timing controls to the LED

or laser driver, control and data signals to the DMD, and monitoring and diagnostics information to the host

processor. The DLPC230-Q1 communicates with the over an SPI bus. It uses this to configure the and to read

monitoring and diagnostics information from the . The DLPC230-Q1 sends drive enable signals to the LED or

laser driver, and synchronizes this with the DMD mirror timing. The control signals to the DMD are sent using a

sub-LVDS interface.

The is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and diagnostics

information for the DLP HUD system. The power sequencing and monitoring blocks of the properly power up the

DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V), and then monitor the system’s power

rails during operation. The integration of these functions into one IC significantly reduces design time and

complexity.

The receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and potentially

several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the over an SPI bus

and several other control signals. The DLPC230-Q1’s clocks are also monitored by the watchdogs in the to

detect any errors. The power rails are monitored by the in order to detect power failures or glitches and request a

proper power down of the DMD in case of an error. The host processor can read diagnostics information from the

using a dedicated SPI bus, which enables independent monitoring. Additionally the host can request the image to

be turned on or off using a PROJ_ON signal. Lastly, the has several general-purpose ADCs that can be used to

implement system level monitoring functions.

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

Typical Application (continued)

The outputs of the are diagnostic information and error alerts to the DLPC230-Q1, and control signals to the LED

or laser driver. The can output diagnostic information to the host and the DLPC230-Q1 over two SPI buses. In

case of critical system errors, such as power loss, it outputs signals to the DLPC230-Q1 that trigger power down

or reset sequences. It also has output signals that can be used to implement various LED or laser driver

topologies.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video

data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS

interface with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD

array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.

8.2.2 Reference Design

For information about connecting together the DLP5530-Q1 DMD, DLPC230-Q1 controller, and TPS99000-Q1,

please contact the TI Application Team for additional information about the DLP5530-Q1 evaluation module

(EVM). TI has optical-mechanical reference designs available, see the TI Application team for more information.

8.2.3 Application Mission Profile Consideration

Each application is anticipated to have different mission profiles, or number of operating hours at different

temperatures. To assist in evaluation the Application Report Reliability Lifetime Estimates for DLP3030-Q1 and

DLP553x-Q1 DMDs in Automotive Applications may be provided. See the TI Application team for more

information.

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.

All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the

TPS99000-Q1 devices.

CAUTION

For reliable operation of the DMD, the following power supply sequencing

requirements must be followed. Failure to adhere to the prescribed power-up and

power-down procedures may affect device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated

during power-up and power-down operations. Failure to meet any of the below

requirements will result in a significant reduction in the DMD’s reliability and lifetime.

VSS must also be connected.

9.1 Power Supply Power-Up Procedure

•

During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in the Recommended Operating Conditions.

During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled

at operating voltage.

During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in Figure 21.

9.2 Power Supply Power-Down Procedure

•

The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

•

During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended

Operating Conditions (Refer to Note 2 in Figure 21).

•

During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the

Recommended Operating Conditions.

During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in Figure 21.

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

9.3 Power Supply Sequencing Requirements

TPS99000 initiates DMD power-down

sequence. DLPC230 executes critical

commands.

Note 5

DLPC230 and TPS99000

disables VBIAS, VOFFSET,

and VRESET

Drawing Not To Scale.

DLPC230 and TPS99000

control start of DMD operation

Mirror Park Sequence

Note 4

Details Omitted For Clarity.

Power Off

VDD / VDDI

VSS

VBIAS

VBIAS < 4 V

ûV < Specification

Note 1

ûV < Specification

VSS

Note 3

ûV < Specification

Note 2

VOFFSET

VOFFSET < 4 V

VOFFSET

VSS

VRESET < 0.5 V

VRESET > - 4 V

VRESET

VDD

VRESET

VDD

DMD_DEN_ARSTZ

VSS

Initialization

LS_CLK_P

LS_CLK_N

LS_WDATA_P

LS_WDATA_N

Waveforms Not To Scale.

D_AP(7:0) , D_AN(7:0)

D_BP(7:0) , D_BN(7:0)

DCLK_AP , DCLK_AN

DCLK_BP , DCLK_BN

VSS

Refer to the sections —Absolute Maximum Ratings“ and —Recommended Operating Conditions“.

(1) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in the

Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET

prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Also, is capable of

managing the timing between VBIAS and VOFFSET.

(2) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified than the limit

shown in the Recommended Operating Conditions.

(3) When system power is interrupted, the TPS9000 initiates hardware power-down that disables VBIAS, VRESET and

VOFFSET after the Micromirror Park Sequence.

(4) Drawing is not to scale and details are omitted for clarity.

Figure 21. Power Supply Sequencing Requirements (Power Up and Power Down)

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

Please refer to the DLPC230-Q1 and data sheets for specific PCB layout and routing guidelines. For specific

DMD PCB guidelines, use the following:

•

Match lengths for the LS_WDATA and LS_CLK signals.

Minimize vias, layer changes, and turns for the HS bus signals.

Minimum of two 220-nF decoupling capacitors close to VBIAS.

Minimum of two 220-nF decoupling capacitors close to VRESET.

Minimum of two 220-nF decoupling capacitors close to VOFFSET.

Minimum of four 100-nF decoupling capacitors close to VDDI and VDD.

Temperature diode pins

The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411

temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to

noise. Please see the TMP411 data sheet for specific routing recommendations.

DLP5530-Q1

www.ti.com.cn

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

DLP5530 A FYK Q1

Automotive

Package Type

Temperature Rating (-40°C to 105°C)

Device Descriptor

图 22. 器件型号说明

11.1.2 器件标记

器件标记包括清晰可辨的字符串 GHJJJJK DLP5530AFYKQ1。GHJJJJK 是批次跟踪代码。DLP5530AFYKQ1 是

器件型号。

TI Internal Numbering

Part 2 of Serial Number

(7 Characters)

Part 1 of Serial Number

(7 Characters)

2-Dimension Matrix Code

(Part Number and Serial Number)

DMD Part Number

图 23. DMD 标记

11.2 相关链接

下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链

接。

表 2. 相关链接

器件

产品文件夹

链接

样片与购买

链接

技术文档

链接

工具与软件

链接

支持和社区

链接

DLP5530-Q1

DLPC230-Q1

TPS99000-Q1

链接

DLP5530-Q1

ZHCSIF9F –MARCH 2016–REVISED MAY 2019

www.ti.com.cn

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 DMD 处理

DMD 是光学器件，故应注意避免损坏玻璃窗口。有关正确处理 DMD 的说明，请参阅《DLPA019 DMD 处理》应

用手册。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

24-Dec-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP5530AFYKQ1

ACTIVE

CPGA

FYK

149

RoHS & Green

Call TI

N / A for Pkg Type

-40 to 105

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2514853

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

DATE

12/7/2015

4/25/2017

11/9/2017

ECO 2155049: INITIAL RELEASE

ECO 2165903: UPDATE SUBSTRATE BACK MARKING, SH. 4

ECO 2170159: RELAX DIE HEIGHT TOL., WAS +/-0.08

BMH

SUBSTRATE EDGE PERPENDICULARITY TOLERANCE APPLIES TO ENTIRE SURFACE.

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM VALUE OF 0.8 DEGREES.

SUBSTRATE SYMBOLIZATION PAD AND PLATING AT BOTTOM OF DATUMS B AND C

HOLES TO BE ELECTRICALLY CONNECTED TO VSS PLANE WITHIN THE SUBSTRATE.

BOUNDARY MIRRORS SURROUNDING THE ACTIVE ARRAY.

MAXIMUM ENCAPSULANT PROFILE SHOWN.

ENCAPSULANT ALLOWED ON THE SURFACE OF THE CERAMIC IN THE AREA SHOWN

IN VIEW B (SHEET 2). ENCAPSULATION SHALL NOT EXCEED 0.2 THICKNESS MAXIMUM.

INDICATED CERAMIC SUBSTRATE FEATURES TO BE PLATED WITH 0.3 MICROMETERS

MINIMUM ELECTROLYTIC GOLD OVER 0.1 MICROMETER MINIMUM PALLADIUM OVER

1.27-8.89 MICROMETERS ELECTROLYTIC NICKEL PER ASTM B488-01, ASTM

B679-95(2009), AND AMS-QQ-N-290, RESPECTIVELY.

0.2E



SEE VIEW E (SHEET 3)

FOR WINDOW AND ACTIVE

ARRAY DIMENSIONS

NOTE THAT THE ACTIVE ARRAY CENTER IS IN A DIFFERENT LOCATION FROM ALL

PRIOR SERIES 450 DMD'S.

3 0.5

(Ø2)

1.0640.15

3 0.5

22.30.22

12.6870.15

(1.5)

2.335 0.15

23.330.15

32.20.32

SUBSTRATE

3 PLACES

ENCAPSULANT

(0.56)

INCIDENT

LIGHT

0.8 MAX

WINDOW

WINDOW APERTURE

INDICATED

(SHEET 2)

1.1 0.05

1.61 0.077

0.0254A

0.02G

1.050.1

2.925 0.24



(0.51)

(0.75)

ACTIVE ARRAY

149X 1.4 0.1

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TEXAS

12/7/2015

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

TOLERANCES:

Dallas Texas

12/7/2015

12/8/2015

ANGLES 1

TITLE

ICD, MECHANICAL, DMD

.55 2:1 1.3MP SERIES 450 -A1

(FYK PACKAGE)

(Ø0.305)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

SECTION A-A

P. KONRAD

SCALE 20 : 1

S. SUSI

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

NONE

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

M. DORAK

APPROVED

B. RAY

2514853

NEXT ASSY

SCALE

SHEET

APPLICATION

4:1

INV2013-DLPa

DWG NO.

2514853

0.5 MIN

(Ø2)

1.840.13

280.28

(DATUM B TO CENTER OF DATUM C SLOT)

25.85 MAX

2.1 0.15

2 MIN

ENCAPSULANT ALLOWED

ON CERAMIC AREA

2±0.05

SECTION C-C

DATUM B

SCALE 16 : 1

5.150.15

2.9

23.2° 1°

120.12

14.9

0.5 MIN

(1.5)

3X 4

1.840.13

1.5 0.05

0.750.025

1 0.1

WINDOW

SECTION D-D

DATUM C

0.5 0.05

(VIEW ROTATED FOR CLARITY)

SCALE 16 : 1

2X 28

(DATUM B TO A2 AND A3)

VIEW B

DATUMS AND ENCAPSULANT ALLOWABLE AREA

SCALE 10 : 1

DWG NO

REV

SIZE

DRAWN

DATE

12/7/2015

TEXAS

2514853

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

DWG NO.

2514853

(2.1)

(12.447)

ACTIVE ARRAY

7.7760.076

4X (0.108)

(Ø2)

(5.15)

1.073±0.0885

2.887 0.076



2.0750.05

(8.033)

WINDOW

APERTURE

(10)

WINDOW

(6.2262)

ACTIVE ARRAY

6.96±0.0885

7.925±0.05

(1.5)

0.356±0.0885

12.802±0.0885

(13.158)

WINDOW APERTURE

2.68440.05

15.13140.05

(17.8158)

WINDOW

VIEW E

ACTIVE ARRAY AND WINDOW

SCALE 12 : 1

DWG NO

REV

SIZE

DRAWN

DATE

12/7/2015

TEXAS

2514853

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

DWG NO.

2514853

19.145

9 X 1.27 = 11.43

1.625

(A1, A2, & B1 OMITTED)

1.625

3.8950.25

14.510.25

15 X 1.27 = 19.05

SYMBOLIZATION

PAD

0.05

8.5 0.25

11.85 0.25

149X 0.305

0.5DEF

PINS

0.025



0.25D

VIEW F

PINS AND SYMBOLIZATION PAD

SCALE 8 : 1

0.28 MAX

(BRAZE AREA)

Ø0.85 MAX

(BRAZE AREA)

(R0.05)

(Ø0.305)

(1.4)

DETAIL G

PIN AND BRAZE DIMENSIONS

149 PLACES

SCALE 40 : 1

DWG NO

REV

SIZE

DRAWN

DATE

12/7/2015

TEXAS

2514853

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DLP5530AFYKQ1 [TI]

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SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E