DLP5532AFYSQ1 [TI]

Automotive 0.55-inch DLP® digital micromirror device for interior and transparent window displays | FYS | 149 | -40 to 105;


型号：	DLP5532AFYSQ1
厂家：	TEXAS INSTRUMENTS
描述：	Automotive 0.55-inch DLP® digital micromirror device for interior and transparent window displays \| FYS \| 149 \| -40 to 105
文件：	总38页 (文件大小：1881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP5530S-Q1

ZHCSMN0 –JUNE 2021

DLP5532-Q1 适用于汽车显示的0.55 英寸130 万像素DMD

1 特性

3 说明

• 符合汽车应用要求

DLP5532-Q1 汽车 DMD 与 DLPC230-Q1 DMD 控制

器和TPS99000-Q1 系统管理和照明控制器结合使用，

能够在照射到特殊窗口薄膜表面时实现高性能汽车窗口

显示。2:1 宽高比支持非常宽的宽高比设计，130 万个

原生像素支持高分辨率内容。DLP5532-Q1 的光通量

是前代 DLP3030-Q1 汽车 DMD 的 3 倍以上，能够实

现更亮、更大的显示效果，从而实现更佳的观看体验。

该芯片组与 LED 和投影仪配合使用，可实现 125%

NTSC 的深度饱和色彩、超过 1,000 流明的超高亮度

以及大于100:1 的调光比。DLP5532-Q1 汽车DMD 微

镜阵列针对底部照明而配置，可实现更高效率和更紧凑

的光学引擎设计。S450 封装针对 DMD 阵列而言具有

低热阻的特点，可实现更高效的热解决方案。

– DMD 阵列工作温度范围-40°C 至105°C

• DLP5532-Q1 汽车芯片组包括：

– DLP5532-Q1 DMD

– DLPC230-Q1 DMD 控制器

– TPS99000-Q1 系统管理和照明控制器

• 0.55 英寸对角线微镜阵列

– 7.6 μm 微镜间距

– ±12° 微镜倾斜角（相对于平面）

– 底部照明，实现最优的效率和光学引擎尺寸

– 支持1152 × 576 输入分辨率

– 高达2304 x 1152 分辨率，外部基于GPU 的菱

形预处理

– 与LED 或激光照明兼容

• 600 MHz sub-LVDS DMD 接口，可实现低功耗和低

排放

为了帮助设计和制造基于 DLP 技术的符合汽车标准的

投影仪，可利用许多老牌光学模块制造商和设计公司来

支持您的设计。

• 温度极值下DMD 刷新率为10 kHz

• DMD 存储器单元的内置自检

• 图像性能针对窗口显示和其他内部显示进行了优化

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DLP5532-Q1

FYS (149)

22.30mm × 32.20mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 适用于车辆前窗、侧窗、后窗的窗口显示

• 室内天花板投影仪

Voltage

Monitor and

Enables

TPS99000-Q1

Power

Regulation

1.8V

1.1V

3.3V

6.5V

LED dimming

System

diagnostics

V_OFFSET

SPI

DLPC230-Q1

SPI

V_BIAS

DMD power

management

DLP5532-Q1

V_RESET

Video

ARM®

Cortex®-R4F

SubLVDS

DMD video

processing &

control

TMP411

Temperature

Sensor

0.55" DMD

2:1 aspect ratio

1.3M pixels

I²C

LED

ENABLE

Video

memory

Flash

SPI

DLP5532-Q1 TI DLP^®芯片组系统方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS208

DLP5530S-Q1

ZHCSMN0 –JUNE 2021

www.ti.com.cn

Table of Contents

7.4 System Optical Considerations.................................20

7.5 Micromirror Array Temperature Calculation.............. 21

7.6 Micromirror Landed-On/Landed-Off Duty Cycle....... 23

8 Application and Implementation..................................24

8.1 Application Information............................................. 24

8.2 Typical Application.................................................... 24

9 Power Supply Recommendations................................27

9.1 Power Supply Power-Up Procedure......................... 27

9.2 Power Supply Power-Down Procedure.....................27

9.3 Power Supply Sequencing Requirements................ 28

10 Layout...........................................................................29

10.1 Layout Guidelines................................................... 29

11 Device and Documentation Support..........................30

11.1 Device Support........................................................30

11.2 接收文档更新通知................................................... 30

11.3 支持资源..................................................................30

11.4 Trademarks............................................................. 30

11.5 静电放电警告...........................................................31

11.6 DMD Handling.........................................................31

11.7 术语表..................................................................... 31

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings ....................................... 8

6.2 Storage Conditions .................................................... 8

6.3 ESD Ratings .............................................................. 8

6.4 Recommended Operating Conditions ........................9

6.5 Thermal Information .................................................10

6.6 Electrical Characteristics ..........................................10

6.7 Timing Requirements ............................................... 11

6.8 Switching Characteristics .........................................14

6.9 System Mounting Interface Loads ........................... 15

6.10 Physical Characteristics of the Micromirror Array ..15

6.11 Micromirror Array Optical Characteristics .............. 17

6.12 Window Characteristics ......................................... 17

6.13 Chipset Component Usage Specification............... 17

7 Detailed Description......................................................18

7.1 Overview...................................................................18

7.2 Functional Block Diagram.........................................18

7.3 Feature Description...................................................19

Information.................................................................... 31

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

June 2021

Initial Release

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English Data Sheet: DLPS208

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5 Pin Configuration and Functions

图5-1. FYS Package

149-Pin CPGA

Bottom View

Pin Functions - Connector Pins

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

NO.

DATA INPUTS

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AP(0)

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

SubLVDS

Double

Data, Negative

Data, Positive

Data, Negative

K19

J19

H19

G19

E19

D19

C19

B19

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Pin Functions - Connector Pins (continued)

NAME

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

K20

J20

H20

G20

E20

D20

C20

B20

D_BP(0)

SubLVDS

Double

Single

Data, Positive

Clock, Negative

Clock, Positive

Clock, Negative

Clock, Positive

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

LS_CLKN

LS_CLKP

LS_WDATAN

LS_WDATAP

CONTROL INPUTS

F19

F20

Clock for Low Speed Interface, Negative

Clock for Low Speed Interface, Positive

Write Data for Low Speed Interface, Negative

Write Data for Low Speed Interface, Positive

Single

Asynchronous Reset Active Low. Logic High

Enables DMD.

DMD_DEN_ARSTZ

T10

LPSDR

LS_RDATA_A

LS_RDATA_B

LPSDR

Single

Read Data for Low Speed Interface

TEMPERATURE SENSE DIODE

TEMP_N

TEMP_P

RESERVED PINS

VCCH

Calibrated temperature diode used to assist

accurate temperature measurements of DMD die.

Ground

VCCH

A10

Reserved Pin. Connect to Ground.

VCCH

B10

A11

A12

A13

B11

B12

B13

VSSH

Reserved Pin. Connect to Ground.

VSSH

English Data Sheet: DLPS208

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Pin Functions - Connector Pins (continued)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NAME

POWER

VBIAS

VOFFSET

VRESET

VDD

NO.

T15

Power

Supply voltage for positive bias level at

micromirrors.

T13

Supply voltage for High Voltage CMOS core

logic. Supply voltage for offset level at

micromirrors.

A16

B16

Supply voltage for negative reset level at

micromirrors.

T14

VDD

R10

R11

R20

VDD

M20

VDD

Supply voltage for Low Voltage CMOS core logic;

for LPSDR inputs; for normal high level at

micromirror address electrodes.

VDD

K18

VDD

G18

VDD

D18

VDD

A18

VDDI

L18

VDDI

Supply voltage for SubLVDS receivers.

VDDI

H18

VDDI

E18

VDDI

B18

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Pin Functions - Connector Pins (continued)

NAME

VSS

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

Ground

T16

T19

T20

R13

R14

R15

P20

N19

N20

Common return. Ground for all power.

L19

L20

J18

F18

C18

B15

B17

A15

A17

A19

A20

English Data Sheet: DLPS208

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Pin Functions - Test Pads

NUMBER

T11

SYSTEM BOARD

Do not connect

T12

T17

T18

R12

R16

R17

R18

R19

P18

P19

N18

M18

M19

B14

A14

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6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE

Supply voltage for LVCMOS core logic

VDD

2.3

–0.5

Supply voltage for LPSDR low speed interface

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)

VDDI

2.3

8.75

–0.5

–11

VOFFSET

VBIAS

VRESET

0.5

0.3

| VDDI–VDD |

Supply voltage delta (absolute value)

8.75

| VBIAS–VOFFSET |

| VBIAS–VRESET |

INPUT VOLTAGE

Supply voltage delta (absolute value)

Input voltage for other inputs LPSDR

Input voltage for other inputs SubLVDS

INPUT PINS

VDD + 0.5

VDDI + 0.5

–0.5

| V_ID

I_ID

SubLVDS input differential voltage (absolute value)

SubLVDS input differential current

810

TEMPERATURE DIODE

I_{TEMP_DIODE}

Max current source into temperature diode

120

μA

ENVIRONMENTAL

ILL_OVERFILL

37 mW/mm²

105 °C

Illumination overfill maximum heat load in area shown in 图6-1

T_ARRAY

Operating DMD array temperature

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may

affect device reliability.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

T_stg

DMD storage temperature

125

°C

–40

6.3 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

±2000

±750

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

English Data Sheet: DLPS208

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

VDD

1.7

1.8

1.95

VDDI

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode

Supply voltage for mirror electrode

1.7

8.25

1.8

8.5

1.95

8.75

VOFFSET

VBIAS

15.5

16.5

VRESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)

–9.5

–10

–10.5

0.3

| VDDI–VDD |

| VBIAS–VOFFSET |

CLOCK FREQUENCY

ƒ_max

8.75

Clock frequency for low speed interface LS_CLK

Clock frequency for high speed interface DCLK

Duty cycle distortion DCLK

120

600

MHz

ƒ_max

44%

56%

SUBLVDS INTERFACE

| V_ID

V_CM

SubLVDS input differential voltage (absolute value)⁽²⁾

Common mode voltage ⁽²⁾

150

700

250

900

100

350

1100

110

Z_LINE

Line differential impedance (PWB/trace)

Internal differential termination resistance⁽³⁾

Z_IN

120

ENVIRONMENTAL

T_ARRAY

Operating DMD array temperature⁽⁵⁾

105

°C

–40

ILL_UV

Illumination, wavelength < 395 nm ⁽⁴⁾

mW/cm ²

ILL_OVERFILL

28 mW/mm ²

Illumination overfill maximum heat load in area shown in 图6-1

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) See 图6-6 and 图6-7

(3) See 图6-8

(4) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.

(5) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.

图6-1. Illumination Overfill Diagram

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6.5 Thermal Information

DLP5532-Q1

FYS (CPGA)

149 PINS

1.1

THERMAL METRIC

UNIT

Thermal resistance

Active area-to-test point 1 (TP1) ⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in 节6.4. The total heat load on the DMD is largely driven by the

incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT

I_DD

Supply current: VDD⁽²⁾

Supply current: VDDI⁽²⁾

Supply current: VOFFSET

Supply current: VBIAS

Supply current: VRESET

VDD = 1.95 V

310

I_DDI

VDDI = 1.95 V

I_OFFSET

I_BIAS

VOFFSET = 8.75 V

VBIAS = 16.5 V

VRESET = -10.5 V

I_RESET

-4.5

POWER

P_DD

Supply power dissipation: VDD⁽²⁾

Supply power dissipation: VDDI⁽²⁾

Supply power dissipation: VOFFSET

Supply power dissipation: VBIAS

Supply power dissipation: VRESET

Supply power dissipation: Total

VDD = 1.95 V

604.5

107.25

52.5

P_DDI

VDDI = 1.95 V

P_OFFSET

P_BIAS

VOFFSET = 8.75 V

VBIAS = 16.5 V

VRESET = -10.5 V

16.5

P_RESET

P_TOTAL

LPSDR INPUT ⁽³⁾

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

47.25

828

DC input high voltage

DC input low voltage

AC input high voltage

AC input low voltage

0.7 × VDD

–0.3

VDD + 0.3

0.3 × VDD

VDD + 0.3

0.2 × VDD

0.4 × VDD

0.8 × VDD

–0.3

0.1 × VDD

∆V_T

I_IL

Hysteresis (V_T+–V_T–

)

See 图6-9

VDD = 1.95 V; V_I= 0 V

VDD = 1.95 V; V_I= 1.95 V

Low–level input current

–100

I_IH

300

High–level input current

LPSDR OUTPUT ⁽⁴⁾

V_OH

DC output high voltage

I_OH= -2mA

I_OL= 2mA

0.8 × VDD

V_OL

DC output low voltage

0.2 × VDD

CAPACITANCE

Input capacitance LPSDR

Input capacitance SubLVDS

Output capacitance

ƒ= 1 MHz

C_IN

C_OUT

ƒ= 1 MHz (1152 X 144

micromirrors)

C_RESET

C_TEMP

Reset group capacitance

350

400

450

Temperature sense diode capacitance

ƒ= 1 MHz

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) Supply power dissipation based on non–compressed commands and data.

(3) LPSDR input specifications are for pin DMD_DEN_ARSTZ.

(4) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.

English Data Sheet: DLPS208

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6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted

MIN

NOM

MAX

UNIT

LPSDR

t_r

Rise slew rate ⁽¹⁾

(20% to 80%) × VDD

0.25

0.75

1.5

V/ns

t_f

Fall slew rate ⁽¹⁾

(80% to 20%) × VDD

t_W(H)

Pulse duration LS_CLK high⁽³⁾

Pulse duration LS_CLK low⁽³⁾

Setup time⁽³⁾

50% to 50% reference points

t_W(L)

50% to 50% reference points

t_su

LS_WDATA valid before LS_CLK ↑or LS_CLK ↓

LS_WDATA valid after LS_CLK ↑or LS_CLK ↓

t_h

Hold time⁽³⁾

1.5

SubLVDS

t_r

Rise slew rate⁽²⁾

20% to 80% reference points

80% to 20% reference points

0.7

V/ns

t_f

Fall slew rate⁽²⁾

t_c

Cycle time DCLK⁽³⁾

Pulse duration DCLK high⁽³⁾

Pulse duration DCLK low⁽³⁾

Window time^{(3) (4)}

1.61

0.75

0.3

1.67

t_W(H)

t_W(L)

t_WINDOW

50% to 50% reference points

Setup time + Hold time

t_{LVDS-ENABLE+REFGEN}Power-up receiver⁽⁵⁾

2000

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-2

(2) See 图6-3

(3) See 图6-4

(4) See 图6-5

(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

图6-2. LPSDR Input Rise and Fall Slew Rate

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图6-3. SubLVDS Input Rise and Fall Slew Rate

图6-4. SubLVDS Switching Parameters

图6-5. High-Speed Training Scan Window

English Data Sheet: DLPS208

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图6-6. SubLVDS Voltage Parameters

图6-7. SubLVDS Waveform Parameters

DCLK_AP

DCLK_BP

D_AP(7:0)

D_BP(7:0)

ESD

Internal

Termination

DCLK_AN

DCLK_BN

D_AN(7:0)

D_BN(7:0)

SubLVDS

Receiver

ESD

图6-8. SubLVDS Equivalent Input Circuit

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图6-9. LPSDR Input Hysteresis

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output propagation, clock to Q, rising edge of LS_CLK

(differential clock signal) input to LS_RDATA output.⁽²⁾

t_PD

C_L= 45 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B

40%

60%

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) See 图6-10 and 图6-11

图6-10. LPSDR Read Out

图6-11. Test Load Circuit for Output Propagation Measurement

English Data Sheet: DLPS208

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6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Condition 1: Maximum load evenly distributed within each area ⁽¹⁾

Thermal Interface Area

110.8

111.3

Electrical Interface Area

Condition 2: Maximum load evenly distributed within each area ⁽¹⁾

Thermal Interface Area

Electrical Interface Area

222.1

(1) See 图6-12

图6-12. System Interface Loads

6.10 Physical Characteristics of the Micromirror Array

PARAMETER

VALUE

1152

7.6

UNIT

Number of active columns⁽¹⁾

micromirrors

Number of active rows⁽¹⁾

micromirrors

Micromirror (pixel) pitch - diagonal⁽¹⁾

Micromirror (pixel) pitch - horizontal and vertical⁽¹⁾

Micromirror active array width

Micromirror active array height

Micromirror active border

µm

10.8

µm

(P × M) + (P / 2)

12.447

6.226

(P x N) / 2 + (P / 2)

Pond of micromirrors (POM) ⁽²⁾

micromirrors/side

(1) See 图6-13

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

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English Data Sheet: DLPS208

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图6-13. Micromirror Array Physical Characteristics

English Data Sheet: DLPS208

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6.11 Micromirror Array Optical Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

Micromirror tilt angle

DMD landed state⁽¹⁾

Micromirror tilt angle tolerance⁽²⁾

DMD efficiency⁽³⁾

–1

420 nm - 700 nm⁽⁴⁾

66%

Adjacent micromirrors

Non-adjacent micromirrors

micromirrors

Number of non-operational micromirrors⁽⁴⁾

(1) Measured relative to the plane formed by the overall micromirror array at 25°C.

(2) For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some

optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(3) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection

apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the

efficiency numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or

overfill loss. This number is measured under conditions described above and deviations from these specified conditions could result in

a different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application

include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as

LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well

as the DMD efficiency factors that are not system dependent are described in detail in DLPA083A

(4) A non-operational micromirror is defined as a micromirror that is unable to transition between the on-state and off-state positions.

6.12 Window Characteristics

PARAMETER

MIN

NOM

Corning Eagle XG

1.5119

MAX

UNIT

Window material designation

Window refractive index

Window aperture ⁽¹⁾

at wavelength 546.1 nm

See ⁽¹⁾

(1) See the mechanical package ICD for details regarding the size and location of the window aperture.

6.13 Chipset Component Usage Specification

The DLP5532-Q1 is a component of a chipset. Reliable function and operation of the DLP5532-Q1 requires that

it be used in conjunction with the TPS99000-Q1 and DLPC230-Q1, and includes components that contain or

implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices

used for operating or controlling a DLP DMD.

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

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7 Detailed Description

7.1 Overview

The DLP5532-Q1 Automotive DMD consists of 1,327,104 highly reflective, digitally switchable, micrometer-sized

mirrors organized in a two-dimensional array. As shown in Figure 6-13, the micromirror array consists of 1152

micromirror columns × 1152 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio.

Around the perimeter of the 1152 × 1152 array of micromirrors is a uniform band of border micromirrors called

the Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors

land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each

side of the 1152 × 1152 active array.

Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns

of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors

are illuminated from the bottom which allows for compact and efficient system optical design.

Although the native resolution of the DLP5532-Q1 is 1152 × 1152, when paired with the DLPC230-Q1 controller,

the DLP5532-Q1 can be driven with different resolutions to utilize the 2:1 aspect ratio. Please see the DLPC230-

Q1 automotive DMD controller data sheet (DLPS054) for a list of supported resolutions. Diamond pixel arrays

also have the capability to increase display resolution beyond native resolution. Future controllers or video

formatters may take advantage of this enhanced resolution.

7.2 Functional Block Diagram

English Data Sheet: DLPS208

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7.3 Feature Description

The DLP5532-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a sub-LVDS bus

from the DLPC230-Q1 and powered by the TPS99000-Q1. The temperature sensing diode is used to

continuously monitor the DMD array temperature.

To ensure reliable operation the DLP5532-Q1 must be used with the DLPC230-Q1 DMD display controller and

the TPS99000-Q1 system management and illumination controller.

7.3.1 Sub-LVDS Data Interface

The Sub-LVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously

maintaining low power and low emission.

Data is loaded into the SRAM under each micromirror using the sub-LVDS interface from the DLPC230-Q1. This

interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and B

loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data

rate (DDR) interface. The sub-LVDS interface also implements a continuous training algorithm to optimize the

data and clock timing to allow for a more robust interface.

The entire DMD array of 1.3 million pixels can be updated at a rate of less than 100 µs as a result of the high

speed sub-LVDS interface.

7.3.2 Low Speed Interface for Control

The purpose of the low speed interface is to configure the DMD at power up and power down and to control the

micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage

controls the time when the mirrors are mechanically switched. The low speed differential interface includes 2

pairs of signals for write data and clock, and 2 single-ended signals for output (A and B).

7.3.3 DMD Voltage Supplies

The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These

voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by

the TPS99000-Q1.

7.3.4 Asynchronous Reset

Reset of the DMD is required and controlled by the DLPC230-Q1 via the signal DMD_DEN_ARSTZ.

7.3.5 Temperature Sensing Diode

The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring

device. The DLPC230-Q1 monitors the temperature sense diode via the TMP411. The DLPC230-Q1 operation

of the DMD timing can be adjusted based on the DMD array temperature, therefore this connection is essential

to ensure reliable operation of the DMD.

图7-1 shows the typical connection between the DLPC230-Q1, TMP411, and the DMD.

56 ꢀ

TEMP_P

SCL

SCA

D+

SCA

100 pF

THERM1

THERM2

56 ꢀ

D-

TEMP_N

DLPC230-Q1

TMP411-Q1

GND

图7-1. Temperature Sense Diode Typical Circuit Configuration

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7.3.5.1 Temperature Sense Diode Theory

A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.

The diode is formed by connecting the transistor base to the collector. Three different known currents flow

through the diode and the resulting diode voltage is measured in each case. The difference in their base–

emitter voltages is proportional to the absolute temperature of the transistor.

Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.

图7-2 and 图7-3 illustrate the relationships between the current and voltage through the diode.

IE1

IE2

TEMP_N

VBE 1,2

TEMP_P

图7-2. Temperature Measurement Theory

100uA

10uA

1uA

Temperature (°C)

图7-3. Example of Delta VBE Versus Temperature

7.4 System Optical Considerations

Optimizing system optical performance and image performance strongly relates to optical system design

parameter trades. Although it is not possible to anticipate every conceivable application, projector image and

optical performance is contingent on compliance to the optical system operating conditions described in the

following sections.

7.4.1 Numerical Aperture and Stray Light Control

The numerical aperture of the illumination and projection optics at the DMD optical area should be the same.

This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless

appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light

from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from

any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces.

English Data Sheet: DLPS208

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7.4.2 Pupil Match

TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is

nominally centered and located at the entrance pupil position of the projection optics. Misalignment of pupils

between the illumination and projection optics can degrade screen image uniformity and cause objectionable

artifacts in the display’s border and/or active area. These artifacts may require additional system apertures to

control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.4.3 Illumination Overfill

Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and

other surfaces that surround the active array. These artifacts may be visible in the projected image. The

illumination optical system should be designed to minimize light flux incident outside the active array and on the

window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this

amount of overfill light on the area outside of the active array may still cause artifacts to be visible.

Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if

illumination light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load

on the aperture in the areas shown in 图 6-1 should not exceed the values listed in Recommended Operating

Conditions. This area is a 0.5-mm wide area the length of the aperture opening. The values listed in

Recommended Operating Conditions assume a uniform distribution. For a non-uniform distribution please

contact TI for additional information.

备注

TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES

CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED

PREVIOUSLY.

7.5 Micromirror Array Temperature Calculation

图7-4. DMD Thermal Test Points

The active array temperature can be computed analytically from measurement points on the outside of the

package, the package thermal resistance, the electrical power, and the illumination heat load.

Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in

图7-4) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

)

(1)

(2)

where

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• T_ARRAY= computed DMD array temperature (°C)

• T_CERAMIC= measured ceramic temperature, TP1 location in 图7-4 (°C)

• R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from array to thermal test point TP1 (°C/W), see

Thermal Information

• Q_ARRAY= total power, electrical plus absorbed, on the DMD array (W)

• Q_ELECTRICAL= nominal electrical power dissipation by the DMD (W)

• Q_ILLUMINATION= (C_L2W× SL)

• C_L2W= conversion constant for screen lumens to power on the DMD (W/lm)

• SL = measured screen lumens (lm)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies.

Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and

the intensity of the light source.

Equations shown above are valid for a 1–chip DMD system with a total projection efficiency from DMD to the

screen of 87%.

The constant C_L2Wis based on the DMD array characteristics. It assumes a spectral efficiency of 300 lm/W for

the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array border.

The following is a sample calculation for a typical projection application:

1. SL = 50 lm

2. C_L2W= 0.00293 W/lm

3. Q_ELECTRICAL= 0.4 W (This number does not represent an actual DMD electrical power; for illustration

purposes only)

4. R_{ARRAY–TO–CERAMIC}= 1.1°C/W

5. T_CERAMIC= 55°C

6. Q_ARRAY= 0.4 W + (0.00293 W/lm × 50 lm) = 0.5465 W

7. T_ARRAY= 55°C + (0.5465 W × 1.1°C/W) = 55.6°C

English Data Sheet: DLPS208

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7.6 Micromirror Landed-On/Landed-Off Duty Cycle

7.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the

time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90%

of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DLP5532-Q1 chipset is designed to support projection-based automotive applications such as window

display systems.

8.2 Typical Application

The chipset consists of three components—the DLP5532-Q1 automotive DMD, the DLPC230-Q1, and the

TPS99000-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images.

The DLPC230-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD

illumination sources and the DMD in order to display the incoming video. The TPS99000-Q1 is a controller for

the illumination sources (e.g. LEDs or lasers) and a management IC for the entire chipset. In conjunction, the

DLPC230-Q1 and the TPS99000-Q1 can also be used for system-level monitoring, diagnostics, and failure

detection features. Window Display System Block Diagram is a system level block diagram with these devices in

the window display configuration and shows the primary features and functions of each device.

VLED

6.5 V

Pre-

Regulator

6.5 V

1.1 V

1.8 V

3.3 V

Supplies for

DLPC230 and DMD

VBATT

reg

Reg

3.3 V

LDO

(optional)

Power sequencing

and monitoring

High-side current

limiting

PROJ_ON

Optional SPI Monitor

12 bit

ADC

External ADC inputs for

general usage

LM3409

LED drive

AC3

ADC_CTRL(2)

SPI(4)

SPI_2

shunt(2)

RED

MPU

WD(2)

LED_SEL(4)

SEQ_START

S_EN

Ultra wide dimming

LED controller

GREEN

SPI_1

ECC

Low-side current

measurement

HOST_IRQ

OpenLDI

CTRL

TPS99000-Q1

D_EN

DLPC230-Q1

Illumination

Optics

Host

photo diode

External watchdogs /

over brightness / and

other monitors

COMPOUT

SEQ_CLK

Parallel

DATA

eSRAM

frame buffer

General

Purpose

PARKZ

RESETZ

INTZ

Photo diode

PD neg

meas. system

LDO

I2C(2)

SPI(4)

I2C_0

SPI_0

BIAS, RST, OFS

(3)

Spare

GPIO

GPIOx

I2C_1

Sys clock

monitor

DMD bias

regulator

VCC_FLASH

VCC_INTF

3.3 V

1.8 V

1.1 V

EEPROM

VIO

TMP411

(2)

DMD die temperature

VCORE

DLP5532-Q1

DMD

Sub-LVDS

Interface

sub-LVDS DATA

Control

图8-1. Window Display System Block Diagram

English Data Sheet: DLPS208

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8.2.1 Application Overview

图 8-1 shows the system block diagram for a DLP window display system. The system uses the DLPC230-Q1,

TPS99000-Q1, and the DLP5532-Q1 automotive DMD to enable a window display with high brightness, high

efficiency, and a high resolution. The combination of the DLPC230-Q1 and TPS99000-Q1 removes the need for

external SDRAM and a dedicated microprocessor. The chipset manages the illumination control of LED sources,

power sequencing functions, and system management functions. Additionally, the chipset supports numerous

system diagnostic and built-in self test (BIST) features. The following paragraphs describe the functionality of the

chipset used for a window system in more detail.

The DLPC230-Q1 is a controller for the DMD and the light sources in the DLP window display module. It

receives input video from the host and synchronizes DMD and light source timing in order to achieve the desired

video. The DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes these video

segments with light source timing in order to create a video with grayscale shading and multiple colors, if

applicable.

The DLPC230-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input

video data. Host commands can be sent using either the I²C bus or SPI bus. The bus that is not being used for

host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an

OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits or 16-bits of data for single light

source or dual light source systems depending on the system design. The SPI flash memory provides the

embedded software for the DLPC230-Q1’s ARM core and default settings. The TPS99000-Q1 provides

diagnostic and monitoring information to the DLPC230-Q1 using an SPI bus and several other control signals

such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The TMP411 uses an

I²C interface to provide the DMD array temperature to the DLPC230-Q1.

The outputs of the DLPC230-Q1 are configuration and monitoring commands to the TPS99000-Q1, timing

controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics

information to the host processor. The DLPC230-Q1 communicates with the TPS99000-Q1 over an SPI bus. It

uses this to configure the TPS99000-Q1 and to read monitoring and diagnostics information from the TPS99000-

Q1. The DLPC230-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD

mirror timing. The control signals to the DMD are sent using a sub-LVDS interface.

The TPS99000-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and

diagnostics information for the DLP window display module. The power sequencing and monitoring blocks of the

TPS99000-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V),

and then monitor the system’s power rails during operation. The integration of these functions into one IC

significantly reduces design time and complexity. The TPS99000-Q1 also has several output signals that can be

used to control a variety of LED or laser driver topologies. The TPS99000-Q1 has several general-purpose

ADCs that designers can use for system level monitoring, such as over-brightness detection.

The TPS99000-Q1 receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and

potentially several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the

TPS99000-Q1 over an SPI bus and several other control signals. The DLPC230-Q1’s clocks are also

monitored by the watchdogs in the TPS99000-Q1 to detect any errors. The power rails are monitored by the

TPS99000-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case

of an error. The host processor can read diagnostics information from the TPS99000-Q1 using a dedicated SPI

bus, which enables independent monitoring. Additionally the host can request the image to be turned on or off

using a PROJ_ON signal. Lastly, the TPS99000-Q1 has several general-purpose ADCs that can be used to

implement system level monitoring functions.

The outputs of the TPS99000-Q1 are diagnostic information and error alerts to the DLPC230-Q1, and control

signals to the LED or laser driver. The TPS99000-Q1 can output diagnostic information to the host and the

DLPC230-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the

DLPC230-Q1 that trigger power down or reset sequences. It also has output signals that can be used to

implement various LED or laser driver topologies.

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The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video

data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS

interface with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD

array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.

8.2.2 Reference Design

For information about connecting together the DLP5532-Q1 DMD, DLPC230-Q1 controller, and TPS99000-Q1 ,

please contact the TI Application Team for additional information about the DLP5532-Q1 evaluation module

(EVM). TI has optical-mechanical reference designs available, see the TI Application team for more information.

8.2.3 Application Mission Profile Consideration

Each application is anticipated to have different mission profiles, or number of operating hours at different

temperatures. To assist in evaluation the Application Report Reliability Lifetime Estimates for DLP3030-Q1 and

DLP553x-Q1 DMDs in Automotive Applications may be provided. See the TI Application team for more

information.

English Data Sheet: DLPS208

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.

All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the

TPS99000-Q1 device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-

up and power-down operations. Failure to meet any of the below requirements will result in a

significant reduction in the DMD’s reliability and lifetime. VSS must also be connected.

9.1 Power Supply Power-Up Procedure

• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in the 节6.4.

• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have

settled at operating voltage.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in 图9-1.

9.2 Power Supply Power-Down Procedure

• The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended

Operating Conditions (Refer to Note 2 in 节9.3).

• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the

Recommended Operating Conditions.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 节9.3.

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9.3 Power Supply Sequencing Requirements

A. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in the Recommended Operating

Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to

remove VBIAS prior to VOFFSET during power-down. Also, the TPS99000-Q1 is capable of managing the timing between VBIAS and

VOFFSET.

B. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified than the limit shown in the

Recommended Operating Conditions.

C. When system power is interrupted, the TPS99000-Q1 initiates hardware power-down that disables VBIAS, VRESET and VOFFSET

after the Micromirror Park Sequence.

D. Drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

English Data Sheet: DLPS208

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10 Layout

10.1 Layout Guidelines

Please refer to the DLPC230-Q1 and TPS99000-Q1 data sheets for specific PCB layout and routing guidelines.

For specific DMD PCB guidelines, use the following:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals.

• Minimum of two 220-nF decoupling capacitors close to VBIAS.

• Minimum of two 220-nF decoupling capacitors close to VRESET.

• Minimum of two 220-nF decoupling capacitors close to VOFFSET.

• Minimum of four 100-nF decoupling capacitors close to VDDI and VDD.

• Temperature diode pins

The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411

temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to

noise. Please see the TMP411 data sheet for specific routing recommendations.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

DLP5532 A FYS Q1

Automotive

Package Type

Temperature Rating (-40°C to 105°C)

Device Descriptor

图11-1. Part Number Description

11.1.2 Device Markings

The device marking includes the legible character string GHJJJJK DLP5532AFYSQ1. GHJJJJK is the lot trace

code. DLP5532AFYSQ1 is the part number.

TI Internal Numbering

Part 2 of Serial Number

(7 Characters)

Part 1 of Serial Number

(7 Characters)

2-Dimension Matrix Code

DMD Part Number

(Part Number and Serial Number)

图11-2. DMD Marking

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

TI DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

English Data Sheet: DLPS208

Submit Document Feedback

Product Folder Links: DLP5530S-Q1

DLP5530S-Q1

ZHCSMN0 –JUNE 2021

www.ti.com.cn

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 DMD Handling

The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see

the application note DLPA019 DMD Handling for instructions on how to properly handle the DMD.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: DLP5530S-Q1

English Data Sheet: DLPS208

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP5532AFYSQ1

ACTIVE

CPGA

FYS

149

RoHS & Green

Call TI

N / A for Pkg Type

-40 to 105

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2516726

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

ECO 2182382: INITIAL RELEASE

ECO 2182408: CHANGE APERTURE TOP EDGE SHAPE

ECO 2187769: CHG APER TOP EDGE SHAPE & LOCATION

DATE

7/17/2019

7/26/2019

5/14/2020

BMH

SUBSTRATE EDGE PERPENDICULARITY TOLERANCE APPLIES TO ENTIRE SURFACE.

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM VALUE OF 0.8 DEGREES.

SUBSTRATE SYMBOLIZATION PAD AND PLATING AT BOTTOM OF DATUMS B AND C

HOLES TO BE ELECTRICALLY CONNECTED TO VSS PLANE WITHIN THE SUBSTRATE.

BOUNDARY MIRRORS SURROUNDING THE ACTIVE ARRAY.

MAXIMUM ENCAPSULANT PROFILE SHOWN.

ENCAPSULANT ALLOWED ON THE SURFACE OF THE CERAMIC IN THE AREA SHOWN

IN VIEW B (SHEET 2). ENCAPSULATION SHALL NOT EXCEED 0.2 THICKNESS MAXIMUM.

INDICATED CERAMIC SUBSTRATE FEATURES TO BE PLATED WITH 0.3 MICROMETERS

MINIMUM ELECTROLYTIC GOLD OVER 0.1 MICROMETER MINIMUM PALLADIUM OVER

1.27-8.89 MICROMETERS ELECTROLYTIC NICKEL PER ASTM B488-01, ASTM

B679-95(2009), AND AMS-QQ-N-290, RESPECTIVELY.

0.2E



SEE VIEW E (SHEET 3)

FOR WINDOW AND ACTIVE

ARRAY DIMENSIONS

NOTE THAT THE LOCATION OF THE ACTIVE ARRAY CENTER FOR THIS DMD IS THE SAME

AS THE AUTOMOTIVE DLP5530-Q1 AND DLP5531-Q1 DMD'S, BUT IS NOT CONSISTENT

WITH ALL OTHER SERIES 450 DMD'S.

3 0.5

(Ø2)

0.0750.15

3 0.5

22.30.22

13.0340.15

(1.5)

3.780.15

20.440.15

32.20.32

SUBSTRATE

INCIDENT

LIGHT

ENCAPSULANT

(0.36)

WINDOW

WINDOW APERTURE

3 PLACES

0.8 MAX

INDICATED

(SHEET 2)

1.1 0.05

1.41 0.077

0.0254A

2.925 0.24



1.050.1

0.02G

(0.31)

(0.75)

ACTIVE ARRAY

149X 1.4 0.1

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TEXAS

7/17/2019

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

TOLERANCES:

Dallas Texas

7/17/2019

7/18/2019

7/17/2019

ANGLES 1

TITLE

(Ø0.305)

ICD, MECHANICAL, DMD

.55 2:1 1.3MP SERIES 450 -A1

(FYS PACKAGE)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

SECTION A-A

P. KONRAD

SCALE 20 : 1

M. LOPEZ

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

NONE

NEXT ASSY

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

J. McKINLEY

APPROVED

B. RAY

2516726

SCALE

SHEET

APPLICATION

4:1

INV2013-DLPa

DWG NO.

2516726

0.5 MIN

(Ø2)

1.840.13

280.28

(DATUM B TO CENTER OF DATUM C SLOT)

25.7 MAX

2.1 0.15

2.3 MIN

ENCAPSULANT ALLOWED

ON CERAMIC AREA

2±0.05

SECTION C-C

DATUM B

SCALE 16 : 1

5.150.15

2.9

23.2° 1°

120.12

14.9

0.5 MIN

(1.5)

3X 4

1.840.13

1.5 0.05

0.750.025

1 0.1

WINDOW

SECTION D-D

DATUM C

0.5 0.05

(VIEW ROTATED FOR CLARITY)

SCALE 16 : 1

2X 28

(DATUM B TO A2 AND A3)

VIEW B

DATUMS AND ENCAPSULANT ALLOWABLE AREA

SCALE 10 : 1

DWG NO

REV

SIZE

DRAWN

DATE

7/17/2019

TEXAS

2516726

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

DWG NO.

2516726

(2.1)

(12.447)

ACTIVE ARRAY

7.7760.076

4X (0.108)

(Ø2)

(5.15)

1.0870.05

0.3160.0885

2.8870.076

(7.022)

(9.359)

WINDOW

(6.2262)

ACTIVE ARRAY

WINDOW

APERTURE

6.7060.0885

8.2720.05

(1.5)

0.604 0.0885

1.2390.05

13.0510.0885

(13.655)

WINDOW APERTURE

13.6860.05

(14.925)

WINDOW

VIEW E

ACTIVE ARRAY AND WINDOW

SCALE 12 : 1

DWG NO

REV

SIZE

DRAWN

DATE

7/17/2019

TEXAS

2516726

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

DWG NO.

2516726

19.145

9 X 1.27 = 11.43

1.625

(A1, A2, & B1 OMITTED)

1.625

3.8950.25

14.510.25

15 X 1.27 = 19.05

SYMBOLIZATION

PAD

0.05

8.5 0.25

11.85 0.25

149X 0.305

0.5DEF

PINS

0.025



0.25D

VIEW F

PINS AND SYMBOLIZATION PAD

SCALE 8 : 1

0.28 MAX

(BRAZE AREA)

Ø0.85 MAX

(BRAZE AREA)

(R0.05)

(Ø0.305)

(1.4)

DETAIL G

PIN AND BRAZE DIMENSIONS

149 PLACES

SCALE 40 : 1

DWG NO

REV

SIZE

DRAWN

DATE

7/17/2019

TEXAS

2516726

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV2013-DLPa

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DLP5532AFYSQ1 [TI]

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