DLP7000BFLP_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

DLP7000 DLP^®0.7 XGA 2x LVDS A 型 DMD

1 特性

–

3D 生物识别

共焦显微镜

1

•

0.7 英寸对角线微镜阵列

•

显示

–

1024 × 768 铝制微米级微镜阵列

13.68µm 微镜间距

–

3D 成像显微镜

自适应照明

±12° 微镜倾斜角（相对于平面）

设计用于角落照明

增强现实和信息覆盖

用于可见光（400nm 至 700nm）：

3 说明

–

窗透射率为 97%（单通，两个窗面）

微镜反射率为 88%

DLP7000 XGA 芯片组是 DLP^®Discovery™4100 平台

的一部分，用于实现高分辨率、高性能的空间照明调

制。0.7 XGA 芯片组的基础是一款数字微镜器件

(DMD) DLP7000，这款器件是目前 DLP 系列产品组合

中模式速率最快的一款。DLP Discovery 4100 平台还

提供带有随机行寻址的最高级独立微镜控制。除了采用

密封封装外，DLP7000 具有独特的功能和价值，非常

适合支持各种工业、医疗和高级显示应用。

阵列衍射效率为 86%

阵列填充系数为 92%

两条 16 位低电压差分信令 (LVDS) 双倍数据速率

(DDR) 输入数据总线

•

输入数据时钟速率高达 400MHz

40.64mm × 31.75mm × 6.0mm 封装

密封封装

除了 DLP7000 DMD 外，0.7XGA 芯片组还包括以下

组件：

2 应用

•

工业

•

DLPC410 控制器，专用于 32000Hz（1 位二进

制）和 4000Hz（8 位灰度）以上的高速图形速率

一个 DLPR410（DLP Discovery 4100 配置

PROM）

–

数字成像印刷

激光打标

LCD 和 OLED 修复

计算机直接制版打印机

SLA 3D 打印机

一个 DLPA200（DMD 微镜驱动器）

器件信息⁽¹⁾

器件型号

DLP7000

封装

封装尺寸（标称值）

适用于机器视觉和工厂自动化的 3D 扫描仪

平板印刷

将 FLP (203)

40.64mm × 31.75mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

•

医疗

–

光照治疗设备

眼科

直接制造

高光谱成像

简化应用

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS026

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 23

8.3 Feature Description................................................. 25

8.4 Device Functional Modes........................................ 32

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 5

Pin Configuration and Functions......................... 5

Specifications....................................................... 12

7.1 Absolute Maximum Ratings .................................... 12

7.2 Storage Conditions.................................................. 12

7.3 ESD Ratings............................................................ 12

7.4 Recommended Operating Conditions..................... 13

7.5 Thermal Information................................................ 14

7.6 Electrical Characteristics......................................... 15

7.7 LVDS Timing Requirements ................................... 16

7.8 LVDS Waveform Requirements.............................. 16

7.9 Serial Control Bus Timing Requirements................ 16

7.10 Systems Mounting Interface Loads....................... 19

7.11 Micromirror Array Physical Characteristics........... 20

7.12 Micromirror Array Optical Characteristics ............. 21

7.13 Window Characteristics......................................... 22

7.14 Chipset Component Usage Specification ............. 22

Detailed Description ............................................ 23

8.1 Overview ................................................................. 23

8.5 Optical Interface and System Image Quality

Considerations ........................................................ 34

8.6 Micromirror Array Temperature Calculation............ 35

8.7 Micromirror Landed-On/Landed-Off Duty Cycle ..... 37

Application and Implementation ........................ 40

9.1 Application Information............................................ 40

9.2 Typical Application .................................................. 41

9

10 Power Supply Recommendations ..................... 44

10.1 DMD Power-Up and Power-Down Procedures..... 44

11 Layout................................................................... 44

11.1 Layout Guidelines ................................................. 44

11.2 Layout Example .................................................... 45

12 器件和文档支持 ..................................................... 47

12.1 器件支持................................................................ 47

12.2 文档支持................................................................ 47

12.3 相关链接................................................................ 48

12.4 商标....................................................................... 48

12.5 静电放电警告......................................................... 48

12.6 Glossary................................................................ 48

13 机械、封装和可订购信息....................................... 48

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (May 2017) to Revision F

Page

•

已删除 “宽带” .......................................................................................................................................................................... 1

已更改更改了高速图形速率的数值......................................................................................................................................... 1

已更改封装类型更改为 FLP (203).......................................................................................................................................... 1

Changed package type to FLP; deleted reference to LCCC ................................................................................................. 5

Changed FLP package figure "bottom view".......................................................................................................................... 5

Changed "Case temperature" to "Array temperature" ......................................................................................................... 12

Changed "Device temperature gradient - operational" to "Absolute temperature delta between the window test

points (TP2, TP3) and the ceramic test point TP1" ............................................................................................................. 12

•

Deleted "RH" after "%" ........................................................................................................................................................ 12

Changed "Applicable before the DMD is installed in the final product" to "Applicable for the DMD as a component or

non-operating system".......................................................................................................................................................... 12

•

Changed ", non-condensing" to "(non-condensing)" ........................................................................................................... 12

Changed "JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control

process." to "JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD

control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken." .................... 12

•

Changed Table "Recommended Operating Conditions" ...................................................................................................... 13

Added "RH" under "Environmental" ..................................................................................................................................... 13

Added cross reference to table note at row "ILL_VIS" ............................................................................................................ 13

Changed Array temperature, Long-term operational MAX from "30" to "40" ....................................................................... 13

Changed package type to FLP in table "THERMAL METRIC" ............................................................................................ 14

Added "or the combined loads of the thermal and electrical areas reduced" ...................................................................... 19

2

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

修订历史记录 (接下页)

•

Deleted row "Window artifact size" in table "Window Characteristics"................................................................................. 22

Changed mirror pitch to 13.68 μm........................................................................................................................................ 25

Changed figure "DLPC410 Data Flow" to correct signals of LVDS BUS B out.................................................................... 27

Changed "Window Characteristics and Optics" to "Optical Interface and System Image Quality Considerations" ............ 34

Changed "a Thermal Test Point locations 1 and 2" to "thermal test points TP1, TP2, and TP3" ........................................ 35

Added "(typically used for display applications)" to "Micromirror Array Temperature Calculation - Lumens based" .......... 36

Deleted Subsection "Fiducials" ............................................................................................................................................ 44

Changes from Revision D (November 2015) to Revision E

Page

•

Clarified T_GRADIENTfootnote................................................................................................................................................... 12

Changed TC2 to TP1 to follow latest thermal test point nomenclature convention in Thermal Information ........................ 14

Changed Micromirror active border from 10 to correct value of 6 ....................................................................................... 20

Changed micromirror crossover to mean transition time and renamed previous crossover to micromirror switching

time typical micromirror crossover time typo (16 µs to 13 µs).............................................................................................. 21

•

Added typical micromirror switching time - 13 µs................................................................................................................. 21

Changed "Micromirror switching time" to "Array switching time" for clarity ......................................................................... 21

Added clarification to Micromirror switching time at 400 MHz with global reset ................................................................. 21

Changed references to D4100 Discovery to DPC410 ......................................................................................................... 23

Changed Thermal Test Point Location drawing to current numbering convention ............................................................. 35

Changed Micromirror Array Temperature Calculations to indicate that it is based on lumens ............................................ 36

Added Micromirror Array Temperature Calculation based on power ................................................................................... 37

更新了图 22 .......................................................................................................................................................................... 47

删除了 DLP Discovery 4100 芯片组数据表的链接................................................................................................................ 47

已添加 “将 DLPR410 添加到了“相关链接”表......................................................................................................................... 48

Changes from Revision C (April 2014) to Revision D

Page

•

更新了器件命名规则的图 21 和图........................................................................................................................................ 47

更新了器件标记的图 22 和图............................................................................................................................................... 47

Changes from Revision B (June 2013) to Revision C

Page

•

已添加添加了引脚配置和功能部分、ESD 额定值表、特性说明部分、器件功能模式、应用和实施部分、电源相关

建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................. 1

已删除芯片组列表中的 /DLPR4101 增强型 PROM ............................................................................................................... 1

Corrected VCC2 max to 8 V ................................................................................................................................................ 12

Added array temperature vs duty cycle graph...................................................................................................................... 14

Replaced serial communications bus timing parameters ..................................................................................................... 18

Converted interface loads to Newtons.................................................................................................................................. 19

Grayed out LVDS buses that are unused on DLP7000 ....................................................................................................... 27

Added micromirror landed duty cycle section....................................................................................................................... 37

Changed to DLP7000 ........................................................................................................................................................... 42

已删除从相关文档中删除了 / DLPR4101 增强型 PROM ..................................................................................................... 47

•

3

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Changes from Revision A (September 2012) to Revision B

Page

•

已添加 /DLPR4101 增强型 PROM 至芯片组列表中的 DLPR410 部分................................................................................... 1

Changed pin number of DCLK_AN From: D19 To: B22 ....................................................................................................... 9

Changed pin number of DCLK_AP From: E19 To: B24 ........................................................................................................ 9

Changed pin number of DCLK_BN From: M19 To: AB22 ..................................................................................................... 9

Changed pin number of DCLK_BP From: N19 To: AB24 ..................................................................................................... 9

已添加将 / DLPR4101 增强型 PROM 添加至相关文档中的 DLPR410 部分 ....................................................................... 47

Changes from Original (August 2012) to Revision A

Page

•

将器件状态从“产品预览”更改成了“生产” ................................................................................................................................. 1

4

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

5 说明（续）

DLP7000 需要与芯片组的其他元件结合使用才能实现可靠功能和操作。一套专用的芯片组能够使开发人员更加轻

松地访问 DMD 并使用高速而独立的微镜控制。

DLP7000 是一款数控微光机电系统 (MEMS) 空间照明调制器 (SLM)。当与适当的光系统成对使用时，DLP7000 能

够可用于调制进入光的振幅、方向和/或相位。

电子方面，DLP7000 由 1 位 CMOS 内存单元的两维阵列组成，其组织结构为 1024 内存单元列乘以 768 内存单元

行的栅格。CMOS 存储器阵列通过两条 16 位低压差分信令 (LVDS) 双倍数据速率 (DDR) 总线逐行进行寻址。寻址

由一个串行控制总线处理。特定的 CMOS 存储器访问协议由 DLPC410 数字控制器处理。

6 Pin Configuration and Functions

FLP Package

203-Pin CLGA

Bottom View

15

9

29 27 25 23 21 19 17

13 11

7

5

3

1

30 26 24 22 20 18 16 14 12 10

8

2

28

6

4

A

C

E

B

D

F

G

J

H

K

M

P

T

L

N

R

U

W

AA

V

Y

AB

AC

5

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

TRACE

Pin Functions

PIN⁽¹⁾

TYPE

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

(I/O/P)

RATE⁽²⁾

NAME

NO.

DATA INPUT

Differential

Terminated -

100 Ω

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

D_AP(0)

D_AP(1)

B10

A13

D16

C17

B18

A17

A25

D22

C29

D28

E27

F26

G29

H28

J27

Input

LVCMOS

DDR

DCLK_A

368.72

424.61

433.87

391.39

438.57

391.13

563.26

411.62

595.11

543.07

455.98

359.5

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus A

(2x LVDS)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

542.67

551.51

528.04

484.38

366.99

417.47

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

K26

B12

A11

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.

(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.

(3) Refer to Electrical Characteristics for differential termination specification.

6

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Pin Functions (continued)

PIN⁽¹⁾

TYPE

(I/O/P)

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

TRACE

RATE⁽²⁾

NAME

NO.

Differential

Terminated -

100 Ω

D_AP(2)

D14

Input

LVCMOS

DDR

DCLK_A

434.89

Differential

Terminated -

100 Ω

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

C15

B16

A19

A23

D20

A29

B28

C27

D26

F30

LVCMOS

DCLK_A

DCLK_B

394.67

437.3

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

389.01

562.92

410.34

594.61

539.88

456.78

360.68

543.97

570.85

527.18

481.02

368.72

424.61

433.87

391.39

438.57

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus A -

continued (2x

LVDS)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

H30

J29

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

K28

AB10

AC13

Y16

AA17

AB18

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus B

(2x LVDS)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

7

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

PIN⁽¹⁾

TYPE

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

TRACE

(I/O/P)

RATE⁽²⁾

NAME

NO.

Differential

Terminated -

100 Ω

D_BN(5)

AC17

Input

LVCMOS

DDR

DCLK_B

391.13

Differential

Terminated -

100 Ω

D_BN(6)

D_BN(7)

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

AC25

Y22

Input

DCLK_B

563.26

411.62

595.11

543.07

455.98

360.94

575.85

519.37

532.59

441.14

366.99

417.47

434.89

394.67

437.3

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

AA29

Y28

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

W27

V26

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

T30

Differential

Terminated -

100 Ω

R29

Differential

Terminated -

100 Ω

Input data bus B -

continued (2x

LVDS)

R27

Differential

Terminated -

100 Ω

N27

Differential

Terminated -

100 Ω

AB12

AC11

Y14

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

AA15

AB16

AC19

AC23

Y20

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

389.01

562.92

410.34

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

8

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Pin Functions (continued)

PIN⁽¹⁾

TYPE

(I/O/P)

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

TRACE

RATE⁽²⁾

NAME

NO.

Differential

Terminated -

100 Ω

D_BP(8)

AC29

Input

LVCMOS

DDR

DCLK_B

594.61

Differential

Terminated -

100 Ω

D_BP(9)

AB28

AA27

Y26

LVCMOS

DCLK_B

539.88

456.78

360.68

578.46

509.74

534.59

440

Differential

Terminated -

100 Ω

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

Differential

Terminated -

100 Ω

Input data bus B -

continued (2x

LVDS)

Differential

Terminated -

100 Ω

U29

T28

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

P28

Differential

Terminated -

100 Ω

D_BP(15)

P26

DATA CLOCK

DCLK_AN

Differential

Terminated -

100 Ω

B22

B24

Input

LVCMOS

–

477.1

477.14

477.07

477.14

DCLK for data

bus A (2x LVDS)

Differential

Terminated -

100 Ω

DCLK_AP

DCLK_BN

DCLK_BP

Differential

Terminated -

100 Ω

AB22

AB24

DCLK for data

bus B (2x LVDS)

Differential

Terminated -

100 Ω

DATA CONTROL INPUTS

Differential

Terminated -

100 Ω

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

C21

C23

Input

LVCMOS

DDR

DCLK_A

DCLK_B

477.07

477.14

477.07

477.14

Serial control for

data bus A (2x

LVDS)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

AA21

AA23

Serial control for

data bus B (2x

LVDS)

Differential

Terminated -

100 Ω

SERIAL COMMUNICATION AND CONFIGURATION

SCPCLK

SCPDO

SCPDI

E3

B2

F4

D4

C3

Input

Output

Input

LVCMOS

–

Pull-down

–

Serial port clock

Serial port output

Serial port input

Serial port enable

Device Reset

379.29

480.91

323.56

326.99

406.28

SCPCLK

–

Pull-down

SCPENZ

PWRDNZ

Input

9

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

TRACE

Pin Functions (continued)

PIN⁽¹⁾

TYPE

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

(I/O/P)

RATE⁽²⁾

NAME

NO.

Data bandwidth

mode select A

MODE_A

D8

Input

LVCMOS

–

Pull-down

–

396.05

208.86

Data bandwidth

mode select B

MODE_B

C11

Input

MICROMIRROR BIAS CLOCKING PULSE

MBRST(0)

MBRST(1)

MBRST(2)

MBRST(3)

MBRST(4)

MBRST(5)

MBRST(6)

MBRST(7)

MBRST(8)

MBRST(9)

MBRST(10)

MBRST(11)

MBRST(12)

MBRST(13)

MBRST(14)

MBRST(15)

POWER

P2

AB4

AA7

N3

Input

Analog

–

M4

AB6

AA5

L3

Micromirror Bias

Clocking Pulse

"MBRST" signals

"clock"

micromirrors into

state of LVCMOS

memory cell

Y6

K4

associated with

each mirror.

L5

AC5

Y8

J5

K6

AC7

A7, A15,

C1, E1, U1,

W1, AB2,

Power for

LVCMOS Logic

V_CC

Power

Analog

–

AC9, AC15

A21, A27,

D30, M30,

Y30, AC21,

AC27

Power supply for

LVDS Interface

V_CC1

Power

Analog

–

Power for High

Voltage CMOS

Logic

G1, J1, L1,

N1, R1

V_CC2

10

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Pin Functions (continued)

PIN⁽¹⁾

TYPE

(I/O/P)

DATA

INTERNAL

TERM⁽³⁾

SIGNAL

CLOCK

DESCRIPTION

TRACE

RATE⁽²⁾

NAME

NO.

A1, A3, A5,

A9, B4, B8,

B14, B20,

B26, B30,

C7, C13,

C19, C25,

D6, D12,

D18, D24,

E29, F2,

F28, G3,

G27, H2,

H4, H26, J3,

J25, K2,

K30, L25,

L27, L29,

M2, M6,

M26, M28,

N5, N25,

N29, P4,

P30, R3,

R5, R25,

T2, T26,

Common return

for all power

inputs

V_SS

Power

Analog

–

U27, V28,

V30, W5,

W29, Y4,

Y12, Y18,

Y24, AA3,

AA9, AA13,

AA19,

AA25, AB8,

AB14,

AB20,

AB26, AB30

RESERVED SIGNALS (NOT FOR USE IN SYSTEM)

RESERVED

_AA1

Pins should be

connected to VSS

AA1

B6

Input

LVCMOS

–

Pull-down

–

RESERVED

_B6

–

RESERVED

_T4

T4

RESERVED

_U5

U5

AA11, AC3,

C5, C9,

D10, D2,

NO_CONN

ECT

E5, G5, H6,

P6, T6, U3,

V2, V4, W3,

Y10, Y2

–

Do not connect

–

11

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

ELECTRICAL

(2) (3)

V_CC

Voltage applied to V_CC

Voltage applied to V_CCI

–0.5

4

8

V

(2) (3)

V_CCI

V_CC2

(2) (3) (4)

Voltage applied to V_VCC2

Micromirror Clocking Pulse Waveform Voltage applied to MBRST[15:0]

Input Pins (supplied by DLPA200)

V_MBRST

–28

28

V

(4)

|V_CC– V_CCI

|

Supply voltage delta (absolute value)

0.3

V

Voltage applied to all other input pins⁽²⁾

–0.5

V_CC+ 0.3

Maximum differential voltage, damage can occur to internal termination

resistor if exceeded, see Figure 3

|V_ID

I_OH

I_OL

|

700

–20

15

mV

mA

Current required from a high-level

V_OH= 2.4 V

V_OL= 0.4 V

output

Current required from a low-level

output

ENVIRONMENTAL

Array temperature: operational⁽⁵⁾

Array temperature: non-operational⁽⁵⁾

10

65

80

°C

T_ARRAY

–40

Absolute temperature delta between the window test points (TP2, TP3)

and the ceramic test point TP1⁽⁶⁾

T_DELTA

RH

10

95

°C

%

Operating relative humidity (non-condensing)

0

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS(ground).

(3) VOFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |V_CC– V_CCI| must be less than specified limit.

(5) DMD Temperature is the worst-case of any test point shown in Figure 18, or the active array as calculated by the Micromirror Array

Temperature Calculation.

(6) As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point

inside the micromirror array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.

7.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system

MIN

MAX

80

UNIT

°C

Storage temperature

–40

T_stg

Storage humidity (non-condensing)

95

%

7.3 ESD Ratings

VALUE

UNIT

All pins except MBRST[15:0]

Pins MBRST[15:0]

±2000

±250

Electrostatic

V_(ESD)

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

V

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible if necessary precautions are taken.

12

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

UNIT

(2) (3)

ELECTRICAL

V_CC

Supply voltage for LVCMOS core logic

Supply voltage for LVDS receivers

3.0

3.3

7.5

3.6

V

V_CC1

V_CC2

Mirror electrode and HVCMOS supply voltage

7.25

7.75

Clocking Pulse Waveform Voltage applied to MBRST[29:0] Input Pins (supplied by

DLPA200s)

VMBRST

-27

26.5

0.3

V

(4)

|VCCI–VCC|

Supply voltage delta (absolute value)

ENVIRONMENTAL

RH

Operating relative humidity (non-condensing)

95

%

ENVIRONMENTAL ⁽⁵⁾For Illumination Source Between 420 nm and 700 nm

(6)(7) (8)(9)

(10)

Array temperature, Long–term operational

10

0

25-45

65

T_ARRAY

°C

(6)(7) (11)

Array temperature, Short–term operational

10

65

T_WINDOW

|T_DELTA

ILL_VIS

Window Temperature test points TP2 and TP3, Long-term operational⁽⁹⁾

10

°C

Absolute Temperature delta between the window test points (TP2, TP3) and the

ceramic test point TP1.⁽¹²⁾

|

10

Thermally

limited

Illumination⁽¹³⁾

W/cm²

ENVIRONMENTAL ⁽⁵⁾For Illumination Source Between 400 nm and 420 nm

(6)(7) (8)(9)

T_ARRAY

Array temperature, Long–term operational

20

30

°C

T_WINDOW

Window Temperature test points TP2 and TP3, Long-term operational⁽⁹⁾

Absolute Temperature delta between the window test points (TP2, TP3) and the

ceramic test point TP1.⁽¹²⁾

|T_DELTA

|

10

°C

W/cm²

W

11

ILL

Illumination⁽¹³⁾

16.2

ENVIRONMENTAL ⁽⁵⁾For Illumination Source <400 nm and >700 nm

(6)(7) (8)(9)

(10)

Array temperature, Long–term operational

20

0

40

T_ARRAY

°C

(6)(7) (11)

Array temperature, Short–term operational

20

65

10

T_WINDOW

ILL

Window Temperature test points TP2 and TP3, Long-term operational⁽⁹⁾

Illumination⁽¹³⁾

10

°C

mW/cm²

(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(2) Voltages V_CC, V_CC1, and V_CC2are required for proper DMD operation. V_SSmust also be connected.

(3) All voltages are referenced to common ground V_SS

.

(4) Exceeding the recommended allowable absolute voltage difference between V_CCand V_CC1may result in excess current draw. The

difference between VCC and V_CC1, |V_CC– V_CC1|, should be less than the specified limit.

(5) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application

parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage

and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that

application-specific effects be considered as early as possible in the design cycle.

(6) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array

Temperature Calculation for further details.

(7) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in Figure 18 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation.

(8) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will

reduce device lifetime.

(9) Long-term is defined as the usable life of the device.

(10) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty

cycle.

(11) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is

defined as cumulative time over the usable life of the device and is less than 500 hours.

(12) The temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in

Figure 18.

(13) Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range.

13

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Figure 1. Max Recommended DMD Temperature – Derating Curve

7.5 Thermal Information

DLP7000

FLP (Package)

203 PINS

0.90

THERMAL METRIC

Thermal resistance, active area to TP1⁽¹⁾

UNIT

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate

heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the

Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area;

although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical

systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in

this area can significantly degrade the reliability of the device.

14

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

7.6 Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted).

PARAMETERS

High-level output voltage⁽¹⁾

See Figure 11

TEST CONDITIONS

V_CC= 3.0 V, I_OH= –20 mA

MIN

NOM

MAX

UNIT

,

V_OH

V_OL

2.4

V

Low-level output voltage⁽¹⁾

See Figure 11

,

V_CC= 3.6 V, I_OH= 15 mA

0.4

V

Clocking Pulse Waveform applied to

V_MBRSTMBRST[29:0] Input Pins (supplied

by DLPA200)

–27

26.5

I_OZ

I_OH

I_OL

High impedance output current⁽¹⁾

V_CC= 3.6 V

10

–20

µA

V_OH= 2.4 V, V_CC≥ 3 V

V_OH= 1.7 V, V_CC≥ 2.25 V

V_OL= 0.4 V, V_CC≥ 3 V

V_OL= 0.4 V, V_CC≥ 2.25 V

High-level output current⁽¹⁾

mA

–15

15

Low-level output current⁽¹⁾

mA

14

V_IH

V_IL

I_IL

High-level input voltage⁽¹⁾

Low-level input voltage⁽¹⁾

Low-level input current⁽¹⁾

High-level input current⁽¹⁾

Current into V_CCpin

1.7

VCC + .3

0.7

V

–0.3

V_CC= 3.6 V, V_I= 0 V

V_CC= 3.6 V, V_I= V_CC

V_CC= 3.6 V

–60

µA

mA

Ω

I_IH

200

I_CC

I_CCI

I_CC2

Z_IN

1475

450

Current into V_CCIpin⁽²⁾

V_CCI= 3.6 V

Current into V_CC2pin

V_CC2= 8.75 V

25

Internal Differential Impedance

95

90

105

Line Differential Impedance (PWB,

Trace)

Z_LINE

100

110

Ω

C_I

Input capacitance⁽¹⁾

Output capacitance⁽¹⁾

f = 1 MHz

10

pF

C_O

C_IM

Input capacitance for MBRST[29:0]

pins

f = 1 MHz

220

270

pF

(1) Applies to LVCMOS pins only.

(2) Exceeding the maximum allowable absolute voltage difference between V_CCand V_CCImay result in excess current draw. See the

Absolute Maximum Ratings for details.

15

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

7.7 LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted). See Figure 2

MIN

200

2.5

NOM

MAX

UNIT

MHz

ns

f_{DCLK_*}

DCLK_* clock frequency {where * = [A, or B]}

Clock Cycle - DLCK_*

400

t_c

t_w

Pulse Width - DLCK_*

1.25

ns

t_s

Setup Time - D_*[15:0] and SCTRL_* before DCLK_*

Hold Time, D_*[15:0] and SCTRL_* after DCLK_*

Skew between bus A and B

0.35

ns

t_h

ns

t_skew

–1.25

1.25

ns

7.8 LVDS Waveform Requirements

over operating free-air temperature range (unless otherwise noted). See Figure 3

MIN

NOM

400

MAX

UNIT

mV

ps

|V_ID

|

Input Differential Voltage (absolute difference)

Common Mode Voltage

100

600

V_CM

1200

V_LVDS

LVDS Voltage

0

100

2000

400

t_r

Rise Time (20% to 80%)

Fall Time (80% to 20%)

400

ps

7.9 Serial Control Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted). See Figure 4 and Figure 5

MIN

NOM

MAX

500

300

960

UNIT

kHz

ns

f_{SCP_CLK}

SCP Clock Frequency

50

t_{SCP_SKEW}

t_{SCP_DELAY}

Time between valid SCP_DI and rising edge of SCP_CLK

Time between valid SCP_DO and rising edge of SCP_CLK

–300

ns

Time between falling edge of SCP_EN and the first rising edge of

SCP_CLK

t_{SCP_EN}

30

ns

t_{_SCP}

t_{f_SCP}

Rise time for SCP signals

Fall time for SCP signals

200

ns

16

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

DCLK_AN

DCLK_AP

t

h

s

t

c

t

s

h

SCTRL_AN

SCTRL_AP

D_AN(15:0)

D_AP(15:0)

DCLK_BN

DCLK_BP

t

h

s

t

c

t

s

h

SCTRL_BN

SCTRL_BP

D_BN(15:0)

D_BP(15:0)

Figure 2. LVDS Timing Waveforms

V_LVDS(v)

V_LVDSmax= V_CM+ |½V_ID|

V_LVDSmax

T_f(20% - 80%)

V_LVDS= V_CM+/- | 1/2 V_ID

|

V_CM

V_ID

T_r(20% - 80%)

V_{LVDS min}

V_{LVDS min}= 0

Time

Figure 3. LVDS Waveform Requirements

17

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

t

f

= 1 / t

clock c

c

SCPCLK

50%

t_{SCP_SKEW}

SCPDI

50%

t_{SCP_DELAY}

SCPD0

50%

Figure 4. Serial Communications Bus Timing Parameters

t_{f_SCP}

t_{r_SCP}

Input Controller V_CC

SCP_CLK,

SCP_DI,

SCP_EN

V_CC/2

0 v

Figure 5. Serial Communications Bus Waveform Requirements

18

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

7.10 Systems Mounting Interface Loads

MIN

NOM

MAX UNIT

Maximum system mounting interface

load to be applied to the:

Thermal Interface area

Electrical Interface area

Datum “A” Interface area⁽¹⁾

(See Figure 6)

111

423

400

N

(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum

“A” area (425 + 111 – Datum “A"), or the combined loads of the thermal and electrical areas reduced.

Thermal Interface Area

Electrical Interface Area

(all area except thermal area)

Other Areas

Datum 'A' Areas

Figure 6. System Interface Loads

19

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

7.11 Micromirror Array Physical Characteristics

PARAMETER

VALUE

1024

768

UNIT

micromirrors

µm

M

N

P

Number of active columns

Number of active rows

Micromirror (pixel) pitch

See Figure 7

13.68

14.008

10.506

6

Micromirror active array width

Micromirror active array height

Micromirror active border

M × P

mm

N × P

mm

Pond of micromirror (POM)⁽¹⁾

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

0

1

2

3

DMD Active Array

N x P

M x N Micromirrors

N œ 4

N œ 3

N œ 2

N œ 1

M x P

P

Border micromirrors omitted for clarity.

Details omitted for clarity.

P

Not to scale.

P

Refer to Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 7. Micromirror Array Physical Characteristics

20

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

7.12 Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

DMD “parked” state^{(1) (2) (3)}, see

Figure 13

DMD “landed” state^{(1) (4) (5)}

see Figure 13

0

a

Micromirror tilt angle

degrees

12

β

Micromirror tilt angle tolerance^{(1) (4) (6) (7) (8)}

Micromirror crossover time⁽⁹⁾

Micromirror switching time⁽¹⁰⁾

See Figure 13

–1

43

1

degrees

µs

4

13

22

µs

Array switching time at 400 MHz with global

reset⁽¹¹⁾

µs

Non-adjacent micromirrors

adjacent micromirrors

10

0

Non-operating micromirrors⁽¹²⁾

micromirrors

degrees

Orientation of the micromirror axis-of-

rotation⁽¹³⁾

See Figure 12

44

45

46

400 nm to 700 nm, with all

micromirrors in the ON state

Micromirror array optical efficiency^{(14) (15)}

68%

(1) Measured relative to the plane formed by the overall micromirror array.

(2) “Parking” the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed

by the overall micromirror array).

(3) When the micromirror array is “parked”, the tilt angle of each individual micromirror is uncontrolled.

(4) Additional variation exists between the micromirror array and the package datums, as shown in the 机械、封装和可订购信息.

(5) When the micromirror array is “landed”, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS

memory cell associated with each individual micromirror. A binary value of “1” will result in a micromirror “landing” in an nominal angular

position of “+12°”. A binary value of 0 results in a micromirror “landing” in an nominal angular position of “–12°”.

(6) Represents the “landed” tilt angle variation relative to the Nominal “landed” tilt angle.

(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some

System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result

in colorimetry variations and/or system contrast variations.

(9) Micromirror crossover time is primarily a function of the natural response time of the micromirrors and is the time it takes for the

micromirror to crossover to the other state, but does not include mechanical settling time.

(10) Micromirror switching time is the time before a micromirror may be addressed again. Crossover time plus mechanical settling time.

(11) Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time depends

on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and

mirror settling time).

(12) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.

(13) Measured relative to the package datums “B” and “C”, shown in 机械、封装和可订购信息.

(14) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:

–

Illumination wavelength, bandwidth/line-width, degree of coherence

Illumination angle, plus angle tolerance

Illumination and projection aperture size, and location in the system optical path

IIlumination overfill of the DMD micromirror array

Aberrations present in the illumination source and/or path

Aberrations present in the projection path

The specified nominal DMD optical efficiency is based on the following use conditions:

–

Visible illumination (400 nm – 700 nm)

Input illumination optical axis oriented at 24° relative to the window normal

Projection optical axis oriented at 0° relative to the window normal

f/3.0 illumination aperture

f/2.4 projection aperture

Based on these use conditions, the nominal DMD optical efficiency results from the following four components:

21

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

–

Micromirror array fill factor: nominally 92%

Micromirror array diffraction efficiency: nominally 86%

Micromirror surface reflectivity: nominally 88%

Window transmission: nominally 97% (single pass, through two surface transitions)

(15) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle

represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection

path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.

7.13 Window Characteristics

PARAMETER⁽¹⁾

Window material designation

Window refractive index

Window flatness⁽²⁾

CONDITIONS

MIN

TYP

MAX UNIT

Corning 7056

at wavelength 589 nm

Per 25 mm

1.487

4

fringes

(3)

Window aperture

See

Illumination overfill

Refer to Illumination Overfill

At wavelength 405 nm. Applies to 0° and 24° AOI only.

95%

97%

Minimum within the wavelength range 420 nm to 680 nm.

Applies to all angles 0° to 30° AOI.

Window transmittance, single–pass

(4)

through both surfaces and glass

Average over the wavelength range 420 nm to 680 nm.

Applies to all angles 30° to 45° AOI.

97%

(1) See Optical Interface and System Image Quality Considerations for more information.

(2) At a wavelength of 632.8 nm.

(3) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical

ICD in the 机械、封装和可订购信息.

(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window.

7.14 Chipset Component Usage Specification

The DLP7000 is a component of one or more DLP chipsets. Reliable function and operation of the DLP7000

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology is the TI

technology and devices for operating or controlling a DLP DMD.

22

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

8 Detailed Description

8.1 Overview

Optically, the DLP7000 consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors

(“micromirrors”), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows

(Figure 12). Each aluminum micromirror is approximately 13.68 microns in size (see the “Micromirror Pitch” in

Figure 12), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are

measured relative to a 0° “flat state”, which is parallel to the array plane (see Figure 13). The tilt direction is

perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The “On State” landed

position is directed towards “Row 0, Column 0” (upper left) corner of the device package (see the “Micromirror

Hinge-Axis Orientation” in Figure 12). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred

to as "XGA".

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a

specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell

contents, after the micromirror "clocking pulse" is applied. The angular position (–12° or +12°) of the individual

micromirrors changes synchronously with a micromirror “clocking pulse”, rather than being synchronous with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror

"clocking pulse" will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a

memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a

–12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the

CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array

(depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a

DLPA200, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The

border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has

been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array.

Figure 8 shows a DLPC410 and DLP7000 Chipset Block Diagram. The DLPC410 and DLPA200 control and

coordinate the data loading and micromirror switching for reliable DLP7000 operation. The DLPR410 is the

programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset

components, see Application and Implementation. For a typical system application using the DLPC410 chipset

including the DLP7000, see Figure 19.

8.2 Functional Block Diagram

Figure 8 is a simplified system block diagram showing the use of the following components:

● DLPC410

● DLPR410

– Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and

control, and DLPA200 timing and control

– [XCF16PFSG48C] serial flash PROM contains startup configuration information

(EEPROM)

● DLPA200

● DLP7000

– DMD micromirror driver for the DLP7000 DMD

– Spatial Light Modulator (DMD)

23

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

8.3 Feature Description

8.3.1 DLPC410 Chipset DMD Features

Table 1. DLP7000 Overview

DMD

ARRAY

PATTERNS/s

DATA RATE (Gbps)

25.6

MIRROR PITCH

DLP7000 - 0.7”XGA

1024 × 768

32552

13.68 μm

8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset

The DLP7000 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control

interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not

included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in

response to the inputs on the control interface.

For more information, see the DLPC410 data sheet DLPS024.

8.3.1.2 DLPA200 - DMD Micromirror Driver

DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200

is required for DLP7000.

For more information on the DLPA200, see the DLPA200 data sheet DLPS015.

8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset

The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be

altered. For more information, see the DLPR410 data sheet (DLPS027) and the DLPC410 data sheet

(DLPS024).

8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD

8.3.1.4.1 DLP7000 XGA Chip Set Interfaces

This section will describe the interface between the different components included in the chipset. For more

information on component interfacing, see Application and Implementation.

8.3.1.4.1.1 DLPC410 Interface Description

8.3.1.4.1.1.1 DLPC410 IO

Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the

DLPC410 data sheet (DLPS024).

Table 2. Input/Output Description

PIN NAME

DESCRIPTION

I/O

ARST

Asynchronous active low reset

Reference clock, 50 MHz

I

CLKIN_R

DIN_[A,B,C,D](15:0)

DCLKIN[A,B,C,D]

DVALID[A,B,C,D]

ROWMD(1:0)

ROWAD(10:0)

BLK_AD(3:0)

BLK_MD(1:0)

PWR_FLOAT

DMD_TYPE(3:0)

RST_ACTIVE

INIT_ACTIVE

LVDS DDR input for data bus A,B,C,D (15:0)

LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D

LVDS input used to start write sequence for bus A, B, C, and D

DMD row address and row counter control

DMD row address pointer

I

DMD mirror block address pointer

I

DMD mirror block reset and clear command modes

Used to float DMD mirrors before complete loss of power

DMD type in use

I

O

Indicates DMD mirror reset in progress

Initialization in progress.

25

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Table 2. Input/Output Description (continued)

PIN NAME

VLED0

DESCRIPTION

I/O

O

System “heartbeat” signal

VLED1

Denotes initialization complete

O

8.3.1.4.1.1.2 Initialization

The INIT_ACTIVE (Table 2) signal indicates that the DLP7000, DLPA200, and DLPC410 are in an initialization

state after power is applied. During this initialization period, the DLPC410 is initializing the DLP7000 and

DLPA200 by setting all internal registers to their correct states. When this signal goes low, the system has

completed initialization. System initialization takes approximately 220 ms to complete. Data and command write

cycles should not be asserted during the initialization.

During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to

correctly align the data inputs to the data clock. For more information about the interface training pattern, see the

DLPC410 data sheet (DLPS024).

8.3.1.4.1.1.3 DMD Device Detection

The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the

DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the

automatic detection function. All other DMDs do not operate with the DLPC410.

8.3.1.4.1.1.4 Power Down

To ensure long term reliability of the DLP7000, a shutdown procedure must be executed. Prior to power removal,

assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete. This

procedure assures the mirrors are in a flat state.

8.3.1.4.2 DLPC410 to DMD Interface

8.3.1.4.2.1 DLPC410 to DMD IO Description

Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief

functional description.

Table 3. DLPC410 to DMD I/O Pin Descriptions

PIN NAME

DESCRIPTION

I/O

O

DDC_DOUT_[A,B,C,D](15:0)

DDC_DCLKOUT_[A,B,C,D]

DDC_SCTRL_[A,B,C,D]

LVDS DDR output to DMD data bus A,B,C,D (15:0)

LVDS output to DMD data clock A,B,C,D

LVDS DDR output to DMD data control A,B,C,D

O

26

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

8.3.1.4.2.2 Data Flow

Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the

DLPC410 to allow best signal flow.

LVDS BUS D

ꢀDIN_D(15:0)

ꢀDCLK_D

LVDS BUS C

ꢀDIN_C(15:0)

ꢀDCLK_C

ꢀDVALID_D

ꢀDVALID_C

DLPC410

LVDS BUS A

ꢀDOUT_A(15:0)

ꢀDCLKOUT_A

ꢀSCTRL_A

LVDS BUS D

ꢀDOUT_D(15:0)

ꢀDCLKOUT_D

ꢀSCTRL_D

Figure 9. DLPC410 Data Flow

Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge

aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the

DLPC410 (DVALID).

Output LVDS buses transfer data from the DLPC410 to the DLP7000. Output buses LVDS A and LVDS B are

used as highlighted in Figure 9.

8.3.1.4.3 DLPC410 to DLPA200 Interface

8.3.1.4.3.1 DLPA200 Operation

The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that

combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a

family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD

requirements.

The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the

DLPA200 data sheet.

8.3.1.4.3.2 DLPC410 to DLPA200 IO Description

The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows

exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000.

27

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

DLPA200

SCP bus

DLPC410

DLPA200

(Only with 1080p DMD)

Figure 10. Serial Port System Configuration

There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ.

Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief

functional description.

Table 4. DLPC410 to DLPA200 I/O Pin Descriptions

PIN NAME

DESCRIPTION

I/O

O

A_SCPEN

Active low chip select for DLPA200 serial bus

DLPA200 control signal strobe

DLPA200 mode control

A_STROBE

A_MODE(1:0)

A_SEL(1:0)

A_ADDR(3:0)

B_SCPEN

DLPA200 select control

DLPA200 address control

Active low chip select for DLPA200 serial bus (2)

DLPA200 control signal strobe (2)

DLPA200 mode control

B_STROBE

B_MODE(1:0)

B_SEL(1:0)

B_ADDR(3:0)

DLPA200 select control

DLPA200 address control

The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],

SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two

outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected

by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the

selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror

Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle.

8.3.1.4.4 DLPA200 to DLP7000 Interface

8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview

The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST

lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied

directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by

regulators.

The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three

voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse

waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic

control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the

DMD type to determine the appropriate Micromirror Clocking Pulse waveform.

28

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the

next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is

initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror

Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state

regardless of the address while a new address is set up, after which the mirror can be driven to a new latched

state.

A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as “off”

although the light is likely to be more than a mirror latched in the “off” state. System designers should carefully

evaluate the impact of relaxed mirror conditions on optical performance.

8.3.1.5 Measurement Conditions

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. Figure 11 shows an equivalent test load circuit for the

output under test. The load capacitance value stated is only for characterization and measurement of AC timing

signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise

and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks, V_OLMAX and V_OH

MIN for output clocks.

LOAD CIRCUIT

R

L

From Output

Under Test

Tester

Channel

C

= 50 pF

L

= 5 pF for Disable Time

Figure 11. Test Load Circuit for AC Timing Measurements

29

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Incident

Illumination

Package Pin

A1 Corner

Details Omitted For Clarity.

Not To Scale.

DMD

Micromirror

Array

Active Micromirror Array

(Border micromirrors eliminated for clarity)

0

Nœ1

Micromirror Pitch

Micromirror Hinge-Axis Orientation

P (um)

—On-State“

Tilt Direction

45°

—Off-State“

Tilt Direction

P (um)

Figure 12. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation

30

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Package Pin

A1 Corner

DLP7000

Two Two

“On-State” “Off-State”

Micromirrors Micromirrors

For Reference

Flat-State

( “parked” )

Micromirror Position

a

b

-a

b

Silicon Substrate

“On-State”

Micromirror

“Off-State”

Micromirror

Figure 13. Micromirror Landed Positions and Light Paths

31

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

8.4 Device Functional Modes

8.4.1 DMD Operation

The DLP7000 has only one functional mode, it is set to be highly optimized for low latency and high speed in

generating mirror clocking pulses and timings.

When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000 can be

operated in several display modes. The DLP7000 is loaded as 16 blocks of 48 rows each. Figure 14, Figure 15,

Figure 16, and Figure 17 show how the image is loaded by the different Micromirror Clocking Pulse modes.

There are four Micromirror Clocking Pulse modes that determine which blocks are "reset" when a Micromirror

Clocking Pulse command is issued:

•

Single block mode

Dual block mode

Quad block mode

Global mode

8.4.1.1 Single Block Mode

In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset

to transfer the information to the mechanical state of the mirrors.

Data Loaded

Reset

Figure 14. Single Block Mode Diagram

8.4.1.2 Dual Block Mode

In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be

reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of

the mirrors.

Data Loaded

Reset

Figure 15. Dual Block Mode Diagram

32

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Device Functional Modes (continued)

8.4.1.3 Quad Block Mode

In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each

quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the

information to the mechanical state of the mirrors.

Data Loaded

Reset

Figure 16. Quad Block Mode Diagram

8.4.1.4 Global Mode

In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be

loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of

the mirrors.

Reset

Data Loaded

Figure 17. Global Mode Diagram

33

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

8.5 Optical Interface and System Image Quality Considerations

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

8.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

8.5.2 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light

path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt

angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.

8.5.3 Pupil Match

TI recommends the exit pupil of the illumination is nominally centered within 2° of the entrance pupil of the

projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active

area, which may require additional system apertures to control, especially if the numerical aperture of the system

exceeds the pixel tilt angle.

8.5.4 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical

operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the

window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical

system should be designed to limit light flux incident anywhere on the window aperture from exceeding

approximately 10% of the average flux level in the active area. Depending on the particular system’s optical

architecture, overfill light may have to be further reduced below the suggested 10% level in order to be

acceptable.

34

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

8.6 Micromirror Array Temperature Calculation

Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the

maximum temperature of any individual micromirror in the active array, the maximum temperature of the window

aperture, and the temperature gradient between case temperature and the predicted micromirror array

temperature. (see Figure 18).

See the Recommended Operating Conditions for applicable temperature limits.

8.6.1 Package Thermal Resistance

The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can

be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the

package within the specified operational temperatures, refer to Figure 18. The total heat load on the DMD is

typically driven by the incident light absorbed by the active area; although other contributions include light energy

absorbed by the window aperture and electrical power dissipation of the array.

8.6.2 Case Temperature

The temperature of the DMD case can be measured directly. For consistency, thermal test points TP1, TP2, and

TP3 are defined, as shown in Figure 18.

3X 15.88

TP1

TP3

TP2

TP3 (TP2)

Array

TP3

TP2

TP1

10.16

Figure 18. Thermal Test Point Location

35

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Micromirror Array Temperature Calculation (continued)

8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display

applications)

Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from:

•

the measurement points (Figure 18)

the package thermal resistance

the electrical power

the illumination heat load

The relationship between micromirror array temperature and the reference ceramic temperature (thermal test

point TP1 in Figure 18) is provided by the following equations:

T_ARRAY= T _CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

)

where

•

T_ARRAY= computed array temperature (°C)

T_CERAMIC= measured ceramic temperature (°C) (TP1 location)

R_{ARRAY-TO-CERAMIC}= thermal resistance of DMD package (specified in Thermal Information) from array to

ceramic TP1 (°C/W)

•

Q_ARRAY= total power (electrical + absorbed) on the array (Watts)

Q_ELECTRICAL= nominal electrical power (Watts)

Q_ILLUMINATION= (C_L2W× SL) (Watts)

C_L2W= conversion constant for screen lumens to power on DMD (Watts/lumen)

SL = measured screen lumens

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The conversion constant C_L2Wis based on the DMD input illumination

characteristics. It assumes a spectral efficiency of 300 lumens/Watt for the projected light and an illumination

distribution of 83.7% on the active array and 16.3% on the array border. The equations shown above are valid for

a system with a total projection efficiency through the projection lens from the DMD to the projection surface of

87%.

Sample calculation for typical application:

•

T_Ceramic= 55°C (measured)

SL = 2000 lm (measured)

Q_ELECTRICAL= 2.0 Watts

R_{ARRAY-TO-CERAMIC}= 0.9 °C/W

C_L2W= 0.00274 W/lm

Q_ARRAY= 2.0 + (0.00274 W/lm × 2000 lm) = 7.48 W

T_ARRAY= 55°C + (7.48 W x 0.9 °C) = 61.7 °C

36

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Micromirror Array Temperature Calculation (continued)

8.6.4 Micromirror Array Temperature Calculation - Power Density Based

Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from:

•

the measurement points (Figure 18)

the package thermal resistance

the electrical power

the illumination heat load

The relationship between array temperature and the reference ceramic temperature (thermal test point TP1 in

Figure 18) is provided by the following equations:

T_ARRAY= T _CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ (0.42 x Q_INCIDENT

)

where

•

T_ARRAY= computed array temperature (°C)

T_CERAMIC= measured ceramic temperature (°C) (TP1 location)

R_{ARRAY-TO-CERAMIC}= thermal resistance of DMD package (specified in Thermal Information) from array to

ceramic TP1 (°C/W)

•

Q_ARRAY= total power (electrical + absorbed) on the array (Watts)

Q_ELECTRICAL= nominal electrical power (Watts)

Q_INCIDENT= total incident optical power on DMD (Watts)

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for each DMD chip in a system. It

assumes an illumination distribution of 83.7% on the active array and 16.3% on the array border.

Sample Calculation for each DMD in a system with a measured illumination power density:

•

T_Ceramic= 20°C (measured)

ILL_DENSITY= 11 Watts per cm²(optical power on DMD per unit area) (measured)

Overfill = 16.3% (optical design)

Q_ELECTRICAL= 2.0 Watts

R_{ARRAY-TO-CERAMIC}= 0.9 °C/W

Area of array = ( 1.4008 cm x 1.0506 cm ) = 1.4717 cm²

ILL_AREA= 1.4717 cm²/ (83.7%) = 1.7583 cm²

Q_INCIDENT=11 W/cm²x 1.7583 cm²= 19.34 W

Q_ARRAY= 2.0 W + (0.42 x 19.34 W) = 10.12 W

T_ARRAY= 20°C + (10.12 W x 0.9 °C) = 29.11 °C

8.7 Micromirror Landed-On/Landed-Off Duty Cycle

8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On–state versus the amount of time the same

micromirror is landed in the Off–state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the

time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of

the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

37

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Micromirror Landed-On/Landed-Off Duty Cycle (continued)

8.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

8.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:

•

All points along this curve represent the same usable life.

All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

•

All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a give long-term average Landed Duty Cycle.

8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5.

Table 5. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given

primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%

38

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

× Blue_Scale_Value)

where

•

Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,

Green, and Blue are displayed (respectively) to achieve the desired white point.

(1)

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

blue color intensities would be as shown in Table 6.

Table 6. Example Landed Duty Cycle for Full-Color

RED CYCLE PERCENTAGE

50%

GREEN CYCLE PERCENTAGE

20%

BLUE CYCLE PERCENTAGE

30%

LANDED DUTY CYCLE

RED SCALE VALUE

GREEN SCALE VALUE

BLUE SCALE VALUE

0%

100%

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

0%

60%

100%

12%

100%

39

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLP7000 devices require they be coupled with the DLPC410 controller to provide a reliable solution for

many different applications. The DMDs are spatial light modulators which reflect incoming light from an

illumination source to one of two directions, with the primary direction being into a projection collection optic.

Each application is derived primarily from the optical architecture of the system and the format of the data

coming into the DLPC410. Applications of interest include 3D measurement systems, lithography, medical

systems, and compressive sensing.

40

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

9.2.1 Design Requirements

All applications using the DLP7000 XGA chipset require both the controller and the DMD components for

operation. The system also requires an external parallel flash memory device loaded with the DLPC410

Configuration and Support Firmware. The chipset has several system interfaces and requires some support

circuitry. The following interfaces and support circuitry are required:

•

DLPC410 System Interfaces:

–

Control Interface

Trigger Interface

Input Data Interface

Illumination Interface

Reference Clock

•

DLP7000 Interfaces:

–

DLPC410 to DLP7000 Digital Data

DLPC410 to DLP7000 Control Interface

DLPC410 to DLP7000 Micromirror Reset Control Interface

DLPC410 to DLPA200 Micromirror Driver

DLPA200 to DLP7000 Micromirror Reset

9.2.2 Device Description

The DLP7000 XGA chipset offers developers a convenient way to design a wide variety of industrial, medical,

telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data,

and light patterns.

The DLP7000 XGA chipset includes the following four components: DMD Digital Controller (DLPC410),

EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000).

DLPC410 Digital Controller for DLP Discovery 4100 chipset

•

Provides high speed LVDS data and control interface to the DLP7000.

Drives mirror clocking pulse and timing information to the DLPA200.

Supports random row addressing.

DLPR410 PROM for DLP Discovery 4100 chipset

Contains startup configuration information for the DLPC410.

DLPA200 DMD Micromirror Driver

Generates Micromirror Clocking Pulse control (sometimes referred to as a "Reset") of DMD mirrors.

DLP7000 DLP 0.7 XGA 2xLVDS Type-A DMD

•

Steers light in two digital positions (+12º and -12º) using 1024 x 768 micromirror array of aluminum

mirrors.

Table 7. DLPC410 Chipset Configuration for 0.7 XGA Chipset

QUANTITY

TI PART

DLP7000

DLPC410

DLPR410

DLPA200

DESCRIPTION

1

DLP 0.7 XGA 2xLVDS Type-A DMD

Digital Controller for DLP Discovery 4100 chipset

PROM for DLP Discovery 4100 chipset

DMD Micromirror Driver

42

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

Reliable function and operation of DLP7000 XGA chipsets require the components be used in conjunction with

each other. This document describes the proper integration and use of the DLP7000 XGA chipset components.

The DLP7000 XGA chipset can be combined with a user programmable Application FPGA (not included) to

create high performance systems.

9.2.3 Detailed Design Procedure

The DLP7000 DMD is well suited for visible light applications requiring fast, spatially programmable light patterns

using the micromirror array. See the Functional Block Diagram to see the connections between the DLP7000

DMD, the DLPC410 digital controller, the DLPR410 EEPROM, and the DLPA200 DMD micromirror drivers. See

the Figure 19 for an application example. Follow the Layout Guidelines for reliability.

43

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

10 Power Supply Recommendations

10.1 DMD Power-Up and Power-Down Procedures

Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.

The DLP7000 power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024). These

procedures must be followed to ensure reliable operation of the device.

11 Layout

11.1 Layout Guidelines

The DLP7000 is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These

guidelines are targeted at designing a PCB board with these components.

A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal

layers.

11.1.1 Impedance Requirements

Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs

(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across

each pair.

11.1.2 PCB Signal Routing

When designing a PCB for the DLP7000 controlled by the DLPC410 in conjunction with the DLPA200, the

following are recommended:

Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces

routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2

Memory, DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces should not cross over slots in adjacent power and/or ground planes.

Table 8. Important Signal Trace Constraints

SIGNAL

CONSTRAINTS

P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle

<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)

Trace width: 4 mil (0.1 mm)

Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)

Maximum recommended trace length <6 inches (150 mm)

LVDS (DMD_DAT_xnn,

DMD_DCKL_xn, and

DMD_SCTRL_xn)

Table 9. Power Trace Widths and Spacing

MINIMUM TRACE

SPACING

SIGNAL NAME

LAYOUT REQUIREMENTS

WIDTH

GND

Maximize

5 mil (0.13 mm)

10 mil (0.25 mm)

15 mil (0.38 mm)

Maximize trace width to connecting pin as a minimum

VCC, VCC2

MBRST[15:0]

20 mil (0.51 mm)

11 mil (0.23 mm)

11.1.3 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data

is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS

signals should have 100 Ω differential impedance. The differential signals should be matched but kept as short

as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not

necessary.

44

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

11.1.3.1 Trace Length Matching

The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of

100Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair

uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all

signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal

DMD routing must be considered in this calculation.

11.1.4 DLP7000 Decoupling

General decoupling capacitors for the DLP7000 should be distributed around the PCB and placed to minimize

the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have

vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is

discouraged. The power and ground pads of the DLP7000 should be tied to the voltage and ground planes with

their own vias.

11.1.4.1 Decoupling Capacitors

Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and

ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors

meet the following guidelines:

•

The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The

decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to

the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be

tied to the voltage or ground plane through separate vias.

•

The trace lengths of the voltage and ground connections for decoupling capacitors and components should

be less than 0.1 inch to minimize inductance.

The trace width of the power and ground connection to decoupling capacitors and components should be as

wide as possible to minimize inductance.

Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance.

Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

11.1.5 VCC and VCC2

The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should

be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each

decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND

pads of the DMD should be tied to the VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the

distance from the DMD’s VCC2 and ground pads. Using wide etch from the decoupling capacitors to the DMD

connection will reduce inductance and improve decoupling performance.

11.1.6 DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.

11.1.7 DLPA200

The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the

DLPA200 (MBRST[15:0] should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.

The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum

trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet for mechanical

package and layout information.

11.2 Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the

dashed lines, Figure 20 shows correct matching of signal pair lengths with serpentine sections to maintain the

correct impedance.

45

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

Layout Example (continued)

Figure 20. Mitering LVDS Traces to Match Lengths

46

DLP7000

www.ti.com.cn

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

图 21 提供了读取任一 DLP 器件完整器件名称的图例。

DLP7000 FLP

Package

TI Internal Numbering

Device Descriptor

图 21. 器件命名规则

12.1.2 器件标记

器件标记由图 22 中显示的字段组成。

TI Internal Numbering

DMD Part Number

2-Dimensional Matrix Code

(DMD Part Number and

Serial Number)

YYYYYYY

DLP7000_FLP

GHXXXXX LLLLLLM

LLLLLL

Part 1 of Serial Number

Part 2 of Serial Number

(7 characters)

TI Internal Numbering

图 22. 器件标识

12.2 文档支持

12.2.1 相关文档

以下文档包含关于使用 DLP7000 器件的更多信息：

•

《适用于 DLP Discovery 4100 芯片组的 DLPC410 数字控制器数据表》，DLPS024

《DLPA200 DMD 微镜驱动器数据表》，DLPS015

《适用于 DLP Discovery 4100 的 DLPR410 PROM 数据表》，DLPS027

47

DLP7000

ZHCSA87F –AUGUST 2012–REVISED JUNE 2019

www.ti.com.cn

12.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链

接。

表 10. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

DLP7000

DLPA200

DLPC410

DLPR410

12.4 商标

Discovery is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

48

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP7000BFLP
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.7 XGA 2xLVDS A 型 DMD \| FLP \| 203 \| 10 to 65
文件：	总54页 (文件大小：1725K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP7000BFLP [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E