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DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

DLP7000UV DLP^®0.7 UV XGA 2x LVDS A 类 DMD

1 特性

3 说明

1

•

0.7 英寸对角线微镜阵列

DLP7000UV 是一种数控 MEMS（微机电系统）空间

光调制器 (SLM)。当与适当的光学系统配合使用

时，DLP7000UV 可用于调制入射光的振幅、方向和/

或相位。

–

1024 × 768 铝微米尺寸微镜阵列

13.68µm 微镜间距

±12°微镜倾斜角（相对于平板状态）

设计用于边缘照明

DLP7000UV 数字微镜器件 (DMD) 作为 DLP^®

设计用于紫外光（363nm 至 420nm）：

Discovery™ 4100 平台的新成员，可确保非常快速的

图形速率，同时还可在深入 UVA 光谱（363nm 至

420nm）的可见光谱之外实现高性能的空间光调制。

DLP7000UV DMD 设计采用了针对 UV 透射进行优化

的特殊窗口。DLP Discovery 4100 平台还提供具有随

机行寻址选项的最高级独立微镜控制。除了采用密封封

装外，DLP7000UV 具有独特的功能和价值，非常适合

支持各种工业、医疗和高级显示应用。

–

窗透射率 98%（单通，通过两个窗面）

微镜反射率 88%

阵列衍射效率 85%

阵列填充因子 92%（标称值）

两条 16 位低压差分信令 (LVDS) 双倍数据速率

(DDR) 输入数据总线

•

高达 400MHz 的输入数据时钟速率

40.64mm x 31.75mm x 6.0mm 封装尺寸

气密封装

采用密封封装的 DLP7000UV DMD 与一个专用的

DLPC410 控制器（用于支持大于 32000Hz（1 位二进

制）和大于 1900Hz（8 位灰度）的高速图形速率）、

一个 DLPR410（DLP Discovery 4100 配置 PROM）

和一个 DLPA200（DMD 微镜驱动器）配套出售。

2 应用

•

工业

–

直接成像平版印刷术

激光打标和修复系统

计算机直接制版打印机

快速成型机

器件信息 ⁽¹⁾

部件号

封装

封装尺寸（标称值）

DLP7000UV

LCCC (203)

40.64mm × 31.75mm

3D 打印机

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

•

医疗

–

眼科

简化电路原理图

光化疗法

高光谱成像

Illumination

Driver

DLPC410

DLP7000UV

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: DLPS061

DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 23

8.3 Feature Description................................................. 23

8.4 Device Functional Modes........................................ 31

8.5 Window Characteristics and Optics ....................... 33

8.6 Micromirror Array Temperature Calculation............ 34

8.7 Micromirror Landed-On/Landed-Off Duty Cycle ..... 36

Application and Implementation ........................ 38

9.1 Application Information............................................ 38

9.2 Typical Application .................................................. 39

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 4

Specifications....................................................... 11

7.1 Absolute Maximum Ratings .................................... 11

7.2 Storage Conditions.................................................. 11

7.3 ESD Ratings............................................................ 11

7.4 Recommended Operating Conditions..................... 12

7.5 Thermal Information................................................ 13

7.6 Electrical Characteristics......................................... 14

7.7 LVDS Timing Requirements ................................... 15

7.8 LVDS Waveform Requirements.............................. 16

7.9 Serial Control Bus Timing Requirements................ 17

7.10 Systems Mounting Interface Loads....................... 18

7.11 Micromirror Array Physical Characteristics........... 19

7.12 Micromirror Array Optical Characteristics ............. 20

7.13 Window Characteristics......................................... 21

7.14 Chipset Component Usage Specification ............. 21

Detailed Description ............................................ 22

8.1 Overview ................................................................. 22

9

10 Power Supply Recommendations ..................... 42

10.1 Power-Up Sequence (Handled by the DLPC410)

................................................................................. 42

11 Layout................................................................... 42

11.1 Layout Guidelines ................................................. 42

11.2 Layout Example .................................................... 44

12 器件和文档支持 ..................................................... 45

12.1 器件支持................................................................ 45

12.2 文档支持................................................................ 45

12.3 相关链接................................................................ 46

12.4 社区资源................................................................ 47

12.5 商标....................................................................... 47

12.6 静电放电警告......................................................... 47

12.7 Glossary................................................................ 47

13 机械、封装和可订购信息....................................... 47

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (September 2015) to Revision D

Page

•

Updated Pin Configuration and Functions diagram ............................................................................................................... 4

Changed T_GRADIENTfrom 5 °C to 10 °C to accommodate increase in power density from 400 to 420 nm and added

RH symbol for relative humidity in Absolute Maximum Ratings........................................................................................... 11

•

Clarified T_GRADIENTfootnote in Absolute Maximum Ratings.................................................................................................. 11

Changed T_stgto T_DMDin Storage Conditions ........................................................................................................................ 11

Changed 363 to 420 nm to 363 to 400 nm max for 2.5 W/cm²power density and 3.7 W max optical power in

Recommended Operating Conditions ................................................................................................................................. 12

•

Added 400 to 420 nm max power density of 11 W/cm²and max optical power of 16.2 W in Recommended

Operating Conditions ........................................................................................................................................................... 12

Added 363 to 420 nm total integrated max power density of 11 W/cm²and total integrated max optical power of

16.2 W in Recommended Operating Conditions ................................................................................................................. 12

Changed T_GRADIENTfrom 5 °C to 10 °C to accommodate increase in power density from 400 to 420 nm

Recommended Operating Conditions ................................................................................................................................. 12

•

Changed Micromirror active border value from 10 to correct value of 6 in Micromirror Array Physical Characteristics...... 19

Changed micromirror crossover to mean transition time and renamed previous crossover to micromirror switching

time typical micromirror crossover time typo (16 µs to 13 µs) in Micromirror Array Optical Characteristics........................ 20

•

Added typical micromirror switching time - 13 µs in Micromirror Array Optical Characteristics........................................... 20

Changed "Micromirror switching time" to "Array switching time" for clarity in Micromirror Array Optical Characteristics.... 20

Added clarification to Micromirror switching time at 400 MHz with global reset in Micromirror Array Optical

Characteristics...................................................................................................................................................................... 20

•

Changed Figure 17 drawing to current thermal test point numbering convention ............................................................... 34

已添加 “相关链接”表.............................................................................................................................................................. 46

2

DLP7000UV

www.ti.com.cn

ZHCSE66D –MAY 2015–REVISED MAY 2017

修订历史记录 (接下页)

Changes from Revision B (July 2015) to Revision C

Page

•

将器件状态从“产品预览”更改为“生产数据”.............................................................................................................................. 1

Added 3.7-W maximum value to illumination power (from 363 nm to 420 nm) in Recommended Operating

Conditions ............................................................................................................................................................................ 12

•

Updated Figure 18 ............................................................................................................................................................... 38

Changes from Revision A (June 2015) to Revision B

Page

•

发布完整版产品说明书............................................................................................................................................................ 1

在说明中将 UVA 光谱的最小值从 365nm 更正为 363nm...................................................................................................... 1

Changes from Original (May 2015) to Revision A

Page

•

更正了器件的部件号 ............................................................................................................................................................... 1

3

DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

www.ti.com.cn

5 说明（续）

DLP7000UV 需要与芯片组的其他组件结合使用才能实现可靠功能和运行。一套专用的芯片组能够使开发人员更加

轻松地访问 DMD 并使用高速而独立的微镜控制。

电子方面，DLP7000UV 由 1 位 CMOS 存储器单元的两维阵列组成，其组织结构为 1024 存储器单元列乘以 768

存储器单元行的栅格。CMOS 存储器阵列通过两条 16 位低压差分信令 (LVDS) 双倍数据速率 (DDR) 总线逐行进行

寻址。寻址由一个串行控制总线处理。特定的 CMOS 存储器访问协议由 DLPC410 数字控制器处理。

6 Pin Configuration and Functions

FLP Package

203-Pin LCCC

Bottom View

A

B

C

D

E

F

074

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

4

DLP7000UV

www.ti.com.cn

ZHCSE66D –MAY 2015–REVISED MAY 2017

Pin Functions

(1)

NAME

TYPE

(I/O/P)

DATA

INTERNAL

SIGNAL

CLOCK

DESCRIPTION

TRACE (MILS)

(2)

(3)

RATE

TERM

NO.

DATA INPUT

Differential

Terminated -

100 Ω

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

D_AP(0)

D_AP(1)

B10

A13

D16

C17

B18

A17

A25

D22

C29

D28

E27

F26

G29

H28

J27

Input

LVCMOS

DDR

DCLK_A

368.72

424.61

433.87

391.39

438.57

391.13

563.26

411.62

595.11

543.07

455.98

359.5

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus A

(2x LVDS)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

542.67

551.51

528.04

484.38

366.99

417.47

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

K26

B12

A11

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.

(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.

(3) Refer to Electrical Characteristics for differential termination specification.

5

DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

www.ti.com.cn

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

SIGNAL

CLOCK

DESCRIPTION

TRACE (MILS)

(2)

(3)

NAME

NO.

Differential

Terminated -

100 Ω

D_AP(2)

D14

Input

LVCMOS

DDR

DCLK_A

434.89

Differential

Terminated -

100 Ω

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

C15

B16

A19

A23

D20

A29

B28

C27

D26

F30

LVCMOS

DDR

DCLK_A

DCLK_B

394.67

437.3

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

389.01

562.92

410.34

594.61

539.88

456.78

360.68

543.97

570.85

527.18

481.02

368.72

424.61

433.87

391.39

438.57

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus A

(2x LVDS)

Differential

Terminated -

100 Ω

H30

J29

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

K28

AB10

AC13

Y16

AA17

AB18

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

6

DLP7000UV

www.ti.com.cn

ZHCSE66D –MAY 2015–REVISED MAY 2017

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

SIGNAL

CLOCK

DESCRIPTION

TRACE (MILS)

(2)

(3)

NAME

NO.

Differential

Terminated -

100 Ω

D_BN(5)

D_BN(6)

D_BN(7)

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

AC17

Input

LVCMOS

DDR

DCLK_B

391.13

Differential

Terminated -

100 Ω

AC25

Y22

LVCMOS

DDR

DCLK_B

563.26

411.62

595.11

543.07

455.98

360.94

575.85

519.37

532.59

441.14

366.99

417.47

434.89

394.67

437.3

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

AA29

Y28

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

W27

V26

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

T30

Differential

Terminated -

100 Ω

R29

Differential

Terminated -

100 Ω

R27

Differential

Terminated -

100 Ω

N27

Differential

Terminated -

100 Ω

AB12

AC11

Y14

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

AA15

AB16

AC19

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

389.01

Input data bus B

(2x LVDS) Input

data bus B (2x

LVDS)

Differential

Terminated -

100 Ω

D_BP(6)

D_BP(7)

AC23

Y20

Input

LVCMOS

DDR

DCLK_B

562.92

410.34

Differential

Terminated -

100 Ω

7

DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

www.ti.com.cn

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

SIGNAL

CLOCK

DESCRIPTION

TRACE (MILS)

(2)

(3)

NAME

NO.

Differential

Terminated -

100 Ω

D_BP(8)

AC29

Input

LVCMOS

DDR

DCLK_B

594.61

Differential

Terminated -

100 Ω

D_BP(9)

AB28

AA27

Y26

LVCMOS

DDR

DCLK_B

539.88

456.78

360.68

578.46

509.74

534.59

440

Differential

Terminated -

100 Ω

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

D_BP(15)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

U29

T28

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Input data bus B

(2x LVDS)

P28

Differential

Terminated -

100 Ω

P26

DATA CLOCK

Differential

Terminated -

100 Ω

DCLK_AN

B22

B24

Input

LVCMOS

–

477.10

477.11

477.10

477.11

Differential

Terminated -

100 Ω

DCLK_AP

DCLK_BN

DCLK_BP

Differential

Terminated -

100 Ω

AB22

AB24

Differential

Terminated -

100 Ω

DATA CONTROL INPUTS

Differential

Terminated -

100 Ω

Serial control for

data bus A (2x

LVDS)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

C21

C23

Input

LVCMOS

DDR

DCLK_A

DCLK_B

477.07

477.14

477.07

477.14

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Serial control for

data bus B (2x

LVDS)

AA21

AA23

Differential

Terminated -

100 Ω

SERIAL COMMUNICATION AND CONFIGURATION

SCPCLK

SCPDO

SCPDI

E3

B2

F4

D4

C3

Input

Output

Input

LVCMOS

–

Pull-down

–

Serial port clock

Serial port output

Serial port input

Serial port enable

Device Reset

379.29

480.91

323.56

326.99

406.28

SCPCLK

–

Pull-down

SCPENZ

PWRDNZ

Input

8

DLP7000UV

www.ti.com.cn

ZHCSE66D –MAY 2015–REVISED MAY 2017

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

SIGNAL

CLOCK

DESCRIPTION

TRACE (MILS)

(2)

(3)

NAME

NO.

D8

Data bandwidth

mode select

MODE_A

MODE_B

Input

LVCMOS

–

Pull-down

–

396.05

208.86

C11

MICROMIRROR BIAS CLOCKING PULSE

MBRST(0)

MBRST(1)

MBRST(2)

MBRST(3)

MBRST(4)

MBRST(5)

MBRST(6)

P2

AB4

AA7

N3

Input

Analog

–

M4

AB6

AA5

Micromirror Bias

Clocking Pulse

MBRST signals

clock micromirrors

into state of

MBRST(7)

L3

Input

Analog

–

LVCMOS memory

cell associated

with each mirror.

MBRST(8)

MBRST(9)

MBRST(10)

MBRST(11)

MBRST(12)

MBRST(13)

MBRST(14)

MBRST(15)

POWER

Y6

K4

Input

Analog

–

L5

AC5

Y8

J5

K6

AC7

A7, A15,

C1, E1, U1,

W1,

AB2,AC9,

AC15

Power for

LVCMOS Logic

VCC

Power

Analog

–

A21, A27,

D30, M30,

Y30, AC21,

AC27

Power supply for

LVDS Interface

VCC1

VCC2

Power

Analog

–

Power for High

Voltage CMOS

Logic

G1, J1, L1,

N1, R1

9

DLP7000UV

ZHCSE66D –MAY 2015–REVISED MAY 2017

www.ti.com.cn

TRACE (MILS)

Pin Functions (continued)

(1)

TYPE

DATA

INTERNAL

SIGNAL

CLOCK

DESCRIPTION

(2)

(3)

(I/O/P)

RATE

TERM

NAME

NO.

A1, A3, A5,

A9, B4, B8,

B14, B20,

B26, B30,

C7,

C13, C19,

C25, D6,

D12, D18,

D24, E29,

F2, F28,

G3, G27,

H2, H4,

H26, J3,

J25 ,K2,

K30, L25,

L27, L29,

M2, M6,

M26, M28,

N5, N25,

N29, P4,

Common return

for all power

inputs

VSS

Power

Analog

–

P30, R3,

R5, R25,

T2, T26,

U27, V28,

V30, W5,

W29, Y4,

Y12, Y18,

Y24,

AA3,AA9,

AA13,

AA19,

AA25, AB8,

AB14,

AB20,

AB26, AB30

RESERVED SIGNALS (NOT FOR USE IN SYSTEM)

RESERVED

_AA1

Pins should be

connected to VSS

AA1

B6

Input

LVCMOS

–

Pull-down

–

RESERVED

_B6

–

RESERVED

_T4

T4

RESERVED

_U5

U5

AA11, AC3,

C5, C9,

D10, D2,

E5,G5, H6,

P6, T6,

NO_CONN

ECT

DO NOT

CONNECT

–

U3, V2, V4,

W3, Y10,

Y2

10

DLP7000UV

www.ti.com.cn

ZHCSE66D –MAY 2015–REVISED MAY 2017

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

ELECTRICAL

(2) (3)

V_CC

Voltage applied to V_CC

Voltage applied to V_CCI

–0.5

4

8

V

(2) (3)

V_CCI

V_CC2

(2) (3) (4)

Voltage applied to V_VCC2

Micromirror clocking pulse waveform voltage applied to MBRST[15:0]

Input Pins (supplied by DLPA200)

V_MBRST

–28

28

V

(4)

|V_CC– V_CCI

|

Supply voltage delta (absolute value)

0.3

V

(2)

Voltage applied to all other input pins

–0.5

V_CC+ 0.3

Maximum differential voltage, damage can occur to internal termination

resistor if exceeded, see Figure 2

|V_ID

|

700

mV

I_OH

I_OL

Current required from a high-level output

Current required from a low-level output

V_OH= 2.4 V

V_OL= 0.4 V

–20

15

mA

ENVIRONMENTAL

(5)

Case temperature – operational

20

30

80

10

95

°C

T_C

(5)

Case temperature – non-operational

–40

(6)

T_GRADIENT

RH

Device temperature gradient – operational

Relative humidity (non-condensing)

°C

%RH

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS(ground).

(3) Voltages V_CC, V_CCI, and V_CC2are required for proper DMD operation.

(4) Exceeding the recommended allowable absolute voltage difference between V_CCand V_CCImay result in excess current draw. The

difference between V_CCand V_CCI, |V_CC– V_CCI|, should be less than the specified limit.

(5) DMD Temperature is the worst-case of any test point shown in Case Temperature, or the active array as calculated by the Micromirror

Array Temperature Calculation.

(6) As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point

inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.

7.2 Storage Conditions

are applicable before the DMD is installed in the final product.

MIN

MAX

80

UNIT

°C

T_DMD

RH

Storage temperature

–40

Relative humidity (non-condensing)

95

%RH

7.3 ESD Ratings

VALUE

±2000

<250

UNIT

All pins except MBRST[0:15]

MBRST[0:15] pins

Electrostatic

V_(ESD)

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001

V

(1)

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible if necessary precautions are taken.

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7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1)

MIN NOM

MAX

UNIT

ELECTRICAL

(2) (3)

V_CC

Supply voltage for LVCMOS core logic

3.0

3.3

7.5

3.6

V

(2) (3)

V_CCI

Supply voltage for LVDS receivers

(2) (3)

V_CC2

Mirror electrode and HVCMOS supply voltage

7.25

–27

7.75

26.5

0.3

V_MBRST

|V_CC– V_CCI

Clocking pulse waveform voltage applied to MBRST[15:0] input pins (supplied by DLPA200)

(3)

|

Supply voltage delta (absolute value)

ENVIRONMENTAL

(6)

mW/cm²

W/cm²

W

< 363 nm

2

2.5

3.7

11

(7)

363 to 400 nm

W/cm²

W

(4) (5)

(7)

Illumination power density

400 to 420 nm

16.2

11

W/cm²

W

(7)(8)

363 to 420 nm total

> 420 nm

16.2

(7)

W/cm²

°C

Thermally limited

(9) (10)

(11)

T_C

Case/array temperature

20

30

(12)

T_GRADIENT

RH

Device temperature gradient – operational

Relative humidity (non-condensing)

10

95

°C

%RH

(13)

Operating landed duty cycle

25%

(1) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(2) All voltages referenced to VSS (ground).

(3) Voltages V_CC, V_CCI, and V_CC2, are required for proper DMD operation.

(4) Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination

power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or

power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(5) Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range.

(6) The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363 nm should not be

implemented simultaneously.

(7) Also limited by the resulting micromirror array temperature. Refer to Case Temperature and Micromirror Array Temperature Calculation

for information related to calculating the micromirror array temperature.

(8) The total integrated illumination power density from 363 to 420 nm shall not exceed 11 W/cm²(or 16.2 W evenly distributed on the

active array area). Therefore if 2.5 W/cm²of illumination is used in the 363 to 400 nm range, then illumination in the 400 to 420 nm

range must be limited to 8.5 W/cm².

(9) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. Refer to Micromirror

Array Temperature Calculation for further details.

(10) Temperature is the highest measured value of any test point shown in Figure 17 or the active array as calculated by the Micromirror

Array Temperature Calculation.

(11) Refer to Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device

temperature calculation.

(12) As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point

inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.

(13) Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other

state (–12° or 12°).

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7.5 Thermal Information

DLP7000UV

(1) (2)

THERMAL METRIC

FLP (LCCC)

203 PINS

0.9

UNIT

Active micromirror array resistance to TP1

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate

heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the

Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area;

although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical

systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in

this area can significantly degrade the reliability of the device.

(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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7.6 Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

V_CC= 3.0 V, I_OH= –20 mA

MIN

TYP

MAX

UNIT

(1)

High-level output voltage

See Figure 10

,

V_OH

V_OL

2.4

V

(1)

Low-level output voltage

See Figure 10

,

V_CC= 3.6 V, I_OH= 15 mA

0.4

V

Clocking Pulse Waveform applied to

V_MBRSTMBRST[29:0] Input Pins (supplied

-27

26.5

by DLPA200)

(1)

I_OZ

I_OH

I_OL

High impedance output current

V_CC= 3.6 V

10

–20

µA

V_OH= 2.4 V, V_CC≥ 3 V

V_OH= 1.7 V, V_CC≥ 2.25 V

V_OL= 0.4 V, V_CC≥ 3 V

V_OL= 0.4 V, V_CC≥ 2.25 V

(1)

High-level output current

mA

–15

15

(1)

Low-level output current

mA

14

(1)

V_IH

V_IL

I_IL

High-level input voltage

1.7

VCC + .3

0.7

V

(1)

Low-level input voltage

–0.3

(1)

Low-level input current

V_CC= 3.6 V, V_I= 0 V

V_CC= 3.6 V, V_I= V_CC

V_CC= 3.6 V

–60

µA

mA

W

(1)

I_IH

High-level input current

200

I_CC

I_CCI

I_CC2

P_D

Z_IN

Current into V_CCpin

1475

450

(2)

Current into V_CCIpin

V_CCI= 3.6 V

Current into V_CC2pin

Power dissipation

V_CC2= 8.75 V

25

2.0

Internal differential impedance

95

90

105

110

Ω

Line differential impedance (PWB,

Trace)

Z_LINE

100

Ω

(1)

C_I

Input capacitance

f = 1 MHz

10

pF

(1)

C_O

C_IM

Output capacitance

Input capacitance for MBRST[0:15]

pins

f = 1 MHz

220

270

pF

(1) Applies to LVCMOS pins only.

(2) Exceeding the maximum allowable absolute voltage difference between V_CCand V_CCImay result in excess current draw. See the

Absolute Maximum Ratings for details.

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7.7 LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 1

MIN

200

2.5

NOM

MAX

UNIT

MHz

ns

f_{DCLK_*}

DCLK_* clock frequency {where * = [A, or B]}

Clock cycle - DLCK_*

400

t_c

t_w

Pulse width - DLCK_*

1.25

ns

t_s

Setup time - D_*[15:0] and SCTRL_* before DCLK_*

Hold time, D_*[15:0] and SCTRL_* after DCLK_*

Skew between bus A and B

0.35

ns

t_h

ns

t_skew

–1.25

1.25

ns

DCLK_AN

DCLK_AP

t

h

s

t

c

t

s

h

SCTRL_AN

SCTRL_AP

D_AN(15:0)

D_AP(15:0)

DCLK_BN

DCLK_BP

t

s

h

t

c

t

s

h

SCTRL_BN

SCTRL_BP

D_BN(15:0)

D_BP(15:0)

Figure 1. LVDS Timing Waveforms

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7.8 LVDS Waveform Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 2

MIN

NOM

400

MAX

UNIT

mV

ps

|V_ID

|

Input differential voltage (absolute difference)

Common mode voltage

100

600

V_CM

1200

V_LVDS

LVDS voltage

0

100

2000

400

t_r

Rise time (20% to 80%)

Fall time (80% to 20%)

400

ps

V_LVDS(v)

V_LVDSmax= V_CM+ |½V_ID|

V_LVDSmax

T_f(20% - 80%)

V_LVDS= V_CM+/- | 1/2 V_ID

|

V_CM

V_ID

T_r(20% - 80%)

V_{LVDS min}

V_{LVDS min}= 0

Time

Figure 2. LVDS Waveform Requirements

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7.9 Serial Control Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 3 and Figure 4

MIN

NOM

MAX

500

300

960

UNIT

kHz

ns

f_{SCP_CLK}

SCP clock frequency

50

t_{SCP_SKEW}

t_{SCP_DELAY}

Time between valid SCP_DI and rising edge of SCP_CLK

Time between valid SCP_DO and rising edge of SCP_CLK

–300

ns

Time between falling edge of SCP_EN and the first rising edge of

SCP_CLK

t _{SCP_EN}

30

ns

t_{_SCP}

t_{f_SCP}

Rise time for SCP signals

Fall time for SCP signals

200

ns

t

f

= 1 / t

c

clock

SCPCLK

50%

t_{SCP_SKEW}

SCPDI

50%

t_{SCP_DELAY}

SCPD0

50%

Figure 3. Serial Communications Bus Timing Parameters

t_{f_SCP}

t_{r_SCP}

Input Controller V_CC

SCP_CLK,

SCP_DI,

SCP_EN

V_CC/2

0 v

Figure 4. Serial Communications Bus Waveform Requirements

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MAX UNIT

7.10 Systems Mounting Interface Loads

PARAMETER

MIN

NOM

Thermal interface area (see Figure 5)

111

423

400

N

Maximum system mounting interface

load to be applied to the:

Electrical interface area

(1)

Datum A Interface area (see Figure 5 )

(1) Combined loads of the thermal and electrical interface areas in excess of Datum A load shall be evenly distributed outside the Datum A

area (423 + 111 – Datum A).

Thermal

Interface Area

Electrical

Interface Area

(all area less thermal interface)

Other Areas

Datum ‘A’ Area

Figure 5. System Interface Loads

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7.11 Micromirror Array Physical Characteristics

VALUE

1024

768

UNIT

micromirrors

µm

M

N

P

Number of active columns

Number of active rows

See Figure 6

Micromirror (pixel) pitch

13.68

14.008

10.506

6

Micromirror active array width

Micromirror active array height

Micromirror active border

M × P

mm

N × P

mm

(1)

Pond of micromirror (POM)

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

0

1

2

3

DMD Active Array

N x P

M x N Micromirrors

N œ 4

N œ 3

N œ 2

N œ 1

M x P

P

Pond of micromirrors (POM) omitted for clarity.

Details omitted for clarity.

P

Not to scale.

P

Refer to Micromirror Array Physical Characteristics for M, N, and P specifications.

Figure 6. Micromirror Array Physical Characteristics

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7.12 Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DMD parked state ^{(1) (2) (3)}, See

Figure 12

0

a

Micromirror tilt angle

degrees

DMD landed state ^{(1) (4) (5)}

See Figure 12

12

(1) (4) (6) (7) (8)

β

Micromirror tilt angle tolerance

Micromirror crossover time ⁽⁹⁾

Micromirror switching time ⁽¹⁰⁾

See Figure 12

–1

43

1

22

degrees

µs

4

13

µs

Array switching time at 400 MHz with global

reset ⁽¹¹⁾

µs

Non-adjacent micromirrors

Adjacent micromirrors

10

0

Non operating micromirrors ⁽¹²⁾

micromirrors

degrees

Orientation of the micromirror axis-of-rotation

See Figure 11

44

45

46

(13)

363 to 420 nm, with all micromirrors

in the ON state

(14) (15)

Micromirror array optical efficiency

66%

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by

the overall micromirror array).

(3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.

(4) Additional variation exists between the micromirror array and the package datums, as shown in the 机械、封装和可订购信息.

(5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS

memory cell associated with each individual micromirror. A binary value of 1 will result in a micromirror landing in an nominal angular

position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.

(6) Represents the landed tilt angle variation relative to the Nominal landed tilt angle.

(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some

System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result

in colorimetry variations and/or system contrast variations.

(9) Micromirror crossover time is primarily a function of the natural response time of the micromirrors and is the time it takes for the

micromirror to crossover to the other state, but does not include mechanical settling time.

(10) Micromirror switching time is the time before a micromirror may be addressed again. Crossover time plus mechanical settling time.

(11) Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time depends

on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and

mirror settling time).

(12) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.

(13) Measured relative to the package datums B and C, shown in the 机械、封装和可订购信息.

(14) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:

–

Illumination wavelength, bandwidth/line-width, degree of coherence

Illumination angle, plus angle tolerance

Illumination and projection aperture size, and location in the system optical path

IIlumination overfill of the DMD micromirror array

Aberrations present in the illumination source and/or path

Aberrations present in the projection path

The specified nominal DMD optical efficiency is based on the following use conditions:

–

Visible illumination (363 to 420 nm)

Input illumination optical axis oriented at 24° relative to the window normal

Projection optical axis oriented at 0° relative to the window normal

f / 3.0 illumination aperture

f / 2.4 projection aperture

Based on these use conditions, the nominal DMD optical efficiency results from the following four components:

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–

Micromirror array fill factor: nominally 92%

Micromirror array diffraction efficiency: nominally 85%

Micromirror surface reflectivity: nominally 88%

Window transmission: nominally 98% for wavelengths 363 nm to 420 nm, applies to all angles 0° to 30° AOI (Angle of Incidence)

(single pass, through two surface transitions)

(15) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle

represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection

path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.

7.13 Window Characteristics

(1)

PARAMETER

Window material designation

Window refractive index

CONDITIONS

MIN

TYP

MAX UNIT

Corning 7056

At wavelength 589 nm

Per 25 mm

1.487

(2)

Window flatness

4

fringes

µm

(3)

Window artifact size

Within the Window Aperture

400

(4)

Window aperture

See

Illumination overfill

Refer to Illumination Overfill

Window transmittance, single–pass

through both surfaces and glass

Within the wavelength range 363 nm to 420 nm. Applies to all

angles 0 to 30 AOI

98%

(5)

(1) See Window Characteristics and Optics for more information.

(2) At a wavelength of 632.8 nm.

(3) See the 机械、封装和可订购信息 section at the end of this document for details regarding the size and location of the window aperture.

(4) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the 机械、封装

和可订购信息 section.

(5) See the TI application report Wavelength Transmittance Considerations for DMD Window, DLPA031.

7.14 Chipset Component Usage Specification

The DLP7000UV is a component of one or more DLP chipsets. Reliable function and operation of the

DLP7000UV requires that it be used in conjunction with the other components of the applicable DLP chipset,

including those components that contain or implement TI DMD control technology. TI DMD control technology

consists of the TI technology and devices for operating or controlling a DLP DMD.

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8 Detailed Description

8.1 Overview

Optically, the DLP7000UV consists of 786432 highly reflective, digitally switchable, micrometer-sized mirrors

(micromirrors), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows

(Figure 11). Each aluminum micromirror is approximately 13.68 microns in size (see the Micromirror Pitch in

Figure 11), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are

measured relative to a 0° flat state, which is parallel to the array plane (see Figure 12). The tilt direction is

perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The On State landed

position is directed towards Row 0, Column 0 (upper left) corner of the device package (see the Micromirror

Hinge-Axis Orientation in Figure 11). In the field of visual displays, the 1024 by 768 pixel resolution is referred to

as XGA.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a

specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell

contents, after the micromirror clocking pulse is applied. The angular position (–12° or +12°) of the individual

micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror

clocking pulse will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a

memory cell followed by a micromirror clocking pulse will result in the corresponding micromirror switching to a

–12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the

CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array

(depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a

DLPA200, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of active border micromirrors.

The pond of micromirror (POM) is not user-addressable. The border micromirrors land in the –12° position once

power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active

array.

Figure 7 shows a DLPC410 and DLP7000UV Chipset Block Diagram. The DLPC410 and DLPA200 control and

coordinate the data loading and micromirror switching for reliable DLP7000UV operation. The DLPR410 is the

programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset

components, see Application and Implementation. For a typical system application using the DLP Discovery 4100

chipset including the DLP7000UV, see Figure 19.

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8.2 Functional Block Diagram

DLP7000UV

Figure 7. DLPC410 and DLP7000UV Chipset Block Diagram

8.3 Feature Description

Table 1. DLPC410 DMD Types Overview

DMD

ARRAY

1024 × 768

PATTERNS/s

DATA RATE (Gbs)

25.6

MIRROR PITCH

(1)

DLP7000UV - 0.7” XGA

32552

13.6 µm

(1) This is for single block mode resets.

Figure 7 is a simplified system block diagram showing the use of the following components:

– Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control,

and DLPA200 timing and control

•

DLPC410

DLPR410

– [XCF16PFSG48C] serial flash PROM contains startup configuration information

(EEPROM)

•

DLPA200

– DMD micromirror driver for the DLP7000UV DMD

– Spatial Light Modulator (DMD)

DLP7000UV

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8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset

The DLP7000UV chipset includes the DLPC410 controller which provides a high-speed LVDS data and control

interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not

included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in

response to the inputs on the control interface.

For more information, see the DLPC410 data sheet (DLPS024).

8.3.2 DLPA200 DMD Micromirror Driver

DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200

is required for DLP7000UV.

For more information on the DLPA200, see the DLPA200 data sheet (DLPS015).

8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset

The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be

altered. For more information, see the DLPR410 data sheet (DLPS027) and the DLPC410 data sheet

(DLPS024).

8.3.4 DLP7000 - DLP 0.7 XGA 2xLVDS UV Type-A DMD

8.3.4.1 DLP7000UV Chipset Interfaces

This section will describe the interface between the different components included in the chipset. For more

information on component interfacing, see Application and Implementation.

8.3.4.1.1 DLPC410 Interface Description

8.3.4.1.1.1 DLPC410 IO

Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the

DLPC410 data sheet.

Table 2. Input/Output Description

PIN NAME

DESCRIPTION

I/O

I

ARST

Asynchronous active low reset

Reference clock, 50 MHz

CLKIN_R

I

DIN_[A,B,C,D](15:0)

DCLKIN[A,B,C,D]

DVALID[A,B,C,D]

ROWMD(1:0)

ROWAD(10:0)

BLK_AD(3:0)

BLK_MD(1:0)

PWR_FLOAT

DMD_TYPE(3:0)

RST_ACTIVE

INIT_ACTIVE

VLED0

LVDS DDR input for data bus A,B,C,D (15:0)

LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D

LVDS input used to start write sequence for bus A, B, C, and D

DMD row address and row counter control

DMD row address pointer

I

DMD mirror block address pointer

I

DMD mirror block reset and clear command modes

Used to float DMD mirrors before complete loss of power

DMD type in use

I

O

Indicates DMD mirror reset in progress

Initialization in progress

System heartbeat signal

VLED1

Denotes initialization complete

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8.3.4.1.1.2 Initialization

The INIT_ACTIVE (Table 2) signal indicates that the DLP7000UV, DLPA200, and DLPC410 are in an

initialization state after power is applied. During this initialization period, the DLPC410 is initializing the

DLP7000UV and DLPA200 by setting all internal registers to their correct states. When this signal goes low, the

system has completed initialization. System initialization takes approximately 220 ms to complete. Data and

command write cycles should not be asserted during the initialization.

During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to

correctly align the data inputs to the data clock. For more information, see the DLPC410 data sheet – Interface

Training Pattern.

8.3.4.1.1.3 DMD Device Detection

The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the

DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the

automatic detection function. All other DMDs do not operate with the DLPC410.

8.3.4.1.1.4 Power Down

To ensure long term reliability of the DLP7000UV, a shutdown procedure must be executed. Prior to power

removal, assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete.

This procedure assures the mirrors are in a flat state.

8.3.4.2 DLPC410 to DMD Interface

8.3.4.2.1 DLPC410 to DMD IO Description

Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief

functional description.

Table 3. DLPC410 to DMD I/O Pin Descriptions

PIN NAME

DDC_DOUT_[A,B,C,D](15:0)

DDC_DCLKOUT_[A,B,C,D]

DDC_SCTRL_[A,B,C,D]

DESCRIPTION

I/O

O

LVDS DDR output to DMD data bus A, B, C, D (15:0)

LVDS output to DMD data clock A, B, C, D

LVDS DDR output to DMD data control A, B, C, D

O

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8.3.4.2.2 Data Flow

Figure 8 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the

DLPC410 to allow best signal flow.

LVDS BUS D

sDIN_D(15:0)

sDCLK_D

LVDS BUS C

sDIN_C(15:0)

sDCLK_C

sDVALID_C

sDVALID_D

DLPC410

LVDS BUS D

sDOUT_D(15:0)

sDCLKOUT_D

sSCTRL_D

LVDS BUS A

sDOUT_A(15:0)

sDCLKOUT_A

sSCTRL_A

Figure 8. DLPC410 Data Flow

Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge

aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the

DLPC410 (DVALID).

Output LVDS buses transfer data from the DLPC410 to the DLP7000UV. Output buses LVDS A and LVDS B are

used as highlighted in Figure 8.

8.3.4.3 DLPC410 to DLPA200 Interface

8.3.4.3.1 DLPA200 Operation

The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that

combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a

family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD

requirements.

The DLPA200 operates from a +12 volt power supply input. For more detailed information on the DLPA200, see

the DLPA200 data sheet.

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8.3.4.3.2 DLPC410 to DLPA200 IO Description

The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows

exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000UV.

DLPA200

SCP bus

DLPC410

SCP bus

DLPA200

(Only with 1080p DMD)

Figure 9. Serial Port System Configuration

There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ.

Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief

functional description.

Table 4. DLPC410 to DLPA200 I/O Pin Descriptions

PIN NAME

A_SCPEN

DESCRIPTION

Active low chip select for DLPA200 serial bus

DLPA200 control signal strobe

DLPA200 mode control

I/O

O

A_STROBE

A_MODE(1:0)

A_SEL(1:0)

A_ADDR(3:0)

B_SCPEN

DLPA200 select control

DLPA200 address control

Active low chip select for DLPA200 serial bus (2)

DLPA200 control signal strobe (2)

DLPA200 mode control

B_STROBE

B_MODE(1:0)

B_SEL(1:0)

B_ADDR(3:0)

DLPA200 select control

DLPA200 address control

The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],

SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two

outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected

by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the

selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror

Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle.

8.3.4.4 DLPA200 to DLP7000UV Interface Overview

The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST

lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied

directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by

regulators.

The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three

voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse

waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic

control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the

DMD type to determine the appropriate Micromirror Clocking Pulse waveform.

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A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the

next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is

initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror

Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state

regardless of the address while a new address is set up, after which the mirror can be driven to a new latched

state.

A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off

although the light is likely to be more than a mirror latched in the off state. System designers should carefully

evaluate the impact of relaxed mirror conditions on optical performance.

8.3.5 Measurement Conditions

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. Figure 10 shows an equivalent test load circuit for the

output under test. The load capacitance value stated is only for characterization and measurement of AC timing

signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise

and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks, V_OLMAX and V_OH

MIN for output clocks.

LOAD CIRCUIT

R

L

From Output

Under Test

Tester

Channel

C

= 50 pF

L

= 5 pF for Disable Time

Figure 10. Test Load Circuit for AC Timing Measurements

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Incident

Illumination

Package Pin

A1 Corner

Details Omitted For Clarity.

Not To Scale.

DMD

Micromirror

Array

Active Micromirror Array

(Border micromirrors eliminated for clarity)

0

Nœ1

Micromirror Pitch

Micromirror Hinge-Axis Orientation

P (um)

—On-State“

Tilt Direction

45°

—Off-State“

Tilt Direction

P (um)

Figure 11. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation

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Package Pin

A1 Corner

DLP7000UV

Two Two

“On-State” “Off-State”

Micromirrors Micromirrors

For Reference

Flat-State

( “parked” )

Micromirror Position

a

b

-a

b

Silicon Substrate

“On-State”

Micromirror

“Off-State”

Micromirror

Figure 12. Micromirror Landed Positions and Light Paths

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8.4 Device Functional Modes

8.4.1 DMD Operation

The DLP7000UV has only one functional mode, it is set to be highly optimized for low latency and high speed in

generating mirror clocking pulses and timings.

When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000UV can be

operated in several display modes. The DLP7000UV is loaded as 16 blocks of 48 rows each. Figure 13,

Figure 14, Figure 15, and Figure 16 show how the image is loaded by the different Micromirror Clocking Pulse

modes.

There are four Micromirror Clocking Pulse modes that determine which blocks are reset when a Micromirror

Clocking Pulse command is issued:

•

Single block mode

Dual block mode

Quad block mode

Global mode

8.4.1.1 Single Block Mode

In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset

to transfer the information to the mechanical state of the mirrors.

Data Loaded

Reset

Figure 13. Single Block Mode

8.4.1.2 Dual Block Mode

In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be

reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of

the mirrors.

Data Loaded

Reset

Figure 14. Dual Block Mode

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Device Functional Modes (continued)

8.4.1.3 Quad Block Mode

In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each

quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the

information to the mechanical state of the mirrors.

Data Loaded

Reset

Figure 15. Quad Block Mode

8.4.1.4 Global Mode

In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be

loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of

the mirrors.

Reset

Data Loaded

Figure 16. Global Mode

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8.5 Window Characteristics and Optics

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

8.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

8.5.2 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light

path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt

angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.

8.5.3 Pupil Match

TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance

pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border

and/or active area, which may require additional system apertures to control, especially if the numerical aperture

of the system exceeds the pixel tilt angle.

8.5.4 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical

operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the

window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical

system should be designed to limit light flux incident anywhere on the window aperture from exceeding

approximately 10% of the average flux level in the active area. Depending on the particular system’s optical

architecture, overfill light may have to be further reduced below the suggested 10% level in order to be

acceptable.

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8.6 Micromirror Array Temperature Calculation

Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the

maximum temperature of any individual micromirror in the active array, the maximum temperature of the window

aperture, and the temperature gradient between case temperature and the predicted micromirror array

temperature (See Figure 17).

See the Recommended Operating Conditions for applicable temperature limits.

8.6.1 Package Thermal Resistance

The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can

be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the

package within the specified operational temperatures, refer to Figure 17. The total heat load on the DMD is

typically driven by the incident light absorbed by the active area; although other contributions include light energy

absorbed by the window aperture and electrical power dissipation of the array.

8.6.2 Case Temperature

The temperature of the DMD case can be measured directly. For consistency, Thermal Test Point locations 1, 2,

and 3 are defined, as shown in Figure 17.

3X 15.88

TP1

TP3

TP2

TP3 (TP2)

Array

TP2

TP3

TP1

10.16

Figure 17. Thermal Test Point Location

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Micromirror Array Temperature Calculation (continued)

8.6.3 Micromirror Array Temperature Calculation

Active array temperature cannot be measured directly; therefore, it must be computed analytically from

measurement points on the outside of the package, package thermal resistance, electrical power, and

illumination heat load. The relationship between array temperature and the reference ceramic temperature (test

point number 1 in Figure 17) is provided by the following equations:

T_Array= Measured Ceramic temperature at location (test point number 3) + (Temperature increase due to power incident

to the array × array-to-ceramic resistance)

(1)

T_Array= T_Ceramic+ (Q_Array× R_{Array-To-Ceramic}

)

where

•

T_Ceramic= Measured ceramic temperature (°C) at location (test point number 3)

R_{Array-To-Ceramic}= DMD package thermal resistance from array to outside ceramic (°C/W)

Q_Array= Total DMD array power, which is both electrical plus absorbed on the DMD active array (W)

Q_Array= Q_Electrical+ (Q_Illumination× DMD absorption constant (0.42))

where

•

Q_Electrical= Approximate nominal electrical internal power dissipation (W)

Q_Illumination= [Illumination power density × illumination area on DMD] (W)

DMD absorption constant = 0.42

(2)

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. The nominal electrical power dissipation of the DMD is variable and depends on the operating state

of mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation

with an illumination distribution of 83.7% on the active array, 11.9% on the array border, and 4.4% on the window

aperture. A system aperture may be required to limit power incident on the package aperture since this area

absorbs much more efficiently than the array.

Sample Calculation:

•

Illumination power density = 2 W/cm²

Illumination area = (1.4008 cm × 1.0506 cm) / 83.7% = 1.76 cm²(assumes 83.7% on the active array and

16.3% overfill)

•

Q_Illumination= 2 W/cm²× 1.76 cm²= 3.52 W

Q_Electrical= 2.0 W

R_{Array-To-Ceramic}= 0.9°C/W

T_Ceramic= 20°C (measured on ceramic)

Q_Array= 2.0 W + (3.52 W × 0.42) = 3.48 W

T_Array= 20°C + (3.48 W × 0.9°C/W) =23.1°C

(3)

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8.7 Micromirror Landed-On/Landed-Off Duty Cycle

8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On–state versus the amount of time the same

micromirror is landed in the Off–state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the

time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of

the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

8.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

8.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life.

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a given long-term average Landed Duty Cycle.

8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5.

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Table 5. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLP7000UV devices require they be coupled with the DLPC410 controller to provide a reliable solution for

many different applications. The DMDs are spatial light modulators which reflect incoming light from an

illumination source to one of two directions, with the primary direction being into a projection collection optic.

Each application is derived primarily from the optical architecture of the system and the format of the data

coming into the DLPC410. Applications of interest include lithography, 3D Printing, medical systems, and

compressive sensing.

9.1.1 DMD Reflectivity Characteristics

TI assumes no responsibility for end-equipment reflectivity performance. Achieving the desired end-equipment

reflectivity performance involves making trade-offs between numerous component and system design

parameters. DMD reflectivity characteristics over UV exposure times are represented in Figure 18.

100

90

80

70

60

50

40

30

20

20èC

25èC

10

30èC

0

10000

20000

30000

40000

50000

Exposure Hours

D001

2.3 W/cm², 363 to 400 nm

Figure 18. Nominal DMD Relative Reflectivity Percentage and Exposure Hours

DMD reflectivity includes micromirror surface reflectivity and window transmission. The DMD was characterized

for DMD reflectivity using a broadband light source (200-W metal-halide lamp). Data is based off of a 2.3-W/cm²

UV exposure at the DMD surface (363-nm peak output) using a 363-nm high-pass filter between the light source

and the DMD. (Contact your local Texas Instruments representative for additional information about power

density measurements and UV filter details.)

9.1.2 Design Considerations Influencing DMD Reflectivity

Optimal, long-term performance of the digital micromirror device (DMD) can be affected by various application

parameters. Below is a list of some of these application parameters and includes high level design

recommendations that may help extend relative reflectivity from time zero:

•

Illumination spectrum – using longer wavelengths for operation while preventing shorter wavelengths from

striking the DMD

•

Illumination power density – using lower power density

DMD case temperature – operating the DMD with the case temperature at the low end of its specification

Cumulative incident illumination – limiting the total hours of UV illumination exposure when the DMD is not

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Application Information (continued)

actively steering UV light in the application. For example, a design might include a shutter to block the

illumination or LED illumination where the LEDs can be strobed off during periods not requiring UV exposure.

•

Micromirror landed duty cycle – applying a 50/50 duty cycle pattern during periods where operational patterns

are not required.

9.2 Typical Application

OPTICAL

SENSOR

(CAMERA)

LED

DRIVERS

LEDS

OPTICS

LED

SENSORS

LVDS BUS (A,B)

DDC_DCLK, DVALID, DDC_DIN(15:0)

LVDS BUS (A,B)

DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)

USER

INTERFACE

SCP BUS

SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, A_SCPENZ

ROW and BLOCK SIGNALS

ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ

CONTROL SIGNALS

COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT

DLP7000UV

DLPA200 CONTROL

A_MODE(1:0), A_SEL(1:0),

DLPA200

MBRST1_(15:0)

CONNECTIVITY

USER - MAIN

DLPC410 INFO SIGNALS

RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,

DMD_TYPE(3:0), DDC_VERSION(2:0)

(USB, ETHERNET, ETC.)

A_ADDR(3:0), OEZ, INIT

PROCESSOR / FPGA

A

DLPC410

PGM SIGNALS

PROM_CCK_DDC, PROGB_DDC,

PROM_DO_DDC, DONE_DDC, INTB_DDC

DLPR410

VOLATILE

and

NON-VOLATILE

STORAGE

JTAG

VLED0

VLED1

ARSTZ

CLKIN_R

OSC

50 MHz

DMD_RESET

POWER MANAGMENT

~

Figure 19. DLPC410 and DLP7000UV Embedded Example Block Diagram

9.2.1 Design Requirements

All applications using the DLP7000UV chipset require both the controller and the DMD components for operation.

The system also requires an external parallel flash memory device loaded with the DLPC410 Configuration and

Support Firmware. The chipset has several system interfaces and requires some support circuitry. The following

interfaces and support circuitry are required:

•

DLPC410 system interfaces:

–

Control interface

Trigger interface

Input data interface

Illumination interface

Reference clock

•

DLP7000UV interfaces:

–

DLPC410 to DLP7000UV digital data

DLPC410 to DLP7000UV control interface

DLPC410 to DLP7000UV micromirror reset control interface

DLPC410 to DLPA200 micromirror driver

DLPA200 to DLP7000UV micromirror reset

Device Description:

The DLP7000UV XGA chipset offers developers a convenient way to design a wide variety of industrial, medical,

telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data,

and light patterns.

The DLP7000UV XGA chipset includes the following four components: DMD Digital Controller (DLPC410),

EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000UV).

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Typical Application (continued)

DLPC410 Digital Controller for DLP Discovery 4100 chipset

•

Provides high speed LVDS data and control interface to the DLP7000UV.

Drives mirror clocking pulse and timing information to the DLPA200.

Supports random row addressing.

DLPR410 PROM for DLP Discovery 4100 chipset

Contains startup configuration information for the DLPC410.

DLPA200 DMD Micromirror Driver

Generates Micromirror Clocking Pulse control (sometimes referred to as a Reset) of DMD mirrors.

DLP7000UV DLP 0.7XGA 2xLVDS UV Type-A DMD

•

Steers light in two digital positions (+12° and –12°) using 1024 × 768 micromirror array of aluminum mirrors.

Table 6. DLP Discovery 4100 Chipset Configuration: 0.7 XGA Chipset

QTY

TI PART

DLP7000UV

DLPC410

DLPR410

DLPA200

DESCRIPTION

DLP 0.7XGA 2xLVDS UV Type-A DMD

Digital Controller for DLP Discovery 4100 chipset

DLP Discovery 4100 configuration PROM

DMD micromirror driver

1

Reliable function and operation of DLP7000UV XGA chipsets require the components be used in conjunction

with each other. This document describes the proper integration and use of the DLP7000UV XGA chipset

components.

The DLP7000UV XGA chipset can be combined with a user programmable Application FPGA (not included) to

create high performance systems.

9.2.2 Detailed Design Procedure

The DLP7000UV DMD is designed with a window which allows transmission of Ultra-Violet (UV) light. This

makes it well suited for UV applications requiring fast, spatially programmable light patterns using the micromirror

array. UV wavelengths can affect the DMD differently than visible wavelengths. There are system level

considerations which should be leveraged when designing systems using this DMD.

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9.2.3 Application Curve

100

90

80

70

UV AOI = 0^o

60

50

40

30

20

10

0

300

320

340

360

380

400

420

440

460

480

500

Wavelength (nm)

Type A UVA on 7056 glass (3-mm thick)

Figure 20. Corning 7056 Nominal UV Window Transmittance (Maximum Transmission Region)

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10 Power Supply Recommendations

10.1 Power-Up Sequence (Handled by the DLPC410)

The sequence of events for DMD system power-up is:

1. Apply logic supply voltages to the DLPA200 and to the DMD according to DMD specifications.

2. Place DLPA200 drivers into high impedance states.

3. Turn on DLPA200 bias, offset, or reset supplies according to driver specifications.

4. After all supply voltages are assured to be within the limits specified and with all micromirror clocking pulse

operations logically suspended, enable all drivers to either VOFFSET or VBIAS level.

5. Begin micromirror clocking pulse operations.

Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.

The DLP7000UV power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024).

These procedures must be followed to ensure reliable operation of the device.

11 Layout

11.1 Layout Guidelines

The DLP7000UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These

guidelines are targeted at designing a PCB board with these components.

11.1.1 Impedance Requirements

Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs

(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across

each pair.

11.1.2 PCB Signal Routing

When designing a PCB board for the DLP7000UV controlled by the DLPC410 in conjunction with the DLPA200,

the following are recommended:

Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces

routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2

Memory, DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces should not crossover slots in adjacent power and/or ground planes.

Table 7. Important Signal Trace Constraints

SIGNAL

CONSTRAINTS

P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle

<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)

Trace width: 4 mil (0.1 mm)

Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)

Maximum recommended trace length <6 inches (150 mm)

LVDS (DMD_DAT_xnn,

DMD_DCKL_xn, and

DMD_SCTRL_xn)

Table 8. Power Trace Widths and Spacing

MINIMUM TRACE

SPACING

SIGNAL NAME

LAYOUT REQUIREMENTS

WIDTH

GND

Maximize

5 mil (0.13 mm)

10 mil (0.25 mm)

Maximize trace width to connecting pin as a minimum

VCC, VCC2

MBRST[15:0]

20 mil (0.51 mm)

10 mil (0.25 mm)

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11.1.3 Fiducials

Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials

for optical auto insertion are placed on three corners of both sides of the PCB.

11.1.4 PCB Layout Guidelines

A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal

layers.

11.1.4.1 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data

is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS

signals should have 100-Ω differential impedance. The differential signals should be matched but kept as short

as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not

necessary.

11.1.4.1.1 Trace Length Matching

The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of

100 Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair

uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all

signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal

DMD routing must be considered in this calculation.

11.1.4.2 DLP7000UV Decoupling

General decoupling capacitors for the DLP7000UV should be distributed around the PCB and placed to minimize

the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have

vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is

discouraged. The power and ground pads of the DLP7000UV should be tied to the voltage and ground planes

with their own vias.

11.1.4.2.1 Decoupling Capacitors

Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and

ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors

meet the following guidelines:

•

The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The

decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to

the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be

tied to the voltage or ground plane through separate vias.

•

The trace lengths of the voltage and ground connections for decoupling capacitors and components should

be less than 0.1 inch to minimize inductance.

The trace width of the power and ground connection to decoupling capacitors and components should be as

wide as possible to minimize inductance.

Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance.

Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

11.1.4.3 VCC and VCC2

The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should

be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each

decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND

pads of the DMD should be tied to the VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the

distance from the VCC2 and ground pads of the DMD. Using wide etch from the decoupling capacitors to the

DMD connection will reduce inductance and improve decoupling performance.

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11.1.4.4 DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.

11.1.4.5 DLPA200

The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the

DLPA200 (MBRST[15:0]) should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.

The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum

trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet (DLPS015) for

mechanical package and layout information.

11.2 Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the

dashed lines, Figure 21 shows correct matching of signal pair lengths with serpentine sections to maintain the

correct impedance.

Figure 21. Mitering LVDS Traces to Match Lengths

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12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

图 22 提供了读取任一 DLP 器件完整器件名称的图例。

图 22. 器件命名规则

12.1.1.1 器件标记

器件标记由图 23 中显示的字段组成。

TI Internal Numbering

2-Dimensional Matrix Code

(DMD Part Number and

Serial Number)

DMD Part Number

YYYYYYY

DLP7000UVFLP

GHXXXXX LLLLLLM

LLLLLL

Part 2 of Serial Number

(7 characters)

Part 1 of Serial Number

(7 characters)

TI Internal Numbering

图 23. 器件标记

12.2 文档支持

12.2.1 相关文档

以下文档包含关于使用 DLP7000UV 器件的更多信息：

表 9. 相关文档

文档标题

文档链接

《适用于 DLP Discovery 4100 芯片组的 DLPC410 数字控制器产品说明书》

《DLPA200 DMD 微镜驱动器产品说明书》

DLPS024

DLPS015

DLPS027

《适用于 DLP Discovery 4100 芯片组的 DLPR410 PROM 产品说明书》

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12.3 相关链接

下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的

快速链接。

表 10. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

DLP7000UV

DLPA200

DLPC410

DLPR410

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12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

Discovery, E2E are trademarks of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

47

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP7000UV
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.7XGA 2xLVDS UV A 型 DMD
文件：	总53页 (文件大小：2002K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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