DLPC1438ZEZ_技术文档

DLPC1438

ZHCSOH4A –JULY 2021 –REVISED AUGUST 2021

DLPC1438 适用于TI DLP^®3D 打印机的数字控制器

1 特性

2 应用

• 适用于DLP300S 和DLP301S（0.3 英寸360 万像

素）DMD 的数字控制器

• 3D 打印特性：

• TI DLP® 3D 打印机

– 增材制造

– 光聚合

– 掩模立体光刻（mSLA 3D 打印机）

• 牙科DLP 3D 打印机

• 曝光：可编程空间和时间曝光

– 经过优化的线性伽马模式，用于优化照明均匀性

和灰度打印

– 可编程层曝光时间

– 8 位单色灰度输出

3 说明

• 系统特性:

DLPC1438 3D 打印控制器可为适用于 DLP 3D 打印机

应用的 DLP300S 和 DLP301S 数字微镜器件 (DMD)

的可靠运行提供支持。DLPC1438 控制器可在用户电

子产品和 DMD 之间提供一个便捷的接口，以支持快

速、可靠的高分辨率DLP 3D 打印机。

– 带有低成本SPI 数据输入接口的前端FPGA

– 传动器控制

– 器件配置的I2C 控制

– 可编程LED 电流控制

• 针对DLP 3D 打印机应用中的可靠性能进行了运行

优化

• 与DLPA2000、DLPA2005、DLPA3000 或

DLPA3005 PMIC（电源管理集成电路）和LED 驱

动器配对使用

TI DLP® 光控制技术入门页，了解如何开始使用

DLP300S。

ti.com 上的 DLP 先进光控制资源可加快上市速度，这

些资源包括参考设计、光学模块制造商和 DLP 设计网

络合作伙伴。

器件信息

封装尺寸（标称值）

器件型号

封装

DLPC1438 ⁽¹⁾

NFBGA (201)

13.00mm x 13.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V

LED

SYSPWR

1.8 V external

1.8 V

PROJ_ON

GPIO_8 SPI1

DLP PMIC

2

I

C

R

LIM

RESETZ

PARKZ

HOST_IRQ

Parallel (12)

SUB_FRAME

SPI

Illumination

optics

VDD

ACT_SYNC

2

DLP Controller

FPGA

I

C

V

, V ,

BIAS OFFSET

SPI0

VCC_18

V

RESET

DAC_DATA,

DAC_CLK

1.8 V

Actuator

Drive

DMD

CTRL

VCC_INTF

Sub-LVDS

1.8 V

VCC_FLSH

Circuit

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS216

DLPC1438

ZHCSOH4A –JULY 2021 –REVISED AUGUST 2021

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Table of Contents

7 Detailed Description......................................................25

7.1 Overview...................................................................25

7.2 Functional Block Diagram.........................................25

7.3 Feature Description...................................................26

7.4 Device Functional Modes..........................................34

7.5 Programming............................................................ 34

8 Application and Implementation..................................35

8.1 Application Information............................................. 35

8.2 Typical Application.................................................... 35

9 Power Supply Recommendations................................38

9.1 PLL Design Considerations...................................... 38

9.2 System Power-Up and Power-Down Sequence....... 38

9.3 Power-Up Initialization Sequence.............................41

9.4 DMD Fast Park Control (PARKZ)..............................42

9.5 Hot Plug I/O Usage...................................................42

10 Layout...........................................................................44

10.1 Layout Guidelines................................................... 44

10.2 Layout Example...................................................... 52

11 Device and Documentation Support..........................53

11.1 Device Support........................................................53

11.2 Documentation Support.......................................... 54

11.3 接收文档更新通知................................................... 54

11.4 支持资源..................................................................54

11.5 Trademarks............................................................. 54

11.6 Electrostatic Discharge Caution..............................54

11.7 术语表..................................................................... 54

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications................................................................ 11

6.1 Absolute Maximum Ratings...................................... 11

6.2 ESD Ratings..............................................................11

6.3 Recommended Operating Conditions.......................12

6.4 Thermal Information..................................................12

6.5 Power Electrical Characteristics............................... 13

6.6 Pin Electrical Characteristics.................................... 14

6.7 Internal Pullup and Pulldown Electrical

Characteristics.............................................................16

6.8 DMD Sub-LVDS Interface Electrical

Characteristics.............................................................17

6.9 DMD Low-Speed Interface Electrical

Characteristics.............................................................18

6.10 System Oscillator Timing Requirements.................19

6.11 Power Supply and Reset Timing Requirements......19

6.12 Parallel Interface Frame Timing Requirements.......20

6.13 Parallel Interface General Timing Requirements.... 21

6.14 BT656 Interface General Timing Requirements......22

6.15 Flash Interface Timing Requirements..................... 23

6.16 Other Timing Requirements....................................23

6.17 DMD Sub-LVDS Interface Switching

Characteristics.............................................................24

6.18 DMD Parking Switching Characteristics................. 24

6.19 Chipset Component Usage Specification............... 24

Information.................................................................... 54

4 Revision History

Changes from Revision (July 2021) to Revision A (August 2021)

Page

• 将器件状态从预告信息更改为量产数据.............................................................................................................1

2

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5 Pin Configuration and Functions

图5-1. ZEZ Package 201-Pin NFBGA Bottom View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

P

CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM

SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0

A

B

C

D

E

F

LK

DATA

DATAH_P DATAG_P

DATAF_P

DATAE_P

DATAD_P

DATAC_P

DATAB_P

DATAA_P

DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

N

ARSTZ

DATA

DATAH_N DATAG_N

DATAF_N

DATAE_N

DATAD_N

DATAC_N

DATAB_N

DATAA_N

HWTEST_E

N

DD3P

DD3N

VDDLP12

VDD

VSS

VCC

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

VSS

VCC

RESETZ SPI0_CSZ1

PARKZ

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

GPIO_00

GPIO_02

GPIO_04

GPIO_06

GPIO_08

GPIO_10

GPIO_12

GPIO_14

GPIO_16

GPIO_01

GPIO_03

GPIO_05

GPIO_07

GPIO_09

GPIO_11

GPIO_13

GPIO_15

GPIO_17

GPIO_19

TSTPT_7

TSTPT_5

TSTPT_3

DD2P

DCLKP

DD1P

DD2N

DCLKN

DD1N

VDD

VSS

VDD

VSS

VCC_FLSH

VDD

VCC

VSS

VDD

VSS

VDD

VSS

VDD

RREF

VSS

DD0P

DD0N

VSS_PLLM

G

H

J

PLL_REFCL

K_I

VDD_PLLM VSS_PLLD

PLL_REFCL

K_O

VDD_PLLD

PDATA_0

PDATA_2

PDATA_4

PDATA_6

VSS

VDD

PDATA_1

PDATA_3

PDATA_5

PDATA_7

VSYNC_WE

PDATA_8

K

L

VSS

VCC_INTF

PCLK

VSS

VDD

3DR

VCC_INTF

VSS

VDD

VCC

JTAGTMS1 GPIO_18

M

N

P

R

PDM_CVS_

TE

HSYNC_CS

VCC_INTF HOST_IRQ IIC0_SDA

IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1

TSTPT_6

TSTPT_4

TSTPT_2

DATEN_CM

D

PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK

JTAGTDI

TSTPT_1

PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22

IIC1_SDA

IIC1_SCL

TSTPT_0

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表5-1. Test Pins and General Control

I/O

TYPE⁽⁴⁾

DESCRIPTION

NAME

HWTEST_EN

NO.

Manufacturing test enable signal. Connect this signal directly to ground on the

PCB for normal operation.

C10

I

6

DMD fast park control (active low Input with a hysteresis buffer). This signal is

used to quickly park the DMD when loss of power is imminent. The longest

lifetime of the DMD may not be achieved with the fast park operation;

therefore, this signal is intended to only be asserted when a normal park

operation is unable to be completed. The PARKZ signal is typically provided

from the DLPAxxxx interrupt output signal.

PARKZ

C13

I

6

JTAGTCK

JTAGTDI

P12

P13

I

6

1

6

TI internal use. Leave this pin unconnected.

JTAGTDO1

JTAGTDO2

JTAGTMS1

JTAGTMS2

N13⁽¹⁾

N12⁽¹⁾

M13

O

I

N11

I

TI internal use.

This pin must be tied to ground, through an external resistor for normal

operation. Failure to tie this pin low during normal operation can cause start

up and initialization problems.⁽²⁾

JTAGTRSTZ

P11

C11

I

6

Power-on reset (active low input with a hysteresis buffer). Self-configuration

starts when a low-to-high transition is detected on RESETZ. All controller

power and clocks must be stable before this reset is de-asserted. No signals

are in their active state while RESETZ is asserted. This pin is typically

connected to the RESETZ pin of the DLPA200x or RESET_Z of the

DLPA300X.

RESETZ

6

TSTPT_0

TSTPT_1

TSTPT_2

R12

R13

R14

I/O

1

Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ

is asserted low. Sampled as an input test mode selection control

approximately 1.5 µs after de-assertion of RESETZ, and then driven as

outputs.^{(2) (3)}

Normal use: reserved for test output. Leave open for normal use.

Note: An external pullup may put the DLPC1438 in a test mode. See 节7.3.6

for more information.

TSTPT_3

TSTPT_4

R15

P14

I/O

1

Test pin 4 (Includes weak internal pulldown) –tri-stated while RESETZ is

asserted low. Sampled as an input test mode selection control approximately

1.5 μs after de-assertion of RESETZ and then driven as an output.

TSTPT_5

TSTPT_6

P15

N14

I/O

1

Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ

is asserted low. Sampled as an input test mode selection control

approximately 1.5 µs after de-assertion of RESETZ, and then driven as

outputs.^{(2) (3)}

Normal use: reserved for test output. Leave open for normal use.

Note: An external pullup may put the DLPC1438 in a test mode. See 节7.3.6

for more information.

TSTPT_7

N15

I/O

1

(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal

pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an

external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is

recommended to ensure a logic low.

(2) External resistor must have a value of 8 kΩor less to compensate for pins that provide internal pullup or pulldown resistors.

(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal

pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but

there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to

ensure a logic low.

(4) See 表5-10 for type definitions.

表5-2. Parallel Port Input

PIN⁽¹⁾

I/O

TYPE⁽³⁾

DESCRIPTION

NAME

NO.

PCLK

P3

I

11

Pixel clock

4

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表5-2. Parallel Port Input (continued)

PIN⁽¹⁾

I/O

TYPE⁽³⁾

DESCRIPTION

NAME

NO.

Parallel data mask. Programable polarity with

default of active high. Optional signal.

PDM_CVS_TE

N4

I/O

5

VSYNC_WE

HSYNC_CS

DATAEN_CMD

P1

N5

P2

I

11

Vsync⁽²⁾

Hsync⁽²⁾

Data valid

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

K2

K1

L2

(bit weight 1)

(bit weight 2)

(bit weight 4)

(bit weight 8)

(bit weight 16)

(bit weight 32)

(bit weight 64)

(bit weight 128)

L1

I

11

M2

M1

N2

N1

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

R1

R2

R3

P4

R4

P5

R5

P6

I

Unused

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

R6

P7

R7

P8

R8

P9

R9

P10

I

11

Unused

3DR

N6

(1) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩor less).

(2) VSYNC and HSYNC polarity can be adjusted by software.

(3) See 表5-10 for type definitions.

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表5-3. DSI Input Data and Clock

I/O

Type⁽¹⁾

DESCRIPTION

NAME

NO.

DCLKN

DCLKP

E2

E1

---

unused; Leave unconnected and floating.

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

G2

G1

F2

F1

D2

D1

C2

C1

---

unused; Leave unconnected and floating.

Leave this pin unconnected and floating.

RREF

F3

—

(1) See 表5-10 for type definitions.

表5-4. DMD Reset and Bias Control

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DMD driver enable (active high). DMD reset (active low). When

corresponding I/O power is supplied, the controller drives this signal low

after the DMD is parked and before power is removed from the DMD. If the

1.8-V power to the DLPC1438 is independent of the 1.8-V power to the

DMD, then TI recommends including a weak, external pulldown resistor to

hold the signal low in case DLPC1438 power is inactive while DMD power

is applied.

DMD_DEN_ARSTZ

B1

O

2

DMD_LS_CLK

A1

A2

B2

O

I

3

6

DMD, low speed (LS) interface clock

DMD, low speed (LS) serial write data

DMD, low speed (LS) serial read data

DMD_LS_WDATA

DMD_LS_RDATA

(1) See 表5-10 for type definitions.

表5-5. DMD Sub-LVDS Interface

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DMD_HS_CLK_P

DMD_HS_CLK_N

A7

B7

O

4

DMD high speed (HS) interface clock

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A3

B3

A4

B4

A5

B5

A6

B6

A8

B8

A9

B9

A10

B10

A11

B11

DMD sub-LVDS high speed (HS) interface write data lanes. The true

numbering and application of the DMD_HS_WDATA pins depend on the

software configuration. See 表7-9.

O

4

(1) See 表5-10 for type definitions.

6

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表5-6. Peripheral Interface⁽¹⁾

PIN⁽¹⁾

NAME

I/O

TYPE⁽³⁾

DESCRIPTION

NO.

Successive approximation ADC (analog-to-digital converter) comparator output

(DLPC1438 Input). To implement, use a successive approximation ADC with a

thermistor feeding one input of the external comparator and the DLPC1438

controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator.

It is recommended to use the DLPAxxxx to achieve this function. CMP_OUT

must be pulled-down to ground if this function is not used. (hysteresis buffer)

CMP_OUT

A12

I

6

CMP_PWM

A15

N8

O

1

9

TI internal use. Leave this pin unconnected.

Host interrupt (output)

HOST_IRQ indicates when the DLPC1438 auto-initialization is in progress and

most importantly when it completes.

HOST_IRQ⁽²⁾

This pin is tri-stated during reset. An external pullup must be included on this

signal.

I²C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The slave I²C I/Os are 3.6-V tolerant

(high-voltage-input tolerant) and are powered by VCC_INTF (which can be 1.8,

2.5, or 3.3 V). External I²C pullups must be connected to a host supply with an

equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply

voltage does not typically satisfy the V_IHspecification of the slave I²C input

buffers).

IIC0_SCL⁽⁴⁾

IIC1_SCL

N10

R11

N9

I/O

7

8

7

8

TI internal use. TI recommends an external pullup resistor.

I²C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The slave I²C port is the control port

of controller. The slave I²C I/O pins are 3.6-V tolerant (high-volt-input tolerant)

and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C

pullups must be connected to a host supply with an equal or higher supply

voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not

typically satisfy the V_IHspecification of the slave I²C input buffers).

IIC0_SDA⁽⁴⁾

IIC1_SDA

R10

TI internal use. TI recommends an external pullup resistor.

LED enable select. Automatically controlled by the DLPC1438 programmable

DMD sequence

LED_SEL(1:0)

Enabled LED

None

Red

Green

Blue

LED_SEL_0

LED_SEL_1

B15

B14

O

1

00

01

10

11

The controller drives these signals low when RESETZ is asserted and the

corresponding I/O power is supplied. The controller continues to drive these

signals low throughout the auto-initialization process. A weak, external pulldown

resistor is recommended to ensure that the LEDs are disabled when I/O power is

not applied.

SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to

the flash memory clock.

SPI0_CLK

A13

A14

O

13

SPI port 0, chip select 0 (active low output). This pin is typically connected to the

flash memory chip select.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ0

SPI port 0, chip select 1 (active low output). This pin typically remains unused.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ1

C12

O

13

Synchronous serial port 0, receive data in. This pin is typically connected to the

flash memory data out.

SPI0_DIN

B12

B13

I

12

13

Synchronous serial port 0, transmit data out. This pin is typically connected to

the flash memory data in.

SPI0_DOUT

O

(1) External pullup resistor must be 8 kΩor less.

(2) For more information about usage, see 节7.3.3.

(3) See 表5-10 for type definitions.

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(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication

on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional slave devices

on this bus.

表5-7. GPIO Peripheral Interface⁽¹⁾

PIN⁽¹⁾

I/O TYPE⁽³⁾

DESCRIPTION⁽²⁾

NAME

NO.

General purpose I/O 19 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_19

M15

I/O

1

General purpose I/O 18 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_18

GPIO_17

GPIO_16

GPIO_15

M14

L15

L14

K15

General purpose I/O 17 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 16 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 15 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 14 (hysteresis buffer). FPGA_RDY (input): Input from FPGA, indicating when the

FPGA initialization process is complete.

GPIO_14

GPIO_13

K14

J15

I/O

1

General purpose I/O 13 (hysteresis buffer). AWG_ERR (input): Input from FPGA, indicating instability

in actuator operation in order to halt printing and recover.

General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_12

J14

I/O

1

General purpose I/O 11 (hysteresis buffer). Options:

1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and

enabled.

GPIO_11

H15

I/O

1

2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

General Purpose I/O 10 (hysteresis buffer). Options:

1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.

2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

GPIO_10

H14

I/O

1

General purpose I/O 09 (hysteresis buffer). Reserved for Print Active signal. Indicates that a layer is

GPIO_09

GPIO_08

G15

G14

I/O

1

actively being printed with previously sent print layer command. Applicable to External Print Mode

only.

General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven

by the PROJ_ON output of the host. A logic low on this signal causes the DLPC1438 to PARK the

DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high

time is 200 ms. The minimum low time is 200 ms.

General purpose I/O 07 (hysteresis buffer). ACT_SYNC (output): Output to FPGA, used for

synchronizing the actuator position with the controller data processing.

GPIO_07

GPIO_06

F15

F14

I/O

1

General purpose I/O 06 (hysteresis buffer). Reserved for System Ready signal (Output). Indicates

when system is configured and ready for first print layer command after being commanded to go into

External Print Mode. Applicable to External Print Mode only.

General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_05

E15

I/O

1

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表5-7. GPIO Peripheral Interface⁽¹⁾(continued)

PIN⁽¹⁾

I/O TYPE⁽³⁾

DESCRIPTION⁽²⁾

NAME

NO.

General purpose I/O 04 (hysteresis buffer). Options:

1. SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup

resistor to deactivate this signal during reset and auto-initialization processes.

2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

GPIO_04

E14

I/O

1

General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.

This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to

deactivate this signal during reset and auto-initialization processes.

GPIO_03

D15

I/O

1

General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is

typicallyconnected to the DLPAxxxx SPI_DIN pin.

GPIO_02

GPIO_01

GPIO_00

D14

C15

C14

I/O

1

General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically

connected to the DLPAxxxx SPI_CLK pin.

General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is

typically connected to the DLPAxxxx SPI_DOUT pin.

(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or

more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as

open-drain.

(2) General purpose I/O for the DLPC1438 controller. These GPIO pins are software configurable.

(3) See 表5-10 for type definitions.

表5-8. Clock and PLL Support

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Reference clock crystal input. If an external oscillator is used instead of a crystal, use

this pin as the oscillator input.

PLL_REFCLK_I

H1

I

11

5

Reference clock crystal return. If an external oscillator is used instead of a crystal,

leave this pin unconnected (floating with no added capacitive load).

PLL_REFCLK_O

J1

O

(1) See 表5-10 for type definitions.

表5-9. Power and Ground

I/O

TYPE

DESCRIPTION

NAME

NO.

C5, D5, D7,

D12, J4,

J12, K3, L4,

L12, M6,

M9, D9,

D13, F13,

H13, L13,

M10, D3, E3

VDD

PWR

---

Core 1.1-V power (main 1.1 V)

—

VDDLP12

C3

Unused. It is recommended to externally tie this pin to VDD.

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表5-9. Power and Ground (continued)

I/O

TYPE

DESCRIPTION

NAME

NO.

C4, D6, D8,

D10, E4,

E13, F4, G4,

G12, H4,

H12, J3,

J13, K4,

K12, L3, M4,

M5, M8,

M12, G13,

C6, C8, F6,

F7, F8, F9,

F10, G6,

VSS

GND

Core ground (eDRAM, DSI, I/O ground, thermal ground)

—

G7, G8, G9,

G10, H6,

H7, H8, H9,

H10, J6, J7,

J8, J9, J10,

K6, K7, K8,

K9, K10

All 1.8-V I/O power:

C7, C9, D4,

E12, F12,

K13, M11

(1.8-V power supply for all I/O pins except the host or parallel interface

and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL,

CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins)

VCC18

PWR

—

M3, M7, N3,

N7

Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA,

video syncs, and HOST_IRQ pins)

VCC_INTF

VCC_FLSH

PWR

—

Flash interface I/O power: 1.8 V to 3.3 V

(Dedicated SPI0 power pin)

D11

VDD_PLLM

VSS_PLLM

VDD_PLLD

VSS_PLLD

H2

G3

J2

PWR

RTN

PWR

RTN

MCG PLL (master clock generator phase lock loop) 1.1-V power

MCG PLL return

—

DCG PLL (DMD clock generator phase lock loop) 1.1-V power

DCG PLL return

H3

表5-10. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

1

2

1.8-V LVCMOS I/O buffer with 8-mA drive

1.8-V LVCMOS I/O buffer with 4-mA drive

1.8-V LVCMOS I/O buffer with 24-mA drive

1.8-V sub-LVDS output with 4-mA drive

1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive

1.8-V LVCMOS input

V_cc18

ESD diode to GND and supply rail

3

V_cc18

4

V_cc18

5

V_{cc_INTF}

V_cc18

V_{cc_INTF}

V_cc18

6

7

1.8-V, 2.5-V, 3.3-V I²C with 3-mA drive

1.8-V I²C with 3-mA drive

8

9

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

Reserved

V_{cc_INTF}

10

11

12

13

1.8-V, 2.5-V, 3.3-V LVCMOS input

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

V_{cc_INTF}

V_{cc_FLSH}

ESD diode to GND and supply rail

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGE ⁽²⁾

V_(VDD)

1.21

1.32

1.96

3.60

1.21

See ⁽³⁾

V

–0.3

V_(VDDLP12)

V_(VCC18)

DMD Sub-LVDS Interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)

V_{(VCC_INTF)}

V_{(VCC_FLSH)}

V_{(VDD_PLLM)}(MCG PLL)

V_{(VDD_PLLD)}(DCG PLL)

V_{I2C buffer}(I/O type 7)

GENERAL

T_J

Operating junction temperature

Storage temperature

125

°C

–30

–40

T_stg

(1) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS (GND).

(3) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.045

NOM

1.10

MAX

UNIT

V

V_(VDD)

Core power 1.1 V (main 1.1 V)

Unused

1.155

V_(VDDLP12)

V

All 1.8-V I/O power:

(1.8-V power supply for all I/O pins except the host or

parallel interface and the SPI flash interface. This includes

RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO, IIC1,

TSTPT, and JTAG pins.)

V_(VCC18)

1.64

1.80

1.96

V

1.64

2.28

1.80

2.50

1.96

2.72

3.58

1.96

2.72

3.58

1.155

85

Host or parallel interface I/O power: 1.8 to 3.3 V (includes

IIC0, PDATA, video syncs, and HOST_IRQ pins)

V_{(VCC_INTF)}

See ⁽¹⁾

V

3.02

3.30

1.64

1.80

V_{(VCC_FLSH)}

Flash interface I/O power: 1.8 V to 3.3 V

2.28

2.50

3.02

3.30

V_{(VDD_PLLM)}

MCG PLL 1.1-V power

See ⁽²⁾

1.025

–30

1.100

V

V_{(VDD_PLLD)}

DCG PLL 1.1-V power

T_A

T_J

Operating ambient temperature⁽³⁾

°C

Operating junction temperature

105

(1) These supplies have multiple valid ranges.

(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop

across the filter.

(3) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value

at 0 forced air flow (R_θJAat 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum

estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects R_θJA

Thus, maximum operating ambient temperature varies by application.

.

•

T_{a_min}= T_{j_min}–(P_{d_min}× R_θJA) = –30°C –(0.0 W × 28.8°C/W) = –30°C

T_{a_max}= T_{j_max}–(P_{d_max}× R_θJA) = +105°C –(0.348 W × 28.8°C/W) = +95.0°C

6.4 Thermal Information

DLPC1438 controller

THERMAL METRIC⁽¹⁾

ZEZ (NFBGA)

201 PINS

10.1

UNIT

°C/W

R_θJC

Junction-to-case thermal resistance

at 0 m/s of forced airflow⁽²⁾

28.8

Junction-to-air thermal

R_θJA

at 1 m/s of forced airflow⁽²⁾

at 2 m/s of forced airflow⁽²⁾

25.3

resistance

24.4

Temperature variance from junction to package top center temperature, per

unit power dissipation⁽³⁾

0.23

°C/W

ψ_JT

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC

defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC1438 controller PCB and thus the

reported thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be

different , it is the best information available during the design phase to estimate thermal performance.

(3) Example: (0.5 W) × (0.2 °C/W) ≈0.1°C temperature rise.

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6.5 Power Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER^{(3) (4) (5)}

TEST CONDITIONS

MIN

TYP ⁽¹⁾

MAX ⁽²⁾UNIT

I_(VDD)

I_{(VDD_PLLM)}

I_{(VDD_PLLD)}

+

1.1-V rails

8 bit, 60 Hz, External Print Mode

163

278

mA

I_{(VDD_PLLM)}

I_{(VDD_PLLD)}

MCG PLL 1.1V ⁽⁶⁾

DCG PLL 1.1V ⁽⁶⁾

8 bit, 60 Hz, External Print Mode

6

mA

All 1.8-V I/O current: (1.8-V power supply

for all I/O other than the host or parallel

interface and the SPI flash interface)

I_(VCC18)

8 bit, 60 Hz, External Print Mode

35

48

mA

Host or parallel interface I/O current: 1.8 to

I_{(VCC_INTF)}

I_{(VCC_FLSH)}

3.3 V (includes IIC0, PDATA, video syncs, 8 bit, 60 Hz, External Print Mode

2

1

mA

and HOST_IRQ pins) ⁽⁶⁾

Flash interface I/O current: 1.8 to 3.3 V ⁽⁶⁾8 bit, 60 Hz, External Print Mode

(1) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.

(2) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.

(3) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum

nominal voltage (that is 1.8 V).

(4) Input image is 1280 × 720, 8-bits on the parallel interface with 144 MHz pixel clock at the frame rate shown with the DLP300S DMD.

(5) The values do not take into account software updates or customer changes that may affect power performance.

(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor,

30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells.

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6.6 Pin Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

0.7 ×

VCC_INTF

I²C buffer (I/O type 7)

See

(1)

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

1.17

3.6

I/O type 1, 6 for pins noted in ⁽²⁾

VCC18 = 1.8 V

1.3

1.17

1.7

3.6

High-level input

threshold voltage

I/O type 5, 9, 11

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

V_IH

V

I/O type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

1.7

I/O type 5, 9, 11

2.0

I/O type 12, 13

2.0

0.3 ×

VCC_INTF

I²C buffer (I/O type 7)

–0.5

–0.3

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

0.63

I/O type 1, 6 for pins noted in ⁽²⁾

I/O type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

0.5

0.63

0.7

–0.3

1.35

1.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC18 = 1.8 V

Low-level input

threshold voltage

V_IL

V

I/O type 5, 9, 11

I/O type 12, 13

0.7

I/O type 5, 9, 11

I/O type 12, 13

0.8

I/O type 1, 2, 3, 6, 8

I/O type 5, 9, 11

I/O type 12, 13

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC_INTF > 2 V

High-level output

voltage

V_OH

I/O type 5, 9, 11

I/O type 12, 13

V

1.7

I/O type 5, 9, 11

2.4

I/O type 12, 13

2.4

I²C buffer (I/O type 7)

0.4

0.2 ×

VCC_INTF

I²C buffer (I/O type 7)

VCC_INTF < 2 V

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

VCC18 = 1.8 V

0.45

0.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

Low-level output

voltage

V_OL

V

0.7

0.4

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6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

I/O type 2, 4

I/O type 5

VCC18 = 1.8 V

2

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

3.5

10.6

5.4

10.8

7.8

15

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

High-level output

current⁽⁵⁾

I_OH

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_INTF = 2.5V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9, 13

I/O type 13

I/O type 5

I/O type 9

I/O type 13

I²C buffer (I/O type 7)

I/O type 2, 4

I/O type 5

15

3

VCC18 = 1.8 V

2.3

4.6

13.9

5.2

10.4

4.4

8.9

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

Low-level output

current⁽⁶⁾

I_OL

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9

I/O type 13

I/O type 5

I/O type 9

I/O type 13

V_{I2C buffer}< 0.1 ×

VCC_INTF or

V_{I2C buffer}> 0.9 ×

VCC_INTF

I²C buffer (I/O type 7)

10

–10

I/O type 1, 2, 3, 6, 8,

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

10

–10

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

High-impedance

leakage current

I_OZ

µA

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MAX UNIT

6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

CONDITIONS⁽⁴⁾

I²C buffer (I/O type 7)

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

5

3.5

VCC18 = 1.8 V

2.6

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

3.5

pF

Input capacitance

(including package)

C_I

3.5

I/O type 5, 9, 11

I/O type 12, 13

sub-LVDS –DMD high speed

(I/O type 4)

VCC18 = 1.8 V

3

(1) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

(2) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied V_IHand V_ILrange from other 1.8-V

I/O.

(3) The I/O type refers to the type defined in 表5-10.

(4) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply

reference is set to.

(5) At a high level output signal, the given I/O will be able to output at least the minimum current specified.

(6) At a low level output signal, the given I/O will be able to sink at least the minimum current specified.

6.7 Internal Pullup and Pulldown Electrical Characteristics

over operating free-air temperature (unless otherwise noted) ⁽²⁾

TEST

INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS

MIN

MAX

UNIT

CONDITIONS⁽¹⁾

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

29

38

56

30

36

52

63

90

kΩ

Weak pullup resistance

148

72

101

167

Weak pulldown resistance

(1) The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in 表5-10).

(2) An external 8-kΩpullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any

associated internal pullups or pulldowns.

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6.8 DMD Sub-LVDS Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.0

UNIT

V

V_CM

Common mode voltage

0.8

0.9

V_CM(Δpp)⁽¹⁾

V_CMchange peak-to-peak (during switching)

V_CMchange steady state

75

mV

V

V_CM(Δss)⁽¹⁾

–10

170

10

(2)

|V_OD

|

Differential output voltage magnitude

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Internal differential termination

250

350

10

V_OD(Δ)

V_OH

–10

0.825

0.625

80

1.025

0.775

100

1.175

0.975

120

V_OL

V

Tx_term

Ω

100-Ωdifferential PCB trace

(50-Ωtransmission lines)

Tx_load

0.5

6

inches

(1) See 图6-1

(2) V_ODis the differential voltage measured across a 100-Ωtermination resistance connected directly between the transmitter differential

pins. V_OD= V_P- V_N, where P and N are the differential output pins. |V_OD| is the magnitude of the peak-to-peak voltage swing across

the P and N output pins (see 图6-2). V_CMcancels out between signals when measured differentially, thus the reason V_ODswings

relative to zero.

+V

OD

100

90

80

|V_OD|

70

60

V

(û

CM SS

)

V

(û )

CM P-P

V

CM

(0 V) 50

40

30

|V_OD|

20

10

0

œV

OD

t_FALL

t_RISE

图6-1. Common Mode Voltage

V_CMis removed when the signals are viewed differentially

图6-2. Differential Output Signal

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6.9 DMD Low-Speed Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.7 ×

VCC18

V_OH(DC)

V_OL(DC)

V_OH(AC)

V_OL(AC)

V

DC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.3 ×

VCC18

V

AC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.8 ×

VCC18

VCC18 +

0.5

(1)

(2)

AC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.2 ×

VCC18

-0.5

1.0

V_OL(DC)to V_OH(AC)for rising edge

and V_OH(DC)to V_OL(AC)for rising

edge

DMD_LS_WDATA and DMD_LS_CLK

3.0

Slew rate

V/ns

DMD_DEN_ARSTZ

DMD_LS_RDATA

V_OL(AC)to V_OH(AC)for rising edge

0.25

0.5

(1) V_OH(AC)maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(2) V_OL(AC)minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(3) See 图6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See 图6-4 for DMD_DEN_ARSTZ rise and fall times.

DMD_DEN_ARSTZ

LS_CLK, LS_WDATA

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

OH(AC)

OH(DC)

V

OL(DC)

V

OL(AC)

10

0

10

0

t_RISE

t_FALL

t_RISE

t_FALL

图6-3. LS_CLK and LS_WDATA Slew Rate

图6-4. DMD_DEN_ARSTZ Slew Rate

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6.10 System Oscillator Timing Requirements

MIN

23.998

41.663

40%

NOM

24.000

41.667

50%

MAX

24.002

41.670

UNIT

MHz

ns

f_clk

t_c

Clock frequency, MOSC (master oscillator clock)⁽¹⁾

Cycle time, MOSC (clock period)⁽¹⁾

See 图6-5

t_w(H)

Pulse duration as percent of t_c⁽²⁾, MOSC, high

50% to 50% reference

points (signal)

t_w(L)

t_t

Pulse duration as percent of t_c⁽²⁾, MOSC, low

Transition time⁽²⁾, MOSC

50% to 50% reference

points (signal)

40%

50%

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

10

ns

t_jp

Long-term, peak-to-peak, period jitter⁽²⁾, MOSC

(that is the deviation in period from ideal period due

solely to high frequency jitter)

2%

(1) The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.)

The MOSC input does not support spread spectrum clock spreading.

(2) Applies only when driven by an external digital oscillator.

t

C

t

T

t

T

t

W(L)

W(H)

80%

20%

50%

MOSC

图6-5. System Oscillators

6.11 Power Supply and Reset Timing Requirements

MIN

MAX

UNIT

µs

t_w(L)

t_r

Pulse duration, active low, RESETZ

Rise time, RESETZ⁽¹⁾

50% to 50% reference points (signal)

20% to 80% reference points (signal)

80% to 20% reference points (signal)

0.3 V to 1.045 V (VDD)

1.25

0.5

1

µs

t_f

Fall time, RESETZ⁽¹⁾

µs

t_rise

Rise time, VDD (during VDD ramp up at

turn-on)

ms

(1) For more information on RESETZ, see 节5.

DC Power Supplies

t_f

t_r

80%

50%

20%

80%

50%

20%

RESETZ

t_w(L)

Time

图6-6. Power-Up and Power-Down RESETZ Timing

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6.12 Parallel Interface Frame Timing Requirements

See for additional information

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

50% reference points

1

lines

Pulse duration –default VSYNC_WE high

Vertical back porch (VBP) –time from the active edge of

VSYNC_WE to the active edge of HSYNC_CS for the first

active line⁽¹⁾

2

1

lines

Vertical front porch (VFP) –time from the active edge of the

HSYNC_CS following the last active line in a frame to the active

edge of VSYNC_WE⁽¹⁾

t_{p_vfp}

50% reference points

Total vertical blanking –the sum of VBP and VFP (t_{p_vbp}

t_{p_vfp}

+

t_{p_tvb}

t_{p_hsw}

t_{p_hbp}

50% reference points

See ⁽¹⁾

lines

)

4

128

PCLKs

Pulse duration –default HSYNC_CS high

Horizontal back porch (HBP) –time from the active edge of

HSYNC_CS to the rising edge of DATAEN_CMD

Horizontal front porch (HFP) –time from the falling edge of

DATAEN_CMD to the active edge of HSYNC_CS

t_{p_hfp}

50% reference points

8

PCLKs

(1) The minimum total vertical blanking is defined by the following equation: t_{p_tvb}(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines

where:

•

SOURCE_ALPF = Input source active lines per frame

DMD_ALPF = Actual DMD used lines per frame supported

1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

PDATA(23/15:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

图6-7. Parallel Interface Frame Timing

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6.13 Parallel Interface General Timing Requirements

MIN

1.0

MAX

155.0

1000

UNIT

MHz

ns

PCLK frequency

PCLK period

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

50% reference points

Max ƒ_clock

6.45

PCLK jitter

see ⁽¹⁾

PCLK pulse duration high

PCLK pulse duration low

50% reference points

2.43

ns

t_{p_wl}

Setup time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

t_{p_su}

t_{p_h}

50% reference points

0.9

ns

Hold time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

2.0

ns

Transition time –all signals

t_setup, 3DR

t_hold, 3DR

This is the setup time with respect to VSYNC⁽²⁾

This is the hold time with respect VSYNC⁽³⁾

50% reference points

1.0

ms

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock–5.76 ns]. Setup and hold times must be met even with clock jitter.

(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes

(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

图6-8. Parallel Interface Pixel Timing

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6.14 BT656 Interface General Timing Requirements

The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate

ITU-R BT.656 specification for detailed interface timing requirements. ⁽²⁾

MIN

MAX

UNIT

MHz

ns

PCLK frequency

PCLK period

1.0

33.5

ƒ_cll

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

t_{p_wl}

50% reference points

Max f_clock

29.85

1000

PCLK jitter

See ⁽¹⁾

PCLK pulse duration high

PCLK pulse duration low

50% reference points

10.0

ns

Setup time –PDATA(7:0) before the active edge of

PCLK

t_{p_su}

t_{p_h}

50% reference points

3.0

0.9

ns

Hold time –PDATA(7:0) after the active edge of

PCLK

20% to 80% reference points

(rising signal)

80% to 20% reference points

(falling signal)

t_t

0.2

3.0

ns

Transition time –all signals

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock–5.76 ns]. Clock jitter must maintain setup and hold times. BT.656

data bits must be mapped to the DLPC34xx PDATA bus as shown in 图6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA

(23:0) mapping.

(2) The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK. See 图6-9.

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PDATA(7:0) of the input pixel data bus

Bus assignment mapping

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

Data bit mapping on controller pin

n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a

图6-9. BT.656 Interface Mode Bit Mapping

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6.15 Flash Interface Timing Requirements

The DLPC3478 flash memory interface consists of a SPI flash serial interface. The DLPC3478 can support 1- to 128-Mb

flash memories.^{(2) (3) (4)}

MIN

MAX

36.0

704

UNIT

MHz

ns

f_clock

SPI_CLK frequency

See ⁽¹⁾

1.4

t_{p_clkper}

t_{p_wh}

t_{p_wl}

SPI_CLK period

50% reference points

27.8

352

SPI_CLK pulse duration high

SPI_CLK pulse duration low

ns

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

3.0

ns

Transition time –all signals

Setup time –SPI_DIN valid before SPI_CLK falling

edge

t_{p_su}

t_{p_h}

50% reference points

10.0

0.0

ns

Hold time –SPI_DIN valid after SPI_CLK falling edge

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

t_{p_clqv}

1.0

3.0

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

t_{p_clqx}

50% reference points

ns

–3.0

(1) This range include the ±200 ppm of the external oscillator (but no jitter).

(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3478 does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. DLPC3478 hold capture timing has been set to facilitate reliable operation with standard external

SPI protocol devices.

(3) With the above output timing, DLPC3478 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the

rising edge of SPI_CLK.

(4) For additional requirements of the external flash device view the 节7.3.4 section.

t_CLKPER

SPI_CLK

(Controller output)

t_WL

t_WH

t_{P_SU}

t_{P_H}

SPI_DIN

(Controller input)

t_{P_CLQV}

SPI_DOUT, SPI_CS(1:0)

(Controller output)

t_{P_CLQX}

图6-10. Flash Interface Timing

6.16 Other Timing Requirements

MIN

MAX

10

UNIT

ns

t_rise, all^{(1) (2)}

20% to 80% reference points

80% to 20% reference points

20% to 80% reference points

80% to 20% reference points

t_fall, all^{(1) (2)}

10

ns

t_rise, PARKZ⁽²⁾

150

ns

t_fall, PARKZ⁽²⁾

ns

t_w, GPIO_08 (normal park) pulse width⁽³⁾

I²C baud rate

200

ms

kHz

100

(1) Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.

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(2) This is the recommended signal transition time to avoid input buffer oscillations.

(3) The pulse width encompasses the minimum high time and the minimum low time for this signal.

6.17 DMD Sub-LVDS Interface Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

45%

MIN

TYP

MAX

UNIT

(1)

t_R

t_F

Differential output rise time

Differential output fall time

DMD HS Clock switching rate

DMD HS Clock frequency

DMD HS Clock output duty cycle

250

ps

t_switch

f_clock

1200

600

Mbps

MHz

DCout

50%

55%

(1) Rise and fall times are defined for the differential V_ODsignal as shown in 图6-2.

6.18 DMD Parking Switching Characteristics

See ⁽²⁾

PARAMETER

Normal Park time⁽¹⁾

Fast park time⁽³⁾

TEST CONDITIONS

TYP

MAX

20

UNIT

ms

t_park

t_{fast park}

32

µs

(1) Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the

normal park request (GPIO_08 goes low).

(2) The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be

held on for a time after parking is completed to satisfy DMD requirements. See 节9.2 and the appropriate DMD or PMIC datasheet for

more information.

(3) Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast

park request (PARKZ goes low).

6.19 Chipset Component Usage Specification

The DLPC1438 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires

that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.

表6-1. DLPC1438 Supported DMDs and PMICs

DLPC1438 DLP Chipset

DLP300S

DMD

DLP301S

DLPA2000

DLPA2005

PMIC

DLPA3000

DLPA3005

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7 Detailed Description

7.1 Overview

The DLPC1438 controller is part of the chipset that includes the DLP300S or DLP301S DMD, and the DLPA200x

or DLPA300x PMIC/LED driver. To ensure reliable operation of the DLP chipset, the DLPC1438 must always be

used with the supported devices shown in 表6-1.

7.2 Functional Block Diagram

Test

Pattern

Generator

Video Processing

/5

Parallel Video

or BT656 Port

ñ

Brightness Enhancement

Chroma Interpolation

Color Space Conversion

Color Correction

ñ

Contrast Adjustment

Dynamic Scaling

Gamma Correction

/24

Input

Control

Processing

Image Format Processing

Power Saving Operations

Splash

Screen

CAIC Processing

DLP Subsystem

Display Formatting

eDRAM (Frame Memory)

Arm^®Cortex^®-M3

Processor

128 KB I/D Memory

JTAG

I2C_0

/

Real Time

Control System

SPI_0

DMD_HS_CLK

(sub-LVDS)

DMD_HS_DATA(A:H)

/

(sub-LVDS)

DMD Interface

DMD_LS_CLK

SPI_1

I2C_1

LED Control

Other options

Clocks and Reset

Generation

DMD_LS_WDATA

DMD_LS_RDATA

/20

GPIO

DMD_DEN_ARSTZ

Clock (Crystal)

Reset Control

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7.3 Feature Description

7.3.1 Input Source

7.3.1.1 Supported Resolution and Frame Rates

表7-1. Supported Input Source Ranges^{(1) (2) (3)}

SOURCE RESOLUTION RANGE⁽⁵⁾

HORIZONTAL VERTICAL

Landscape Portrait Landscape Portrait

1280 720 720 1280

FRAME RATE

RANGE

INTERFACE

Bits / Pixel ⁽⁴⁾

Parallel

8

60 ±2 Hz

(1) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line

rate.

(2) The maximum DMD size for all rows in the table is 1280 × 720.

(3) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to

determine the latest available frame rate and input resolution support for a given firmware image.

(4) Bits per pixel does not necessarily equal the number of data pins used on the DLPC1438 controller.

(5) By using an I2C command, portrait image inputs can be rotated on the DMD by minus 90 degrees so that the image is displayed in

landscape format.

7.3.1.2 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes the signals listed in 表

7-2.

表7-2. Parallel Interface Signals

SIGNAL

DESCRIPTION

VSYNC_WE

HSYNC_CS

vertical sync

horizontal sync

data valid

DATAEN_CMD

PDATA

8-bit data bus

pixel clock

PCLK

PDM_CVS_TE

parallel data mask (optional)

Note

VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no

longer active, the display sequencer stops and causes the LEDs to turn off.

The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section

shows the relationship of these signals.

An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without

losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source

image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or

active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic

low signal. PDM_CVS_TE must only change during vertical blanking.

The parallel interface supports a single 8-bit data format with bitweights as defined in 表5-2.

7.3.2 External Print

External Print is one of the key capabilities of the DLPC1438 controller. When the DLPC1438 controller is

configured for external print, most video processing functions are bypassed to allow for accurate pattern display.

In external print mode, frame data is sent to the DLPC1438 controller over parallel interface. Commands to the

DLPC1438 controller execute a printed layer with a programmable number of frames to expose before disabling

illumination to prepare for the next print layer.

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The DLPC1438 controller has two trigger out signals to synchronize printing operation with a host processor.

表7-3. External Print Signals

SIGNAL NAME

DESCRIPTION

SYS_RDY (GPIO_06)

System Ready: After switching to External Print Mode, some setup time is required. Once setup is

complete and the controller is ready to accept a print layer command, SYS_RDY goes high.

Active during printing of each layer. When PRINT_ACTIVE is low, illumination is turned off and it is safe

to perform mechanical motion to prepare for the next layer print.

PRINT_ACTIVE (GPIO_09)

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7.3.3 Device Startup

• The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.

• While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).

• HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is

pulled high, this indicates that the controller is performing boot-up and auto-initialization.

• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to

indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the

external signal).

• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the

falling edge of the signal, the initialization is complete.

• The DLPC1438 controller is ready to receive commands through I²C or accept video over the video interface

only after auto-initialization is complete.

• The controller initialization typically completes (HOST_IRQ goes low) within 500 ms of RESETZ being

asserted. However, this time may vary depending on the software version and the contents of the user

configurable auto initialization file.

RESETZ

auto-initialization

HOST_IRQ

(with external pullup)

(INIT_BUSY)

t0

t1

t0: rising edge of RESETZ; auto-initialization begins

t1: falling edge of HOST_IRQ; auto-initialization is complete

图7-1. HOST_IRQ Timing

7.3.4 SPI Flash

7.3.4.1 SPI Flash Interface

The DLPC1438 controller requires an external SPI serial flash memory device to store the firmware. Follow the

below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing

Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC1438 Validated SPI Flash

Device Options table for example compatible flash options. The minimum required flash size depends on the

size of the utilized firmware. The firmware size depends upon a variety of factors including the number of

sequences, lookup tables, and splash images.

The DLPC1438 controller uses a single SPI interface that complies to industry standard SPI flash protocol. The

device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.

The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash

device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip

select zero. The boot routine uploads program code from flash memory to program memory then transfers

control to an auto-initialization routine within program memory.

The DLPC1438 is designed to support any flash device that is compatible with the modes of operation, features,

and performance as defined in the Additional DLPC1438 SPI Flash Requirements table below 表 7-4, 表 7-5,

and 表7-6.

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表7-4. Additional DLPC1438 SPI Flash Requirements

FEATURE

DLPC1438 REQUIREMENT

SPI interface width

SPI polarity and phase settings

Fast READ addressing

Programming mode

Page size

Single

SPI mode 0

Auto-incrementing

Page mode

256 B

Sector size

4-KB sector

Any

Block size

Block protection bits

Status register bit(0)

Status register bit(1)

Status register bits(6:2)

Status register bit(7)

0 = Disabled

Write in progress (WIP), also called flash busy

Write enable latch (WEN)

A value of 0 disables programming protection

Status register write protect (SRWP)

Because the DLPC1438 controller supports only single-byte status register R/W command

execution, it may not be compatible with flash devices that contain an expansion status byte.

However, as long as the expansion status byte is considered optional in the byte 3 position and any

write protection control in this expansion status byte defaults to unprotected, then the flash device is

likely compatible with the DLPC1438.

Status register bits(15:8)

(that is expansion status byte)

The DLPC1438 controller is intended to support flash devices with program protection defaults of either enabled

or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as

part of the boot process.

The DLPC1438 issues these commands during the boot process:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8

bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC1438 controller issues similar commands:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

表 7-5 and 表 7-6 below list the specific instruction OpCode and timing compatibility requirements. The

DLPC1438 controller does not adapt protocol or clock rate based on the flash type connected.

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表7-5. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

BYTE 1

SPI FLASH COMMAND

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

(OPCODE)

Fast READ (1 output)

Read status

0x0B

0x05

0x01

0x06

0x02

0x20

0xC7

ADDRS(0)

N/A

ADDRS(1)

N/A

ADDRS(2)

STATUS(0)

dummy

DATA(0)⁽¹⁾

Write status

STATUS(0)

See ⁽²⁾

Write enable

Page program

Sector erase (4 KB)

Chip erase

ADDRS(0)

ADDRS(1)

ADDRS(2)

DATA(0)⁽¹⁾

(1) Shows the first data byte only. Data continues.

(2) Access to a second (expansion) write status byte not supported by the DLPC1438 controller.

表 7-6 below and the Flash Interface Timing Requirements section list the specific timing compatibility

requirements for a DLPC1438 compatible flash device.

表7-6. SPI Flash Key Timing Parameter Compatibility Requirements

SPI FLASH TIMING PARAMETER^{(1) (2)}

SYMBOL

ALTERNATE SYMBOL

MIN

MAX

UNIT

Access frequency (all commands)

FR

f_C

MHz

≤1.4

≥30.1

Chip select high time (also called chip select

deselect time)

t_SHSL

t_CSH

ns

≤200

≥0

Output hold time

t_CLQX

t_CLQV

t_DVCH

t_CHDX

t_HO

t_V

t_DSU

t_DH

ns

Clock low to output valid time

Data in set-up time

Data in hold time

≤11

≤5

(1) The timing values apply to the specification of the peripheral flash device, not the DLPC1438 controller. For example, the flash device

minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.

(2) The DLPC1438 does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to

a logic high on the PCB through an external pullup.

In order for the DLPC1438 controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin

must be supplied with the corresponding voltage. The DLPC1438 Validated SPI Flash Device Options table

contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC1438

controller.

表7-7. DLPC1438 Validated SPI Flash Device Options^{(1) (2) (3)}

DENSITY (Mb)

VENDOR

PART NUMBER

1.8-V COMPATIBLE DEVICES

W25Q40BWUXIG

PACKAGE SIZE

4 Mb

8 Mb

Winbond

Macronix

2 × 3 mm USON

MX25U4033EBAI-12G

1.43 × 1.94 mm WLCSP

1.68 × 1.99 mm WLCSP

MX25U8033EBAI-12G

2.5- OR 3.3-V COMPATIBLE DEVICES

Winbond W25Q16CLZPIG

16 Mb

5 × 6 mm WSON

(1) The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC1438 controller. Make sure to order the device that

supports the correct supply voltage as multiple voltage options are often available.

(2) Numonyx (Micron) serial flash devices typically do not support the 4 KB sector size compatibility requirement for the DLPC1438

controller.

(3) The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC1438

controller, but they have not been formally validated by TI.

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7.3.4.2 SPI Flash Programming

The SPI pins of the flash can directly be driven for flash programming while the DLPC1438 controller I/Os are tri-

stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state

while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.

Alternatively, the DLPC1438 controller can program the SPI flash itself when commanded via I²C if a valid

firmware image has already been loaded and the controller is operational.

7.3.5 I²C Interface

Both of the DLPC1438 I²C interface ports support a 100-kHz baud rate. Because I²C interface transactions

operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices

in the system.

7.3.6 Test Point Support

The DLPC1438 test point output port, TSTPT_(7:0), provides selected system calibration and controller debug

support. These test points are inputs when reset is applied. These test points are outputs when reset is released.

The controller samples the signal state upon the release of system reset and then uses the captured value to

configure the test mode until the next time reset is applied. Because each test point includes an internal

pulldown resistor, external pullups must be used to modify the default test configuration.

The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce

switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is

recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for

a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially

adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points

are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is

released does not have any effect until the next time reset asserts and releases. 表 7-8 describes the test mode

selections for one programmable scenario defined by TSTPT_(2:0).

表7-8. Test Mode Selection Scenario Defined by TSTPT_(2:0)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT OUTPUT VALUE⁽¹⁾

TSTPT_(2:0) = 0b000

TSTPT_(2:0) = 0b010

60 MHz

TSTPT_0

TSTPT_1

TSTPT_2

TSTPT_3

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

HI-Z

30 MHz

0.7 to 22.5 MHz

HIGH

LOW

HIGH

7.5 MHz

(1) These are default output selections. Software can reprogram the selection at any time.

7.3.7 DMD Interface

The DLPC1438 controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface

and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.

7.3.7.1 Sub-LVDS (HS) Interface

The DLP300S/DLP301S DMD does not require all of the available output data lanes of the controller. Internal

software selection allows the controller to support multiple DMD interface swap configurations. These options

can improve board layout by remapping specific combinations of DMD interface lines to other DMD interface

lines as needed. 表 7-9 shows the two options available for the DLP300S/DLP301S DMD. Leave any unused

DMD signal pairs unconnected on the final board design.

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表7-9. DLP300S/DLP301S DMD –ASIC to 8-Lane DMD Pin Mapping Options

DLPC1438 CONTROLLER 8 LANE DMD ROUTING OPTIONS

DMD PINS

OPTION 1 OPTION 2

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_E_P

HS_WDATA_E_N

Input DATA_p_0

Input DATA_n_0

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_F_P

HS_WDATA_F_N

Input DATA_p_1

Input DATA_n_1

HS_WDATA_B_P

HS_WDATA_B_N

HS_WDATA_G_P

HS_WDATA_G_N

Input DATA_p_2

Input DATA_n_2

HS_WDATA_A_P

HS_WDATA_A_N

HS_WDATA_H_P

HS_WDATA_H_N

Input DATA_p_3

Input DATA_n_3

HS_WDATA_H_P

HS_WDATA_H_N

HS_WDATA_A_P

HS_WDATA_A_N

Input DATA_p_4

Input DATA_n_4

HS_WDATA_G_P

HS_WDATA_G_N

HS_WDATA_B_P

HS_WDATA_B_N

Input DATA_p_5

Input DATA_n_5

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_C_P

HS_WDATA_C_N

Input DATA_p_6

Input DATA_n_6

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_D_P

HS_WDATA_D_N

Input DATA_p_7

Input DATA_n_7

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DLPC1438

High Speed sub-LVDS DDR Interface

DMD_HS_WDATA_A_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

(Example DMD)

Sub-LVDS-DMD

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

DMD_LS_CLK

DMD_LS_WDATA

DMD_DEN_ARSTZ

DMD_LS_RDATA

Low Speed SDR Interface (120 MHz)

图7-2. DLP300S/DLP301S DMD Interface Example

The sub-LVDS high-speed interface waveform quality and timing on the DLPC1438 controller depends on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and

Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both

waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).

Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements.

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7.4 Device Functional Modes

The DLPC1438 controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON

(GPIO_08).

• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the

DMD.

• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.

7.5 Programming

The DLPC1438 controller contains an Arm^®Cortex^®-M3 processor with additional functional blocks to enable

video processing and control. TI provides software as a firmware image. The customer is required to flash this

firmware image onto the SPI flash memory. The DLPC1438 controller loads this firmware during startup and

regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.

The available controller functions depend on the firmware version installed. Different firmware is required for

different chipset combinations (such as when using different PMIC devices). See Documentation Support at the

end of this document or contact TI to view or download the latest published software.

Users can modify software behavior through I²C interface commands. For a list of commands, view the software

user's guide accessible through the Documentation Support page.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The DLPC1438 3D Print controller with DLP300S or DLP301S DMD enables high resolution fast 3D printer

products. This section describes typical 3D printer DLP systems with and without actuation. The DMDs are

spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the

primary direction being into projection or collection optics. The optical architecture of the system and the format

of the image digital data coming into the DLPC1438 are what primarily determine the application requirements.

Typical applications include:

• DLP 3D printer

– Additive manufacturing

– Vat polymerization

– Masked stereolithography (mSLA 3D printer)

• Light exposure: programmable spatial and temporal light exposure

8.2 Typical Application

8.2.1 Pattern projector for 3D printer without actuation and without FPGA

DLPC1438 controller with DLP300S/DLP301S DMD enables high accuracy and low cost 3D printer products. 图

8-1 shows a typical 3D printer system block diagram using external print mode.

1.1 V

1.1 Reg

L3

SYSPWR

L2

DC

Supplies

1.8 V

1.8 V external

L1

DLPA200x

VSPI

V

LED

1.8 V

PROJ_ON

LED_SEL (2)

PROJ_ON

SPI (4)

INTZ

GPIO_8

SPI1

RESETZ

PARKZ

2

I

C

R

LIM

Thermistor

HOST_IRQ

Parallel (12)

CMP_OUT

Front End

Processor

VDDLP12

VDD

1.1 V

Illumination

optics

DLPC1438

RC_

CHARGE

SPI0

GPIO_10

V

, V ,

BIAS OFFSET

VCC_18

1.8 V

V

RESET

DMD

VCC_INTF

VCC_FLSH

CTRL

Sub-LVDS DATA

1.8 V

SPI (4)

Flash

TI DLP Chipset

Non-TI Device

图8-1. System without FPGA and without actuator

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8.2.1.1 Design Requirements

A DLP 3D printer can be created using the DLP300S/DLP301S, DLPC1438, and DLPA200x PMIC/LED driver. In

addition to the DLP chipset, other IC components may be needed including a flash device to store the software

and firmware to control the DLPC1438.

A 405nm LED typically supplies the illumination for the DMD. In addition to LEDs, other light sources are

supported.

For connecting the DLPC1438 controller to the host processing for receiving patterns or video data, the parallel

interface is used. Connect an I²C interface to the host processor to send commands to the DLPC1438 controller.

8.2.1.2 Detailed Design Procedure

For connecting the DLP300S/DLP301S DMD, the DLPC1438 controller and the DLPA200x or DLPA300x

PMIC/LED driver see the reference design schematic. Follow the layout guidelines shown in 节 10 to achieve

reliable DLP system results.

8.2.1.3 Application Curve

As the LED currents that are driven through LED_0, LED_1 or LED_2 LEDs are increased, the brightness of the

projector increases. This increase is somewhat non-linear, and the curve for typical white screen lumens

changes with LED currents is shown in 图 8-2. For the LED currents shown, it is assumed that the same current

amplitude is applied to the LED_0, LED_1 or LED_2 LEDs.

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

100

200

300 400

Current (mA)

500

600

700

D001

图8-2. Luminance vs Current

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8.2.2 Pattern projector for 3D printer with actuator

DLPC1438 controller with DLP300S/DLP301S DMD enables high accuracy and low cost 3D printer products. 图

8-3 shows a typical 3D printer system block diagram using external print mode.

1.1 V

1.1 Reg

L3

SYSPWR

L2

DC

Supplies

1.8 V

1.8 V external

L1

DLPA200x

VSPI

V

LED

1.8 V

PROJ_ON

LED_SEL (2)

PROJ_ON

SPI (4)

INTZ

GPIO_8

SPI1

RESETZ

PARKZ

2

I

C

R

LIM

Thermistor

HOST_IRQ

CMP_OUT

2

I C

Front End

Processor

VDDLP12

VDD

DLPC1438

SPI_RDY

SPI (4)

Parallel (12)

1.1 V

Illumination

optics

FPGA

FPGA_READY

ACT_SYNC

RC_

CHARGE

SPI0

GPIO_10

V

, V ,

BIAS OFFSET

Flash

VCC_18

1.8 V

V

RESET

VCC_INTF

VCC_FLSH

DMD

CTRL

Sub-LVDS DATA

Frame

Memory

1.8 V

SPI (4)

Flash

TI DLP Chipset

Non-TI Device

Actuator

Driver

Actuator

图8-3. Internal Pattern Streaming Mode

8.2.2.1 Design Requirements

When higher resolution is required, a front-end FPGA design is provided which provides actuator control and

synchronization, as well as providing a data bridge between an SPI output of a host processor and the parallel

interface of the DLPC1438. This FPGA combined with the DLP300S/DLP301S, DLPC1438, and DLPA200x

PMIC/LED driver complete the control electronics for the optical module of a 3D printer. In addition to the DLP

chipset, other IC components may be needed including a flash device to store the software and firmware to

control the DLPC1438.

A 405nm LED typically supplies the illumination for the DMD. In addition to LEDs, other light sources are

supported.

For connecting the DLPC1438 controller to the host processing for receiving patterns or video data, the parallel

interface is used. Connect an I²C interface to the host processor to send commands to the DLPC1438 controller.

8.2.2.2 Detailed Design Procedure

For connecting the DLP300S/DLP301S DMD, the DLPC1438 controller and the DLPA200x or DLPA300x

PMIC/LED driver see the reference design schematic. Follow the layout guidelines shown in 节 10 to achieve

reliable DLP system results.

8.2.2.3 Application Curve

See the 节8.2.1.3 as the brightness considerations are similar in systems with and without an FPGA.

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9 Power Supply Recommendations

9.1 PLL Design Considerations

It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.

However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC1438 requires an array of power supply voltages, (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), because VDDLP12 is tied to the 1.1-V VDD supply, then there

are no restrictions regarding the relative order of power supply sequencing to avoid damaging the controller

(This is true for both power-up and power-down scenarios). Similarly, there is no minimum time between

powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.

Although there is no risk of damaging the controller if the above power sequencing rules are followed, the

following additional power sequencing recommendations must be considered to ensure proper system

operation.

• To ensure that DLPC1438 output signal states behave as expected, all controller I/O supplies should remain

applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is

applied, then the output signal state associated with the inactive I/O supply goes to a high impedance state.

• Additional power sequencing rules may exist for devices that share the supplies with the controller, and thus

these devices may force additional system power sequencing requirements.

Note that when V_DDcore power is applied, but I/O power is not applied, additional leakage current may be

drawn. This added leakage does not affect normal controller operation or reliability.

图 9-1, 图 9-2 and 图 9-3 show the controller power-up and power-down sequence for both the normal PARK

and fast PARK operations of the DLPC1438 controller.

Note

During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms

after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely

power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended

that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least

50 ms after PROJ_ON goes low.

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Signals

from PMIC (DLPA3000)

from other source

Pre-Initialization

Initialization

Regular operation

PWR On

PWR Off

VIN On

Chipset State

SYSPWR

PROJ_ON

VDD (1.1V)

VCC18 (1.8V)

VCC_INTF (1.8V)

VCC_FLSH (1.8V)

PARKZ

FPGA PWR

(a)

PLL_REFC

LK

RESETZ

FPGA_RDY

(b)

(c)

HOST_IRQ

I2C

(d)

t1

t2

t3

t4

t1:

t2:

SYSPWR (VIN) applied to the PMIC. All other voltage rails are derived from SYSPWR.

All DLPC1438 supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a

different external supply.

t3:

Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.

HOST_IRQ goes low to indicate initialization is complete. I²C is now ready to accept commands.

t4:

(a):

The typical delay between the PLL reference clock becoming active and RESETZ being deasserted (going high) is less than 1

ms. PLL_REFCLK must be stable within 5 ms of all power being applied, and may be active before power is applied.

(b):

(c):

(d):

There is a typical controller boot time of 100 ms. PARKZ must be high before RESETZ releases to support auto-initialization.

RESETZ must also be held low for at least 5 ms after DLPC1438 power supplies are in specification.

There is a typical FPGA setup time of 2.75 ms before the system completes boot process. During this period, the DLPC1438

controller writes startup values to the FPGA registers.

After FPGA setup is complete, I²C now accepts commands.

图9-1. DLPC1438 Power-Up Timing

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Signals

from PMIC (DLPA3000)

from other source

Normal

Park

System State

Regular operation

Power supply shutdown

(b)

SYSPWR

(c)

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

VDDLP12

(if not tied to VDD)

FPGA PWR

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

HOST_IRQ

RESETZ

(a)

I²C (activity)

t1

t2

t3

t4

t5

t1:

t2:

t3:

(a):

PROJ_ON goes low to begin the power down sequence.

The controller finishes parking the DMD.

Controller power supplies are turned off.

The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and

VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is

deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore

recommended to follow note (c).

(b):

(c):

DMD reset voltage regulation stops typically after 12 ms of normal DMD park being completed.

It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the

DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.

图9-2. DLPC1438 Normal Power-Down

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Signals

from PMIC (DLPA3000)

from other source

Fast

Park

(a)

System State

Regular operation

Power supplies collapse

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

VDDLP12

(if not tied to VDD)

FPGA PWR

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

(b)

PARKZ

PLL_REFCLK

HOST_IRQ

RESETZ

I²C (activity)

t1

t3

t4

t2

t1:

t2:

t3:

t4:

A fault is detected and PARKZ is asserted (goes low) to tell the controller to initiate a fast park of the DMD.

The controller finishes the fast park procedure.

Eventually all power supplies that were derived from SYSPWR collapse.

System is completely turned off.

图9-3. DLPC1438 Fast Power-Down

9.3 Power-Up Initialization Sequence

An external power monitor is required to hold the DLPC1438 controller in system reset during the power-up

sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller

voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The

external power monitoring is automatically done by the DLPAxxxx PMIC.

No signals output by the DLPC1438 controller will be in their active state while RESETZ is asserted. The

following signals are tri-stated while RESETZ is asserted:

• SPI0_CLK

• SPI0_DOUT

• SPI0_CSZ0

• SPI0_CSZ1

• GPIO [19:00]

Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be

configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the

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PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.

Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after

RESETZ is set high.

The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power

is applied:

• LED_SEL_0

• LED_SEL_1

• DMD_DEN_ARSTZ

After power is stable and the PLL_REFCLK_I clock input to the DLPC1438 controller is stable, then RESETZ

should be deactivated (set to a logic high). The DLPC1438 controller then performs a power-up initialization

routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of

RESETZ, all DLPC1438 I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ

signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup

resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively

drives it high. Upon completion of the auto-initialization routine, the DLPC1438 controller will drive HOST_IRQ

low to indicate the initialization done state of the controller has been reached.

To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be

deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine

must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting

PROJ_ON).

Note

No I²C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.

9.4 DMD Fast Park Control (PARKZ)

PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages

drop below specifications. Typically, the PARKZ signal is provided by the DLPAxxxx interrupt output signal.

PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on

the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park

operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue

running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to

allow the park operation to complete.

Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host

processor (for example, when the external power source has been disconnected or the battery has dropped

below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The

longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically

only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park

operation takes much longer than 32 µs to park the mirrors. During a Normal Park operation, the DLPAxxxx

keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.

Additionally, the DLPAxxxx may hold the supplies on for a period of time after the parking has been completed.

View the relevant DLPAxxxx datasheet for more information. The longer mirror parking time ensures the longest

DMD lifetime and reliability. The DMD Parking Switching Characteristics section specifies the park timings.

9.5 Hot Plug I/O Usage

The DLPC1438 controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).

This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the

controller does not load the input signal nor draw excessive current that could degrade controller reliability. For

example, the I²C bus from the host to other components is not affected by powering off VCC_INTF to the

DLPC1438 controller. The allows additional devices on the I²C bus to be utilized even if the controller is not

powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back

to the host.

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If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input

buffer may experience added leakage current; however, the added leakage current does not damage the

DLPC1438 controller.

However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which

prevents communication on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin

for any system that has additional secondary devices on this bus.

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10 Layout

10.1 Layout Guidelines

For a summary of the PCB design requirements for the DLPC1438 controller see PCB Design Requirements for

TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the

use of 1-oz (or greater) copper planes to manage the controller package heat.

10.1.1 PLL Power Layout

Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The

DLPC1438 controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,

VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground

pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the

spectrum of noise absorption). It is recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all

four components as close to the controller as possible. It is especially important to keep the leads of the high

frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and

VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.

Select ferrite beads with these characteristics:

• DC resistance less than 0.40 Ω

• Impedance at 10 MHz equal to or greater than 180 Ω

• Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC1438 controller to both

capacitors and then through the series ferrites to the power source. Make the power and ground traces as short

as possible, parallel to each other, and as close as possible to each other.

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signal via

via to common analog digital board power plane

via to common analog digital board ground plane

PCB pad

Controller pad

1

2

3

4

5

A

Signal

VSS

Signal

F

VSS_

PLLM

G

Signal

VSS

Signal

Local

decoupling

for the PLL

digital

GND

FB

supply

PLL_

REF

CLK_I

VDD_

PLLM

VSS_

PLLD

H

1.1-V

Power

PLL_

REF

CLK_O

Crystal

Circuit

VDD_

PLLD

J

VSS

VDD

图10-1. PLL Filter Layout

10.1.2 Reference Clock Layout

The DLPC1438 controller requires an external reference clock to feed the internal PLL. Use either a crystal or

oscillator to supply this reference. The DLPC1438 reference clock must not exceed a frequency variation of ±200

ppm (including aging, temperature, and trim component variation).

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图10-2 shows the required discrete components when using a crystal.

PLL_REFCLK_I

PLL_REFCLK_O

R_FB

R_S

Crystal

C_L1

C_L2

C_L= Crystal load capacitance (farads)

C_L1= 2 × (C_L–Cstray_pll_refclk_i)

C_L2= 2 × (C_L–Cstray_pll_refclk_o)

where:

•

Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.

Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.

图10-2. Required Discrete Components

10.1.2.1 Recommended Crystal Oscillator Configuration

表10-1. Crystal Port Characteristics

PARAMETER

NOM

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

1.5

pF

表10-2. Recommended Crystal Configuration

PARAMETER ^{(1) (2)}

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

24

Crystal nominal frequency

MHz

PPM

ms

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

Crystal load

120 (max)

Ω

6

pF

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

100

1

Ω

MΩ

pF

See equation in 图10-2 notes

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) Temperature range of –30°C to 85°C.

(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC1438

controller, and the PLL_REFCLK_O pin must be left unconnected.

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表10-3. Recommended Crystal Parts

TEMPERATURE

LOAD

CAPACITANCE

(pF)

PACKAGE

DIMENSIONS

(mm)

MAXIMUM

MANUFACTURER

SPEED

(MHz)

PART NUMBER

AND AGING

(ppm)

(1) (2)

ESR (Ω)

KDS

DSX211G-24.000M-8pF-50-50

XRCGB24M000F0L11R0

24

±50

120

8

6

2.0 × 1.6

Murata

±100

NX2016SA 24M

NDK

24

±145

120

6

2.0 × 1.6

EXS00A-CS05733

(1) The crystal devices in this table have been validated to work with the DLPC1438 controller. Other devices may also be compatible but

have not necessarily been validated by TI.

(2) Operating temperature range: –30°C to 85°C for all crystals.

10.1.3 Unused Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused

controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For

controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown

unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be

expected to drive an external device. The DLPC1438 controller implements very few internal resistors and are

listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown

resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8

kΩ.

Never tie unused output-only pins directly to power or ground. Leave them open.

When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that

the pin can remain open. If this control is not available and the pins may become an input, then include an

appropriate pullup (or pulldown) resistor.

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10.1.4 DMD Control and Sub-LVDS Signals

表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations

SIGNAL INTERCONNECT TOPOLOGY

DMD BUS SIGNAL^{(1) (2)}

UNIT

SINGLE-BOARD SIGNAL

MULTI-BOARD SIGNAL

ROUTING LENGTH

DMD_HS_CLK_P

6.0

in

See ⁽³⁾

DMD_HS_CLK_N

(152.4)

(mm)

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

6.0

in

See ⁽³⁾

(152.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

6.5

in

DMD_LS_CLK

See ⁽³⁾

(165.1)

(mm)

6.5

in

DMD_LS_WDATA

DMD_LS_RDATA

(165.1)

(mm)

6.5

in

(165.1)

(mm)

7.0

in

DMD_DEN_ARSTZ

(177.8)

(mm)

(1) Maximum signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS

model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.

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INTERFACE

表10-5. High Speed PCB Signal Routing Matching Requirements

SIGNAL GROUP LENGTH MATCHING^{(1) (2) (3)}

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH⁽⁴⁾

UNIT

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_CLK_P

DMD_HS_CLK_N

±1.0

in

DMD⁽⁵⁾

(±25.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

±0.025

in

DMD

DMD_HS_WDATA_x_P

DMD_HS_CLK_P

DMD_HS_WDATA_x_N

DMD_HS_CLK_N

DMD_LS_CLK

N/A

(±0.635)

(mm)

±0.025

in

(±0.635)

(mm)

DMD_LS_WDATA

DMD_LS_RDATA

±0.2

in

(±5.08)

(mm)

in

DMD_DEN_ARSTZ

N/A

(mm)

(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC1438

controller or the DMD require no additional consideration.

(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data

lines.

(3) DMD LS signals are single ended.

(4) Mismatch variance for a signal group is always with respect to the reference signal.

(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.

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表10-6. Signal Requirements

PARAMETER

REFERENCE

REQUIREMENT

DMD_LS_WDATA

Required

DMD_LS_CLK

Required

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Acceptable

Source series termination

Required

Not acceptable

68 Ω±10%

100 Ω±10%

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Endpoint termination

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

PCB impedance

SDR (single data rate) referenced to DMD_LS_DCLK

SDR referenced to DMD_LS_DCLK

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

SDR

Signal type

SDR referenced to DMD_LS_DLCK

sub-LVDS

10.1.5 Layer Changes

• Single-ended signals: Minimize the number of layer changes.

• Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the

signals of a given pair do not change layers.

10.1.6 Stubs

• Avoid using stubs.

10.1.7 Terminations

• DMD_HS differential signals require no external termination resistors.

• Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ωseries termination resistor

located as close as possible to the corresponding controller pins.

• Make sure the DMD_LS_RDATA signal path includes a 43-Ωseries termination resistor located as close as

possible to the corresponding DMD pin.

• The DMD_DEN_ARSTZ pin requires no series resistor.

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10.1.8 Routing Vias

• The number of vias on DMD_HS signals must be minimized and ideally not exceed two.

• Any and all vias on DMD_HS signals must be located as close to the controller as possible.

• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not

exceed two.

• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the

controller as possible.

10.1.9 Thermal Considerations

The underlying thermal limitation for the DLPC1438 controller is that the maximum operating junction

temperature (T_J) not be exceeded (this is defined in the Recommended Operating Conditions section).

Some factors that influence T_Jare as follows:

• operating ambient temperature

• airflow

• PCB design (including the component layout density and the amount of copper used)

• power dissipation of the DLPC1438 controller

• power dissipation of surrounding components

The controller package is designed to primarily extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

The recommends maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC1438 controller power dissipation and R_θJAat 0 m/s of forced airflow, where R_θJAis

the thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz

power planes. This JEDEC test PCB is not necessarily representative of the DLPC1438 controller PCB, so the

reported thermal resistance may not be accurate in the actual product application. Although the actual thermal

resistance may be different, it is the best information available during the design phase to estimate thermal

performance. TI highly recommended that thermal performance be measured and validated after the PCB is

designed and the application is built.

To evaluate the thermal performance, measure the top center case temperature under the worse case product

scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the

controller does not exceed the maximum recommended case temperature (T_C). This specification is based on

the measured φ_JTfor the DLPC1438 controller package and provides a relatively accurate correlation to

junction temperature.

Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI

recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that

they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally

conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead

through the wires.

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10.2 Layout Example

图10-3. Layout Recommendation

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

11.1.2.1 Device Markings

1

2

DLPC1438

SC

DLPC1438XXX

XXXXXXXXXX-TT

YMZLLLS

3

4

5

TW YYWW

Terminal A1 corner identifier

Marking Definitions:

Line 1:

DLP^®Device Name: DLPC1438 device name ID.

SC: Solder ball composition

e1: Indicates lead-free solder balls consisting of SnAgCu

G8: G indicates mold compound green; 8 indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with

silver content less than or equal to 1.5% and that the mold compound meets TI's definition of green.

Line 2:

TI Part Number

DLP^®Device Name: DLPC1438 = x indicates 8 device name ID.

XXX corresponds to the device package designator.

Line 3:

Line 4:

XXXXXXXXXX-TT Manufacturer part number

Foundry lot code for semiconductor wafers and lead-free solder ball marking

YM: Year month date code

Z: Site code

LLL: Assembly lot code

S: Site code

May also be in the format LLLLLL.ZZZ

LLLLLL: Fab lot number

ZZZ: Lot split number

Line 5:

PH YYWW: Package assembly information

PH: Manufacturing site

YYWW: Date code (YY = Year :: WW = Week)

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Note

1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For

example, 2512737-0001X.

11.2 Documentation Support

11.2.1 Related Documentation

The following table lists quick access links for associated parts of the DLP chipset.

表11-1. Chipset Documentation

TECHNICAL

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TOOLS & SOFTWARE

DOCUMENTS

Click here

DLPA2000

DLPA2005

DLPA3000

DLPA3005

DLP300S

DLP301S

Click here

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®are registered trademarks of Texas Instruments.

Arm^®and Cortex^®are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

For the device mechanical, packaging, and orderable information, refer to the Mechanical, Packaging, and

Orderable Information section of the data sheet available in the DLPC1438 product folder.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OUTLINE

ZEZ0201A

NFBGA - 1 mm max height

SCALE 1.000

PLASTIC BALL GRID ARRAY

13.1

12.9

A

B

BALL A1 CORNER

13.1

12.9

1 MAX

C

SEATING PLANE

0.1 C

0.31

0.21

BALL TYP

TYP

11.2 TYP

SYMM

(0.9) TYP

R

P

N

M

L

K

J

(0.9) TYP

SYMM

11.2

TYP

H

G

F

0.4

201X

E

D

C

0.3

0.15

0.08

C A

C

B

A

1

2

5 6

3 7 9 10 11 12 13 14 15

4

8

0.8 TYP

BALL A1 CORNER

4221521/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

201X ( 0.4)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221521/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

3

4

5

6

8

9

13 14 15

7

10 11 12

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221521/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC1438ZEZ
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP300S 和 DLP301S 数字微镜器件 (DMD) 的 DLP® 控制器 \| ZEZ \| 201 \| -30 to 105 控制器
文件：	总61页 (文件大小：2529K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC1438ZEZ [TI]

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