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DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

DLPC150 DLP^®用于高级照明控制的数字控制器

1 特性

3 说明

1

•

DLP2010 和 DLP2010NIR DMD 可靠运行所需的

显示控制器

DLPC150 控制器在用户电子设备与可见光 DLP2010

或近红外 (NIR) DLP2010NIR 数字微镜器件 (DMD) 之

间提供了一个方便、可靠的多功能接口，可快速、准确

且高效地操控照明以及生成图案。DLPC150 控制器支

持高速模式速率以及 LED 控制和数据格式化，适用于

多种输入格式。DLPC150 控制器还提供输入和输出触

发信号，用于将显示的图案与摄像机、传感器等外设同

步。DLPC150 控制器属于 0.2 WVGA 芯片组，该芯片

组包含 DLP2010 或 DLP2010NIR DMD 以及

•

高速图形序列模式

–

1 位二进制图形速率可达 2880Hz

输入与微镜 1 对 1 映射

•

与摄像头和传感器轻松同步

–

一个输入触发器

两个输出触发器

I²C 配置接口

•

DLPA2000 或 DLPA2005 电源管理集成芯片

输入像素接口支持：

(PMIC)。DLPC150 控制器能够将 DLP^®0.2 WVGA 可

见光或 NIR 芯片组集成到低功耗且低成本的小外形尺

寸应用中，从而实现可编程光谱和波长控制。例如

3D 扫描或计量系统、光谱仪、交互式显示屏、化学分

析仪、医疗仪器、皮肤分析、材料鉴别和化学检测。

–

24 位并行 RGB888 接口协议

16 位并行 RGB565 接口协议

高达 75MHz 的像素时钟

•

集成微镜驱动器

集成时钟生成功能

断电时自动 DMD 停止

器件信息⁽¹⁾

201 引脚、13mm × 13mm、0.8mm 间距、VFBGA

封装

器件型号

DLPC150

封装

封装尺寸（标称值）

13.00 × 13.00 mm²

VFBGA (201)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

•

分光计（化学分析）

–

便携式过程分析仪

便携式设备

•

压缩传感（单像素 NIR 摄像机）

3D 生物识别

机器视觉

红外场景投影

显微镜

激光打标

光学斩波器

光纤网络

DLP 0.2 英寸 WVGA 芯片组

DLPA2000

or

DLPA2005

(PMIC and LED

Driver)

DLPC150

Display Controller

DLP2010 DMD

or

DLP2010NIR DMD

D_P(0)

D_N(0)

VOFFSET

VBIAS

D_P(1)

D_N(1)

532-MHz

SubLVDS

DDR

D_P(2)

D_N(2)

VRESET

Interface

D_P(3)

D_N(3)

VDDI

VDD

DCLK_P

DCLK_N

LS_WDATA

LS_CLK

120-MHz

SDR

Interface

LS_RDATA

VSS

DMD_DEN_ARSTZ

System Signal Routing Omitted For Clarity

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS048

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 27

8.3 Feature Description................................................. 27

8.4 Device Functional Modes........................................ 33

Application and Implementation ........................ 34

9.1 Application Information............................................ 34

9.2 Typical Application ................................................. 35

1

2

3

4

5

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

5.1 DLPC150 Mechanical Data..................................... 11

Specifications....................................................... 13

6.1 Absolute Maximum Ratings .................................... 13

6.2 ESD Ratings............................................................ 13

6.3 Recommended Operating Conditions..................... 14

6.4 Thermal Information................................................ 14

9

10 Power Supply Recommendations ..................... 37

10.1 System Power-Up and Power-Down Sequence ... 37

10.2 DLPC150 Power-Up Initialization Sequence ........ 39

10.3 DMD Fast Park Control (PARKZ) ......................... 40

10.4 Hot Plug Usage..................................................... 40

10.5 Maximum Signal Transition Time.......................... 40

11 Layout................................................................... 41

11.1 Layout Guidelines ................................................. 41

11.2 Layout Example .................................................... 46

11.3 Thermal Considerations........................................ 46

12 器件和文档支持 ..................................................... 47

12.1 器件支持................................................................ 47

12.2 相关链接................................................................ 48

12.3 社区资源................................................................ 48

12.4 商标....................................................................... 48

12.5 静电放电警告......................................................... 48

12.6 Glossary................................................................ 48

13 "机械、封装和可订购信息..................................... 48

13.1 Package Option Addendum .................................. 49

6

6.5 Electrical Characteristics Over Recommended

Operating Conditions ............................................... 15

6.6 Electrical Characteristics......................................... 16

6.7 High-Speed Sub-LVDS Electrical Characteristics... 18

6.8 Low-Speed SDR Electrical Characteristics............. 19

6.9 System Oscillators Timing Requirements............... 20

6.10 Power-Up and Reset Timing Requirements ......... 20

6.11 Parallel Interface Frame Timing Requirements .... 21

6.12 Parallel Interface General Timing Requirements.. 23

6.13 Flash Interface Timing Requirements................... 24

Parameter Measurement Information ................ 25

7.1 Host_irq Usage Model ............................................ 25

7.2 Input Source............................................................ 26

Detailed Description ............................................ 27

8.1 Overview ................................................................. 27

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (March 2018) to Revision C

Page

•

Changed normal park time from 500 µs to 20 ms ................................................................................................................. 3

Deleted mention of bit weight for parallel data input ............................................................................................................. 4

Changes from Revision A (March 2015) to Revision B

Page

•

Changed maximum binary pattern rate to 2880 Hz in Table 4 ............................................................................................ 27

更新了器件标记图................................................................................................................................................................ 47

已添加社区资源部分 ............................................................................................................................................................. 48

Added MSL Peak Temp and Op Temp to Packaging Option Addendum ........................................................................... 49

Changes from Original (March 2015) to Revision A

Page

•

Consolidated the Pin Functions table .................................................................................................................................... 3

Moved Storage temperature to Absolute Maximum Ratings ............................................................................................... 13

Changed Handling Ratings to ESD Ratings ........................................................................................................................ 13

2

DLPC150

www.ti.com.cn

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

5 Pin Configuration and Functions

ZEZ Package

201-Pin VFBGA

Bottom View

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

CONTROL AND INITIALIZATION

DLPC150 power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a low-

to-high transition is detected on RESETZ. All DLPC150 controller power and clocks must be stable

before this reset is de-asserted. Connect to the reset output pin (RESETZ) of the DLPA2000 or

DLPA2005 PMIC. Note that the following signals will be tri-stated while RESETZ is asserted:

SPI0_CLK, SPI0_DOUT, SPI0_CSZ0, SPI0_CSZ1, PMIC_SPI_CLK, PMIC_SPI_CSZ,

PMIC_SPI_DIN, PMIC_SPI_DOUT, TRIG_OUT_1, TRIG_OUT_2, and GPIO[19:05]

External pullups or downs (as appropriate) should be added to all tri-stated output signals listed

(including bidirectional signals to be configured as outputs) to avoid floating DLPC150 controller

outputs during reset if connected to devices on the PCB that can malfunction. For SPI, at a

minimum, any chip selects connected to the devices should have a pullup.

Unused bidirectional signals can be functionally configured as outputs to avoid floating DLPC150

controller inputs after RESETZ is set high.

RESETZ

C11

I₆

The following signals are forced to a logic low state while RESETZ is asserted and corresponding

I/O power is applied:

LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ

No signals will be in their active state while RESETZ is asserted.

Note that no I²C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are set

high.

DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to enable

normal operation. PARKZ should be set high prior to releasing RESETZ (that is, prior to the low-to-

high transition on the RESETZ input). PARKZ should be set low for a minimum of 40 µs before any

power is removed from the DLPC150 such that the fast DMD PARK operation can be completed.

Note for PARKZ, fast PARK control should only be used when loss of power is eminent and beyond

the control of the host processor (for example, when the external power source has been

disconnected or the battery has dropped below a minimum level). The longest lifetime of the DMD

may not be achieved with the fast PARK operation. The longest lifetime is achieved with a normal

PARK operation. Because of this, PARKZ is typically used in conjunction with a normal PARK

request control input through PROJ_ON. The difference being that when the host sets PROJ_ON

low, which connects to both DLPC150 and the DLPA200x PMIC chip, the DLPC150 takes much

longer than 40 µs to park the mirrors. The DLPA200x holds on all power supplies, and keep

RESETZ high, until the longer mirror parking has completed. This longer mirror parking time, of up

to 20 ms, ensures the longest DMD lifetime and reliability.

PARKZ

C13

I₆

The DLPA2000 or DLPA2005 monitors power to the DLPC150 and detects an eminent power loss

condition and drives the PARKZ signal accordingly. Connect to the interrupt output pin of the

DLPA2000 or DLPA2005 PMIC.

(1) Refer to Table 1.

3

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A

logic low on this signal will cause the DLPC150 to PARK the DMD, but it will not power down the

DMD (the DLPA2000 or DLPA2005 controls the power down). The minimum high time is 200 ms.

The minimum low time is also 200 ms.

PROJ_ON

G14

B₁

Host interrupt (output)

This signal has two primary uses. The first use is to indicate when DLPC150 auto-initialization is in

progress and most importantly when it completes. The second is to indicate when service is

requested (that is an interrupt request).

HOST_IRQ⁽²⁾

N8

O₉

The DLPC150 tri-states this output during reset and requires an external pullup to drive this signal

to its inactive state.

I²C slave (port 0) SCL A bidirectional, open-drain signal with input hysteresis that requires an

external pullup. The slave I²C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by

VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to an equal or

higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely

satisfy the VIH specification of the slave I²C input buffers).

I²C slave (port 0) SDA. A bidirectional, open-drain signal with input hysteresis that requires an

external pullup. The slave I²C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by

VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to an equal or

higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely

satisfy the VIH specification of the slave I²C input buffers).

IIC0_SCL

IIC0_SDA

N10

N9

B₇

PARALLEL PORT INPUT DATA AND CONTROL

PCLK

P3

N4

P1

N5

I₁₁

B₅

I₁₁

Pixel clock⁽³⁾

Parallel data mask⁽⁴⁾

Vsync⁽⁵⁾

PDM_CVS_TE

VSYNC_WE

HSYNC_CS

Hsync⁽⁵⁾

Data valid active high framing signal.⁽⁵⁾DLPC150 also offers a manual data framing mode through

a software command. Refer to the DLPC150 Programmer's Guide for more information on the

manual data framing command.

DATAEN_CMD

P2

I₁₁

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

K2

K1

L2

Blue

L1

I₁₁

M2

M1

N2

N1

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

R1

R2

R3

P4

R4

P5

R5

P6

Green

I₁₁

(2) For more information about usage, see Host_irq Usage Model.

(3) Pixel clock capture edge is software programmable.

(4) The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to

ground through an external resistor (8 kΩ or less).

(5) VSYNC, HSYNC, and DATAEN polarity is software programmable.

4

DLPC150

www.ti.com.cn

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

Pin Functions (continued)

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

(TYPICAL RGB 888)

PDATA_16

R6

P7

R7

P8

R8

P9

R9

P10

Red

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

I₁₁

DMD RESET AND BIAS CONTROL

DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is

supplied, this signal will be driven low after the DMD is parked and before power is removed from

the DMD. If the 1.8-V power to the DLPC150 is independent of the 1.8-V power to the DMD, then

TI recommends a weak, external pulldown resistor to hold the signal low in the event DLPC150

power is inactive while DMD power is applied.

DMD_DEN_ARSTZ

B1

O₂

DMD_LS_CLK

A1

A2

B2

O₃

I₆

DMD, low speed interface clock

DMD, low speed serial write data

DMD, low speed serial read data

DMD_LS_WDATA

DMD_LS_RDATA

DMD SUB-LVDS INTERFACE

DMD_HS_CLK_P

DMD_HS_CLK_N

A7

B7

O₄

DMD high speed interface

DMD_HS_WDATA

_H_P

DMD_HS_WDATA

_H_N

DMD_HS_WDATA

_G_P

DMD_HS_WDATA

_G_N

DMD_HS_WDATA

_F_P

A3

B3

DMD_HS_WDATA

_F_N

A4

B4

DMD_HS_WDATA

_E_P

A5

B5

DMD_HS_WDATA

_E_N

DMD_HS_WDATA

_D_P

A6

B6

A8

B8

DMD high speed interface lanes, write data bits: (The true numbering and application of the

DMD_HS_DATA pins are software configuration dependent)

O₄

DMD_HS_WDATA

_D_N

A9

B9

DMD_HS_WDATA

_C_P

DMD_HS_WDATA

_C_N

A10

B10

A11

B11

DMD_HS_WDATA

_B_P

DMD_HS_WDATA

_B_N

DMD_HS_WDATA

_A_P

DMD_HS_WDATA

_A_N

5

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

SERIAL FLASH MEMORY INTERFACE

Synchronous serial port 0, clock output. Connect to clock input pin of the serial Flash memory

device.

SPI0_CLK

A13

A14

O₁₃

Synchronous serial port 0, chip select 0 output. Active low output. Connect to chip select pin of the

serial Flash memory device.

TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during

DLPC150 controller reset assertion.

SPI0_CSZ0

O₁₃

Synchronous serial port 0, chip select 1 output. Active low output. Connect to chip select pin of a

second serial Flash memory device.

TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during

DLPC150 controller reset assertion.

SPI0_CSZ1

C12

O₁₃

Synchronous serial port 0, receive data input. Connect to the data output of the serial Flash

memory device.

SPI0_DIN

B12

B13

I₁₂

Synchronous serial port 0, transmit data output. Connect to the data input of the serial Flash

memory device.

SPI0_DOUT

O₁₃

DLPA2000 OR DLPA2005 PMIC INTERFACE

Synchronous PMIC serial port, clock output. Connect to the clock input (SPI_CLK) of the

DLPA2000 or DLPA2005 PMIC.

PMIC_SPI_CLK

C15

B₁

Synchronous PMIC serial port, chip select output. Active low output. Connect to the chip select

input (SPI_CSZ) of the DLPA2000 or DLPA2005 PMIC.

TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during

DLPC150 controller reset assertion.

PMIC_SPI_CSZ

D15

B₁

Synchronous PMIC serial port, receive data input. Connect to the data output (SPI_DOUT) of the

DLPA2000 or DLPA2005 PMIC.

PMIC_SPI_DIN

C14

D14

B₁

Synchronous PMIC serial port, receive data output. Connect to the data input (SPI_DIN) of the

DLPA2000 or DLPA2005 PMIC.

PMIC_SPI_DOUT

Successive approximation ADC comparator input. Assumes a successive approximation ADC is

implemented with a WPC light sensor and/or a thermistor feeding one input of an external

comparator and the other side of the comparator is driven from the DLPC150 controller’s

CMP_PWM pin. Connect to the analog comparator output (CMP_OUT) of the DLPA2000 or

DLPA2005 PMIC. If this function is not used, pulled-down to ground.

PMIC_CMP_IN

A12

I₆

Successive approximation comparator pulse-duration modulation output. Supplies a PWM signal to

drive the successive approximation ADC comparator used in WPC light-to-voltage sensor

applications. Connect to the reference voltage input for analog comparator (PWM_IN) of the

DLPA2000 or DLPA2005. If this function is not used, leave this pin unconnected.

PMIC_CMP_PWM

PMIC_LED_SEL_0

A15

B15

O₁

LED enable select. Controlled by programmable DMD sequence

Enabled LED Timing

DLPA2000 or DLPA2005 application

00 = None

LED_SEL(1:0)

01 = Red

10 = Green

11 = Blue

These signals will be driven low when RESETZ is asserted and the corresponding I/O power is

supplied. They will continue to be driven low throughout the auto-initialization process. A weak,

external pulldown resistor is still recommended to ensure that the LEDs are disabled when I/O

power is not applied.

PMIC_LED_SEL_1

B14

N6

O₁

TRIGGER CONTROL

Input Trigger mode 1. Active high input signal that display the next pattern in the pattern sequence.

Pull-down this signal with an external resistor.

TRIG_IN_1

I₁₁

TRIG_OUT_1

TRIG_OUT_2

L14

E14

B₁

Output Trigger mode 1. Active high output signal during pattern exposure

Output Trigger mode 2. Active high output signal that indicates the first pattern in a sequence.

6

DLPC150

www.ti.com.cn

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

Pin Functions (continued)

NAME

GPIO PERIPHERAL INTERFACE

I/O⁽¹⁾

DESCRIPTION

NO.

General purpose I/O 19 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_19

M15

B₁

2. KEYPAD_4 (input): keypad applications

General purpose I/O 18 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_18

GPIO_17

GPIO_15

M14

L15

K15

B₁

2. KEYPAD_3 (input): keypad applications

General purpose I/O 17 (hysteresis buffer). Options:

1. Optional GPIO. Configured as a logic zero GPIO output and left unconnected if not used.

General purpose I/O 15 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. KEYPAD_0 (input): keypad applications

General purpose I/O 14 (hysteresis buffer). Option:

GPIO_14

GPIO_13

K14

J15

B₁

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 13 (hysteresis buffer). Options:

1. CAL_PWR (output): Intended to feed the calibration control of the successive approximation

ADC light sensor.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 12 (hysteresis buffer). Option:

GPIO_12

GPIO_11

J14

B₁

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 11 (hysteresis buffer). Options:

1. (Output): thermistor power enable.

H15

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General Purpose I/O 10 (hysteresis buffer). Options:

1. RC_CHARGE (output): Intended to feed the RC charge circuit of the successive approximation

ADC used to control the light sensor comparator.

GPIO_10

GPIO_09

H14

G15

B₁

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 09 (hysteresis buffer). Options:

1. LS_PWR (active high output): Intended to feed the power control signal of the successive

approximation ADC light sensor.

B₁

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 07 (hysteresis buffer). Options:

1. (All) LED_ENABLE (active high input). This signal can be used as an optional shutdown

interlock for the LED driver. Specifically, when so configured, setting LED_ENABLE = 0

(disabled), will cause LDEDRV_ON to be forced to 0 and LED_SEL(2:0) to be forced to b000.

Otherwise when LED_ENABLE = 1 (enabled), the DLPC150 controller is free to control the

LED SEL signals as it desires. There is however a 100-ms delay after LED_ENABLE

transitions from low-to-high before the interlock is released.

GPIO_07

GPIO_06

F15

F14

B₁

2. (Output): LABB output sample and hold sensor control signal.

3. (All) GPIO (bidirectional): Optional GPIO. Should be configured as a logic zero GPIO output

and left unconnected if not used (otherwise it will require an external pullup or pulldown to

avoid a floating GPIO input).

General purpose I/O 06 (hysteresis buffer). Option:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used. An external pulldown resistor is required to deactivate this signal during reset and auto-

initialization processes.

B₁

7

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

General purpose I/O 05 (hysteresis buffer). Option:

GPIO_05

E15

B₁

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

CLOCK AND PLL SUPPORT

Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin

serves as the oscillator input.

PLL_REFCLK_I

PLL_REFCLK_O

H1

J1

I₁₁

O₅

Reference clock crystal return. If an external oscillator is used in place of a crystal, then leave this

pin unconnected with no capacitive load.

BOARD LEVEL TEST AND DEBUG

Reserved Manufacturing test enable pin. For proper device operation, connect this signal directly to

ground.

HWTEST_EN

C10

I₆

Reserved

P12

P13

N13⁽⁶⁾

N12⁽⁶⁾

R10

I₆

Reserved pin. For proper device operation, leave this pin unconnected.

Reserved pin. For proper device operation, pull high to V_cc18with external pullup resistor.

Reserved pin. For proper device operation, leave this pin unconnected.

O₁

B₈

I₆

R11

M13

N11

I₆

Reserved pin.

Reserved

P11

I₆

For proper device operation, this pin must be tied to ground, through an external 8-kΩ, or less,

resistor. Failure to tie this pin low will cause startup and initialization problems.

Reserved

E1

E2

F1

F2

F3

G1

G2

D1

D2

C1

C2

Reserved pin. For proper device operation, leave this pin unconnected.

Reserved Test pin 0. For proper device operation, leave this pin unconnected (includes weak

internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as an output.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test

mode.

TSTPT_0

TSTPT_1

TSTPT_2

R12

R13

R14

B₁

Reserved Test pin 1. For proper device operation, leave this pin unconnected (includes weak

internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test

mode.

Reserved Test pin 2. For proper device operation, leave this pin unconnected (includes weak

internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test

mode.

(6) If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,

then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external

logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.

8

DLPC150

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ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

Pin Functions (continued)

NAME

I/O⁽¹⁾

DESCRIPTION

NO.

Reserved Test pin 3. For proper device operation, leave this pin unconnected (includes weak

internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

TSTPT_3

R15

B₁

Reserved Test pin 4. For proper device operation, leave this pin unconnected (includes weak

internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

P14

P15

N14

N15

B₁

Reserved Test pin 5. For proper device operation, leave this pin unconnected (includes weak

internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

Reserved Test pin 6. For proper device operation, leave this pin unconnected (includes weak

internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

Reserved Test pin 7. For proper device operation, leave this pin unconnected (includes weak

internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode

selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.

POWER AND GROUND

C5, D5,

D7,

D12,

J4, J12,

K3, L4,

L12,

M6, M9,

D9,

VDD

PWR Core power 1.1 V (main 1.1 V)

D13,

F13,

H13,

L13,

M10,

D3, E3

VDDLP12

C3

PWR Core power 1.1 V

C4, D6,

D8,

D10,

E4,

E13,

F4, G4,

G12,

H4,

H12,

J3, J13,

K4,

K12,

L3, M4,

M5, M8,

M12,

VSS

G13,

GND Core ground (eDRAM, I/O ground, thermal ground)

C6, C8,

F6, F7,

F8, F9,

F10,

G6, G7,

G8, G9,

G10,

H6, H7,

H8, H9,

H10,

J6, J7,

J8, J9,

J10, K6,

K7, K8,

K9, K10

9

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

C7, C9,

D4,

E12,

F12,

K13,

M11

All 1.8-V I/O power:

VCC18

PWR (1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface.

This includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)

M3, M7,

N3, N7

Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0, PDATA, video syncs, and

HOST_IRQ pins)

VCC_INTF

VCC_FLSH

PWR

Flash interface I/O power:1.8 to 3.3 V

PWR

D11

(Dedicated SPI0 power pin)

VDD_PLLM

VSS_PLLM

VDD_PLLD

VSS_PLLD

H2

G3

J2

PWR MCG PLL 1.1-V power

RTN MCG PLL return

PWR DCG PLL 1.1-V power

RTN DCG PLL return

H3

10

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ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

Table 2. Internal Pullup and Pulldown Characteristics⁽¹⁾⁽²⁾

INTERNAL PULLUP AND PULLDOWN

RESISTOR CHARACTERISTICS

V_CCIO

MIN

MAX

UNIT

3.3 V

2.5 V

1.8 V

3.3 V

2.5 V

1.8 V

29

38

56

30

36

52

63

90

kΩ

Weak pullup resistance

148

72

Weak pulldown resistance

101

167

(1) The resistance is dependent on the supply voltage level applied to the I/O.

(2) An external 8-kΩ pullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any associated

internal pullups or pulldowns.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (see

(1)

)

MIN

MAX

UNIT

SUPPLY VOLTAGE⁽²⁾⁽³⁾

V_(VDD)(core)

–0.3

1.21

1.32

1.96

3.60

1.99

2.75

3.60

1.96

2.72

3.58

1.21

V

V_(VDDLP12)(core)

Power + sub-LVDS

Host I/O power

If 1.8-V power used

V_{(VCC_INTF)}

V

If 2.5-V power used

If 3.3-V power used

Flash I/O power

If 1.8-V power used

V_{(VCC_FLSH)}

If 2.5-V power used

If 3.3-V power used

V_{(VDD_PLLM)}(MCG PLL)

V_{(VDD_PLLD)}(DCG PLL)

GENERAL

V

T_J

Operating junction temperature

Storage temperature

–30

–40

125

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Overlap currents, if allowed to continue flowing unchecked, not only increase total power dissipation in a circuit, but degrade the circuit

reliability, thus shortening its usual operating life.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.045

1.02

NOM

1.1

MAX

UNIT

V_(VDD)

Core power 1.1 V (main 1.1 V)

Core power 1.1 V

±5% tolerance

1.155

1.18

1.28

V

1.1

V_(VDDLP12)

V

(1)

See

1.12

1.2

All 1.8-V I/O power:

(1.8-V power supply for all I/O other than the

host or parallel interface and the SPI flash

interface. This includes RESETZ, PARKZ,

LED_SEL, CMP, GPIO, TSTPT, and Reserved

pins.)

V_(VCC18)

±8.5% tolerance

1.64

1.8

1.96

1.64

2.28

3.02

1.64

2.28

3.02

1.8

2.5

3.3

1.8

2.5

3.3

1.96

2.72

3.58

1.96

2.72

3.58

Host or parallel interface I/O power: 1.8 to 3.3 V

(includes IIC0, PDATA, video syncs, and

HOST_IRQ pins)

±8.5% tolerance

See

V_{(VCC_INTF)}

V

(1)

±8.5% tolerance

V_{(VCC_FLSH)}

Flash interface I/O power:1.8 to 3.3 V

MCG PLL 1.1-V power

V

(1)

See

±9.1% tolerance

V_{(VDD_PLLM)}

V_{(VDD_PLLD)}

T_A

1.025

1.1

1.155

(2)

See

±9.1% tolerance

DCG PLL 1.1-V power

1.025

–30

1.155

85

V

(2)

See

Operating ambient temperature range⁽³⁾

°C

(1) These supplies have multiple valid ranges.

(2) These I/O supply ranges are wider to facilitate additional filtering.

(3) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value at

0 forced air flow (R_θJAat 0 m/s), a JEDEC JESD51 standard test card and environment, along with min and max estimated power

dissipation across process, voltage, and temperature. Thermal conditions vary by application, which will impact R_θJA. Thus, maximum

operating ambient temperature varies by application.

(a) T_{a_min}= T_{j_min}– (P_{d_min}× R_θJA) = –30°C – (0.0W × 30.3°C/W) = –30°C

(b) T_{a_max}= T_{j_max}– (P_{d_max}× R_θJA) = +105°C – (0.348W × 30.3°C/W) = +94.4°C

6.4 Thermal Information

DLPC150

THERMAL METRIC⁽¹⁾

ZEZ (VFBGA)

UNIT

°C/W

176 PINS

201 PINS

10.1

R_θJC

Junction-to-case thermal resistance

11.2

30.3

27.4

26.6

at 0 m/s of forced airflow⁽²⁾

at 1 m/s of forced airflow⁽²⁾

at 2 m/s of forced airflow⁽²⁾

28.8

R_θJA

Junction-to-air thermal resistance

25.3

24.4

Temperature variance from junction to package top center temperature, per unit power

dissipation

(3)

ψ_JT

.27

.23

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC defined

standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC150 PCB and thus the reported thermal

resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different , it is the best

information available during the design phase to estimate thermal performance.

(3) Example: (0.5 W) × (0.2 C/W) ≈ 1.00°C temperature rise.

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6.5 Electrical Characteristics Over Recommended Operating Conditions

(1)(2)(3)(4)(5)(6)

(see

)

PARAMETER

TEST CONDITIONS⁽⁷⁾

IDLE disabled, WVGA, 60 Hz

IDLE enabled, WVGA, 60 Hz

IDLE disabled, WVGA, 60 Hz

IDLE enabled, WVGA, 60 Hz

IDLE disabled, WVGA, 60 Hz

IDLE enabled, WVGA, 60 Hz

IDLE disabled, WVGA, 60 Hz

MIN TYP⁽⁸⁾MAX⁽⁹⁾UNIT

112

85

232.2

I_CC11

Supply voltage, 1.1-V Main core power

Supply voltage, 1.1-V MCG PLL power

Supply voltage, 1.1-V DCG PLL power

mA

112

85

I_{CC_PLLM}

112

85

I_{CC_PLLD}

Supply voltage, 1.8-V I/O power:

13

(1.8-V power supply for all I/O other than the

host or parallel interface and the SPI flash

interface. This includes sub-LVDS DMD I/O,

RESETZ, PARKZ LED_SEL, CMP, GPIO,

IIC1, TSTPT, and JTAG pins)

I_CC18

mA

IDLE enabled, WVGA, 60 Hz

13

Supply voltage, 1.8-V Host or parallel

interface I/O power: (includes IIC0, PDATA,

video syncs, and HOST_IRQ pins)

IDLE disabled, WVGA, 60 Hz,

V_{VCC_INTF}= 1.8V

I_{CC_INTF}

1.5

mA

Supply voltage, 1.8-V Flash interface I/O

power

IDLE disabled, WVGA, 60 Hz,

V_{VCC_FLSH}= 1.8V

I_{CC_FLSH}

1.01

(1) Assumes 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT or HVT cells.

(2) Programmable host and flash I/O are at minimum voltage (that is 1.8 V) for this typical scenario.

(3) Max currents column use typical motion video as the input. The typical currents column uses SMPTE color bars as the input.

(4) Some applications (that is, high-resolution 3D) may be forced to use 1-oz copper to manage DLPC150 controller package heat.

(5) For the typical cases, all pins using 1.8 V are tied together as are 1.1-V pins, and the current specified is for the collective 1.8-V and 1.1-

V current.

(6) Input image is 854 × 480 (WVGA) 24-bits on the parallel interface at the frame rate shown with DLP2010 or DLP2010NIR.

(7) In normal mode.

(8) Assumes typical case power PVT condition = nominal process, typical voltage, typical temperature (55°C junction). WVGA resolution.

(9) Assumes worse case power PVT condition = corner process, high voltage, high temperature (105°C junction), WVGA resolution .

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6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (see

(1)(2)

)

PARAMETER⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

I²C buffer (I/O type 7)

0.7 × VCC_INTF

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

1.17

3.6

1.8-V LVTTL (I/O type 1, 6)

identified below: (2)

CMP_OUT; PARKZ; RESETZ;

GPIO[19:05]; TRIG_OUT_1;

TRIG_OUT_2

High-level

input

threshold

voltage

1.3

1.7

3.6

V

V_IH

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

3.6

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13)

I²C buffer (I/O type 7)

2

–0.5

–0.3

0.3 × VCC_INTF

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

0.63

0.5

1.8-V LVTTL (I/O type 1, 6)

identified below: (2)

CMP_OUT; PARKZ; RESETZ;

GPIO[19:05]; TRIG_OUT_1;

TRIG_OUT_2

Low-level

input

threshold

voltage

–0.3

V_IL

V

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

–0.3

0.7

0.8

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13)

Steady-state

common

mode voltage

1.8 sub-LVDS (DMD high speed)

(I/O type 4)

V_CM

800

900

200

1000

mV

Differential

ǀV_ODǀ output

magnitude

1.8 sub-LVDS (DMD high speed)

(I/O type 4)

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

1.35

1.7

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

High-level

output

voltage

V_OH

V

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13)

2.4

1.8 sub-LVDS – DMD high

speed (I/O type 4)

1

I²C buffer (I/O type 7)

VCC_INTF > 2 V

VCC_INTF < 2 V

0.4

0.2 × VCC_INTF

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

0.45

0.7

Low-level

output

voltage

2.5 V LVTTL (I/O type 5, 9, 11,

12, 13)

V_OL

V

3.3 V LVTTL (I/O type 5, 9, 11,

12, 13)

0.4

1.8 sub-LVDS – DMD high

speed (I/O type 4)

0.8

(1) I/O is high voltage tolerant; that is, if VCC = 1.8 V, the input is 3.3-V tolerant, and if VCC = 3.3 V, the input is 5-V tolerant.

(2) DLPC150 controller pins: CMP_OUT; PARKZ; RESETZ; GPIO[19:05]; TRIG_OUT_1; TRIG_OUT_2 have slightly varied V_IHand V_IL

range from other 1.8-V I/O.

(3) The number inside each parenthesis for the I/O refers to the type defined in Table 1.

16

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ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) (see ⁽¹⁾⁽²⁾

)

PARAMETER⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

4 mA

2

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

8 mA

3.5

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

24 mA

10.6

High-level

output

current

I_OH

mA

2.5-V LVTTL (I/O type 5)

4 mA

8 mA

5.4

2.5-V LVTTL (I/O type 9, 13)

10.8

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

24 mA

28.7

3.3-V LVTTL (I/O type 5 )

3.3-V LVTTL (I/O type 9, 13)

I²C buffer (I/O type 7)

4 mA

8 mA

7.8

15

3

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

4 mA

8 mA

24 mA

2.3

4.6

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

Low-level

output

13.9

I_OL

mA

current

2.5-V LVTTL (I/O type 5)

4 mA

8 mA

5.2

2.5-V LVTTL (I/O type 9, 13)

10.4

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

24 mA

31.1

3.3-V LVTTL (I/O type 5 )

4 mA

8 mA

4.4

8.9

3.3-V LVTTL (I/O type 9, 13)

0.1 × VCC_INTF < VI

< 0.9 × VCC_INTF

I²C buffer (I/O type 7)

–10

10

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

High-

10

µA

10

impedance

leakage

current

I_OZ

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13)

I²C buffer (I/O type 7)

10

5

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13)

2.6

3.5

Input

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13)

capacitance

(including

package)

3.5

pF

C_I

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13)

3.5

3

1.8 sub-LVDS – DMD high

speed (I/O type 4)

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ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

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6.7 High-Speed Sub-LVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

1

UNIT

V

V_CM

V_CM(Δpp)⁽¹⁾

V_CM(Δss)⁽¹⁾

Steady-state common mode voltage

V_CMchange peak-to-peak (during switching)

V_CMchange steady state

0.8

0.9

75

mV

V

–10

10

(2)

|V_OD

|

Differential output voltage magnitude

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Differential output rise time

200

V_OD(Δ)

V_OH

10

1

V_OL

0.8

V

(2)

t_R

250

ps

(2)

t_F

Differential output fall time

ps

t_MAX

Max switching rate

1064

55%

120

Mbps

DCout

Output duty cycle

45%

80

50%

100

(1)

Tx_term

Internal differential termination

Ω

100-Ω differential PCB trace

(50-Ω transmission lines)

Tx_load

0.5

6

inches

(1) Definition of V_CMchanges:

V_cm

V_cm(ûss)

V_cm(ûpp)

(2) Note that V_ODis the differential voltage swing measured across a 100-Ω termination resistance connected directly between the

transmitter differential pins. |V_OD| is the magnitude of this voltage swing relative to 0. Rise and fall times are defined for the differential

V_ODsignal as follows:

+ Vod

t_F

t_R

80%

20%

|Vod|

0V

V_od

- Vod

Differential Output Signal

(Note Vcm is removed when the signals are viewed differentially)

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ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

6.8 Low-Speed SDR Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

ID

TEST CONDITIONS

MIN

MAX

UNIT

Operating voltage

VCC18 (all signal groups)

1.64

1.96

V

VIHD(DC)

Signal group 1

DC input high voltage

DC input low voltage⁽¹⁾

AC input high voltage⁽²⁾

AC input low voltage

All

0.7 × VCC18

–0.5

VCC18 + 0.5

0.3 × VCC18

VCC18 + 0.5

V

VILD(DC)

Signal group 1

All

VIHD(AC)

Signal group 1

0.8 × VCC18

–0.5

VILD(AC)

Signal group 1

0.2 × VCC18

3

Signal group 1

Signal group 2

Signal group 3

1

0.25

0.5

(3)(4)(5)(6)

Slew rate

V/ns

(1) VILD(AC) min applies to undershoot.

(2) VIHD(AC) max applies to overshoot.

(3) Signal group 1 output slew rate for rising edge is measured between VILD(DC) to VIHD(AC).

(4) Signal group 1 output slew rate for falling edge is measured between VIHD(DC) to VILD(AC).

(5) Signal group 1: See Figure 2.

(6) Signal groups 2 and 3 output slew rate for rising edge is measured between VILD(AC) to VIHD(AC).

Figure 2. Low Speed (Ls) I/O Input Thresholds

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6.9 System Oscillators Timing Requirements⁽¹⁾

NUMBER

MIN

23.998

41.67

MAX

UNIT

MHz

ns

1a

1b

2

ƒ_clockClock frequency, MOSC⁽²⁾

t_c

Cycle time, MOSC⁽²⁾

ƒ_clockClock frequency, MOSC⁽²⁾

t_c

Cycle time, MOSC⁽²⁾

t_w(H)Pulse duration⁽³⁾, MOSC, high

t_w(L)Pulse duration⁽³⁾, MOSC, low

Option 1: 24-MHz oscillator

24.002

41.663

16.002

62.492

40 t_c%

10

Option 1: 24-MHz oscillator

Option 2: 16-MHz oscillator

15.998

62.508

MHz

ns

Option 2: 16-MHz oscillator

50% to 50% reference points (signal)

20% to 80% reference points (signal)

3

4

t_t

Transition time⁽³⁾, MOSC, t_t= t_f/ t_r

ns

5

t_jp

Long-term, peak-to-peak, period jitter⁽³⁾

MOSC

,

2%

(that is the deviation in period from ideal

period due solely to high frequency jitter)

(1) The I/O pin TSTPT_6 enables the DLPC150 controller to use two different oscillator frequencies through a pullup control at initial

DLPC150 controller power-up. If a pullup is applied to this pin then a 16.0-MHz oscillator option must be used instead of the 24-MHz

option shown.

(2) The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.) The

MOSC input cannot support spread spectrum clock spreading.

(3) Applies only when driven through an external digital oscillator.

t_t

t_c

t_w(H)

t_w(L)

80%

20%

80%

20%

50%

MOSC

50%

Figure 3. System Oscillators

6.10 Power-Up and Reset Timing Requirements

NUMBER

MIN

1.25

MAX

UNIT

1

2

t_w(L)

t_t

Pulse duration, inactive low, RESETZ 50% to 50% reference points

(signal)

Transition time, RESETZ⁽¹⁾, t_t= t_f/ t_r20% to 80% reference points

(signal)

µs

0.5

µs

(1) For more information on RESETZ, see Pin Configuration and Functions.

DC Power

Supplies

t_t

80%

50%

20%

80%

50%

20%

80%

50%

20%

80%

50%

20%

RESETZ

t_w(L)

Figure 4. Power-Up and Power-Down RESETZ Timing

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6.11 Parallel Interface Frame Timing Requirements

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

Pulse duration – VSYNC_WE high

50% reference

points

1

lines

Vertical back porch (VBP) – time from the leading

edge of VSYNC_WE to the leading edge

HSYNC_CS for the first active line (see

50% reference

points

2

1

lines

(1)

)

t_{p_vfp}

Vertical front porch (VFP) – time from the leading

50% reference

edge of the HSYNC_CS following the last active line points

in a frame to the leading edge of VSYNC_WE (see

(1)

)

(1)

t_{p_tvb}

Total vertical blanking – time from the leading edge

of HSYNC_CS following the last active line of one

frame to the leading edge of HSYNC_CS for the first

active line in the next frame. (This is equal to the

sum of VBP (t_{p_vbp}) + VFP (t_{p_vfp}).)

50% reference

points

See

lines

t_{p_hsw}

t_{p_hbp}

t_{p_hfp}

t_{p_thb}

Pulse duration – HSYNC_CS high

50% reference

points

4

128

PCLKs

Horizontal back porch – time from rising edge of

HSYNC_CS to rising edge of DATAEN_CMD

50% reference

points

Horizontal front porch – time from falling edge of

DATAEN_CMD to rising edge of HSYNC_CS

50% reference

points

8

(2)

Total horizontal blanking – sum of horizontal front

and back porches

50% reference

points

See

(1) The minimum total vertical blanking is defined by the following equation: t_{p_tvb}(min) = 6 + [6 × Max(1, Source_ALPF/ DMD_ALPF)] lines

where:

(a) SOURCE_ALPF = Input source active lines per frame

(b) DMD_ALPF = Actual DMD used lines per frame supported

(2) Total horizontal blanking is driven by the max line rate for a given source which will be a function of resolution and orientation. The

following equation can be applied for this: t_{p_thb}= Roundup[(1000 × ƒ_clock)/ LR] – APPL

where:

(a) ƒ_clock= Pixel clock rate in MHz

(b) LR = Line rate in kHz

(c) APPL is the number of active pixels per (horizontal) line.

(d) If t_{p_thb}is calculated to be less than t_{p_hbp}+ t_{p_hfp}then the pixel clock rate is too low or the line rate is too high, and one or both

must be adjusted.

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1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

P

n-2

P

n-1

PDATA(23/15:0)

PCLK

P0

P1

P2

P3

Pn

Figure 5. Parallel Interface Frame Timing

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6.12 Parallel Interface General Timing Requirements⁽¹⁾

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

Clock frequency, PCLK

Clock period, PCLK

1

75

50% reference points

Max ƒ_clock

6.66

1000

(2)

Clock jitter, PCLK

see

Pulse duration low, PCLK

Pulse duration high, PCLK

50% reference points

2.43

0.9

ns

t_{p_wl}

t_{p_su}

Setup time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

t_{p_h}

t_t

Hold time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

50% reference points

0.9

0.2

ns

Transition time – all signals

20% to 80% reference

points

2

(1) The active (capture) edge of PCLK for HSYNC_CS, DATEN_CMD and PDATA(23:0) is software programmable, but defaults to the

rising edge.

(2) Clock jitter (in ns) should be calculated using this formula: Jitter = [1 / ƒ_clock– 5.76 ns]. Setup and hold times must be met during clock

jitter.

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

Figure 6. Parallel Interface General Timing

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6.13 Flash Interface Timing Requirements

The DLPC150 controller flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The

(1)(2)

DLPC150 controller can support 1- to 16-Mb flash memories. (see

)

MIN

1.42

704

352

0.2

MAX

36

UNIT

MHz

ns

(3)

ƒ_clock

t_{p_clkper}

t_{p_wh}

t_{p_wl}

t_t

Clock frequency, SPI_CLK

Clock period, SPI_CLK

See

50% reference points

27.7

Pulse duration low, SPI_CLK

Pulse duration high, SPI_CLK

Transition time – all signals

ns

20% to 80% reference

points

3

ns

t_{p_su}

Setup time – SPI_DIN valid before SPI_CLK falling

edge

50% reference points

10

0

ns

t_{p_h}

Hold time – SPI_DIN valid after SPI_CLK falling edge

50% reference points

ns

t_{p_clqv}

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

1

3

t_{p_clqx}

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

50% reference points

–3

ns

(1) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC150 controller

does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for

SPI devices with long clock-to-Q timing. DLPC150 controller hold capture timing has been set to facilitate reliable operation with

standard external SPI protocol devices.

(2) With the above output timing, the DLPC150 controller provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative

to the rising edge of SPI_CLK.

(3) This range include the 200 ppm of the external oscillator (but no jitter).

t_clkper

SPI_CLK

t_wh

t_wl

(ASIC Output)

t_{p_su}

t_{p_h}

SPI_DIN

(ASIC Inputs)

t_{p_clqv}

SPI_DOUT, SPI_CS(1:0)

(ASIC Outputs)

t_{p_clqx}

Figure 7. Flash Interface Timing

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7 Parameter Measurement Information

7.1 Host_irq Usage Model

•

While reset is applied, HOST_IRQ will reset to tri-state (an external pullup pulls the line high).

HOST_IRQ will remain tri-state (pulled high externally) until the microprocessor boot completes. While the

signal is pulled high, this indicates that the DLPC150 controller is performing boot-up and auto-initialization.

•

As soon as possible after boot-up, the microprocessor will drive HOST_IRQ to a logic high state to indicate

that the DLPC150 controller is continuing to perform auto-initialization (no real state change occurs on the

external signal).

•

Upon completion of auto-initialization, software will set HOST_IRQ to a logic low state to indicate the

completion of auto-initialization. At the falling edge, the system is said to enter the INIT_DONE state.

After auto-initialization completes, HOST_IRQ is used to generate a logic high interrupt pulse to the host

through software control. This interrupt indicates that the DLPC150 controller has detected an error condition

or otherwise requires service.

500 ms max

RESETZ

The ﬁrst falling edge of HOST_IRQ

indicates auto-initialization done.

(ERR IRQ)

(INIT_BUSY)

HOST_IRQ

(with External

Pullup)

3 µs min

0 ms min

An active high pulse on HOST_IRQ following the

initialization period indicates an error condition

was detected. The source of the error is reported

in the system status.

I²C access to DLPC150 should not start until HOST_IRQ

goes low (this should occur within 500 ms from the

release of RESETZ.

Figure 8. Host Irq Timing

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7.2 Input Source

Table 3. Supported Input Source Ranges^(1)(2)(3)(4)

SOURCE RESOLUTION RANGE

HORIZONTAL VERTICAL

(5)

INTERFACE

BITS / PIXEL

FRAME RATE RANGE

Parallel

16 or 24-bit

16-bit

320 to 1280

200 to 800

47 to 63 Hz

60 Hz

SPI Flash

(1) The user must stay within specifications for all source interface parameters such as max clock rate and max line rate.

(2) The max DMD size for all rows in the table is 854 × 480.

(3) To achieve the ranges stated, the composer-created firmware used must be defined to support the source parameters used.

(4) These interfaces are supported with the DMD sequencer sync mode command (3Bh) set to auto.

(5) Bits / Pixel does not necessarily equal the number of data pins used on the DLPC150 controller. Fewer pins are used if multiple clocks

are used per pixel transfer.

7.2.1 Parallel Interface Supports Two Data Transfer Formats

•

24-bit RGB888 on a 24 data wire interface

16-bit RGB565 on a 16 data wire interface

Pdata Bus – Parallel Interface Bit Mapping Modes shows the required PDATA(23:0) bus mapping for these two

data transfer formats.

7.2.1.1 Pdata Bus – Parallel Interface Bit Mapping Modes

23

0

Red / Cr

Green / Y

Blue / Cb

ASIC Input

Mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

ASIC Internal Re-

Mapping

7

5

4

3

5

4

3

4

3

2

0

Red / Cr

Green / Y

Blue / Cb

Figure 9. 24-Bit Rgb-888 I/O Mapping

23

7

0

Input

3

Input

ASIC Input

Mapping

6

5

4

3

2

1

0

7

6

5

4

2

1

0

7

6

5

4

3

2

1

0

ASIC Internal Re-

Mapping

7

6

3

2

3

4

3

0

Red / Cr

Green / Y

Blue / Cb

Figure 10. 16-Bit Rgb-565 I/O Mapping

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8 Detailed Description

8.1 Overview

In DLP-based solutions, image data is 100% digital from the DLPC150 controller input port to the image on the

DMD. The image stays in digital form and is not converted into an analog signal. The DLPC150 controller

processes the digital input image and converts the data into a format needed by the DMD. The DMD steers light

by using binary pulse-duration modulation (PWM) for each micromirror. For further details, refer to DMD data

sheet (DLPS046 for the DLP2010 and DLPS059 for the DLP2010NIR).

As shown in Functional Block Diagram, the DLPC150 controller takes input data from the Parallel or SPI

interface, optionally performs image processing, and formats the data for the DMD. The DLPC150 controller

offers a Pattern Generation Mode of operation. In Pattern Generation Mode, the DLPC150 bypasses the video

processing functions for accurate pattern display with one-to-one association with the corresponding micromirror

on the DMD. The pattern generation mode supports inputs and speeds shown in Table 4. This high speed

pattern display is well-suited for wavelength selection and control techniques used in spectroscopy, compressive

sensing, machine vision, or laser marking.

Table 4. Pattern Generation Mode Supported Inputs And Speeds

INPUT

FORMAT

MAXIMUM PATTERN RATE

SPI Flash memory

Binary pattern sequence encoded as a

16-bit RGB565 image

960 Hz

24-bit parallel input

Binary pattern sequence encoded as a

16-bit RGB565 image

1008 Hz

2880 Hz

Binary pattern sequence encoded as a

24-bit RGB888 image

8.2 Functional Block Diagram

PDATA[23:0]

PCLK

Parallel

HSYNC

VSYNC

DATAEN

Interface

DMD

Formatter

DMD

Interface

Sub-LVDS DATA

LPSDR CTRL

Image Processing

- Image Resizing

- Degamma

- Color Coordinate Adjustment

SPI0_CLK

SPI

Interface

SPI0_CSZ

SPI0_DIN

SPIO_DOUT

embedded

DRAM

RESETZ

PARKZ

PROJ_ON

Control

HOST_IRQ

Trigger

Control

PMIC

Interface

GPIO

Clocks

IIC0

8.3 Feature Description

8.3.1 Interface Timing Requirements

This section defines the timing requirements for the external interfaces for the DLPC150 controller.

8.3.1.1 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal

(VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data

bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are

programmable. Figure 5 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is

optional in that the DLPC150 provides auto-framing parameters that can be programmed to define the data valid

window based on pixel and line counting relative to the horizontal and vertical syncs.

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Feature Description (continued)

In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows

periodic frame updates to be stopped without losing the displayed image. When PDM_CVS_TE is active, it acts

as a data mask and does not allow the source image to be propagated to the display. A programmable PDM

polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE

active high; if this function is not desired, then it should be tied to a logic low on the PCB. PDM_CVS_TE is

restricted to change only during vertical blanking.

NOTE

VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display

sequencer will stop and cause the LEDs to be turned off.

8.3.2 Serial Flash Interface

DLPC150 uses an external SPI serial flash memory device for configuration support. The minimum required size

is dependent on the desired minimum number of sequences, CMT tables, and splash options while the maximum

supported is 16 Mb.

For access to flash, the DLPC150 uses a single SPI interface operating at a programmable frequency complying

to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to 180 MHz/N,

where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz. Note that this

results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz, 25.7 MHz,

22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The DLPC150 supports two independent SPI chip selects; however, the flash must be connected to SPI chip

select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select

zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control

to an auto-initialization routine within program memory. The DLPC150 asserts the HOST_IRQ output signal high

while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after

auto-initialization is complete will the DLPC150 be ready to receive commands through I²C.

The DLPC150 should support any flash device that is compatible with the modes of operation, features, and

performance as defined in Table 5 and Table 6.

Table 5. SPI Flash Required Features or Modes of Operation

FEATURE

SPI interface width

SPI protocol

DLPC150 REQUIREMENT

Single

SPI mode 0

Auto-incrementing

Page mode

256 B

Fast READ addressing

Programming mode

Page size

Sector size

4 KB sector

any

Block size

Block protection bits

Status register bit(0)

Status register bit(1)

Status register bits(6:2)

Status register bit(7)

0 = Disabled

Write in progress (WIP) {also called flash busy}

Write enable latch (WEN)

A value of 0 disables programming protection

Status register write protect (SRWP)

The DLPC150 only supports single-byte status register R/W command execution, and thus may not be

compatible with flash devices that contain an expansion status byte. However, as long as expansion status

Status register bits(15:8)

(that is expansion status byte) byte is considered optional in the byte 3 position and any write protection control in this expansion status

byte defaults to unprotected, then the device should be compatible with DLPC150.

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To support flash devices with program protection defaults of either enabled or disabled, the DLPC150 always

assumes the device default is enabled and goes through the process of disabling protection as part of the boot-

up process. This process consists of:

•

A write enable (WREN) instruction executed to request write enable, followed by

A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable

latch (WEL) bit

•

After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes

0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC150 issues:

•

A write enable (WREN) instruction to request write enable, followed by

A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

After the write enable latch (WEL) bit is set, the program or erase instruction is executed

Note the flash automatically clears the write enable status after each program and erase instruction

The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note

however that DLPC150 does not read the flash’s electronic signature ID and thus cannot automatically adapt

protocol and clock rate based on the ID.

Table 6. SPI Flash Instruction Opcode and Access Profile Compatibility Requirements

FIRST BYTE

(OPCODE)

SECOND

BYTE

SPI FLASH COMMAND

THIRD BYTE FOURTH BYTE FIFTH BYTE

SIXTH BYTE

Fast READ (1 Output)

Read status

0x0B

0x05

0x01

0x06

0x02

0x20

0xC7

ADDRS(0)

n/a

ADDRS(1)

ADDRS(2)

STATUS(0)

dummy

DATA(0)⁽¹⁾

n/a

(2)

Write status

STATUS(0)

Write enable

Page program

Sector erase (4KB)

Chip erase

ADDRS(0)

ADDRS(1)

ADDRS(2)

DATA(0)⁽¹⁾

(1) Only the first data byte is show, data continues for the duration of the read.

(2) DLPC150 does not support access to a second/ expansion Write Status byte.

The specific and timing compatibility requirements for a DLPC150 compatible flash are listed in Table 7 and

Table 8.

Table 7. SPI Flash Key Timing Parameter Compatibility Requirements⁽¹⁾⁽²⁾

SPI FLASH TIMING PARAMETER

SYMBOL

ALTERNATE

SYMBOL

MIN

MAX

UNIT

Access frequency

(all commands)

FR

f_C

≤1.42

MHz

ns

Chip select high time (also called chip select deselect

time)

t_SHSL

t_CSH

≤200

≥0

Output hold time

t_CLQX

t_CLQV

t_DVCH

t_CHDX

t_HO

t_V

t_DSU

t_DH

ns

Clock low to output valid time

Data in set-up time

Data in hold time

≤ 11

≤5

(1) The timing values are related to the specification of the flash device itself, not the DLPC150.

(2) The DLPC150 does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins should be tied to a

logic high on the PCB through an external pullup.

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The DLPC150 supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the

corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices

supported by DLPC150.

Table 8. DLPC150 Verified Compatible SPI Flash Device Options^{(1) (2)}

DENSITY (M-BITS)

VENDOR

PART NUMBER

PACKAGE SIZE

1.8-V Compatible Devices

4 Mb

Winbond

Macronix

W25Q40BWUXIG

MX25U4033EBAI-12G

2 × 3 mm USON

4 Mb

1.43 × 1.94 mm WLCSP

1.68 × 1.99 mm WLCSP

4 Mb

2.5- or 3.3-V Compatible Devices

16 Mb

64 Mb

Winbond

W25Q16CLZPIG

W25Q64FVZPIG

5 × 6 mm WSON

8.3.3 Serial Flash Programming

Note that the flash can be programmed through the DLPC150 over I²C or by driving the SPI pins of the flash

directly while the DLPC150 I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by

holding RESETZ in a logic low state while power is applied to the DLPC150. Note that SPI0_CSZ1 is not tri-

stated by this same action.

8.3.4 I²C Control Interface

DLPC150 supports I2C commands through the control interface. The control interface allows another master

processor to send commands to the DLPC150 chipset to query system status or perform realtime operations.

The DLPC150 I²C interface ports support 100-kHz baud rate at the 7-bit address 0x1B. By definition, I²C

transactions operate at the speed of the slowest device on the bus, thus there is no requirement to match the

speed grade of all devices in the system.

8.3.5 DMD (Sub-LVDS) Interface

The DLPC150 controller DMD interface consists of a high speed 1.8-V sub-LVDS output only interface with a

maximum clock speed of 532-MHz DDR and a low speed SDR (1.8-V LVCMOS) interface with a fixed clock

speed of 120 MHz. The DLPC150 sub-LVDS interface supports a number of DMD display sizes, and as a

function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With

internal software selection, the DLPC150 also supports a limited number of DMD interface swap configurations

that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface

lines as needed. Table 9 shows the four options available for the DLP2010 or DLP2010NIR (0.2-inch WVGA)

DMD. Any unused DMD signal pairs should be left unconnected on the final board design.

Table 9. DLP2010 or DLP2010NIR (0.2-Inch WVGA) DMD – Controller to 4-Lane DMD Pin Mapping

Options

DLPC150 CONTROLLER 4 LANE DMD ROUTING OPTIONS

DMD PINS

OPTION 1

OPTION 2

OPTION 3

OPTION 4

SWAP CONTROL = x0

SWAP CONTROl = x2

SWAP CONTROL = x1

SWAP CONTROL = x3

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_H_P

HS_WDATA_H_N

HS_WDATA_A_P

HS_WDATA_A_N

Input DATA_p_0

Input DATA_n_0

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_G_P

HS_WDATA_G_N

HS_WDATA_B_P

HS_WDATA_B_N

Input DATA_p_1

Input DATA_n_1

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_B_P

HS_WDATA_B_N

HS_WDATA_G_P

HS_WDATA_G_N

Input DATA_p_2

Input DATA_n_2

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_A_P

HS_WDATA_A_N

HS_WDATA_H_P

HS_WDATA_H_N

Input DATA_p_3

Input DATA_n_3

(1) The flash supply voltage must match VCC_FLSH on the DLPC150. Special attention needs to be paid when ordering devices to be sure

the desired supply voltage is attained as multiple voltage options are often available under the same base part number.

(2) Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be

DLPC150 compatible.

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532-MHz sub-LVDS DDR (High Speed)

DMD_HS_WDATA_A_N

DMD_HS_WDATA_A_P

Leave Open for .2

WVGA DMD

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

Leave Open for .2

WVGA DMD

Sub-LVDS-DMD

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

DLP2010NIR

or

DLP2010

0.2 WVGA

854 x 480 display

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

DLPC150

Controller

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

Leave Open for .2

WVGA DMD

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

Leave Open for .2

WVGA DMD

DMD_LS_CLK

DMD_LS_WDATA

DMD_DEN_ARSTZ

DMD_LS_RDATA

120-MHz SDR (Low Speed)

Figure 11. DLP2010 Or DLP2010NIR (0.2-Inch WVGA) DMD Interface Example (Mapping Option 1 Shown)

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8.3.6 Calibration And Debug Support

The DLPC150 contains a test point output port, TSTPT_(7:0), which provides selected system calibration support

as well as controller debug support. These test points are inputs while reset is applied and switch to outputs

when reset is released. The state of these signals is sampled upon the release of system reset and the captured

value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown

resistor, thus external pullups must be used to modify the default test configuration. The default configuration

(x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal

operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0).

Pullups on TSTPT_(6:3) are used to configure the controller for a specific mode or option. TI does not

recommend adding pullups to TSTPT_(7:3) because this has adverse affects for normal operation. This external

pullup is only sampled upon a 0-to-1 transition on the RESETZ input, thus changing their configuration after reset

is released will not have any effect until the next time reset is asserted and released. Table 10 defines the test

mode selection for one programmable scenario defined by TSTPT(2:0).

Table 10. Test Mode Selection Scenario Defined By Tstpt(2:0)⁽¹⁾

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT(2:0) CAPTURE VALUE

x000

HI-Z

x010

60 MHz

30 MHz

0.7 to 22.5MHz

HIGH

TSTPT(0)

TSTPT(1)

TSTPT(2)

TSTPT(3)

TSTPT(4)

TSTPT(5)

TSTPT(6)

TSTPT(7)

LOW

HIGH

7.5 MHz

(1) These are only the default output selections. Software can reprogram the selection at any time.

8.3.7 DMD Interface Considerations

The sub-LVDS HS interface waveform quality and timing on the DLPC150 controller is dependent on the total

length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and

how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention

to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup Margin = (DLPC150 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)

Hold-time Margin = (DLPC150 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

(1)

where PCB SI degradation is signal integrity degradation due to PCB affects which includes such things as

Simultaneously Switching Output (SSO) noise, cross-talk and Inter-symbol Interference (ISI) noise. (2)

DLPC150 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding data

sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However,

PCB SI degradation is a more complicated adjustment.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that will satisfy both waveform quality and

timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these

recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements.

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DMD_HS Differential Signals

DMD_LS Signals

Figure 12. DMD Interface Board Stack-Up Details

8.4 Device Functional Modes

DLPC150 has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:

•

When pin PROJ_ON is set high, the DLPA2000 or DLPA2005 applies power to the DMD and the DLPC150.

When pin PROJ_ON is set low, the DLPA2000 or DLPA2005 powers down and only microwatts of power are

consumed.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLPC150 controller couples with DLP2010 or DLP2010NIR DMD to provide a reliable solution for many data

and video display applications. The DMDs are spatial light modulators which reflect incoming light from an

illumination source to one of two positions, with the primary position being into a projection or collection optic.

Each specific application typically requires a system-level optical architecture that integrates the DMD, as well

as, a particular data format to the DLPC150. For example, in a spectroscopy application, the DLP2010NIR DMD

is often combined with a single element detector to replace expensive InGaAs array-based detector designs. In

this application, the DMD acts as a wavelength selector diverting specific wavelengths of light through the

collection optics into the single point detector by setting specific columns of pixel in the "on" position. All other

DMD columns that are "off" divert the unselected wavelengths away from the detector's optical path so as to not

interfere with the selected wavelength measurement. The DLPC150 controls the set of patterns that sequentially

turns columns of pixels "on" or "off" to scan the desired wavelenght spectrum.

Other applications of interest include machine vision systems, spectrometers, skin analysis, medical systems,

material identification, chemical sensing, infrared projection, and compressive sensing.

9.1.1 DLPC150 System Design Consideration – Application Notes

System power regulation: It is acceptable for VDD_PLLD and VDD_PLLM to be derived from the same regulator

as the core VDD, but to minimize the AC noise component they should be filtered as recommended in the PCB

Layout Guidelines For Internal Controller PLL Power.

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9.2 Typical Application

A typical embedded system application using the DLPC150 controller and the DLPC2010NIR is shown in

Figure 13. In this configuration, the DLPC150 controller supports a 24-bit parallel RGB input, typical of LCD

interfaces, from an external source or processor. The DLPC150 controller processes the digital input image and

converts the data into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific

micromirrors to the "on" position, directing light to the detector, while unwanted micromirrors are set to "off"

position, directing light away from the detector. The microprocessor sends binary images to the DLP2010NIR to

steer specific wavelengths of light into the detector. The microprocessor uses an analog-to-digital converter to

sample the signal received by the detector into a digital value. By sequentially selecting different wavelengths of

light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light.

DC_IN

BAT

Charger

2.3 to 5.5 V

Power

Management

1.8 V

1.1 V

Other

Supplies

1.1-V

Reg

VIN

SYSPWR

PROJ_ON

On/Off

VDD

1.8 V

1.8S V

LS_IN

VLED

PROJ_ON

USB

DLPA2000

or

DLPA2005

PROJ_ON

SPI_0

RED

Detector

ADC

4

FLASH

Current

Sense

SPI_1

4

RESETZ

INTZ

FLASH,

SDRAM

Microprocessor

PARKZ

HOST_IRQ

TRIG_IN

Illumination

Optics

BIAS, RST, OFS

3

LED_SEL(2)

CMP_PWM

DLPC150

TRIG_OUT (2)

Keypad

CMP_OUT

Parallel RGB I/F (28)

SD

Card

DLP2010NIR

WVGA

(WVGA

DDR DMD

DMD)

Thermistor

I2C

Sub-LVDS DATA

LPSDR CTRL

1.8S V

1.1 V

VIO

Bluetooth

VCC_INTF

VCC_FLSH

VCORE

Projection

Optics

NIR

Detector

ADC + Ampliﬁer

DLP® Chip Set

Figure 13. Typical Application Diagram

9.2.1 Design Requirements

All applications using the DLP 0.2-inch WVGA chipset require the:

•

DLPC150 controller, and

DLPA2000 or DLPA2005 PMIC, and

DLP2010 or DLP2010NIR DMD

components for operation. The system also requires an external parallel flash memory device loaded with the

DLPC150 configuration and support firmware. DLPC150 does the digital image processing and formats the data

for the DMD. DLPA2000 or DLPA2005 PMIC provides the needed analog functions for the DLPC150 and

DLP2010 or DLP2010NIR. The chipset has several system interfaces and requires some support circuitry. The

following interfaces and support circuitry are required:

•

DLPC150 system interfaces:

–

Control interface

Trigger interface

Input data interface

Illumination interface

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Typical Application (continued)

•

DLPC150 support circuitry and interfaces:

–

Reference clock

PLL

Program memory flash interface

DMD interfaces:

–

DLPC150 to DMD digital data

DLPC150 to DMD control interface

DLPC150 to DMD micromirror reset control interface

9.2.2 Detailed Design Procedure

9.2.2.1 DLPC150 System Interfaces

The 0.2-inch WVGA chipset supports a16-bit or 24-bit parallel RGB interface for image data transfers from

another device. There are two primary output interfaces: illumination driver control interface and sync outputs.

9.2.2.1.1 Control Interface

The 0.2-inch WVGA chipset supports I2C commands through the control interface. The control interface allows

another master processor to send commands to the DLPC150 controller to query system status or perform

realtime operations such as LED driver current settings.

9.2.3 Application Curve

In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light

spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150 controls

individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The

microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital

value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the

microprocessor can then plot a spectral response to the light. This systems allows the measurement of the

collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption

spectrum shown in Figure 14.

Figure 14. Sample DLPC150-Based Spectrometer Output

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10 Power Supply Recommendations

10.1 System Power-Up and Power-Down Sequence

Although the DLPC150 requires an array of power supply voltages, (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is assumed

to be the typical configuration), then there are no restrictions regarding the relative order of power supply

sequencing to avoid damaging the DLPC150. This is true for both power-up and power-down scenarios.

Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is

tied to the 1.1-V VDD supply.

If however VDDLP12 is not tied to the VDD supply, then VDDLP12 must be powered-on after the VDD supply is

powered-on, and powered-off before the VDD supply is powered-off. In addition, if VDDLP12 is not tied to VDD,

then VDDLP12 and VDD supplies must be powered on or powered off within 100 ms of each other.

Although there is no risk of damaging the DLPC150 if the above power sequencing rules are followed, the

following additional power sequencing recommendations must be considered to ensure proper system operation.

•

To ensure that DLPC150 output signal states behave as expected, all DLPC150 I/O supplies must remain

applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is

applied, then the output signal state associated with the inactive I/O supply will go to a high impedance state.

•

Additional power sequencing rules may exist for devices that share the supplies with the DLPC150, and thus

these devices may force additional system power sequencing requirements.

Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be

drawn. This added leakage does not affect normal DLPC150 operation or reliability.

Figure 15 and Figure 16 show the DLPC150 power-up and power-down sequence for both the normal PARK and

fast PARK operations of the DLPC150 controller.

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System Power-Up and Power-Down Sequence (continued)

Figure 15. DLPC150 Power-Up / Proj_on = 0 Initiated Normal Park and Power-Down

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System Power-Up and Power-Down Sequence (continued)

Normal

Power-up

Power-down

Operation

PROJ_ON

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

VDD (1.1 V)

Point at which all supplies reach 95% of

VDD_PLLM/D (1.1 V)

their speciﬁed nominal values.

VDDLP12 (if not tied to VDD)

0 µs

Min

PARKZ must be set high a minimum

VCC18 (1.8 V)

of 0 µs before RESETZ is released to

support auto-initialization.

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements deﬁned

in the DLPA200x speciﬁcation.

0 µs

Max

PARKZ

32 µs Min

PARKZ must be set low a

minimum of 32 µs before any

power is removed (except

PLL_REFCLK may be active

before power is applied.

PLL_REFCLK

VDDLP12), before PLL_REFCLK

is stopped and before RESETZ is

asserted low to allow time for the

DMD mirrors to be parked.

0 µs Min

5 ms Min

RESETZ

500 ms Min

0 µs Min

I2C activity should cease

immediately upon active low

assertion of PARKZ.

I2C (activity)

0 µs

Min

HOST_IRQ

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and DLPC150

oscillator cell dependent).

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the DLPC150 is not ready for

operation, and then is driven low after

initialization is complete.

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ)

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

Figure 16. DLPC150 Power-Up / PARKZ = 0 Initiated Fast Park and Power-Down

10.2 DLPC150 Power-Up Initialization Sequence

It is assumed that an external power monitor will hold the DLPC150 in system reset during power-up. It must do

this by driving RESETZ to a logic low state. It should continue to assert system reset until all controller voltages

have reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this

time, most controller outputs will be driven to an inactive state and all bidirectional signals will be configured as

inputs to avoid contention. controller outputs that are not driven to an inactive state are tri-stated. These include

LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal

descriptions in Pin Configuration and Functions). After power is stable and the PLL_REFCLK_I clock input to the

DLPC150 is stable, then RESETZ should be deactivated (set to a logic high). The DLPC150 then performs a

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DLPC150 Power-Up Initialization Sequence (continued)

power-up initialization routine that first locks its PLL followed by loading self configuration data from the external

flash. Upon release of RESETZ all DLPC150 I/Os will become active. Immediately following the release of

RESETZ, the HOST_IRQ signal will be driven high to indicate that the auto initialization routine is in progress.

However, since a pullup resistor is connected to signal HOST_IRQ, this signal will have already gone high before

the DLPC150 actively drives it high. Upon completion of the auto-initialization routine, the DLPC150 will drive

HOST_IRQ low to indicate the initialization done state of the DLPC150 has been reached.

Note that the host processor can start sending I²C commands after HOST_IRQ goes low.

10.3 DMD Fast Park Control (PARKZ)

The PARKZ signal is defined to be an early warning signal that should alert the controller 40 µs before DC

supply voltages have dropped below specifications in fast PARK operation. This allows the controller time to park

the DMD, ensuring the integrity of future operation. Note that the reference clock should continue to run and

RESETZ should remain deactivated for at least 40 µs after PARKZ has been deactivated (set to a logic low) to

allow the park operation to complete.

10.4 Hot Plug Usage

The DLPC150 provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF). This allows

these inputs to be driven high even when no I/O power is applied. Under this condition, the DLPC150 will not

load the input signal nor draw excessive current that could degrade controller reliability. For example, the I²C bus

from the host to other components would not be affected by powering off VCC_INTF to the DLPC150. TI

recommends weak pullups or pulldowns on signals feeding back to the host to avoid floating inputs.

If the I/O supply (VCC_INTF) is powered off, but the core supply (VDD) is powered on, then the corresponding

input buffer may experience added leakage current, but this does not damage the DLPC150.

10.5 Maximum Signal Transition Time

Unless otherwise noted, 10 ns is the maximum recommended 20 to 80% rise or fall time to avoid input buffer

oscillation. This applies to all DLPC150 input signals. However, the PARKZ input signal includes an additional

small digital filter that ignores any input buffer transitions caused by a slower rise or fall time for up to 150 ns.

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11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Guidelines For Internal Controller PLL Power

The following guidelines are recommended to achieve desired controller performance relative to the internal PLL.

The DLPC150 contains 2 internal PLLs which have dedicated analog supplies (VDD_PLLM , VSS_PLLM,

VDD_PLLD, VSS_PLLD). As a minimum, VDD_PLLx power and VSS_PLLx ground pins should be isolated using

a simple passive filter consisting of two series Ferrites and two shunt capacitors (to widen the spectrum of noise

absorption). It’s recommended that one capacitor be a 0.1µF capacitor and the other be a 0.01µF capacitor. All

four components should be placed as close to the controller as possible but it’s especially important to keep the

leads of the high frequency capacitors as short as possible. Note that both capacitors should be connected

across VDD_PLLM and VSS_PLLM / VDD_PLLD and VSS_PLLD respectfully on the controller side of the

Ferrites.

For the ferrite beads used, their respective characteristics should be as follows:

•

DC resistance less than 0.40 Ω

Impedance at 10 MHz equal to or greater than 180 Ω

Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC150 to both capacitors and

then through the series ferrites to the power source. The power and ground traces should be as short as

possible, parallel to each other, and as close as possible to each other.

Signal VIA

PCB Pad

VIA to Common Analog

Digital Board Power Plane

ASIC Pad

VIA to Common Analog

Digital Board Ground Plane

1

2

3

4

5

A

Signal

VSS

Signal

F

Local

VSS_

PLLM

G

VSS

Decoupling

for the PLL

Digital Supply

GND

FB

PLL_

REF

CLK_I

VDD_

PLLM

VSS_

PLLD

H

J

1.1 V

PWR

PLL_

REF

CLK_O

VDD_

PLLD

Crystal Circuit

VSS

VDD

Figure 17. PLL Filter Layout

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Layout Guidelines (continued)

11.1.2 DLPC150 Reference Clock

The DLPC150 requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply this

reference. For flexibility, the DLPC150 accepts either of two reference clock frequencies (see Table 12), but both

must have a maximum frequency variation of ±200 ppm (including aging, temperature, and trim component

variation). When a crystal is used, several discrete components are also required as shown in Figure 18.

PLL_REFCLK_I

PLL_REFCLK_O

R

FB

R

S

Crystal

C

L2

L1

A. CL = Crystal load capacitance (farads)

B. CL1 = 2 × (CL – Cstray_pll_refclk_i)

C. CL2 = 2 × (CL – Cstray_pll_refclk_o)

D. Where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the

controller pin pll_refclk_i. Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin

associated with the controller pin pll_refclk_o.

Figure 18. Recommended Crystal Oscillator Configuration

11.1.2.1 Recommended Crystal Oscillator Configuration

Table 11. Crystal Port Characteristics

PARAMETER

NOMINAL

1.5

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

1.5

pF

Table 12. Recommended Crystal Configuration⁽¹⁾⁽²⁾

PARAMETER

RECOMMENDED

Parallel resonant

UNIT

Crystal circuit configuration

Crystal type

Fundamental (first harmonic)

24 or 16

Crystal nominal frequency

MHz

PPM

ms

Ω

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

Crystal load

120 max

6

pF

Ω

RS drive resistor (nominal)

RFB feedback resistor (nominal)

CL1 external crystal load capacitor

CL2 external crystal load capacitor

100

1Meg

Ω

See equation in Figure 18 notes

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) Temperature range of –30°C to +85°C.

(2) The crystal bias is determined by the controller's VCC_INTF voltage rail, which is variable (not the VCC18 rail).

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If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC150

DLPC150 controller and the PLL_REFCLK_O pins should be left unconnected.

Table 13. DLPC150 Recommended Crystal Parts⁽¹⁾⁽²⁾

MANUFACTURE

R

PART NUMBER

SPEED

TEMPERATURE

AND AGING

ESR

LOAD CAPACITANCE

KDS

DSX211G-24.000M-8pF-50-50

24 MHz

±50 ppm

120-Ω max

8 pF

(1) Crystal package sizes: 2.0 × 1.6 mm for both crystals.

(2) Operating temperature range: –30°C to +85°C for all crystals.

11.1.3 General PCB Recommendations

TI recommends 1-oz. copper planes in the PCB design to achieve needed thermal connectivity.

11.1.4 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused

DLPC150 controller input pins be tied through a pullup resistor to its associated power supply or a pulldown to

ground. For DLPC150 controller inputs with an internal pullup or pulldown resistors, it is unnecessary to add an

external pullup or pulldown unless specifically recommended. Note that internal pullup and pulldown resistors are

weak and should not be expected to drive the external line. The DLPC150 implements very few internal resistors

and these are noted in the pin list. When external pullup or pulldown resistors are needed for pins that have built-

in weak pullups or pulldowns, use the value 8 kΩ (max).

Unused output-only pins should never be tied directly to power or ground, but can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then they should be

pulled-up (or pulled-down) using an appropriate, dedicated resistor.

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11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 14. Max Pin-to-Pin PCB Interconnect Recommendations⁽¹⁾⁽²⁾

SIGNAL INTERCONNECT TOPOLOGY

DMD BUS SIGNAL

DMD_HS_CLK_P

UNIT

SINGLE BOARD SIGNAL ROUTING

MULTI-BOARD SIGNAL ROUTING

LENGTH

6.0

152.4

inch

(mm)

(3)

See

DMD_HS_CLK_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

6.0

152.4

inch

(mm)

(3)

See

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

6.5

165.1

inch

(mm)

(3)

DMD_LS_CLK

See

6.5

165.1

inch

(mm)

(3)

DMD_LS_WDATA

DMD_LS_RDATA

DMD_DEN_ARSTZ

See

6.5

165.1

inch

(mm)

(3)

See

7.0

177.8

inch

(mm)

(3)

See

(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to board variations, these are impossible to define. Any board designs should SPICE simulate with the DLPC150 controller IBIS

models to ensure single routing lengths do not exceed requirements.

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Table 15. High Speed PCB Signal Routing Matching Requirements^(1)(2)(3)(4)

SIGNAL GROUP LENGTH MATCHING

REFERENCE SIGNAL

INTERFACE

SIGNAL GROUP

MAX MISMATCH⁽⁵⁾

UNIT

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_CLK_P

DMD_HS_CLK_N

±0.1

(±25.4)

inch

(mm)

DMD

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_LS_WDATA

DMD_LS_RDATA

±0.2

(±5.08)

inch

(mm)

DMD

DMD_LS_CLK

N/A

inch

(mm)

DMD_DEN_ARSTZ

N/A

(1) These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC150, the

DMD.

(2) DMD HS data lines are differential, thus these specifications are pair-to-pair.

(3) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.

(4) DMD LS signals are single ended.

(5) Mismatch variance applies to high-speed data pairs. For all high-speed data pairs, the maximum mismatch between pairs should be 1

mm or less.

11.1.6 Number of Layer Changes

•

Single-ended signals: Minimize the number of layer changes.

Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair

should not change layers.

11.1.7 Stubs

Stubs should be avoided.

•

11.1.8 Terminations

•

No external termination resistors are required on DMD_HS differential signals.

The DMD_LS_CLK and DMD_LS_WDATA signal paths should include a 43-Ω series termination resistor

located as close as possible to the corresponding DLPC150 controller pins.

•

The DMD_LS_RDATA signal path should include a 43-Ω series termination resistor located as close as

possible to the corresponding DMD pin.

DMD_DEN_ARSTZ does not require a series resistor.

11.1.9 Routing Vias

•

The number of vias on DMD_HS signals should be minimized and should not exceed two.

Any and all vias on DMD_HS signals should be located as close to the DLPC150 controller as possible.

The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be minimized and not

exceed two.

•

Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be located as close to the

DLPC150 controller as possible.

45

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

11.2 Layout Example

Figure 19. Board Layout Example

11.3 Thermal Considerations

The underlying thermal limitation for the DLPC150 is that the maximum operating junction temperature (T_J) not

be exceeded (this is defined in the Recommended Operating Conditions). This temperature is dependent on

operating ambient temperature, airflow, PCB design (including the component layout density and the amount of

copper used), power dissipation of the DLPC150, and power dissipation of surrounding components. The

DLPC150’s package is designed primarily to extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

The recommended maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC150 power dissipation and R_θJAat 0 m/s of forced airflow, where R_θJAis the thermal

resistance of the package as measured using a glater test PCB with two, 1-oz power planes. This JEDEC test

PCB is not necessarily representative of the DLPC150 PCB; the reported thermal resistance may not be

accurate in the actual product application. Although the actual thermal resistance may be different, it is the best

information available during the design phase to estimate thermal performance. However, after the PCB is

designed and the product is built, TI highly recommends that thermal performance be measured and validated.

To do this, measure the top center case temperature under the worse case product scenario (max power

dissipation, max voltage, max ambient temperature) and validated not to exceed the maximum recommended

case temperature (T_C). This specification is based on the measured φ_JTfor the DLPC150 package and provides

a relatively accurate correlation to junction temperature. Take care when measuring this case temperature to

prevent accidental cooling of the package surface. TI recommends a small (approximately 40 gauge)

thermocouple. The bead and thermocouple wire should contact the top of the package and be covered with a

minimal amount of thermally conductive epoxy. The wires should be routed closely along the package and the

board surface to avoid cooling the bead through the wires.

46

DLPC150

www.ti.com.cn

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

12.1.1.1 器件标记

DLPC150

DLPC150ZEZ

标记定义：

第 1 行：

DLP 器件名称：DLPC150

SC：焊锡球成分

e1：表示含 SnAgCu 的无铅焊锡球

G8：表示含 SnAgCu 的无铅焊锡球，其中银含量

小于等于 1.5%，模压混合物满足德州仪器 (TI) 的绿色定义。

第 2 行：

第 3 行：

第 4 行：

第 5 行：

TI 部件号

XXXXXXXX-TT 制造商部件号

LLLLLLLL.ZZ 半导体晶圆的铸造批次代码以及无铅焊锡球标记

PH YYWW：封装组件信息

47

DLPC150

ZHCSDJ3C –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

12.2 相关链接

下面的表格中列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品

的快速链接。

表 16. 相关链接

器件

产品文件夹

请单击此处

单击此处

样片和购买

请单击此处

单击此处

技术文档

请单击此处

单击此处

工具与软件

请单击此处

单击此处

支持和社区

请单击此处

单击此处

DLP2010NIR

DLP2010

DLPA2000

DLPA2005

请单击此处

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 "机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

48

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OUTLINE

ZEZ0201A

NFBGA - 1 mm max height

SCALE 1.000

PLASTIC BALL GRID ARRAY

13.1

12.9

A

B

BALL A1 CORNER

13.1

12.9

1 MAX

C

SEATING PLANE

0.1 C

0.31

0.21

BALL TYP

TYP

11.2 TYP

SYMM

(0.9) TYP

R

P

N

M

L

K

J

(0.9) TYP

SYMM

11.2

TYP

H

G

F

0.4

201X

E

D

C

0.3

0.15

0.08

C A

C

B

A

1

2

5 6

3 7 9 10 11 12 13 14 15

4

8

0.8 TYP

BALL A1 CORNER

4221521/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

201X ( 0.4)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221521/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

3

4

5

6

8

9

13 14 15

7

10 11 12

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221521/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	DLPC150
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP2010NIR DMD 的数字控制器控制器
文件：	总54页 (文件大小：2287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC150 [TI]

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