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DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

适用于 DLP553x-Q1 芯片组的 DLPC230-Q1 汽车用 DMD 控制器

1 特性

2 应用

1

•

符合汽车类应用的要求

•

宽视野和增强现实

抬头显示屏 (HUD)

•

具有符合 AEC-Q100 标准的下列特性：中

•

高分辨率前照灯

–

器件温度等级 2 级：环境工作温度范围为

–40°C 至 105°C

3 说明

–

器件 HBM ESD 分类等级 2

汽车用 DLPC230-Q1 应用 DMD 显示屏控制器是两种

DMD 芯片组：DLP5530-Q1（内部显示屏应用，例如

HUD）和 DLP5531-Q1（外部照明应用，例如高分辨

率前照灯）的组成部分。两种芯片组均包含 0.55 英寸

DMD 和 TPS99000-Q1 系统管理和照明控制器。

DLPC230-Q1 集成了具备错误代码校正 (SECDED

ECC) 功能的嵌入式处理器，支持主机控制和实时反

馈、片上诊断和系统监控。还包括片上 SRAM，无需

外部 DRAM。DLPC230-Q1 与 TPS99000-Q1 结合使

用，可支持 HUD 应用超过 5000:1 的高动态范围调

光。Sub-LVDS 600MHz DMD 接口支持高 DMD 刷新

率，以无缝生成优质数字图像，同时降低辐射发射。

器件 CDM ESD 分类等级 C4B

•

DMD 显示控制器支持：

–

DLP5530-Q1 汽车内部显示屏芯片组

DLP5531-Q1 汽车外部照明芯片组

视频处理

–

扩展输入图像以匹配 DMD 分辨率

边框调整：垂直图像位置 ±50%，水平图像位置

±10%，降低了机械对齐 (HUD) 需求

–

支持两倍或四倍像素，以允许低分辨率视频输入

伽马校正

•

具备错误矫正 (ECC) 功能的嵌入式处理器

–

片上诊断和自检能力

器件信息⁽¹⁾

系统诊断包括温度监控、器件接口监控和光电二

极管监控

器件型号

封装

封装尺寸（标称值）

–

集成平滑调光管理

DLPC230-Q1

BGA (324)

23.00mm x 23.00mm

可配置 GPIO

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

•

无需外部 RAM，内部 SRAM 可用于图像处理

600MHz Sub-LVDS DMD 接口，以实现低功率和

低排放

DLP553x-Q1 DLP^®芯片组系统方框图

•

扩频计时，以降低 EMI

Control &

Monitor

TPS99000-Q1

Power

Regulation

VBATT

PROJ_ON

视频输入接口

1.1V

1.8V

3.3V

6.5V

Power sequencing

and monitoring

–

高达 110MHz 的单 OpenLDI (FPD-Link I) 端口

Reset &

Power Good

External

Monitor

SPI

高达 110MHz 的 24 位 RGB 并行接口中的并

行接口最大像素时钟，并进行了水平边框调整

System Diagnostics:

external watchdogs,

over brightness, and

other monitors

DLPC230-Q1

I²C

•

可配置主机控制接口

Host

SPI

6.5V

SPI

Internal

Control

–

串行外设接口 (SPI) 10MHz

Ultra wide

dimming LED

Controller

2-TIA, 12bit ADC

DAC, FET Drive, ...

LED

drive

HOST

IRQ

LED

Control

I²C (400kHz)

MPU

Illumination

Control

& feedback

FET

Drive

F

E

T

s

主机 IRQ 信号，用于针对重大系统错误提供实

时反馈

DMD Power

Regulation

OpenLDI

Image Scaling &

Bezel

adjustment

24-bit RGB

& Syncs

GPIO

(configurable)

TPS99000-Q1 系统管理和照明控制器接口

Photodiode

DMD Power

eSRAM

frame buffer

Sub-LVDS

TMP411

DLP553X-Q1

Flash

SPI

0.55 s450

1.3MP DMD

I²

C

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS054

DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

www.ti.com.cn

6.20 TPS99000-Q1 AD3 Interface Timing

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications....................................................... 15

6.1 Absolute Maximum Ratings .................................... 15

6.2 ESD Ratings............................................................ 15

6.3 Recommended Operating Conditions..................... 16

6.4 Thermal Information................................................ 16

6.5 Electrical Characteristics......................................... 17

6.6 Electrical Characteristics for Fixed Voltage I/O ...... 18

Requirements........................................................... 33

6.21 Master I²C Port Interface Timing Requirements... 34

6.22 Chipset Component Usage Specification ............. 34

Parameter Measurement Information ................ 35

7.1 HOST_IRQ Usage Model ....................................... 35

7.2 Input Source............................................................ 35

Detailed Description ............................................ 37

8.1 Overview ................................................................. 37

8.2 Functional Block Diagram ....................................... 37

8.3 Feature Description................................................. 37

8.4 Device Functional Modes........................................ 50

Application and Implementation ........................ 51

9.1 Application Information............................................ 51

9.2 Typical Application .................................................. 52

7

8

9

6.7 DMD High-Speed Sub-LVDS Electrical

Characteristics ......................................................... 20

6.8 DMD Low-Speed Sub-LVDS Electrical

Characteristics ......................................................... 21

10 Power Supply Recommendations ..................... 56

10.1 Power Supply Management.................................. 56

10.2 Hot Plug Usage..................................................... 56

10.3 Power Supply Filtering.......................................... 56

11 Layout................................................................... 57

11.1 Layout Guidelines ................................................. 57

11.2 Thermal Considerations........................................ 65

12 器件和文档支持 ..................................................... 66

12.1 器件支持 ............................................................... 66

12.2 商标....................................................................... 67

12.3 静电放电警告......................................................... 67

12.4 术语表 ................................................................... 67

13 机械、封装和可订购信息....................................... 67

13.1 DLPC230-Q1 机械数据 ......................................... 68

6.9 OpenLDI LVDS Electrical Characteristics............... 22

6.10 Power Dissipation Characterisics ......................... 22

6.11 System Oscillators Timing Requirements ............ 22

6.12 Power Supply and Reset Timing Requirements... 23

6.13 Parallel Interface General Timing Requirements.. 24

6.14 OpenLDI Interface General Timing Requirements 25

6.15 Parallel/OpenLDI Interface Frame Timing

Requirements........................................................... 26

6.16 Host/Diagnostic Port SPI Interface Timing

Requirements........................................................... 28

6.17 Host/Diagnostic Port I²C Interface Timing

Requirements........................................................... 28

6.18 Flash Interface Timing Requirements................... 29

6.19 TPS99000-Q1 SPI Interface Timing

Requirements........................................................... 31

4 修订历史记录

Changes from Revision D (May 2018) to Revision E

Page

•

已更改将器件状态从“预告信息”更改为“生产数据”.................................................................................................................. 1

2

DLPC230-Q1

www.ti.com.cn

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

5 Pin Configuration and Functions

ZDQ Package

324-Pin BGA

Top View

Note that there is one VCCK power ball located in the thermal ball array.

Pin Functions – Board Level Test, Debug, and Initialization

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

Active low power-on reset for the DLPC230-Q1. A low-to-high transition starts

self-configuration and initialization of the ASIC.

('0' = Reset, '1' = Normal Operation)

All ASIC power and input clocks must be stable before this reset is de-asserted

high.

The signals listed below should be forced low by external pull-down, and will then

be driven low as the power supplies stabilize with RESETZ asserted.

PMIC_LEDSEL_0, PMIC_LEDSEL_1, PMIC_LEDSEL_2, PMIC_LEDSEL_3,

DMD_DEN_ARSTZ, PMIC_AD3_CLK, and PMIC_AD3_MOSI

All other bi-directional and output signals will be tri-stated while reset is asserted.

External pull-ups or pull-downs must be added where necessary to protect

external devices that would typically be driven by the ASIC to prevent device

malfunction.

RESETZ

F3

I₇

This pin includes hysteresis.

Specific timing requirements for this signal are shown in Power Supply and Reset

Timing Requirements.

(1) See Table 1 for more information on I/O definitions.

3

DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

www.ti.com.cn

Pin Functions – Board Level Test, Debug, and Initialization (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

DMD Park Control

('0' = Park, '1' = Un-Park)

The TI TPS99000-Q1 device is used to control this signal. As part of this function,

it monitors power to the DLPC230-Q1 watching for an imminent power loss

condition, upon which it will drive the PMIC_PARKZ signal accordingly. The

specific timing requirements for this signal are shown in Power Supply and Reset

Timing Requirements.

PMIC_PARKZ

E3

I₇

Selects which input interface port will be used for Host Command and Control.

The port that is not selected as the Host Command and Control port will be

available as a Diagnostic Processor monitoring port.

('0' = Host SPI, '1' = Host I²C)

This pin includes a weak internal pull-down. If a pull-up is used to obtain a '1'

value, the pull-up value must be ≤ 8 kΩ.

HOST_IF_SEL

R4

B_13,14

Tri-stated while RESETZ is asserted low, and is sampled as a host directive

approximately 1.5 µs after RESETZ is de-asserted. It may be driven as an output

for TI debug use after sampling.

Selects the SPI mode (clock phase and polarity) that will be used with the HOST

SPI interface. This value is applicable regardless of whether the Host SPI

interface is used for Host Command and Control, or for the Diagnostic Processor

monitoring port.

('0' = SPI Mode 0 or 3, '1' = SPI Mode 1 or 2)

This pin includes a weak internal pull-down. If a pull-up is used to obtain a '1'

value, the pull-up value must be ≤ 8 kΩ.

Tri-stated while RESETZ is asserted low, and is sampled as a host directive

approximately 1.5 µs after RESETZ is de-asserted. It may be driven as an output

for TI debug use after sampling.

HOST_SPI_MODE

RTPPUB_ENZ

V1

B_13,14

AA3

AB3

TI internal use. Must be left unconnected. Includes a weak pull-down.

Selects whether the Host will use 8-bit CRC or Checksum on the Host Command

and Control interface. This value is only applicable for the Host Command and

Control interface. The value for the Diagnostic Processor monitoring port will be

specified in Flash.

('0' = 8-bit CRC, '1' = 8-bit Checksum)

This pin includes a weak internal pull-down. If a pull-up is used to obtain a '1'

value, the pull-up value must be ≤ 8 kΩ.

CRCZ_CHKSUM_SEL

Tri-stated while RESETZ is asserted low, and is sampled as a host directive

approximately 1.5 µs after RESETZ is de-asserted. It may be driven as an output

for TI debug use after sampling.

ETM_TRACECLK

ETM_TRACECTL

AB6

AB7

O₁₃

TI internal use. Must be left unconnected. (Clock for Trace Debug)

TI internal use. Must be left unconnected. (Control for Trace Debug)

Test pin 0 / STAY-IN-BOOT:

Selects whether the system should stay in the Boot Application, or proceed with

the normal load of the Main Application.

('0' = Load Main Application, '1' = Stay in Boot Application)

This pin includes a weak internal pull-down. If a pull-up is being used to obtain a

'1' value, the pull-up value must be ≤ 8 kΩ.

TSTPT_0

Y4

B_13,14

Tri-stated while RESETZ is asserted low, and is sampled as a host directive

approximately 1.5 µs after RESETZ is de-asserted. It may be driven as an output

for debug use after sampling as described in Debug Support.

Test pin 1:

This pin must be externally pulled down, left open or unconnected. Includes a

weak pull-down.

It may be driven as an output for debug use as described in Debug Support.

TSTPT_1

TSTPT_2

TSTPT_3

AA4

Y5

B_13,14

Test pin 2:

This pin must be externally pulled down, left open or unconnected. Includes a

weak pull-down.

It may be driven as an output for debug use as described in Debug Support.

Test pin 3:

This pin must be externally pulled down, left open or unconnected. Includes a

weak pull-down.

AA5

It may be driven as an output for debug use as described in Debug Support.

4

DLPC230-Q1

www.ti.com.cn

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Pin Functions – Board Level Test, Debug, and Initialization (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

Test pin 4:

This pin must be externally pulled down, left open or unconnected. Includes a

weak pull-down.

TSTPT_4

Y6

B_13,14

It may be driven as an output for debug use as described in Debug Support.

Test pin 5 / Spread Spectrum Disable:

Selects whether spread spectrum flash settings are used or whether spread

spectrum clocking will be disabled.

('0' = Spread Spectrum Disabled, '1' = Use flash Spread Spectrum settings)

This pin includes a weak internal pull-down. If a pull-up is being used to obtain a

'1' value, the pull-up value must be ≤ 8 kΩ.

This signal is tri-stated while RESETZ is asserted low, and is sampled as a host

directive approximately 1.5 µs after RESETZ is de-asserted. It may be driven as

an output for debug use after sampling as described in Debug Support.

TSTPT_5

TSTPT_6

AA6

B_13,14

Test pin 6:

An external pull-up resistor must be used (≤ 8 kΩ since pin includes a weak pull-

down).

This signal is tri-stated while RESETZ is asserted low, and is sampled as a host

directive approximately 1.5 µs after RESETZ is de-asserted. It may be driven as

an output for debug use after sampling as described in Debug Support.

Y7

B_13,14

Test pin 7:

This pin must be externally pulled down, left open or unconnected. Includes a

weak pull-down.

It may be driven as an output for debug use as described in Debug Support.

TSTPT_7

AA7

H3

B_13,14

Manufacturing test enable signal.

This signal must be connected directly to ground on the PCB.

Includes weak internal pull-down and hysteresis.

HWTEST_EN

I₁₄

JTAG Serial Data Clock

Includes a weak internal pull-up.

JTAGTCK

G22

G21

I₁₁

JTAG Test Mode Select

Includes weak internal pull-up.

JTAGTMS1

JTAG Reset

Includes a weak internal pull-up and Hysteresis.

For normal operation, this pin must be pulled to ground through an external 8 kΩ

or less resistor. Failure to pull this pin low during normal operation will

cause start-up and initialization problems.

JTAGTRSTZ

L20

I₁₁

For JTAG Boundary Scan, this pin must be pulled-up or left disconnected.

JTAGTDI

K20

J20

I₁₁

JTAG Serial Data In Includes a weak internal pull-up.

JTAG Serial Data Out

Includes weak internal pull-up.

JTAGTDO1

B_10,11

This pin must be left open or unconnected.

Includes a weak internal pull-up.

JTAGTDO2

JTAGTDO3

JTAGTMS2

H20

G20

N20

B_10,11

I₁₁

This pin must be left open or unconnected. Includes a weak internal pull-up.

This pin must be left open or unconnected. Includes a weak internal pull-up. See

Debug Support for important debug access considerations.

This pin must be left open or unconnected. Includes a weak internal pull-up. See

Debug Support for important debug access considerations.

JTAGTMS3

M20

I₁₁

5

DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

www.ti.com.cn

Pin Functions – Parallel Port Input Data and Control⁽¹⁾

DESCRIPTION

PARALLEL RGB MODE

I/O⁽²⁾

NAME

PCLK

NUMBER

R22

I₁₁

Pixel clock

Vsync⁽³⁾

Hsync⁽³⁾

VSYNC

HSYNC

DATEN

H21

H22

P21

Data Valid

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

AA21

AA22

Y21

W21

Y22

V21

W22

U21

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

I₁₁

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

V22

T21

U22

R21

T22

P22

N21

N22

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

M22

M21

L22

L21

K22

K21

J22

J21

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

(1) Unused inputs should be grounded or pulled down to ground through an external resistor (≤ 10 kΩ).

(2) See Table 1 for more information on I/O definitions.

(3) VSYNC and HSYNC polarity are software programmable.

6

DLPC230-Q1

www.ti.com.cn

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Pin Functions – OpenLDI Ports Input Data and Control⁽¹⁾⁽²⁾

I/O⁽³⁾

DESCRIPTION

NAME

NUMBER

L1_CLK_P

L1_CLK_N

AB11

AA11

I₁₈

OpenLDI (FPD Link I) Port 1 Clock Lane

L1_DATA0_P

L1_DATA0_N

L1_DATA1_P

L1_DATA1_N

L1_DATA2_P

L1_DATA2_N

L1_DATA3_P

L1_DATA3_N

AB9

AA9

AB10

AA10

AB12

AA12

AB13

AA13

OpenLDI (FPD Link I) Port 1 Data Lanes: Intra-port data lane swapping can be done

on a product configuration basis to support board considerations.

I₁₈

L2_CLK_P

L2_CLK_N

AB17

AA17

OpenLDI (FPD Link I) Port 2 Clock Lane

L2_DATA0_P

L2_DATA0_N

L2_DATA1_P

L2_DATA1_N

L2_DATA2_P

L2_DATA2_N

L2_DATA3_P

L2_DATA3_N

AB15

AA15

AB16

AA16

AB18

AA18

AB19

AA19

OpenLDI (FPD Link I) Port 2 Data Lanes: Intra-port data lane swapping can be done

on a product configuration basis to support board considerations.

(1) The system only supports the operational use of one port. As two ports are available, the host can select which port they wish to be

active (to optimize board routing as an example).

(2) The inputs for any un-used port(s) should be left unconnected, and will be powered down by the system.

(3) See Table 1 for more information on I/O definitions.

7

DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

www.ti.com.cn

Pin Functions – DMD Reset and Bias Control Interfaces⁽¹⁾⁽²⁾

I/O⁽³⁾

DESCRIPTION

NAME

NUMBER

DMD driver enable signal

('1' = Enabled, '0' = Reset)

This signal will be driven low after the DMD is parked and before power is removed

from the DMD. If the 1.8-V power to the DLPC230-Q1 is independent of the 1.8-V

power to the DMD, then an external pull-down resistor (≤ 2.2 kΩ) must be used to

hold the signal low in the event DLPC230-Q1 power is inactive while DMD power is

applied.

DMD_DEN_ARSTZ

D11

O₁

DMD_LS0_CLK

C11

C10

C9

O₂

I₃

TI internal use. Must be left unconnected.

DMD, low-speed single-ended serial read data

DMD_LS0_WDATA

DMD_LS0_RDATA

DMD, low-speed single-ended serial read data (Training data response for second

port of DMD)

DMD_LS1_RDATA

C8

I₃

DMD_LS0_CLK_P

DMD_LS0_CLK_N

B12

A12

O₄

DMD low-speed differential interface clock

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

B11

A11

DMD low-speed differential interface write data

(1) The low-speed write control interface to the DMD is differential.

(2) All control interface reads will make use of the single-ended low-speed signals. The read data will be clocked by the write clock.

(3) See Table 1 for more information on I/O definitions.

Pin Functions – DMD Sub-LVDS Interfaces

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

DMD_HS0_CLK_P

DMD_HS0_CLK_N

B17

A17

O₄

DMD high-speed interface, Port 0 Clock Lane.

DMD_HS0_WDATA0_P

DMD_HS0_WDATA0_N

DMD_HS0_WDATA1_P

DMD_HS0_WDATA1_N

DMD_HS0_WDATA2_P

DMD_HS0_WDATA2_N

DMD_HS0_WDATA3_P

DMD_HS0_WDATA3_N

DMD_HS0_WDATA4_P

DMD_HS0_WDATA4_N

DMD_HS0_WDATA5_P

DMD_HS0_WDATA5_N

DMD_HS0_WDATA6_P

DMD_HS0_WDATA6_N

DMD_HS0_WDATA7_P

DMD_HS0_WDATA7_N

B21

A21

B20

A20

B19

A19

B18

A18

B16

A16

B15

A15

B14

A14

B13

A13

DMD high-speed interface, Port 0 Data Lanes: The true numbering and

application of the DMD_HS_DATA pins are software configuration dependent

as discussed in DMD (Sub-LVDS) Interface.

O₄

DMD_HS1_CLK_P

DMD_HS1_CLK_N

B6

A6

DMD high-speed interface, Port 1 Clock Lane.

DMD_HS1_WDATA0_P

DMD_HS1_WDATA0_N

DMD_HS1_WDATA1_P

DMD_HS1_WDATA1_N

DMD_HS1_WDATA2_P

DMD_HS1_WDATA2_N

DMD_HS1_WDATA3_P

DMD_HS1_WDATA3_N

DMD_HS1_WDATA4_P

DMD_HS1_WDATA4_N

DMD_HS1_WDATA5_P

DMD_HS1_WDATA5_N

DMD_HS1_WDATA6_P

DMD_HS1_WDATA6_N

DMD_HS1_WDATA7_P

DMD_HS1_WDATA7_N

B2

A2

B3

A3

B4

A4

B5

A5

B7

A7

B8

A8

B9

A9

B10

A10

DMD high-speed interface, Port 1 Data Lanes: The true numbering and

application of the DMD_HS_DATA pins are software configuration dependent

as discussed in DMD (Sub-LVDS) Interface.

(1) See Table 1 for more information on I/O definitions.

8

DLPC230-Q1

www.ti.com.cn

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Pin Functions – Peripheral Interfaces

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

Host interrupt (output active HIGH)

This signal is used to indicate that the DLPC230-Q1 has detected a serious error for which

the ASIC has initiated an Emergency Shutdown. This is discussed further in HOST_IRQ

Usage Model.

HOST_IRQ⁽²⁾

T20

O₁₀

The DLPC230-Q1 tri-states this output during reset. An external pull-down (≤ 10 kΩ) is

required to drive this signal to its inactive state.

I²C Port (Slave), Host Command and Control to ASIC, SCL (bidirectional, open-drain): An

external pull-up is required.

HOST_IIC_SCL

R20

B₁₂

I²C Port (Slave), Host Command and Control to ASIC, SDA. (bidirectional, open-drain): An

external pull-up is required.

HOST_IIC_SDA

HOST_SPI_CLK

P20

Y20

B₁₂

I₁₁

SPI Port (Slave), Host Command and Control to ASIC, clock

SPI Port (Slave), Host Command and Control to ASIC, chip select (active low input)

An external pull-up resistor (≤ 2.2 kΩ) is required to avoid a floating chip select input to the

ASIC

HOST_SPI_CSZ

W20

I₁₁

HOST_SPI_DIN

V20

U20

I₁₁

SPI Port (Slave), Host Command and Control to ASIC, receive data in

SPI Port (Slave), Host Command and Control to ASIC, transmit data out

HOST_SPI_DOUT

O₁₀

SPI Port (Master), Control Interface to Flash device, chip select (active low output)

An external pullup resistor (≤ 10 kΩ) is required to avoid a floating chip select input to the

Flash

FLSH_SPI_CSZ

Y1

O₈

FLSH_SPI_CLK

W1

V2

O₈

SPI Port (Master), Control Interface to Flash device, clock

SPI Port (Master), Control Interface to Flash device, transmit and receive data

An external pullup resistor (≤ 10 kΩ) is required

FLSH_SPI_DIO_0

B_8,9

SPI Port (Master), Control Interface to Flash device, transmit and receive data

An external pullup resistor (≤ 10 kΩ) is required

FLSH_SPI_DIO_1

FLSH_SPI_DIO_2

FLSH_SPI_DIO_3

W2

Y2

B_8,9

SPI Port (Master), Control Interface to Flash device, transmit and receive data

An external pullup resistor (≤ 3.3 kΩ) is required

SPI Port (Master), Control Interface to Flash device, transmit and receive data

An external pullup resistor (≤ 3.3 kΩ) is required

W3

TPS99000-Q1 interrupt (input with hysteresis)

The ASIC provides a weak internal pull-up

PMIC_INTZ⁽²⁾

G3

E1

I₇

PMIC_SPI_CLK

O₆

SPI Port (Master), General Control Interface to TPS99000-Q1, clock

SPI Port (Master), General Control Interface to TPS99000-Q1, chip select 0 (active low

output)

An external pullup resistor (≤ 10 kΩ) must be used to avoid floating chip select inputs to the

external SPI device during ASIC reset assertion.

PMIC_SPI_CSZ0

E2

O₆

PMIC_SPI_DIN

F1

D1

I₇

SPI Port (Master), General Control Interface to TPS99000-Q1, receive data in

SPI Port (Master), General Control Interface to TPS99000-Q1, transmit data out

PMIC_SPI_DOUT

O₆

Sequencer Clock / TPS99000-Q1 primary system clock

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled behavior during

ASIC reset assertion.

PMIC_AD3_CLK

PMIC_AD3_MISO

PMIC_AD3_MOSI

H2

J2

J1

O₂₀

I₁₄

Measurement control interface to TPS99000-Q1, receive data in

Measurement control interface to TPS99000-Q1, transmit data out

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled behavior during

ASIC reset assertion.

O₂₀

LED Control Interface to TPS99000-Q1

PMIC_LEDSEL_0

PMIC_LEDSEL_1

PMIC_LEDSEL_2

F2

G1

G2

O₆

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled illumination

during ASIC reset assertion.

LED Control Interface to TPS99000-Q1

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled illumination

during ASIC reset assertion.

LED Control Interface to TPS99000-Q1

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled illumination

during ASIC reset assertion.

(1) See Table 1 for more information on I/O definitions.

(2) For more information about usage, see HOST_IRQ Usage Model.

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Pin Functions – Peripheral Interfaces (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

LED Control Interface to TPS99000-Q1

PMIC_LEDSEL_3

MSTR_SDA

H1

O₆

An external pull-down resistor (≤ 10 kΩ) must be used to avoid uncontrolled illumination

during ASIC reset assertion.

I²C Port (Master), SDA. (bidirectional, open-drain)

An external pull-up is required. Typical use of the Master I²C port is communication with

temperature sensing devices and an optional EEPROM. The Master I²C I/Os are powered by

VCC3IO (3.3 V only).

AB5

AB4

B₁₅

I²C Port (Master), SCL. (bidirectional, open-drain)

An external pull-up is required. Typical use of the Master I²C port is communication with

temperature sensing devices and an optional EEPROM. The Master I²C I/Os are powered by

VCC3IO (3.3 V only).

MSTR_SCL

B₁₅

10

DLPC230-Q1

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Pin Functions – GPIO Peripheral Interface⁽¹⁾⁽²⁾

I/O⁽³⁾

DESCRIPTION

NAME

NUMBER

D22

E21

E22

F20

F21

F22

V3

GPIO_31

GPIO_30

GPIO_29

GPIO_28

GPIO_27

GPIO_26

GPIO_25

GPIO_24

GPIO_23

GPIO_22

GPIO_21

GPIO_20

GPIO_19

GPIO_18

GPIO_17

GPIO_16

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

GPIO_09

GPIO_08

GPIO_07

GPIO_06

GPIO_05

GPIO_04

GPIO_03

GPIO_02

GPIO_01

GPIO_00

B_20,14

General purpose I/O 31

General purpose I/O 30

General purpose I/O 29

General purpose I/O 28

General purpose I/O 27

General purpose I/O 26

General purpose I/O 25

General purpose I/O 24

General purpose I/O 23

General purpose I/O 22

General purpose I/O 21

General purpose I/O 20

General purpose I/O 19

General purpose I/O 18

General purpose I/O 17

General purpose I/O 16

General purpose I/O 15

General purpose I/O 14

General purpose I/O 13

General purpose I/O 12

General purpose I/O 11

General purpose I/O 10

General purpose I/O 09

General purpose I/O 08

General purpose I/O 07

General purpose I/O 06

General purpose I/O 05

General purpose I/O 04

General purpose I/O 03

General purpose I/O 02

General purpose I/O 01

General purpose I/O 00

U3

U2

U1

T3

T2

T1

R3

R2

R1

P3

P2

P1

N3

N2

N1

M3

M2

M1

L3

L2

L1

K3

K2

K1

J3

(1) Some GPIO signals are reserved for specific purposes. These signals vary per product configuration. These product allocations are

discussed further in GPIO Supported Functionality. All GPIO that are available for Host use must be configured as an input, a standard

output, or an open-drain output. This is set in the flash configuration or by command using the Host command interface. The reset

default for all GPIO is as an input signal. An external pull-up (≤ 10 kΩ) is required for each signal configured as open-drain.

(2) All GPIO include hysteresis.

(3) See Table 1 for more information on I/O definitions.

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Pin Functions – Clock and PLL Support

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

Reference clock crystal input. If an external oscillator is used in place of a crystal, this pin

should be left unconnected (floating with no added capacitive load).

PLL_REFCLK_I

PLL_REFCLK_O

D15

I₁₇

Reference clock crystal return. If an external oscillator is used in place of a crystal, this pin

must be used for the oscillator input.

D14

B_16,17

Selects whether an external crystal or external oscillator will be used to drive the internal

PLL.

OSC_BYPASS

D16

I₁₉

('0' = Crystal, '1' = Oscillator)

This pin includes a weak internal pull-down. If a pull-up is being used to obtain a '1' value,

the pull-up value must be ≤ 8 kΩ.

(1) See Table 1 for more information on I/O definitions.

Pin Functions – Power and Ground

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

B1, B22, C1, C22, D2, D3, D4,

D5, D7, D18, D19, D20, D21,

E20

1.8-V Power for the differential High-Speed and Low-Speed

DMD Interfaces

VCC18A_LVDS

PWR

A1, A22, C2, C3, C4, C5, C6,

C7, C16, C17, C18, C19, C20,

C21, D8

1.8-V GND for the differential High-Speed and Low-Speed DMD

Interfaces

GND18A_LVDS

RTN

VCC18IO

D10

H4

PWR

1.8-V Power for 1.8-V IO

VCC3IO_MVGP

VCC3IO_FLSH

3.3-V Power for TPS99000-Q1 Interfaces

3.3-V Power for the Serial Flash Interface

V4

3.3-V Power for the Parallel Data, JTAG, and Host Command

Interfaces

VCC3IO_INTF

K19, L19, M19, R19, T19

PWR

VCC3IO_COSC

C15

C14

PWR

RTN

3.3-V I/O Power for the Crystal Oscillator

3.3-V I/O GND for the Crystal Oscillator

GNDIOLA_COSC

J4, K4, M4, N4, P4, W4, W5,

G19

3.3-V I/O Power for all "other" I/O (such as GPIO, TSTPT,

PMIC_AD3)

VCC3IO

PWR

RTN

PWR

RTN

W9, W13, W15, W19, Y9, Y13,

Y15, Y19

VCC33A_LVDS

GND33A_LVDS

VCC11AD_PLLM

GND11AD_PLLM

3.3-V I/O Power for the OpenLDI Interface

3.3-V I/O GND for the OpenLDI Interface

W14, Y14, AA8, AA14, AA20,

AB8, AB14, AB20, AB21

1.1-V Analog/Digital Power for MCG (Master Clock Generator)

PLL

D13

C13

1.1-V Analog/Digital GND for MCG (Master Clock Generator)

PLL

1.1-V Analog/Digital Power for DCG (DMD Clock Generator)

PLL

VCC11AD_PLLD

GND11AD_PLLD

VCC11A_DDI_0

D12

C12

PWR

RTN

PWR

1.1-V Analog/Digital GND for DCG (DMD Clock Generator) PLL

1.1-V Filtered Core Power - External Filter Group A (HS DMD

Interface 0)

E19, F19

1.1-V Filtered Core Power - External Filter Group B (HS DMD

Interface 1)

VCC11A_DDI_1

VCC11A_LVDS

E4, F4

PWR

1.1-V Filtered Core Power - External Filter Group C (OpenLDI

Interface)

W11, W12, W17, W18

G4, H19, (J11), J19, L4, N19,

P19, T4, U4, U19, V19, W6,

W8, W10, W16

1.1-V Core Power (Ball numbers in parenthesis are also used as

thermal ball and are located within the package center region)

VCCK

PWR

(1) See Table 1 for more information on I/O definitions.

12

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Pin Functions – Power and Ground (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NUMBER

(J9, J10, J12, J13, J14, K9,

K10, K11, K12, K13, K14, L9,

L10, L11, L12, L13, L14, M9,

M10, M11, M12, M13, M14, N9,

N10, N11, N12, N13, N14, P9,

P10, P11, P12, P13,P14), Y3,

AA1, AA2, AB1, AB2, AB22,

Y10, Y11, Y12, Y16, Y17, Y18

1.1-V Core GND (Ball numbers in parenthesis are also used as

thermal ball and are located within the package center region)

GND

RTN

EFUSE_VDDQ

EFUSE_POR33

W7

Y8

Manufacturing use only. Must be tied to ground.

Bandgap Reference for sub-LVDS drivers (Supports

DMD_HS0_xxxx). Requires a resistor (1% Tolerance) to

GND18A_LVDS - Value specified in Table 18.

RPI_0

RPI_1

RPI_LS

D17

D6

I₅

Bandgap Reference for sub-LVDS drivers (Supports

DMD_HS1_xxxx). Requires a resistor (1% Tolerance) to

GND18A_LVDS - Value specified in Table 18.

Bandgap References for sub-LVDS drivers (Supports

DMD_LS0_xxxx differential bus signals). Requires a resistor (1%

Tolerance) to GND18A_LVDS - Value specified in Table 18.

D9

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DLPC230-Q1

ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

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Table 1. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

1

2

1.8-V LVCMOS Input

1.8-V LVCMOS Output

1.8-V LVCMOS Input

1.8-V sub-LVDS Output

1.8-V sub-LVDS Input

3.3-V LVCMOS Output

3.3-V LVCMOS Input

3.3-V LVCMOS Output

3.3-V LVCMOS Input

3.3-V LVCMOS Output

3.3-V LVCMOS Input

3.3-V I²C I/O

VCC18IO

ESD diode to GND and supply rail

3

VCC18IO

4

VCC18A_LVDS

VCC3IO_MVGP

VCC3IO_FLSH

VCC3IO_INTF

VCC3IO

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

TYPE

I

3.3-V LVCMOS Output

3.3-V LVCMOS Input

3.3-V I²C I/O with 3-mA drive

3.3-V LVCMOS Output

3.3-V LVCMOS Input

3.3-V LVDS Input

VCC3IO

VCC3IO_OSC

VCC33A_LVDS

VCC3IO_OSC

VCC3IO

3.3-V LVCMOS Input

3.3-V LVCMOS Output

Input

O

Output

B

Bidirectional

Power

N/A

PWR

RTN

Ground return

Table 2. Internal Pull-up and Pull-down Characteristics⁽¹⁾⁽²⁾

INTERNAL PULL-UP AND PULL-DOWN

RESISTOR CHARACTERISTICS

VCCIO

MIN

MAX

UNIT

Weak pull-up resistance

Weak pull-down resistance

3.3 V

40

30

190

kΩ

(1) The resistance is dependent on the supply voltage level applied to the I/O.

(2) An external 8-kΩ or less pull-up or pull-down (if needed) will work for any voltage condition to correctly override any associated internal

pull-ups or pull-downs.

14

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGE⁽²⁾

V_(VCCK)(Core)

–0.5

1.5

2.5

4.6

V

V_{(VCC11A_DDIx)}(Core)

V_{(VCC11A_LVDS)}(Core)

V_{(VCC11AD_PLLM)}(Core)

V_{(VCC11AD_PLLD)}(Core)

V_{(VCC18A_LVDS)}

V_(VCC18IO)

V_{(VCC3IO_MVGP)}

V_{(VCC3IO_INF)}

V_{(VCC3IO_FLSH)}

V_{(VCC3IO_OSC)}

V_(VCC3IO)

V_{(VCC33A_LVDS)}

GENERAL

T_J

Operating junction temperature

Operating case temperature

Latch-up

–40

125

124⁽³⁾

100

°C

T_C

I_lat

–100

–40

mA

°C

T_stg

Storage temperature range

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Value calculated using package parameters defined in Thermal Information.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Electrostatic

discharge

All pins (except corner pins)

V_(ESD)

V

Charged-device model (CDM), per

AEC Q100-011

Corner pins (A1, A22, AB0, and AB22)

only

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_(VCCK)

Core power 1.1 V (main 1.1 V)

±5% tolerance

1.045

1.1

1.155

V

Core power 1.1 V (External Filter Group A - HS

DMD Interface 0)

V_{(VCC11A_DDI_0)}

±8.18% tolerance⁽¹⁾

1.01

1.1

1.19

V

Core power 1.1 V (External Filter Group B - HS

DMD Interface 1)

V_{(VCC11A_DDI_1)}

V_{(VCC11A_LVDS)}

±8.18% tolerance⁽¹⁾

1.19

Core power 1.1 V (External Filter Group C -

OpenLDI Interface)

V_{(VCC11AD_PLLM)}

V_{(VCC11AD_PLLD)}

MCG PLL 1.1-V power (Analog/Digital)

DCG PLL 1.1-V power (Analog/Digital)

±8.18% tolerance⁽¹⁾

1.01

1.1

1.19

V

1.8-V I/O power (Supports DMD Single-Ended LS

interface I/O)

V_(VCC18IO)

±8.3% tolerance

1.65

1.8

1.95

V

1.8-V I/O power (Supports High-Speed and Low-

Speed differential DMD interfaces)

V_{(VCC18A_LVDS)}

3/3-V I/O power (Supports TPS99000-Q1: SPI,

interrupt, park, RESETZ, and LEDSEL interfaces

V_{(VCC3IO_MVGP)}

V_{(VCC3IO_FLSH)}

±8.5% tolerance

3.02

3.3

3.58

V

3/3-V I/O power (Supports serial flash interface)

3.3-V I/O power (Supports: host command (SPI

V_{(VCC3IO_INTF)}

and I²C), parallel data interface, HOST_IRQ, and ±8.5% tolerance

JTAG

3.02

3.3

3.58

V

V_{(VCC3IO_OSC)}

V_{(VCC33A_LVDS)}

3.3-V I/O power (Supports Oscillator)

±8.5% tolerance

3.02

3.3

3.58

V

3.3-V I/O power (Supports OpenLDI interface)

3.3-V I/O power (Supports all remaining I/O

including: GPIO, PMIC_AD3, TSTPT,

ETM_TRACE, et cetera)

V_(VCC3IO)

±8.5% tolerance

3.02

3.3

3.58

V

T_J

T_C

T_A

Operating junction temperature

–40

125

124

105

°C

Operating case temperature

Operating ambient temperature⁽²⁾

(1) These I/O supply ranges are wider to facilitate additional external filtering.

(2) Operating ambient temperature is dependent on system thermal design. Operating case temperature may not exceed its specified range

across ambient temperature conditions.

6.4 Thermal Information

DLPC230-Q1

THERMAL METRIC⁽¹⁾

ZDQ (BGA)

324 PINS

UNIT

Temperature variance from junction to package top center

temperature, per unit power dissipation

(2)

ψ_JT

0.77

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) (1.22 W) × (0.77°C/W) ≈ 1.00°C temperature difference.

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX⁽²⁾UNIT

TOTAL

I_(VCC11)

I_(VCC18)

I_(VCC33)

1.1-V total current

1.8-V total current

3.3-V total current

201

71

743.9

122.9

30.1

mA

28.1

ESTIMATED CURRENT PER SUPPLY⁽³⁾

I_(VCCK)

1.1-V Core current

131.5

15.8

667.5

17.4

mA

I_{(VCC11A_DDI_0)}

I_{(VCC11A_DDI_1)}

1.1-V Core current (Filtered)

At 600-MHz data rate

OpenLDI Interface, single port, 5

lanes active

I_{(VCC11A_LVDS)}

1.1-V Core current (Filtered)

22.5

24.8

mA

I_{(VCC11AD_PLLM)}

I_{(VCC11AD_PLLD)}

1.1-V Core current (MCG PLL)

1.1-V Core current (DCG PLL)

7.7

8.4

mA

1.8-V I/O current (Both 8-bit ports -

DMD HS differential Interface)

I_{(VCC18A_LVDS)}

I_(VCC18IO)

At 600-MHz data rate

At 120-MHz data rate

63.3

5.2

106.6

8.7

mA

1.8-V I/O current (DMD LS differential

Interface)

1.8-V I/O current (DMD LS single-

ended interfaces, DMD reset)

2.5

7.6

3.3-V I/O current (TPS99000-Q1 SPI,

TPS99000-Q1 Reset, PMIC_PARKZ,

RESETZ)

I_{(VCC3IO_MVGP)}

1.7

1.8

mA

3.3-V I/O current (Host SPI, Host I²C,

Host IRQ, JTAG, Parallel Port)

I_{(VCC3IO_INTF)}

I_{(VCC3IO_FLSH)}

I_{(VCC3IO_OSC)}

I_(VCC3IO)

1.7

5.5

1.8

5.9

mA

3.3-V I/O current (Serial Flash SPI

interface)

With 3-kΩ external series resistor

(R_S)

3.3-V I/O current (Crystal/Oscillator)

0.975

12.6

6.3

1.3

3.3-V I/O current (GPIO, PMIC_AD3,

Mstr I²C, TSTPT, ETM, and so forth)

13.5

6.8

3.3-V I/O current (OpenLDI Interface -

each port - 5 lanes active)

I_{(VCC33A_LVDS)}

(1) Typical-case power measured with PVT condition = nominal process, typical voltage, typical temperature (25°C junction). Input source

1152 × 576 24-bit 60-Hz OpenLDI with RGBW ramp image.

(2) Worst-case power PVT condition = corner process, high voltage, high temperature (125°C junction). Input source 1152 × 1152 24-bit.

60 Hz OpenLDI with pseudo-random noise image.

(3) Estimated current per supply was not directly measured. These values are based on an approximate expected current consumption

percentage of the total measured current drawn by each voltage rail.

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

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MAX UNIT

6.6 Electrical Characteristics for Fixed Voltage I/O

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

1.8-V LVCMOS (I/O type 3)

3.3-V LVCMOS (I/O type 7)

3.3-V LVCMOS (I/O type 9)

3.3-V LVCMOS (I/O type 11)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 14)

3.3-V LVCMOS (I/O type 16,17)

3.3-V LVCMOS (I/O type 19)

3.3-V I²C buffer (I/O type 15)

1.8-V LVCMOS (I/O type 3)

3.3-V LVCMOS (I/O type 7)

3.3-V LVCMOS (I/O type 9)

3.3-V LVCMOS (I/O type 11)

0.7 × VCC18IO

2.0

High-level

input

threshold

voltage

V_IH

0.7 × VCC_INTF

2.0

V

0.7 × VCC3IO

2.0

0.7 × VCC3IO

0.3 × VCC18IO

0.8

Low-level

input

threshold

voltage

0.3 ×

VCC_INTF

V_IL

3.3-V I²C buffer (I/O type 12)

V

3.3-V LVCMOS (I/O type 14)

3.3-V LVCMOS (I/O type 16,17)

3.3-V LVCMOS (I/O type 19)

3.3-V I²C buffer (I/O type 15)

1.8-V LVCMOS (I/O type 1,2)

3.3-V LVCMOS (I/O type 6)

3.3-V LVCMOS (I/O type 8)

3.3-V LVCMOS (I/O type 10)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 13)

3.3-V I²C buffer (I/O type 15)

3.3-V LVCMOS (I/O type 20)

1.8-V LVCMOS (I/O type 1,2)

3.3-V LVCMOS (I/O type 6)

3.3-V LVCMOS (I/O type 8)

3.3-V LVCMOS (I/O type 10)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 13)

3.3-V I²C buffer (I/O type 15)

3.3-V LVCMOS (I/O type 20)

1.8-V LVCMOS (I/O type 1)

1.8-V LVCMOS (I/O type 2)

3.3-V LVCMOS (I/O type 6)

3.3-V LVCMOS (I/O type 8)

3.3-V LVCMOS (I/O type 10)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 13)

3.3-V I²C buffer (I/O type 15)

3.3-V LVCMOS (I/O type 20)

0.8

0.3 × VCC3IO

0.8

0.3 × VCC3IO

I_OH= Max rated

I_OL= Max rated

0.75 × VCC18IO

2.4

N/A

2.4

N/A

2.4

High-level

V_OHoutput

voltage

V

0.4

Low-level

V_OLoutput

voltage

V

6

7.2

6

High-level

output

current

I_OH

6

mA

N/A

8

N/A

6

(1) The number inside each parenthesis for the I/O refers to the type defined in Table 1.

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Electrical Characteristics for Fixed Voltage I/O (continued)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

6

TYP

MAX UNIT

1.8-V LVCMOS (I/O type 1)

1.8-V LVCMOS (I/O type 2)

3.3-V LVCMOS (I/O type 6)

3.3-V LVCMOS (I/O type 8)

3.3-V LVCMOS (I/O type 10)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 13)

3.3-V I²C buffer (I/O type 15)

3.3-V LVCMOS (I/O type 20)

1.8-V LVCMOS (I/O type 1,2)

3.3-V LVCMOS (I/O type 6)

3.3-V LVCMOS (I/O type 8)

3.3-V LVCMOS (I/O type 10)

3.3-V I²C buffer (I/O type 12)

3.3-V LVCMOS (I/O type 13)

3.3-V LVCMOS (I/O type 16)

3.3-V I²C buffer (I/O type 15)

3.3-V LVCMOS (I/O type 20)

7.2

6

Low-level

output

current

I_OL

6

mA

3

8

3

6

±1.0

±10

High-

impedance

leakage

current

I_OZ

±10

µA

±1.0

±10

±1.0

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6.7 DMD High-Speed Sub-LVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

V_CM

Steady-state common mode voltage

1.8-V sub-LVDS (I/O type 4,5)

0.8

0.9

1.0

V

V_CMchange peak-to-peak (during

switching)

V_CM(Δpp)⁽¹⁾

75

mV

V_CM(Δss)⁽¹⁾

V_CMchange steady state

–10

155

10

Differential output voltage magnitude. R_BGR

= 75kΩ.

(2)

|V_OD

|

200

250

V_OD(Δ)⁽³⁾

V_OH

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Differential output rise time

Differential output fall time

Max switching rate

1.8-V sub-LVDS (I/O type 4,5)

–10

0.88

10

1.125

0.925

250

mV

V

1.00

0.80

V_OL

0.675

V

(2)

t_R

ps

(2)

t_F

250

ps

f_MAX

1200

55%

120

Mbps

DCout

Output duty cycle

45%

80

50%

100

(1)

Tx_term

Internal differential termination

Ω

(1) Definition of V_CMchanges:

V_CM

V_CM(4ss)

V_CM(4pp)

(2) Note that V_ODis the differential voltage swing measured across a 100-Ω termination resistance connected directly between the

transmitter differential pins. |V_OD| is the magnitude of the peak to peak voltage swing across the P and N output pins. Since V_CMcancels

out when measured differentially, V_ODvoltage swings relative to 0. Rise and fall times are defined for the differential V_ODsignal as

follows:

t_F

t_R

+ Vod

0V

80%

20%

|Vod|

V_OD

- Vod

Differential Output Signal

(Note: V_CMis removed when signals are viewed differentially)

An invisible line to help with spacing in spec

(3) When TX data input = '1', differential output voltage V_OD1is defined. When TX data input = '0', differential output voltage V_OD0is defined.

As such, the steady state magnitude of the difference is: |V_OD| (Δ) = ||V_OD1| - |V_OD0||.

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

6.8 DMD Low-Speed Sub-LVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

V_CM

Steady-state common mode voltage

1.8-V sub-LVDS (I/O type 4,5)

0.8

0.9

1.0

V

V_CMchange peak-to-peak (during

switching)

V_CM(Δpp)⁽¹⁾

75

10

mV

V_CM(Δss)⁽¹⁾

V_CMchange steady state

–10

155

Differential output voltage magnitude.

R_BGR= 75kΩ.

(2)

|V_OD

|

200

250

V_OD(Δ)⁽³⁾

V_OH

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Differential output rise time

Differential output fall time

Max switching rate

1.8-V sub-LVDS (I/O type 4,5)

–10

0.88

10

1.125

0.925

250

mV

V

1.00

0.80

V_OL

0.675

V

(2)

t_R

ps

(2)

t_F

250

ps

t_MAX

240

Mbps

DCout

Tx_term

Output duty cycle

45%

80

50%

100

55%

120

Internal differential termination

Ω

(1) Definition of V_CMchanges:

V_CM

V_CM(4ss)

V_CM(4pp)

(2) Note that V_ODis the differential voltage swing measured across a 100-Ω termination resistance connected directly between the

transmitter differential pins. |V_OD| is the magnitude of the peak to peak voltage swing across the P and N output pins. Since V_CMcancels

out when measured differentially, V_ODvoltage swings relative to 0. Rise and fall times are defined for the differential V_ODsignal as

follows:

t_F

t_R

+ Vod

0V

80%

20%

|Vod|

V_OD

- Vod

Differential Output Signal

(Note: V_CMis removed when signals are viewed differentially)

An invisible line to help with spacing in spec

(3) When TX data input = '1', differential output voltage V_OD1is defined. When TX data input = '0', differential output voltage V_OD0is defined.

As such, the steady state magnitude of the difference is: |V_OD| (Δ) = ||V_OD1| - |V_OD0||.

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6.9 OpenLDI LVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

0.35

100

90

NOM

MAX

UNIT

V

V_CM

Steady-state common mode voltage

Differential Input Voltage

3.3-V LVDS (I/O type 18)

1.2

1.6

700

132

|V_ID

|

mV

Ω

Rx_term

Internal differential termination

111

6.10 Power Dissipation Characterisics

PARAMETER

VALUE

1.22

UNIT

P_MAX

Package - Maximum Power

W

6.11 System Oscillators Timing Requirements

MIN

NOM

16.000

62.500

MAX UNIT

f_clockClock frequency, MOSC⁽¹⁾

15.997

62.488

40% of t_c

0.2

16.003

MHz

ns

(1)

t_c

Cycle time, MOSC

62.512

t_w(H)Pulse duration⁽²⁾, MOSC, high

t_w(L)Pulse duration⁽²⁾, MOSC, low

50% to 50% reference points (signal)

20% to 80% reference points (signal)

t_t

Transition time⁽²⁾, MOSC, t_t= t_ƒ/ t_r

Long term periodic jitter⁽²⁾, MOSC

2

ns

ps

t_jp

100

(that is the deviation in period from ideal period due solely to high frequency jitter)

(1) The MOSC input cannot support spread spectrum clock spreading.

(2) Applies only when driven through an external digital oscillator. This is a 1 sigma RMS value.

t_t

t_c

t_w(H)

t_w(L)

80%

20%

80%

20%

50%

MOSC

50%

Figure 1. System Oscillators

Table 3. Crystal / Oscillator Electrical Characteristics

PARAMETER

NOMINAL

3.5

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

3.45

pF

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

6.12 Power Supply and Reset Timing Requirements

MIN

MAX

10

UNIT

ms

TPS99000-Q1 REQUIREMENTS⁽¹⁾

Power supply ramp to minimum

recommended operating voltage

t_ramp

Power supply ramp time⁽²⁾

0.5

Leading edge for application or removal of

power. Each 1.1-V power supply to the

DLPC230-Q1 must be applied

t_{ps_aln}1.1-V Power Supply Alignment⁽³⁾

10

µs

simultaneously within this time.

t_rst

RESETZ low to Power Supply disable⁽⁴⁾

Pulse duration, active low, RESETZ⁽⁴⁾

Leading edge for removal of power

1.0

5.0

µs

95% power to 50% RESETZ reference

point

t_w(L1)

ms

At initial application of power

50% to 50% reference points (RESETZ)

Subsequent resets after initial application

of power

t_w(L2)

t_t

Pulse duration, active low, RESETZ

Transition time, RESETZ, t_t= t_ƒand t_r

1.0

µs

20% to 80% reference points (signal)

6

(1) The TPS99000-Q1 controls power supply timing for the DLPC230-Q1. Refer to the TPS99000-Q1 data sheet for additional system

power timing requirements.

(2) Power supplies do not need to ramp simultaneously, but each supply must reach its minimum voltage within the maximum ramp time

specified.

(3) The DLPC230-Q1 does not require specific sequencing or alignment of 1.8-V and 3.3-V supplies. However, the TPS99000-Q1 enforces

sequencing of the 1.1-V, 1.8-V, and 3.3-V voltage rails. The following describes DLPC230-Q1 behavior when the voltage rails are not

brought up simultaneously:

(a) VCCK (1.1-V core) Power = On, I/O Power = Off, RESETZ = '0': While this condition exists, additional leakage current may be

drawn, and all outputs are unknown (likely to be a weak "low").

(b) VCCK (1.1-V core) Power = Off, I/O Power = On, RESETZ = '0': While this condition exists all outputs are tri-stated.

Neither of these two conditions will impact normal DLPC230-Q1 reliability.

(4) RESETZ must be held low if any supply (Core or I/O) is less than its minimum specified on value. For more information on RESETZ,

see Pin Configuration and Functions.

t_ramp

All 1.1V Power

(Core Power)

95% of specified

nominal value

All 1.8V & 3.3V Power

(I/O Power)

TPS99000

95% of specified

t_t

Control

nominal value

t_rst

80%

50%

RESETZ

20%

t_w(L1)

t_w(L2)

PARKZ

DLPC230

Control

DMD Control

Signals

Control / Display Park

Figure 2. Power Supply and RESETZ Timing

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6.13 Parallel Interface General Timing Requirements

MIN

12.0

MAX

110.0

83.33

UNIT

MHz

ns

ƒ_clock

t_{p_clkper}

t_{p_wh}

Clock frequency, PCLK

Clock period, PCLK

50% reference points

9.091

2.286

Pulse duration low, PCLK

Pulse duration high, PCLK

ns

t_{p_wl}

ns

Setup time – HSYNC, DATEN,

PDATA(23:0) valid before the active

edge of PCLK

t_{p_su}

50% reference points

0.8

ns

Hold time – HSYNC, DATEN,

PDATA(23:0) valid after the active edge 50% reference points

of PCLK

t_{p_h}

t_{t_clk}

t_t

Transition time – PCLK

20% to 80% reference points

6

ns

Transition time – all other signals on

this port

20% to 80% reference points

Percent of ƒ_clockrate

ƒ_spread

ƒ_mod

Supported Spread Spectrum range

Supported Spread Spectrum Modulation Frequency⁽¹⁾⁽²⁾

–1%

25

+1%⁽¹⁾

65⁽³⁾

kHz

t_{p_clkper}

–

t_{p_clkjit}

Clock jitter, PCLK

ps

5.414

(1) This value is limited by the maximum clock frequency for ƒ_clock(that is, if ƒ_clock= max clock freq, then ƒ_spreadmax = 0%).

(2) Modulation Waveforms supported: Sine and Triangle.

(3) Spread spectrum modulation tested at a maximum of 35 kHz. Simulated up to 65 kHz.

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

Figure 3. Parallel Interface General Timing

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

6.14 OpenLDI Interface General Timing Requirements

The DLPC230-Q1 ASIC input interface supports a subset of the industry standard OpenLDI (FPD-Link I) interface (Open

LVDS Display Interface Specification v0.95 - May 13, 1999). Specifically, from the standard, the ASIC supports the 24-bit,

Single Pixel Format, using the Unbalanced Operating Mode and Pixel Mapping.

MIN

NOM

MAX

UNIT

ƒ_clock

t_p

Clock frequency, L1_CLK_P/N, L2_CLK_P/N

20.0

110

MHz

50% reference

Clock period, PCLK

9.091

50

ns

points

ƒ_clock> 85 MHz

–150

–400

0

150

400

ps

Skew Margin (between clock and

data)

t_skew

ƒ_clock≤ 85 MHz

0

t_ip1

t_ip0

t_ip6

t_ip5

t_ip4

t_ip3

t_ip2

Input data position 0

Input data position 1

Input data position 2

Input data position 3

Input data position 4

Input data position 5

Input data position 6

–t_skew

t_skew

(t_p/ 7) – t_skew

2 * (t_p/ 7) – t_skew

3 * (t_p/ 7) – t_skew

4 * (t_p/ 7) – t_skew

5 * (t_p/ 7) – t_skew

6 * (t_p/ 7) – t_skew

(t_p/ 7)

(t_p/ 7) + t_skew

2 * (t_p/ 7) 2 * (t_p/ 7) + t_skew

3 * (t_p/ 7) 3 * (t_p/ 7) + t_skew

4 * (t_p/ 7) 4 * (t_p/ 7) + t_skew

5 * (t_p/ 7) 5 * (t_p/ 7) + t_skew

6 * (t_p/ 7) 6 * (t_p/ 7) + t_skew

Input Jitter Tolerance

(cycle to cycle, peak to peak)

t_jitter

100

ps

percent of ƒ_clock

rate

Supported Spread Spectrum Modulation Frequency⁽³⁾⁽⁴⁾

ƒ_spread

ƒ_mod

Supported Spread Spectrum range

–1%⁽¹⁾

25

+1%⁽²⁾

65

kHz

(1) This value is limited by the minimum clock frequency for ƒ_clock(that is, if ƒ_clock= min clock freq, then ƒ_spreadmax = 0%).

(2) This value is limited by the maximum clock frequency for ƒ_clock(that is, if ƒ_clock= max clock freq, then ƒ_spreadmax = 0%).

(3) Modulation Waveforms supported: Sine and Triangle.

(4) Spread spectrum on OpenLDI interfaces was simulated, but not tested.

t_p

Lx_CLK

Lx_DATA0

Lx_DATA1

Lx_DATA2

Lx_DATA3

D0(1)

D1(1)

D2(1)

D3(1)

D0(0)

D1(0)

D2(0)

D3(0)

D0(6)

D1(6)

D2(6)

D3(6)

D0(5)

D1(5)

D2(5)

D3(5)

D0(3)

D1(3)

D2(3)

D3(3)

D0(4)

D1(4)

D2(4)

D3(4)

D0(2)

D1(2)

D2(2)

D3(2)

t_ip1

t_ip0

t_ip6

t_ip5

t_ip4

t_ip3

t_ip2

Figure 4. OpenLDI Interface Timing

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6.15 Parallel/OpenLDI Interface Frame Timing Requirements

See⁽¹⁾

MIN

MAX

UNIT

Vertical Sync Rate (for the specified active source

resolution)

1152 × 576

See Supported Input Sources

VSYNC

58

61

Hz

Vertical Sync Rate (for the specified active source

resolution)

1152 × 1152

See Supported Input Sources

58

Hz

Vertical Sync Rate (for the specified active source

resolution)

576 × 288

See Supported Input Sources

VSYNC

t_{p_vsw}

58

1

Hz

Pulse duration – VSYNC high

50% reference points

lines

Vertical back porch (VBP) – time from the leading

t_{p_vbp}

edge of VSYNC to the leading edge HSYNC for the 50% reference points

first active line (includes t_{p_vsw}).

2

1

lines

Vertical front porch (VFP) – time from the leading

edge of the HSYNC following the last active line in a 50% reference points

frame to the leading edge of VSYNC

t_{p_vƒp}

Total vertical blanking – time from the leading edge

of HSYNC following the last active line of one frame

to the leading edge of HSYNC for the first active line 50% reference points

in the next frame. (This is equal to the sum of VBP

(t_{p_vbp}) + VFP (t_{p_vfp}))

t_{p_tvb}

14

lines

t_{p_hsw}

t_{p_hbp}

Pulse duration – HSYNC high

50% reference points

8

9

PCLKs

Horizontal back porch – time from rising edge of

HSYNC to rising edge of DATEN (includes t_{p_hsw}

50% reference points

)

Horizontal front porch – time from falling edge of

DATEN to rising edge of HSYNC

t_{p_hfp}

50% reference points

8

PCLKs

t_{p_thb}

Total horizontal blanking

Total Pixels Per Line

64

PCLKs

Pixels

TPPL

8191

(1) While these requirements are not specific to the OpenLDI interface, they are appropriate for any source that drives an OpenLDI

transmitter connected to the ASIC OpenLDI interface.

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1 Frame

t_{p_vsw}

VSYNC

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC

DATAEN

1 Line

t_{p_hsw}

HSYNC

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN

PDATA(23:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

Figure 5. Source Frame Timing

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6.16 Host/Diagnostic Port SPI Interface Timing Requirements

The DLPC230-Q1 ASIC Host/Diagnostic SPI port interface timing requirements are shown below.⁽¹⁾

MIN

MAX

10.00

UNIT

Clock frequency, HOST_SPI_CLK

(50% reference points)

f_clock

t_{p_wh}

t_{p_wl}

t_t

MHz

Pulse duration low, HOST_SPI_CLK

(50% reference points)

45.0

ns

Pulse duration high, HOST_SPI_CLK

(50% reference points)

ns

Transition time – all input signals

20% to 80% reference points

50% reference points

6

Setup time – HOST_SPI_DIN valid before

HOST_SPI_CLK capture edge

(50% reference points)

t_{p_su}

t_{p_h}

t_out

10.0

18.0

0.0

ns

Hold time – HOST_SPI_DIN valid after

HOST_SPI_CLK capture edge

Clock-to-Data out - HOST_SPI_DOUT from

HOST_SPI_CLK launch edge

(50% reference points)

35.0

(1) The DLPC230-Q1 Host/Diagnostic Port SPI interface supports SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock

phases). The HOST_SPI_MODE input must be set to match the SPI mode being used.

Data

Transition Capture

Transition

CSZ

CLK

t_{P_WH}

t_{P_WL}

Z

1

2

3

4

5

6

7

8

Z

MOSI

MISO

Z

1

2

3

4

5

6

7

8

t_OUT

Figure 6. Host/Diagnostic Port SPI Interface Timing

(Example: SPI Mode 0 (Clock Polarity = 0, Clock Phase = 0))

6.17 Host/Diagnostic Port I²C Interface Timing Requirements

The DLPC230-Q1 ASIC Host/Diagnostic I²C port interface timing requirements are shown below.⁽¹⁾⁽²⁾

MIN

MAX

400

100

200

UNIT

kHz

pF

Clock frequency, HOST_I²C_SCL

(50% reference points)

Fast-Mode

f_clock

C_L

Standard Mode

Capacitive Load (for each bus line)

(1) Meets all I²C timing per the I²C Bus Specification (except for capacitive loading as specified above). For reference see version 2.1 of the

Phillips/NXP specification.

(2) The maximum clock frequency does not account for rise time, nor added capacitance of PCB or external components which may

adversely impact this value.

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6.18 Flash Interface Timing Requirements⁽¹⁾

The DLPC230-Q1 ASIC flash memory interface consists of a SPI serial interface. See Serial Flash Interface.

MIN

MAX

UNIT

f_clock

Clock frequency, FLSH_SPI_CLK

When VCC3IO_FLSH = 3.3 VDC

9.998

50.01⁽²⁾

MHz

Clock period, FLSH_SPI_CLK

(50% reference points)

t_{p_clkper}

20.0

100

ns

Pulse duration low, FLSH_SPI_CLK

(50% reference points)

t_{p_wh}

When VCC3IO_FLSH = 3.3 VDC

9

Pulse duration high, FLSH_SPI_CLK

(50% reference points)

t_{p_wl}

t_t

t_{p_su}

When VCC3IO_FLSH = 3.3 VDC

20% to 80% reference points

ns

Transition time – all input signals

6

Setup time – FLSH_SPI_DIO[3:0] valid before

FLSH_SPI_CLK falling edge

(50% reference points)

When VCC3IO_FLSH = 3.3 VDC

50% reference points

7.0

0.0

ns

Hold time – FLSH_SPI_DIO[3:0] valid after

FLSH_SPI_CLK falling edge

t_{p_h}

FLSH_SPI_DIO[3:0] output delay valid time

(with respect to falling edge of FLSH_SPI_CLK

t_{p_clqv}

When VCC3IO_FLSH = 3.3 VDC

–3.0

3.0

ns

or

falling

edge

of

FLSH_SPI_CSZ)

(50% reference points)

(1) The DLPC230-Q1 communicates with flash devices using a slight variant of SPI Transfer Mode 0 (that is, clock polarity = 0, clock phase

= 0). Instead of capturing MISO data on the clock edge opposite from that used to transmit MOSI data, the DLPC230-Q1 captures MISO

data on the same clock edge used to transmit the next MOSI data. As such, the DLPC230-Q1 Flash SPI interface requires that MISO

data from the flash device remain active until the end of the full clock cycle to allow the last data bit to be captured. This is shown in

Figure 8.

(2) The actual maximum clock rate driven from the DLPC230-Q1 may be slightly less than this value.

t_clkper

SPI_CLK

t_wh

t_wl

(ASIC Output)

t_{p_su}

t_{p_h}

SPI_DIN

(ASIC Inputs)

t_{p_clqv}

SPI_DOUT, SPI_CS(1:0)

(ASIC Outputs)

Figure 7. Flash Interface Timing

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SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data held until end of last clock cycle

œ Compatible with DLPC230

ASIC MISO Sampling Edges

SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data not held until end of last clock cycle

œ Not compatible with DLPC230

ASIC MISO Sampling Edges

Figure 8. Flash Interface Data Capture Requirements

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6.19 TPS99000-Q1 SPI Interface Timing Requirements⁽¹⁾

The DLPC230-Q1 ASIC to TPS99000-Q1 interface consists of a SPI serial interface.

MIN

MAX

UNIT

f_clock

Clock frequency, PMIC_SPI_CLK

9.998

30.006

MHz

Clock period, PMIC_SPI_CLK

(50% reference points)

t_{p_clkper}

33.3

11.5

100

ns

Pulse duration high, PMIC_SPI_CLK

(50% reference points)

t_{p_wh}

Pulse duration low, PMIC_SPI_CLK

(50% reference points)

t_{p_wl}

t_t

ns

Transition time – all input signals

20% to 80% reference points

6

Setup time – PMIC_SPI_DIN valid before PMIC_SPI_CLK falling edge

(50% reference points)

t_{p_su}

7.0

0.0

Hold time – PMIC_SPI_DIN valid after

50% reference points

t_{p_h}

ns

PMIC_SPI_CLK falling edge

PMIC_SPI_DOUT output delay (valid) time

t_{p_clqv}

–3.0

3.0

(with respect to falling edge of PMIC_SPI_CLK or falling edge of PMIC_SPI_CSZ0)

(50% reference points)

(1) The DLPC230-Q1 communicates with the TPS99000-Q1 using a slight variant of SPI Transfer Mode 0 (that is, clock polarity = 0, clock

phase = 0). Instead of capturing MISO data on the clock edge opposite from that used to transmit MOSI data, the DLPC230-Q1

captures MISO data on the same clock edge used to transmit the next MOSI data. As such, the DLPC230-Q1 SPI interface to the

TPS99000-Q1 requires that MISO data from the TPS99000-Q1 remain active until the end of the full clock cycle to allow the last data bit

to be captured. This is shown in Figure 12.

t_{p_clkper}

t_t

t_{p_wl}

t_{p_wh}

SPI_CLK

(ASIC Output)

80%

20%

50%

t_{p_h}

t_{p_su}

SPI_DIN

(ASIC Input)

t_{p_clqv}

SPI_DOUT

(ASIC Output)

Figure 9. TPS99000-Q1 Interface Timing

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SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data held until end of last clock cycle

œ Compatible with DLPC230

ASIC MISO Sampling Edges

SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data not held until end of last clock cycle

œ Not compatible with DLPC230

ASIC MISO Sampling Edges

Figure 10. TPS99000-Q1 Interface Data Capture Requirements

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6.20 TPS99000-Q1 AD3 Interface Timing Requirements^(1)(2)(3)

The DLPC230-Q1 ASIC to TPS99000-Q1 AD3 interface is used to retrieve ADC measurements from the TPS99000-Q1. The

interface is similar to SPI and includes a clock, MOSI, and MISO signal.

MIN

MAX

UNIT

f_clock

Clock frequency, PMIC_AD3_CLK

29.326

30.006

MHz

Clock period, PMIC_AD3_CLK

(50% reference points)

t_{p_clkper}

33.327

40%

34.100

ns

Pulse duration high, PMIC_AD3_CLK

(50% reference points) (Referenced to t_{p_clkper}

t_{p_wh}

)

Pulse duration low, PMIC_AD3_CLK

(50% reference points) (Referenced to t_{p_clkper}

t_{p_wl}

t_t

40%

)

Transition time – all input signals

20% to 80% reference points

6

ns

Setup time – PMIC_AD3_MISO valid before PMIC_AD3_CLK rising edge

(50% reference points)

t_{p_su}

14.5

0

Hold time – PMIC_AD3_MISO valid after PMIC_AD3_CLK rising edge

(50% reference points)

t_{p_h}

ns

PMIC_AD3_MOSI output delay (valid) time (with respect to falling edge of

PMIC_SPI_CLK)

t_{p_clqv}

–2.0

2.0

(50% reference points)

(1) PMIC_AD3_MOSI (Master (DLPC230-Q1) Output / Slave (TPS99000-Q1) Input) is transmitted on the falling edge of PMIC_AD3_CLK.

(2) PMIC_AD3_MISO (Master (DLPC230-Q1) Input / Slave (TPS99000-Q1) Output) is captured on the rising edge of PMIC_AD3_CLK.

(3) PMIC_AD3_CLK is used as the primary TPS99000-Q1 system clock in addition to supporting the AD3 interface.

t_{p_clkper}

t_t

t_{p_wl}

t_{p_wh}

PMIC_AD3_CLK

(ASIC Output)

80%

20%

50%

t_{p_h}

t_{p_su}

PMIC_AD3_MISO

(ASIC Input)

t_{p_clqv}

PMIC_AD3_MOSI

(ASIC Output)

Figure 11. TPS99000-Q1 AD3 Interface Timing

PMIC_AD3_CLK

(ASIC Output)

PMIC_AD3_MOSI

(ASIC Output)

Wr A

Wr B

Wr C

...

Wr n

PMIC_AD3_MISO

(ASIC Input)

Rd A

Rd B

Rd C

...

Rd n

Figure 12. TPS99000-Q1 AD3 Data Capture and Transition

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6.21 Master I²C Port Interface Timing Requirements⁽¹⁾⁽²⁾

The DLPC230-Q1 ASIC Master I²C port interface timing requirements are shown below.

MIN

MAX

UNIT

kHz

pF

Fast-Mode

400

100

200

Clock frequency, MSTR_SCL

(50% reference points)

f_clock

C_L

Standard Mode

Capacitive Load (for each bus line)

(1) Meets all I²C timing per the I²C Bus Specification (except for Capacitive Loading as specified above).

(2) The maximum clock frequency does not account for rise time, nor added capacitance of PCB or external components which may

adversely impact this value.

6.22 Chipset Component Usage Specification

TI DLP^®chipsets include a DMD and one or more controllers. Reliable function and operation of TI DMDs

requires that they be used in conjunction with all of the other components in the applicable chipset, including

those components that contain or implement TI DMD control technology, such as the DLPC230-Q1. TI DMD

control technology is the TI technology and devices for operating or controlling a DLP^®products DMD.

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7 Parameter Measurement Information

7.1 HOST_IRQ Usage Model

In the DLPC230-Q1, the Host_IRQ signal is used to serve as an indication that a serious system error has

occurred for which the ASIC has executed an emergency shutdown. The specific error(s) that precipitated the

shutdown can be retrieved via the Host Command and Control interface. The actions that are taken by the ASIC

for an emergency shutdown are:

•

LEDs are disabled

The DMD is parked and powered-down

The ASIC operational mode is transitioned to Standby

The precipitating errors are captured for later review

The Host_IRQ signal is set to a high state

To recover from an emergency shutdown, the system will require a full power cycle (De-assertion of

PROJ_ON). The host should be sure to obtain the error history from the ASIC prior to this full reset, as the

reset will remove all error history from the system.

PROJ_ON

RESETZ

HOST_IRQ

System

Pwr-Down

System

Pwr-Up

Normal

Operation

Emergency

Shutdown

Figure 13. Host IRQ Timing

7.2 Input Source

The video input source can be configured to accomodate various desired input resolutions. Image processing

such as scaling and line replication may be applied in order to achieve the necessary display resolution. The

desired input resolution may depend on product configuration.

7.2.1 Supported Input Sources

The supported sources with typical timings are shown in Table 4. These typical timing examples do not minimize

blanking or pixel clock rate. Refer to Parallel/OpenLDI Interface Frame Timing Requirements for minimum timing

specifications.

Table 4. Typical Timing for Supported Source Resolutions

HORIZONTAL BLANKING

VERTICAL BLANKING

PIXEL

CLOCK

(MHz)

BACK

SYNC

FRONT

PORCH

(PIXEL

HORIZONTAL

RESOLUTION

VERTICAL

RESOLUTION

VERTICAL

RATE (Hz)

BACK

SYNC

FRONT

PORCH

(LINES)

PORCH

TOTAL⁽¹⁾

(PIXEL

TOTAL⁽¹⁾

PORCH

(PIXEL

(LINES)

CLOCKS)

(LINES)

CLOCKS)

576

1152

288

576

322

80

8

154

32

160

40

181

25

8

83

14

6

90

3

60

25.270

44.426

87.595

1152

80

32

40

33

19

(1) Sync clocks/lines are counted as a part of total blanking in these examples (Total Blanking = sync + back porch + front porch). Note that

the specifications in Parallel/OpenLDI Interface Frame Timing Requirements include sync width as part of back porch (Total Blanking =

back porch + front porch).

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7.2.2 Parallel Interface Supported Data Transfer Formats

•

24-bit RGB888 on a 24 data wire interface

7.2.2.1 OpenLDI Interface Supported Data Transfer Formats

1X 24-bit RGB888 on a 5-lane differential interface

•

OpenLDI Interface Bit Mapping Modes shows the required OpenLDI bus mapping for the supported data transfer

formats.

7.2.2.1.1 OpenLDI Interface Bit Mapping Modes

L1_CLK

L1_DATA0

L1_DATA1

L1_DATA2

L1_DATA3

G0

B1

R5

B0

R4

G5

R3

G4

B5

G7

R2

G3

B4

G6

R1

G2

B3

R7

R0

G1

B2

R6

DV

VSYNC

HSYNC

B6

RES *

B7

Previous Cycle

A. * = Use is undefined/reserved

Current Cycle

Figure 14. OpenLDI 24-bit Single Port

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8 Detailed Description

8.1 Overview

The automotive DLP^®Products chipset consists of three components – the DLP553X-Q1, the DLPC230-Q1, and

the TPS99000-Q1. The DLPC230-Q1 is the display controller for the DMD - it formats incoming video and

controls the timing of the DMD. It also controls TPS99000-Q1 light source signal timing to coordinate with DMD

timing in order to synchronize light output with DMD mirror movement. The DLPC230-Q1 is designed for

automotive applications with a wide operating temperature range and diagnostic features to identify and correct

specific system-level failures. The DLPC230-Q1 provides interfaces such as OpenLDI (video) and sub-LVDS

(DMD interface) to minimize power consumption and EMI. Applications include head-up display (HUD) and

adaptive high beam and smart headlight.

8.2 Functional Block Diagram

Test

Pattern

Generator

Video Processing

Parallel Video Port

OpenLDI Port (5 lanes)

28

Input

Control

Processing

- Dynamic Dimming

- Dynamic Scaling

- Bezel Adjustment

- Image Format Processing

- Contrast Adjust

- Color Correction

- Blue Noise STM

- Internal BIST

10

- Gamma Correction

- External Interface BIST

- DMD Interface Training

Splash

Screen

12KB

Startup

Boot ROM

SRAM

(Frame Memory)

DLP^TMDisplay

Formatting

DMD_HS0 Diff. Port (sub-LVDS)

DMD_LS0 Diff. Port (sub-LVDS)

DMD_LS0 Single Ended Port (LVCMOS)

MPU

HW

CMD

ASSIST

HOST_I²C

HOST_SPI

DMD I/F

DMD_HS1 Diff. Port (sub-LVDS)

DMD_LS1 Diff. Port (sub-LVDS)

DMD_LS1 Single Ended Port (LVCMOS)

Real Time

Control

System

Clocks & Reset

Generation

GPIO (31:0)

Clock (Crystal)

Reset Control

PMIC_AD3

TPS99000 controls,

General use

Figure 15. Functional Block Diagram

8.3 Feature Description

8.3.1 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal

(VSYNC), horizontal sync signal (HSYNC), data valid signal (DATEN), a 24-bit data bus (PDATA_x), and a pixel

clock (PCLK). Figure 5 shows the relationship of these signals.

NOTE

VSYNC must remain active at all times. If VSYNC is lost, the DMD must be transitioned to

a safe state. When the system detects a VSYNC loss, it will switch to a test pattern or

splash image as specified in flash by the Host.

The parallel interface supports intra-interface bit multiplexing (specified in flash) that can help with board layout

as needed. The intra-interface bit multiplexing allows the mapping of any PDATA_x input to any internal data bus

bit. When utilizing this feature, each unique input pin can only be mapped to one unique destination bit. The

typical mapping is shown in Figure 16. An example of an alternate mapping is shown in Figure 17.

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Feature Description (continued)

DLPC230

Parallel

RGB Input

DLPC230

Internal

Data Path

DLPC230 Bit

Swap Mux

Host Parallel

RGB Output

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

PDATA_23

PDATA_22

PDATA_21

PDATA_20

PDATA_19

PDATA_18

PDATA_17

PDATA_16

PDATA_15

PDATA_14

PDATA_13

PDATA_12

PDATA_11

PDATA_10

PDATA_9

PDATA_8

PDATA_7

PDATA_6

PDATA_5

PDATA_4

PDATA_3

PDATA_2

PDATA_1

PDATA_0

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

DATA(23)

DATA(22)

DATA(21)

DATA(20)

DATA(19)

DATA(18)

DATA(17)

DATA(16)

DATA(15)

DATA(14)

DATA(13)

DATA(12)

DATA(11)

DATA(10)

DATA(9)

DATA(8)

DATA(7)

DATA(6)

DATA(5)

DATA(4)

DATA(3)

DATA(2)

DATA(1)

DATA(0)

MUX

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

DLPC230

Figure 16. Example of Typical Parallel Port Bit Mapping

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Feature Description (continued)

DLPC230

Parallel

RGB Input

DLPC230

Internal

Data Path

DLPC230 Bit

Swap Mux

Host Parallel

RGB Output

B0

G0

R0

B1

G1

R1

B2

R2

B7

B6

B5

B4

B3

G7

G6

G5

G4

G3

G2

R7

R6

R5

R4

R3

PDATA_23

PDATA_22

PDATA_21

PDATA_20

PDATA_19

PDATA_18

PDATA_17

PDATA_16

PDATA_15

PDATA_14

PDATA_13

PDATA_12

PDATA_11

PDATA_10

PDATA_9

PDATA_8

PDATA_7

PDATA_6

PDATA_5

PDATA_4

PDATA_3

PDATA_2

PDATA_1

PDATA_0

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

DATA(23)

DATA(22)

DATA(21)

DATA(20)

DATA(19)

DATA(18)

DATA(17)

DATA(16)

DATA(15)

DATA(14)

DATA(13)

DATA(12)

DATA(11)

DATA(10)

DATA(9)

DATA(8)

DATA(7)

DATA(6)

DATA(5)

DATA(4)

DATA(3)

DATA(2)

DATA(1)

DATA(0)

MUX

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

DLPC230

Figure 17. Example of Alternate Parallel Port Bit Mapping

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Feature Description (continued)

8.3.2 OpenLDI Interface

Each DLPC230-Q1 OpenLDI interface port supports intra-port lane multiplexing (specified in flash) that can help

with board layout as needed. The intra-port multiplexing allows the mapping of any Lx_DATA lane pair to any

internal data lane pair. When utilizing this feature, each unique lane pair can only be mapped to one unique

destination lane pair. The typical lane mapping is shown in Figure 18. An example of an alternate lane mapping

is shown in Figure 19.

DLPC230

Internal

OpenLDI

DLPC230

Lane Swap

Mux

DLPC230

OpenLDI Input

Host OpenLDI

Output

L1_DATA3

(P/N pair)

L1_DATA3

(P/N pair)

L1_DATA3

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA2

(P/N pair)

MUX

L1_DATA1

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA0

(P/N pair)

DLPC230

Figure 18. Example of Typical OpenLDI Port Lane Mapping

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Feature Description (continued)

DLPC230

Internal

OpenLDI

DLPC230

Lane Swap

Mux

DLPC230

OpenLDI Input

Host OpenLDI

Output

L1_DATA1

(P/N pair)

L1_DATA3

(P/N pair)

L1_DATA3

(P/N pair)

L1_DATA3

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA2

(P/N pair)

MUX

L1_DATA3

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA1

(P/N pair)

L1_DATA2

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA0

(P/N pair)

L1_DATA0

(P/N pair)

DLPC230

Figure 19. Example of Alternate OpenLDI Port Lane Mapping

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Feature Description (continued)

8.3.3 DMD (Sub-LVDS) Interface

The DLPC230-Q1 ASIC DMD interface supports two high-speed sub-LVDS output-only interfaces for data

transmission, a single low-speed sub-LVDS output-only interface for command write transactions, as well as a

low-speed single-ended input interface used for command read transactions. The DLPC230-Q1 supports a

limited number of DMD interface swap configurations (specified in Flash) that can help board layout by

remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 5 shows

some of the options available.

Table 5. ASIC to 8-Lane DMD Pin Mapping Options

DLPC230-Q1 ASIC PIN ROUTING OPTIONS TO DMD PINS

SWAP HS0 PORT

DMD PINS

SWAP HS0 PORT WITH

HS1 PORT

WITH HS1 PORT

AND FULL FLIP

180

BASELINE

FULL FLIP HS0/HS1 180

HS0_WDATA0_P

HS0_WDATA0_N

HS0_WDATA7_P

HS0_WDATA7_N

HS1_WDATA0_P

HS1_WDATA0_N

HS1_WDATA7_P

HS1_WDATA7_N

D_AP(0)

D_AN(0)

HS0_WDATA1_P

HS0_WDATA1_N

HS0_WDATA6_P

HS0_WDATA6_N

HS1_WDATA1_P

HS1_WDATA1_N

HS1_WDATA6_P

HS1_WDATA6_N

D_AP(1)

D_AN(1)

HS0_WDATA2_P

HS0_WDATA2_N

HS0_WDATA5_P

HS0_WDATA5_N

HS1_WDATA2_P

HS1_WDATA2_N

HS1_WDATA5_P

HS1_WDATA5_N

D_AP(2)

D_AN(2)

HS0_WDATA3_P

HS0_WDATA3_N

HS0_WDATA4_P

HS0_WDATA4_N

HS1_WDATA3_P

HS1_WDATA3_N

HS1_WDATA4_P

HS1_WDATA4_N

D_AP(3)

D_AN(3)

HS0_WDATA4_P

HS0_WDATA4_N

HS0_WDATA3_P

HS0_WDATA3_N

HS1_WDATA4_P

HS1_WDATA4_N

HS1_WDATA3_P

HS1_WDATA3_N

D_AP(4)

D_AN(4)

HS0_WDATA5_P

HS0_WDATA5_N

HS0_WDATA2_P

HS0_WDATA2_N

HS1_WDATA5_P

HS1_WDATA5_N

HS1_WDATA2_P

HS1_WDATA2_N

D_AP(5)

D_AN(5)

HS0_WDATA6_P

HS0_WDATA6_N

HS0_WDATA1_P

HS0_WDATA1_N

HS1_WDATA6_P

HS1_WDATA6_N

HS1_WDATA1_P

HS1_WDATA1_N

D_AP(6)

D_AN(6)

HS0_WDATA7_P

HS0_WDATA7_N

HS0_WDATA0_P

HS0_WDATA0_N

HS1_WDATA7_P

HS1_WDATA7_N

HS1_WDATA0_P

HS1_WDATA0_N

D_AP(7)

D_AN(7)

HS1_WDATA0_P

HS1_WDATA0_N

HS1_WDATA7_P

HS1_WDATA7_N

HS0_WDATA0_P

HS0_WDATA0_N

HS0_WDATA7_P

HS0_WDATA7_N

D_BP(0)

D_BN(0)

HS1_WDATA1_P

HS1_WDATA1_N

HS1_WDATA6_P

HS1_WDATA6_N

HS0_WDATA1_P

HS0_WDATA1_N

HS0_WDATA6_P

HS0_WDATA6_N

D_BP(1)

D_BN(1)

HS1_WDATA2_P

HS1_WDATA2_N

HS1_WDATA5_P

HS1_WDATA5_N

HS0_WDATA2_P

HS0_WDATA2_N

HS0_WDATA5_P

HS0_WDATA5_N

D_BP(2)

D_BN(2)

HS1_WDATA3_P

HS1_WDATA3_N

HS1_WDATA4_P

HS1_WDATA4_N

HS0_WDATA3_P

HS0_WDATA3_N

HS0_WDATA4_P

HS0_WDATA4_N

D_BP(3)

D_BN(3)

HS1_WDATA4_P

HS1_WDATA4_N

HS1_WDATA3_P

HS1_WDATA3_N

HS0_WDATA4_P

HS0_WDATA4_N

HS0_WDATA3_P

HS0_WDATA3_N

D_BP(4)

D_BN(4)

HS1_WDATA5_P

HS1_WDATA5_N

HS1_WDATA2_P

HS1_WDATA2_N

HS0_WDATA5_P

HS0_WDATA5_N

HS0_WDATA2_P

HS0_WDATA2_N

D_BP(5)

D_BN(5)

HS1_WDATA6_P

HS1_WDATA6_N

HS1_WDATA1_P

HS1_WDATA1_N

HS0_WDATA6_P

HS0_WDATA6_N

HS0_WDATA1_P

HS0_WDATA1_N

D_BP(6)

D_BN(6)

HS1_WDATA7_P

HS1_WDATA7_N

HS1_WDATA0_P

HS1_WDATA0_N

HS0_WDATA7_P

HS0_WDATA7_N

HS0_WDATA0_P

HS0_WDATA0_N

D_BP(7)

D_BN(7)

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8.3.4 Serial Flash Interface

The DLPC230-Q1 uses an external SPI serial flash memory device for configuration and operational data. The

minimum supported size is 64 Mb. Larger devices may be required based on operation data and splash image

size. The maximum supported size is 128 Mb. It should be noted that the system will support 256 Mb and 512

Mb devices, however, only the first 128 Mb of space will be used.

The external serial flash device is supported on a single SPI interface and mostly complies with industry standard

SPI flash protocol (See Figure 8). The Host will specify the maximum supported flash interface frequency (which

can be based on device limits, system limits, and/or other factors) and the system will program the closest

obtainable value less than or equal to this specified maximum.

The DLPC230-Q1 ASIC flash must be connected to the designated SPI flash interface (FLSH_SPI_xxx) to

enable support for system initialization, configuration, and operation.

The DLPC230-Q1 should support any flash device that is compatible with the modes of operation, features, and

performance as defined in this section.

Table 6. SPI Flash Required Features or Modes of Operation

FEATURE

SPI interface width

SPI protocol

DLPC230-Q1 REQUIREMENT

Single Wire, Two Wire, Four Wire

COMMENTS

SPI mode 0

Fast READ addressing

Programming mode

Page size

Auto-incrementing

Page mode

256 Bytes

Sector (or sub-sector) size

Block structure

4 KB

Required erase granularity

Uniform sector / sub-sector

0 = Disabled (with Default = 0 = Disabled)

Write in progress (WIP) {also called flash busy}

Write enable latch (WEN)

A value of 0 disables programming protection

Status register write protect (SRWP)

Block protection bits

Status register bit(0)

Status register bit(1)

Status register bits(6:2)

Status register bit(7)

The DLPC230-Q1 supports multi-byte status registers, as well as

separate, additional status registers, but only for specific

devices/register addresses. The supported registers and addresses are

specified in Table 7.

Status register bits(15:8)

(expanded status register), or

Secondary Status register

CAUTION

The selected SPI flash device must block repeated status writes from being written to

internal register. The boot application writes to the flash device status register once per

256 bytes during programming. Most flash devices discard status register writes when

the status content does not change. Some flash parts, such as the Micron

N25Q128A13ESFA0F, do not block status writes when the status data is repeated.

This causes the status register to exceed its maximum write limit after several

programming cycles, making them incompatible with the DLPC230-Q1. Note that the

main application does not write to the status register.

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For each write operation, the DLPC230-Q1 boot application executes the following:

1. Write enable command

2. Write status command (to unprotect memory)

3. Read status command to poll the successful execution of the write status (repeated as needed)

4. Write enable command

5. Program or erase command

6. Read status command (repeated as needed) to poll the successful execution of the program or erase

operation

7. Write disable command (during programming; this is not performed after erase command.)

For each write operation, the DLPC230-Q1 main application executes the following:

1. Write enable command

2. Program or erase command

3. Read status command (repeated as needed) to poll the successful execution of the program or erase

operation

4. Write disable command (during programming; this is not performed after erase command)

The specific instruction op-code and timing compatibility requirements are listed in Table 7 and Flash Interface

Timing Requirements. Note that DLPC230-Q1 does not read the flash’s full electronic signature ID and thus

cannot automatically adapt protocol and clock rates based on the ID.

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Table 7. SPI Flash Instruction Op-Code and Access Profile Compatibility Requirements

FIRST

BYTE

(OP-CODE)

NO. OF

DUMMY

CLOCKS

SPI FLASH

COMMAND

SECOND

BYTE

THIRD

BYTE

FOURTH

BYTE

FIFTH

BYTE

SIXTH

BYTE

COMMENTS

Fast READ (1/1)

Dual READ (1/2)

2X READ (2/2)

Quad READ (1/4)

4X READ (4/4)

0x0B

0x3B

0xBB

0x6B

0xEB

ADDRS(0)

ADDRS(1)

ADDRS(2)

dummy

DATA(0)⁽¹⁾

8

4

8

6

See Table 8

Status(1) - Winbond

only

Read status

Write status

0x05

0x01

0x85

0x81

n/a

STATUS(0) STATUS(1)

0

Status(1) - Winbond

only

STATUS(0) STATUS(1)

Data(0)

Read Volatile

Conf Reg

Micron Only

Write Volatile

Conf Reg

Data(0)

Write Enable

Write Disable

Page program

0x06

0x04

0x02

0

ADDRS(0)

ADDRS(1)

ADDRS(2) DATA(0)⁽¹⁾

ADDRS(2)

Sector/Sub-sector

Erase (4KB)

0x20

0

Full Chip Erase

0xC7

0x66

Software Reset

Enable

Software Reset

Read Id

0x99

0x9F

Data(0)

Data(1)

Data(2)

System will only read

1st three bytes

(1) Only the first data byte is shown, data continues.

More detailed information on the various read operations supported are shown in Table 8.

Table 8. SPI Flash Supported Read Operation Details

NUMBER OF LINES FOR NUMBER OF LINES

NUMBER OF LINES FOR

DUMMY BYTES

NUMBER OF LINES FOR

RETURN DATA

READ TYPE⁽¹⁾

Fast Read (1/1)

OP-CODE⁽²⁾

FOR ADDRESS

1

2

1

4

1

2

1

4

1

2

4

Dual Read (1/2)

2X Read (2/2)

Quad Read (1/4)

4X Read (4/4)

(1) Flash vendors have diverged in naming and controlling their various read capabilities. As such, the Host needs to be very careful to fully

understand what is and what is not supported by the DLPC230-Q1. In general, for the supported devices, the DLPC230-Q1 only

supports "Extended SPI" or "SPI Mode" (as defined in the various Flash Data Sheets). It does not support "Dual SPI Mode", "Quad SPI

Mode", "QPI", "QPI Mode", "Dual QPI", "Quad QPI", "DTR", or "DDR". If uncertain, most devices will support "Fast Reads" in a manner

that is consistent with the DLPC230-Q1.

(2) System does not support Read op-codes being spread across more than one data line.

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Table 9. DLPC230-Q1 Compatible SPI Flash Device Options⁽¹⁾⁽²⁾

DENSITY (M-BITS)

VENDOR

PART NUMBER

PACKAGE SIZE

3.3-V Compatible Devices

128

Micron⁽³⁾

Macronix

MT25QL128ABA8ESF-OAAT

MX25L12835FMR-10G

MX25L12845GMR-10G

MX25L12839FXDQ-10G

SO16

BGA25

(1) For any devices not listed on this table, special care should be taken to insure that the requirements shown in Table 6 and Table 7 are

met.

(2) The boot application writes to the flash device status register once per 256 bytes during programming. Most flash devices discard status

register writes when the status content does not change. Some flash parts, such as Micron N25Q128A13ESFA0F, do not block status

writes when the status data is repeated. This causes the status register to exceed its maximum write limit after several programming

cycles, making them incompatible with the DLPC230-Q1. Note that the main application does not write to the status register.

(3) Care should be used when considering Numonyx versions of Micron serial flash devices as they typically do not have the 4KB sector

size needed to be DLPC230-Q1 compatible.

While the DLPC230-Q1 supports a variety of clock rates and read operation types, it does have a minimum flash

read bandwidth requirement which is shown in Table 10. This minimum read bandwidth can be met in any

number of different ways, with the variables being clock rate and read type. The Host is required to select a flash

device which can meet this minimum read bandwidth using the DLPC230-Q1 supported interface capabilities. It

should be noted that the Host will specify to the system (via flash parameter) the maximum supported clock rate

as well as the supported read types for their selected flash device, with which the DLPC230-Q1 SW will

automatically select an appropriate combination to maximize this bandwidth (which should at least meet the

minimum bandwidth requirement assuming a solution exists per the specified parameters).

Table 10. SPI Flash Interface Bandwidth Requirements

PARAMETER

MIN

MAX

UNIT

FLSH_RD_BW

Flash Read Interface Bandwidth

47.00

Mbps

8.3.5 Serial Flash Programming

The serial flash can be programmed through the DLPC230-Q1 using Host commands through the SPI or I²C

command and control interface.

8.3.6 Host Command and Diagnostic Processor Interfaces

The DLPC230-Q1 provides an interface port for Host commands as well as an interface port for a diagnostic

processor. There are two external communication ports dedicated for this use, one SPI interface and one I²C

interface. The host is allowed to specify (via ASIC input pin) which port will be used for which purpose (for

example, Host Command Interface → SPI, therefore "diagnostic processor"→ I²C - or they can be reversed).

The timing requirements for the SPI interface are shown in Host/Diagnostic Port SPI Interface Timing

Requirements. The timing requirements for the I²C interface are shown in Host/Diagnostic Port I²C Interface

Timing Requirements. The I²C slave address pair is 36h/37h.

8.3.7 GPIO Supported Functionality

The DLPC230-Q1 provides 32 general purpose I/O that are available to support a variety of functions for a

number of different product configurations. In general, most of these I/O will only support one specific function

based on a specific product configuration, although that function may be different for a different product

configuration. There are also a few of these I/O that have been reserved for use by the Host for whatever

function they might require. In addition, most of these I/O can also be made available for TI test and debug use.

Definitions for the HUD and Headlight product configurations are shown in Table 11 and Table 12.

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Table 11. GPIO Supported Functionality - HUD Product Configuration

(1)

SIGNAL NAME

DESCRIPTION

LED control feedback from the TPS99000-Q1. An external pull-down

resistor should be used (connects to TPS99000-Q1 Drive Enable).

GPIO_00 PMIC_CNTRL_OUT (input)

GPIO_01 PMIC_SEQ_STRT (output)

Sequence start output from the DLPC230-Q1. This should be connected

to the TPS99000-Q1 to time LED related actions and shadow

TPS99000-Q1 configuration registers. An external pull-down resistor

should be used.

LED optical comparison feedback. This is used to count light pulses

during each frame. This signal is active-low. An external pull-down

resistor should be used.

GPIO_02 PMIC_COMP_OUT (input)

LED Shunt Enable - shunts current from LEDs to allow faster LED turn-

off. An external pull-down resistor should be used.

GPIO_03 PMIC_LED_SEN (output)

GPIO_04 PMIC_LED_DEN (output)

LED FET Drive Enable - enables LED current switching and defines

LED pulse length. An external pull-down resistor should be used.

GPIO_05 Reserved for Future Use

GPIO_06 Host Available

An external pull-down resistor should be used

Available for general host use via Host Commands

An external pull-down resistor should be used

GPIO_07 Host Available

GPIO_08 Host Available

GPIO_09 Reserved for Future Use

GPIO_10 Reserved for Future Use

GPIO_11 Reserved for Future Use

GPIO_12 Reserved for Future Use

GPIO_13 Reserved for Future Use

GPIO_14 Reserved for Future Use

GPIO_15 PMIC_WD1 (output)

Periodic signal that the DLPC230-Q1 processor generates during

normal operation. TPS99000-Q1 monitors this signal and reports if this

signal stops pulsing. An external pull-down resistor should be used.

GPIO_16 Reserved for Future Use

GPIO_17 Host Available

An external pull-down resistor should be used

Available for general host use via Host Commands

An external pull-down resistor should be used

Available for general host use via Host Commands

GPIO_18 Reserved for Future Use

GPIO_19 Reserved for Future Use

GPIO_20 Reserved for Future Use

GPIO_21 Reserved for Future Use

GPIO_22 Reserved for Future Use

GPIO_23 Reserved for Future Use

GPIO_24 Reserved for Future Use

GPIO_25 Reserved for Future Use

GPIO_26 Host Available

GPIO_27 Host Available

GPIO_28 Host Available

GPIO_29 Host Available

GPIO_30 Host Available

GPIO_31 Host Available

(1) It is recommended that all unused Host Available GPIO be configured as a logic '0' output and be left unconnected in the system. If this

is not done, an external pull-down resistor (≤ 10 kΩ) should be used to avoid floating inputs.

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Table 12. GPIO Supported Functionality - Headlight Product Configuration

(1)

GPIO

SIGNAL NAME

DESCRIPTION

PWM 0 Output - This can be used for general purposes such as

controlling the level of an external light source.

GPIO_00 HL_PWM0 (output)

GPIO_01 PMIC_SEQ_STRT (output)

GPIO_02 HL_PWM1(output)

Sequence start output from the DLPC230-Q1. This should be connected

to the TPS99000-Q1 to time LED related actions and shadow

TPS99000-Q1 configuration registers. An external pull-down resistor

should be used.

PWM 1 Output - This can be used for general purposes such as

controlling the level of an external light source.

GPIO_03 Reserved for Future Use

GPIO_04 Reserved for Future Use

GPIO_05 Reserved for Future Use

GPIO_06 Host Available

An external pull-down resistor should be used

Available for general host use via Host Commands

An external pull-down resistor should be used

GPIO_07 Host Available

GPIO_08 Host Available

GPIO_09 Reserved for Future Use

GPIO_10 Reserved for Future Use

GPIO_11 Reserved for Future Use

GPIO_12 Reserved for Future Use

GPIO_13 Reserved for Future Use

GPIO_14 Reserved for Future Use

Periodic signal that the DLPC230-Q1 processor generates during

normal operation. TPS99000-Q1 monitors this signal and reports if this

signal stops pulsing. An external pull-down resistor should be used.

GPIO_15 PMIC_WD1 (output)

GPIO_16 Reserved for Future Use

GPIO_17 HL_PWM2 (output)

An external pull-down resistor should be used

PWM 2 Output - This can be used for general purposes such as

controlling the level of an external light source.

Connects to TPS99000-Q1 EXT_SMPL input. This sequence-aligned

signal can be configured to trigger TPS99000-Q1 ADC sampling.

GPIO_18 EXT_SMPL

GPIO_19 Reserved for Future Use

GPIO_20 Reserved for Future Use

GPIO_21 Reserved for Future Use

GPIO_22 Reserved for Future Use

GPIO_23 Reserved for Future Use

GPIO_24 Reserved for Future Use

GPIO_25 Reserved for Future Use

GPIO_26 Host Available

An external pull-down resistor should be used

Available for general host use via Host Commands

GPIO_27 Host Available

GPIO_28 Host Available

GPIO_29 Host Available

GPIO_30 Host Available

GPIO_31 Host Available

(1) It is recommended that all unused Host Available GPIO be configured as a logic '0' output and be left unconnected in the system. If this

is not done, an external pull-down resistor (≤ 10 kΩ) should be used to avoid floating inputs.

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8.3.8 Built-In Self Test (BIST)

The DLPC230-Q1 provides a significant amount of BIST support to help ensure the operational integrity of the

system. This BIST support is divided into two general BIST types, which are Non-Periodic and Periodic.

Non-Periodic BISTs are tests that are typically run one time, and are run outside of normal operation since their

activity will disturb the operation of the system. These tests are specified to be run either by a Flash parameter or

by a Host command. The Flash parameter specifies which tests are to be run during system power-up and

initialization. The Host command is used to select and specify the running of these tests when the system is in

Standby Mode (often just before the system is powered down). Some examples of non-periodic tests are: tests

for all of the ASIC memories, tests for the main data processing path, and testing of the DMD memory.

Periodic BISTs are tests that are run on an almost continual basis during normal ASIC operation. These tests are

managed (set up, enabled, results gathered and evaluated) automatically by the ASIC embedded software.

Some examples of periodic tests are: tuning and verification of the DMD High-Speed Interface, input source

monitoring (clock, active pixels, active lines), and external video checksum monitoring.

For more information on BISTs, refer to DLPC230-Q1 Programmer's Guide (DLPU041 for HUD and DLPU048 for

Headlight).

8.3.9 EEPROMs

The DLPC230-Q1 may optionally use an external I²C EEPROM memory device for storage of calibration data as

an alternative to storing calibration data in the SPI flash memory. The EEPROM must be connected to the

designated DLPC230-Q1 master I²C interface (MSTR_XXX).

The DLPC230-Q1 supports the EEPROM devices listed in Table 13.

Table 13. DLPC230-Q1 Supported EEPROMs

MANUFACTURER

STMicro

PART NUMBER

M24C64A125

M24C128A125

A24C64D

DENSITY (Kb)

PACKAGE SIZE

64

128

64

S08

STMicro

Atmel

A24C128C

128

8.3.10 Temperature Sensor

The DLPC230-Q1 requires an external temperature sensor (TMP411) to measure the DMD temperature through

a remote temperature sense diode residing within the DMD. The DLPC230-Q1 will also read the local

temperature reported by the TMP411 device. The TMP411 must be connected to the designated DLPC230-Q1

master I²C interface (MSTR_XXX).

The DLPC230-Q1 uses an averaged DMD temperature reading to manage the thermal environment and/or

operation of the DMD. This management occurs over the full range of temperatures supported by the DMD. This

temperature reading is used change sequence operation across the temperature range, and park the DMD when

it is operated outside of its allowable temperature specification.

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8.3.11 Debug Support

The DLPC230-Q1 contains a test point output port, TSTPT_(7:0), which provides the Host with the ability to

specify a number of initial system configurations, as well as to provide for ASIC debug support. These test points

are tri-stated while reset is applied, are sampled as inputs approximately 1.5 µs after reset is released, and then

switch to outputs once the input values have been sampled. The sampled and captured input state for each of

these signals is used to configure initial system configurations as specified in the table Pin Functions - Parallel

Port Input Data and Control in Pin Configuration and Functions.

There are three other signals (JTAGTDO(3:1)) that are sampled as inputs approximately 1.5 µs after reset is

released, and then switched to outputs. The sampled and captured state for each of these JTAGTDO signals is

used to configure the initial test mode output state of the TSTPT_(7:0) signals. Table 14 defines the test mode

selection for a few programmable output states for TSTPT_(7:0) as defined by JTAGTDO(3:1). For normal use

(that is, no debug required), the default state of x111 (using weak internal pull-ups) should be used to allow for

the normal use of these JTAG TDO signals.

To allow TI to make use of this debug capability, a jumper to an external pull-down is recommended for

JTAGTDO(3:1).

Table 14. Test Mode Selection Scenario Defined by JTAGTDO(3:1)⁽¹⁾

JTAGTDO(3:1) CAPTURED VALUE

TSTPT_(7:0) OUTPUT

x111 (DEFAULT)

x010

(NO SWITCHING ACTIVITY) CLOCK DEBUG OUTPUT

TSTPT(0)

TSTPT(1)

TSTPT(2)

TSTPT(3)

TSTPT(4)

TSTPT(5)

TSTPT(6)

TSTPT(7)

HI-Z

60 MHz

30 MHz

7.5 MHz

LOW

15 MHz

60 MHz

LOW

(1) These are only the default output selections. Software can reprogram the selection at any time.

8.4 Device Functional Modes

The DLPC230-Q1 has three operational modes which are enabled via software command via the Host control

interface. These modes are Standby, Display, and Calibration.

8.4.1 Standby Mode

The system will automatically enter Standby mode after power is applied. This is a reduced functional mode that

allows Flash update operations and Non-Periodic test operations. The DMD will be parked while the system is

operating in this mode and no source may be displayed.

8.4.2 Display Mode

This is the main operational mode of the system. In this mode, normal display activities occur. In this mode the

system may display video data and execute periodic BISTs. After system initialization, a host command can be

used to transition to this mode from Standby mode. Alternatively, a flash configuration setting can be set to allow

the system to automatically transition from standby to display mode after system initialization.

8.4.3 Calibration Mode

This mode is used to calibrate the system's light sources for the desired display properties. For head-up display

applications, this includes the ability to adjust individual color light sources to achieve the desired brightness and

color point.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLPC230-Q1 is designed to support projection-based automotive applications such as head-up display

(HUD) and high resolution headlight.

This DLP^®Products chipset consists of three components—the DLP553X-Q1 Digital Micromirror Device (DMD),

the DLPC230-Q1, and the TPS99000-Q1. The DMD is a light modulator consisting of tiny mirrors that are used

to form and project images. The DLPC230-Q1 is a controller for the DMD; it formats incoming video sources and

controls the timing of the DMD illumination sources and the DMD in order to display the incoming video source.

The TPS99000-Q1 is a controller for the illumination sources (LEDs or lasers) and a management IC for the

entire chipset. In conjunction, the DLPC230-Q1 and the TPS99000-Q1 can also be used for system-level

monitoring, diagnostics, and failure detection features.

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9.2 Typical Application

9.2.1 Head-Up Display

Figure 20 shows the system block diagram for a DLP^®technology HUD.

VLED

6.5 V

Pre-

Regulator

6.5 V

1.1 V

1.8 V

3.3 V

Supplies for

DLPC230 and DMD

VBATT

reg

Reg

3.3 V

LDO

(optional)

Power sequencing

and monitoring

High-side current

limiting

PROJ_ON

Optional SPI Monitor

12 bit

ADC

External ADC inputs for

general usage

LM3409

LED drive

AC3

ADC_CTRL(2)

SPI(4)

F

SPI_2

shunt(2)

E

T

s

RED

MPU

WD(2)

LED_SEL(4)

SEQ_START

S_EN

Ultra wide dimming

LED controller

GREEN

SPI_1

ECC

Low-side current

measurement

HOST_IRQ

OpenLDI

TPS99000-Q1

D_EN

DLPC230-Q1

Illumination

Optics

Host

photo diode

External watchdogs /

over brightness / and

other monitors

CTRL

4

DATA

24

COMPOUT

SEQ_CLK

Parallel

28

eSRAM

frame buffer

General

Purpose

PARKZ

RESETZ

INTZ

Photo diode

meas. system

PD neg

LDO

I2C(2)

SPI(4)

I2C_0

SPI_0

BIAS, RST, OFS

(3)

Spare

GPIO

GPIOx

I2C_1

Sys clock

monitor

DMD bias

regulator

VCC_FLASH

VCC_INTF

3.3 V

1.8 V

1.1 V

EEPROM

VIO

TMP411

(2)

DMD die temperature

VCORE

DLP5530-Q1

DMD

Sub-LVDS

Interface

sub-LVDS DATA

Control

Figure 20. HUD System Block Diagram

9.2.1.1 Design Requirements

The DLPC230-Q1 is a controller for the DMD and the timing of the RGB LEDs in the HUD. It requests the proper

timing and amplitude from the LEDs to achieve the requested color and brightness from the HUD across the

entire operating range. It synchronizes the DMD with these LEDs in order to display full-color video content sent

by the host.

The DLPC230-Q1 receives command and input video data from a host processor in the vehicle. Read and write

(R/W) commands can be sent using either the I²C bus or SPI bus. The bus that is not being used for R/W

commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an OpenLDI

bus or a parallel 24-bit bus. The SPI flash memory provides the embedded software for the DLPC230-Q1’s

embedded processor, color calibration data, and default settings. The TPS99000-Q1 provides diagnostic and

monitoring information to the DLPC230-Q1 using a SPI bus and several other control signals such as PARKZ,

INTZ, and RESETZ to manage power-up and power-down sequencing. The DLPC230-Q1 interfaces to a

TMP411 via I²C for temperature information.

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Typical Application (continued)

The outputs of the DLPC230-Q1 are LED drive information to the TPS99000-Q1, control signals to the DMD, and

monitoring and diagnostics information to the host processor. Based on a host requested brightness and the

operating temperature, the DLPC230-Q1 determines the proper timing and amplitudes for the LEDs. It passes

this information to the TPS99000-Q1 using a SPI bus and several additional control signals such as D_EN,

S_EN, and SEQ_STRT. It controls the DMD mirrors by sending data over a sub-LVDS bus. It can alert the host

about any critical errors using a HOST_IRQ signal.

The TPS99000-Q1 is a highly-integrated mixed-signal IC that controls DMD power, the analog response of the

LEDs, and provides monitoring and diagnostics information for the HUD system. The power sequencing and

monitoring blocks of the TPS99000-Q1 properly power up the DMD, provide accurate DMD voltage rails, as well

as monitor the system’s power rails during operation. The integration of these functions into one IC significantly

reduces design time and complexity. The highly accurate photodiode (PD) measurement system and the

dimming controller block precisely control the LED response. This enables a DLP technology HUD to achieve a

very high dimming range (> 5000:1) with accurate brightness and color across the temperature range of the

system. Finally, the TPS99000-Q1 has several general-purpose ADCs that developers can use for system-level

monitoring, such as over-brightness detection.

The TPS99000-Q1 receives inputs from the DLPC230-Q1, power rail voltages for monitoring, a photodiode that

is used to measure LED response, the host processor, and potentially several other ADC ports. The DLPC230-

Q1 sends commands to the TPS99000-Q1 over a SPI port and several other control signals. The TPS99000-Q1

includes watchdogs to monitor the DLPC230-Q1 and ensure that it is operating as expected. The power rails are

monitored by the TPS99000-Q1 to detect power failures or glitches and request a proper power down of the

DMD in case of an error. The photodiode’s current is measured and amplified using a transimpedance amplifier

(TIA) within the TPS99000-Q1. The host processor can read diagnostics information from the TPS99000-Q1

using a dedicated SPI bus, adding an independent monitoring path from the host processor. Additionally the host

can request the system to be turned on or off using a PROJ_ON signal. The TPS99000-Q1 has several general-

purpose ADCs that can be used to implement other system features such as over-brightness and over-

temperature detection.

The outputs of the TPS99000-Q1 are LED drive signals, diagnostic information, and error alerts to the DLPC230-

Q1. The TPS99000-Q1 has signals connected to the LM3409 buck controller for high power LEDs and to

discrete hardware that control the LEDs. The TPS99000-Q1 can output diagnostic information to the host and the

DLPC230-Q1 over two SPI busses. It also has signals such as RESETZ, PARKZ, and INTZ that can be used to

trigger power down or reset sequences.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video

data) and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS

interface driven with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the

DMD array that can be tilted ±12°. In a projection system, the mirrors are used as pixels in order to display an

image.

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Typical Application (continued)

9.2.2 Headlight

Figure 21 shows the system block diagram for a DLP^®headlight.

ENABLE (Illumination master on/off)

LED_SEL (4) Illumination and Shunt Enables

PWM signals (3) (Optional for analog level control)

VLED/laser

Supplies for

DLPC230 and DMD

6.5 V

Pre-

Regulator

VBATT.

6.5 V

3.3 V

1.1 V

1.8 V

3.3 V

reg

Reg

Power sequencing and

monitoring

LDO

(optional)

PROJ_ON.

Optional SPI Monitor.

12 bit

ADC

LED/laser

driver

External ADC inputs

for general usage

AC3

ADC_CTRL (3).

SPI (4).

with up to 64 HW timed

samples per frame

SPI_2

SPI_1

MPU

WD (2).

TPS99000-Q1

LED or

Laser

ECC

SEQ_START.

EXT_SMPL.

HOST_IRQ.

OpenLDI.

Host

LS_SENSE(N/P)

DLPC230-Q1

CTRL

4.

DATA

8/24.

External watchdogs / and

other monitors

SEQ_CLK.

eSRAM

frame buffer

Parallel

graphics port

illumination

optics

PARKZ.

RESETZ.

INTZ.

projection

optics

Photo diode

PD neg

Measurement

LDO

I2C (2).

SPI (4).

I2C_0

SPI_0

System

BIAS, RST, OFS

(3).

on

state

Sys clock

DMD bias

GPIOx

Spare GPIO

monitor

regulator

VCC_FLASH

VCC_INTF

3.3 V

1.8 V

1.1 V

VIO

I2C_1

DMD

TMP411

(2).

DMD die temperature

VCORE

DLP5531-Q1

sub-LVDS DATA.

Control.

Sub-LVDS

Interface

Figure 21. Headlight System Block Diagram

9.2.2.1 Design Requirements

The DLPC230-Q1 is a controller for the DMD and the light sources in the DLP technology headlight. It receives

input video from the host and synchronizes DMD and light source timing in order to achieve the desired video

output. The DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes these video

segments with light source timing in order to create video with grayscale shading.

The DLPC230-Q1 receives command and input video data from a host processor in the vehicle. R/W commands

can be sent using either the I²C bus or SPI bus. The bus that is not being used for R/W commands can be used

as a read-only bus for diagnostic purposes. Input video can be sent over an OpenLDI bus or a parallel 24-bit

bus. The 24-bit bus can be limited to only 8-bits of data for single light source systems such as headlights. The

SPI flash memory provides the embedded software for the DLPC230-Q1’s embedded processor and default

settings. The TPS99000-Q1 provides diagnostic and monitoring information to the DLPC230-Q1 using a SPI bus

and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down

sequencing. The TMP411 uses an I²C interface to provide the DMD array temperature to the DLPC230-Q1.

The outputs of the DLPC230-Q1 are configuration and monitoring commands to the TPS99000-Q1, timing

controls to the LED or laser driver, control signals to the DMD, and monitoring and diagnostics information to the

host processor. The DLPC230-Q1 communicates with the TPS99000-Q1 over a SPI bus. It uses this to configure

the TPS99000-Q1 and to read monitoring and diagnostics information from the TPS99000-Q1. The DLPC230-Q1

sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD mirror timing. The

control signals to the DMD are sent using a sub-LVDS interface.

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Typical Application (continued)

The TPS99000-Q1 is a highly integrated mixed-signal IC that controls DMD power, the timing of the LEDs or

lasers, and provides monitoring and diagnostics information for the DLP technology headlight system. The power

sequencing and monitoring blocks of the TPS99000-Q1 properly power up the DMD and provide accurate DMD

voltage rails, and then monitor the system’s power rails during operation. The integration of these functions into

one IC significantly reduces design time and complexity. The TPS99000-Q1 also has several output signals that

can be used to control a variety of LED or laser driver topologies. The TPS99000-Q1 also has several general-

purpose ADCs that designers can use for system level monitoring.

The TPS99000-Q1 receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and

potentially several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the

TPS99000-Q1 over a SPI bus and several other control signals. The TPS99000-Q1 includes watchdogs to

monitor the DLPC230-Q1 and ensure that it is operating as expected. The power rails are monitored by the

TPS99000-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case

of an error. The host processor can read diagnostics information from the TPS99000-Q1 using a dedicated SPI

bus. Additionally the host can request the image to be turned on or off using a PROJ_ON signal. Lastly, the

TPS99000-Q1 has several general-purpose ADCs that can be used to implement system level monitoring

functions.

The outputs of the TPS99000-Q1 are diagnostic information and error alerts to the DLPC230-Q1, and control

signals to the LED or laser driver. The TPS99000-Q1 can output diagnostic information to the host and the

DLPC230-Q1 over two SPI busses. In case of critical system errors, such as power loss, it outputs signals to the

DLPC230-Q1 that trigger power down or reset sequences. It also has output signals that can be used to

implement various LED or laser driver topologies.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video

data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS

interface with the DLPC230-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD

array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.

9.2.2.2 Headlight Video Input

The DLPC230-Q1 accepts 8-bit grayscale video data when used in headlight applications.

When using the parallel video port, PDATA_[16-23] are utilized (red input when using a typical RGB888

mapping). PDATA_[0-15] should be tied to ground.

When using the OpenLDI video ports, data bits R0 - R7 are utilized. B0-B7 and G0-G7 are unused.

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10 Power Supply Recommendations

10.1 Power Supply Management

The TPS99000-Q1 manages power for the DLPC230-Q1 and DMD. See Power Supply and Reset Timing

Requirements for all power sequencing and timing requirements.

10.2 Hot Plug Usage

The DLPC230-Q1 does not support Hot Plug use (for itself or for any DMD connected to the system). As such,

the system should always be powered down prior to removal of the ASIC or DMD from any system.

10.3 Power Supply Filtering

The following filtering circuits are recommended for the various supply inputs. High frequency 0.1-µF capacitors

should be evenly distributed amongst the power balls and placed as close to the power balls as possible.

1.1 V

VCCK

10 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 22. VCCK Recommended Filter

100Q @ 100 MHz

35 mQ 5/ Œꢀ•]•šꢁvꢂꢀ

1.1 V

VCC11A_LVDS

2.2 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 23. VCC11A_LVDS Recommended Filter

100Q @ 100 MHz

35 mQ 5/ Œꢀ•]•šꢁvꢂꢀ

1.1 V

VCC11A_DDI_0

VCC11A_DDI_1

2.2 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 24. VCC11A_DDI Recommended Filter

100Q @ 100 MHz

35 mQ 5/ Œꢀ•]•šꢁvꢂꢀ

1.8 V

VCC18A_LVDS

10 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 25. VCC18A_LVDS Recommended Filter

3.3 V

VCC33IO

0.1 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 26. VCC33IO Recommended Filter

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

Power Supply Filtering (continued)

3.3 V

VCC33IO_FLSH

0.1 …F

Figure 27. VCC33IO_FLSH Recommended Filter

3.3 V

VCC33IO_INTF

0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 28. VCC33IO_INTF Recommended Filter

100Q @ 100 MHz

35 mQ 5/ Œꢀ•]•šꢁvꢂꢀ

3.3 V

VCC33A_LVDS

2.2 …F 0.1 …F 0.1 …F 0.1 …F 0.1 …F

Figure 29. VCC33A_LVDS Recommended Filter

11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power

The following guidelines are recommended to achieve desired ASIC performance relative to the internal PLL.

The DLPC230-Q1 contains two internal PLLs which have dedicated analog supplies (VCC11AD_PLLM,

GND11AD_PLLM, VCC11AD_PLLD, GND11AD_PLLD). At

a

minimum, VCC11AD_PLLx power and

GND11AD_PLLx ground pins should be isolated using a simple passive filter consisting of two series Ferrites

and two shunt capacitors (to widen the spectrum of noise absorption). Recommended values and layout are

shown in Table 15 and Figure 30 respectively.

Table 15. Recommended PLL Filter Components

COMPONENT

Shunt Capacitor

PARAMETER

Capacitance

RECOMMENDED VALUE

UNIT

µF

0.1

1.0

Capacitance

µF

Impedance at 100 MHz

DC Resistance

> 100

< 0.40

Ω

Series Ferrite

Since the PCB layout is critical to PLL performance, it is vital that the quiet ground and power are treated like

analog signals. Additional design guidelines are as follows:

•

All four components should be placed as close to the ASIC as possible

It’s especially important to keep the leads of the high frequency capacitors as short as possible

A capacitor of each value should be connected across VCC11AD_PLLM / GND11AD_PLLM and

VCC11AD_PLLD / GND11AD_PLLD respectively on the ASIC side of the Ferrites

•

VCC11AD_PLLM and VCC11AD_PLLD must be a single trace from the DLPC230-Q1 to both capacitors and

then through the series ferrites to the power source

The power and ground traces should be as short as possible, parallel to each other, and as close as possible

to each other

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Signal Via

PCB Pad

ASIC Pad

Via to Common Analog

Digital Board Power Plane

Via to Common Analog

Digital Board Ground Plane

A

B

C

D

E

22

PLL_

REF

CLK_I

Signal

15

14

Crystal Circuit

PLL_

REF

CLK_O

Signal

Local

FB

GND

Decoupling

for the PLL

Digital Supply

GND11

AD_PLL

M

VCC11

AD_PLL

M

13

12

1.1 V

PWR

GND

FB

GND11

AD_PLL

D

VCC11

Signal

VDD

AD_PLL

1.1 V

PWR

D

FB

Figure 30. PLL Filter Layout

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11.1.2 DLPC230-Q1 Reference Clock

The DLPC230-Q1 requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply

this reference. The recommended crystal configurations and reference clock frequencies are listed in Table 16,

with additional required discrete components shown in Figure 31 and defined in Table 16.

PLL_REFCLK_I

PLL_REFCLK_O

R

FB

R

S

Crystal

C

L2

L1

A. C_L= Crystal load capacitance

B. R_FB= Feedback Resistor

Figure 31. Discrete Components Required When Using Crystal

11.1.2.1 Recommended Crystal Oscillator Configuration

Table 16. Recommended Crystal Configuration

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

16

Crystal nominal frequency

MHz

PPM

Ω

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum crystal equivalent series resistance (ESR)

Crystal load capacitance

50

10

pF

Temperature range

–40°C to +105°C

°C

Drive level (nominal)

100

1

µW

MΩ

pF

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

(1)

See equation in

(2)

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) CL1 = 2 × (CL – Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin

associated with the ASIC pin pll_refclk_i.

(2) CL2 = 2 × (CL – Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin

associated with the ASIC pin pll_refclk_o.

The crystal circuit in the DLPC230-Q1 ASIC has dedicated power (VCC3IO_COSC) and ground

(GNDIOLA_COSC) pins, with the recommended filtering shown in Figure 32.

100Q @ 100MHz

FB

3.3 V

VCC3IO_COSC

0.1uF

GNDIOLA_COSC

Figure 32. Crystal Power Supply Filtering

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Table 17. DLPC230-Q1 Recommended Crystal Parts

FREQUENCY

TOLERANCE,

FREQUENCY

STABILITY,

LOAD

CAPACITANCE

OPERATING

TEMPERATURE

MANUFACTURER

PART NUMBER

SPEED

ESR

AGING/YEAR

Freq Tolerance:

±10 ppm

TXC

AM16070006⁽¹⁾

16 MHz

Freq Stability:

±50 ppm

50-Ω max

10 pF

–40°C to +125°C

Aging/Year: ±3 ppm

(1) This device requires a 3-kΩ series resister to limit power.

If an external oscillator is used, the oscillator output must drive the PLL_REFCLK_O pin on the DLPC230-Q1

ASIC, the PLL_REFCLK_I pin should be left unconnected, and the OSC_BYPASS pin must = logic HIGH.

11.1.3 DMD Interface Layout Considerations

The DLPC230-Q1 ASIC sub-LVDS HS/LS differential interface waveform quality and timing is dependent on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

DLPC230-Q1 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding

data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB

design recommendations are provided in Table 18 and Figure 33 as a starting point for the customer.

Table 18. PCB Recommendations for DMD Interface^{(1) (2)}

PARAMETER

Trace Width

MIN

4

MAX

UNIT

mils

kΩ

T_W

T_S

Intra-lane Trace Spacing

Inter-lane Trace Spacing

Resistor - Bandgap Reference

4

T_SPP

R_BGR

2 * (T_S+ T_W

)

42.2 (1%)

(1) Recommendations to achieve the desired nominal differential impedance as specified by Tx_loadin DMD High-Speed Sub-LVDS

Electrical Characteristics and DMD Low-Speed Sub-LVDS Electrical Characteristics.

(2) If using the minimum trace width and spacing to escape the ASIC ball field, widening these out after escape would be desirable if

practical to achieve the target 100-Ω impedance (e.g. to reduce transmission line losses).

Tw

Ts

Tw

Ts

Tw

Tspp

Signal Traces

Differential Pair #1

Differential Pair #2

Ground Plane

Figure 33. DMD Differential Layout Recommendations

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11.1.4 General PCB Recommendations

TI recommends 1-oz copper power planes and 2-oz copper ground planes in the PCB design to achieve the

required thermal connectivity, with:

•

A minimum of 4 power and ground planes

A copper plane beneath the thermal ball array containing a via farm with the following attributes

–

Copper plane area (top side of PCB, under package) = 8.0 mm × 8.0 mm

Copper plane area (bottom side of PCB, opposite of package) = 6.0 mm × 6.0 mm

Thermal via quantity = 7 × 7 array of vias

Thermal via size = 0.25 mm (10 mils)

Thermal via plating thickness = 0.05-mm (2-mils) wall thickness

•

PCB copper coverage per layer

–

Power and Ground layers: 90% minimum coverage

Top/Bottom signal layers (ground fill to achieve coverage): 70% minimum coverage with 1.5-oz copper.

11.1.5 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused

ASIC input pins be tied through a pull-up resistor to its associated power supply or a pull-down to ground unless

specifically noted otherwise in Pin Configuration and Functions. For ASIC inputs with an internal pull-up or pull-

down resistors, it is unnecessary to add an external pull-up or pull-down unless specifically recommended. Note

that internal pull-up and pull-down resistors are weak and should not be expected to drive the external line.

When external pull-up or pull-down resistors are needed for pins that have built-in weak pull-ups or pull-downs,

use the value specified in Table 2.

Unused output-only pins should never be tied directly to power or ground, but can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then they should be

pulled-up (or pulled-down) using an appropriate, dedicated resistor.

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11.1.6 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 19. Max Pin-to-Pin PCB Interconnect Recommendations - DMD

ASIC INTERFACE

SIGNAL INTERCONNECT TOPOLOGY⁽¹⁾⁽²⁾

UNIT

SINGLE BOARD SIGNAL ROUTING

MULTI-BOARD SIGNAL ROUTING

LENGTH

DMD

LENGTH

DMD_HS0_CLK_P

DMD_HS0_CLK_N

6.0

(152.4)

in

(mm)

(3)

See

DMD_HS0_WDATA0_P

DMD_HS0_WDATA0_N

DMD_HS0_WDATA1_P

DMD_HS0_WDATA1_N

DMD_HS0_WDATA2_P

DMD_HS0_WDATA2_N

DMD_HS0_WDATA3_P

DMD_HS0_WDATA3_N

6.0

(152.4)

in

(mm)

(3)

See

DMD_HS0_WDATA4_P

DMD_HS0_WDATA4_N

DMD_HS0_WDATA5_P

DMD_HS0_WDATA5_N

DMD_HS0_WDATA6_P

DMD_HS0_WDATA6_N

DMD_HS0_WDATA7_P

DMD_HS0_WDATA7_N

DMD_HS1_CLK_P

DMD_HS1_CLK_N

6.0

(152.4)

in

(mm)

(3)

See

DMD_HS1_WDATA0_P

DMD_HS1_WDATA0_N

DMD_HS1_WDATA1_P

DMD_HS1_WDATA1_N

DMD_HS1_WDATA2_P

DMD_HS1_WDATA2_N

DMD_HS1_WDATA3_P

DMD_HS1_WDATA3_N

6.0

(152.4)

in

(mm)

(3)

See

DMD_HS1_WDATA4_P

DMD_HS1_WDATA4_N

DMD_HS1_WDATA5_P

DMD_HS1_WDATA5_N

DMD_HS1_WDATA6_P

DMD_HS1_WDATA6_N

DMD_HS1_WDATA7_P

DMD_HS1_WDATA7_N

DMD_LS0_CLK_P

DMD_LS0_CLK_N

6.5

(165.1)

in

(mm)

(3)

See

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

6.5

(165.1)

in

(mm)

(3)

See

6.5

(165.1)

in

(mm)

(3)

DMD_LS0_RDATA

DMD_LS1_RDATA

DMD_DEN_ARSTZ

See

6.5

(165.1)

in

(mm)

(3)

See

in

(mm)

N/A

(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to board variations, these are impossible to define. Any board designs should SPICE simulate with the ASIC IBIS models to ensure

signal routing lengths do not exceed requirements.

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Table 20. Max Pin-to-Pin PCB Interconnect Recommendations - TPS99000-Q1

(1)(2)

ASIC INTERFACE

TPS99000-Q1

PMIC_LEDSEL(3)

SIGNAL INTERCONNECT TOPOLOGY

UNIT

SINGLE BOARD SIGNAL ROUTING

LENGTH

MULTI-BOARD SIGNAL ROUTING

LENGTH

PMIC_LEDSEL(2)

PMIC_LEDSEL(1)

PMIC_LEDSEL(0)

PMIC_ADC3_CLK

PMIC_ADC3_MOSI

PMIC_ADC3_MISO

PMIC_SEQ_STRT

6.0

(152.4)

in

(mm)

(3)

See

(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to board variations, these are impossible to define. Any board designs should SPICE simulate with the ASIC IBIS models to ensure

signal routing lengths do not exceed requirements.

Table 21. High-Speed PCB Signal Routing Matching Requirements

(1)(2)

SIGNAL GROUP LENGTH MATCHING

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD_HS0_WDATA0_P

DMD_HS0_WDATA0_N

DMD_HS0_WDATA1_P

DMD_HS0_WDATA1_N

DMD_HS0_WDATA2_P

DMD_HS0_WDATA2_N

DMD_HS0_WDATA3_P

DMD_HS0_WDATA3_N

DMD_HS0_CLK_P

DMD_HS0_CLK_N

±1.0

(±25.4)

in

(mm)

DMD⁽³⁾

DMD_HS0_WDATA4_P

DMD_HS0_WDATA4_N

DMD_HS0_WDATA5_P

DMD_HS0_WDATA5_N

DMD_HS0_WDATA6_P

DMD_HS0_WDATA6_N

DMD_HS0_WDATA7_P

DMD_HS0_WDATA7_N

±0.025

(±0.635)

in

(mm)

DMD⁽⁴⁾

DMD_HS0_x_P

DMD_HS0_x_N

(1) These routing requirements are specific to the PCB routing. Internal package routing mismatches in the DLPC230-Q1 and DMD have

already been accounted for in these requirements.

(2) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.

(3) This is an inter-pair specification (that is, differential pair to differential pair within the group).

(4) This is an intra-pair specification (that is, length mismatch between P and N for the same pair).

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Table 21. High-Speed PCB Signal Routing Matching Requirements (continued)

(1)(2)

SIGNAL GROUP LENGTH MATCHING

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD_HS1_WDATA0_P

DMD_HS1_WDATA0_N

DMD_HS1_WDATA1_P

DMD_HS1_WDATA1_N

DMD_HS1_WDATA2_P

DMD_HS1_WDATA2_N

DMD_HS1_WDATA3_P

DMD_HS1_WDATA3_N

DMD_HS1_CLK_P

DMD_HS1_CLK_N

±1.0

(±25.4)

in

(mm)

DMD⁽³⁾

DMD_HS1_WDATA4_P

DMD_HS1_WDATA4_N

DMD_HS1_WDATA5_P

DMD_HS1_WDATA5_N

DMD_HS1_WDATA6_P

DMD_HS1_WDATA6_N

DMD_HS1_WDATA7_P

DMD_HS1_WDATA7_N

±0.025

(±0.635)

in

(mm)

DMD⁽⁴⁾

DMD⁽³⁾

DMD⁽⁴⁾

DMD

DMD_HS1_x_P

DMD_HS1_x_N

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

DMD_LS0_CLK_P

DMD_LS0_CLK_N

±1.0

(±25.4)

in

(mm)

±0.025

(±0.635)

in

(mm)

DMD_LS0_x_P

DMD_LS0_x_N

DMD_LS0_RDATA

DMD_LS1_RDATA

in

(mm)

(5)

N/A

in

(mm)

DMD

DMD_DEN_ARSTZ

N/A

PMIC_LEDSEL(3)

PMIC_LEDSEL(2)

PMIC_LEDSEL(1)

PMIC_LEDSEL(0)

PMIC_SEQ_STRT

PMIC_ADC3_MOSI

±1.0

(±25.4)

in

(mm)

TPS99000-Q1

PMIC_ADC3_CLK

(5) For legacy DMD support, the ASIC provides a single-ended low-speed write interface. The primary low-speed write control interface to

the DMD is differential. The low-speed read control interface from the DMD is single-ended, and makes use of the differential write

clock. As such, a routing mismatch between these is not applicable.

11.1.7 Number of Layer Changes

•

Single-ended signals: Minimize the number of layer changes.

Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair

should not change layers.

11.1.8 Stubs

Stubs should be avoided.

•

11.1.9 Terminations

•

No external termination resistors are required on the DMD_HS or DMD_LS differential signals.

The DMD_LS0_RDATA and DMD_LS1_RDATA single-ended signal paths should include a 10-Ω series

termination resistor located as close as possible to the corresponding DMD pin.

•

DMD_DEN_ARSTZ does not typically require a series resistor, however, for a long trace, one might be

needed to reduce undershoot/overshoot.

64

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

11.1.10 Routing Vias

•

The number of vias on each DMD_HS and DMD_LS signal should be minimized and should not exceed two.

If two are required, one should be placed at each end of the line (one at the ASIC and one at the DMD).

11.2 Thermal Considerations

The underlying thermal limitation for the DLPC230-Q1 is that the maximum operating junction temperature (T_J)

not be exceeded (this is defined in the Recommended Operating Conditions). This temperature is dependent on

operating ambient temperature, airflow, PCB design (including the component layout density and the amount of

copper used), power dissipation of the DLPC230-Q1, and power dissipation of surrounding components. The

DLPC230-Q1’s package is designed primarily to extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

TI highly recommends that once the host PCB is designed and built that the thermal performance be measured

and validated.

To do this, measure the top center case temperature under the worse case product scenario (max power

dissipation, max voltage, max ambient temperature) and validate that the maximum recommended case

temperature (T_C) is not exceeded. This specification is based on the measured φ_JTfor the DLPC230-Q1 package

and provides a relatively accurate correlation to junction temperature. Take care when measuring this case

temperature to prevent accidental cooling of the package surface. TI recommends a small (approximately 40

gauge) thermocouple. The bead and thermocouple wire should contact the top of the package and be covered

with a minimal amount of thermally conductive epoxy. The wires should be routed closely along the package and

the board surface to avoid cooling the bead through the wires.

65

DLPC230-Q1

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www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.1.2 器件命名规则

12.1.2.1 器件标记

Line 1

Line 2

Line 3

标记定义：

第 1

行：

TI 器件型号：工程样片

X = 工程样片

DLPC230 = 器件 ID

空白或 A、B、C ... = 器件修订版本

T = 温度设计器

ZDQ = 封装符号

Q1 = 通过汽车认证

TI 器件型号：生产

DLPC230 = 器件 ID

空白或 A、B、C ... = 器件修订版本

T = 温度设计器

ZDQ = 封装符号

Q1 = 通过汽车认证

第 2

行：

供应商批次和制造信息

供应商年和周代码

XXXXX = 制造批次编号

-XX = 制造子批次

X（末尾的 X） = 组装子批次

制造编号为 UMC12A。同样，批次编号的首个字符为 K

第 3

行：

YY = 年

WW = 周

示例：1614 - 器件于 2016 年第 14 周制造

12.1.2.2 视频时序参数定义

每帧有效扫描行数 (ALPF) 定义一帧中包含可显示数据的行数：ALPF 是每帧总行数 (TLPF) 的子集。

每行有效像素 (APPL) 定义包含可显示数据的一行中的像素时钟数：APPL 是每行总像素 (TPPL) 的子集。

66

DLPC230-Q1

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ZHCSIF8E –DECEMBER 2015–REVISED JUNE 2018

器件支持 (接下页)

水平后沿 (HBP) 消隐水平同步之后，第一个有效像素之前的消隐像素时钟数量。注意：HBP 时间参考各自同步

信号的前缘（有效）边沿。

水平前沿 (HFP) 消隐最后一个有效时钟之后，水平同步之前的消隐像素时钟的数量。

水平同步 (HS) 定义水平间隔（行）开始的时序基准点。绝对基准点由 HS 信号的有效边沿定义。有效边沿（源定

义的上升沿或下降沿）是测量所有水平消隐参数的基准。

每帧总行数 (TLPF) 以行数定义垂直扫描时间（帧时间）：TLPF = 每帧总行数（有效和无效行）。

每行总像素 (TPPL) 以像素时钟数定义水平行扫描时间：TPPL = 每行总像素时钟数（有效和无效像素时钟）

垂直同步 (VS) 定义垂直间隔（帧）开始的时序基准点。这个绝对基准点由 VS 信号的有效边沿定义。有效边沿

（源定义的上升沿或下降沿）是测量所有垂直消隐参数的基准。

垂直后沿 (VBP) 消隐垂直同步后，第一个有效行之前的消隐行的数量。

垂直前沿 (VFP) 消隐在最后一个有效行后，垂直同步前的消隐行数。

TPPL

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

ALPF

(HBP)

(HFP)

Vertical Front Porch (VFP)

12.2 商标

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

67

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC230-Q1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP553x-Q1 芯片组的 DLP® 汽车数字微镜器件 (DMD) 控制器控制器
文件：	总71页 (文件大小：1546K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC230-Q1 [TI]

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