DLPC3421 [TI]
DLP® display controller for DLP160CP (0.16 nHD) DMD;
| 型号： | DLPC3421 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® display controller for DLP160CP (0.16 nHD) DMD |
| 文件： | 总63页 (文件大小：2098K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLPC3421
ZHCSOV7A –OCTOBER 2021 –REVISED JANUARY 2022
DLPC3421 Display Controller
1 特性
3 说明
• 适用于DLP160CP (0.16 nHD) DMD 的显示控制器
DLPC3421 数字控制器是 DLP160CP (0.16 nHD) 芯片
组的组成部分，为 DLP160CP 数字微镜器件 (DMD)
的运行提供支持。DLPC3421 控制器在用户电子设备
与 DMD 之间提供了一个便捷的多功能接口，可支持小
外形尺寸的低功耗显示应用。
– 支持高达WVGA 的输入分辨率
– 支持接口训练的低功耗DMD 接口
• 输入帧速率高达360 Hz
• 像素数据处理：
访问TI DLP®Pico™ 显示技术入门页面，并查看编程人
员指南了解详情。
– 内容自适应照明控制(CAIC)
– 局部亮度增强(LABB)
– 1D 梯形校正
该芯片组提供现成的资源，可帮助用户加快设计周期。
这些资源包括 可直接用于生产环境的光学模块、光学
模块制造商和设计公司。
– 色彩坐标调整
– 主动电源管理处理
– 可编程degamma
– 色彩空间转换
器件信息
器件型号(1)
DLPC3421
封装尺寸（标称值）
– 4:2:2 至4:4:4 色度插值
• 24 位输入像素接口支持：
封装
NFBGA (176)
7.00mm × 7.00mm
– 并行或BT656 接口协议
– 高达155MHz 的像素时钟
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
– 多个输入像素数据格式选项
• MIPI® DSI（显示屏串行接口）3 类：
– 1 至4 条通道，通道速率高达470Mbps
• 支持外部闪存
• 断电时自动DMD 停止
• 嵌入式帧存储器(eDRAM)
• 系统特性：
V
LED
SYSPWR
1.8 V external
PROJ_ON
1.8 V
2
I C
GPIO_8
SPI1
DLPA200x
RESETZ
PARKZ
R
LIM
HOST_IRQ
DSI (10)
VDDLP12
VDD
– I2C 器件控制
– 可编程启动界面
– 可编程LED 电流控制
– 显示图像旋转
Parallel
(28)
Illumination
optics
DLPC34xx
SPI0
VCC_18
V
V
V
,
OFFSET
SPI (4)
1.8 V
,
BIAS
RESET
• 与DLPA2000 和DLPA2005 PMIC（电源管理集成
电路）及LED 驱动器配对使用
CTRL
DMD
VCC_INTF
VCC_FLSH
Sub-LVDS
1.8 V
2 应用
• 移动投影仪
• 智能显示
• 智能手机
简化版应用
• 增强现实眼镜
• 智能家居显示
• Pico 投影仪
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS231
DLPC3421
www.ti.com.cn
ZHCSOV7A –OCTOBER 2021 –REVISED JANUARY 2022
Table of Contents
7.1 Overview...................................................................25
7.2 Functional Block Diagram.........................................25
7.3 Feature Description...................................................26
7.4 Device Functional Modes..........................................39
7.5 Programming............................................................ 39
8 Application and Implementation..................................40
8.1 Application Information............................................. 40
8.2 Typical Application.................................................... 40
9 Power Supply Recommendations................................42
9.1 PLL Design Considerations...................................... 42
9.2 System Power-Up and Power-Down Sequence....... 42
9.3 Power-Up Initialization Sequence.............................46
9.4 DMD Fast Park Control (PARKZ)..............................47
9.5 Hot Plug I/O Usage...................................................47
10 Layout...........................................................................48
10.1 Layout Guidelines................................................... 48
10.2 Layout Example...................................................... 57
11 Device and Documentation Support..........................58
11.1 Device Support........................................................58
11.2 Related Documentation...........................................60
11.3 Related Links.......................................................... 60
11.4 接收文档更新通知................................................... 60
11.5 支持资源..................................................................60
11.6 Trademarks............................................................. 60
11.7 Electrostatic Discharge Caution..............................60
11.8 术语表..................................................................... 60
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 11
6.1 Absolute Maximum Ratings...................................... 11
6.2 ESD Ratings..............................................................11
6.3 Recommended Operating Conditions.......................12
6.4 Thermal Information..................................................12
6.5 Power Electrical Characteristics............................... 13
6.6 Pin Electrical Characteristics.................................... 14
6.7 Internal Pullup and Pulldown Electrical
Characteristics.............................................................16
6.8 DMD Sub-LVDS Interface Electrical
Characteristics.............................................................17
6.9 DMD Low-Speed Interface Electrical
Characteristics.............................................................18
6.10 System Oscillator Timing Requirements.................19
6.11 Power Supply and Reset Timing Requirements......19
6.12 Parallel Interface Frame Timing Requirements.......20
6.13 Parallel Interface General Timing Requirements.... 21
6.14 BT656 Interface General Timing Requirements......22
6.15 DSI Host Timing Requirements...............................22
6.16 Flash Interface Timing Requirements..................... 23
6.17 Other Timing Requirements....................................24
6.18 DMD Sub-LVDS Interface Switching
Characteristics.............................................................24
6.19 DMD Parking Switching Characteristics................. 24
6.20 Chipset Component Usage Specification............... 24
7 Detailed Description......................................................25
Information.................................................................... 60
13 Package Option Addendum........................................61
13.1 Packaging Information............................................ 61
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2021) to Revision A (January 2022)
Page
• 将器件状态从“预告信息”更改为“量产数据”。.............................................................................................1
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5 Pin Configuration and Functions
图5-1. ZVB Package 176-Pin NFBGA Bottom View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
P
CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM
SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0
A
B
C
D
E
F
LK
DATA
DATAH_P DATAG_P
DATAF_P
DATAE_P
DATAD_P
DATAC_P
DATAB_P
DATAA_P
DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
N
ARSTZ
DATA
DATAH_N DATAG_N
DATAF_N
DATAE_N
DATAD_N
DATAC_N
DATAB_N
DATAA_N
HWTEST_E
N
DD3P
DD3N
VDD
VDD
VSS
VCC
VSS
VSS
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VCC
VDD
VSS
VCC
RESETZ SPI0_CSZ1
PARKZ
VDD
VSS
VDD
VSS
VDD
VSS
VCC
VDD
GPIO_00
GPIO_02
GPIO_04
GPIO_06
GPIO_08
GPIO_10
GPIO_12
GPIO_14
GPIO_16
GPIO_01
GPIO_03
GPIO_05
GPIO_07
GPIO_09
GPIO_11
GPIO_13
GPIO_15
GPIO_17
GPIO_19
TSTPT_7
TSTPT_5
TSTPT_3
DD2P
DCLKP
DD1P
DD2N
DCLKN
DD1N
VDD
VSS
VSS
VDD
VSS
VCC_FLSH
VDD
VCC
VCC
VSS
VSS
VDD
VSS
VDD
VSS
VDD
RREF
DD0P
DD0N
VSS_PLLM
G
H
J
PLL_REFCL
K_I
VDD_PLLM VSS_PLLD
PLL_REFCL
K_O
VDD_PLLD
PDATA_0
PDATA_2
PDATA_4
PDATA_6
VSS
VDD
PDATA_1
PDATA_3
PDATA_5
PDATA_7
VSYNC_WE
PDATA_8
K
L
VSS
VCC_INTF
VCC_INTF
PCLK
VSS
VDD
3DR
VCC_INTF
VSS
VDD
VDD
VCC
JTAGTMS1 GPIO_18
M
N
P
R
PDM_CVS_
TE
HSYNC_CS
VCC_INTF HOST_IRQ IIC0_SDA
IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1
TSTPT_6
TSTPT_4
TSTPT_2
DATEN_CM
D
PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK
JTAGTDI
TSTPT_1
PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22
IIC1_SDA
IIC1_SCL
TSTPT_0
Note: The lower image view is from the top.
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表5-1. Test Pins and General Control
PIN
I/O
TYPE(4)
DESCRIPTION
NAME
HWTEST_EN
NO.
Manufacturing test enable signal. Connect this signal directly to ground on the
PCB for normal operation.
C10
I
6
DMD fast park control (active low Input with a hysteresis buffer). This signal is
used to quickly park the DMD when loss of power is imminent. The longest
lifetime of the DMD may not be achieved with the fast park operation;
therefore, this signal is intended to only be asserted when a normal park
operation is unable to be completed. The PARKZ signal is typically provided
from the DLPA200x interrupt output signal.
PARKZ
C13
I
6
JTAGTCK
JTAGTDI
P12
P13
I
I
6
6
1
1
6
6
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
TI internal use. Leave this pin unconnected.
JTAGTDO1
JTAGTDO2
JTAGTMS1
JTAGTMS2
N13(1)
N12(1)
M13
O
O
I
N11
I
TI internal use.
This pin must be tied to ground, through an external resistor for normal
operation. Failure to tie this pin low during normal operation can cause start
up and initialization problems.(2)
JTAGTRSTZ
RESETZ
P11
C11
I
I
6
6
Power-on reset (active low input with a hysteresis buffer). Self-configuration
starts when a low-to-high transition is detected on RESETZ. All controller
power and clocks must be stable before this reset is de-asserted. No signals
are in their active state while RESETZ is asserted. This pin is typically
connected to the RESETZ pin of the DLPA200x.
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
TSTPT_4
TSTPT_5
TSTPT_6
TSTPT_7
R12
R13
R14
R15
P14
P15
N14
N15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
1
1
1
1
1
1
Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ
is asserted low. Sampled as an input test mode selection control
approximately 1.5 µs after de-assertion of RESETZ, and then driven as
outputs.(2) (3)
Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34xx in a test mode. See 节7.3.6
for more information.
(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal
pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an
external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is
recommended to ensure a logic low.
(2) External resistor must have a value of 8 kΩor less to compensate for pins that provide internal pullup or pulldown resistors.
(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal
pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but
there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to
ensure a logic low.
(4) See 表5-11 for type definitions.
表5-2. Parallel Port Input
PIN(1) (2)
NAME
DESCRIPTION
PARALLEL RGB MODE BT656 INTERFACE MODE
Pixel clock Pixel clock
I/O
TYPE(4)
NO.
PCLK
P3
I
11
Parallel data mask. Programable
polarity with default of active high.
Optional signal.
PDM_CVS_TE
N4
I/O
5
Unused
VSYNC_WE
HSYNC_CS
DATAEN_CMD
P1
N5
P2
I
I
I
11
11
11
Vsync(3)
Hsync(3)
Data valid
Unused
Unused
Unused
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表5-2. Parallel Port Input (continued)
PIN(1) (2)
NAME
DESCRIPTION
PARALLEL RGB MODE BT656 INTERFACE MODE
(TYPICAL RGB 888)
I/O
TYPE(4)
NO.
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
K2
K1
L2
Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
BT656_Data (0)
BT656_Data (1)
BT656_Data (2)
BT656_Data (3)
BT656_Data (4)
BT656_Data (5)
BT656_Data (6)
BT656_Data (7)
L1
I
11
M2
M1
N2
N1
(TYPICAL RGB 888)
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15
R1
R2
R3
P4
R4
P5
R5
P6
Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
I
11
Unused
(TYPICAL RGB 888)
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23
R6
P7
R7
P8
R8
P9
R9
P10
Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
I
11
11
Unused
3D reference
•
For 3D applications: left or right 3D reference (left = 1, right = 0). To be
provided by the host. Must transition in the middle of each frame (no
closer than 1 ms to the active edge of VSYNC).
If a 3D application is not used, pull this input low through an external
resistor.
3DR
N6
I
•
(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.
(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩor less).
(3) VSYNC and HSYNC polarity can be adjusted by software.
(4) See 表5-11 for type definitions.
表5-3. DSI Input Data and Clock
PIN
I/O
TYPE(2)
DESCRIPTION
NAME
NO.
DCLKN
DCLKP
E2
E1
I/O
10
DSI LVDS differential clock for DSI interface.
DD0N
DD0P
DD1N
DD1P
DD2N
DD2P
DD3N
DD3P
G2
G1
F2
F1
D2
D1
C2
C1
Differential data bus for DSI data lane LVDS differential pair inputs 0
through 3.
I/O
10
(support a maximum of 4 input DSI lanes)(1)
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表5-3. DSI Input Data and Clock (continued)
PIN
I/O
TYPE(2)
DESCRIPTION
NAME
NO.
DSI reference resistor. RREF is an analog signal that requires a fixed
precision 30-kΩ±1% resistor connected from this pin to ground when DSI
is used. If DSI is NOT used, leave this pin unconnected and floating.
RREF
F3
—
(1) Differential data bus 0 (DD0x) is required for DSI operation. The remaining three data lanes are optional and only needed depending
on the implementation and required video bandwidth. Leave any unused DSI LVDS pairs unconnected and floating.
(2) See 表5-11 for type definitions.
表5-4. DMD Reset and Bias Control
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
DMD driver enable (active high). DMD reset (active low). When
corresponding I/O power is supplied, the controller drives this signal low
after the DMD is parked and before power is removed from the DMD. If the
1.8-V power to the DLPC34xx is independent of the 1.8-V power to the
DMD, then TI recommends including a weak, external pulldown resistor to
hold the signal low in case DLPC34xx power is inactive while DMD power
is applied.
DMD_DEN_ARSTZ
B1
O
2
DMD_LS_CLK
A1
A2
B2
O
O
I
3
3
6
DMD low speed (LS) interface clock
DMD low speed (LS) serial write data
DMD low speed (LS) serial read data
DMD_LS_WDATA
DMD_LS_RDATA
(1) See 表5-11 for type definitions.
表5-5. DMD Sub-LVDS Interface
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
DMD_HS_CLK_P
DMD_HS_CLK_N
A7
B7
O
4
DMD high speed (HS) interface clock
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
DMD sub-LVDS high speed (HS) interface write data lanes. The true
numbering and application of the DMD_HS_WDATA pins depend on the
software configuration. See 表7-8.
O
4
(1) See 表5-11 for type definitions.
表5-6. Peripheral Interface
PIN(1)
I/O
TYPE(2)
DESCRIPTION
NAME
NO.
Successive approximation ADC (analog-to-digital converter) comparator output (DLPC34xx Input). To implement, use a
successive approximation ADC with a thermistor feeding one input of the external comparator and the DLPC34xx
controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator. It is recommended to use the
DLPA200x to achieve this function. CMP_OUT must be pulled-down to ground if this function is not used. (hysteresis
buffer)
CMP_OUT
A12
I
6
CMP_PWM
A15
N8
O
O
1
9
TI internal use. Leave this pin unconnected.
Host interrupt (output)
HOST_IRQ(3)
HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and most importantly when it completes.
This pin is tri-stated during reset. An external pullup must be included on this signal.
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表5-6. Peripheral Interface (continued)
PIN(1)
I/O
TYPE(2)
DESCRIPTION
NAME
NO.
N10
R11
N9
I2C secondary (port 0) SCL (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup
resistor. The secondary I2C I/Os are 3.6-V tolerant (high-voltage-input tolerant) and are powered by VCC_INTF (which
can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to a host supply with an equal or higher supply
voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not typically satisfy the VIH specification of the
secondary I2C input buffers).
IIC0_SCL(4)
I/O
I/O
I/O
I/O
7
8
7
8
IIC1_SCL
IIC0_SDA(4)
IIC1_SDA
TI internal use. TI recommends an external pullup resistor.
I2C secondary (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup
resistor. The secondary I2C port is the control port of controller. The secondary I2C I/O pins are 3.6-V tolerant (high-
volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be
connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply
voltage does not typically satisfy the VIH specification of the secondary I2C input buffers).
R10
TI internal use. TI recommends an external pullup resistor.
LED enable select. Automatically controlled by the DLPC34xx programmable DMD sequence.
LED_SEL(1:0)
Enabled LED
None
Red
Green
Blue
00
01
10
11
LED_SEL_0
B15
O
1
The controller drives these signals low when RESETZ is asserted and the corresponding I/O power is supplied. The
controller continues to drive these signals low throughout the auto-initialization process. A weak, external pulldown
resistor is recommended to ensure that the LEDs are disabled when I/O power is not applied.
LED_SEL_1
SPI0_CLK
B14
A13
A14
O
O
O
1
13
13
SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to the flash memory clock.
SPI port 0, chip select 0 (active low output). This pin is typically connected to the flash memory chip select.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset
assertion.
SPI0_CSZ0
SPI port 0, chip select 1 (active low output). This pin typically remains unused.
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset
assertion.
SPI0_CSZ1
C12
O
13
SPI0_DIN
B12
B13
I
12
13
Synchronous serial port 0, receive data in. This pin is typically connected to the flash memory data out.
Synchronous serial port 0, transmit data out. This pin is typically connected to the flash memory data in.
SPI0_DOUT
O
(1) External pullup resistor must be 8 kΩor less.
(2) See 表5-11 for type definitions.
(3) For more information about usage, see 节7.3.2.
(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication
on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional secondary
devices on this bus.
表5-7. GPIO Peripheral Interface
PIN(1)
I/O TYPE(3)
DESCRIPTION(2)
NAME
NO.
General purpose I/O 19 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_19
M15
I/O
1
General purpose I/O 18 (hysteresis buffer). Options:
1. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
GPIO_18
M14
I/O
1
2. MTR_SENSE, Motor Sense (Input): For focus motor control applications, this GPIO must be
configured as an input to the DLPC34xx and supplied from the focus motor position sensor.
General purpose I/O 17 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_17
GPIO_16
GPIO_15
GPIO_14
L15
L14
K15
K14
I/O
I/O
I/O
I/O
1
1
1
1
General purpose I/O 16 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 15 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 14 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
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表5-7. GPIO Peripheral Interface (continued)
PIN(1)
NAME
I/O TYPE(3)
DESCRIPTION(2)
NO.
General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_13
GPIO_12
J15
I/O
I/O
1
1
General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
J14
General purpose I/O 11 (hysteresis buffer). Options:
1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and
enabled.
GPIO_11
GPIO_10
H15
I/O
I/O
1
1
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
General purpose I/O 10 (hysteresis buffer). Options:
1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
H14
General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_09
GPIO_08
G15
G14
I/O
I/O
1
1
General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven
by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the
DMD, but it does not power down the DMD (the DLPA200x does that instead). At power-up, GPIO_08
must remain high until HOST_IRQ goes low (see 节9.3).
General purpose I/O 07 (hysteresis buffer). If unused TI recommends this pin be configured as a logic
zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to
avoid a floating GPIO input.
GPIO_07
GPIO_06
GPIO_05
F15
F14
E15
I/O
I/O
I/O
1
1
1
General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
General purpose I/O 04 (hysteresis buffer). Options:
1. 3D glasses control (output): Controls the shutters on 3D glasses (Left = 1, Right = 0).
2. SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup
resistor to deactivate this signal during reset and auto-initialization processes.
3. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
GPIO_04
GPIO_03
GPIO_02
E14
D15
D14
I/O
I/O
I/O
1
1
1
General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.
This pin is typically connected to the DLPA200x SPI_CSZ pin. Requires an external pullup resistor to
deactivate this signal during reset and auto-initialization processes.
General purpose I/O 02 (hysteresis buffer). Options:
1. SPI1_DOUT (output): SPI1 data output signal. This pin is typically connected to the DLPA200x
SPI_DIN pin.
2. Optional DSI Bus Width Config 1 (input): The controller samples this pin during boot and is used
to define the number of lanes used for DSI operation. Requires an external pullup or pulldown
resistor to configure as defined in 表5-8. After boot, this GPIO pin will continue to be used as
SPI1_DOUT. Select the external pullup or pulldown resistor to not interfere.
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表5-7. GPIO Peripheral Interface (continued)
PIN(1)
I/O TYPE(3)
DESCRIPTION(2)
NAME
NO.
General purpose I/O 01 (hysteresis buffer). Options:
1. SPI1_CLK (output): SPI1 clock signal. This pin is typically connected to the DLPA200x SPI_CLK
pin.
2. Optional DSI Bus Width Config 0 (input): The controller samples this pin during boot and is used
to define the number of lanes used for DSI operation. Requires an external pullup or pulldown
resistor to configure as defined in 表5-8. After boot, this GPIO pin will continue to be used as
SPI1_CLK. Select the external pullup or pulldown resistor to not interfere.
GPIO_01
GPIO_00
C15
I/O
I/O
1
1
General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is
typically connected to the DLPA200x SPI_DOUT pin.
C14
(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or
more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as
open-drain.
(2) General purpose I/O for the DLPC3421 controllers. These GPIO pins are software configurable.
(3) See 表5-11 for type definitions.
表5-8. GPIO_01 and GPIO_02
GPIO_02
GPIO_01
Number of DSI Data
Lanes
DSI Lane Config 1
DSI Lane Config 0
0
0
1
1
0
1
0
1
1
2
3
4
表5-9. Clock and PLL Support
PIN
I/O
TYPE(1)
DESCRIPTION
NAME
NO.
Reference clock crystal input. If an external oscillator is used instead of a crystal, use
this pin as the oscillator input.
PLL_REFCLK_I
PLL_REFCLK_O
H1
I
11
5
Reference clock crystal return. If an external oscillator is used instead of a crystal,
leave this pin unconnected (floating with no added capacitive load).
J1
O
(1) See 表5-11 for type definitions.
表5-10. Power and Ground
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
C5, D5, D7,
D12, J4,
J12, K3, L4,
L12, M6,
M9, D9,
D13, F13,
H13, L13,
M10, D3, E3
VDD
PWR
PWR
Core 1.1-V power (main 1.1 V)
—
—
DSI PHY Low Power mode driver supply. It is recommended to externally
tie this pin to VDD.
VDDLP12
C3
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表5-10. Power and Ground (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
C4, D6, D8,
D10, E4,
E13, F4, G4,
G12, H4,
H12, J3,
VSS
GND
Core ground (eDRAM, DSI, I/O ground, thermal ground)
—
J13, K4,
K12, L3, M4,
M5, M8,
M12, G13,
C6, C8
C7, C9, D4,
E12, F12,
K13, M11
All 1.8-V I/O power:
(1.8-V power supply for RESETZ, PARKZ, LED_SEL, CMP_OUT, GPIO,
IIC1, TSTPT, and JTAG pins)
VCC18
PWR
—
M3, M7, N3,
N7
Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA,
video syncs, and HOST_IRQ pins)
VCC_INTF
VCC_FLSH
PWR
PWR
—
—
Flash interface I/O power: 1.8 V to 3.3 V
(Dedicated SPI0 power pin)
D11
VDD_PLLM
VSS_PLLM
VDD_PLLD
VSS_PLLD
H2
G3
J2
PWR
RTN
PWR
RTN
MCG PLL (primary clock generator phase lock loop) 1.1-V power
MCG PLL return
—
—
—
—
DCG PLL (DMD clock generator phase lock loop) 1.1-V power
DCG PLL return
H3
表5-11. I/O Type Subscript Definition
I/O
SUPPLY REFERENCE
ESD STRUCTURE
SUBSCRIPT
DESCRIPTION
1
2
3
4
5
6
7
8
9
1.8-V LVCMOS I/O buffer with 8-mA drive
1.8-V LVCMOS I/O buffer with 4-mA drive
1.8-V LVCMOS I/O buffer with 24-mA drive
1.8-V sub-LVDS output with 4-mA drive
1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive
1.8-V LVCMOS input
Vcc18
Vcc18
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
Vcc18
Vcc18
Vcc_INTF
Vcc18
Vcc_INTF
Vcc18
1.8-V, 2.5-V, 3.3-V I2C with 3-mA drive
1.8-V I2C with 3-mA drive
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
Vcc_INTF
VDD for high speed
transmit, high speed
receive, and low power
receive.
10
DSI LVDS I/O
ESD diode to GND and supply rail
VDDLP12 for low power
transmit
11
12
13
1.8-V, 2.5-V, 3.3-V LVCMOS input
Vcc_INTF
Vcc_FLSH
Vcc_FLSH
ESD diode to GND and supply rail
ESD diode to GND and supply rail
ESD diode to GND and supply rail
1.8-V, 2.5-V, 3.3-V LVCMOS input
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
MAX
UNIT
SUPPLY VOLTAGE(2)
V(VDD)
1.21
1.32
1.96
1.96
3.60
3.60
1.21
1.21
See (3)
V
V
V
V
V
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V(VDDLP12)
V(VCC18)
DMD Sub-LVDS Interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)
V(VCC_INTF)
V(VCC_FLSH)
V(VDD_PLLM) (MCG PLL)
V(VDD_PLLD) (DCG PLL)
VI2C buffer (I/O type 7)
GENERAL
TJ
Operating junction temperature
Storage temperature
125
125
°C
°C
–30
–40
Tstg
(1) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, which do not
imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS (GND).
(3) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.045
1.045
NOM
1.10
1.10
MAX
UNIT
V
V(VDD)
Core power 1.1 V (main 1.1 V)
1.155
1.155
V(VDDLP12)
DSI PHY low power mode driver supply
See (3) (4)
V
All 1.8-V I/O power:
V(VCC18)
(1.8-V power supply for RESETZ, PARKZ LED_SEL,
CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins.)
1.64
1.80
1.96
V
V
1.64
2.28
1.80
2.50
1.96
2.72
3.58
1.96
2.72
3.58
1.155
1.155
85
Host or parallel interface I/O power: 1.8 to 3.3 V (includes
IIC0, PDATA, video syncs, and HOST_IRQ pins)
V(VCC_INTF)
See (1)
See (1)
3.02
3.30
1.64
1.80
V(VCC_FLSH)
Flash interface I/O power: 1.8 to 3.3 V
2.28
2.50
V
3.02
3.30
V(VDD_PLLM)
MCG PLL 1.1-V power
See (2)
See (2)
1.025
1.025
–30
–30
1.100
1.100
V
V
V(VDD_PLLD)
DCG PLL 1.1-V power
TA
TJ
Operating ambient temperature(5)
°C
°C
Operating junction temperature
105
(1) These supplies have multiple valid ranges.
(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop
across the filter.
(3) It is recommended that VDDLP12 rail is tied to the VDD rail. The DSI LP supply (VDDLP12) is only used for read responses from the
controller which are not supported. Because of this, a separate 1.2-V rail is not required. If a separate 1.2-V supply is already being
used to power this rail, a voltage tolerance of ±6.67% is allowed on this separate 1.2-V supply.
(4) When the DSI-PHY LP supply (VDDLP12) is fed from a supply separate from VDD, the VDDLP12 power must sequence ON after the
1.1-V core supply and must sequence OFF before the 1.1-V core supply.
(5) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value
at 0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum
estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects RθJA
Thus, maximum operating ambient temperature varies by application.
.
•
•
Ta_min = Tj_min –(Pd_min × RθJA) = –30°C –(0.0 W × 30.3°C/W) = –30°C
Ta_max = Tj_max –(Pd_max × RθJA) = +105°C –(0.348 W × 30.3°C/W) = +94.4°C
6.4 Thermal Information
DLPC3421
ZVB (NFBGA)
176 PINS
11.2
THERMAL METRIC(1)
UNIT
°C/W
°C/W
RθJC
Junction-to-case top thermal resistance
at 0 m/s of forced airflow(2)
at 1 m/s of forced airflow(2)
at 2 m/s of forced airflow(2)
30.3
Junction-to-air thermal
resistance
RθJA
27.4
26.6
Temperature variance from junction to package top center temperature, per unit power
dissipation(3)
0.27
°C/W
ψJT
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC
defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34xx PCB and thus the reported
thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is
the best information available during the design phase to estimate thermal performance.
(3) Example: (0.5 W) × (0.2°C/W) ≈0.1°C temperature rise.
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6.5 Power Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) (2) (3)
TEST CONDITIONS
MIN
TYP(4)
MAX(5) UNIT
I(VDD)
I(VDD_PLLM)
I(VDD_PLLD)
+
+
1.1-V rails
Frame rate = 60 Hz
69
75
mA
I(VDD_PLLM)
I(VDD_PLLD)
MCG PLL 1.1-V current(6)
DCG PLL 1.1-V current(6)
Frame rate = 60 Hz
Frame rate = 60 Hz
6
6
mA
mA
All 1.8-V I/O current: (1.8-V power supply
for all I/O other than the host or parallel
interface and the SPI flash interface)
I(VCC18)
Frame rate = 60 Hz
21
23
mA
Host or parallel interface I/O current: 1.8 to
I(VCC_INTF)
I(VCC_FLSH)
3.3 V (includes IIC0, PDATA, video syncs, Frame rate = 60 Hz
2
1
mA
mA
and HOST_IRQ pins)(6)
Flash interface I/O current: 1.8 to 3.3 V(6) Frame rate = 60 Hz
(1) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum
nominal voltage (that is 1.8 V).
(2) Input image is 640 × 360 (nHD) 24 bits using VESA reduced blanking v2 timings on the parallel interface at the frame rate shown with
the 0.16-in nHD (DLP160CP) DMD. The controller has the CAIC and LABB algorithms turned off.
(3) The values do not take into account software updates or customer changes that may affect power performance.
(4) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.
(5) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor,
30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells
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6.6 Pin Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST
MIN
TYP
MAX UNIT
CONDITIONS(2)
0.7 ×
VCC_INTF
I2C buffer (I/O type 7)
See (3)
I/O type 1, 2, 3, 6, 8 except pins
noted in (4)
VCC18 = 1.8 V
1.17
3.6
3.6
I/O type 1, 6 for pins noted in (4)
VCC18 = 1.8 V
1.3
1.17
1.17
1.7
High-level input
threshold voltage
I/O type 5, 9, 11
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
3.6
V
3.6
VIH
I/O type 12, 13
I/O type 5, 9, 11
3.6
I/O type 12, 13
1.7
3.6
I/O type 5, 9, 11
2.0
3.6
I/O type 12, 13
2.0
3.6
0.3 ×
VCC_INTF
I2C buffer (I/O type 7)
–0.5
–0.3
I/O type 1, 2, 3, 6, 8 except pins
noted in (4)
VCC18 = 1.8 V
0.63
I/O type 1, 6 for pins noted in (4)
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
0.5
0.63
0.63
0.7
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.35
1.35
1.35
1.7
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
VCC18 = 1.8 V
Low-level input
threshold voltage
VIL
V
I/O type 5, 9, 11
I/O type 12, 13
0.7
I/O type 5, 9, 11
I/O type 12, 13
0.8
0.8
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
VCC_INTF > 2 V
High-level output
voltage
VOH
I/O type 5, 9, 11
I/O type 12, 13
V
1.7
I/O type 5, 9, 11
I/O type 12, 13
2.4
2.4
I2C buffer (I/O type 7)
0.4
0.2 ×
VCC_INTF
I2C buffer (I/O type 7)
VCC_INTF < 2 V
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
I/O type 5, 9, 11
I/O type 12, 13
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
0.45
0.45
0.45
0.7
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
Low-level output
voltage
VOL
V
0.7
0.4
0.4
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over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER(1)
MIN
TYP
MAX UNIT
CONDITIONS(2)
I/O type 2, 4
I/O type 5
VCC18 = 1.8 V
2
2
VCC_INTF = 1.8 V
VCC18 = 1.8 V
I/O type 1
3.5
3.5
3.5
10.6
5.4
10.8
10.8
7.8
15
I/O type 9
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC18 = 1.8 V
I/O type 13
I/O type 3
High-level output
current(5)
IOH
mA
I/O type 5
VCC_INTF = 2.5 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 9, 13
I/O type 13
I/O type 5
I/O type 9
I/O type 13
I2C buffer (I/O type 7)
I/O type 2, 4
I/O type 5
15
3
VCC18 = 1.8 V
2.3
2.3
4.6
4.6
4.6
13.9
5.2
10.4
10.4
4.4
8.9
8.9
VCC_INTF = 1.8 V
VCC18 = 1.8 V
I/O type 1
I/O type 9
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC18 = 1.8 V
I/O type 13
I/O type 3
Low-level output
current(6)
IOL
mA
I/O type 5
VCC_INTF = 2.5 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 9
I/O type 13
I/O type 5
I/O type 9
I/O type 13
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over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER(1)
MIN
TYP
MAX UNIT
CONDITIONS(2)
VI2C buffer < 0.1 ×
VCC_INTF or
VI2C buffer > 0.9 ×
VCC_INTF
I2C buffer (I/O type 7)
10
–10
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
10
10
–10
–10
–10
–10
–10
–10
–10
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
High-impedance
leakage current
IOZ
µA
10
I/O type 5, 9, 11
I/O type 12, 13
10
10
10
10
5
I/O type 5, 9, 11
I/O type 12, 13
I2C buffer (I/O type 7)
I/O type 1, 2, 3, 6, 8
I/O type 5, 9, 11
I/O type 12, 13
VCC18 = 1.8 V
2.6
2.6
2.6
2.6
2.6
2.6
2.6
3.5
3.5
3.5
VCC_INTF = 1.8 V
VCC_FLSH = 1.8 V
VCC_INTF = 2.5 V
VCC_FLSH = 2.5 V
VCC_INTF = 3.3 V
VCC_FLSH = 3.3 V
I/O type 5, 9, 11
I/O type 12, 13
3.5
pF
Input capacitance
(including package)
CI
3.5
3.5
3.5
I/O type 5, 9, 11
I/O type 12, 13
Sub-LVDS –DMD high speed
(I/O type 4)
VCC18 = 1.8 V
3
(1) The I/O type refers to the type defined in 表5-11.
(2) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply
reference is set to.
(3) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
(4) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V
I/O.
(5) At a high level output signal, the given I/O will be able to output at least the minimum current specified.
(6) At a low level output signal, the given I/O will be able to sink at least the minimum current specified.
6.7 Internal Pullup and Pulldown Electrical Characteristics
over operating free-air temperature (unless otherwise noted)(2)
TEST
INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS
MIN
MAX
UNIT
CONDITIONS(1)
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
29
38
56
30
36
52
63
90
Weak pullup resistance
kΩ
148
72
Weak pulldown resistance
101
167
kΩ
(1) The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in 表5-11).
(2) An external 8-kΩpullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any
associated internal pullups or pulldowns.
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6.8 DMD Sub-LVDS Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.0
UNIT
V
VCM
Common mode voltage
0.8
0.9
VCM (Δpp)(1)
VCM change peak-to-peak (during switching)
VCM change steady state
75
mV
mV
mV
mV
V
VCM (Δss)(1)
–10
170
10
(2)
|VOD
|
Differential output voltage magnitude
VOD change (between logic states)
Single-ended output voltage high
Single-ended output voltage low
Internal differential termination
250
350
10
VOD (Δ)
VOH
–10
0.825
0.625
80
1.025
0.775
100
1.175
0.975
120
VOL
V
Txterm
Ω
100-Ωdifferential PCB trace
(50-Ωtransmission lines)
Txload
0.5
6
in
(1) See 图6-1.
(2) VOD is the differential voltage measured across a 100-Ωtermination resistance connected directly between the transmitter differential
pins. VOD = VP –VN, where P and N are the differential output pins. |VOD| is the magnitude of the peak-to-peak voltage swing across
the P and N output pins (see 图6-2). VCM cancels out between signals when measured differentially, thus the reason VOD swings
relative to zero.
+V
OD
100
90
80
|VOD
|
70
60
V
(û
CM SS
)
V
(û )
CM P-P
V
CM
(0 V) 50
40
30
|VOD
|
20
10
0
œV
OD
tFALL
tRISE
图6-1. Common Mode Voltage
VCM is removed when the signals are viewed differentially.
图6-2. Differential Output Signal
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6.9 DMD Low-Speed Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.7 ×
VCC18
VOH(DC)
VOL(DC)
VOH(AC)
VOL(AC)
V
DC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.3 ×
VCC18
V
V
V
AC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.8 ×
VCC18
VCC18 +
0.5
(1)
(2)
AC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
0.2 ×
VCC18
–0.5
VOL(DC) to VOH(AC) for rising edge
and VOH(DC) to VOL(AC) for rising
edge
DMD_LS_WDATA and DMD_LS_CLK
1.0
3.0
Slew rate
V/ns
DMD_DEN_ARSTZ
DMD_LS_RDATA
VOL(AC) to VOH(AC) for rising edge
0.25
0.5
(1) VOH(AC) maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries
termination resistor, the DMD operates within the LPSDR input AC specifications.
(2) VOL(AC) minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries
termination resistor, the DMD operates within the LPSDR input AC specifications.
(3) See 图6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See 图6-4 for DMD_DEN_ARSTZ rise and fall times.
DMD_DEN_ARSTZ
LS_CLK, LS_WDATA
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V
V
V
OH(AC)
OH(AC)
OH(DC)
V
OL(DC)
V
V
OL(AC)
OL(AC)
10
0
10
0
tRISE
tFALL
tRISE
tFALL
图6-3. LS_CLK and LS_WDATA Slew Rate
图6-4. DMD_DEN_ARSTZ Slew Rate
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6.10 System Oscillator Timing Requirements
MIN
23.998
41.663
NOM
24.000
41.667
MAX
24.002
41.670
UNIT
MHz
ns
fclk
tc
Clock frequency, MOSC (primary oscillator clock)(1)
Cycle time, MOSC (clock period)(1)
See 图6-5
50% to 50% reference points
(signal)
tw(H)
tw(L)
Pulse duration as percent of tc (2), MOSC, high
Pulse duration as percent of tc (2), MOSC, low
40%
40%
50%
50%
50% to 50% reference points
(signal)
20% to 80% reference points
(rising signal)
80% to 20% reference points
(falling signal)
tt
Transition time(2), MOSC
10
ns
Long-term, peak-to-peak, period jitter(2), MOSC
(that is the deviation in period from ideal period due solely to
high frequency jitter)
tjp
2%
(1) The frequency accuracy for MOSC is ±200 PPM. This tolerance range includes impact to accuracy due to aging, temperature, and trim
sensitivity. The MOSC input does not support spread spectrum clock spreading.
(2) Applies only when driven by an external digital oscillator.
t
C
t
T
t
T
t
t
W(L)
W(H)
80%
20%
50%
MOSC
图6-5. System Oscillators
6.11 Power Supply and Reset Timing Requirements
MIN
MAX
UNIT
tw(L)
tr
Pulse duration, active low, RESETZ
Rise time, RESETZ(1)
50% to 50% reference points (signal)
20% to 80% reference points (signal)
80% to 20% reference points (signal)
1.25
µs
µs
µs
0.5
0.5
tf
Fall time, RESETZ(1)
Rise time, VDD (during VDD ramp up at turn-
on)
trise
0.3 V to 1.045 V (VDD)
1
ms
(1) For more information on RESETZ, see 节5.
DC Power Supplies
tf
tr
80%
50%
20%
80%
50%
20%
RESETZ
tw(L)
tw(L)
tw(L)
Time
图6-6. Power-Up and Power-Down RESETZ Timing
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6.12 Parallel Interface Frame Timing Requirements
See 节11.1.3 for additional information
MIN
MAX
UNIT
tp_vsw
tp_vbp
50% reference points
50% reference points
1
lines
Pulse duration –default VSYNC_WE high
Vertical back porch (VBP) –time from the active edge of
VSYNC_WE to the active edge of HSYNC_CS for the first
active line(1)
2
1
lines
lines
Vertical front porch (VFP) –time from the active edge of the
HSYNC_CS following the last active line in a frame to the active
edge of VSYNC_WE(1)
tp_vfp
50% reference points
Total vertical blanking –the sum of VBP and VFP (tp_vbp
tp_vfp
+
tp_tvb
tp_hsw
tp_hbp
50% reference points
50% reference points
50% reference points
See (1)
lines
)
4
4
128
PCLKs
PCLKs
Pulse duration –default HSYNC_CS high
Horizontal back porch (HBP) –time from the active edge of
HSYNC_CS to the rising edge of DATAEN_CMD
Horizontal front porch (HFP) –time from the falling edge of
DATAEN_CMD to the active edge of HSYNC_CS
tp_hfp
50% reference points
8
PCLKs
(1) The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF / DMD_ALPF)]
lines
where:
•
•
SOURCE_ALPF = Input source active lines per frame
DMD_ALPF = Actual DMD used lines per frame supported
1 Frame
tp_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
(This diagram assumes the HSYNC
active edge is the rising edge)
tp_hbp
tp_hfp
DATAEN_CMD
PDATA(23/15:0)
PCLK
P
n-2
P
n-1
P0
P1
P2
P3
Pn
图6-7. Parallel Interface Frame Timing
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6.13 Parallel Interface General Timing Requirements
MIN
1.0
MAX
155.0
1000
UNIT
MHz
ns
PCLK frequency
PCLK period
ƒclock
tp_clkper
tp_clkjit
tp_wh
50% reference points
Max ƒclock
6.45
PCLK jitter
See (1)
PCLK pulse duration high
PCLK pulse duration low
50% reference points
50% reference points
2.43
2.43
ns
ns
tp_wl
Setup time –HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid before the active edge of PCLK
tp_su
tp_h
50% reference points
50% reference points
0.9
0.9
ns
ns
Hold time –HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid after the active edge of PCLK
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tt
0.2
2.0
ns
Transition time –all signals
tsetup, 3DR
thold, 3DR
This is the setup time with respect to VSYNC(2)
This is the hold time with respect VSYNC(3)
50% reference points
50% reference points
1.0
1.0
ms
ms
(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock –5.76 ns]. Setup and hold times must be met even with clock jitter.
(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes.
(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes.
tp_clkper
tp_wh
tp_wl
PCLK
tp_h
tp_su
图6-8. Parallel Interface Pixel Timing
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6.14 BT656 Interface General Timing Requirements
The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate
ITU-R BT.656 specification for detailed interface timing requirements.(2)
MIN
MAX
UNIT
MHz
ns
PCLK frequency
PCLK period
1.0
33.5
ƒcll
tp_clkper
tp_clkjit
tp_wh
tp_wl
50% reference points
Max fclock
29.85
1000
PCLK jitter
See (1)
PCLK pulse duration high
PCLK pulse duration low
50% reference points
50% reference points
10.0
10.0
ns
ns
Setup time –PDATA(7:0) before the active edge of
PCLK
tp_su
tp_h
50% reference points
50% reference points
3.0
0.9
ns
ns
Hold time –PDATA(7:0) after the active edge of
PCLK
20% to 80% reference points
(rising signal)
80% to 20% reference points
(falling signal)
tt
0.2
3.0
ns
Transition time –all signals
(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock –5.76 ns]. Clock jitter must maintain setup and hold times. BT.656
data bits must be mapped to the DLPC34xx PDATA bus as shown in 图6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA
(23:0) mapping.
(2) The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active
edge of PCLK. See 图6-9.
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PDATA(7:0) of the input pixel data bus
Bus assignment mapping
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Data bit mapping on controller pin
n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
图6-9. BT.656 Interface Mode Bit Mapping
6.15 DSI Host Timing Requirements
These timing requirements describe specific host minimum values that are higher than those specified in the MIPI standards.
It is critical for proper operation that the host meet these minimum timing requirements for specified MIPI parameters. The
decoded DSI data must also follow all 节6.12.
MIN
MAX
235
470
4
UNIT
Clock lane
Data lane
Frequency
80
MHz
Effective data rate
160
1
Mbps
lanes
Number of data lanes Selectable
80-MHz to 94-MHz HS
clock
565
During a LP to HS transition, the time that
tHS-PREPARE+ tHS-ZERO the transmitter drives the HS-0 state prior to
transmitting the synchronization sequence
ns
95-MHz to 235-MHz HS
clock(1)
465(2)
Time interval during which the HS receiver
ignores any data lane HS transitions,
80-MHz to 94-MHz HS
clock
565(3)
465(3)
starting from the beginning of THS-PREPARE
the HS receiver ignores any data lane
transitions before the minimum value, and
responds to any data lane transitions after
the maximum value
;
tHS-SETTLE
ns
95-MHz to 235-MHz HS
clock
(1) Example: At 172 MHz and tHS-PREPARE = 51.46 ns →51.46 ns + tHS-ZERO ≥465 ns. Therefore tHS-ZERO ≥413.54 ns.
(2) Minimum values are higher than those required by the MIPI standard. tHS-PREPARE must be within the MIPI specified range.
(3) Maximum values are higher than those required by the MIPI standard.
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6.16 Flash Interface Timing Requirements
The DLPC34xx flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The
DLPC34xx can support 1- to 128-Mb flash memories.(2) (3) (4)
MIN
MAX
36.0
704
UNIT
MHz
ns
fclock
SPI_CLK frequency
See (1)
1.4
tp_clkper
tp_wh
tp_wl
SPI_CLK period
50% reference points
50% reference points
50% reference points
27.8
352
352
SPI_CLK pulse duration high
SPI_CLK pulse duration low
ns
ns
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tt
0.2
3.0
ns
Transition time –all signals
Setup time –SPI_DIN valid before SPI_CLK falling
edge
tp_su
tp_h
50% reference points
50% reference points
50% reference points
10.0
0.0
ns
ns
ns
Hold time –SPI_DIN valid after SPI_CLK falling edge
SPI_CLK clock falling edge to output valid time –
SPI_DOUT and SPI_CSZ
tp_clqv
1.0
3.0
SPI_CLK clock falling edge output hold time –
SPI_DOUT and SPI_CSZ
tp_clqx
50% reference points
ns
–3.0
(1) This range include the ±200 ppm of the external oscillator (but no jitter).
(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC34xx does
transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This process provides
support for SPI devices with long clock-to-Q timing. DLPC34xx hold capture timing has been set to facilitate reliable operation with
standard external SPI protocol devices.
(3) With the above output timing, DLPC34xx provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the
rising edge of SPI_CLK.
(4) For additional requirements of the external flash device view the 节7.3.3.1 section.
tCLKPER
SPI_CLK
(Controller output)
tWL
tWH
tP_SU
tP_H
SPI_DIN
(Controller input)
tP_CLQV
SPI_DOUT, SPI_CS(1:0)
(Controller output)
tP_CLQX
图6-10. Flash Interface Timing
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6.17 Other Timing Requirements
MIN
MAX
UNIT
ns
trise, all(1) (2)
20% to 80% reference points
10
10
tfall, all(1) (2)
80% to 20% reference points
20% to 80% reference points
80% to 20% reference points
ns
trise, PARKZ(2)
150
150
ns
tfall, PARKZ(2)
ns
tw, GPIO_08 (PROJ_ON) pulse width low(3)
I2C baud rate
200
ms
kHz
100
(1) Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.
(2) This is the recommended signal transition time to avoid input buffer oscillations.
(3) When the controller is turned off by setting PROJ_ON low, PROJ_ON must not be brought high again for at least 200 ms. View 节9.3
for additional requirements.
6.18 DMD Sub-LVDS Interface Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
45%
MIN
TYP
MAX
250
UNIT
ps
(1)
(1)
tR
tF
Differential output rise time
Differential output fall time
DMD HS clock switching rate
DMD HS clock frequency
DMD HS clock output duty cycle
250
ps
tswitch
fclock
1200
600
Mbps
MHz
DCout
50%
55%
(1) Rise and fall times are defined for the differential VOD signal as shown in 图6-2.
6.19 DMD Parking Switching Characteristics
See (2)
PARAMETER
Normal park time(1)
Fast park time(3)
TEST CONDITIONS
TYP
MAX
20
UNIT
ms
tpark
tfast park
32
µs
(1) Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the
normal park request (GPIO_08 goes low).
(2) The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be
held on for a time after parking is completed to satisfy DMD requirements. See 节9.2 and the appropriate DMD or PMIC datasheet for
more information.
(3) Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast
park request (PARKZ goes low).
6.20 Chipset Component Usage Specification
The DLPC3421 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires
that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.
表6-1. DLPC3421 Supported DMDs and PMICs
DLPC3421 DLP Chipset
DMD
PMIC
DLP160CP
DLPA2000
DLPA2005
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7 Detailed Description
7.1 Overview
The DLPC3421 part is a display controller for the DLP160CP (0.16 nHD) DMD. The DLPC3421 controller is part
of the chipset composed of the controller, DLP160CP (0.16 nHD) DMD, and DLPA200x PMIC (which includes an
LED driver). To ensure reliable operation of the DLP chipset, the DLPC34xx must always be used with the
supported devices shown in 表6-1.
The DLPC34xx display controller provides interfaces along with data and image processing functions that are
optimized for small form factor and power-constrained display applications. Applications include projection within
mobile projectors, smart displays, smartphones, tablets, augmented reality glasses, mobile accessories, smart
home displays, and Pico projectors. The DLPC3421 is not a front-end processor; therefore, standalone
projectors must include a separate front-end chip to interface to the outside world (for example, a video decoder,
HDMI receiver, or USB I/F chip).
7.2 Functional Block Diagram
Test
Pattern
Generator
Video Processing
/5
Parallel Video
or BT656 Port
ñ
ñ
ñ
ñ
ñ
Brightness Enhancement
Chroma Interpolation
Color Space Conversion
Color Correction
ñ
ñ
ñ
ñ
Contrast Adjustment
Gamma Correction
/24
Input
Control
Processing
Image Format Processing
Power Saving Operations
Splash
Screen
CAIC Processing
DLP Subsystem
Display Formatting
eDRAM (Frame Memory)
Arm® Cortex®-M3
Processor
128 KB I/D Memory
JTAG
I2C_0
/
/
/
Real Time
Control System
SPI_0
DMD_HS_CLK
(sub-LVDS)
DMD_HS_DATA(A:H)
/
(sub-LVDS)
DMD Interface
DMD_LS_CLK
SPI_1
I2C_1
LED Control
Other options
Clocks and Reset
Generation
DMD_LS_WDATA
DMD_LS_RDATA
/20
GPIO
DMD_DEN_ARSTZ
Clock (Crystal)
Reset Control
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7.3 Feature Description
7.3.1 Input Source Requirements
7.3.1.1 Supported Resolution and Frame Rates
表7-1. Supported Input Source Ranges(1) (2)
SOURCE RESOLUTION RANGE (pixels)
HORIZONTAL VERTICAL
Landscape
FRAME RATE
RANGE
INTERFACE
Parallel
FORMAT(3)
IMAGE TYPE
2D only
(Hz)
Landscape
Portrait(4)
N/A
Portrait(4)
N/A
320
640
854
320
640
854
180
360
480
180
360
480
RGB888,
YCrCb888,
RGB666,
YCrCb666,
RGB565,
N/A
N/A
48 to 360
N/A
N/A
N/A
N/A
48 to 240
48 to 60
DSI(5)
2D only
N/A
N/A
YCrCb565,
YCrCb4:2:2
N/A
N/A
(1) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line
rate.
(2) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to
determine the latest available frame rate and input resolution support for a given firmware image.
(3) Bits per pixel does not necessarily equal the number of data pins used on the DLPC34xx controller.
(4) Rotation of the image into Portrait orientation is not supported for this chipset.
(5) Applications may require up to four DSI lanes in order to fully utilize the available DSI bandwidth (and therefore achieve the maximum
display rates and resolutions).
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7.3.1.2 Parallel Interface
The parallel interface complies with standard graphics interface protocol, which includes the signals listed in 表
7-2.
表7-2. Parallel Interface Signals
SIGNAL
DESCRIPTION
VSYNC_WE
HSYNC_CS
vertical sync
horizontal sync
data valid
DATAEN_CMD
PDATA
24-bit data bus
pixel clock
PCLK
PDM_CVS_TE
parallel data mask (optional)
备注
VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no
longer active, the display sequencer stops and causes the LEDs to turn off.
The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section
shows the relationship of these signals.
An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without
losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source
image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or
active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic
low signal. PDM_CVS_TE must only change during vertical blanking.
The parallel interface supports six data transfer formats. They are as follows:
• 24-bit RGB888 or 24-bit YCbCr888 on a 24 data wire interface
• 18-bit RGB666 or 18-bit YCbCr666 on an 18 data wire interface
• 16-bit YCbCr 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, ...)
The 节7.3.1.2.1 section shows the required PDATA(23:0) bus mapping for these six data transfer formats.
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7.3.1.2.1 PDATA Bus –Parallel Interface Bit Mapping Modes
23
0
Red / Cr
Green / Y
Blue / Cb
Controller input mapping
7
7
6
6
5
4
3
2
2
1
1
0
0
7
7
6
6
5
4
3
2
2
1
1
0
0
7
7
6
6
5
5
4
3
2
1
1
0
Controller internal re-mapping
5
4
3
5
4
3
4
3
2
0
Red / Cr
Green / Y
Blue / Cb
图7-1. RGB-888 and YCbCr-888 I/O Mapping
23
0
Input
3
Input
3
Input
7
7
6
6
5
4
2
2
1
1
0
0
7
7
6
6
5
4
2
2
1
1
0
0
7
6
5
4
3
2
1
0
Controller input mapping
Controller internal re-mapping
5
4
3
5
4
3
7
6
5
4
3
2
1
0
Red / Cr
Green / Y
Blue / Cb
图7-2. RGB-666 and YCbCr-666 I/O Mapping
23
0
Cr / Cb
Y
N/A
Controller input mapping
7
7
6
6
5
5
4
3
2
2
1
1
0
0
7
7
6
6
5
5
4
3
3
2
2
1
1
0
0
7
7
6
6
5
5
4
4
3
2
2
1
1
0
Controller internal re-mapping
4
3
4
3
0
Cr / Cb
Y
N/A
图7-3. 16-Bit YCbCr-880 I/O Mapping
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7.3.1.3 DSI Interface
The DLPC34xx controller supports the industry standard DSI (Display Serial Interface) Type-3 LVDS video
interface with up to four lanes. DSI is a source-synchronous, high-speed, low-power, low-cost physical layer. The
DSI-PHY unit receives data when it operates in high-speed (HS) mode. The DSI-PHY unit receives and
transmits data when it operates in low-power (LP) mode for unidirectional data lanes. Point-to-point lane
interconnect can be used for either data or clock signal transmission. The high-speed receiver is a differential
line receiver circuit. The low-power receiver is an unterminated, single-ended receiver circuit. 图 7-4 shows a
high-level view of the DSI interface.
For a given frame rate, the DSI high-speed (HS) clock frequency must be fixed. If a different DSI clock frequency
is ever needed (such as to support another frame rate), an I2C command must be sent to the controller with the
updated HS clock frequency.
MIPI refers to the Mobile Industry Processor Interface standard.
Various DSI requirements and features of the DLPC34xx are as follows:
• compliant with the DSI-MIPI Specification for Display Serial Interface (V 1.02.00) except for those items noted
in the DSI Host Timing Requirements table
• compliant with D-PHY standard MIPI Specification (V 1.0)
• MIPI DSI Type 3 architecture
• supports display resolutions shown in 节7.3.1.1
• supports video mode (command mode not supported)
• MIPI DCSSM (Display Command SetSM) commands sent over DSI not supported (send commands via I2C
instead)
• supports multiple packets per transmission
• supports trigger messages in the forward direction
• data lanes configurable from one to four channels
• EOT (End of Transfer) command is supported and must be enabled
• CRC (cyclic redundancy check) and ECC (error correction code) for header supported
– CRC and ECC can be disabled
• checksum for long packets with error reporting (but no ECC)
• supports one virtual channel for video mode
• supports burst mode
• supports non-burst with sync pulses and with sync event
• BTA (bus turn-around) mode not supported and must be disabled in the DSI host processor
• LP mode is required during vertical blanking and vertical sync. LP mode is not supported between pixel lines
(i.e. HS blanking must be used for horizontal blanking and horizontal sync)
• an active DSI HS clock is required during LP blanking
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Host Processor
DSI Transmitter
DLPC34xx
DSI Receiver
DataN+
DataN+
DataNœ
DataNœ
Data0+
Data0+
Data0œ
Data0œ
Clock+
Clock+
Clockœ
Clockœ
- one clock lane
- one bi-directional data lane (Data0)
- up to three additional uni-directional data lanes (Data1, Data2, and Data3)
图7-4. DSI High Level View
The differential DSI clock lane (DCLKN and DCLKP) must be in the LP11 (Idle) state upon the de-assertion of
RESETZ (zero-to-one transition) and must remain in this state until HOST_IRQ is de-asserted (one-to-zero
transition) to ensure proper DSI initialization.
The controller requires differential data lane '0' (DD0N:DD0P) for DSI operation. The three remaining data lanes
are optional depending on the desired input resolution and frame rate. Not all display resolutions and frame rates
are supported without using all four data lanes.
The state of GPIO (2:1) pins upon the de-assertion of RESETZ (zero-to-one transition) determines the number of
DSI data lanes that are enabled for both LP and HS bus operation.
DSI supported data transfer formats are as follows:
• 24-bit RGB888 - each pixel uses 3 bytes
• 18-bit RGB666 - each pixel packed into 2 or more bytes
• 18-bit RGB666 - each pixel loosely packed into 3 bytes
• 16-bit 4:2:2 YCbCr - each pixel uses 2 bytes
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7.3.2 Device Startup
• The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.
• While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).
• HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is
pulled high, this indicates that the controller is performing boot-up and auto-initialization.
• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to
indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the
external signal).
• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the
falling edge of the signal, the initialization is complete.
• The DLPC34xx controller is ready to receive commands through I2C or accept video over the DSI or the
parallel interface only after auto-initialization is complete.
• The controller initialization typically completes (HOST_IRQ goes low) within 500 ms of RESETZ being
asserted. However, this time may vary depending on the software version and the contents of the user
configurable auto initialization file.
RESETZ
auto-initialization
HOST_IRQ
(with external pullup)
(INIT_BUSY)
t0
t1
t0: rising edge of RESETZ; auto-initialization begins
t1: falling edge of HOST_IRQ; auto-initialization is complete
图7-5. HOST_IRQ Timing
7.3.3 SPI Flash
7.3.3.1 SPI Flash Interface
The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the
below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing
Requirements section.
The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash
Device Options table for example compatible flash options. The minimum required flash size depends on the
size of the utilized firmware. The firmware size depends upon a variety of factors including the number of
sequences, lookup tables, and splash images.
The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The
device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.
The flash device must support these rates.
The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash
device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip
select zero. The boot routine uploads program code from flash memory to program memory then transfers
control to an auto-initialization routine within program memory.
The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features,
and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below 表7-3, 表7-4, and
表7-5.
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表7-3. Additional DLPC34xx SPI Flash Requirements
FEATURE
SPI interface width
DLPC34xx REQUIREMENT
Single
SPI polarity and phase settings
Fast READ addressing
Programming mode
Page size
SPI mode 0
Auto-incrementing
Page mode
256 B
Sector size
4-KB sector
Any
Block size
Block protection bits
Status register bit(0)
Status register bit(1)
Status register bits(6:2)
Status register bit(7)
0 = Disabled
Write in progress (WIP), also called flash busy
Write enable latch (WEN)
A value of 0 disables programming protection
Status register write protect (SRWP)
Because the DLPC34xx controller supports only single-byte status register R/W command execution,
it may not be compatible with flash devices that contain an expansion status byte. However, as long
as the expansion status byte is considered optional in the byte 3 position and any write protection
control in this expansion status byte defaults to unprotected, then the flash device is likely compatible
with the DLPC34xx.
Status register bits(15:8)
(that is expansion status byte)
The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled
or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as
part of the boot process.
The DLPC34xx issues these commands during the boot process:
• A write enable (WREN) instruction to request write enable, followed by
• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8
bits (this disables all programming protection)
Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:
• A write enable (WREN) instruction to request write enable, followed by
• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
• After the write enable latch (WEL) bit is set, the program or erase instruction
Note that the flash device automatically clears the write enable status after each program and erase instruction.
表 7-4 and 表 7-5 below list the specific instruction OpCode and timing compatibility requirements. The
DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.
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表7-4. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
BYTE 1
SPI FLASH COMMAND
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(OPCODE)
Fast READ (1 output)
Read status
0x0B
0x05
0x01
0x06
0x02
0x20
0xC7
ADDRS(0)
N/A
ADDRS(1)
N/A
ADDRS(2)
STATUS(0)
dummy
DATA(0)(1)
Write status
STATUS(0)
See (2)
Write enable
Page program
Sector erase (4 KB)
Chip erase
ADDRS(0)
ADDRS(0)
ADDRS(1)
ADDRS(1)
ADDRS(2)
ADDRS(2)
DATA(0)(1)
(1) Shows the first data byte only. Data continues.
(2) Access to a second (expansion) write status byte not supported by the DLPC34xx controller.
表 7-5 below and the Flash Interface Timing Requirements section list the specific timing compatibility
requirements for a DLPC34xx compatible flash device.
表7-5. SPI Flash Key Timing Parameter Compatibility Requirements
SPI FLASH TIMING PARAMETER(1) (2)
SYMBOL
ALTERNATE SYMBOL
MIN
MAX
UNIT
Access frequency (all commands)
FR
fC
MHz
≤1.4
≥30.1
Chip select high time (also called chip select
deselect time)
tSHSL
tCSH
ns
≤200
≥0
Output hold time
tCLQX
tCLQV
tDVCH
tCHDX
tHO
tV
tDSU
tDH
ns
ns
ns
ns
Clock low to output valid time
Data in set-up time
Data in hold time
≤11
≤5
≤5
(1) The timing values apply to the specification of the peripheral flash device, not the DLPC34xx controller. For example, the flash device
minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.
(2) The DLPC34xx does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to
a logic high on the PCB through an external pullup.
In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin
must be supplied with the corresponding voltage. The DLPC34xx Validated SPI Flash Device Options table
contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx
controller.
表7-6. DLPC34xx Validated SPI Flash Device Options(1) (2) (3)
DENSITY (Mb)
VENDOR
PART NUMBER
1.8-V COMPATIBLE DEVICES
W25Q40BWUXIG
PACKAGE SIZE
4 Mb
4 Mb
8 Mb
Winbond
Macronix
Macronix
2 × 3 mm USON
MX25U4033EBAI-12G
1.43 × 1.94 mm WLCSP
1.68 × 1.99 mm WLCSP
MX25U8033EBAI-12G
2.5- OR 3.3-V COMPATIBLE DEVICES
Winbond W25Q16CLZPIG
16 Mb
5 × 6 mm WSON
(1) The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC34xx controller. Make sure to order the device that
supports the correct supply voltage as multiple voltage options are often available.
(2) Numonyx (Micron) serial flash devices typically do not support the 4-KB sector size compatibility requirement for the DLPC34xx
controller.
(3) The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC34xx controller,
but they have not been formally validated by TI.
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7.3.3.2 SPI Flash Programming
The SPI pins of the flash can directly be driven for flash programming while the DLPC34xx controller I/Os are tri-
stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state
while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.
Alternatively, the DLPC34xx controller can program the SPI flash itself when commanded via I2C if a valid
firmware image has already been loaded and the controller is operational.
7.3.4 I2C Interface
Both of the DLPC34xx I2C interface ports support a 100-kHz baud rate. Because I2C interface transactions
operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices
in the system.
7.3.5 Content Adaptive Illumination Control (CAIC)
Content Adaptive Illumination control (CAIC) is part of the IntelliBright® suite of advanced image processing
algorithms that adaptively enhances brightness and reduces power. In common real-world image content most
pixels in the images are well below full scale for the R (red), G (green), and B (blue) digital channels input to the
DLPC34xx. As a result of this, the average picture level (APL) for the overall image is also well below full scale,
and the dynamic range for the collective set of pixel values is not fully used. CAIC takes advantage of the
headroom between the source image APL and the top of the available dynamic range of the display system.
CAIC evaluates images on a frame-by-frame basis and derives three unique digital gains, one for each of the R,
G, and B color channel. During image processing, CAIC applies each gain to all pixels in the associated color
channel. The calculated gain is applied to all pixels in that channel so that the pixels as a group collectively shift
upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the
point where just a few pixels in each color channel are clipped. The Source Pixels for a Color Channel and
Pixels for a Color Channel After CAIC Processing figures below show an example of the application of CAIC for
one color channel.
Single-pixel
Headroom
255
255
APL Headroom
Clipped
to 255
166
110
Time
Time
(1) APL = 110
.
(1) APL = 166
(2) Channel gain = 166/110 = 1.51
图7-6. Source Pixels for a Color Channel
图7-7. Pixels for a Color Channel After CAIC
Processing
Above, 图 7-7 shows the gain that is applied to a color processing channel inside the DLPC34xx. Additionally,
CAIC adjusts the power for the R, G, and B LED by commanding different LED currents. For each color channel
of an individual frame, CAIC intelligently determines the optimal combination of digital gain and LED power. The
user configurable CAIC settings heavily influence the amount of digital gain that is applied to a color channel and
the LED power for that color.
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0.33
0.22
0.18
(1)
CAIC Disabled
= 1 W
CAIC Enabled
P
TOTAL
P
= 0.73 W
TOTAL
(1) With CAIC enabled, if red and blue LEDs require less than nominal power for a given input image, the red and blue LED power will
reduce.
图7-8. CAIC Power Reduction Mode (for Constant Brightness)
As CAIC applies a digital gain to each color channel and adjusts the power to each LED, CAIC ensures the
resulting color balance in the final image matches the target color balance for the projector system. Thus, the
effective displayed white point of images is held constant by CAIC from frame to frame.
CAIC can be used to increase the overall image brightness while holding the total power for all LEDs constant,
or CAIC can be used to hold the overall image brightness constant while decreasing LED power. In summary,
CAIC has two primary modes of operation:
• Power reduction mode holds overall image brightness constant while reducing LED power
• Enhanced brightness mode holds overall LED power constant while enhancing image brightness
In power reduction mode, since the R, G, and B channels can be gained up by CAIC inside the DLPC34xx, the
LED power can be reduced for any color channel until the brightness of the color on the screen is unchanged.
Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as
if CAIC was not used. 图 7-8 shows an example of LED power reduction by CAIC for an image where the red
and blue LEDs can consume less power.
In enhanced brightness mode the R, G, and B channels can be gained up by CAIC with LED power generally
being held constant. This results in an enhanced brightness with no power savings.
While there are two primary modes of operation described, the DLPC34xx actually operates within the extremes
of pure power reduction mode and enhanced brightness mode. The user can configure which operating mode
the DLPC34xx will more closely follow by adjusting the CAIC gain setting as described in the software
programmer's guide.
In addition to the above functionality, CAIC also can be used as a tool with which FOFO (full-on full-off) contrast
on a projection system can be improved. While operating in power reduction mode, the DLPC34xx reduces LED
power as the intensity of the image content for each color channel decreases. This process will result in the
LEDs operating at nominal settings with full-on content (a white screen) and reducing power output until the
dimmest possible content (a black screen) is reached. In this latter case, the LEDs will be operating at minimum
power output capacity and thus producing the minimum possible amount of off-state light. This optimization
provided by CAIC will thereby improve FOFO contrast ratio. The given contrast ratio will further increase as
nominal LED current (full-on state) is increased.
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7.3.6 Test Point Support
The DLPC34xx test point output port, TSTPT_(7:0), provides selected system calibration and controller debug
support. These test points are inputs when reset is applied. These test points are outputs when reset is released.
The controller samples the signal state upon the release of system reset and then uses the captured value to
configure the test mode until the next time reset is applied. Because each test point includes an internal
pulldown resistor, external pullups must be used to modify the default test configuration.
The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce
switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is
recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for
a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially
adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points
are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is
released does not have any effect until the next time reset asserts and releases. 表 7-7 describes the test mode
selections for one programmable scenario defined by TSTPT_(2:0).
表7-7. Test Mode Selection Scenario Defined by TSTPT_(2:0)
NO SWITCHING ACTIVITY
CLOCK DEBUG OUTPUT
TSTPT OUTPUT VALUE(1)
TSTPT_(2:0) = 0b000
TSTPT_(2:0) = 0b010
60 MHz
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
TSTPT_4
TSTPT_5
TSTPT_6
TSTPT_7
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
30 MHz
0.7 to 22.5 MHz
HIGH
LOW
HIGH
HIGH
7.5 MHz
(1) These are default output selections. Software can reprogram the selection at any time.
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7.3.7 DMD Interface
The DLPC34xx controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface
and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.
7.3.7.1 Sub-LVDS (HS) Interface
Internal software selection allows the controller to support multiple DMD interface swap configurations. These
options can improve board layout by remapping specific combinations of DMD interface lines to other DMD
interface lines as needed. 表7-8 shows the four options available for the DLP160CP DMD.
表7-8. DLP160CP (0.16 nHD) DMD - Controller to 4-Lane DMD Pin Mapping Options
DLPC3421 Controller 4-LANE DMD ROUTING OPTIONS
DMD PINS
Option 1
Option 2
Option 3
Option 4
Swap Control = x0
Swap Control = x2
Swap Control = x1
Swap Control = x3
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
Input DATA_p_1
Input DATA_n_1
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
Input DATA_p_2
Input DATA_n_2
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
Input DATA_p_3
Input DATA_n_3
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600-MHz sub-LVDS DDR (High Speed)
Leave Open
DLPC34xx
DMD_HS_WDATA_A_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_B_P
Leave Open
DMD_HS_WDATA_C_N
DMD_HS_WDATA_C_P
(Example DMD)
DLP160xx
Sub-LVDS-DMD
DMD_HS_WDATA_D_N
DMD_HS_WDATA_D_P
DMD_HS_CLK_N
DMD_HS_CLK_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_G_P
Leave Open
Leave Open
DMD_HS_WDATA_H_N
DMD_HS_WDATA_H_P
DMD_LS_CLK
DMD_LS_WDATA
DMD_DEN_ARSTZ
DMD_LS_RDATA
120-MHz SDR (Low Speed)
图7-9. DLP160CP (0.16 nHD) DMD Interface Example
The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the
total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,
and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires
attention to many factors.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and
Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both
waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).
Variation from these recommendations may also work, but should be confirmed with PCB signal integrity
analysis or lab measurements.
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7.4 Device Functional Modes
The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON
(GPIO_08).
• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the
DMD.
• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.
7.5 Programming
The DLPC34xx controller contains an Arm® Cortex®-M3 processor with additional functional blocks to enable
video processing and control. TI provides software as a firmware image. The customer is required to flash this
firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and
regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.
The available controller functions depend on the firmware version installed. Different firmware is required for
different chipset combinations (such as when using different PMIC devices). See Documentation Support at the
end of this document or contact TI to view or download the latest published software.
Users can modify software behavior through I2C interface commands. For a list of commands, view the software
user's guide accessible through the Documentation Support page.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The DLPC34xx controller is used with the DLP160CP DMD to provide a reliable display solution for many data
and video display applications. The DMDs are spatial light modulators which reflect incoming light from an
illumination source to one of two directions, with the primary direction being into projection or collection optics.
The optical architecture of the system and the format of the image digital data coming into the DLPC34xx are
what primarily determine the application requirements.
Click these links to find more information about typical applications:
Mobile projector, Smart display, Smartphone, Tablet (multimedia), Augmented reality glasses, Smart home
display, or Pico projector.
8.2 Typical Application
A common application when using the DLPC34xx controller with the DLP160CP DMD and the DLPA200x
PMIC/LED driver is to create a Pico projector embedded in a handheld product. For example, a Pico projector
may be embedded in a smartphone, a tablet, or a camera. The controller in the Pico projector embedded module
typically receives images from a host processor within the product.
1.1 V
1.1 Reg
L3
SYSPWR
L2
DC
Supplies
1.8 V
1.8 V external
L1
DLPA200x
VSPI
V
LED
1.8 V
PROJ_ON
LED_SEL (2)
SPI (4)
PROJ_ON
GPIO_8
SPI1
2
I C
RESETZ
PARKZ
R
LIM
INTZ
1.1 V
Thermistor
Video
Front End
HOST_IRQ
DSI (10)
CMP_OUT
HDMI
VDDLP12
VDD
Illumination
optics
Parallel Interface (28)
Flash
DLPC34xx
System
Controller
RC_
CHARGE
SPI (4)
SPI0
GPIO_10
Keypad
V
, V
BIAS OFFSET
,
VCC_18
1.8 V
TI DLP Chipset
Non-TI Device
V
RESET
DMD
VCC_INTF
VCC_FLSH
CTRL
Sub-LVDS DATA
1.8 V
图8-1. Typical Simplified Application Schematic (using DLPA200x)
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8.2.1 Design Requirements
A Pico projector can be created by using the DLP chipset that includes the DLP160CP (0.16 nHD) DMD, the
DLPC34xx controller, and the DLPA200x PMIC/LED driver. The DLPC34xx controller processes the digital
images, the DLPA200x PMIC provides the analog functions for the chipset, and the DMD displays the image for
projection.
In addition to the three DLP devices in the chipset, other components may be needed. At a minimum, a flash
device is needed to store the firmware that controls the DLPC34xx controller.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These LEDs are
often contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the Pico projector.
To receive images, connect the DLPC34xx controller to the host processor using the parallel (or potentially DSI)
interface. To send commands to the controller, connect it to the host processor using the I2C interface.
The only required power supplies that are external to the projector system chipset are the battery (SYSPWR)
and possibly a regulated 1.8-V supply (some TI PMICs generate the 1.8-V supply but the DLPA200x does not).
The entire projector chipset can be turned on and off by using a single signal called PROJ_ON. When
PROJ_ON is high, the chipset turns on and can begin displaying images. When PROJ_ON is set low, the
projector chipset turns off and draws just microamps of current on SYSPWR. If 1.8 V is supplied separately from
the PMIC (as is the case with the DLPA200x), when PROJ_ON is set low, the 1.8-V supply can continue to be
left at 1.8 V and used by other non-projector sections of the product.
8.2.2 Detailed Design Procedure
For connecting the DLP160CP (0.16 nHD) DMD, DLPC34xx controller, and DLPA200x PMIC, see the reference
design schematic and board layout TIDA-080002. When a circuit board layout is created from this schematic, a
small circuit board is possible. Follow the layout guidelines to design a reliable projector.
It is typical for an optical engine manufacturer to supply the optical engine that includes the LED packages and a
mounted DMD. These manufacturers specialize in designing optics for DLP projectors. There exists production-
ready optical modules, optical module manufacturers, and design houses.
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is shown in 图 8-2. For the LED currents shown, it is assumed that
the same current amplitude is applied to the red, green, and blue LEDs. The shape of the curve depends on the
LED devices used as well as the LED system-level heat sink implementation.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300 400
Current (mA)
500
600
700
D001
图8-2. Typical Luminance vs Current
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9 Power Supply Recommendations
9.1 PLL Design Considerations
It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.
However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.
9.2 System Power-Up and Power-Down Sequence
Although the DLPC34xx controller requires an array of power supply voltage pins (for example, VDD, VDDLP12,
VDD_PLLM/D, VCC18, VCC_FLSH, and VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is
assumed to be the typical configuration), then there are no restrictions regarding the relative order of power
supply sequencing to avoid damaging the DLPC34xx controller (this remains true for both power-up and power-
down scenarios). The controller requires no minimum delay time between powering-up and powering-down the
individual supplies if the VDDLP12 is tied to the 1.1-V VDD supply.
However, if the VDDLP12 pin is not tied to the VDD supply, then the VDDLP12 pin must be powered-on only
after the VDD supply is powered-on. And in a similar sequence, the VDDLP12 pin must be powered-off before
the VDD supply is powered-off. If the VDDLP12 pin is not tied to VDD, then the VDDLP12 pin and VDD supply
pins must be powered-on or powered-off within 100 ms of each other.
Although there is no risk of damaging the DLPC34xx controller when the above power sequencing rules are
followed, these additional power sequencing recommendations must be considered to ensure proper system
operation:
• To ensure that the DLPC34xx controller output signal states behave as expected, all controller I/O supplies
are encouraged to remain applied while VDD core power is applied. If VDD core power is removed while the
I/O supply (VCC_INTF) is applied, then the output signal states associated with the inactive I/O supply go to
a high impedance state.
• Because additional power sequencing rules may exist for devices that share the supplies with the DLPC34xx
controller (such as the PMIC and DMD), these devices may force additional system power sequencing
requirements.
图 9-1, 图 9-2, and 图 9-3 show the DLPC34xx power-up sequence, the normal PARK power-down sequence,
and the fast PARK power-down sequence of a typical DLPC34xx system.
When the VDD core power is applied, but I/O power is not applied, the controller may draw additional leakage
current. This leakage current does not affect the normal DLPC34xx controller operation or reliability.
备注
During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms
after PROJ_ON goes low. Doing so allows the DMD to be parked and the power supply rails to safely
power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended
that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least
50 ms after PROJ_ON goes low.
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Signals
from PMIC
from other source
Pre-Initial-
ization
Power
Startup
System State
Initialization
Regular Operation
SYSPWR
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12 (if not tied to VDD)
VCC18 (1.8 V)
(a)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
(b)
(c)
(d)
(e)
I2C (activity)
t1
t2
t3
t0
t0:
t1:
SYSPWR applied to the PMIC. All other voltage rails are derived from SYSPWR.
All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different
external supply.
t2:
Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.
HOST_IRQ goes low to indicate initialization is complete.
t3:
(a):
(b):
(c):
VDDLP12 must be powered on after VDD if it is supplied from a separate source.
PLL_REFCLK is allowed to be active before power is applied.
PLL_REFCLK must be stable within 5 ms of all power being applied. For external oscillator applications this is oscillator
dependent, and for crystal applications this is crystal and controller oscillator cell dependent.
(d):
(e):
PARKZ must be high before RESETZ releases to support auto-initialization. RESETZ must also be held low for at least 5 ms
after the power supplies are in specification.
I2C activity cannot start until HOST_IRQ goes low to indicate auto-initialization completes.
图9-1. System Power-Up Waveforms
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Signals
from PMIC
from other source
Normal
Park
System State
Regular operation
Power supply shutdown
(b)
SYSPWR
(c)
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not ed to VDD)
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
(a)
I2C (activity)
t1
t2
t3
t4
t5
t1:
t2:
t3:
t4:
t5:
(a):
(b):
PROJ_ON goes low to begin the power down sequence.
The controller finishes parking the DMD.
RESETZ is asserted which causes HOST_IRQ to be pulled high.
All controller power supplies are turned off.
SYSPWR is removed now that all other supplies are turned off.
I2C activity must stop before PROJ_ON is deasserted (goes low).
The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and
VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is
deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore
recommended to follow note (c).
(c):
It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the
DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.
图9-2. Normal Park Power-Down Waveforms
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Signals
from PMIC
from other source
Fast
Park
(a)
System State
Regular operation
Power supplies collapse
SYSPWR
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not ed to VDD)
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
(b)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
I2C (activity)
t1
t3
t4
t2
t1:
A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to
initiate a fast park of the DMD.
t2:
t3:
t4:
(a):
The controller finishes the fast park procedure.
RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.
Eventually all power supplies that were derived from SYSPWR collapse.
VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within
specification for a minimum of 32 µs after PARKZ is asserted (goes low).
(b):
VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet.
Also see the DLPA200x datasheets for more information.
图9-3. Fast Park Power-Down Waveforms
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9.3 Power-Up Initialization Sequence
An external power monitor is required to hold the DLPC34xx controller in system reset during the power-up
sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller
voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The
external power monitoring is automatically done by the DLPA200x PMIC.
No signals output by the DLPC34xx controller will be in their active state while RESETZ is asserted. The
following signals are tri-stated while RESETZ is asserted:
• SPI0_CLK
• SPI0_DOUT
• SPI0_CSZ0
• SPI0_CSZ1
• GPIO [19:00]
Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be
configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the
PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.
Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after
RESETZ is set high.
The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power
is applied:
• LED_SEL_0
• LED_SEL_1
• DMD_DEN_ARSTZ
After power is stable and the PLL_REFCLK_I clock input to the DLPC34xx controller is stable, then RESETZ
should be deactivated (set to a logic high). The DLPC34xx controller then performs a power-up initialization
routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of
RESETZ, all DLPC34xx I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ
signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup
resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively
drives it high. Upon completion of the auto-initialization routine, the DLPC34xx controller will drive HOST_IRQ
low to indicate the initialization done state of the controller has been reached.
To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be
deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine
must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting
PROJ_ON).
备注
No I2C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.
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9.4 DMD Fast Park Control (PARKZ)
PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages
drop below specifications. Typically, the PARKZ signal is provided by the DLPA200x interrupt output signal.
PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on
the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park
operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue
running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to
allow the park operation to complete.
Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host
processor (for example, when the external power source has been disconnected or the battery has dropped
below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The
longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically
only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park
operation takes much longer than 32 µs to park the mirrors. During a Normal Park operation, the DLPA200x
keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.
Additionally, the DLPA200x may hold the supplies on for a period of time after the parking has been completed.
View the relevant DLPA200x datasheet for more information. The longer mirror parking time ensures the longest
DMD lifetime and reliability. The DMD Parking Switching Characteristics section specifies the park timings.
9.5 Hot Plug I/O Usage
The DLPC34xx controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).
This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the
controller does not load the input signal nor draw excessive current that could degrade controller reliability. For
example, the I2C bus from the host to other components is not affected by powering off VCC_INTF to the
DLPC34xx controller. The allows additional devices on the I2C bus to be utilized even if the controller is not
powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back
to the host.
If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input
buffer may experience added leakage current; however, the added leakage current does not damage the
DLPC34xx controller.
However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which
prevents communication on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin
for any system that has additional secondary devices on this bus.
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10 Layout
10.1 Layout Guidelines
For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for
TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the
use of 1-oz (or greater) copper planes to manage the controller package heat.
10.1.1 PLL Power Layout
Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The
DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,
VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground
pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the
spectrum of noise absorption). It is recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all
four components as close to the controller as possible. It is especially important to keep the leads of the high
frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and
VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.
Select ferrite beads with these characteristics:
• DC resistance less than 0.40 Ω
• Impedance at 10 MHz equal to or greater than 180 Ω
• Impedance at 100 MHz equal to or greater than 600 Ω
The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog
signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both
capacitors and then through the series ferrites to the power source. Make the power and ground traces as short
as possible, parallel to each other, and as close as possible to each other.
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signal via
via to common analog digital board power plane
via to common analog digital board ground plane
PCB pad
Controller pad
1
2
3
4
5
A
Signal
Signal
VSS
Signal
F
VSS_
PLLM
G
Signal
VSS
VSS
Signal
Local
decoupling
for the PLL
digital
GND
FB
FB
supply
PLL_
REF
CLK_I
VDD_
PLLM
VSS_
PLLD
H
1.1-V
Power
PLL_
REF
CLK_O
Crystal
Circuit
VDD_
PLLD
J
VSS
VDD
图10-1. PLL Filter Layout
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10.1.2 Reference Clock Layout
The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or
oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200
ppm (including aging, temperature, and trim component variation).
图10-2 shows the required discrete components when using a crystal.
PLL_REFCLK_I
PLL_REFCLK_O
RFB
RS
Crystal
CL1
CL2
CL = Crystal load capacitance (farads)
CL1 = 2 × (CL –Cstray_pll_refclk_i)
CL2 = 2 × (CL –Cstray_pll_refclk_o)
where:
•
•
Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.
Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.
图10-2. Required Discrete Components
10.1.2.1 Recommended Crystal Oscillator Configuration
表10-1. Crystal Port Characteristics
PARAMETER
NOM
UNIT
pF
PLL_REFCLK_I TO GND capacitance
PLL_REFCLK_O TO GND capacitance
1.5
1.5
pF
表10-2. Recommended Crystal Configuration
PARAMETER (1) (2)
RECOMMENDED
UNIT
Crystal circuit configuration
Crystal type
Parallel resonant
Fundamental (first harmonic)
24
Crystal nominal frequency
MHz
PPM
ms
Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200
Maximum startup time
1.0
Crystal equivalent series resistance (ESR)
Crystal load
120 (max)
Ω
6
pF
RS drive resistor (nominal)
RFB feedback resistor (nominal)
CL1 external crystal load capacitor
CL2 external crystal load capacitor
100
1
Ω
MΩ
pF
See equation in 图10-2 notes
See equation in 图10-2 notes
pF
A ground isolation ring around the
crystal is recommended
PCB layout
(1) Temperature range of –30°C to 85°C.
(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).
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If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx
controller, and the PLL_REFCLK_O pin must be left unconnected.
表10-3. Recommended Crystal Parts
TEMPERATURE
AND AGING
(ppm)
LOAD
CAPACITANCE
(pF)
PACKAGE
DIMENSIONS
(mm)
MAXIMUM
ESR (Ω)
MANUFACTURER
SPEED
(MHz)
PART NUMBER
(1) (2)
KDS
DSX211G-24.000M-8pF-50-50
XRCGB24M000F0L11R0
24
24
±50
120
120
8
6
2.0 × 1.6
2.0 × 1.6
Murata
±100
NX2016SA 24M
EXS00A-CS05733
NDK
24
±145
120
6
2.0 × 1.6
(1) The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but
have not necessarily been validated by TI.
(2) Operating temperature range: –30°C to 85°C for all crystals.
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10.1.3 DSI Interface Layout
Follow these PCB layout guidelines for the DSI LVDS interface to ensure proper DSI operation.
• Route the differential clock and data lines to match 50-Ωsingle-ended and 100-Ωdifferential impedance.
• The length of dp and dn should be matched. If that is not possible, ensure that dp is only slightly longer than
dn (delta delay not to exceed 8-10 ps), especially for the clock-lane. Doing so prevents propagation on the
clock lane during the HS to LP transition.
• No thru-hole vias permitted on high-speed traces.
• Create trace routes on top or bottom layers preferably.
• Must have a ground reference plane.
• Avoid power plane transitions in upper or lower layers.
• Avoid using SMD (surface mount device) resistors larger than 0402. If resistors are used in the traces, ensure
that the layer below has a void.
• No thru-hole SMA (SubMiniature version A) connectors.
• Minimize trace length as much as possible.
• Perform signal integrity simulations to ensure board performance.
10.1.4 Unused Pins
To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused
controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For
controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown
unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be
expected to drive an external device. The DLPC34xx controller implements very few internal resistors and are
listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown
resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8
kΩ.
Never tie unused output-only pins directly to power or ground. Leave them open.
When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that
the pin can remain open. If this control is not available and the pins may become an input, then include an
appropriate pullup (or pulldown) resistor.
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10.1.5 DMD Control and Sub-LVDS Signals
表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations
SIGNAL INTERCONNECT TOPOLOGY
DMD BUS SIGNAL(1) (2)
UNIT
SINGLE-BOARD SIGNAL
MULTI-BOARD SIGNAL
ROUTING LENGTH
ROUTING LENGTH
DMD_HS_CLK_P
6.0
in
See (3)
DMD_HS_CLK_N
(152.4)
(mm)
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
6.0
in
See (3)
(152.4)
mm
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
6.5
in
DMD_LS_CLK
See (3)
See (3)
See (3)
See (3)
(165.1)
(mm)
6.5
in
DMD_LS_WDATA
DMD_LS_RDATA
(165.1)
(mm)
6.5
in
(165.1)
(mm)
7.0
in
DMD_DEN_ARSTZ
(177.8)
(mm)
(1) Maximum signal routing length includes escape routing.
(2) Multi-board DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS
model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.
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表10-5. High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1) (2) (3)
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH(4)
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_CLK_P
DMD_HS_CLK_N
±1.0
in
DMD(5)
(±25.4)
(mm)
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
±0.025
in
DMD
DMD
DMD
DMD
DMD_HS_WDATA_x_P
DMD_HS_CLK_P
DMD_HS_WDATA_x_N
DMD_HS_CLK_N
DMD_LS_CLK
N/A
(±0.635)
(mm)
±0.025
in
(±0.635)
(mm)
DMD_LS_WDATA
DMD_LS_RDATA
±0.2
in
(±5.08)
(mm)
in
DMD_DEN_ARSTZ
N/A
(mm)
(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx
controller or the DMD require no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data
lines.
(3) DMD LS signals are single ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.
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表10-6. Signal Requirements
PARAMETER
REFERENCE
REQUIREMENT
DMD_LS_WDATA
Required
DMD_LS_CLK
Required
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
Acceptable
Source series termination
Required
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
Not acceptable
68 Ω±10%
68 Ω±10%
68 Ω±10%
68 Ω±10%
100 Ω±10%
100 Ω±10%
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
Endpoint termination
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
DMD_LS_WDATA
DMD_LS_CLK
PCB impedance
SDR (single data rate) referenced to DMD_LS_DCLK
SDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZ
DMD_LS_RDATA
DMD_HS_WDATA_x_y
DMD_HS_CLK_y
SDR
Signal type
SDR referenced to DMD_LS_DLCK
sub-LVDS
sub-LVDS
10.1.6 Layer Changes
• Single-ended signals: Minimize the number of layer changes.
• Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the
signals of a given pair do not change layers.
10.1.7 Stubs
• Avoid using stubs.
10.1.8 Terminations
• DMD_HS differential signals require no external termination resistors.
• Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ωseries termination resistor
located as close as possible to the corresponding controller pins.
• Make sure the DMD_LS_RDATA signal path includes a 43-Ωseries termination resistor located as close as
possible to the corresponding DMD pin.
• The DMD_DEN_ARSTZ pin requires no series resistor.
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10.1.9 Routing Vias
• The number of vias on DMD_HS signals must be minimized and ideally not exceed two.
• Any and all vias on DMD_HS signals must be located as close to the controller as possible.
• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not
exceed two.
• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the
controller as possible.
10.1.10 Thermal Considerations
The underlying thermal limitation for the DLPC34xx controller is that the maximum operating junction
temperature (TJ) not be exceeded (this is defined in the Recommended Operating Conditions section).
Some factors that influence TJ are as follows:
• operating ambient temperature
• airflow
• PCB design (including the component layout density and the amount of copper used)
• power dissipation of the DLPC34xx controller
• power dissipation of surrounding components
The controller package is designed to primarily extract heat through the power and ground planes of the PCB.
Thus, copper content and airflow over the PCB are important factors.
The recommends maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC34xx controller power dissipation and RθJA at 0 m/s of forced airflow, where RθJA is
the thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz
power planes. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB, so the
reported thermal resistance may not be accurate in the actual product application. Although the actual thermal
resistance may be different, it is the best information available during the design phase to estimate thermal
performance. TI highly recommended that thermal performance be measured and validated after the PCB is
designed and the application is built.
To evaluate the thermal performance, measure the top center case temperature under the worst case product
scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the
controller does not exceed the maximum recommended case temperature (TC). This specification is based on
the measured φJT for the DLPC34xx controller package and provides a relatively accurate correlation to junction
temperature.
Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI
recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that
they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally
conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead
through the wires.
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10.2 Layout Example
图10-3. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Device Nomenclature
11.1.2.1 Device Markings
1
DLPC342xZVB
2
YMZLLLS SC
Pin (terminal) A1 corner identifier
Marking Definitions:
Line 1:
Line 2:
DLP Device Name: DLPC342x where x is a "1" for this device
YMZLLLS SC: Foundry lot code for semiconductor wafers and lead-free solder ball marking
YM: Year Month
Z, S: Assembly site
LLL: Assembly lot traceability
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content
less than or equal to 1.5% and that the mold compound meets TI's definition of green
备注
1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For
example, 2512737-0001X.
2. See 节7.3.1.1, for DLPC342x resolutions on the DMD supported per part number.
11.1.3 Video Timing Parameter Definitions
See 图11-1 for a visual description.
Active Lines Per Frame Defines the number of lines in a frame containing displayable data. ALPF is a
(ALPF)
subset of the TLPF.
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Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data. APPL is a
(APPL) subset of the TPPL.
Horizontal Back Porch Defines the number of blank pixel clocks after the active edge of horizontal sync but
(HBP) Blanking before the first active pixel.
Horizontal Front Porch Defines the number of blank pixel clocks after the last active pixel but before
(HFP) Blanking horizontal sync.
Horizontal Sync (HS or Timing reference point that defines the start of each horizontal interval (line). The
Hsync)
active edge of the HS signal defines the absolute reference point. The active edge
(either rising or falling edge as defined by the source) is the reference from which all
horizontal blanking parameters are measured.
Total Lines Per Frame Total number of active and inactive lines per frame; defines the vertical period (or
(TLPF) frame time).
Total Pixel Per Line Total number of active and inactive pixel clocks per line; defines the horizontal line
(TPPL) period in pixel clocks.
Vertical Sync (VS or Timing reference point that defines the start of the vertical interval (frame). The
Vsync)
absolute reference point is defined by the active edge of the VS signal. The active
edge (either rising or falling edge as defined by the source) is the reference from
which all vertical blanking parameters are measured.
Vertical
Back
Porch Defines the number of blank lines after the active edge of vertical sync but before
(VBP) Blanking
the first active line.
Vertical Front Porch Defines the number of blank lines after the last active line but before the active edge
(VFP) Blanking
of vertical sync.
TPPL
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
Horizontal
Front
Porch
TLPF
ALPF
(HBP)
(HFP)
Vertical Front Porch (VFP)
图11-1. Parameter Definitions
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11.2 Related Documentation
The following table lists quick access links for associated parts of the DLP chipset.
表11-1. Chipset Documentation
TECHNICAL
DOCUMENTS
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TOOLS & SOFTWARE
DLPA2000
DLPA2005
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
DLP160CP
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表11-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DLPC3421
Click here
Click here
Click here
Click here
Click here
11.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.6 Trademarks
Pico™ and TI E2E™ are trademarks of Texas Instruments.
MIPI® is a registered trademark of MIPI Alliance.
DLP® is a registered trademark of Texas Instruments.
IntelliBright® is a registered trademark of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
所有商标均为其各自所有者的财产。
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13 Package Option Addendum
13.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Orderable Device
Status (1)
Pins
Eco Plan (2) Lead/Ball Finish
TBD Call TI
MSL Peak Temp (3)
Op Temp (°C)
Device Marking(4) (5)
DLPC3421CZVB
ACTIVE
NFBGA
ZVB
176
260
Level-3-260C-168 HRS
DLPC342x
–30 to 85°C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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