DLPC3437CZEZ_技术文档

DLPC3437

ZHCSHH9D –JANUARY 2017 –REVISED AUGUST 2021

DLPC3437 显示控制器

1 特性

2 应用

• 适用于DLP3310 (.33 1080p) DMD 的显示控制器

• DLP 标牌

• 移动投影仪

• 移动智能电视

• 智能家居显示

• Pico 投影仪

– 两个DLP3437 控制器驱动DLP3310 DMD

– 最高支持1080p 的输入图像大小

– 支持接口训练的低功耗DMD 接口

• 输入帧速率高达120 Hz（1080p 分辨率时为

60Hz）

3 说明

• 像素数据处理：

DLPC3437 数字控制器是 DLP3310 (.33 1080p) 芯片

组的组成部分，用于支持 DLP3310 数字微镜器件

(DMD) 的可靠运行。DLPC3437 控制器在系统电子设

备与 DMD 之间提供一个方便的多功能接口，从而实现

了小外形尺寸的低功耗高分辨率全HD 显示屏。

– IntelliBright^™图像处理算法套件

• 内容自适应照明控制(CAIC)

• 局部亮度增强(LABB)

– 色彩坐标调整

– 可编程degamma

访问TI DLP^®Pico^™显示技术入门页面，并查看编程人

员指南了解详情。

– 图像大小调整（缩放）

– 色彩空间转换

• 24 位输入像素接口支持：

– 并行接口协议

– 高达155MHz 的像素时钟

– 多个输入像素数据格式选项

• 双路FPD-link 输入像素接口支持利用所需的

FPGA：

该芯片组提供现成的资源，可帮助用户加快设计周期。

这些资源包括可直接用于生产环境的光学模块、光学

模块制造商和设计公司。

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DLPC3437

NFBGA (201)

13.00mm x 13.00mm

– LVDS 接口

– 有效像素时钟高达155 MHz

• 支持外部闪存

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 断电时自动DMD 停止

• 嵌入式帧存储器(eDRAM)

• 系统特性：

– 器件配置的I²C 控制

– 可编程启动界面

– 可编程LED 电流控制

– 一帧延迟

• 与DLPA3000 或DLPA3005 PMIC（电源管理集成

电路）和LED 驱动器配对使用

SYSPWR

V

LED

PROJ_ON

1.8 V

SPI1

GPIO_8

I2C_0

DLPA300x

2

I

RESETZ

PARKZ

C

Illumination

optics

R

LIM

HOST_IRQ

SPI (4)

VDD

SPI0

VDDLP12

DLPC3437

Parallel

ACT_SYNC

FPGA_RDY

1.8 V

CTRL

FPGA

XC7Z020-

1CLG484I4493

Sub-LVDS

Parallel

(28)

VCC_18

VCC_INTF

VCC_FLSH

DLPC3437

RESETZ

V

OFFSET

,

RESETZ

I2C_1

V

,

BIAS

I2C_0

I2C_1

PARKZ

VDDLP12

VDD

FPD-

Link

RESET

DMD

I2C_0

I2C_1

1.8 V

VCC_18

VCC_INTF

SPI

VCC_FLSH

Parallel

Actuator drive circuit

CTRL

Sub-LVDS

DAC_Data

SPI0

DAC_CLK

SPI (4)

典型简化版系统图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS084

DLPC3437

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ZHCSHH9D –JANUARY 2017 –REVISED AUGUST 2021

Table of Contents

7 Detailed Description......................................................25

7.1 Overview...................................................................25

7.2 Functional Block Diagram.........................................25

7.3 Feature Description...................................................26

7.4 Device Functional Modes..........................................40

7.5 Programming............................................................ 41

8 Application and Implementation..................................42

8.1 Application Information............................................. 42

8.2 Typical Application.................................................... 42

9 Power Supply Recommendations................................45

9.1 PLL Design Considerations...................................... 45

9.2 System Power-Up and Power-Down Sequence....... 45

9.3 Power-Up Initialization Sequence.............................49

9.4 DMD Fast PARK Control (PARKZ)............................49

9.5 Hot Plug I/O Usage...................................................50

10 Layout...........................................................................51

10.1 Layout Guidelines................................................... 51

10.2 Layout Example...................................................... 59

11 Device and Documentation Support..........................60

11.1 Device Support........................................................60

11.2 接收文档更新通知................................................... 61

11.3 支持资源..................................................................61

11.4 Trademarks............................................................. 62

11.5 Electrostatic Discharge Caution..............................62

11.6 术语表..................................................................... 62

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications................................................................ 12

6.1 Absolute Maximum Ratings...................................... 12

6.2 ESD Ratings............................................................. 12

6.3 Recommended Operating Conditions.......................13

6.4 Thermal Information..................................................13

6.5 Power Electrical Characteristics............................... 14

6.6 Pin Electrical Characteristics.................................... 15

6.7 Internal Pullup and Pulldown Electrical

Characteristics.............................................................18

6.8 DMD Sub-LVDS Interface Electrical

Characteristics.............................................................18

6.9 DMD Low-Speed Interface Electrical

Characteristics.............................................................19

6.10 System Oscillators Timing Requirements............... 20

6.11 Power Supply and Reset Timing Requirements......20

6.12 Parallel Interface Frame Timing Requirements.......21

6.13 Parallel Interface General Timing Requirements.... 22

6.14 Flash Interface Timing Requirements..................... 23

6.15 Other Timing Requirements....................................24

6.16 DMD Sub-LVDS Interface Switching

Characteristics.............................................................24

6.17 DMD Parking Switching Characteristics................. 24

6.18 Chipset Component Usage Specification............... 24

Information.................................................................... 63

12.1 Package Option Addendum....................................64

4 Revision History

Changes from Revision C (June 2019) to Revision D (August 2021)

Page

• 总数据表格式和订购更新.................................................................................................................................... 1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将提到I²C 或SPI 的旧术语实例全局更改为初级和次级。................................................................................. 1

• Deleted mention of mirror parking time from PARKZ pin description and moved to a specification table.......... 4

• Changed JTAG pin names from Reserved to proper names .............................................................................4

• Deleted support for adjustable DATAEN_CMD polarity .....................................................................................4

• Deleted support for adjusting PCLK capture edge in software ..........................................................................4

• Added DSI pin information..................................................................................................................................4

• Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use

GPIO_10 (RC_CHARGE) instead of CMP_PWM ............................................................................................. 4

• Deleted support for CMP_PWM......................................................................................................................... 4

• Deleted mention of unsupported light sensor on GPIO_13 and GPIO_12 ........................................................ 4

• Deleted reference of the LS_PWR circuit being used for the light sensor..........................................................4

• Deleted mention of the unsupported LABB output sample and hold sensor control signal................................4

• Clarified GPIO_03 - GPIO_01 pins are required to be used as a SPI1 port.......................................................4

• Deleted unneeded VCC_INTF and VCC_FLSH absolute maximum values ................................................... 12

• Changed Updated VDDLP12 information ........................................................................................................13

• Changed incorrect pin tolerance ......................................................................................................................13

• Changed and fixed incorrect test conditions for current drive strengths...........................................................15

• Deleted redundant ǀV_ODǀ specification which is referenced in later sections....................................................15

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• Added minimum and maximum values for V_OHfor I/O type 4.......................................................................... 15

• Added minimum and maximum values for V_OLfor I/O type 4...........................................................................15

• Deleted incorrect reference to 2.5V, 24mA drive ............................................................................................. 15

• Deleted incorrect steady-state common mode voltage reference ................................................................... 15

• Changed high voltage tolerant I/O note to only refer to the I²C buffer and changed VCC to VCC_INTF......... 15

• Added |V_OD| minimum and maximum values, and changed the typical value..................................................18

• Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted

redundant mention of specification, and changed the typical value. ............................................................... 18

• Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted

redundant mention of specification, and changed the typical value. ............................................................... 18

• Corrected the name of the DMD Low-Speed signals from inputs to outputs. ..................................................19

• Deleted V_OH(DC)maximum and V_OL(DC)minimum values. ...............................................................................19

• Added note about DMD input specs being met if a proper series termination resistor is used ....................... 19

• Deleted reference of selecting unsupported oscillator frequency ....................................................................20

• Corrected system oscillator clock period to match clock frequency ................................................................ 20

• Changed pulse duration percent spec from a maximum to a minimum ...........................................................20

• Added condition for VDD rise time ...................................................................................................................20

• Changed the minimum flash SPI_CLK frequency............................................................................................ 23

• Corrected flash interface clock period to match clock frequency .....................................................................23

• Changed DMD HS Clock switching rate from maximum to nominal and added accompanying clock

specification .....................................................................................................................................................24

• Added the 节6.18 section to clarify chipset support requirements...................................................................24

• Added information that the parallel interface isn't ready to accept data until the auto-initialization process is

completed......................................................................................................................................................... 31

• Changed how the 500 ms startup time is described ........................................................................................31

• Changed device markings image and definitions ............................................................................................ 60

Changes from Revision B (January 2018) to Revision C (June 2019)

Page

• Changed mirror parking time from "500 μs" to "20 ms" for PARKZ description in Pin Functions table.............4

• Added 节7.3.7 .................................................................................................................................................36

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5 Pin Configuration and Functions

图5-1. ZEZ Package 201-Pin NFBGA Bottom View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

P

CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM

SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0

A

B

C

D

E

F

LK

DATA

DATAH_P DATAG_P

DATAF_P

DATAE_P

DATAD_P

DATAC_P

DATAB_P

DATAA_P

DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

N

ARSTZ

DATA

DATAH_N DATAG_N

DATAF_N

DATAE_N

DATAD_N

DATAC_N

DATAB_N

DATAA_N

HWTEST_E

N

NC

VDDLP12

VDD

VSS

VCC

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

VSS

VCC

RESETZ SPI0_CSZ1

PARKZ

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

GPIO_00

GPIO_02

GPIO_04

GPIO_06

GPIO_08

GPIO_10

GPIO_12

GPIO_14

GPIO_16

GPIO_01

GPIO_03

GPIO_05

GPIO_07

GPIO_09

GPIO_11

GPIO_13

GPIO_15

GPIO_17

GPIO_19

TSTPT_7

TSTPT_5

TSTPT_3

NC

VDD

VSS

VDD

VSS

VCC_FLSH

VDD

VCC

VSS

VDD

VSS

VDD

VSS

VDD

RREF

VSS

VSS_PLLM

G

H

J

PLL_REFCL

K_I

VDD_PLLM VSS_PLLD

PLL_REFCL

K_O

VDD_PLLD

PDATA_0

PDATA_2

PDATA_4

PDATA_6

VSS

VDD

PDATA_1

PDATA_3

PDATA_5

PDATA_7

VSYNC_WE

PDATA_8

K

L

VSS

VCC_INTF

PCLK

VSS

VDD

3DR

VCC_INTF

VSS

VDD

VCC

JTAGTMS1 GPIO_18

M

N

P

R

PDM_CVS_

TE

HSYNC_CS

VCC_INTF HOST_IRQ IIC0_SDA

IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1

TSTPT_6

TSTPT_4

TSTPT_2

DATEN_CM

D

PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK

JTAGTDI

TSTPT_1

PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22

IIC1_SDA

IIC1_SCL

TSTPT_0

Note: The lower image view is from the top.

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表5-1. Test Pins and General Control

I/O

TYPE⁽⁴⁾

DESCRIPTION

NAME

NO.

Manufacturing test enable signal. Connect this signal directly to ground on the

PCB for normal operation.

HWTEST_EN

C10

I

6

DMD fast park control (active low Input with a hysteresis buffer). This signal is

used to quickly park the DMD when loss of power is imminent. The longest

lifetime of the DMD may not be achieved with the fast park operation,

therefore, this signal is intended to only be asserted when a normal park

operation is unable to be completed. The PARKZ signal is typically provided

from the DLPAxxxx interrupt output signal.

PARKZ

C13

I

6

JTAGTCK

JTAGTDI

P12

P13

I

6

1

6

TI internal use. Leave this pin unconnected.

JTAGTDO1

JTAGTDO2

JTAGTMS1

JTAGTMS2

N13⁽¹⁾

N12⁽¹⁾

M13

O

I

N11

I

TI internal use.

This pin must be tied to ground, through an external resistor for normal

operation. Failure to tie this pin low during normal operation can cause start-

up and initialization problems.⁽²⁾

JTAGTRSTZ

RESETZ

P11

C11

I

6

Power-on reset (active low input with a hysteresis buffer). Self-configuration

starts when a low-to-high transition is detected on RESETZ. All controller

power and clocks must be stable before this reset is de-asserted. No signals

are in their active state while RESETZ is asserted. This pin is typically

connected to the RESET_Z pin of the DLPA300x.

TSTPT_0

TSTPT_1

TSTPT_2

TSTPT_3

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

R12

R13

R14

R15

P14

P15

N14

N15

I/O

1

Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ

is asserted low. Sampled as an input test mode selection control

approximately 1.5 µs after de-assertion of RESETZ, and then driven as

outputs.^{(2) (3)}

Normal use: reserved for test output. Leave open for normal use.

Note: An external pullup may put the DLPC3437 in a test mode. See 节7.3.8

for more information.

(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal

pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an

external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is

recommended to ensure a logic low.

(2) External resistor must have a value of 8 kΩor less to compensate for pins that provide internal pullup or pulldown resistors.

(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal

pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but

there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to

ensure a logic low.

(4) See 表5-10 for type definitions.

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表5-2. Parallel Port Input

DESCRIPTION

PARALLEL RGB MODE

I/O

TYPE⁽⁴⁾

NAME^{(1) (2)}

NO.

PCLK

P3

I

10

5

Pixel clock

Parallel data mask. Programable polarity with

default of active high. Optional signal.

PDM_CVS_TE

N4

I/O

VSYNC_WE

HSYNC_CS

DATAEN_CMD

P1

N5

P2

I

10

Vsync⁽³⁾

Hsync⁽³⁾

Data valid

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

K2

K1

L2

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

L1

I

10

M2

M1

N2

N1

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

R1

R2

R3

P4

R4

P5

R5

P6

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

I

10

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

R6

P7

R7

P8

R8

P9

R9

P10

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

I

10

3D reference

•

For 3D applications: left or right 3D reference

(left = 1, right = 0). To be provided by the host.

Must transition in the middle of each frame (no

closer than 1 ms to the active edge of VSYNC)

If a 3D application is not used, pull this input

low through an external resistor.

3DR

N6

I

10

•

(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.

(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩor less).

(3) VSYNC and HSYNC polarity can be adjusted by software.

(4) See 表5-10 for type definitions.

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表5-3. DSI Input Data and Clock

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DCLKN

DCLKP

E2

E1

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

G2

G1

F2

F1

D2

D1

C2

C1

Unused; leave unconnected and floating.

RREF

F3

—

(1) See 表5-10 for type definitions.

表5-4. DMD Reset and Bias Control

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

DMD driver enable (active high). DMD reset (active low). When

corresponding I/O power is supplied, the controller drives this signal low

after the DMD is parked and before power is removed from the DMD. If the

1.8-V power to the DLPC3437 is independent of the 1.8-V power to the

DMD, then TI recommends including a weak, external pulldown resistor to

hold the signal low in case DLPC3437 power is inactive while DMD power

is applied.

DMD_DEN_ARSTZ

B1

O

2

DMD_LS_CLK

A1

A2

B2

O

I

3

6

DMD, low speed interface clock

DMD, low speed serial write data

DMD, low speed serial read data

DMD_LS_WDATA

DMD_LS_RDATA

(1) See 表5-10 for type definitions.

表5-5. DMD Sub-LVDS Interface

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

DMD_HS_CLK_P

DMD_HS_CLK_N

A7

B7

O

4

DMD high speed interface

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A3

B3

A4

B4

A5

B5

A6

B6

A8

B8

A9

B9

A10

B10

A11

B11

DMD sub-LVDS high speed (HS) interface write data lanes. The true

numbering and application of the DMD_HS_WDATA pins depend on

the software configuration. See 表7-8.

O

4

(1) See 表5-10 for type definitions.

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表5-6. Peripheral Interface

I/O

TYPE⁽³⁾

DESCRIPTION

NAME⁽¹⁾

NO.

Successive approximation ADC (analog-to-digital converter) comparator output

(DLPC3437 Input). To implement, use a successive approximation ADC

(DLPAxxxx) with a thermistor feeding one input of the external comparator and

the DLPC3437 controller GPIO_10 (RC_CHARGE) pin driving the other side of

the comparator. CMP_OUT must be pulled down to ground if this function is not

used. (hysteresis buffer).

CMP_OUT

A12

I

6

CMP_PWM

A15

N8

O

1

9

TI internal use. Leave this pin unconnected.

Host interrupt (output)

HOST_IRQ indicates when the DLPC3437 auto-initialization is in progress and

most importantly, when it completes.

HOST_IRQ⁽²⁾

This pin is tri-stated during reset. An external pullup must be included on this

signal.

I²C target (port 0) SCL (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The target I²C I/Os are 3.6-V

tolerant (high-voltage-input tolerant) and are powered by VCC_INTF (which can

be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to a host supply

with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup

supply voltage does not typically satisfy the V_IHspecification of the target I²C

input buffers).

IIC0_SCL⁽⁴⁾

IIC1_SCL

N10

R11

N9

I/O

7

8

7

8

TI internal use. TI recommends an external pullup resistor.

I²C target (port 0) SDA. (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The target I²C port is the control

port of controller. The target I²C I/O pins are 3.6-V tolerant (high-volt-input

tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V).

External I²C pullups must be connected to a host supply with an equal or higher

supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does

not typically satisfy the V_IHspecification of the target I²C input buffers).

IIC0_SDA⁽⁴⁾

IIC1_SDA

R10

TI internal use. TI recommends an external pullup resistor.

LED enable select. Automatically controlled by the DLPC3437 programmable

DMD sequence

LED_SEL(1:0)

Enabled LED

None

Red

Green

Blue

LED_SEL_0

LED_SEL_1

B15

B14

O

1

00

01

10

11

The controller drives these signals low when RESETZ is asserted and the

corresponding I/O power is supplied. The controller continues to drive these

signals low throughout the auto-initialization process. A weak, external pulldown

resistor is recommended to ensure that the LEDs are disabled when I/O power is

not applied.

SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to

the flash memory clock.

SPI0_CLK

A13

A14

O

13

SPI port 0, chip select 0 (active low output). This pin is typically connected to the

flash memory chip select.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ0

SPI port 0, chip select 1 (active low output). This pin typically remains unused.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ1

C12

O

13

Synchronous serial port 0, receive data in. This pin is typically connected to the

flash memory data out.

SPI0_DIN

B12

B13

I

12

13

Synchronous serial port 0, transmit data out. This pin is typically connected to

the flash memory data in.

SPI0_DOUT

O

(1) External pullup resistor must be 8 kΩor less.

(2) For more information about usage, see 节7.3.2.

(3) See 表5-10 for type definitions.

8

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(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication

on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional target devices

on this bus.

表5-7. GPIO Peripheral Interface

PIN⁽¹⁾

NAME

TYPE⁽¹⁾

I/O

DESCRIPTION⁽²⁾

(3)

NO.

M15

M14

L15

L14

K15

GPIO_19

GPIO_18

GPIO_17

GPIO_16

GPIO_15

I/O

1

HBT_ODAT (Output): Connect to the HBT_IDAT (GPIO_17) pin of the second DLPC3437.

HBT_OCLK (Output): Connect to the HBT_ICLK (GPIO_16) pin of the second DLPC3437.

HBT_IDAT (Input): Connect to the HBT_ODAT (GPIO_19) pin of the second DLPC3437.

HBT_ICLK (Input): Connect to the HBT_OCLK (GPIO_18) pin of the second DLPC3437.

DA_SYNC (BiDir): Connect to the DA_SYNC (GPIO_15) pin of the second DLPC3437.

SEQ_SYNC (BiDir): Connect to the SEQ_SYNC (GPIO_14) pin of the second DLPC3437 with a

7.87k pullup resistor to VCC18.

GPIO_14

GPIO_13

K14

J15

I/O

1

General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise, this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise, this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_12

GPIO_11

J14

I/O

1

General purpose I/O 11 (hysteresis buffer). Options:

1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and

enabled.

H15

2. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output

and left unconnected. Otherwise, this pin requires an external pullup or pulldown to avoid a

floating GPIO input.

General Purpose I/O 10 (hysteresis buffer). Options:

1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.

2. Optional GPIO. If unused, TI recommends this pin be configured as a logic zero GPIO output

and left unconnected. Otherwise, this pin requires an external pullup or pulldown to avoid a

floating GPIO input.

GPIO_10

H14

I/O

1

General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise, this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_09

GPIO_08

G15

G14

I/O

1

General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven

by the PROJ_ON output of the host. A logic low on this signal causes the DLPC3437 to PARK the

DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high

time is 200 ms. The minimum low time is 200 ms.

General purpose I/O 07 (hysteresis buffer). If unused, TI recommends this pin be configured as a

logic zero GPIO output and left unconnected. Otherwise, this pin requires an external pullup or

pulldown to avoid a floating GPIO input.

GPIO_07

GPIO_06

F15

F14

I/O

1

General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise, this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused, TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise, this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_05

GPIO_04

GPIO_03

E15

E14

D15

I/O

1

MST_SLVZ (Input): Primary or secondary controller identifier signal (Primary = 1, Secondary = 0).

General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.

This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to

deactivate this signal during reset and auto-initialization processes.

General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is

typically connected to the DLPAxxxx SPI_DIN pin.

GPIO_02

GPIO_01

D14

C15

I/O

1

General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically

connected to the DLPAxxxx SPI_CLK pin.

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表5-7. GPIO Peripheral Interface (continued)

PIN⁽¹⁾

NAME

TYPE⁽¹⁾

I/O

DESCRIPTION⁽²⁾

(3)

NO.

General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is

typically connected to the DLPAxxxx SPI_DOUT pin.

GPIO_00

C14

I/O

1

(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or

more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as

open-drain.

(2) General purpose I/O for the DLPC3437 controller. These GPIO pins are software configurable.

(3) See 表5-10 for type definitions.

表5-8. Clock and PLL Support

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

Reference clock crystal input. If an external oscillator is used in place of a

crystal, this pin is the oscillator input.

PLL_REFCLK_I

H1

I

11

Reference clock crystal return. If an external oscillator is used in place of a

crystal, leave this pin unconnected (that is floating with no added capacitive

load).

PLL_REFCLK_

O

J1

O

5

(1) See 表5-10 for type definitions.

表5-9. Power and Ground

I/O

TYPE

DESCRIPTION

NAME

NO.

C5, D5, D7,

D12, J4,

J12, K3, L4,

L12, M6,

M9, D9,

D13, F13,

H13, L13,

M10, D3, E3

VDD

PWR

Core 1.1-V power (main 1.1 V)

—

VDDLP12

C3

Reserved –tie to the VDD rail

C4, D6, D8,

D10, E4,

E13, F4, G4,

G12, H4,

H12, J3,

J13, K4,

K12, L3, M4,

M5, M8,

M12, G13,

C6, C8, F6,

F7, F8, F9,

F10, G6,

VSS

GND

Core ground (eDRAM, I/O ground, thermal ground)

—

G7, G8, G9,

G10, H6,

H7, H8, H9,

H10, J6, J7,

J8, J9, J10,

K6, K7, K8,

K9, K10

All 1.8-V I/O power:

C7, C9, D4,

E12, F12,

K13, M11

1.8-V power supply for all I/O pins (RESETZ, PARKZ, LED_SEL,

CMP_OUT, GPIO, IIC1, TSTPT, and JTAG) except the host or parallel

interface and the SPI flash interface.

VCC18

PWR

—

M3, M7, N3,

N7

Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA,

video syncs, and HOST_IRQ pins)

VCC_INTF

VCC_FLSH

PWR

—

Flash interface I/O power: 1.8 V to 3.3 V

(Dedicated SPI0 power pin)

D11

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表5-9. Power and Ground (continued)

I/O

TYPE

DESCRIPTION

NAME

NO.

VDD_PLLM

VSS_PLLM

VDD_PLLD

VSS_PLLD

H2

G3

J2

PWR

RTN

PWR

RTN

MCG PLL (primary clock generator phase lock loop) 1.1-V power

MCG PLL return

—

DCG PLL (DMD clock generator phase lock loop) 1.1-V power

DCG PLL return

H3

表5-10. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

1

2

1.8-V LVCMOS I/O buffer with 8-mA drive

1.8-V LVCMOS I/O buffer with 4-mA drive

1.8-V LVCMOS I/O buffer with 24-mA drive

1.8-V sub-LVDS output with 4-mA drive

1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive

1.8-V LVCMOS input

V_cc18

ESD diode to GND and supply rail

3

V_cc18

4

V_cc18

5

V_{cc_INTF}

V_cc18

V_{cc_INTF}

V_cc18

6

7

1.8-V, 2.5-V, 3.3-V I²C with 3-mA drive

1.8-V I²C with 3-mA drive

8

9

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

Reserved

V_{cc_INTF}

10

11

12

13

1.8-V, 2.5-V, 3.3-V LVCMOS input

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

V_{cc_INTF}

V_{cc_FLSH}

ESD diode to GND and supply rail

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGE⁽²⁾

V_(VDD)

1.21

1.32

1.96

3.60

1.21

V

–0.3

V_(VDDLP12)

V_(VCC18)

DMD sub-LVDS interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)

V_{(VCC_INTF)}

V_{(VCC_FLSH)}

V_{(VDD_PLLM)}(MCG PLL)

V_{(VDD_PLLD)}(DCG PLL)

V_{I2C buffer}(I/O type 7)

GENERAL

See ⁽³⁾

V

T_J

Operating junction temperature

Storage temperature

125

°C

–30

–40

T_stg

(1) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS (GND).

(3) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.045

NOM

1.10

MAX

1.155

UNIT

V

V_(VDD)

Core power 1.1 V (main 1.1 V)

Reserved

V_(VDDLP12)

See⁽³⁾

V

All 1.8-V I/O power:

1.8-V power supply for all I/O pins (RESETZ, PARKZ

LED_SEL, CMP_OUT, GPIO, IIC1, TSTPT, and JTAG)

except the host or parallel interface and the SPI flash

interface.

V_(VCC18)

1.64

1.80

1.96

V

1.64

2.28

1.80

2.50

1.96

2.72

3.58

1.96

2.72

3.58

1.155

85

Host or parallel interface I/O power: 1.8 to 3.3 V (includes

IIC0, PDATA, video syncs, and HOST_IRQ pins)

V_{(VCC_INTF)}

See ⁽¹⁾

V

3.02

3.30

1.64

1.80

V_{(VCC_FLSH)}

Flash interface I/O power: 1.8 V to 3.3 V

2.28

2.50

3.02

3.30

V_{(VDD_PLLM)}

MCG PLL 1.1-V power

See ⁽²⁾

1.025

–30

1.100

V

V_{(VDD_PLLD)}

DCG PLL 1.1-V power

T_A

T_J

Operating ambient temperature ⁽⁴⁾

°C

Operating junction temperature

105

(1) These supplies have multiple valid ranges.

(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop

across the filter.

(3) VDDLP12 must be tied to the VDD rail.

(4) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value

at 0 forced air flow (R_θJAat 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum

estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects R_θJA

Thus, maximum operating ambient temperature varies by application.

.

•

T_{a_min}= T_{j_min}–(P_{d_min}× R_θJA) = –30°C –(0.0 W × 28.8°C/W) = –30°C

T_{a_max}= T_{j_max}–(P_{d_max}× R_θJA) = +105°C –(0.348 W × 28.8°C/W) = +95.0°C

6.4 Thermal Information

DLPC3437

ZEZ (NFBGA)

201 PINS

10.1

THERMAL METRIC⁽¹⁾

UNIT

°C/W

R_θJC

Junction-to-case top thermal resistance

at 0 m/s of forced airflow⁽²⁾

at 1 m/s of forced airflow⁽²⁾

at 2 m/s of forced airflow⁽²⁾

28.8

Junction-to-air thermal

resistance

R_θJA

25.3

24.4

Temperature variance from junction to package top center temperature, per unit power

dissipation⁽³⁾

0.23

°C/W

ψ_JT

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC

defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34xx PCB and thus the reported

thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is

the best information available during the design phase to estimate thermal performance.

(3) Example: (0.5 W) × (0.2 °C/W) ≈0.1°C temperature rise.

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6.5 Power Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER^{(1) (2) (3)}

TEST CONDITIONS

MIN

TYP⁽⁴⁾

Frame rate = 50 Hz

input=1920x1080 to FPGA

196

330

mA

347

I_(VDD)

I_{(VDD_PLLM)}

I_{(VDD_PLLD)}

+

1.1V rails

Frame rate = 60 Hz

input=1920x1080 to FPGA

216

6

Frame rate = 50 Hz

input=1920x1080 to FPGA

I_{(VDD_PLLM)}

I_{(VDD_PLLD)}

I_(VCC18)

MCG PLL 1.1-V current

DCG PLL 1.1-V current

mA

Frame rate = 60 Hz

input=1920x1080 to FPGA

6

Frame rate = 50 Hz

input=1920x1080 to FPGA

6

Frame rate = 60 Hz

input=1920x1080 to FPGA

6

Frame rate = 50 Hz

input=1920x1080 to FPGA

31

2

45

All 1.8-V I/O current: (1.8-V power supply

for all I/O other than the host or parallel

interface and the SPI flash interface)

mA

45

Frame rate = 60 Hz

input=1920x1080 to FPGA

Frame rate = 50 Hz

input=1920x1080 to FPGA

Host or parallel interface I/O current: 1.8 V

(includes IIC0, PDATA, video syncs, and

HOST_IRQ pins)

I_{(VCC_INTF)}

mA

Frame rate = 60 Hz

input=1920x1080 to FPGA

2

Frame rate = 50 Hz

input=1920x1080 to FPGA

1

I_{(VCC_FLSH)}

Flash interface I/O current:1.8 to 3.3 V

Frame rate = 60 Hz

input=1920x1080 to FPGA

1

(1) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum

nominal voltage (that is 1.8 V).

(2) Input image is 1920 x 1080 (1080p) 24-bits using VESA reduced blanking v2 timings on the parallel interface at the frame rate shown

with the 0.33-inch 1080p (DLP3310) DMD. The controller has the CAIC and LABB algorithms turned off.

(3) The values do not take into account software updates or customer changes that may affect power performance.

(4) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.

(5) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.

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6.6 Pin Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

0.7 ×

VCC_INTF

I²C buffer (I/O type 7)

See

(1)

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

1.17

3.6

I/O type 1, 6 for pins noted in ⁽²⁾

VCC18 = 1.8 V

1.3

1.17

1.7

3.6

High-level input

threshold voltage

I/O type 5, 9, 11

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

V_IH

V

I/O type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

1.7

I/O type 5, 9, 11

2.0

I/O type 12, 13

2.0

0.3 ×

VCC_INTF

I²C buffer (I/O type 7)

–0.5

–0.3

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

0.63

I/O type 1, 6 for pins noted in ⁽²⁾

I/O type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

0.5

0.63

0.7

–0.3

1.35

1.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC18 = 1.8 V

Low-level input

threshold voltage

V_IL

V

I/O type 5, 9, 11

I/O type 12, 13

0.7

I/O type 5, 9, 11

I/O type 12, 13

0.8

I/O type 1, 2, 3, 6, 8

I/O type 5, 9, 11

I/O type 12, 13

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC_INTF > 2 V

High-level output

voltage

V_OH

I/O type 5, 9, 11

I/O type 12, 13

V

1.7

I/O type 5, 9, 11

2.4

I/O type 12, 13

2.4

I²C buffer (I/O type 7)

0.4

0.2 ×

VCC_INTF

I²C buffer (I/O type 7)

VCC_INTF < 2 V

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

VCC18 = 1.8 V

0.45

0.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

Low-level output

voltage

V_OL

V

0.7

0.4

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6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

CONDITIONS⁽⁴⁾

I/O type 2, 4

I/O type 5

VCC18 = 1.8 V

2

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

3.5

10.6

5.4

10.8

7.8

15

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

High-level output

current⁽⁵⁾

I_OH

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_INTF = 2.5V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9, 13

I/O type 13

I/O type 5

I/O type 9

I/O type 13

I²C buffer (I/O type 7)

I/O type 2, 4

I/O type 5

15

3

VCC18 = 1.8 V

2.3

4.6

13.9

5.2

10.4

4.4

8.9

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

Low-level output

current⁽⁶⁾

I_OL

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9

I/O type 13

I/O type 5

I/O type 9

I/O type 13

V_{I2C buffer}< 0.1 ×

VCC_INTF or

V_{I2C buffer}> 0.9 ×

VCC_INTF

I²C buffer (I/O type 7)

10

–10

I/O type 1, 2, 3, 6, 8,

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

10

–10

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

High-impedance

leakage current

I_OZ

µA

10

16

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6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

I²C buffer (I/O type 7)

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

5

3.5

VCC18 = 1.8 V

2.6

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

3.5

pF

Input capacitance

(including package)

C_I

3.5

I/O type 5, 9, 11

I/O type 12, 13

sub-LVDS –DMD high speed

(I/O type 4)

VCC18 = 1.8 V

3

(1) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

(2) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied V_IHand V_ILrange from other 1.8-V

I/O.

(3) The I/O type refers to the type defined in 表5-10.

(4) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O supply

reference is set to.

(5) At a high level output signal, the given I/O outputs at least the minimum current specified.

(6) At a low level output signal, the given I/O sinks at least the minimum current specified.

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6.7 Internal Pullup and Pulldown Electrical Characteristics

over operating free-air temperature (unless otherwise noted) ⁽²⁾

INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS

TEST

MIN

MAX

UNIT

CONDITIONS⁽¹⁾

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

29

38

56

30

36

52

63

90

kΩ

Weak pullup resistance

148

72

101

167

Weak pulldown resistance

(1) The resistance is dependent on VCCIO, the supply reference for the pin (see 表5-10).

(2) An external 8-kΩpullup or pulldown (if needed) works for any voltage condition to correctly pull enough to override any associated

internal pullups or pulldowns.

6.8 DMD Sub-LVDS Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.0

UNIT

V

V_CM

Common mode voltage

0.8

0.9

V_CM(Δpp)⁽¹⁾

V_CMchange peak-to-peak (during switching)

V_CMchange steady state

75

mV

V

V_CM(Δss)⁽¹⁾

–10

170

10

(2)

|V_OD

|

Differential output voltage magnitude

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Internal differential termination

250

350

10

V_OD(Δ)

V_OH

–10

0.825

0.625

80

1.025

0.775

100

1.175

0.975

120

V_OL

V

Tx_term

Ω

100-Ωdifferential PCB trace

(50-Ωtransmission lines)

Tx_load

0.5

6

inches

(1) See 图6-1

(2) V_ODis the differential voltage measured across a 100-Ωtermination resistance connected directly between the transmitter differential

pins. V_OD= V_P- V_N, where P and N are the differential output pins. |V_OD| is the magnitude of the peak-to-peak voltage swing across

the P and N output pins (see 图6-2). V_CMcancels out between signals when measured differentially, thus the reason V_ODswings

relative to zero.

+V

OD

100

90

80

|V_OD|

70

60

(0 V) 50

40

V

(û

CM SS

)

V

(û )

CM P-P

V

CM

30

|V_OD|

20

10

0

œV

OD

t_FALL

t_RISE

V_CMis removed when the signals are viewed differentially

图6-1. Common Mode Voltage

图6-2. Differential Output Signal

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6.9 DMD Low-Speed Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.7 ×

VCC18

V_OH(DC)

V_OL(DC)

V_OH(AC)

V_OL(AC)

V

DC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.3 ×

VCC18

V

AC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.8 ×

VCC18

VCC18 +

0.5

(1)

(2)

AC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.2 ×

VCC18

-0.5

1.0

V_OL(DC)to V_OH(AC)for rising edge

and V_OH(DC)to V_OL(AC)for rising

edge

DMD_LS_WDATA and DMD_LS_CLK

3.0

Slew rate

V/ns

DMD_DEN_ARSTZ

DMD_LS_RDATA

V_OL(AC)to V_OH(AC)for rising edge

0.25

0.5

(1) V_OH(AC)maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(2) V_OL(AC)minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(3) See 图6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See 图6-4 for DMD_DEN_ARSTZ rise and fall times.

DMD_DEN_ARSTZ

LS_CLK, LS_WDATA

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

OH(AC)

OH(DC)

V

OL(DC)

V

OL(AC)

10

0

10

0

t_RISE

t_FALL

t_RISE

t_FALL

图6-3. LS_CLK and LS_WDATA Slew Rate

图6-4. DMD_DEN_ARSTZ Slew Rate

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6.10 System Oscillators Timing Requirements

MIN

23.998

NOM

24.000

MAX

UNIT

MHz

f_clk

t_c

Clock frequency, MOSC (primary oscillator clock)⁽¹⁾

Cycle time, MOSC (clock period)⁽¹⁾

24.002

41.670

41.663

40%

41.667

50%

ns

See 图6-5

50% to 50% reference

points (signal)

t_w(H)

t_w(L)

Pulse duration as percent of t_c⁽²⁾, MOSC, high

Pulse duration as percent of t_c⁽²⁾, MOSC, low

50% to 50% reference

points (signal)

40%

50%

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

Transition time⁽²⁾, MOSC

10

ns

Long-term, peak-to-peak, period jitter⁽²⁾, MOSC

(that is the deviation in period from ideal period due

solely to high frequency jitter)

t_jp

2%

(1) The frequency accuracy for MOSC is ±200 PPM. This requirement includes any impact to accuracy due to aging, temperature, and

trim sensitivity. The MOSC input cannot support spread spectrum clock spreading.

(2) Applies only when driven by an external digital oscillator.

t

C

t

T

t

T

t

W(L)

W(H)

80%

20%

50%

MOSC

图6-5. System Oscillators

6.11 Power Supply and Reset Timing Requirements

MIN

MAX

UNIT

µs

t_w(L)

t_r

Pulse duration, inactive low, RESETZ

Rise time, RESETZ⁽¹⁾

50% to 50% reference points (signal)

20% to 80% reference points (signal)

80% to 20% reference points (signal)

0.3 V to 1.045 V (VDD)

1.25

0.5

1

µs

t_f

Fall time, RESETZ⁽¹⁾

µs

t_rise

Rise time, VDD (during VDD ramp up at

turn-on)

ms

(1) For more information on RESETZ, see 节5.

DC Power Supplies

t_f

t_r

80%

50%

20%

80%

50%

20%

RESETZ

t_w(L)

Time

图6-6. Power-Up and Power-Down RESETZ Timing

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6.12 Parallel Interface Frame Timing Requirements

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

50% reference points

1

lines

Pulse duration –default VSYNC_WE high

Vertical back porch (VBP) –time from the active edge of

VSYNC_WE to the active edge of HSYNC_CS for the first

active line⁽¹⁾

2

1

lines

Vertical front porch (VFP) –time from the active edge of the

HSYNC_CS following the last active line in a frame to the active

edge of VSYNC_WE⁽¹⁾

t_{p_vfp}

50% reference points

Total vertical blanking –the sum of VBP and VFP (t_{p_vbp}

t_{p_vfp}

+

t_{p_tvb}

t_{p_hsw}

t_{p_hbp}

50% reference points

See ⁽¹⁾

lines

)

4

128

PCLKs

Pulse duration –default HSYNC_CS high

Horizontal back porch (HBP) –time from the active edge of

HSYNC_CS to the rising edge of DATAEN_CMD

Horizontal front porch (HFP) –time from the falling edge of

DATAEN_CMD to the active edge of HSYNC_CS

t_{p_hfp}

50% reference points

8

PCLKs

(1) The minimum total vertical blanking is defined by the following equation: t_{p_tvb}(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines

where:

•

SOURCE_ALPF = Input source active lines per frame

DMD_ALPF = Actual DMD used lines per frame supported

1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

PDATA(23/15:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

图6-7. Parallel Interface Frame Timing

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6.13 Parallel Interface General Timing Requirements

MIN

1.0

MAX

UNIT

MHz

ns

PCLK frequency

PCLK period

155.0

1000

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

50% reference points

Max ƒ_clock

6.45

PCLK jitter

see ⁽¹⁾

PCLK pulse duration high

PCLK pulse duration low

50% reference points

2.43

ns

t_{p_wl}

Setup time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

t_{p_su}

t_{p_h}

50% reference points

0.9

ns

Hold time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

2.0

ns

Transition time –all signals

t_setup, 3DR

t_hold, 3DR

Setup time with respect to VSYNC⁽²⁾

Hold time with respect VSYNC⁽³⁾

50% reference points

1.0

ms

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock–5.76 ns]. Setup and hold times must be met even with clock jitter.

(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes

(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

图6-8. Parallel Interface General Timing

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6.14 Flash Interface Timing Requirements

The DLPC3437 controller flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The

DLPC3437 can support 1- to 128-Mb flash memories.^{(1) (2) (4)}

MIN

MAX

36.0

704

UNIT

MHz

ns

SPI_CLK frequency

See ⁽³⁾

1.4

ƒ_clock

t_{p_clkper}

t_{p_wh}

SPI_CLK period

50% reference points

27.8

352

SPI_CLK pulse duration high

SPI_CLK pulse duration low

ns

t_{p_wl}

ns

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

3.0

ns

Transition time –all signals

Setup time –SPI_DIN valid before SPI_CLK falling

edge

t_{p_su}

t_{p_h}

50% reference points

10.0

0.0

ns

Hold time –SPI_DIN valid after SPI_CLK falling edge

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

t_{p_clqv}

1.0

3.0

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

t_{p_clqx}

50% reference points

ns

–3.0

(1) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3437 does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This feature provides support

for SPI devices with long clock-to-Q timing. DLPC3437 hold capture timing has been set to facilitate reliable operation with standard

external SPI protocol devices.

(2) With the above output timing, DLPC3437 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the

rising edge of SPI_CLK.

(3) This range includes the 200 ppm of the external oscillator (but no jitter).

(4) For additional requirements of the external flash device view 节7.3.3.1.

t_CLKPER

SPI_CLK

(Controller output)

t_WL

t_WH

t_{P_SU}

t_{P_H}

SPI_DIN

(Controller input)

t_{P_CLQV}

SPI_DOUT, SPI_CS(1:0)

(Controller output)

t_{P_CLQX}

图6-9. Flash Interface Timing

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6.15 Other Timing Requirements

MIN

MAX

UNIT

ns

t_rise, all^{(1) (2)}

20% to 80% reference points

80% to 20% reference points

20% to 80% reference points

80% to 20% reference points

10

t_fall, all^{(1) (2)}

ns

t_rise, PARKZ⁽²⁾

150

ns

t_fall, PARKZ⁽²⁾

ns

t_w, GPIO_08 (normal park) pulse width⁽³⁾

I²C baud rate

200

ms

kHz

100

(1) Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.

(2) This is the recommended signal transition time to avoid input buffer oscillations.

(3) When the controller is turned off by setting PROJ_ON low, PROJ_ON must not be brought high again for at least 200 ms. See 节9.3

for additional requirements.

6.16 DMD Sub-LVDS Interface Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

45%

MIN

TYP

MAX

250

UNIT

(1)

t_R

t_F

Differential output rise time

Differential output fall time

DMD HS Clock switching rate

DMD HS Clock frequency

DMD HS Clock output duty cycle

ps

250

t_switch

f_clock

1200

600

Mbps

MHz

DCout

50%

55%

(1) Rise and fall times are defined for the differential V_ODsignal as shown in 图6-2.

6.17 DMD Parking Switching Characteristics

See ⁽²⁾

PARAMETER

Normal park time⁽¹⁾

Fast park time⁽³⁾

TEST CONDITIONS

TYP

MAX

20

UNIT

ms

t_park

t_{fast park}

40

µs

(1) Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the

normal park request (GPIO_08 goes low).

(2) The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be

held on for a time after parking is completed to satisfy DMD requirements. See 节9.2 and the appropriate DMD or PMIC datasheet for

more information.

(3) Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast

park request (PARKZ goes low).

6.18 Chipset Component Usage Specification

Reliable function and operation of the DLP chipset requires that it be used with all components (DMD, PMIC,

and controller) of the applicable DLP chipset.

表6-1. DLPC3437 Supported DMDs and PMICs

DLPC3437 DLP CHIPSET

DMD

PMIC

DLP3310

DLPA3000

DLPA3005

In addition to the required DLP chipset, the XC7Z020-1CLG484I4493 FPGA is required to be used in

conjunction with this particular DLP chipset.

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7 Detailed Description

7.1 Overview

The DLPC3437 is the display controller for the DLP3310 (0.33 1080p) DMD. The DLPC3437 is part of the

chipset comprising the DLPC3437 controller, the DLP3310 (0.33 1080p) DMD, and the DLPA300X PMIC (which

includes an LED driver). All three components of the chipset must be used in conjunction with each other, along

with the XC7Z020-1CLG484I4493 FPGA for reliable operation of the DLP3310 (0.33 1080p) DMD. See 表 6-1.

The DLPC3437 display controller provides data and image processing functions that are optimized for small form

factor and power-constrained full HD display applications. Applications include pico projectors, wearable

displays, and digital signage. Standalone projectors must include a separate front-end chip to interface to the

outside world (for example, video decoder, HDMI receiver, triple ADC, or USB I/F chip).

7.2 Functional Block Diagram

Test

Pattern

Generator

Video Processing

/5

Parallel Video

or BT656 Port

ñ

Brightness Enhancement

Chroma Interpolation

Color Space Conversion

Color Correction

ñ

Contrast Adjustment

Dynamic Scaling

Gamma Correction

/24

Input

Control

Processing

Image Format Processing

Power Saving Operations

Splash

Screen

CAIC Processing

DLP Subsystem

Display Formatting

eDRAM (Frame Memory)

Arm^®Cortex^®-M3

Processor

128 KB I/D Memory

JTAG

I2C_0

/

Real Time

Control System

SPI_0

DMD_HS_CLK

(sub-LVDS)

DMD_HS_DATA(A:H)

/

(sub-LVDS)

DMD Interface

DMD_LS_CLK

SPI_1

I2C_1

LED Control

Other options

Clocks and Reset

Generation

DMD_LS_WDATA

DMD_LS_RDATA

/20

GPIO

DMD_DEN_ARSTZ

Clock (Crystal)

Reset Control

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7.3 Feature Description

7.3.1 Input Source Requirements

7.3.1.1 Supported Resolution and Frame Rates

This section defines the timing requirements for the external interfaces for the DLPC3437 controller.

表7-1. Supported Input Source Ranges

SOURCE RESOLUTION RANGE^{(3) (5)}

FRAME RATE

RANGE

INTERFACE⁽¹⁾BITS / PIXEL ⁽⁴⁾IMAGE TYPE⁽²⁾

HORIZONTAL

VERTICAL

LANDSCAPE PORTRAIT

Parallel

24

2D - 1080p

2D - WXGA

2D - 720p

3D - 720p

1920

1366

1280

N/A

1080

768

720

N/A

50 ± 2 Hz,

60 ± 2 Hz

50 ± 2 Hz,

60 ± 2 Hz

50 ± 2 Hz,

60 ± 2 Hz

100 ± 2 Hz,

120 ± 2 Hz

(1) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line

rate.

(2) The maximum DMD pixel display resolution is 1920x1080 while system actuator is enabled.

(3) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to

determine the latest available frame rate and input resolution support for a given firmware image.

(4) Bits per pixel does not necessarily equal the number of data pins used on the DLPC34xx controller. Fewer pins are used if multiple

clocks are used per pixel transfer.

(5) The DLPC3437 only supports Landscape orientation.

7.3.1.2 3D Display

For 3D sources on the video input interface, images must be frame sequential (L, R, L, ...) when input to the

DLPC34xx controller. Any processing required to unpack 3D images and to convert them to frame sequential

input must be done by external electronics prior to inputting the images to the controller. Each 3D source frame

input must contain a single eye frame of data, separated by a VSYNC, where an eye frame contains image data

for a single left or right eye. The signal 3DR input to the controller indicates whether the input frame is for the left

eye or right eye.

Each DMD frame is displayed at the same rate as the input interface frame rate. 图 7-1 below shows the typical

timing for a 50-Hz or 60-Hz 3D HDMI source frame, the input interface of the DLPC34xx controller, and the

DMD. In general, video frames sent over the HDMI interface pack both the left and right content into the same

video frame. GPIO_04 is optionally sent to a transmitter on the system PCB for wirelessly transmitting a

synchronization signal to 3D glasses (usually an IR sync signal). The glasses are then in phase with the DMD

images displayed. Alternately, the 3D Glasses Operation section shows how DLP link pulses can be used

instead.

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50 Hz or 60 Hz

(HDMI)

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L

R

L

R

L

R

L

R

L

R

L

R

100 Hz or 120 Hz

(34xx Input)

R

3DR ⁽²⁾

(3D L/R input)

100 Hz or 120 Hz

(on DMD)

R

L

R

L

R

L

R

L

R

L

R

L

GPIO_04 ⁽¹⁾

(3D L/R output)

(1) Left = 1, Right = 0

(2) 3DR must toggle at least 1 ms before VSYNC

图7-1. 3D Display Left and Right Frame Timing

The frame and sub-frame timing for 2D sources is shown in 图 7-2 while the frame and sub-frame timing for 3D

sources is shown in 图7-3.

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T

VSYNC_PRD

IN_VSYNC

IN_3DR

(3D processing not available when actuator is enabled)

FPGA

Input

FRAME 1

( 1920 x 1080 )

IN_DATA

FRAME 2

FRAME 3

OUT_VSYNC

OUT_3DR

FRAME 1

SUBFRAME A

( 1358 x 764 )

FRAME 1

SUBFRAME B

( 1358 x 764 )

FRAME 2

SUBFRAME A

FRAME 2

SUBFRAME B

OUTPUT DATA

FPGA

Output

&

Controller

Input

FRAME 1 - DMD

LEFT

SUBFRAME A

( 679+32 x 764 )

FRAME 1 - DMD

LEFT

SUBFRAME B

( 679+32 x 764 )

FRAME 1 - DMD

LEFT

SUBFRAME A

FRAME 1 - DMD

LEFT

SUBFRAME B

P_DATA_L_(0:23)

FRAME 1 -

DMD RIGHT

SUBFRAME A

( 679+32 x 764 )

FRAME 1 -

DMD RIGHT

SUBFRAME B

( 679+32 x 764 )

FRAME 1 -

DMD RIGHT

SUBFRAME A

FRAME 1 -

DMD RIGHT

SUBFRAME B

P_DATA_R_(0:23)

SUB_FRAME_REF

FRAME 1

SUBFRAME A

( 1358 x 764 )

FRAME 1

SUBFRAME B

( 1358 x 764 )

DMD_Data

Controller

Output

ACT_SYNC

POSITION A

POSITION B

Actuator Position

图7-2. DLPC3437 2D Actuator Frame and Signal Timing

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T_{VSYNC_PRD}

IN_VSYNC

IN_3DR

FPGA

Input

FRAME 1 – LEFT EYE

( 1280 x 720 )

FRAME 2 – RIGHT EYE

FRAME 3 – LEFT EYE

( 1280 x 720 )

IN_DATA

( 1280 x 720 )

OUT_VSYNC

OUT_3DR

FPGA

Output

&

Controller

Input

FRAME 1 – LEFT EYE

( 1280 x 720 )

FRAME 2 – RIGHT EYE

( 1280 x 720 )

FRAME 3 – LEFT EYE

( 1280 x 720 )

OUT_DATA

FRAME 1 – LEFT EYE

( 1280 x 720 )

FRAME 2 – RIGHT EYE

( 1280 x 720 )

DMD_Data

ACT_SYNC

Controller

Output

图7-3. DLPC3437 3D Frame and Signal Timing

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7.3.1.3 Parallel Interface

The parallel interface complies with standard graphics interface protocol, with the addition of the SUB_FRAME

signal (which is a necessary output from the XC7Z020-1CLG484I4493 FPGA). The standard graphics interface

protocol includes a vertical sync signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid

signal (DATAEN_CMD), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the

active edge of the clock are programmable. 图6-7 shows the relationship of these signals.

备注

VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display sequencer stops

and turns off the LEDs.

7.3.1.3.1 Parallel Interface Data Transfer Format

The data format on the PDATA(23:0) bus between the 0.33 1080p FPGA and the DLPC3437 is always RGB888,

as shown in 图7-4.

23

0

Red / Cr

Green / Y

Blue / Cb

Controller input mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Controller internal re-mapping

7

5

4

3

5

4

3

4

3

2

0

Red / Cr

Green / Y

Blue / Cb

图7-4. RGB-888 I/O Mapping

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7.3.2 Device Start-Up

• The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.

• While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).

• HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is

pulled high, this indicates that the controller is performing boot-up and auto-initialization.

• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to

indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the

external signal).

• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the

falling edge of the signal, the initialization is complete.

• The DLPC34xx controller is ready to receive commands through I²C or accept video over the parallel

interface only after auto-initialization is complete.

• The controller initialization typically completes (HOST_IRQ goes low) within 3.29 s of RESETZ being

asserted. However, this time can vary depending on the software version and the contents of the user

configurable auto initialization file.

RESETZ

auto-initialization

HOST_IRQ

(with external pullup)

(INIT_BUSY)

t0

t1

t0: rising edge of RESETZ; auto-initialization begins

t1: falling edge of HOST_IRQ; auto-initialization is complete

图7-5. HOST_IRQ Timing

7.3.3 SPI Flash

7.3.3.1 SPI Flash Interface

The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the

below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing

Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash

Device Options table for example compatible flash options. The minimum required flash size depends on the

size of the utilized firmware. The firmware size depends upon a variety of factors including the number of

sequences, lookup tables, and splash images.

The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The

device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.

The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash

device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip

select zero. The boot routine uploads program code from flash memory to program memory then transfers

control to an auto-initialization routine within program memory.

The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features,

and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below 表7-2, 表7-3, and

表7-4.

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表7-2. Additional DLPC34xx SPI Flash Requirements

FEATURE

SPI interface width

DLPC34xx REQUIREMENT

Single

SPI polarity and phase settings

Fast READ addressing

Programming mode

Page size

SPI mode 0

Auto-incrementing

Page mode

256 B

Sector size

4-KB sector

Any

Block size

Block protection bits

Status register bit(0)

Status register bit(1)

Status register bits(6:2)

Status register bit(7)

0 = Disabled

Write in progress (WIP), also called flash busy

Write enable latch (WEN)

A value of 0 disables programming protection

Status register write protect (SRWP)

Because the DLPC34xx controller supports only single-byte status register R/W command execution,

it may not be compatible with flash devices that contain an expansion status byte. However, as long

as the expansion status byte is considered optional in the byte 3 position and any write protection

control in this expansion status byte defaults to unprotected, then the flash device is likely compatible

with the DLPC34xx.

Status register bits(15:8)

(that is expansion status byte)

The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled

or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as

part of the boot process.

The DLPC34xx issues these commands during the boot process:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8

bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

表 7-3 and 表 7-4 below list the specific instruction OpCode and timing compatibility requirements. The

DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.

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表7-3. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

BYTE 1

SPI FLASH COMMAND

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

(OPCODE)

Fast READ (1 output)

Read status

0x0B

0x05

0x01

0x06

0x02

0x20

0xC7

ADDRS(0)

N/A

ADDRS(1)

N/A

ADDRS(2)

STATUS(0)

dummy

DATA(0)⁽¹⁾

Write status

STATUS(0)

See ⁽²⁾

Write enable

Page program

Sector erase (4 KB)

Chip erase

ADDRS(0)

ADDRS(1)

ADDRS(2)

DATA(0)⁽¹⁾

(1) Shows the first data byte only. Data continues.

(2) Access to a second (expansion) write status byte not supported by the DLPC34xx controller.

表 7-4 below and the Flash Interface Timing Requirements section list the specific timing compatibility

requirements for a DLPC34xx compatible flash device.

表7-4. SPI Flash Key Timing Parameter Compatibility Requirements

SPI FLASH TIMING PARAMETER^{(1) (2)}

SYMBOL

ALTERNATE SYMBOL

MIN

MAX

UNIT

Access frequency (all commands)

FR

f_C

MHz

≤1.4

≥30.1

Chip select high time (also called chip select

deselect time)

t_SHSL

t_CSH

ns

≤200

≥0

Output hold time

t_CLQX

t_CLQV

t_DVCH

t_CHDX

t_HO

t_V

t_DSU

t_DH

ns

Clock low to output valid time

Data in set-up time

Data in hold time

≤11

≤5

(1) The timing values apply to the specification of the peripheral flash device, not the DLPC34xx controller. For example, the flash device

minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.

(2) The DLPC34xx does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to

a logic high on the PCB through an external pullup.

In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin

must be supplied with the corresponding voltage. The DLPC34xx Validated SPI Flash Device Options table

contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx

controller.

表7-5. DLPC34xx Validated SPI Flash Device Options^{(1) (2) (3)}

DENSITY (Mb)

VENDOR

PART NUMBER

1.8-V COMPATIBLE DEVICES

W25Q40BWUXIG

PACKAGE SIZE

4 Mb

8 Mb

Winbond

Macronix

2 × 3 mm USON

MX25U4033EBAI-12G

1.43 × 1.94 mm WLCSP

1.68 × 1.99 mm WLCSP

MX25U8033EBAI-12G

2.5- OR 3.3-V COMPATIBLE DEVICES

Winbond W25Q16CLZPIG

16 Mb

5 × 6 mm WSON

(1) The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC34xx controller. Make sure to order the device that

supports the correct supply voltage as multiple voltage options are often available.

(2) Numonyx (Micron) serial flash devices typically do not support the 4 KB sector size compatibility requirement for the DLPC34xx

controller.

(3) The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC34xx controller,

but they have not been formally validated by TI.

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7.3.3.2 SPI Flash Programming

The SPI pins of the flash can directly be driven for flash programming while the DLPC34xx controller I/Os are tri-

stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state

while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.

Alternatively, the DLPC34xx controller can program the SPI flash itself when commanded via I²C if a valid

firmware image has already been loaded and the controller is operational.

7.3.4 I²C Interface

Both of the DLPC34xx I²C interface ports support a 100-kHz baud rate. Because I²C interface transactions

operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices

in the system.

7.3.5 Content Adaptive Illumination Control (CAIC)

Content Adaptive Illumination control (CAIC) is part of the IntelliBright^®suite of advanced image processing

algorithms that adaptively enhances brightness and reduces power. In common real-world image content most

pixels in the images are well below full scale for the for the R (red), G (green), and B (blue) digital channels input

to the DLPC34xx. As a result of this, the average picture level (APL) for the overall image is also well below full

scale, and the dynamic range for the collective set of pixel values is not fully used. CAIC takes advantage of the

headroom between the source image APL and the top of the available dynamic range of the display system.

CAIC evaluates images on a frame-by-frame basis and derives three unique digital gains, one for each of the R,

G, and B color channel. During image processing, CAIC applies each gain to all pixels in the associated color

channel. The calculated gain is applied to all pixels in that channel so that the pixels as a group collectively shift

upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the

point where just a few pixels in each color channel are clipped. The Source Pixels for a Color Channel and

Pixels for a Color Channel After CAIC Processing figures below show an example of the application of CAIC for

one color channel.

Single-pixel

Headroom

255

APL Headroom

Clipped

to 255

166

110

Time

(1) APL = 110

.

(1) APL = 166

(2) Channel gain = 166/110 = 1.51

图7-6. Source Pixels for a Color Channel

图7-7. Pixels for a Color Channel After CAIC

Processing

Above, 图 7-7 shows the gain that is applied to a color processing channel inside the DLPC34xx. Additionally,

CAIC adjusts the power for the R, G, and B LED by commanding different LED currents. For each color channel

of an individual frame, CAIC intelligently determines the optimal combination of digital gain and LED power. The

user configurable CAIC settings heavily influence the amount of digital gain that is applied to a color channel and

the LED power for that color.

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0.33

0.22

0.18

(1)

CAIC Disabled

= 1 W

CAIC Enabled

P

TOTAL

P

= 0.73 W

TOTAL

(1) With CAIC enabled, if red and blue LEDs require less than nominal power for a given input image, the red and blue LED power will

reduce.

图7-8. CAIC Power Reduction Mode (for Constant Brightness)

As CAIC applies a digital gain to each color channel and adjusts the power to each LED, CAIC ensures the

resulting color balance in the final image matches the target color balance for the projector system. Thus, the

effective displayed white point of images is held constant by CAIC from frame to frame.

CAIC can be used to increase the overall image brightness while holding the total power for all LEDs constant,

or CAIC can be used to hold the overall image brightness constant while decreasing LED power. In summary,

CAIC has two primary modes of operation:

• Power reduction mode holds overall image brightness constant while reducing LED power

• Enhanced brightness mode holds overall LED power constant while enhancing image brightness

In power reduction mode, since the R, G, and B channels can be gained up by CAIC inside the DLPC34xx, the

LED power can be reduced for any color channel until the brightness of the color on the screen is unchanged.

Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as

if CAIC was not used. 图 7-8 shows an example of LED power reduction by CAIC for an image where the red

and blue LEDs can consume less power.

In enhanced brightness mode the R, G, and B channels can be gained up by CAIC with LED power generally

being held constant. This results in an enhanced brightness with no power savings.

While there are two primary modes of operation described, the DLPC34xx actually operates within the extremes

of pure power reduction mode and enhanced brightness mode. The user can configure which operating mode

the DLPC34xx will more closely follow by adjusting the CAIC gain setting as described in the software

programmer's guide.

In addition to the above functionality, CAIC also can be used as a tool with which FOFO (full-on full-off) contrast

on a projection system can be improved. While operating in power reduction mode, the DLPC34xx reduces LED

power as the intensity of the image content for each color channel decreases. This will result in the LEDs

operating at nominal settings with full-on content (a white screen) and reducing power output until the dimmest

possible content (a black screen) is reached. In this latter case, the LEDs will be operating at minimum power

output capacity and thus producing the minimum possible amount of off-state light. This optimization provided by

CAIC will thereby improve FOFO contrast ratio. The given contrast ratio will further increase as nominal LED

current (full-on state) is increased.

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7.3.6 Local Area Brightness Boost (LABB)

Local area brightness boost (LABB), part of the IntelliBright^™suite of advanced image processing algorithms,

adaptively gains up regions of an image that are dim relative to the average picture level. The controller applies

significant gain to some regions of the image, and applies little or no gain to other regions. The LABB algorithm

evaluates images frame-by-frame and calculates the local area gains to be used for each image. Since many

images have a net overall boost in gain, even if the controller applies no gain to some parts of the image, the

controller boosts the overall perceived brightness of the image.

图7-9 shows a split screen example of the impact of the LABB algorithm for an image that includes dark areas.

图7-9. LABB Enabled (Left Side) and LABB Disabled (Right Side)

The LABB algorithm operates most effectively when ambient light conditions are used to help determine the

decision about the strength of gains utilized. For this reason, it may be useful to include an ambient light sensor

in the system design that is used to measure the display screen's reflected ambient light. This sensor can assist

in dynamically controlling the LABB strength. Set the LABB gain higher for bright rooms to help overcome

washed out images. Set the LABB gain lower in dark rooms to prevent overdriven pixel intensities in images.

7.3.7 3D Glasses Operation

When using 3D glasses (with 3D video input and appropriate software support), the controller outputs sync

information to align the left eye and right eye shuttering in the glasses with the displayed DMD image frames. 3D

glasses typically use either Infrared (IR) transmission or DLP Link^™technology to achieve this synchronization.

One glasses type uses an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the

glasses. In this case DLPC34xx controller output signal GPIO_04 can be used to cause the IR transmitter to

send an IR sync signal to the glasses. 图7-10 shows the timing sequence for the GPIO_04 signal.

The second type of glasses relies on sync information that is encoded into the light being output from the

projection lens. This approach uses the DLP Link feature for 3D video. Many 3D glasses from different suppliers

have been built using this method. The advantage of using the DLP Link feature is that it takes advantage of

existing projector hardware to transmit the sync information to the glasses. This method may give an advantage

in cost, size and power savings in the projector.

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When using DLP Link technology, one light pulse per DMD frame is output from the projection lens while the

glasses have both shutters closed. To achieve this, the DLPC34xx tells the DLPAxxxx when to turn on the

illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame.

Because the shutters in the glasses are both off when the pulse is sent, the projector illumination source is also

off except when the light is sent to create the pulse. The pulses may use any color; however, due to the

transmission property of the eye-glass LCD shutter lenses and the sensitivity of the white-light sensor used on

the eye-glasses, it is highly recommended that blue is not used for pulses. Red pulses are the recommended

color to use. 图 7-10 shows 3D timing information. 图 7-11 and 表 7-6 show the timing for the light pulses when

using the DLP Link feature.

50 Hz or 60 Hz

(HDMI)

L

R

L

R

L

R

L

R

L

R

L

R

100 Hz or 120 Hz

(34xx Input)

L

R

L

R

L

R

L

R

L

R

L

R

3DR ⁽¹⁾⁽²⁾

(3D L/R input)

100 Hz or 120 Hz

(on DMD)

R

L

R

L

R

L

R

L

R

L

R

L

GPIO_04 ⁽¹⁾

(3D L/R output)

0 µs (min)

5 µs (max)

GPIO_04

LED_SEL_0, LED_SEL_1

Video

On DMD

Dark time

t1

t2

(1) Left = 1, Right = 0

(2) 3DR must toggle 1 ms before VSYNC

t1: both shutters turned off

t2: next shutter turned on

图7-10. 3D Display Left and Right Frame and Signal Timing

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video data on subframe n

video data on subframe n+1

3D glasses shutter

E

A

C

B

D

A

Video

t1

t2

The time offset of DLP Link pulses at the end of a subframe alternates between B and B+D where D is the delta offset.

图7-11. 3D DLP Link Pulse Timing

表7-6. 3D DLP Link Timing

HDMI SOURCE FRAME

RATE (Hz)⁽¹⁾

DLPC34xx INPUT

FRAME RATE (Hz)

A

B

C

D

E

(µs)

20 - 32

128 - 163

49.0

50.0

51.0

59.0

60.0

61.0

98

> 500

> 622

> 658

> 655

> 634

> 632

> 630

> 2000

(31.8 nominal)

(161.6 nominal)

20 - 32

128 - 163

100

102

118

120

122

(31.2 nominal)

(158.4 nominal)

20 - 32

128 - 163

(30.6 nominal)

(155.3 nominal)

20 - 32

128 - 163

(26.4 nominal)

(134.2 nominal)

20 - 32

128 - 163

(26.0 nominal)

(132.0 nominal)

20 - 32

128 - 163

(25.6 nominal)

(129.8 nominal)

(1) Timing parameter C is always the sum of B+D.

7.3.8 Test Point Support

The DLPC34xx test point output port, TSTPT_(7:0), provides selected system calibration and controller debug

support. These test points are inputs when reset is applied. These test points are outputs when reset is released.

The controller samples the signal state upon the release of system reset and then uses the captured value to

configure the test mode until the next time reset is applied. Because each test point includes an internal

pulldown resistor, external pullups must be used to modify the default test configuration.

The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce

switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is

recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for

a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially

adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points

are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is

released does not have any effect until the next time reset asserts and releases. 表 7-7 describes the test mode

selections for one programmable scenario defined by TSTPT_(2:0).

表7-7. Test Mode Selection Scenario Defined by TSTPT_(2:0)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT_(2:0) = 0b010

60 MHz

TSTPT OUTPUT VALUE⁽¹⁾

TSTPT_(2:0) = 0b000

TSTPT_0

TSTPT_1

TSTPT_2

HI-Z

30 MHz

0.7 to 22.5 MHz

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表7-7. Test Mode Selection Scenario Defined by TSTPT_(2:0) (continued)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT OUTPUT VALUE⁽¹⁾

TSTPT_(2:0) = 0b000

TSTPT_(2:0) = 0b010

TSTPT_3

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

HI-Z

HIGH

LOW

HIGH

7.5 MHz

(1) These are default output selections. Software can reprogram the selection at any time.

7.3.9 DMD Interface

The DLPC3437 controller DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum

clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz.

7.3.9.1 Sub-LVDS (HS) Interface

表7-8 shows how the 8 sub-LVDS lanes are configured for the DLP3310 (.33 1080p) DMD.

表7-8. DLP3310 (.33 1080p) DMD –DLPC to 8-Lane DMD Pin Mapping

DLPC3437 8 LANE DMD ROUTING OPTION #1

PRIMARY DLPC3437 PINS

SECONDARY DLPC3437 PINS

DMD PINS

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_E_P

HS_WDATA_E_N

Input DATA_p_0

Input DATA_n_0

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_F_P

HS_WDATA_F_N

Input DATA_p_1

Input DATA_n_1

HS_WDATA_B_P

HS_WDATA_B_N

HS_WDATA_G_P

HS_WDATA_G_N

Input DATA_p_2

Input DATA_n_2

HS_WDATA_A_P

HS_WDATA_A_N

HS_WDATA_H_P

HS_WDATA_H_N

Input DATA_p_3

Input DATA_n_3

HS_WDATA_H_P

HS_WDATA_H_N

HS_WDATA_A_P

HS_WDATA_A_N

Input DATA_p_4

Input DATA_n_4

HS_WDATA_G_P

HS_WDATA_G_N

HS_WDATA_B_P

HS_WDATA_B_N

Input DATA_p_5

Input DATA_n_5

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_C_P

HS_WDATA_C_N

Input DATA_p_6

Input DATA_n_6

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_D_P

HS_WDATA_D_N

Input DATA_p_7

Input DATA_n_7

DLPC3437 8 LANE DMD ROUTING OPTION #2

SECONDARY DLPC3437 PINS

PRIMARY DLPC3437 PINS

DMD PINS

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_D_P

HS_WDATA_D_N

Input DATA_p_0

Input DATA_n_0

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_C_P

HS_WDATA_C_N

Input DATA_p_1

Input DATA_n_1

HS_WDATA_G_P

HS_WDATA_G_N

HS_WDATA_B_P

HS_WDATA_B_N

Input DATA_p_2

Input DATA_n_2

HS_WDATA_H_P

HS_WDATA_H_N

HS_WDATA_A_P

HS_WDATA_A_N

Input DATA_p_3

Input DATA_n_3

HS_WDATA_A_P

HS_WDATA_A_N

HS_WDATA_H_P

HS_WDATA_H_N

Input DATA_p_4

Input DATA_n_4

HS_WDATA_B_P

HS_WDATA_B_N

HS_WDATA_G_P

HS_WDATA_G_N

Input DATA_p_5

Input DATA_n_5

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_F_P

HS_WDATA_F_N

Input DATA_p_6

Input DATA_n_6

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表7-8. DLP3310 (.33 1080p) DMD –DLPC to 8-Lane DMD Pin Mapping (continued)

DLPC3437 8 LANE DMD ROUTING OPTION #1

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_E_P

HS_WDATA_E_N

Input DATA_p_7

Input DATA_n_7

High Speed sub-LVDS DDR Interface

DLPC34xx Primary

DMD_HS_WDATA_A_N

DLPC34xx Secondary

S_DMD_HS_WDATA_A_N

S_DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

S_DMD_HS_WDATA_B_N

S_DMD_HS_WDATA_B_P

(Example DMD)

DLP3310

Sub-LVDS-DMD

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

S_DMD_HS_WDATA_C_N

S_DMD_HS_WDATA_C_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

S_DMD_HS_WDATA_D_N

S_DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

S_DMD_HS_CLK_N

S_DMD_HS_CLK_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

S_DMD_HS_WDATA_E_N

S_DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

S_DMD_HS_WDATA_F_N

S_DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

S_DMD_HS_WDATA_G_N

S_DMD_HS_WDATA_G_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

S_DMD_HS_WDATA_H_N

S_DMD_HS_WDATA_H_P

DMD_LS_CLK

DMD_LS_WDATA

S_DMD_LS_CLK

S_DMD_LS_WDATA

DMD_DEN_ARSTZ

S_DMD_DEN_ARSTZ

DMD_LS_RDATA

S_DMD_LS_RDATA

Low Speed SDR Interface (120 MHz)

图7-12. DLP3310 (.33 1080p) DMD Interface Example (Option 1 and 2)

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and

Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both

waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).

Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements.

7.4 Device Functional Modes

The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON

(GPIO_08).

• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the

DMD.

• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.

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7.5 Programming

The DLPC34xx controller contains an Arm^®Cortex^®-M3 processor with additional functional blocks to enable

video processing and control. TI provides software as a firmware image. The customer is required to flash this

firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and

regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.

The available controller functions depend on the firmware version installed. Different firmware is required for

different chipset combinations (such as when using different PMIC devices). See Documentation Support at the

end of this document or contact TI to view or download the latest published software.

Users can modify software behavior through I²C interface commands. For a list of commands, view the software

user's guide accessible through the Documentation Support page.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DLPC3437 controller is required to be coupled with DLP3310 (0.33 1080p) DMD to provide a reliable

display solution for various data and video display applications. DMDs are spatial light modulators which reflect

incoming light from an illumination source to one of two directions, with the primary direction being into a

projection or collection optic. Each application is derived primarily from the optical architecture of the system and

the format of the data coming into the chipset.

Click on these links to find more information about Applications of interest: Mobile Smart TV, DLP Signage,

Mobile projector, Commercial gaming displays, Pico projectors, and Smart home displays.

8.2 Typical Application

A common application when using a DLPC3437 controller with DLP3310 DMD and DLPA300X PMIC/LED driver

is for creating an accessory Pico projector. A functional block diagram of a typical Pico projector is shown in 图

8-1.

+ Battery

œ

V

DC

Reg

LED

L5

SYSPWR

1.8V

Reg

DC

Supplies

L4

L3

Charger

PROJ_ON

1.1V

Reg

SPI1

DLPA300x

PROJ_ON

GPIO_8

I2C_0

RESETZ

PARKZ

VDD

1.8V

2

I C

INTZ

1.1V

R

LIM

LDO#1

LDO#2

3.3V

2.5V

HOST_IRQ

CMP_OUT

DLPC3437

HDMI

Illumination

optics

SPI (4)

Flash

SPI0

RC_CHARGE

3DR

Flash,

SDRAM

V

,

OFFSET

Parallel

ACT_SYNC

,

BIAS

RESET

FPGA_RDY

1.8 V

Front-End Chip

VCC_18

VCC_INTF

VCC_FLSH

Parallel (28)

CTRL

Sub-LVDS

Keypad

I2C_1

3DR

1.8 V

I2C_0

DLP3310

FPGA

XC7Z020-

HOST_IRQ

SD Card

Reader,

Video

FPD-Link

I2C_0

ñ

OSD

1CLG484I4493

I2C_1

Autolock

Scaler

Micro-controller

VCC_18

VCC_INTF

CTRL

Decoder

RESETZ

Sub-LVDS

VCC_FLSH

Frame

Memory

DDR3LI/F

Parallel

3DR

GPIO_09

3D L/R

DLPC3437

DAC_Data

Actuator

Drive

Circuit

Flash

SPI

TI Device

RESETZ

PARKZ

DAC_CLK

Actuator

Non-TI Device

VDDLP12

VDD

Flash

SPI (4)

SPI0

图8-1. Typical Application Diagram

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8.2.1 Design Requirements

A Pico projector can be created by using the DLP chipset that includes the DLP3310 (.33 1080p) DMD,

2xDLPC3437 controller, a XC7Z020-1CLG484I4493 FPGA, and DLPA300X PMIC/LED driver. The DLPC3437

and FPGA do the digital image processing, the DLPA300X PMIC provides the needed analog functions for the

projector, and the DMD displays the projection.

In addition to the four DLP chips in the chipset, other chips can be needed. At a minimum, flash memories are

needed to store the software and firmware to control the two DLPC3437s and the FPGA.

The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These LEDs are

often contained in three separate packages, but sometimes more than one color of LED die can be in the same

package to reduce the overall size of the pico-projector.

The entire pico-projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is

high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and

draws just microamps of current on SYSPWR. When PROJ_ON is set low, the 1.8-V supply can continue to be

left at 1.8 V and used by other non-projector sections of the product. If PROJ_ON is low, the DLPA300X does

not draw current on the 1.8-V supply.

8.2.2 Detailed Design Procedure

For connecting together the DLP3310 (.33 1080p) DMD, 2xDLPC3437 controller, XC7Z020-1CLG484I4493

FPGA, and DLPA3000 PMIC/LED driver, see the reference design schematic and board layoutTIDA-00325.

When a circuit board layout is created from this schematic a very small circuit board is possible. Follow the

layout guidelines to achieve a reliable projector.

Typically an optical engine manufacturer supplies the optical engine that includes the LED packages and a

mounted DMD. These manufacturers specialize in designing optics for DLP projectors. There exists production-

ready optical modules, optical module manufacturers, and design houses.

8.2.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is shown in 图 8-2 when using the DLPA3000. For the LED currents

shown, it is assumed that the same current amplitude is applied to the red, green, and blue LEDs.

SPACE

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1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.5

1

1.5

2

2.5

3

3.5

LED CURRENT (A)

4

4.5

5

5.5

6

D001

图8-2. Typical Luminance vs Current

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9 Power Supply Recommendations

9.1 PLL Design Considerations

It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.

However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC3437 requires an array of power supply voltages, (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), since VDDLP12 is tied to the 1.1-V VDD supply, then there are

no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC3437 (true

for both power-up and power-down scenarios). Similarly, there is no minimum time between powering-up or

powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.

Although there is no risk of damaging the DLPC3437 if the above power sequencing rules are followed, the

following additional power sequencing recommendations must be considered to ensure proper system

operation.

• To ensure that DLPC3437 output signal states behave as expected, all DLPC3437 I/O supplies must remain

applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is

applied, then the output signal state associated with the inactive I/O supply goes into a high impedance state.

• Additional power sequencing rules can exist for devices that share the supplies with the DLPC3437, and thus

these devices may force additional system power sequencing requirements.

Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be

drawn. This added leakage does not affect normal DLPC3437 operation or reliability.

图 9-1 and 图 9-2 show the DLPC3437 power-up and power-down sequence for both the normal PARK and fast

PARK operations of the DLPC3437 controller.

备注

During a Normal Park, it is recommended to maintain SYSPWR within specification for at least 50 ms

after PROJ_ON goes low to allow the DMD to be parked and the power supply rails to safely power

down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended that

the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least 50

ms after PROJ_ON goes low.

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Signals

from PMIC (DLPA3000)

from other source

Pre-Initialization

Initialization

Regular operation

PWR On

PWR Off

VIN On

Chipset State

SYSPWR

PROJ_ON

VDD (1.1 V)

VCC18 (1.8 V)

VCC_INTF (1.8 V)

VCC_FLSH (1.8 V)

FPGA RESETZ

PARKZ

FPGA PWR

(a)

PLL_REFCLK

RESETZ

(b)

FPGA_RDY

(c)

(d)

HOST_IRQ (Primary)

I²C (Primary)

(e)

t1

t2

t3

t4

图9-1. DLPC3437 Power-Up Timing

t1:

t2:

(VIN) applied to the PMIC. All other voltage rails are derived from SYSPWR.

All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different

external supply.

t3:

t4:

Point where RESETZ is deasserted (goes high). Indicates the beginning of the controller auto-initialization routine.

HOST_IRQ goes low to indicate initialization is complete. I2C is now ready to accept commands.

(a):

The typical delay between the PLL reference clock becoming active and RESETZ being deasserted (going high) is less than 1

ms. PLL_REFCLK must be stable within 5 ms of all power being applied, and may be active before power is applied.

(b):

(c):

RESETZ must also be held low for at least 5 ms after the power supplies are in specification.

There is a typical delay of 1.5 s between being FPGA RESETZ being deasserted and FPGA_RDY being asserted (going high).

This duration is due to FPGA boot logic.

(d):

(e):

There is a typical controller boot time of 100 ms. PARKZ must be high before RESETZ releases to support auto-initialization.

There is a typical FPGA setup time of 2.75 ms before the system completes boot process. During this period, the DLPC3437

controller writes startup values to the FPGA registers. After FPGA setup is complete, I²C now accepts commands.

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Signals

from PMIC (DLPA3000)

from other source

Normal

Park

System State

Regular operation

Power supply shutdown

(b)

SYSPWR

(c)

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

FPGA PWR

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

HOST_IRQ (Primary)

RESETZ

(a)

I²C (Primary)

t1

t2

t3

t4

t5

图9-2. DLPC3437 Normal Power-Down

t1:

t2:

t3:

t4:

t5:

(a):

(b):

PROJ_ON goes low to begin the power down sequence.

The controller finishes parking the DMD.

RESETZ is asserted which causes HOST_IRQ to be pulled high.

All controller power supplies are turned off.

SYSPWR is removed now that all other supplies are turned off.

I²C activity must stop before PROJ_ON is deasserted (goes low).

The DMD parks within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and

VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is

deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. Follow note (c).

(c):

Do not turn off SYSPWR until at least 50 ms after PROJ_ON is deasserted (goes low). This time allows the DMD to be parked,

the controller to turn off, and the PMIC supplies to shut down.

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Signals

from PMIC (DLPA3000)

from other source

Fast

Park

(a)

System State

Regular operation

Power supplies collapse

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

FPGA PWR

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

(b)

PARKZ

PLL_REFCLK

HOST_IRQ (Primary)

RESETZ

I²C (Primary)

t1

t3

t4

t2

图9-3. DLPC3437 Fast Power-Down

t1:

A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to

initiate a fast park of the DMD.

t2:

t3:

t4:

(a):

The controller finishes the fast park procedure.

RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.

Eventually all power supplies that were derived from SYSPWR collapse.

VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within

specification for a minimum of 32 µs after PARKZ is asserted (goes low).

(b):

VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet.

Also see the DLPAxxxx datasheets for more information.

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9.3 Power-Up Initialization Sequence

An external power monitor is required to hold the DLPC34xx controller in system reset during the power-up

sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller

voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The

external power monitoring is automatically done by the DLPAxxxx PMIC.

No signals output by the DLPC34xx controller will be in their active state while RESETZ is asserted. The

following signals are tri-stated while RESETZ is asserted:

• SPI0_CLK

• SPI0_DOUT

• SPI0_CSZ0

• SPI0_CSZ1

• GPIO [19:00]

Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be

configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the

PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.

Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after

RESETZ is set high.

The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power

is applied:

• LED_SEL_0

• LED_SEL_1

• DMD_DEN_ARSTZ

After power is stable and the PLL_REFCLK_I clock input to the DLPC34xx controller is stable, then RESETZ

should be deactivated (set to a logic high). The DLPC34xx controller then performs a power-up initialization

routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of

RESETZ, all DLPC34xx I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ

signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup

resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively

drives it high. Upon completion of the auto-initialization routine, the DLPC34xx controller will drive HOST_IRQ

low to indicate the initialization done state of the controller has been reached.

To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be

deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine

must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting

PROJ_ON).

备注

No I²C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.

9.4 DMD Fast PARK Control (PARKZ)

PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages

drop below specifications. Typically, the PARKZ signal is provided by the DLPAxxxx interrupt output signal.

PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on

the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park

operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue

running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to

allow the park operation to complete.

Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host

processor (for example, when the external power source has been disconnected or the battery has dropped

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below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The

longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically

only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park

operation takes much longer than 40 µs to park the mirrors. During a Normal Park operation, the DLPAxxxx

keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.

Additionally, the DLPAxxxx may hold the supplies on for a period of time after the parking has been completed.

View the relevant DLPAxxxx datasheet for more information. The longer mirror parking time ensures the longest

DMD lifetime and reliability. 节6.17 specifies the park timings

9.5 Hot Plug I/O Usage

The DLPC34xx controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).

This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the

controller does not load the input signal nor draw excessive current that could degrade controller reliability. For

example, the I²C bus from the host to other components is not affected by powering off VCC_INTF to the

DLPC34xx controller. The allows additional devices on the I²C bus to be utilized even if the controller is not

powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back

to the host.

If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input

buffer may experience added leakage current; however, the added leakage current does not damage the

DLPC34xx controller.

However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which

prevents communication on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin

for any system that has additional target devices on this bus.

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10 Layout

10.1 Layout Guidelines

For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for

TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the

use of 1-oz (or greater) copper planes to manage the controller package heat.

10.1.1 PLL Power Layout

Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The

DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,

VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground

pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the

spectrum of noise absorption). It is recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all

four components as close to the controller as possible. It is especially important to keep the leads of the high

frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and

VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.

Select ferrite beads with these characteristics:

• DC resistance less than 0.40 Ω

• Impedance at 10 MHz equal to or greater than 180 Ω

• Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both

capacitors and then through the series ferrites to the power source. Make the power and ground traces as short

as possible, parallel to each other, and as close as possible to each other.

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signal via

via to common analog digital board power plane

via to common analog digital board ground plane

PCB pad

Controller pad

1

2

3

4

5

A

Signal

VSS

Signal

F

VSS_

PLLM

G

Signal

VSS

Signal

Local

decoupling

for the PLL

digital

GND

FB

supply

PLL_

REF

CLK_I

VDD_

PLLM

VSS_

PLLD

H

1.1-V

Power

PLL_

REF

CLK_O

Crystal

Circuit

VDD_

PLLD

J

VSS

VDD

图10-1. PLL Filter Layout

10.1.2 Reference Clock Layout

The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or

oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200

ppm (including aging, temperature, and trim component variation).

52

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图10-2 shows the required discrete components when using a crystal.

PLL_REFCLK_I

PLL_REFCLK_O

R_FB

R_S

Crystal

C_L1

C_L2

C_L= Crystal load capacitance (farads)

C_L1= 2 × (C_L–Cstray_pll_refclk_i)

C_L2= 2 × (C_L–Cstray_pll_refclk_o)

where:

•

Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.

Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.

图10-2. Required Discrete Components

10.1.2.1 Recommended Crystal Oscillator Configuration

表10-1. Crystal Port Characteristics

PARAMETER

NOM

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

1.5

pF

表10-2. Recommended Crystal Configuration

PARAMETER ^{(1) (2)}

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

24

Crystal nominal frequency

MHz

PPM

ms

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

Crystal load

120 (max)

Ω

6

pF

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

100

1

Ω

MΩ

pF

See equation in 图10-2 notes

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) Temperature range of –30°C to 85°C.

(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx

controller, and the PLL_REFCLK_O pin must be left unconnected.

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表10-3. Recommended Crystal Parts

TEMPERATURE

AND AGING

(ppm)

LOAD

CAPACITANCE

(pF)

PACKAGE

DIMENSIONS

(mm)

MAXIMUM

MANUFACTURER

SPEED

(MHz)

PART NUMBER

(1) (2)

ESR (Ω)

KDS

DSX211G-24.000M-8pF-50-50

XRCGB24M000F0L11R0

24

±50

120

8

6

2.0 × 1.6

Murata

±100

NX2016SA 24M

NDK

24

±145

120

6

2.0 × 1.6

EXS00A-CS05733

(1) The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but

have not necessarily been validated by TI.

(2) Operating temperature range: –30°C to 85°C for all crystals.

10.1.3 Unused Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused

controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For

controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown

unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be

expected to drive an external device. The DLPC34xx controller implements very few internal resistors and are

listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown

resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8

kΩ.

Never tie unused output-only pins directly to power or ground. Leave them open.

When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that

the pin can remain open. If this control is not available and the pins may become an input, then include an

appropriate pullup (or pulldown) resistor.

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10.1.4 DMD Control and Sub-LVDS Signals

表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations

SIGNAL INTERCONNECT TOPOLOGY

DMD BUS SIGNAL^{(1) (2)}

UNIT

SINGLE-BOARD SIGNAL

MULTI-BOARD SIGNAL

ROUTING LENGTH

DMD_HS_CLK_P

6.0

in

See ⁽³⁾

DMD_HS_CLK_N

(152.4)

(mm)

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

6.0

in

See ⁽³⁾

(152.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

6.5

in

DMD_LS_CLK

See ⁽³⁾

(165.1)

(mm)

6.5

in

DMD_LS_WDATA

DMD_LS_RDATA

(165.1)

(mm)

6.5

in

(165.1)

(mm)

7.0

in

DMD_DEN_ARSTZ

(177.8)

(mm)

(1) Maximum signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS

model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.

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表10-5. High Speed PCB Signal Routing Matching Requirements

SIGNAL GROUP LENGTH MATCHING^{(1) (2) (3)}

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH⁽⁴⁾

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_CLK_P

DMD_HS_CLK_N

±1.0

in

DMD⁽⁵⁾

(±25.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

±0.025

in

DMD

DMD_HS_WDATA_x_P

DMD_HS_CLK_P

DMD_HS_WDATA_x_N

DMD_HS_CLK_N

DMD_LS_CLK

N/A

(±0.635)

(mm)

±0.025

in

(±0.635)

(mm)

DMD_LS_WDATA

DMD_LS_RDATA

±0.2

in

(±5.08)

(mm)

in

DMD_DEN_ARSTZ

N/A

(mm)

(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx

controller or the DMD require no additional consideration.

(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data

lines.

(3) DMD LS signals are single ended.

(4) Mismatch variance for a signal group is always with respect to the reference signal.

(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.

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表10-6. Signal Requirements

PARAMETER

REFERENCE

REQUIREMENT

DMD_LS_WDATA

DMD_LS_CLK

Required

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Acceptable

Source series termination

Required

Not acceptable

68 Ω±10%

100 Ω±10%

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Endpoint termination

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

PCB impedance

SDR (single data rate) referenced to DMD_LS_DCLK

SDR referenced to DMD_LS_DCLK

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

SDR

Signal type

SDR referenced to DMD_LS_DLCK

sub-LVDS

10.1.5 Layer Changes

• Single-ended signals: Minimize the number of layer changes.

• Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the

signals of a given pair do not change layers.

10.1.6 Stubs

• Avoid using stubs.

10.1.7 Terminations

• DMD_HS differential signals require no external termination resistors.

• Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ωseries termination resistor

located as close as possible to the corresponding controller pins.

• Make sure the DMD_LS_RDATA signal path includes a 43-Ωseries termination resistor located as close as

possible to the corresponding DMD pin.

• The DMD_DEN_ARSTZ pin requires no series resistor.

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10.1.8 Routing Vias

• The number of vias on DMD_HS signals must be minimized and ideally not exceed two.

• Any and all vias on DMD_HS signals must be located as close to the controller as possible.

• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not

exceed two.

• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the

controller as possible.

10.1.9 Thermal Considerations

The underlying thermal limitation for the DLPC34xx controller is that the maximum operating junction

temperature (T_J) not be exceeded (this is defined in the Recommended Operating Conditions section).

Some factors that influence T_Jare as follows:

• operating ambient temperature

• airflow

• PCB design (including the component layout density and the amount of copper used)

• power dissipation of the DLPC34xx controller

• power dissipation of surrounding components

The controller package is designed to primarily extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

The recommends maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC34xx controller power dissipation and R_θJAat 0 m/s of forced airflow, where R_θJAis

the thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz

power planes. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB, so the

reported thermal resistance may not be accurate in the actual product application. Although the actual thermal

resistance may be different, it is the best information available during the design phase to estimate thermal

performance. TI highly recommended that thermal performance be measured and validated after the PCB is

designed and the application is built.

To evaluate the thermal performance, measure the top center case temperature under the worse case product

scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the

controller does not exceed the maximum recommended case temperature (T_C). This specification is based on

the measured φ_JTfor the DLPC34xx controller package and provides a relatively accurate correlation to junction

temperature.

Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI

recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that

they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally

conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead

through the wires.

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10.2 Layout Example

图10-3. Board Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

11.1.2.1 Device Markings

1

DLPC343x

SC

2

DLPC343xRXXX

3

4

XXXXXXXXXX-TT

LLLLLL.ZZZ

AA YYWW

5

Pin (terminal) A1 corner identifier

Marking Definitions:

Line 1:

DLP® Device Name: DLPC343x wherex is a "7" for this device.

SC: Solder ball composition

e1: Indicates lead-free solder balls consisting of SnAgCu

G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content

less than or equal to 1.5% and that the mold compound meets TI's definition of green.

Line 2:

TI Part Number

DLP® Device Name: DLPC343x = x is a "7" for this device.

R corresponds to the TI device revision letter for example A, B or C

XXX corresponds to the device package designator.

Line 3:

Line 4:

XXXXXXXXXX-TT Manufacturer Part Number

LLLLLL.ZZZ Foundry lot code for semiconductor wafers

LLLLLL: Fab lot number

ZZZ: Lot split number

Line 5:

AA YYWW ES : Package assembly information

AA corresponds to the manufacturing site

YYWW: Date code (YY = Year :: WW = Week)

备注

1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For

example, 2512737-0001X.

2. See , for DLPC3437 resolutions on the DMD supported per part number.

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11.1.2.2 Video Timing Parameter Definitions

See 图11-1 for a visual description.

Active Lines Per Frame Defines the number of lines in a frame containing displayable data. ALPF is a

(ALPF) subset of the TLPF.

Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data. APPL is a

(APPL) subset of the TPPL.

Horizontal Back Porch Defines the number of blank pixel clocks after the active edge of horizontal sync but

(HBP) Blanking before the first active pixel.

Horizontal Front Porch Defines the number of blank pixel clocks after the last active pixel but before

(HFP) Blanking horizontal sync.

Horizontal Sync (HS or Timing reference point that defines the start of each horizontal interval (line). The

Hsync)

active edge of the HS signal defines the absolute reference point. The active edge

(either rising or falling edge as defined by the source) is the reference from which all

horizontal blanking parameters are measured.

Total Lines Per Frame Total number of active and inactive lines per frame; defines the vertical period (or

(TLPF) frame time).

Total Pixel Per Line Total number of active and inactive pixel clocks per line; defines the horizontal line

(TPPL) period in pixel clocks.

Vertical Sync (VS or Timing reference point that defines the start of the vertical interval (frame). The

Vsync)

absolute reference point is defined by the active edge of the VS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all vertical blanking parameters are measured.

Vertical

Back

Porch Defines the number of blank lines after the active edge of vertical sync but before

(VBP) Blanking

the first active line.

Vertical Front Porch Defines the number of blank lines after the last active line but before the active edge

(VFP) Blanking

of vertical sync.

TPPL

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

ALPF

(HBP)

(HFP)

Vertical Front Porch (VFP)

图11-1. Parameter Definitions

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

IntelliBright^™and Link^™are trademarks of Texas Instruments.

Pico^™and TI E2E^™are trademarks of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

IntelliBright^®is a registered trademark of Texas Instruments.

Arm^®and Cortex^®are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

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TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OUTLINE

ZEZ0201A

NFBGA - 1 mm max height

SCALE 1.000

PLASTIC BALL GRID ARRAY

13.1

12.9

A

B

BALL A1 CORNER

13.1

12.9

1 MAX

C

SEATING PLANE

0.1 C

0.31

0.21

BALL TYP

TYP

11.2 TYP

SYMM

(0.9) TYP

R

P

N

M

L

K

J

(0.9) TYP

SYMM

11.2

TYP

H

G

F

0.4

201X

E

D

C

0.3

0.15

0.08

C A

C

B

A

1

2

5 6

3 7 9 10 11 12 13 14 15

4

8

0.8 TYP

BALL A1 CORNER

4221521/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

201X ( 0.4)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221521/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

3

4

5

6

8

9

13 14 15

7

10 11 12

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221521/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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型号：	DLPC3437CZEZ
厂家：	TEXAS INSTRUMENTS
描述：	DLP® display controller for DLP3310 (0.33 1080p) DMD \| ZEZ \| 201 \| -30 to 85
文件：	总69页 (文件大小：2579K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC3437CZEZ [TI]

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