DLPC3478CZEZ_技术文档

DLPC3478

ZHCSHY3C –APRIL 2018 –REVISED DECEMBER 2020

DLPC3478 显示和光控制器

1 特性

2 应用

• 适用于DLP3010LC (0.3 720p) DMD 的显示和光控

制器

• 光控制特性：

– 针对机器视觉和数码曝光进行了优化的图形显示

• 移动投影仪

• 智能显示

• 智能手机

• 增强现实眼镜

• 智能家居显示

• Pico 投影仪

• 3D 机器视觉

– 灵活的内部(1D) 和外部(2D) 图形流模式

• 可编程曝光时间

• 高达2500Hz（1 位）和360 Hz（8 位）的

高速图形速率

3 说明

– 可编程2D 静态图形

DLPC3478 显示和光控制器为 DLP3010LC 数字微镜

器件 (DMD) 的可靠运行提供支持，适用于视频显示和

光控制应用。DLPC3478 控制器提供了连接用户电子

产品和 DMD 的便捷接口，以高速、精确且高效地显示

视频和控制光图形。

– 内部图形流模式支持简化的系统设计

• 不再需要视频接口

• 通过闪存存储超过1000 个图形

– 用于实现摄像头或传感器同步的灵活触发器信号

• 一个可配置输入触发器

访问 TI DLP ^®Pico ^™显示技术入门页面，并查看编程

人员指南了解详情。

• 两个可配置输入触发器

• 显示特性

– 最高支持720p 的输入图像大小

– 输入帧速率高达120Hz

– 24 位，输入像素接口支持：

该芯片组提供现成的资源，可帮助用户加快设计周期。

这些资源包括量产就绪型光学模块、光学模块制造商和

设计公司。

• 并行或BT656，接口协议

• 像素时钟高达155 MHz

– 图像处理- IntelliBright^™算法、图像大小调整、

1D 梯形校正、可编程去伽马校正

• 系统特性:

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

DLPC3478

封装

NFBGA (201)

13.00mm x 13.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 器件配置的I²C 控制

– 可编程Splash 屏幕

– 可编程LED 电流控制

– 断电时自动实现DMD 停放

SYSPWR

V

LED

1.8 V external

1.8 V

PROJ_ON

GPIO_8

SPI1

RESETZ

PARKZ

DLPA200x

2

I C

R

LIM

HOST_IRQ

TRIG_IN

3DR

VDDLP12

VDD

Illumination

optics

Parallel

(28)

DLPC347x

V

,

OFFSET

TSTPT

TRIG_OUT_1

SPI (4)

1.8 V

SPI0

V

,

BIAS

RESET

GPIO

TRIG_OUT_2

PAT_READY

V

VCC_18

DMD

VCC_INTF

VCC_FLSH

CTRL

Sub-LVDS

1.8 V

典型的独立系统

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS111

DLPC3478

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ZHCSHY3C –APRIL 2018 –REVISED DECEMBER 2020

Table of Contents

7 Detailed Description......................................................27

7.1 Overview...................................................................27

7.2 Functional Block Diagram.........................................27

7.3 Feature Description...................................................28

7.4 Device Functional Modes..........................................50

7.5 Programming............................................................ 50

8 Application and Implementation..................................51

8.1 Application Information............................................. 51

8.2 Typical Application.................................................... 51

9 Power Supply Recommendations................................55

9.1 PLL Design Considerations...................................... 55

9.2 System Power-Up and Power-Down Sequence....... 55

9.3 Power-Up Initialization Sequence.............................59

9.4 DMD Fast Park Control (PARKZ)..............................59

9.5 Hot Plug I/O Usage...................................................60

10 Layout...........................................................................61

10.1 Layout Guidelines................................................... 61

10.2 Layout Example...................................................... 69

11 Device and Documentation Support..........................70

11.1 Device Support........................................................70

11.2 Documentation Support.......................................... 72

11.3 接收文档更新通知................................................... 72

11.4 支持资源..................................................................72

11.5 Trademarks............................................................. 72

11.6 静电放电警告...........................................................72

11.7 术语表..................................................................... 72

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications................................................................ 13

6.1 Absolute Maximum Ratings...................................... 13

6.2 ESD Ratings............................................................. 13

6.3 Recommended Operating Conditions.......................14

6.4 Thermal Information..................................................14

6.5 Power Electrical Characteristics............................... 15

6.6 Pin Electrical Characteristics.................................... 16

6.7 Internal Pullup and Pulldown Electrical

Characteristics.............................................................18

6.8 DMD Sub-LVDS Interface Electrical

Characteristics.............................................................19

6.9 DMD Low-Speed Interface Electrical

Characteristics.............................................................20

6.10 System Oscillator Timing Requirements.................21

6.11 Power Supply and Reset Timing Requirements......21

6.12 Parallel Interface Frame Timing Requirements.......22

6.13 Parallel Interface General Timing Requirements.... 23

6.14 BT656 Interface General Timing Requirements......24

6.15 Flash Interface Timing Requirements..................... 25

6.16 Other Timing Requirements....................................25

6.17 DMD Sub-LVDS Interface Switching

Characteristics.............................................................26

6.18 DMD Parking Switching Characteristics................. 26

6.19 Chipset Component Usage Specification............... 26

Information.................................................................... 72

4 Revision History

Changes from Revision B (June 2019) to Revision C (December 2020)

Page

• 将像素时钟更改为155MHz.................................................................................................................................1

• 更新了支持的DMD.............................................................................................................................................1

• Reorganized Pin Function description................................................................................................................4

• Updated Absolute Maximum Rating ................................................................................................................ 13

• Updated Recommended Operating Conditions................................................................................................14

• Updated Power Electrical Characteristics ........................................................................................................15

• Updated Pin Electrical Characteristics..............................................................................................................16

• Updated DMD Sub-LVDS Interface Electrical Characteristics .........................................................................19

• Updated DMD Low-Speed Interface Electrical Characteristics........................................................................ 20

• Updated System Oscillator Timing Requirements............................................................................................ 21

• Updated Power Supply and Reset Timing Requirements ................................................................................21

• Added BT.656 Interface Mode Bit Mapping ..................................................................................................... 24

• Added Flash Interface Timing diagram.............................................................................................................25

• Updated maximum SPI flash size to 128Mb.....................................................................................................25

• Added DMD Sub-LVDS Interface Switching Characteristics............................................................................ 26

• Added DMD Parking Switching Characteristics................................................................................................26

• Added Chipset Component Usage Specification .............................................................................................26

• Updated external pattern streaming system block diagram..............................................................................51

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• Updated internal pattern streaming system block diagram...............................................................................51

Changes from Revision A (July 2018) to Revision B (June 2019)

Page

• 版本C 更改替代了版本B 更改........................................................................................................................... 1

Changes from Revision * (April 2018) to Revision A (July 2018)

Page

• 首次公开发布完整数据表.................................................................................................................................... 1

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ZHCSHY3C –APRIL 2018 –REVISED DECEMBER 2020

5 Pin Configuration and Functions

图5-1. ZEZ Package 201-Pin NFBGA Bottom View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

P

CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PWM

SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0

A

B

C

D

E

F

LK

DATA

DATAH_P DATAG_P

DATAF_P

DATAE_P

DATAD_P

DATAC_P

DATAB_P

DATAA_P

DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W

N

ARSTZ

DATA

DATAH_N DATAG_N

DATAF_N

DATAE_N

DATAD_N

DATAC_N

DATAB_N

DATAA_N

HWTEST_E

N

DD3P

DD3N

VDDLP12

VDD

VSS

VCC

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

VSS

VCC

RESETZ SPI0_CSZ1

PARKZ

VDD

VSS

VDD

VSS

VDD

VSS

VCC

VDD

GPIO_00

GPIO_02

GPIO_04

GPIO_06

GPIO_08

GPIO_10

GPIO_12

GPIO_14

GPIO_16

GPIO_01

GPIO_03

GPIO_05

GPIO_07

GPIO_09

GPIO_11

GPIO_13

GPIO_15

GPIO_17

GPIO_19

TSTPT_7

TSTPT_5

TSTPT_3

DD2P

DCLKP

DD1P

DD2N

DCLKN

DD1N

VDD

VSS

VDD

VSS

VCC_FLSH

VDD

VCC

VSS

VDD

VSS

VDD

VSS

VDD

RREF

VSS

DD0P

DD0N

VSS_PLLM

G

H

J

PLL_REFCL

K_I

VDD_PLLM VSS_PLLD

PLL_REFCL

K_O

VDD_PLLD

PDATA_0

PDATA_2

PDATA_4

PDATA_6

VSS

VDD

PDATA_1

PDATA_3

PDATA_5

PDATA_7

VSYNC_WE

PDATA_8

K

L

VSS

VCC_INTF

PCLK

VSS

VDD

3DR

VCC_INTF

VSS

VDD

VCC

JTAGTMS1 GPIO_18

M

N

P

R

PDM_CVS_

TE

HSYNC_CS

VCC_INTF HOST_IRQ IIC0_SDA

IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1

TSTPT_6

TSTPT_4

TSTPT_2

DATEN_CM

D

PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK

JTAGTDI

TSTPT_1

PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22

IIC1_SDA

IIC1_SCL

TSTPT_0

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表5-1. Test Pins and General Control

I/O

TYPE⁽⁴⁾

DESCRIPTION

NAME

NO.

Manufacturing test enable signal. Connect this signal directly to ground on the

PCB for normal operation.

HWTEST_EN

C10

I

6

DMD fast park control (active low Input with a hysteresis buffer). This signal is

used to quickly park the DMD when loss of power is imminent. The longest

lifetime of the DMD may not be achieved with the fast park operation;

therefore, this signal is intended to only be asserted when a normal park

operation is unable to be completed. The PARKZ signal is typically provided

from the DLPAxxxx interrupt output signal.

PARKZ

C13

I

6

JTAGTCK

JTAGTDI

P12

P13

I

6

1

6

TI internal use. Leave this pin unconnected.

JTAGTDO1

JTAGTDO2

JTAGTMS1

JTAGTMS2

N13⁽¹⁾

N12⁽¹⁾

M13

O

I

N11

I

TI internal use.

This pin must be tied to ground, through an external resistor for normal

operation. Failure to tie this pin low during normal operation can cause start

up and initialization problems.⁽²⁾

JTAGTRSTZ

P11

C11

I

6

Power-on reset (active low input with a hysteresis buffer). Self-configuration

starts when a low-to-high transition is detected on RESETZ. All controller

power and clocks must be stable before this reset is de-asserted. No signals

are in their active state while RESETZ is asserted. This pin is typically

connected to the RESETZ pin of the DLPA200x or RESET_Z of the

DLPA300X.

RESETZ

6

TSTPT_0

TSTPT_1

TSTPT_2

R12

R13

R14

I/O

1

Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ

is asserted low. Sampled as an input test mode selection control

approximately 1.5 µs after de-assertion of RESETZ, and then driven as

outputs.^{(2) (3)}

Normal use: reserved for test output. Leave open for normal use.

Note: An external pullup may put the DLPC34xx in a test mode. See 节7.3.9

for more information.

TSTPT_3

R15

I/O

1

Test pin 4 (Includes weak internal pulldown) –tri-stated while RESETZ is

asserted low. Sampled as an input test mode selection control approximately

1.5 μs after de-assertion of RESETZ and then driven as an output. Reserved

for TRIG_OUT_1 signal (Output).

TSTPT_4

P14

I/O

1

TSTPT_5

TSTPT_6

P15

N14

I/O

1

Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ

is asserted low. Sampled as an input test mode selection control

approximately 1.5 µs after de-assertion of RESETZ, and then driven as

outputs.^{(2) (3)}

Normal use: reserved for test output. Leave open for normal use.

Note: An external pullup may put the DLPC34xx in a test mode. See 节7.3.9

for more information.

TSTPT_7

N15

I/O

1

(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal

pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an

external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is

recommended to ensure a logic low.

(2) External resistor must have a value of 8 kΩor less to compensate for pins that provide internal pullup or pulldown resistors.

(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal

pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but

there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to

ensure a logic low.

(4) See 表5-10 for type definitions.

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表5-2. Parallel Port Input

PIN^{(1) (2)}

NAME

DESCRIPTION

PARALLEL RGB MODE BT656 INTERFACE MODE

Pixel clock Pixel clock

I/O

Type⁽⁴⁾

NO.

PCLK

P3

I

11

5

Parallel data mask. Programable

polarity with default of active high.

Optional signal.

PDM_CVS_TE

N4

I/O

Unused

VSYNC_WE

HSYNC_CS

DATAEN_CMD

P1

N5

P2

I

11

Vsync⁽³⁾

Unused

Hsync⁽³⁾

Data valid

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

K2

K1

L2

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

BT656_Data (0)

BT656_Data (1)

BT656_Data (2)

BT656_Data (3)

BT656_Data (4)

BT656_Data (5)

BT656_Data (6)

BT656_Data (7)

L1

I

11

M2

M1

N2

N1

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

R1

R2

R3

P4

R4

P5

R5

P6

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

Unused

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

R6

P7

R7

P8

R8

P9

R9

P10

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

Unused

Light Control

•

External input trigger signal for Internal Pattern mode (input)

3D reference

•

For 3D applications: left or right 3D reference (left = 1, right = 0). To be

provided by the host. Must transition in the middle of each frame (no

closer than 1 ms to the active edge of VSYNC)

3DR

N6

I

11

If a 3D application is not used, pull this input low through an external

resistor.

(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.

(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩor less).

(3) VSYNC and HSYNC polarity can be adjusted by software.

(4) See 表5-10 for type definitions.

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表5-3. DSI Input Data and Clock

I/O

Type⁽¹⁾

DESCRIPTION

NAME

NO.

DCLKN

DCLKP

E2

E1

---

unused; Leave unconnected and floating.

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

G2

G1

F2

F1

D2

D1

C2

C1

---

unused; Leave unconnected and floating.

Leave this pin unconnected and floating.

RREF

F3

—

(1) See 表5-10 for type definitions.

表5-4. DMD Reset and Bias Control

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DMD driver enable (active high). DMD reset (active low). When

corresponding I/O power is supplied, the controller drives this signal low

after the DMD is parked and before power is removed from the DMD. If the

1.8-V power to the DLPC34xx is independent of the 1.8-V power to the

DMD, then TI recommends including a weak, external pulldown resistor to

hold the signal low in case DLPC34xx power is inactive while DMD power

is applied.

DMD_DEN_ARSTZ

B1

O

2

DMD_LS_CLK

A1

A2

B2

O

I

3

6

DMD, low speed (LS) interface clock

DMD, low speed (LS) serial write data

DMD, low speed (LS) serial read data

DMD_LS_WDATA

DMD_LS_RDATA

(1) See 表5-10 for type definitions.

表5-5. DMD Sub-LVDS Interface

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

DMD_HS_CLK_P

DMD_HS_CLK_N

A7

B7

O

4

DMD high speed (HS) interface clock

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A3

B3

A4

B4

A5

B5

A6

B6

A8

B8

A9

B9

A10

B10

A11

B11

DMD sub-LVDS high speed (HS) interface write data lanes. The true

numbering and application of the DMD_HS_WDATA pins depend on the

software configuration. See 表7-10.

O

4

(1) See 表5-10 for type definitions.

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表5-6. Peripheral Interface⁽¹⁾

PIN⁽¹⁾

I/O

TYPE⁽³⁾

DESCRIPTION

NAME

NO.

Successive approximation ADC (analog-to-digital converter) comparator output

(DLPC34xx Input). To implement, use a successive approximation ADC with a

thermistor feeding one input of the external comparator and the DLPC34xx

controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator.

It is recommended to use the DLPAxxxx to achieve this function. CMP_OUT

must be pulled-down to ground if this function is not used. (hysteresis buffer)

CMP_OUT

A12

I

6

CMP_PWM

A15

N8

O

1

9

TI internal use. Leave this pin unconnected.

Host interrupt (output)

HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and

most importantly when it completes.

HOST_IRQ⁽²⁾

This pin is tri-stated during reset. An external pullup must be included on this

signal.

I²C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The slave I²C I/Os are 3.6-V tolerant

(high-voltage-input tolerant) and are powered by VCC_INTF (which can be 1.8,

2.5, or 3.3 V). External I²C pullups must be connected to a host supply with an

equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply

voltage does not typically satisfy the V_IHspecification of the slave I²C input

buffers).

IIC0_SCL⁽⁴⁾

IIC1_SCL

N10

R11

N9

I/O

7

8

7

8

TI internal use. TI recommends an external pullup resistor.

I²C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis):

This pin requires an external pullup resistor. The slave I²C port is the control port

of controller. The slave I²C I/O pins are 3.6-V tolerant (high-volt-input tolerant)

and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C

pullups must be connected to a host supply with an equal or higher supply

voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not

typically satisfy the V_IHspecification of the slave I²C input buffers).

IIC0_SDA⁽⁴⁾

IIC1_SDA

R10

TI internal use. TI recommends an external pullup resistor.

LED enable select. Automatically controlled by the DLPC34xx programmable

DMD sequence

LED_SEL(1:0)

Enabled LED

None

Red

Green

Blue

LED_SEL_0

LED_SEL_1

B15

B14

O

1

00

01

10

11

The controller drives these signals low when RESETZ is asserted and the

corresponding I/O power is supplied. The controller continues to drive these

signals low throughout the auto-initialization process. A weak, external pulldown

resistor is recommended to ensure that the LEDs are disabled when I/O power is

not applied.

SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to

the flash memory clock.

SPI0_CLK

A13

A14

O

13

SPI port 0, chip select 0 (active low output). This pin is typically connected to the

flash memory chip select.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ0

SPI port 0, chip select 1 (active low output). This pin typically remains unused.

TI recommends an external pullup resistor to avoid floating inputs to the external

SPI device during controller reset assertion.

SPI0_CSZ1

C12

O

13

Synchronous serial port 0, receive data in. This pin is typically connected to the

flash memory data out.

SPI0_DIN

B12

B13

I

12

13

Synchronous serial port 0, transmit data out. This pin is typically connected to

the flash memory data in.

SPI0_DOUT

O

(1) External pullup resistor must be 8 kΩor less.

(2) For more information about usage, see 节7.3.3.

(3) See 表5-10 for type definitions.

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(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication

on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional slave devices

on this bus.

表5-7. GPIO Peripheral Interface⁽¹⁾

PIN⁽¹⁾

I/O TYPE⁽³⁾

DESCRIPTION⁽²⁾

NAME

NO.

General purpose I/O 19 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_19

M15

I/O

1

General purpose I/O 18 (hysteresis buffer). Options:

1. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

GPIO_18

M14

I/O

1

2. MTR_SENSE, Motor Sense (Input): For focus motor control applications, this GPIO must be

configured as an input to the DLPC34xx and supplied from the focus motor position sensor.

General purpose I/O 17 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_17

GPIO_16

GPIO_15

GPIO_14

GPIO_13

GPIO_12

L15

L14

K15

K14

J15

J14

I/O

1

General purpose I/O 16 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 15 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 14 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 11 (hysteresis buffer). Options:

1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and

enabled.

GPIO_11

GPIO_10

H15

H14

I/O

1

2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

General Purpose I/O 10 (hysteresis buffer). Options:

1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.

2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

GPIO_09

GPIO_08

G15

G14

I/O

1

General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven

by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the

DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high

time is 200 ms. The minimum low time is 200 ms.

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表5-7. GPIO Peripheral Interface⁽¹⁾(continued)

PIN⁽¹⁾

NAME

I/O TYPE⁽³⁾

DESCRIPTION⁽²⁾

NO.

General purpose I/O 07 (hysteresis buffer). Options:

1. Light Control: Reserved for TRIG_OUT_2 signal (Output).

GPIO_07

F15

I/O

1

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 06 (hysteresis buffer). Option:

1. Light Control: Reserved for pattern ready signal (Output). Applicable in Internal Pattern

Streaming Mode only.

GPIO_06

GPIO_05

F14

E15

I/O

1

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not

used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be

configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external

pullup or pulldown to avoid a floating GPIO input.

General purpose I/O 04 (hysteresis buffer). Options:

1. 3D glasses control (output): Controls the shutters on 3D glasses (Left = 1, Right = 0).

2. SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup

resistor to deactivate this signal during reset and auto-initialization processes.

3. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

GPIO_04

GPIO_03

E14

D15

I/O

1

General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.

This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to

deactivate this signal during reset and auto-initialization processes.

General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is

typicallyconnected to the DLPAxxxx SPI_DIN pin.

GPIO_02

GPIO_01

GPIO_00

D14

C15

C14

I/O

1

General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically

connected to the DLPAxxxx SPI_CLK pin.

General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is

typically connected to the DLPAxxxx SPI_DOUT pin.

(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or

more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as

open-drain.

(2) General purpose I/O for the DLPC3478 controller. These GPIO pins are software configurable.

(3) See 表5-10 for type definitions.

表5-8. Clock and PLL Support

I/O

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Reference clock crystal input. If an external oscillator is used instead of a crystal, use

this pin as the oscillator input.

PLL_REFCLK_I

H1

I

11

5

Reference clock crystal return. If an external oscillator is used instead of a crystal,

leave this pin unconnected (floating with no added capacitive load).

PLL_REFCLK_O

J1

O

(1) See 表5-10 for type definitions.

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表5-9. Power and Ground

I/O

TYPE

DESCRIPTION

NAME

NO.

C5, D5, D7,

D12, J4,

J12, K3, L4,

L12, M6,

M9, D9,

D13, F13,

H13, L13,

M10, D3, E3

VDD

PWR

---

Core 1.1-V power (main 1.1 V)

—

VDDLP12

C3

Unused. It is recommended to externally tie this pin to VDD.

C4, D6, D8,

D10, E4,

E13, F4, G4,

G12, H4,

H12, J3,

J13, K4,

K12, L3, M4,

M5, M8,

M12, G13,

C6, C8, F6,

F7, F8, F9,

F10, G6,

VSS

GND

Core ground (eDRAM, DSI, I/O ground, thermal ground)

—

G7, G8, G9,

G10, H6,

H7, H8, H9,

H10, J6, J7,

J8, J9, J10,

K6, K7, K8,

K9, K10

All 1.8-V I/O power:

C7, C9, D4,

E12, F12,

K13, M11

(1.8-V power supply for all I/O pins except the host or parallel interface

and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL,

CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins)

VCC18

PWR

—

M3, M7, N3,

N7

Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA,

video syncs, and HOST_IRQ pins)

VCC_INTF

VCC_FLSH

PWR

—

Flash interface I/O power: 1.8 V to 3.3 V

(Dedicated SPI0 power pin)

D11

VDD_PLLM

VSS_PLLM

VDD_PLLD

VSS_PLLD

H2

G3

J2

PWR

RTN

PWR

RTN

MCG PLL (master clock generator phase lock loop) 1.1-V power

MCG PLL return

—

DCG PLL (DMD clock generator phase lock loop) 1.1-V power

DCG PLL return

H3

表5-10. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

1

2

1.8-V LVCMOS I/O buffer with 8-mA drive

1.8-V LVCMOS I/O buffer with 4-mA drive

1.8-V LVCMOS I/O buffer with 24-mA drive

1.8-V sub-LVDS output with 4-mA drive

1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive

1.8-V LVCMOS input

V_cc18

ESD diode to GND and supply rail

3

V_cc18

4

V_cc18

5

V_{cc_INTF}

V_cc18

V_{cc_INTF}

V_cc18

6

7

1.8-V, 2.5-V, 3.3-V I²C with 3-mA drive

1.8-V I²C with 3-mA drive

8

9

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

Reserved

V_{cc_INTF}

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表5-10. I/O Type Subscript Definition (continued)

I/O

SUPPLY REFERENCE

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

11

12

13

1.8-V, 2.5-V, 3.3-V LVCMOS input

V_{cc_INTF}

V_{cc_FLSH}

ESD diode to GND and supply rail

1.8-V, 2.5-V, 3.3-V LVCMOS input

1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGE ⁽²⁾

V_(VDD)

1.21

1.32

1.96

3.60

1.21

See ⁽³⁾

V

–0.3

V_(VDDLP12)

V_(VCC18)

DMD Sub-LVDS Interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)

V_{(VCC_INTF)}

V_{(VCC_FLSH)}

V_{(VDD_PLLM)}(MCG PLL)

V_{(VDD_PLLD)}(DCG PLL)

V_{I2C buffer}(I/O type 7)

GENERAL

T_J

Operating junction temperature

Storage temperature

125

°C

–30

–40

T_stg

(1) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS (GND).

(3) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.045

NOM

1.10

MAX

UNIT

V

V_(VDD)

Core power 1.1 V (main 1.1 V)

Unused

1.155

V_(VDDLP12)

V

All 1.8-V I/O power:

(1.8-V power supply for all I/O pins except the host or

parallel interface and the SPI flash interface. This includes

RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO, IIC1,

TSTPT, and JTAG pins.)

V_(VCC18)

1.64

1.80

1.96

V

1.64

2.28

1.80

2.50

1.96

2.72

3.58

1.96

2.72

3.58

1.155

85

Host or parallel interface I/O power: 1.8 to 3.3 V (includes

IIC0, PDATA, video syncs, and HOST_IRQ pins)

V_{(VCC_INTF)}

See ⁽¹⁾

V

3.02

3.30

1.64

1.80

V_{(VCC_FLSH)}

Flash interface I/O power: 1.8 V to 3.3 V

2.28

2.50

3.02

3.30

V_{(VDD_PLLM)}

MCG PLL 1.1-V power

See ⁽²⁾

1.025

–30

1.100

V

V_{(VDD_PLLD)}

DCG PLL 1.1-V power

T_A

T_J

Operating ambient temperature⁽³⁾

°C

Operating junction temperature

105

(1) These supplies have multiple valid ranges.

(2) The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop

across the filter.

(3) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value

at 0 forced air flow (R_θJAat 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum

estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects R_θJA

Thus, maximum operating ambient temperature varies by application.

.

•

T_{a_min}= T_{j_min}–(P_{d_min}× R_θJA) = –30°C –(0.0 W × 28.8°C/W) = –30°C

T_{a_max}= T_{j_max}–(P_{d_max}× R_θJA) = +105°C –(0.348 W × 28.8°C/W) = +95.0°C

6.4 Thermal Information

DLPC3478 controller

THERMAL METRIC⁽¹⁾

ZEZ (NFBGA)

201 PINS

10.1

UNIT

°C/W

R_θJC

Junction-to-case thermal resistance

at 0 m/s of forced airflow⁽²⁾

28.8

Junction-to-air thermal

R_θJA

at 1 m/s of forced airflow⁽²⁾

at 2 m/s of forced airflow⁽²⁾

25.3

resistance

24.4

Temperature variance from junction to package top center temperature, per

unit power dissipation⁽³⁾

0.23

°C/W

ψ_JT

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC

defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB and thus the

reported thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be

different , it is the best information available during the design phase to estimate thermal performance.

(3) Example: (0.5 W) × (0.2 °C/W) ≈0.1°C temperature rise.

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6.5 Power Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER^{(3) (4) (5)}

TEST CONDITIONS

MIN

TYP ⁽¹⁾

MAX ⁽²⁾UNIT

I_(VDD)

I_{(VDD_PLLM)}

I_{(VDD_PLLD)}

+

Frame rate = 60 Hz

Frame rate = 120 Hz

168

278

+

1.1-V rails

mA

211

362

Frame rate = 60 Hz

Frame rate = 120 Hz

Frame rate = 60 Hz

Frame rate = 120 Hz

6

I_{(VDD_PLLM)}

MCG PLL 1.1V ⁽⁶⁾

DCG PLL 1.1V ⁽⁶⁾

mA

6

I_{(VDD_PLLD)}

mA

6

All 1.8-V I/O current: (1.8-V power supply Frame rate = 60 Hz

for all I/O other than the host or parallel

interface and the SPI flash interface)

35

48

I_(VCC18)

mA

Frame rate = 120 Hz

35

2

48

Host or parallel interface I/O current: 1.8 to Frame rate = 60 Hz

3.3 V (includes IIC0, PDATA, video syncs,

I_{(VCC_INTF)}

mA

and HOST_IRQ pins) ⁽⁶⁾

Frame rate = 120 Hz

2

Frame rate = 60 Hz

Frame rate = 120 Hz

1

I_{(VCC_FLSH)}

Flash interface I/O current: 1.8 to 3.3 V ⁽⁶⁾

(1) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.

(2) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.

(3) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum

nominal voltage (that is 1.8 V).

(4) Input image is 1280 × 720 (HD) 24 bits using VESA reduced blanking v2 timings on the parallel interface at the frame rate shown with

the 0.3-in 720p (DLP3010LC) DMD. The controller has the CAIC and LABB algorithms turned off.

(5) The values do not take into account software updates or customer changes that may affect power performance.

(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor,

30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells.

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6.6 Pin Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

0.7 ×

VCC_INTF

I²C buffer (I/O type 7)

See

(1)

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

1.17

3.6

I/O type 1, 6 for pins noted in ⁽²⁾

VCC18 = 1.8 V

1.3

1.17

1.7

3.6

High-level input

threshold voltage

I/O type 5, 9, 11

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

V_IH

V

I/O type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

1.7

I/O type 5, 9, 11

2.0

I/O type 12, 13

2.0

0.3 ×

VCC_INTF

I²C buffer (I/O type 7)

–0.5

–0.3

I/O type 1, 2, 3, 6, 8 except pins

noted in ⁽²⁾

VCC18 = 1.8 V

0.63

I/O type 1, 6 for pins noted in ⁽²⁾

I/O type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

0.5

0.63

0.7

–0.3

1.35

1.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC18 = 1.8 V

Low-level input

threshold voltage

V_IL

V

I/O type 5, 9, 11

I/O type 12, 13

0.7

I/O type 5, 9, 11

I/O type 12, 13

0.8

I/O type 1, 2, 3, 6, 8

I/O type 5, 9, 11

I/O type 12, 13

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

VCC_INTF > 2 V

High-level output

voltage

V_OH

I/O type 5, 9, 11

I/O type 12, 13

V

1.7

I/O type 5, 9, 11

2.4

I/O type 12, 13

2.4

I²C buffer (I/O type 7)

0.4

0.2 ×

VCC_INTF

I²C buffer (I/O type 7)

VCC_INTF < 2 V

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O Type 12, 13

VCC18 = 1.8 V

0.45

0.7

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

Low-level output

voltage

V_OL

V

0.7

0.4

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6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

MAX UNIT

CONDITIONS⁽⁴⁾

I/O type 2, 4

I/O type 5

VCC18 = 1.8 V

2

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

3.5

10.6

5.4

10.8

7.8

15

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

High-level output

current⁽⁵⁾

I_OH

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_INTF = 2.5V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9, 13

I/O type 13

I/O type 5

I/O type 9

I/O type 13

I²C buffer (I/O type 7)

I/O type 2, 4

I/O type 5

15

3

VCC18 = 1.8 V

2.3

4.6

13.9

5.2

10.4

4.4

8.9

VCC_INTF = 1.8 V

VCC18 = 1.8 V

I/O type 1

I/O type 9

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC18 = 1.8 V

I/O type 13

I/O type 3

Low-level output

current⁽⁶⁾

I_OL

mA

I/O type 5

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

I/O type 9

I/O type 13

I/O type 5

I/O type 9

I/O type 13

V_{I2C buffer}< 0.1 ×

VCC_INTF or

V_{I2C buffer}> 0.9 ×

VCC_INTF

I²C buffer (I/O type 7)

10

–10

I/O type 1, 2, 3, 6, 8,

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O Type 12, 13

I/O Type 5, 9, 11

I/O type 12, 13

VCC18 = 1.8 V

10

–10

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

High-impedance

leakage current

I_OZ

µA

10

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6.6 Pin Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

TEST

PARAMETER⁽³⁾

MIN

TYP

CONDITIONS⁽⁴⁾

I²C buffer (I/O type 7)

I/O type 1, 2, 3, 6, 8

I/O Type 5, 9, 11

I/O Type 12, 13

I/O type 5, 9, 11

I/O type 12, 13

5

3.5

VCC18 = 1.8 V

2.6

VCC_INTF = 1.8 V

VCC_FLSH = 1.8 V

VCC_INTF = 2.5 V

VCC_FLSH = 2.5 V

VCC_INTF = 3.3 V

VCC_FLSH = 3.3 V

3.5

pF

Input capacitance

(including package)

C_I

3.5

I/O type 5, 9, 11

I/O type 12, 13

sub-LVDS –DMD high speed

(I/O type 4)

VCC18 = 1.8 V

3

(1) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.

(2) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied V_IHand V_ILrange from other 1.8-V

I/O.

(3) The I/O type refers to the type defined in 表5-10.

(4) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply

reference is set to.

(5) At a high level output signal, the given I/O will be able to output at least the minimum current specified.

(6) At a low level output signal, the given I/O will be able to sink at least the minimum current specified.

6.7 Internal Pullup and Pulldown Electrical Characteristics

over operating free-air temperature (unless otherwise noted) ⁽²⁾

TEST

INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS

MIN

MAX

UNIT

CONDITIONS⁽¹⁾

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

VCCIO = 3.3 V

VCCIO = 2.5 V

VCCIO = 1.8 V

29

38

56

30

36

52

63

90

kΩ

Weak pullup resistance

148

72

101

167

Weak pulldown resistance

(1) The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in 表5-10).

(2) An external 8-kΩpullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any

associated internal pullups or pulldowns.

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6.8 DMD Sub-LVDS Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.0

UNIT

V

V_CM

Common mode voltage

0.8

0.9

V_CM(Δpp)⁽¹⁾

V_CMchange peak-to-peak (during switching)

V_CMchange steady state

75

mV

V

V_CM(Δss)⁽¹⁾

–10

170

10

(2)

|V_OD

|

Differential output voltage magnitude

V_ODchange (between logic states)

Single-ended output voltage high

Single-ended output voltage low

Internal differential termination

250

350

10

V_OD(Δ)

V_OH

–10

0.825

0.625

80

1.025

0.775

100

1.175

0.975

120

V_OL

V

Tx_term

Ω

100-Ωdifferential PCB trace

(50-Ωtransmission lines)

Tx_load

0.5

6

inches

(1) See 图6-1

(2) V_ODis the differential voltage measured across a 100-Ωtermination resistance connected directly between the transmitter differential

pins. V_OD= V_P- V_N, where P and N are the differential output pins. |V_OD| is the magnitude of the peak-to-peak voltage swing across

the P and N output pins (see 图6-2). V_CMcancels out between signals when measured differentially, thus the reason V_ODswings

relative to zero.

+V

OD

100

90

80

|V_OD|

70

60

V

(û

CM SS

)

V

(û )

CM P-P

V

CM

(0 V) 50

40

30

|V_OD|

20

10

0

œV

OD

t_FALL

t_RISE

图6-1. Common Mode Voltage

V_CMis removed when the signals are viewed differentially

图6-2. Differential Output Signal

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6.9 DMD Low-Speed Interface Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.7 ×

VCC18

V_OH(DC)

V_OL(DC)

V_OH(AC)

V_OL(AC)

V

DC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.3 ×

VCC18

V

AC output high voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.8 ×

VCC18

VCC18 +

0.5

(1)

(2)

AC output low voltage for DMD_LS_WDATA

and DMD_LS_CLK

0.2 ×

VCC18

-0.5

1.0

V_OL(DC)to V_OH(AC)for rising edge

and V_OH(DC)to V_OL(AC)for rising

edge

DMD_LS_WDATA and DMD_LS_CLK

3.0

Slew rate

V/ns

DMD_DEN_ARSTZ

DMD_LS_RDATA

V_OL(AC)to V_OH(AC)for rising edge

0.25

0.5

(1) V_OH(AC)maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(2) V_OL(AC)minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ωseries

termination resistor, the DMD operates within the LPSDR input AC specifications.

(3) See 图6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See 图6-4 for DMD_DEN_ARSTZ rise and fall times.

DMD_DEN_ARSTZ

LS_CLK, LS_WDATA

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

OH(AC)

OH(DC)

V

OL(DC)

V

OL(AC)

10

0

10

0

t_RISE

t_FALL

t_RISE

t_FALL

图6-3. LS_CLK and LS_WDATA Slew Rate

图6-4. DMD_DEN_ARSTZ Slew Rate

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6.10 System Oscillator Timing Requirements

MIN

23.998

41.663

40%

NOM

24.000

41.667

50%

MAX

24.002

41.670

UNIT

MHz

ns

f_clk

t_c

Clock frequency, MOSC (master oscillator clock)⁽¹⁾

Cycle time, MOSC (clock period)⁽¹⁾

See 图6-5

t_w(H)

Pulse duration as percent of t_c⁽²⁾, MOSC, high

50% to 50% reference

points (signal)

t_w(L)

t_t

Pulse duration as percent of t_c⁽²⁾, MOSC, low

Transition time⁽²⁾, MOSC

50% to 50% reference

points (signal)

40%

50%

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

10

ns

t_jp

Long-term, peak-to-peak, period jitter⁽²⁾, MOSC

(that is the deviation in period from ideal period due

solely to high frequency jitter)

2%

(1) The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.)

The MOSC input does not support spread spectrum clock spreading.

(2) Applies only when driven by an external digital oscillator.

t

C

t

T

t

T

t

W(L)

W(H)

80%

20%

50%

MOSC

图6-5. System Oscillators

6.11 Power Supply and Reset Timing Requirements

MIN

MAX

UNIT

µs

t_w(L)

t_r

Pulse duration, active low, RESETZ

Rise time, RESETZ⁽¹⁾

50% to 50% reference points (signal)

20% to 80% reference points (signal)

80% to 20% reference points (signal)

0.3 V to 1.045 V (VDD)

1.25

0.5

1

µs

t_f

Fall time, RESETZ⁽¹⁾

µs

t_rise

Rise time, VDD (during VDD ramp up at

turn-on)

ms

(1) For more information on RESETZ, see 节5.

DC Power Supplies

t_f

t_r

80%

50%

20%

80%

50%

20%

RESETZ

t_w(L)

Time

图6-6. Power-Up and Power-Down RESETZ Timing

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6.12 Parallel Interface Frame Timing Requirements

See for additional information

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

50% reference points

1

lines

Pulse duration –default VSYNC_WE high

Vertical back porch (VBP) –time from the active edge of

VSYNC_WE to the active edge of HSYNC_CS for the first

active line⁽¹⁾

2

1

lines

Vertical front porch (VFP) –time from the active edge of the

HSYNC_CS following the last active line in a frame to the active

edge of VSYNC_WE⁽¹⁾

t_{p_vfp}

50% reference points

Total vertical blanking –the sum of VBP and VFP (t_{p_vbp}

t_{p_vfp}

+

t_{p_tvb}

t_{p_hsw}

t_{p_hbp}

50% reference points

See ⁽¹⁾

lines

)

4

128

PCLKs

Pulse duration –default HSYNC_CS high

Horizontal back porch (HBP) –time from the active edge of

HSYNC_CS to the rising edge of DATAEN_CMD

Horizontal front porch (HFP) –time from the falling edge of

DATAEN_CMD to the active edge of HSYNC_CS

t_{p_hfp}

50% reference points

8

PCLKs

(1) The minimum total vertical blanking is defined by the following equation: t_{p_tvb}(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines

where:

•

SOURCE_ALPF = Input source active lines per frame

DMD_ALPF = Actual DMD used lines per frame supported

1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

PDATA(23/15:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

图6-7. Parallel Interface Frame Timing

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6.13 Parallel Interface General Timing Requirements

MIN

1.0

MAX

155.0

1000

UNIT

MHz

ns

PCLK frequency

PCLK period

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

50% reference points

Max ƒ_clock

6.45

PCLK jitter

see ⁽¹⁾

PCLK pulse duration high

PCLK pulse duration low

50% reference points

2.43

ns

t_{p_wl}

Setup time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

t_{p_su}

t_{p_h}

50% reference points

0.9

ns

Hold time –HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

2.0

ns

Transition time –all signals

t_setup, 3DR

t_hold, 3DR

This is the setup time with respect to VSYNC⁽²⁾

This is the hold time with respect VSYNC⁽³⁾

50% reference points

1.0

ms

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock–5.76 ns]. Setup and hold times must be met even with clock jitter.

(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes

(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes

t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

图6-8. Parallel Interface Pixel Timing

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6.14 BT656 Interface General Timing Requirements

The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate

ITU-R BT.656 specification for detailed interface timing requirements. ⁽²⁾

MIN

MAX

UNIT

MHz

ns

PCLK frequency

PCLK period

1.0

33.5

ƒ_cll

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

t_{p_wl}

50% reference points

Max f_clock

29.85

1000

PCLK jitter

See ⁽¹⁾

PCLK pulse duration high

PCLK pulse duration low

50% reference points

10.0

ns

Setup time –PDATA(7:0) before the active edge of

PCLK

t_{p_su}

t_{p_h}

50% reference points

3.0

0.9

ns

Hold time –PDATA(7:0) after the active edge of

PCLK

20% to 80% reference points

(rising signal)

80% to 20% reference points

(falling signal)

t_t

0.2

3.0

ns

Transition time –all signals

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock–5.76 ns]. Clock jitter must maintain setup and hold times. BT.656

data bits must be mapped to the DLPC34xx PDATA bus as shown in 图6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA

(23:0) mapping.

(2) The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK. See 图6-9.

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

PDATA(7:0) of the input pixel data bus

Bus assignment mapping

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

Data bit mapping on controller pin

n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a

图6-9. BT.656 Interface Mode Bit Mapping

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6.15 Flash Interface Timing Requirements

The DLPC3478 flash memory interface consists of a SPI flash serial interface. The DLPC3478 can support 1- to 128-Mb

flash memories.^{(2) (3) (4)}

MIN

MAX

36.0

704

UNIT

MHz

ns

f_clock

SPI_CLK frequency

See ⁽¹⁾

1.4

t_{p_clkper}

t_{p_wh}

t_{p_wl}

SPI_CLK period

50% reference points

27.8

352

SPI_CLK pulse duration high

SPI_CLK pulse duration low

ns

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

t_t

0.2

3.0

ns

Transition time –all signals

Setup time –SPI_DIN valid before SPI_CLK falling

edge

t_{p_su}

t_{p_h}

50% reference points

10.0

0.0

ns

Hold time –SPI_DIN valid after SPI_CLK falling edge

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

t_{p_clqv}

1.0

3.0

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

t_{p_clqx}

50% reference points

ns

–3.0

(1) This range include the ±200 ppm of the external oscillator (but no jitter).

(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3478 does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. DLPC3478 hold capture timing has been set to facilitate reliable operation with standard external

SPI protocol devices.

(3) With the above output timing, DLPC3478 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the

rising edge of SPI_CLK.

(4) For additional requirements of the external flash device view the 节7.3.4 section.

t_CLKPER

SPI_CLK

(Controller output)

t_WL

t_WH

t_{P_SU}

t_{P_H}

SPI_DIN

(Controller input)

t_{P_CLQV}

SPI_DOUT, SPI_CS(1:0)

(Controller output)

t_{P_CLQX}

图6-10. Flash Interface Timing

6.16 Other Timing Requirements

MIN

MAX

10

UNIT

ns

t_rise, all^{(1) (2)}

20% to 80% reference points

80% to 20% reference points

20% to 80% reference points

80% to 20% reference points

t_fall, all^{(1) (2)}

10

ns

t_rise, PARKZ⁽²⁾

150

ns

t_fall, PARKZ⁽²⁾

ns

t_w, GPIO_08 (normal park) pulse width⁽³⁾

I²C baud rate

200

ms

kHz

100

(1) Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.

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(2) This is the recommended signal transition time to avoid input buffer oscillations.

(3) The pulse width encompasses the minimum high time and the minimum low time for this signal.

6.17 DMD Sub-LVDS Interface Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

45%

MIN

TYP

MAX

UNIT

(1)

t_R

t_F

Differential output rise time

Differential output fall time

DMD HS Clock switching rate

DMD HS Clock frequency

DMD HS Clock output duty cycle

250

ps

t_switch

f_clock

1200

600

Mbps

MHz

DCout

50%

55%

(1) Rise and fall times are defined for the differential V_ODsignal as shown in 图6-2.

6.18 DMD Parking Switching Characteristics

See ⁽²⁾

PARAMETER

Normal Park time⁽¹⁾

Fast park time⁽³⁾

TEST CONDITIONS

TYP

MAX

20

UNIT

ms

t_park

t_{fast park}

32

µs

(1) Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the

normal park request (GPIO_08 goes low).

(2) The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be

held on for a time after parking is completed to satisfy DMD requirements. See 节9.2 and the appropriate DMD or PMIC datasheet for

more information.

(3) Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast

park request (PARKZ goes low).

6.19 Chipset Component Usage Specification

The DLPC3478 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires

that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.

表6-1. DLPC3478 Supported DMDs and PMICs

DLPC3478 DLP Chipset

DMD

PMIC

DLP3010LC

DLPA2000

DLPA2005

DLPA3000

DLPA3005

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7 Detailed Description

7.1 Overview

The DLPC3478 controller is part of the chipset that includes the DLP3010LC (0.3 inch 720p) DMD, and the

DLPA200x or DLPA300x PMIC/LED driver. To ensure reliable operation of the DLP chipset, the DLPC3478 must

always be used with the supported devices shown in 表6-1.

7.2 Functional Block Diagram

Test

Pattern

Generator

Video Processing

/5

Parallel Video

or BT656 Port

ñ

Brightness Enhancement

Chroma Interpolation

Color Space Conversion

Color Correction

ñ

Contrast Adjustment

Dynamic Scaling

Gamma Correction

/24

Input

Control

Processing

Image Format Processing

Power Saving Operations

Splash

Screen

CAIC Processing

DLP Subsystem

Display Formatting

eDRAM (Frame Memory)

Arm^®Cortex^®-M3

Processor

128 KB I/D Memory

JTAG

I2C_0

/

Real Time

Control System

SPI_0

DMD_HS_CLK

(sub-LVDS)

DMD_HS_DATA(A:H)

/

(sub-LVDS)

DMD Interface

DMD_LS_CLK

SPI_1

I2C_1

LED Control

Other options

Clocks and Reset

Generation

DMD_LS_WDATA

DMD_LS_RDATA

/20

GPIO

DMD_DEN_ARSTZ

Clock (Crystal)

Reset Control

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7.3 Feature Description

7.3.1 Input Source

7.3.1.1 Supported Resolution and Frame Rates

表7-1. Supported Input Source Ranges^{(2) (3) (4)}

SOURCE RESOLUTION RANGE⁽⁷⁾

HORIZONTAL VERTICAL

Landscape Portrait Landscape Portrait

200 to 800 320 to 1280

FRAME RATE

RANGE

INTERFACE

Bits / Pixel ⁽⁵⁾

IMAGE TYPE

Parallel

24 max

2D only

3D only

320 to 1280

200 to 800

200 to 720

10 to 122 Hz

200 to 720

320 to 1280

100 ±2 Hz

120 ±2 Hz

BT.656-NTSC

See ⁽⁶⁾

2D only

720

n/a

240

288

n/a

60 ±2 Hz

(1)

BT.656-PAL ⁽¹⁾

n/a

50 ±2 Hz

(1) All parameters in this row follow the BT.656 standard. The image format is always landscape.

(2) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line

rate.

(3) The maximum DMD size for all rows in the table is 1280 × 720.

(4) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to

determine the latest available frame rate and input resolution support for a given firmware image.

(5) Bits per pixel does not necessarily equal the number of data pins used on the DLPC3478 controller.

(6) BT.656 uses 16-bit 4:2:2 YCr/Cb.

(7) By using an I2C command, portrait image inputs can be rotated on the DMD by minus 90 degrees so that the image is displayed in

landscape format.

7.3.1.2 3D Display

For 3D sources on the video input interface, images must be frame sequential (L, R, L, ...) when input to the

DLPC34xx controller. Any processing required to unpack 3D images and to convert them to frame sequential

input must be done by external electronics prior to inputting the images to the controller. Each 3D source frame

input must contain a single eye frame of data, separated by a VSYNC, where an eye frame contains image data

for a single left or right eye. The signal 3DR input to the controller indicates whether the input frame is for the left

eye or right eye.

Each DMD frame is displayed at the same rate as the input interface frame rate. 图 7-1 below shows the typical

timing for a 50-Hz or 60-Hz 3D HDMI source frame, the input interface of the DLPC34xx controller, and the

DMD. In general, video frames sent over the HDMI interface pack both the left and right content into the same

video frame. GPIO_04 is optionally sent to a transmitter on the system PCB for wirelessly transmitting a

synchronization signal to 3D glasses (usually an IR sync signal). The glasses are then in phase with the DMD

images displayed. Alternately, the 3D Glasses Operation section shows how DLP link pulses can be used

instead.

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50 Hz or 60 Hz

(HDMI)

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L

R

L

R

L

R

L

R

L

R

L

R

100 Hz or 120 Hz

(34xx Input)

R

3DR ⁽²⁾

(3D L/R input)

100 Hz or 120 Hz

(on DMD)

R

L

R

L

R

L

R

L

R

L

R

L

GPIO_04 ⁽¹⁾

(3D L/R output)

(1) Left = 1, Right = 0

(2) 3DR must toggle at least 1 ms before VSYNC

图7-1. 3D Display Left and Right Frame Timing

7.3.1.3 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes the signals listed in 表

7-2.

表7-2. Parallel Interface Signals

SIGNAL

DESCRIPTION

VSYNC_WE

HSYNC_CS

vertical sync

horizontal sync

data valid

DATAEN_CMD

PDATA

24-bit data bus

pixel clock

PCLK

PDM_CVS_TE

parallel data mask (optional)

Note

VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no

longer active, the display sequencer stops and causes the LEDs to turn off.

The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section

shows the relationship of these signals.

An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without

losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source

image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or

active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic

low signal. PDM_CVS_TE must only change during vertical blanking.

The parallel interface supports six data transfer formats. They are as follows:

• 24-bit RGB888 or 24-bit YCbCr888 on a 24 data wire interface

• 18-bit RGB666 or 18-bit YCbCr666 on an 18 data wire interface

• 16-bit RGB565 or 16-bit YCbCr565 on a 16 data wire interface

• 16-bit YCbCr 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, ...)

• 8-bit RGB888 or 8-bit YCbCr888 serial (1 color per clock input; 3 clocks per displayed pixel) on an 8 data wire

interface

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• 8-bit YCbCr 4:2:2 serial (1 color per clock input; 2 clocks per displayed pixel) on an 8 data wire interface

The 节7.3.1.3.1 section shows the required PDATA(23:0) bus mapping for these six data transfer formats.

7.3.1.3.1 PDATA Bus –Parallel Interface Bit Mapping Modes

23

0

Red / Cr

Green / Y

Blue / Cb

Controller input mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Controller internal re-mapping

7

5

4

3

5

4

3

4

3

2

0

Red / Cr

Green / Y

Blue / Cb

图7-2. RGB-888 and YCbCr-888 I/O Mapping

23

0

Input

3

Input

3

Input

7

6

5

4

2

1

0

7

6

5

4

2

1

0

7

6

5

4

3

2

1

0

Controller input mapping

Controller internal re-mapping

5

4

3

5

4

3

7

6

5

4

3

2

1

0

Red / Cr

Green / Y

Blue / Cb

图7-3. RGB-666 and YCbCr-666 I/O Mapping

23

0

Input

Controller input mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Controller internal re-mapping

4

3

4

3

7

6

5

4

3

2

1

0

Red / Cr

Green / Y

Blue / Cb

图7-4. RGB-565 and YCbCr-565 I/O Mapping

23

0

Cr / Cb

Y

N/A

Controller input mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Controller internal re-mapping

4

3

4

3

Cr / Cb

Y

N/A

图7-5. 16-Bit YCbCr-880 I/O Mapping

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23

6

Input 1 single color pixel per clock, contiguous

Green / Y

0

Red / Cr

Blue / Cb

Controller input mapping

7

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Input order must be R‰G‰B

First Input Clock

Second Input Clock

Third Input Clock

Controller internal re-mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Red / Cr

Green / Y

(Output 1 full pixel per clock, non-contiguous)

Blue / Cb

图7-6. 8-Bit RGB-888 or YCbCr-888 I/O Mapping

[Input 1 single Y/Cr-Cb pixel per clock œ Contiguous]

23

0

Cr / Cb

Y

Blue / Cb

Controller input mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Input Order must be Cr/Cb ‰ Y

First Input Clock

Second Input Clock

Controller internal re-mapping

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Cr/Cb

Y

Blue / Cb

[Output 1 full pixel per clock œ Non-Contiguous]

图7-7. 8-Bit Serial YCbCr-422 I/O Mapping

7.3.2 Pattern Display

Pattern display is one of the key capabilities of the DLPC3478 display and light controller. When the DLPC3478

controller is configured for pattern display, most video processing functions can be bypassed to allow for

accurate pattern display. For user flexibility and simple system design the DLPC3478 controller supports both

external pattern and internal pattern streaming modes. In external pattern streaming mode, patterns are sent to

the DLPC3478 controller over parallel interface. In internal pattern streaming mode, 1D patterns are pre-loaded

in flash memory and a host command is sent to DLPC3478 controller to display the patterns. Internal pattern

mode allows for a simple system design by eliminating the need for any external processor to generate and sent

1D patterns to the DLPC3478 controller.

The DLPC3478 controller has two optional trigger out signals and one optional trigger in signal to synchronize

patterns with a camera, sensor, or other peripherals.

表7-3. Pattern Display Signals

SIGNAL NAME

DESCRIPTION

External Pattern Mode: Active at the beginning of each input frame.

Internal Pattern Mode: Active at the beginning of a predefined group of patterns.

TRIG_OUT_1 (TSTPT_4)

Active during display of each pattern. When operating in external pattern mode, one video frame can

have multiple patterns.

TRIG_OUT_2 (GPIO_07)

TRIG_IN (3DR)

Active in Internal Pattern Display mode only. An external input trigger signal is used to advance to the

next pattern in internal pattern mode.

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7.3.2.1 External Pattern Mode

External pattern mode supports 8-bit and 1-bit monochrome or RGB patterns.

7.3.2.1.1 8-bit Monochrome Patterns

In 8-bit external pattern mode, the DLPC3478 controller supports up to 120-Hz input frame rate (VSYNC). In this

mode, the 24-bit input data sent over the parallel interface can be configured as a combination of 1 (8-bits), 2

(16-bits), or 3 (24-bits) 8-bit patterns. 方程式1 calculates the maximum pattern rate for an 8-bit pattern.

120 Hz × 3 = 360 Hz

(1)

where

• the maximum allowed input frame rate is 120 Hz

The DLPC3478 controller firmware allows for the following user programmability.

• Exposure time (t_Exposure): Time during which a pattern displays and the illumination is on.

• DarkPre time (t_DarkPre): Dark time (before the pattern exposure) during which no pattern displays and the

illumination is off.

• DarkPost time (t_DarkPost): Dark time (after the pattern exposure) during which no pattern displays and the

illumination is off.

• Number of 8-bit patterns within a frame: 1, 2, or 3 within each frame period

• Selection of Illuminator that is on for each 8-bit pattern.

• TRIG_OUT_1 and TRIG_OUT_2 signal configuration and delay.

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图7-8 shows a configuration with 3 × 8-bit patterns.

VSYNC

[Frame N+1] PDATA 23:0

t_DarkPost

Parallel Input

t_DarkPost

t_DarkPre

t_DarkPost

t_DarkPre

t_Exposure

[Frame N]

PDATA 23:16

[Frame N]

PDATA 15:8

[Frame N]

PDATA 7:0

Displayed Pattern

Illuminator

BLUE LED

t

D1

Trigger Out 1

(Frame Trigger)

t

D2

t

D2

t

D2

Trigger Out 2

(Pattern Trigger)

t_D1is the configurable delay for the frame trigger

t_D2is the configurable delay for the sub-frame trigger

图7-8. 3 × 8-bit (Blue) Pattern Configurations

• 3 × 8-bit patterns are displayed within each input VSYNC frame period.

• t_DarkPre, t_Exposureand t_DarkPostare the same for each pattern within a frame period.

• The sum of dark time and exposure time (t_DarkPre+ t_Exposure+ t_DarkPost) for the three patterns must be equal to

or less than the full frame period. If the sum is less than the full frame period, additional dark time will be

appended to the end of the last pattern.

• The Blue LED is configured to be on for each pattern.

• TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20

microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to input V_SYNC

.

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure . TRIG_OUT_2 delay (t_D2) is configured with reference to the start of the pattern and is set once per

pattern within a frame.

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图7-9 shows a configuration with 2 × 8-bit patterns.

V_SYNC

[Frame N+1] PDATA 23:0

t_DarkPost

[Frame N+2] PDATA 23:0

t_DarkPost

Parallel Input

t_DarkPost

t_DarkPre

t_DarkPost

t_DarkPre

t_Exposure

[Frame N]

PDATA 23:16

t_DarkPre

t_Exposure

[Frame N]

PDATA 15:8

t_Exposure

[Frame N+1]

PDATA 15:8

[Frame N+1]

PDATA 23:16

Displayed Pa ern

Illuminator

RED LED

t_D1

Trigger Out 1

(Frame Trigger)

t_D2

Trigger Out 2

(Pa ern Trigger)

图7-9. 2 × 8-bit (Red) Pattern Configurations

• 2 × 8-bit patterns are displayed within each input VSYNC frame period.

• t_DarkPre, t_Exposureand t_DarkPostare the same for each pattern within a frame period.

• The sum of dark time and exposure time (t_DarkPre+ t_Exposure+ t_DarkPost) for the three patterns must be equal to

or less than the full frame period. If the sum is less than the full frame period, additional dark time will be

appended to the end of the last pattern.

• The Red LED is configured to be ON for each pattern.

• TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20

microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to input V_SYNC

.

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure. TRIG_OUT_2 delay (t_D2) is configured with reference to the start of the pattern and is set once per

pattern within a frame.

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图7-10 shows a configuration with 1 × 8-bit patterns.

V

SYNC

[Frame N+1] PDATA 23:16

[Frame N+2] PDATA 23:16

[Frame N+1] PDATA 23:16

Parallel Input

[Frame N] PDATA 23:16

t_Exposure

t_DarkPre

t_Exposure

t_DarkPostt_DarkPre

t_DarkPost

Displayed Pa ern

GREEN LED

Illuminator

t_D1

Trigger Out 1

(Frame Trigger)

Trigger Out 2

t_D2

(Pa ern Trigger)

图7-10. 1 × 8-bit (Green) Pattern Configurations

• 1 × 8-bit pattern is displayed within each input VSYNC frame period.

• t_DarkPre, t_Exposureand t_DarkPostare the same for each pattern within a frame period.

• The sum of dark time and exposure time (t_DarkPre+ t_Exposure+ t_DarkPost) for the three patterns must be equal to

or less than the full frame period. If the sum is less than the full frame period, additional dark time will be

appended to the end of the last pattern.

• The Green LED is configured to be on for each pattern.

• TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20

microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to input V_SYNC

.

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure . TRIG_OUT_2 delay (t_D2) is configured with reference to the start of the pattern and is set once per

pattern within a frame.

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7.3.2.1.2 1-Bit Monochrome Patterns

Similar to the 8-bit external pattern mode, the maximum supported 24-bit input frame for 1-bit external pattern

mode is 104.2 Hz. In 1-bit pattern mode each of the 24-bit inputs are treated as separate binary patterns

resulting in a maximum of 24 patterns. The maximum pattern rate for each 1-bit pattern is 2500 Hz.

The DLPC3478 controller firmware allows for the following user programmability:

• Exposure time: Time during which a pattern is displayed.

• Dark time: Time during which no pattern is displayed and the illumination in off.

• Number of 1-bit patterns within a frame - up to maximum of 24.

• Illuminator: Illuminator that is on for each 1-bit pattern. User defined illuminator is auto selected for all the

patterns within a frame. User cannot select different illuminator for different 1-bit patterns within a frame.

• TRIG_OUT_1 and TRIG_OUT_2 signal configuration and delay.

图7-11 shows a configuration with 24 × 1-bit patterns.

VSYNC

[Frame N+1] PDATA 23:0

[Frame N+2] PDATA 23:0

Parallel Input

t

DarkPost+Pre

t

DarkPost+Pr

DarkPost+Pre

DarkPre

e

t_Exposure

Displayed Pa ern

Illuminator

Pat 0

Pat 1

Pat 23

Pat 0

Pat 1

Pat 23

Blue

LED

Blue

LED

Blue

LED

Blue

LED

Blue

LED

Blue

LED

t

D1

t

D1

Trigger Out 1

(Set Trigger)

t_D2

Trigger Out 2

(Pa ern Trigger)

图7-11. 24 × 1-bit (Blue) Pattern Configurations

• 24 × 1-bit patterns are displayed within each input VSYNC frame period.

• t_DarkPre, t_Exposureand t_DarkPostare the same for each pattern within a frame period.

• The sum of dark time and exposure time (t_DarkPre+ t_Exposure+ t_DarkPost) for all the 1-bit patterns must be equal

to or less than the full frame period. If the sum is less than the full frame period, additional dark time will be

appended to the end of the last pattern.

• The Blue LED is configured to be ON for each pattern.

• TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20

microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to input V_SYNC

.

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure. TRIG_OUT_2 delay (t_D2) is configured with reference to the start of the pattern and is set once per

pattern within a frame.

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7.3.2.2 Internal Pattern Mode

There are two key differences between internal and external pattern mode:

• Internal pattern mode only supports 1D patterns i.e the pattern data is the same across the entire row or

column of the DMD (图7-12, 图7-13).

• Internal pattern mode enables user to design a simple system by eliminating need of an external processor to

generate and send patterns every frame. In internal pattern mode one row or one column patterns are pre-

loaded in the flash memory and a command is send to DLPC3478 controller to display the patterns.

Implementation details on how to create patterns, save patterns in Flash memory and load patterns from

flash memory into the DLPC3478 controller’s internal memory are described in Software Programmers

Guide.

Copy to every column on the DMD

图7-12. Column Replication

Copy to every line on the DMD

Line of Data

图7-13. Row Replication

Internal pattern mode additionally provides two configurations to trigger the display of patterns, free running

mode, (shown in 图7-14) and trigger in mode (shown in 图7-15).

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7.3.2.2.1 Free Running Mode

In free running mode the DLPC3478 controller generates an internal synchronization signal to display pre-stored

patterns. User sends an I²C command to instruct the DLPC3478 controller to download the 1D patterns from

flash memory into DLPC3478 controller’s internal memory and begin display of the 1D patterns.

Internally

Generated V

SYNC

Pattern Data

t_DarkPre+Post

Pattern Data

t_Exposure

t_DarkPre

Pat

M

Pat 0

Pat 1

Pat N

Pat 0

Pat 1

Pattern Display

Illuminator

Blue

LED

Blue

LED

Blue

LED

Blue

LED

Blue

LED

Blue

LED

t_D1

Trigger Out 1

(Set Trigger)

t_D2

Trigger Out 2

(Pattern Trigger)

图7-14. Free Running Mode

• The device displays multiple 1D patterns within an internally-generated V_SYNCperiod. t_Exposure(exposure

time), t_DarkPreand t_DarkPost(dark time) are equal for all the 1D patterns within one internally generated V_SYNC

frame.

• The Blue LED is configured to be on for each pattern.

• TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20

microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to internally generated V_SYNC

.

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure. TRIG_OUT_2 delay (t_D2) is configured with reference to the start of each pattern.

• V_SYNCis generated internally according to different sets of patterns stored in the SPI flash memory.

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7.3.2.2.2 Trigger In Mode

Trigger In mode provides higher level of control to the user for displaying patterns. In this mode, the user

determines when to display the pattern by sending an external trigger signal to the DLPC3478 controller. The

DLPC3478 controller outputs a Pattern Ready signal to let the user know when DLPC3478 controller is ready to

accept an external trigger signal.

Pa ern Ready

(Output)

Trigger In

(External)

Load

Pattern Data

Pa ern Data

t_{DarkPre+DarkPost}

t_{DarkPost+Load}

t_DarkPre

t_Exposure

Pat

0

Pat N

Pat 0

Pat 1

Pat M

Pat 1

Pa ern Display

Illuminator

Blue

LED

Blue

LED

Blue

LED

Blue LED

BLUE LED

t_D1

Trigger Out 1

(Set Trigger)

t_D2

Trigger Out 2

(Pa ern Trigger)

图7-15. Trigger In Mode

• The DLPC3478 controller sets the Pattern Ready signal high to denote that the DLPC3478 controller is ready

to accept the Trigger In signal.

• The user sends the external trigger input signal to the DLPC3478 controller to begin the display of the next

pattern with t_Exposure(exposure time), t_DarkPreand t_DarkPost(dark time).

• The Blue LED is configured to be on for each pattern.

• TRIG_OUT_1 (Pattern Set Trigger) is configured active high polarity and will have a minimum pulse width of

20 microseconds. TRIG_OUT_1 delay (t_D1) is configured with respect to external trigger input (TRIG_IN).

• TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern

exposure. TRIG_OUT_2 delay (t_D2) is configured with reference to the start of each pattern exposure.

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7.3.3 Device Startup

• The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.

• While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).

• HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is

pulled high, this indicates that the controller is performing boot-up and auto-initialization.

• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to

indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the

external signal).

• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the

falling edge of the signal, the initialization is complete.

• The DLPC34xx controller is ready to receive commands through I²C or accept video over the video interface

only after auto-initialization is complete.

• The controller initialization typically completes (HOST_IRQ goes low) within 500 ms of RESETZ being

asserted. However, this time may vary depending on the software version and the contents of the user

configurable auto initialization file.

RESETZ

auto-initialization

HOST_IRQ

(with external pullup)

(INIT_BUSY)

t0

t1

t0: rising edge of RESETZ; auto-initialization begins

t1: falling edge of HOST_IRQ; auto-initialization is complete

图7-16. HOST_IRQ Timing

7.3.4 SPI Flash

7.3.4.1 SPI Flash Interface

The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the

below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing

Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash

Device Options table for example compatible flash options. The minimum required flash size depends on the

size of the utilized firmware. The firmware size depends upon a variety of factors including the number of

sequences, lookup tables, and splash images.

The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The

device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.

The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash

device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip

select zero. The boot routine uploads program code from flash memory to program memory then transfers

control to an auto-initialization routine within program memory.

The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features,

and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below 表7-4, 表7-5, and

表7-6.

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表7-4. Additional DLPC34xx SPI Flash Requirements

FEATURE

DLPC34xx REQUIREMENT

SPI interface width

SPI polarity and phase settings

Fast READ addressing

Programming mode

Page size

Single

SPI mode 0

Auto-incrementing

Page mode

256 B

Sector size

4-KB sector

Any

Block size

Block protection bits

Status register bit(0)

Status register bit(1)

Status register bits(6:2)

Status register bit(7)

0 = Disabled

Write in progress (WIP), also called flash busy

Write enable latch (WEN)

A value of 0 disables programming protection

Status register write protect (SRWP)

Because the DLPC34xx controller supports only single-byte status register R/W command execution,

it may not be compatible with flash devices that contain an expansion status byte. However, as long

as the expansion status byte is considered optional in the byte 3 position and any write protection

control in this expansion status byte defaults to unprotected, then the flash device is likely compatible

with the DLPC34xx.

Status register bits(15:8)

(that is expansion status byte)

The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled

or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as

part of the boot process.

The DLPC34xx issues these commands during the boot process:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8

bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

表 7-5 and 表 7-6 below list the specific instruction OpCode and timing compatibility requirements. The

DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.

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表7-5. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

BYTE 1

SPI FLASH COMMAND

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

(OPCODE)

Fast READ (1 output)

Read status

0x0B

0x05

0x01

0x06

0x02

0x20

0xC7

ADDRS(0)

N/A

ADDRS(1)

N/A

ADDRS(2)

STATUS(0)

dummy

DATA(0)⁽¹⁾

Write status

STATUS(0)

See ⁽²⁾

Write enable

Page program

Sector erase (4 KB)

Chip erase

ADDRS(0)

ADDRS(1)

ADDRS(2)

DATA(0)⁽¹⁾

(1) Shows the first data byte only. Data continues.

(2) Access to a second (expansion) write status byte not supported by the DLPC34xx controller.

表 7-6 below and the Flash Interface Timing Requirements section list the specific timing compatibility

requirements for a DLPC34xx compatible flash device.

表7-6. SPI Flash Key Timing Parameter Compatibility Requirements

SPI FLASH TIMING PARAMETER^{(1) (2)}

SYMBOL

ALTERNATE SYMBOL

MIN

MAX

UNIT

Access frequency (all commands)

FR

f_C

MHz

≤1.4

≥30.1

Chip select high time (also called chip select

deselect time)

t_SHSL

t_CSH

ns

≤200

≥0

Output hold time

t_CLQX

t_CLQV

t_DVCH

t_CHDX

t_HO

t_V

t_DSU

t_DH

ns

Clock low to output valid time

Data in set-up time

Data in hold time

≤11

≤5

(1) The timing values apply to the specification of the peripheral flash device, not the DLPC34xx controller. For example, the flash device

minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.

(2) The DLPC34xx does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to

a logic high on the PCB through an external pullup.

In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin

must be supplied with the corresponding voltage. The DLPC34xx Validated SPI Flash Device Options table

contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx

controller.

表7-7. DLPC34xx Validated SPI Flash Device Options^{(1) (2) (3)}

DENSITY (Mb)

VENDOR

PART NUMBER

1.8-V COMPATIBLE DEVICES

W25Q40BWUXIG

PACKAGE SIZE

4 Mb

8 Mb

Winbond

Macronix

2 × 3 mm USON

MX25U4033EBAI-12G

1.43 × 1.94 mm WLCSP

1.68 × 1.99 mm WLCSP

MX25U8033EBAI-12G

2.5- OR 3.3-V COMPATIBLE DEVICES

Winbond W25Q16CLZPIG

16 Mb

5 × 6 mm WSON

(1) The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC34xx controller. Make sure to order the device that

supports the correct supply voltage as multiple voltage options are often available.

(2) Numonyx (Micron) serial flash devices typically do not support the 4 KB sector size compatibility requirement for the DLPC34xx

controller.

(3) The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC34xx controller,

but they have not been formally validated by TI.

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7.3.4.2 SPI Flash Programming

The SPI pins of the flash can directly be driven for flash programming while the DLPC34xx controller I/Os are tri-

stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state

while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.

Alternatively, the DLPC34xx controller can program the SPI flash itself when commanded via I²C if a valid

firmware image has already been loaded and the controller is operational.

7.3.5 I²C Interface

Both of the DLPC34xx I²C interface ports support a 100-kHz baud rate. Because I²C interface transactions

operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices

in the system.

7.3.6 Content Adaptive Illumination Control (CAIC)

Content Adaptive Illumination control (CAIC) is part of the IntelliBright^®suite of advanced image processing

algorithms that adaptively enhances brightness and reduces power. In common real-world image content most

pixels in the images are well below full scale for the for the R (red), G (green), and B (blue) digital channels input

to the DLPC34xx. As a result of this, the average picture level (APL) for the overall image is also well below full

scale, and the dynamic range for the collective set of pixel values is not fully used. CAIC takes advantage of the

headroom between the source image APL and the top of the available dynamic range of the display system.

CAIC evaluates images on a frame-by-frame basis and derives three unique digital gains, one for each of the R,

G, and B color channel. During image processing, CAIC applies each gain to all pixels in the associated color

channel. The calculated gain is applied to all pixels in that channel so that the pixels as a group collectively shift

upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the

point where just a few pixels in each color channel are clipped. The Source Pixels for a Color Channel and

Pixels for a Color Channel After CAIC Processing figures below show an example of the application of CAIC for

one color channel.

Single-pixel

Headroom

255

APL Headroom

Clipped

to 255

166

110

Time

(1) APL = 110

.

(1) APL = 166

(2) Channel gain = 166/110 = 1.51

图7-17. Source Pixels for a Color Channel

图7-18. Pixels for a Color Channel After CAIC

Processing

Above, 图 7-18 shows the gain that is applied to a color processing channel inside the DLPC34xx. Additionally,

CAIC adjusts the power for the R, G, and B LED by commanding different LED currents. For each color channel

of an individual frame, CAIC intelligently determines the optimal combination of digital gain and LED power. The

user configurable CAIC settings heavily influence the amount of digital gain that is applied to a color channel and

the LED power for that color.

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0.33

0.22

0.18

(1)

CAIC Disabled

= 1 W

CAIC Enabled

P = 0.73 W

TOTAL

P

TOTAL

(1) With CAIC enabled, if red and blue LEDs require less than nominal power for a given input image, the red and blue LED power will

reduce.

图7-19. CAIC Power Reduction Mode (for Constant Brightness)

As CAIC applies a digital gain to each color channel and adjusts the power to each LED, CAIC ensures the

resulting color balance in the final image matches the target color balance for the projector system. Thus, the

effective displayed white point of images is held constant by CAIC from frame to frame.

CAIC can be used to increase the overall image brightness while holding the total power for all LEDs constant,

or CAIC can be used to hold the overall image brightness constant while decreasing LED power. In summary,

CAIC has two primary modes of operation:

• Power reduction mode holds overall image brightness constant while reducing LED power

• Enhanced brightness mode holds overall LED power constant while enhancing image brightness

In power reduction mode, since the R, G, and B channels can be gained up by CAIC inside the DLPC34xx, the

LED power can be reduced for any color channel until the brightness of the color on the screen is unchanged.

Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as

if CAIC was not used. 图 7-19 shows an example of LED power reduction by CAIC for an image where the red

and blue LEDs can consume less power.

In enhanced brightness mode the R, G, and B channels can be gained up by CAIC with LED power generally

being held constant. This results in an enhanced brightness with no power savings.

While there are two primary modes of operation described, the DLPC34xx actually operates within the extremes

of pure power reduction mode and enhanced brightness mode. The user can configure which operating mode

the DLPC34xx will more closely follow by adjusting the CAIC gain setting as described in the software

programmer's guide.

In addition to the above functionality, CAIC also can be used as a tool with which FOFO (full-on full-off) contrast

on a projection system can be improved. While operating in power reduction mode, the DLPC34xx reduces LED

power as the intensity of the image content for each color channel decreases. This will result in the LEDs

operating at nominal settings with full-on content (a white screen) and reducing power output until the dimmest

possible content (a black screen) is reached. In this latter case, the LEDs will be operating at minimum power

output capacity and thus producing the minimum possible amount of off-state light. This optimization provided by

CAIC will thereby improve FOFO contrast ratio. The given contrast ratio will further increase as nominal LED

current (full-on state) is increased.

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7.3.7 Local Area Brightness Boost (LABB)

Local area brightness boost (LABB), part of the IntelliBright^™suite of advanced image processing algorithms,

adaptively gains up regions of an image that are dim relative to the average picture level. The controller applies

significant gain to some regions of the image, and applies little or no gain to other regions. The LABB algorithm

evaluates images frame-by-frame and calculates the local area gains to be used for each image. Since many

images have a net overall boost in gain, even if the controller applies no gain to some parts of the image, the

controller boosts the overall perceived brightness of the image.

图 7-20 below shows a split screen example of the impact of the LABB algorithm for an image that includes dark

areas.

图7-20. LABB enabled (left side) and LABB disabled (right side)

The LABB algorithm operates most effectively when ambient light conditions are used to help determine the

decision about the strength of gains utilized. For this reason, it may be useful to include an ambient light sensor

in the system design that is used to measure the display screen's reflected ambient light. This sensor can assist

in dynamically controlling the LABB strength. Set the LABB gain higher for bright rooms to help overcome

washed out images. Set the LABB gain lower in dark rooms to prevent overdriven pixel intensities in images.

7.3.8 3D Glasses Operation

When using 3D glasses (with 3D video input and appropriate software support), the controller outputs sync

information to align the left eye and right eye shuttering in the glasses with the displayed DMD image frames. 3D

glasses typically use either Infrared (IR) transmission or DLP Link^™technology to achieve this synchronization.

One glasses type uses an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the

glasses. In this case DLPC34xx controller output signal GPIO_04 can be used to cause the IR transmitter to

send an IR sync signal to the glasses. The 图7-21 figure shows the timing sequence for the GPIO_04 signal.

The second type of glasses relies on sync information that is encoded into the light being output from the

projection lens. This approach uses the DLP Link feature for 3D video. Many 3D glasses from different suppliers

have been built using this method. The advantage of using the DLP Link feature is that it takes advantage of

existing projector hardware to transmit the sync information to the glasses. This method may give an advantage

in cost, size and power savings in the projector.

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When using DLP Link technology, one light pulse per DMD frame is output from the projection lens while the

glasses have both shutters closed. To achieve this, the DLPC34xx tells the DLPAxxxx when to turn on the

illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame.

Because the shutters in the glasses are both off when the pulse is sent, the projector illumination source is also

off except when the light is sent to create the pulse. The pulses may use any color; however, due to the

transmission property of the eye-glass LCD shutter lenses and the sensitivity of the white-light sensor used on

the eye-glasses, it is highly recommended that blue is not used for pulses. Red pulses are the recommended

color to use. The 图 7-21 figure below shows 3D timing information. 图 7-22 and 表 7-8 show the timing for the

light pulses when using the DLP Link feature.

50 Hz or 60 Hz

(HDMI)

L

R

L

R

L

R

L

R

L

R

L

R

100 Hz or 120 Hz

(34xx Input)

L

R

L

R

L

R

L

R

L

R

L

R

3DR ⁽¹⁾⁽²⁾

(3D L/R input)

100 Hz or 120 Hz

(on DMD)

R

L

R

L

R

L

R

L

R

L

R

L

GPIO_04 ⁽¹⁾

(3D L/R output)

0 µs (min)

5 µs (max)

GPIO_04

LED_SEL_0, LED_SEL_1

Video

On DMD

Dark time

t1

t2

(1) Left = 1, Right = 0

(2) 3DR must toggle 1 ms before VSYNC

t1: both shutters turned off

t2: next shutter turned on

图7-21. 3D Display Left and Right Frame and Signal Timing

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video data on subframe n

video data on subframe n+1

3D glasses shutter

E

A

C

B

D

A

Video

t1

t2

The time offset of DLP Link pulses at the end of a subframe alternates between B and B+D where D is the delta offset.

图7-22. 3D DLP Link Pulse Timing

表7-8. 3D DLP Link Timing

HDMI Source Frame DLPC34xx Input Frame

A

B

C

D

E

Rate (Hz)⁽¹⁾

Rate (Hz)

(µs)

20 - 32

128 - 163

49.0

98

> 500

> 622

> 658

> 655

> 634

> 632

> 630

> 2000

(31.8 nominal)

(161.6 nominal)

20 - 32

128 - 163

50.0

51.0

59.0

60.0

61.0

100

102

118

120

122

(31.2 nominal)

(158.4 nominal)

20 - 32

128 - 163

(30.6 nominal)

(155.3 nominal)

20 - 32

128 - 163

(26.4 nominal)

(134.2 nominal)

20 - 32

128 - 163

(26.0 nominal)

(132.0 nominal)

20 - 32

128 - 163

(25.6 nominal)

(129.8 nominal)

(1) Timing parameter C is always the sum of B+D.

7.3.9 Test Point Support

The DLPC34xx test point output port, TSTPT_(7:0), provides selected system calibration and controller debug

support. These test points are inputs when reset is applied. These test points are outputs when reset is released.

The controller samples the signal state upon the release of system reset and then uses the captured value to

configure the test mode until the next time reset is applied. Because each test point includes an internal

pulldown resistor, external pullups must be used to modify the default test configuration.

The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce

switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is

recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for

a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially

adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points

are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is

released does not have any effect until the next time reset asserts and releases. 表 7-9 describes the test mode

selections for one programmable scenario defined by TSTPT_(2:0).

表7-9. Test Mode Selection Scenario Defined by TSTPT_(2:0)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT_(2:0) = 0b010

60 MHz

TSTPT OUTPUT VALUE⁽¹⁾

TSTPT_(2:0) = 0b000

TSTPT_0

TSTPT_1

TSTPT_2

HI-Z

30 MHz

0.7 to 22.5 MHz

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表7-9. Test Mode Selection Scenario Defined by TSTPT_(2:0) (continued)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT OUTPUT VALUE⁽¹⁾

TSTPT_(2:0) = 0b000

TSTPT_(2:0) = 0b010

TSTPT_3

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

HI-Z

HIGH

LOW

HIGH

7.5 MHz

(1) These are default output selections. Software can reprogram the selection at any time.

7.3.10 DMD Interface

The DLPC34xx controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface

and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.

7.3.10.1 Sub-LVDS (HS) Interface

The DLP3010LC (0.3 inch 720p) DMD does not require all of the available output data lanes of the controller.

Internal software selection allows the controller to support multiple DMD interface swap configurations. These

options can improve board layout by remapping specific combinations of DMD interface lines to other DMD

interface lines as needed. 表 7-10 shows the two options available for the DLP3010LC DMD. Leave any unused

DMD signal pairs unconnected on the final board design.

表7-10. DLP3010LC (0.3 inch 720p) DMD –ASIC to 8-Lane DMD Pin Mapping Options

DLPC3478 ASIC 8 LANE DMD ROUTING OPTIONS

DMD PINS

OPTION 1

OPTION 2

HS_WDATA_D_P

HS_WDATA_D_N

HS_WDATA_E_P

HS_WDATA_E_N

Input DATA_p_0

Input DATA_n_0

HS_WDATA_C_P

HS_WDATA_C_N

HS_WDATA_F_P

HS_WDATA_F_N

Input DATA_p_1

Input DATA_n_1

HS_WDATA_B_P

HS_WDATA_B_N

HS_WDATA_G_P

HS_WDATA_G_N

Input DATA_p_2

Input DATA_n_2

HS_WDATA_A_P

HS_WDATA_A_N

HS_WDATA_H_P

HS_WDATA_H_N

Input DATA_p_3

Input DATA_n_3

HS_WDATA_H_P

HS_WDATA_H_N

HS_WDATA_A_P

HS_WDATA_A_N

Input DATA_p_4

Input DATA_n_4

HS_WDATA_G_P

HS_WDATA_G_N

HS_WDATA_B_P

HS_WDATA_B_N

Input DATA_p_5

Input DATA_n_5

HS_WDATA_F_P

HS_WDATA_F_N

HS_WDATA_C_P

HS_WDATA_C_N

Input DATA_p_6

Input DATA_n_6

HS_WDATA_E_P

HS_WDATA_E_N

HS_WDATA_D_P

HS_WDATA_D_N

Input DATA_p_7

Input DATA_n_7

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High Speed sub-LVDS DDR Interface

DMD_HS_WDATA_A_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

(Example DMD)

DLP3010

1280 x 720 display

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

Sub-LVDS-DMD

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

DMD_LS_CLK

DMD_LS_WDATA

DMD_DEN_ARSTZ

DMD_LS_RDATA

Low Speed SDR Interface (120 MHz)

图7-23. DLP3010LC (.3 720p) DMD Interface Example

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and

Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both

waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).

Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements.

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7.4 Device Functional Modes

The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON

(GPIO_08).

• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the

DMD.

• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.

7.5 Programming

The DLPC34xx controller contains an Arm^®Cortex^®-M3 processor with additional functional blocks to enable

video processing and control. TI provides software as a firmware image. The customer is required to flash this

firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and

regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.

The available controller functions depend on the firmware version installed. Different firmware is required for

different chipset combinations (such as when using different PMIC devices). See Documentation Support at the

end of this document or contact TI to view or download the latest published software.

Users can modify software behavior through I²C interface commands. For a list of commands, view the software

user's guide accessible through the Documentation Support page.

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

DLPC3478 display and light controller with DLP3010LC DMD enables high accuracy and very small form factor

3D Depth sensing products. This section describes typical 3D depth sensor DLP systems using both external

and internal pattern streaming modes. The DMDs are spatial light modulators which reflect incoming light from

an illumination source to one of two directions, with the primary direction being into projection or collection

optics. The optical architecture of the system and the format of the image digital data coming into the DLPC3478

are what primarily determine the application requirements.

Typical applications include:

• Battery-powered, mobile accessory

– 3D Camera

– Tablets

– Smartphones

– Laptop

• Dental scanner (desktop or intra-oral)

• Robotics

• In-line automated inspection

• 3D biometrics: facial and finger print recognition

• Light exposure: 3D printers, programmable spatial and temporal light exposure

8.2 Typical Application

8.2.1 Pattern projector for 3D depth scanning

DLPC3478 controller with DLP3010LC DMD enables high accuracy and very small form factor 3D Depth

scanner products. 图 8-1 shows a typical 3D depth scanner system block diagram using external pattern

streaming mode.

1.1 V

1.1 Reg

L3

SYSPWR

L2

DC

Supplies

1.8 V

1.8 V external

L1

DLPA200x

VSPI

V

LED

1.8 V

PROJ_ON

LED_SEL (2)

PROJ_ON

I

SPI (4)

GPIO_8

SPI1

RESETZ

PARKZ

2

C

R

LIM

INTZ

Thermistor

Video

HOST_IRQ

DSI (10)

CMP_OUT

Front End

HDMI

VDDLP12

VDD

1.1 V

Illumination

optics

Parallel Interface (28)

DLPC3478

System

Controller

RC_

CHARGE

Flash

SPI (4)

SPI0

GPIO_10

Keypad

V

, V ,

BIAS OFFSET

TSTPT_4

GPIO_7

TRIG_OUT_1

TRIG_OUT_2

VCC_18

1.8 V

V

RESET

DMD

DLP3010LC

VCC_INTF

CTRL

Sub-LVDS DATA

TI DLP Chipset

Non-TI Device

VCC_FLSH

1.8 V

A. Options to elect different LEDs, but only 1 channel used at a time

图8-1. External Pattern Streaming Mode

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8.2.1.1 Design Requirements

A high accuracy 3D depth scanner product can be created by using a DLP chipset comprised of DLP3010LC

DMD, DLPC3478 controller and DLPA200x or DLPA300x PMIC/LED drive. The DLPC3478 simplifies the pattern

generation, the DLPA200x or DLPA300x provides the needed analog functions and DMD displays the required

patterns for accurate 3D depth scanning.

In addition to the three DLP devices in the chipset, other components may be required to complete the

application. Minimally, a flash component is required to store patterns, the software, and the firmware in order to

control the DLPC3478 controller.

DLPC3478 controller supports any illumination source including IR light source (LEDs or vertical-cavity surface-

emitting laser - VCSEL), UV light source, or visible light source (red, green or blue LEDs or lasers).

For connecting the DLPC3478 controller to the host processing for receiving patterns or video data, the parallel

interface is used. Connect an I²C interface to the host processor to send commands to the DLPC3478 controller.

The only required power supplies that are external to the projector system chipset are the battery (SYSPWR)

and possibly a regulated 1.8-V supply (some TI PMICs generate the 1.8-V supply but the DLPA200x does not).

The entire pico-projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is

high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and

draws just microamps of current on SYSPWR. If 1.8 V is supplied separately from the PMIC (as is the case with

the DLPA200x), when PROJ_ON is set low, the 1.8-V supply can continue to be left at 1.8 V and used by other

non-projector sections of the product.

8.2.1.2 Detailed Design Procedure

For connecting the DLP3010LC DMD, the DLPC3478 controller and the DLPA200x or DLPA300x PMIC/LED

driver see the reference design schematic. An example board layout is included in the reference design data

base. Follow the layout guidelines shown in 节10 to achieve reliable DLP system results.

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8.2.1.3 Application Curve

As the LED currents that are driven through the red, green or blue LEDs are increased, the brightness of the

projector increases. This increase is somewhat non-linear, and the curve for typical white screen lumens

changes with LED currents is shown in 图 8-2. For the LED currents shown, it is assumed that the same current

amplitude is applied to the red, green, and blue LEDs. For mono-chrome use case with a single LED or a

different light source, this curve will be different and the specific light source documentation needs to be referred

for similar information.

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

100

200

300 400

Current (mA)

500

600

700

D001

图8-2. Luminance vs Current

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8.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode

图8-3 shows a typical 3D depth scanner system block diagram using internal pattern streaming mode.

A. Options to elect different LEDs, but only 1 channel used at a time

图8-3. Internal Pattern Streaming Mode

8.2.2.1 Design Requirements

The design requirements for the 3D Depth scanner system using Internal Pattern Streaming Mode is identical to

the design procedure for the 3D Depth capture system External Pattern Streaming Mode. (See the 节 8.2.1.1

section.)

8.2.2.2 Detailed Design Procedure

The design procedure for the 3D Depth scanner Using Internal Pattern Streaming Mode is identical to the design

procedure for the 3D Depth scanner using External Pattern Streaming Mode. (See the 节8.2.1.2 section.)

8.2.2.3 Application Curve

See the 节 8.2.1.3 as the brightness considerations are similar in both external and internal pattern streaming

modes.

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9 Power Supply Recommendations

9.1 PLL Design Considerations

It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.

However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC34xx controller requires an array of power supply voltage pins (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, and VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is

assumed to be the typical configuration), then there are no restrictions regarding the relative order of power

supply sequencing to avoid damaging the DLPC34xx controller (this remains true for both power-up and power-

down scenarios). The controller requires no minimum delay time between powering-up and powering-down the

individual supplies if the VDDLP12 is tied to the 1.1-V VDD supply.

However, if the VDDLP12 pin is not tied to the VDD supply, then the VDDLP12 pin must be powered-on only

after the VDD supply is powered-on. And in a similar sequence, the VDDLP12 pin must be powered-off before

the VDD supply is powered-off. If the VDDLP12 pin is not tied to VDD, then the VDDLP12 pin and VDD supply

pins must be powered-on or powered-off within 100 ms of each other.

Although there is no risk of damaging the DLPC34xx controller when the above power sequencing rules are

followed, these additional power sequencing recommendations must be considered to ensure proper system

operation:

• To ensure that the DLPC34xx controller output signal states behave as expected, all controller I/O supplies

are encouraged to remain applied while VDD core power is applied. If VDD core power is removed while the

I/O supply (VCC_INTF) is applied, then the output signal states associated with the inactive I/O supply go to

a high impedance state.

• Because additional power sequencing rules may exist for devices that share the supplies with the DLPC34xx

controller (such as the PMIC and DMD), these devices may force additional system power sequencing

requirements.

图 9-1, 图 9-2, and 图 9-3 show the DLPC34xx power-up sequence, the normal PARK power-down sequence,

and the fast PARK power-down sequence of a typical DLPC34xx system.

When the VDD core power is applied, but I/O power is not applied, the controller may draw additional leakage

current. This leakage current does not affect the normal DLPC34xx controller operation or reliability.

Note

During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms

after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely

power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended

that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least

50 ms after PROJ_ON goes low.

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Signals

from PMIC (DLPA3000)

from other source

Pre-Initial-

ization

Power

System State

Startup

Initialization

Regular Operation

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

(a)

VDDLP12 (if not tied to VDD)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

(b)

(c)

(d)

PLL_REFCLK

HOST_IRQ

RESETZ

(e)

I²C (activity)

t1

t2

t3

t0

t0:

t1:

SYSPWR applied to the PMIC. All other voltage rails are derived from SYSPWR.

All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different

external supply.

t2:

Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.

HOST_IRQ goes low to indicate initialization is complete.

t3:

(a):

(b):

(c):

VDDLP12 must be powered on after VDD if it is supplied from a separate source.

PLL_REFCLK is allowed to be active before power is applied.

PLL_REFCLK must be stable within 5 ms of all power being applied. For external oscillator applications this is oscillator

dependent, and for crystal applications this is crystal and controller oscillator cell dependent.

(d):

(e):

PARKZ must be high before RESETZ releases to support auto-initialization. RESETZ must also be held low for at least 5 ms

after the power supplies are in specification.

I²C activity cannot start until HOST_IRQ goes low to indicate auto-initialization completes.

图9-1. System Power-Up Waveforms (With DLPA3000)

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Signals

from PMIC (DLPA3000)

from other source

Normal

Park

System State

Regular operation

Power supply shutdown

(b)

SYSPWR

(c)

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

VDDLP12

(if not tied to VDD)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

HOST_IRQ

RESETZ

(a)

I²C (activity)

t1

t2

t3

t4

t5

t1:

t2:

t3:

t4:

t5:

(a):

(b):

PROJ_ON goes low to begin the power down sequence.

The controller finishes parking the DMD.

RESETZ is asserted which causes HOST_IRQ to be pulled high.

All controller power supplies are turned off.

SYSPWR is removed now that all other supplies are turned off.

I²C activity must stop before PROJ_ON is deasserted (goes low).

The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and

VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is

deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore

recommended to follow note (c).

(c):

It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the

DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.

图9-2. Normal Park Power-Down Waveforms

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Signals

from PMIC (DLPA3000)

from other source

Fast

Park

(a)

System State

Regular operation

Power supplies collapse

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDD_PLLM/D (1.1 V)

VDDLP12

(if not tied to VDD)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

(b)

PARKZ

PLL_REFCLK

HOST_IRQ

RESETZ

I²C (activity)

t1

t3

t4

t2

t1:

A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to

initiate a fast park of the DMD.

t2:

t3:

t4:

(a):

The controller finishes the fast park procedure.

RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.

Eventually all power supplies that were derived from SYSPWR collapse.

VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within

specification for a minimum of 32 µs after PARKZ is asserted (goes low).

(b):

VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet.

Also see the DLPAxxxx datasheets for more information.

图9-3. Fast Park Power-Down Waveforms

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9.3 Power-Up Initialization Sequence

An external power monitor is required to hold the DLPC34xx controller in system reset during the power-up

sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller

voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The

external power monitoring is automatically done by the DLPAxxxx PMIC.

No signals output by the DLPC34xx controller will be in their active state while RESETZ is asserted. The

following signals are tri-stated while RESETZ is asserted:

• SPI0_CLK

• SPI0_DOUT

• SPI0_CSZ0

• SPI0_CSZ1

• GPIO [19:00]

Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be

configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the

PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.

Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after

RESETZ is set high.

The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power

is applied:

• LED_SEL_0

• LED_SEL_1

• DMD_DEN_ARSTZ

After power is stable and the PLL_REFCLK_I clock input to the DLPC34xx controller is stable, then RESETZ

should be deactivated (set to a logic high). The DLPC34xx controller then performs a power-up initialization

routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of

RESETZ, all DLPC34xx I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ

signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup

resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively

drives it high. Upon completion of the auto-initialization routine, the DLPC34xx controller will drive HOST_IRQ

low to indicate the initialization done state of the controller has been reached.

To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be

deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine

must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting

PROJ_ON).

Note

No I²C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.

9.4 DMD Fast Park Control (PARKZ)

PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages

drop below specifications. Typically, the PARKZ signal is provided by the DLPAxxxx interrupt output signal.

PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on

the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park

operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue

running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to

allow the park operation to complete.

Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host

processor (for example, when the external power source has been disconnected or the battery has dropped

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below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The

longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically

only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park

operation takes much longer than 32 µs to park the mirrors. During a Normal Park operation, the DLPAxxxx

keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.

Additionally, the DLPAxxxx may hold the supplies on for a period of time after the parking has been completed.

View the relevant DLPAxxxx datasheet for more information. The longer mirror parking time ensures the longest

DMD lifetime and reliability. The DMD Parking Switching Characteristics section specifies the park timings.

9.5 Hot Plug I/O Usage

The DLPC34xx controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).

This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the

controller does not load the input signal nor draw excessive current that could degrade controller reliability. For

example, the I²C bus from the host to other components is not affected by powering off VCC_INTF to the

DLPC34xx controller. The allows additional devices on the I²C bus to be utilized even if the controller is not

powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back

to the host.

If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input

buffer may experience added leakage current; however, the added leakage current does not damage the

DLPC34xx controller.

However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which

prevents communication on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin

for any system that has additional secondary devices on this bus.

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10 Layout

10.1 Layout Guidelines

For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for

TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the

use of 1-oz (or greater) copper planes to manage the controller package heat.

10.1.1 PLL Power Layout

Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The

DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,

VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground

pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the

spectrum of noise absorption). It’s recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all

four components as close to the controller as possible. It’s especially important to keep the leads of the high

frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and

VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.

Select ferrite beads with these characteristics:

• DC resistance less than 0.40 Ω

• Impedance at 10 MHz equal to or greater than 180 Ω

• Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both

capacitors and then through the series ferrites to the power source. Make the power and ground traces as short

as possible, parallel to each other, and as close as possible to each other.

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signal via

via to common analog digital board power plane

via to common analog digital board ground plane

PCB pad

Controller pad

1

2

3

4

5

A

Signal

VSS

Signal

F

VSS_

PLLM

G

Signal

VSS

Signal

Local

decoupling

for the PLL

digital

GND

FB

supply

PLL_

REF

CLK_I

VDD_

PLLM

VSS_

PLLD

H

1.1-V

Power

PLL_

REF

CLK_O

Crystal

Circuit

VDD_

PLLD

J

VSS

VDD

图10-1. PLL Filter Layout

10.1.2 Reference Clock Layout

The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or

oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200

ppm (including aging, temperature, and trim component variation).

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图10-2 shows the required discrete components when using a crystal.

PLL_REFCLK_I

PLL_REFCLK_O

R_FB

R_S

Crystal

C_L1

C_L2

C_L= Crystal load capacitance (farads)

C_L1= 2 × (C_L–Cstray_pll_refclk_i)

C_L2= 2 × (C_L–Cstray_pll_refclk_o)

where:

•

Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.

Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.

图10-2. Required Discrete Components

10.1.2.1 Recommended Crystal Oscillator Configuration

表10-1. Crystal Port Characteristics

PARAMETER

NOM

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

1.5

pF

表10-2. Recommended Crystal Configuration

PARAMETER ^{(1) (2)}

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

24

Crystal nominal frequency

MHz

PPM

ms

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

Crystal load

120 (max)

Ω

6

pF

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

100

1

Ω

MΩ

pF

See equation in 图10-2 notes

pF

A ground isolation ring around the

crystal is recommended

PCB layout

(1) Temperature range of –30°C to 85°C.

(2) The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx

controller, and the PLL_REFCLK_O pin must be left unconnected.

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表10-3. Recommended Crystal Parts

TEMPERATURE

AND AGING

(ppm)

LOAD

CAPACITANCE

(pF)

PACKAGE

DIMENSIONS

(mm)

MAXIMUM

MANUFACTURER

SPEED

(MHz)

PART NUMBER

(1) (2)

ESR (Ω)

KDS

DSX211G-24.000M-8pF-50-50

XRCGB24M000F0L11R0

24

±50

120

8

6

2.0 × 1.6

Murata

±100

NX2016SA 24M

NDK

24

±145

120

6

2.0 × 1.6

EXS00A-CS05733

(1) The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but

have not necessarily been validated by TI.

(2) Operating temperature range: –30°C to 85°C for all crystals.

10.1.3 Unused Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused

controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For

controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown

unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be

expected to drive an external device. The DLPC34xx controller implements very few internal resistors and are

listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown

resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8

kΩ.

Never tie unused output-only pins directly to power or ground. Leave them open.

When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that

the pin can remain open. If this control is not available and the pins may become an input, then include an

appropriate pullup (or pulldown) resistor.

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10.1.4 DMD Control and Sub-LVDS Signals

表10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations

SIGNAL INTERCONNECT TOPOLOGY

DMD BUS SIGNAL^{(1) (2)}

UNIT

SINGLE-BOARD SIGNAL

MULTI-BOARD SIGNAL

ROUTING LENGTH

DMD_HS_CLK_P

6.0

in

See ⁽³⁾

DMD_HS_CLK_N

(152.4)

(mm)

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

6.0

in

See ⁽³⁾

(152.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

6.5

in

DMD_LS_CLK

See ⁽³⁾

(165.1)

(mm)

6.5

in

DMD_LS_WDATA

DMD_LS_RDATA

(165.1)

(mm)

6.5

in

(165.1)

(mm)

7.0

in

DMD_DEN_ARSTZ

(177.8)

(mm)

(1) Maximum signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS

model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.

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表10-5. High Speed PCB Signal Routing Matching Requirements

SIGNAL GROUP LENGTH MATCHING^{(1) (2) (3)}

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH⁽⁴⁾

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_CLK_P

DMD_HS_CLK_N

±1.0

in

DMD⁽⁵⁾

(±25.4)

(mm)

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

±0.025

in

DMD

DMD_HS_WDATA_x_P

DMD_HS_CLK_P

DMD_HS_WDATA_x_N

DMD_HS_CLK_N

DMD_LS_CLK

N/A

(±0.635)

(mm)

±0.025

in

(±0.635)

(mm)

DMD_LS_WDATA

DMD_LS_RDATA

±0.2

in

(±5.08)

(mm)

in

DMD_DEN_ARSTZ

N/A

(mm)

(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx

controller or the DMD require no additional consideration.

(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data

lines.

(3) DMD LS signals are single ended.

(4) Mismatch variance for a signal group is always with respect to the reference signal.

(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.

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表10-6. Signal Requirements

PARAMETER

REFERENCE

REQUIREMENT

DMD_LS_WDATA

DMD_LS_CLK

Required

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Acceptable

Source series termination

Required

Not acceptable

68 Ω±10%

100 Ω±10%

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

Endpoint termination

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

DMD_LS_WDATA

DMD_LS_CLK

PCB impedance

SDR (single data rate) referenced to DMD_LS_DCLK

SDR referenced to DMD_LS_DCLK

DMD_DEN_ARSTZ

DMD_LS_RDATA

DMD_HS_WDATA_x_y

DMD_HS_CLK_y

SDR

Signal type

SDR referenced to DMD_LS_DLCK

sub-LVDS

10.1.5 Layer Changes

• Single-ended signals: Minimize the number of layer changes.

• Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the

signals of a given pair do not change layers.

10.1.6 Stubs

• Avoid using stubs.

10.1.7 Terminations

• DMD_HS differential signals require no external termination resistors.

• Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ωseries termination resistor

located as close as possible to the corresponding controller pins.

• Make sure the DMD_LS_RDATA signal path includes a 43-Ωseries termination resistor located as close as

possible to the corresponding DMD pin.

• The DMD_DEN_ARSTZ pin requires no series resistor.

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10.1.8 Routing Vias

• The number of vias on DMD_HS signals must be minimized and ideally not exceed two.

• Any and all vias on DMD_HS signals must be located as close to the controller as possible.

• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not

exceed two.

• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the

controller as possible.

10.1.9 Thermal Considerations

The underlying thermal limitation for the DLPC34xx controller is that the maximum operating junction

temperature (T_J) not be exceeded (this is defined in the Recommended Operating Conditions section).

Some factors that influence T_Jare as follows:

• operating ambient temperature

• airflow

• PCB design (including the component layout density and the amount of copper used)

• power dissipation of the DLPC34xx controller

• power dissipation of surrounding components

The controller package is designed to primarily extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

The recommends maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC34xx controller power dissipation and R_θJAat 0 m/s of forced airflow, where R_θJAis

the thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz

power planes. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB, so the

reported thermal resistance may not be accurate in the actual product application. Although the actual thermal

resistance may be different, it is the best information available during the design phase to estimate thermal

performance. TI highly recommended that thermal performance be measured and validated after the PCB is

designed and the application is built.

To evaluate the thermal performance, measure the top center case temperature under the worse case product

scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the

controller does not exceed the maximum recommended case temperature (T_C). This specification is based on

the measured φ_JTfor the DLPC34xx controller package and provides a relatively accurate correlation to junction

temperature.

Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI

recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that

they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally

conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead

through the wires.

68

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10.2 Layout Example

图10-3. Layout Recommendation

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

11.1.2.1 Device Markings

1

2

DLPC3478

SC

DLPC347xRXXX

XXXXXXXXXX-TT

LLLLLL.ZZZ

3

4

5

PH YYWW

Terminal A1 corner identifier

Marking Definitions:

Line 1:

DLP^®Device Name: DLPC3478 device name ID.

SC: Solder ball composition

e1: Indicates lead-free solder balls consisting of SnAgCu

G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content

less than or equal to 1.5% and that the mold compound meets TI's definition of green.

Line 2:

TI Part Number

DLP^®Device Name: DLPC347x = x indicates 8 device name ID.

R corresponds to the TI device revision letter for example A, B or C

XXX corresponds to the device package designator.

Line 3:

Line 4:

XXXXXXXXXX-TT Manufacturer part number

LLLLLL.ZZZ Foundry lot code for semiconductor wafers and lead-free solder ball marking

LLLLLL: Fab lot number

ZZZ: Lot split number

Line 5:

PH YYWW: Package assembly information

PH: Manufacturing site

YYWW: Date code (YY = Year :: WW = Week)

70

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Note

1. Engineering prototype samples are marked with an X suffix appended to the TI part number. For

example, 2512737-0001X.

2. See , for DLPC347x resolutions on the DMD supported per part number.

11.1.3 Video Timing Parameter Definitions

See 图11-1 for a visual description.

Active Lines Per Frame Defines the number of lines in a frame containing displayable data. ALPF is a

(ALPF)

Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data. APPL is a

(APPL) subset of the TPPL.

Horizontal Back Porch Defines the number of blank pixel clocks after the active edge of horizontal sync but

(HBP) Blanking before the first active pixel.

Horizontal Front Porch Defines the number of blank pixel clocks after the last active pixel but before

(HFP) Blanking horizontal sync.

Horizontal Sync (HS or Timing reference point that defines the start of each horizontal interval (line). The

subset of the TLPF.

Hsync)

active edge of the HS signal defines the absolute reference point. The active edge

(either rising or falling edge as defined by the source) is the reference from which all

horizontal blanking parameters are measured.

Total Lines Per Frame Total number of active and inactive lines per frame; defines the vertical period (or

(TLPF) frame time).

Total Pixel Per Line Total number of active and inactive pixel clocks per line; defines the horizontal line

(TPPL) period in pixel clocks.

Vertical Sync (VS or Timing reference point that defines the start of the vertical interval (frame). The

Vsync)

absolute reference point is defined by the active edge of the VS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all vertical blanking parameters are measured.

Vertical

Back

Porch Defines the number of blank lines after the active edge of vertical sync but before

(VBP) Blanking

the first active line.

Vertical Front Porch Defines the number of blank lines after the last active line but before the active edge

(VFP) Blanking

of vertical sync.

TPPL

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

ALPF

(HBP)

(HFP)

Vertical Front Porch (VFP)

图11-1. Parameter Definitions

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11.2 Documentation Support

11.2.1 Related Documentation

The following table lists quick access links for associated parts of the DLP chipset.

表11-1. Chipset Documentation

TECHNICAL

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TOOLS & SOFTWARE

DOCUMENTS

Click here

DLPA2000

DLPA2005

DLPA3000

DLPA3005

DLP3010LC

Click here

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

IntelliBright^™, ^™, Link^™are trademarks of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

^®, IntelliBright^®, and DLP^®are registered trademarks of Texas Instruments.

Arm^®and Cortex^®are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

72

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PACKAGE OUTLINE

ZEZ0201A

NFBGA - 1 mm max height

SCALE 1.000

PLASTIC BALL GRID ARRAY

13.1

12.9

A

B

BALL A1 CORNER

13.1

12.9

1 MAX

C

SEATING PLANE

0.1 C

0.31

0.21

BALL TYP

TYP

11.2 TYP

SYMM

(0.9) TYP

R

P

N

M

L

K

J

(0.9) TYP

SYMM

11.2

TYP

H

G

F

0.4

201X

E

D

C

0.3

0.15

0.08

C A

C

B

A

1

2

5 6

3 7 9 10 11 12 13 14 15

4

8

0.8 TYP

BALL A1 CORNER

4221521/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

201X ( 0.4)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221521/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ZEZ0201A

NFBGA - 1 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

3

4

5

6

8

9

13 14 15

7

10 11 12

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221521/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC3478CZEZ
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP3010 (0.3 720p) DMD 的 DLP® 显示和光控制器 \| ZEZ \| 201 \| -30 to 85 控制器商用集成电路
文件：	总78页 (文件大小：3315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC3478CZEZ [TI]

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