DLPC6401ZFF_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

DLPC6401 DLP^®数据处理器

1 特性

– 集成展频计时

•

集成 64Mb 帧存储器，无需使用外部高速存储器

1

•

提供一个 30 位输入像素接口：

外部存储器支持：针对微处理器和 PWM 序列的并

行闪存

–

YUV，YCrCb 或 RGB 数据格式

每个色彩 8，9 或 10 位

•

系统控制：

像素时钟支持高达 150MHz

–

DMD 电源和复位驱动器控制

DMD 水平和垂直显示图像抖动

•

提供一个单通道、基于低压差分信令 (LVDS) 且

兼容平板显示 (FPD)-Link 的输入接口：

•

支持边界扫描测试的 JTAG

–

支持有效像素时钟速率高达 90MHz 的输入源

419 引脚塑料球状引脚栅格阵列封装

支持四种经解调的像素映射模式，适用于 8、

9、10 路 YUV、YCrCb 或 RGB 格式的输入

2 应用

•

支持 45Hz 至 120Hz 的帧速率

完全支持 Diamond 0.45 WXGA

•

电池供电的移动式附件高清 (HD) 投影仪

电池供电的智能 HD 附件

无屏幕显示 – 交互式显示器

移动电影院

高速、双倍数据速率 (DDR) 数字微镜器件 (DMD)

接口

•

149.33MHz ARM926™微处理器

游戏显示

微处理器外设：

–

可编程脉宽调制 (PWM) 和捕捉定时器

两个 I²C 端口

3 说明

DLPC6401 数字控制器属于 DLP4500 (0.45 WXGA)

芯片组，用于支持 DLP4500 数字微镜器件 (DMD) 的

可靠运行。DLPC6401 控制器在系统电子设备与 DMD

之间提供一个方便的多功能接口，从而实现了小外形尺

寸的高分辨率 HD 显示屏。

两个通用异步收发器 (UART) 端口（只用于调

试）

–

32KB 内部随机存取存储器 (RAM)

专用发光二级管 (LED) PWM 发生器

•

图像处理：

–

针对标准、宽和黑边缘的自动锁

器件信息 ⁽¹⁾

1D 梯形失真校正

部件号

DLPC6401

封装

阵列尺寸（像素）

可编程后期色彩校正 (Degamma)

BGA (419)

23.00mm x 23.00mm

•

屏幕显示 (OSD)

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

初始屏幕显示支持

集成型时钟生成电路

–

运行在单个 32MHz 晶振上

典型应用图

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: DLPS031

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Switching Characteristics......................................... 18

Detailed Description ............................................ 22

7.1 Overview ................................................................. 22

7.2 Functional Block Diagram ....................................... 22

7.3 Feature Description................................................. 23

7.4 Device Functional Modes........................................ 28

Application and Implementation ........................ 29

8.1 Application Information............................................ 29

8.2 Typical Application ................................................. 29

Power Supply Recommendations...................... 32

9.1 System Power Regulation ...................................... 32

9.2 System Power-Up Sequence.................................. 32

9.3 Power-On Sense (POSENSE) Support .................. 33

9.4 System Environment and Defaults.......................... 33

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications....................................................... 11

6.1 Absolute Maximum Ratings .................................... 11

6.2 ESD Ratings............................................................ 11

6.3 Recommended Operating Conditions..................... 12

6.4 Thermal Information................................................ 12

6.5 Electrical Characteristics......................................... 13

6.6 Electrical Characteristics (Normal Mode)................ 14

6.7 System Oscillators Timing Requirements............... 14

6.8 Test and Reset Timing Requirements .................... 15

7

8

9

10 Layout................................................................... 35

10.1 Layout Guidelines ................................................. 35

10.2 Layout Example .................................................... 41

10.3 Thermal Considerations........................................ 42

11 器件和文档支持 ..................................................... 44

11.1 器件支持................................................................ 44

11.2 社区资源................................................................ 46

11.3 商标....................................................................... 46

11.4 静电放电警告......................................................... 46

11.5 Glossary................................................................ 46

12 机械、封装和可订购信息....................................... 46

6.9 JTAG Interface: I/O Boundary Scan Application

Timing Requirements............................................... 15

6.10 Port 1 Input Pixel Interface Timing Requirements 16

6.11 Port 2 Input Pixel Interface (FPD-Link Compatible

LVDS Input) Timing Requirements .......................... 16

6.12 Synchronous Serial Port (SSP) Interface Timing

Requirements........................................................... 17

6.13 Programmable Output Clocks Switching

Characteristics ......................................................... 17

6.14 Synchronous Serial Port (SSP) Interface Switching

Characteristics ......................................................... 18

6.15 JTAG Interface: I/O Boundary Scan Application

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (June 2015) to Revision C

Page

•

已更新器件标记图。 ............................................................................................................................................................. 45

Changes from Revision A (January 2014) to Revision B

Page

•

已添加 ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文

档支持部分以及机械、封装和可订购信息部分 ....................................................................................................................... 1

Removed V_(ESD)values from Electrical Characteristics table .............................................................................................. 13

Changes from Original (December 2013) to Revision A

Page

•

已删除产品预览条................................................................................................................................................................... 1

2

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

5 Pin Configuration and Functions

ZFF PACKAGE

419-PIN BGA

TOP VIEW

3

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Pin Functions

(2)

PIN⁽¹⁾

NAME

CONTROL

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NO.

POWER

TYPE

External reset output, LOW true. This output is

asserted low immediately upon asserting power-up

reset (POSENSE) low and remains low while

POSENSE remains low. EXT_ARSTZ continues to

be held low after the release of power-up reset (that

is, POSENSE set high) until released by software.

EXT_ARSTZ is also asserted low approximately 5

µs after the detection of a PWRGOOD or any

internally-generated reset. In all cases, it remains

active for a minimum of 2 ms after the reset

condition is released by software. Note, the ASIC

contains a software register that can be used to

independently drive this output.

EXT_ARST

H20

VDD33

O₁

Async

Power Good is an active-high signal with hysteresis

that is generated by an external power supply or

voltage monitor. A high value indicates all power is

within operating voltage specifications and the

system is safe to exit its reset state. A transition from

high to low should indicate that the controller or

DMD supply voltage will drop below their rated

minimum level within the next 0.5 ms (POSENSE

must remain active high during this interval). This is

an early warning of an imminent power loss

condition. This warning is required to enhance long-

term DMD reliability. A DMD park sequence,

followed by a full controller reset, is performed by the

DLPC6401 when PWRGOOD goes low for a

minimum of 4 µs protecting the DMD. This minimum

de-assertion time is used to protect the input from

glitches. Following this, the DLPC6401 is held in its

reset state as long as PWRGOOD is low.

I₄

H

PWRGOOD

H19

VDDC

Async

PWRGOOD must be driven high for typical

operation. The DLPC6401 device acknowledges

PWRGOOD as active after it is driven high for a

minimum of 625 ns. Uses hysteresis.

Power-On Sense is an active-high input signal with

hysteresis that is generated by an external voltage

monitor circuit. POSENSE must be driven inactive

(low) when any of the controller supply voltages are

below minimum operating voltage specifications.

POSENSE must be active (high) when all controller

supply voltages remain above minimum

I₄

H

POSENSE

G21

Async

specifications.

Power On or Power Off is an active-high signal that

indicates the power of the system. Power On or

Power Off is high when the system is in power-up

state, and low when the system is in standby. Power

On or Power Off can also be used to power on or off

an external power supply.

POWER_ON_OFF N21

VDD33

B₂

Async

Prior to transferring part of code from parallel flash

content to internal memory, the internal memory is

initialized and a memory test is performed. The

result of this test (pass or fail) is recorded in the

system status. If memory test fails, the initialization

process is halted. INIT_DONE is asserted twice to

indicate an error situation. See Figure 12.

INIT_DONE

F19

B₂

This signal is sampled during power-up. If the signal

is low, the I²C addresses are 0x34 and 0x35. If the

signal is low, the I²C are 0x3A and 0x3B.

I2C_ADDR_SEL

I2C1_SCL

F21

J3

VDD33

B₂

Async

N/A

Requires an external pullup to

3.3 V. The minimum

acceptable pullup value is

1 kΩ.

I²C clock. Bidirectional, open-drain signal. I²C slave

clock input from the external processor. This bus

supports 400 kHz.

Requires an external pullup to

3.3 V. The minimum

acceptable pullup value is

1 kΩ.

I²C data. Bidirectional, open-drain signal. I²C slave

to accept command or transfer data to and from the

external processor. This bus supports 400 kHz.

I2C1_SDA

J4

VDD33

B₂

I2C1_SCL

(1) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

(2) I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 1 for subscript explanation.

4

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Pin Functions (continued)

(2)

PIN⁽¹⁾

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

Requires an external pullup to

3.3 V. The minimum

acceptable pullup value is 1

kΩ. This input is not

I²C bus 0, clock; I²C master for on-board peripherals

such as temperature sensor. This bus supports 400-

kHz, fast-mode operation.

I2C0_SCL

I2C0_SDA

M2

VDD33

B₈

N/A

5-V tolerant.

Requires an external pullup to

3.3 V. The minimum

acceptable pullup value is 1

kΩ. This input is not

I²C bus 0, data; I²C master for on-board peripherals

such as temperature sensor. This bus supports 400-

kHz, fast-mode operation.

M3

B₈

I2C0_SCL

5-V tolerant.

SYSTEM CLOCK

MOSC

System clock oscillator input (3.3-V LVCMOS). Note

that the MOSC must be stable a maximum of 25 ms

after POSENSE transitions from high to low.

A14

A15

VDD33

I₁₀

N/A

MOSCN

O₁₀

MOSC crystal return

PORT 1: PARALLEL VIDEO AND GRAPHICS INPUT^(3)(4)(5)

P1A_CLK

P1B_CLK

P1C_CLK

W15

AB17

Y16

VDD33

I₄

Includes an internal pulldown

N/A

Port 1 input data pixel write clock 'A'

Port 1 input data pixel write clock 'B'

Port 1 input data pixel write clock 'C'

B₁

H

P1_VSYNC

Y15

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 vertical sync. Uses hysteresis

B₁

H

P1_HSYNC

P1_DATEN

P1_FIELD

AB16

AA16

W14

VDD33

Includes an internal pulldown

P1A_CLK

Port 1 horizontal sync. Uses hysteresis

Port 1 data enable

I₄

Port 1 field sync. Required for interlaced sources

only (and not progressive)

P1_A_9

P1_A_8

P1_A_7

P1_A_6

P1_A_5

P1_A_4

P1_A_3

P1_A_2

P1_A_1

P1_A_0

P1_B_9

P1_B_8

P1_B_7

P1_B_6

P1_B_5

P1_B_4

P1_B_3

P1_B_2

P1_B_1

P1_B_0

P1_C_9

P1_C_8

AB20

AA19

Y18

VDD33

I₄

Includes an internal pulldown

P1A_CLK

Port 1 A channel input pixel data (bit weight 128)

Port 1 A channel input pixel data (bit weight 64)

Port 1 A channel input pixel data (bit weight 32)

Port 1 A channel input pixel data (bit weight 16)

Port 1 A channel input pixel data (bit weight 8)

Port 1 A channel input pixel data (bit weight 4)

Port 1 A channel input pixel data (bit weight 2)

Port 1 A channel input pixel data (bit weight 1)

Port 1 A channel input pixel data (bit weight 0.5)

Port 1 A channel input pixel data (bit weight 0.25)

Port 1 B channel input pixel data (bit weight 128)

Port 1 B channel input pixel data (bit weight 64)

Port 1 B channel input pixel data (bit weight 32)

Port 1 B channel input pixel data (bit weight 16)

Port 1 B channel input pixel data (bit weight 8)

Port 1 B channel input pixel data (bit weight 4)

Port 1 B channel input pixel data (bit weight 2)

Port 1 B channel input pixel data (bit weight 1)

Port 1 B channel input pixel data (bit weight 0.5)

Port 1 B channel input pixel data (bit weight 0.25)

Port 1 C channel input pixel data (bit weight 128)

Port 1 C channel input pixel data (bit weight 64)

W17

AB19

AA18

Y17

AB18

W16

AA17

U21

U20

V22

U19

V21

W22

W21

AA20

Y19

W18

P21

P22

(3) Port 1 can be used to support multiple source options for a given product (that is, HDMI, BT656). To do so, the data bus from both

source components must be connected to the same port 1 pins and control given to the DLPC6401 to tri-state the inactive source. Tying

them together like this causes some signal degradation due to reflections on the tri-stated path.

(4) The A, B, and C input data channels of port 1 can be internally swapped for optimum board layout.

(5) Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC6401 and

LSBs tied off to 0. For example, an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B, or C input channel.

BT656 are 8 or 10 bits in width. If a BT656-type input is used, the data bits must be MSB justified as with the other types of input

sources on either of the A, B, or C data input channels.

5

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Pin Functions (continued)

(2)

PIN⁽¹⁾

NAME

P1_C_7

I/O

POWER

VDD33

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NO.

R19

R20

R21

R22

T21

T20

T19

U22

TYPE

I₄

Includes an internal pulldown

P1A_CLK

Port 1 C channel input pixel data (bit weight 32)

Port 1 C channel input pixel data (bit weight 16)

Port 1 C channel input pixel data (bit weight 8)

Port 1 C channel input pixel data (bit weight 4)

Port 1 C channel input pixel data (bit weight 2)

Port 1 C channel input pixel data (bit weight 1)

Port 1 C channel input pixel data (bit weight 0.5)

Port 1 C channel input pixel data (bit weight 0.25)

P1_C_6

P1_C_5

P1_C_4

P1_C_3

P1_C_2

P1_C_1

P1_C_0

PORT 2: FPD-LINK COMPATIBLE VIDEO AND GRAPHICS INPUT⁽⁶⁾

Includes weak internal

pulldown

Positive differential input signal for clock, FPD-Link

receiver

RCK_IN_P

RCK_IN_N

RA_IN_P

RA_IN_N

RB_IN_P

RB_IN_N

RC_IN_P

RC_IN_N

RD_IN_P

RD_IN_N

RE_IN_P

RE_IN_N

Y9

VDD33_FPD

I₅

N/A

Includes weak internal

pulldown

Negative differential input signal for clock, FPD-Link

receiver

W9

N/A

Includes weak internal

pulldown

Positive differential input signal for data channel A,

FPD-Link receiver

AB10 VDD33_FPD

AA10 VDD33_FPD

RCK_IN

Includes weak internal

pulldown

Negative differential input signal for data channel A,

FPD-Link receiver

Includes weak internal

pulldown

Positive differential input signal for data channel B,

FPD-Link receiver

Y11

VDD33_FPD

Includes weak internal

pulldown

Negative differential input signal for data channel B,

FPD-Link receiver

W11 VDD33_FPD

AB12 VDD33_FPD

AA12 VDD33_FPD

Includes weak internal

pulldown

Positive differential input signal for data channel C,

FPD-Link receiver

Includes weak internal

pulldown

Negative differential input signal for data channel C,

FPD-Link receiver

Includes weak internal

pulldown

Positive differential input signal for data channel D,

FPD-Link receiver

Y13

VDD33_FPD

Includes weak internal

pulldown

Negative differential input signal for data channel D,

FPD-Link receiver

W13 VDD33_FPD

AB14 VDD33_FPD

AA14 VDD33_FPD

Includes weak internal

pulldown

Positive differential input signal for data channel E,

FPD-Link receiver

Includes weak internal

pulldown

Negative differential input signal for data channel E,

FPD-Link receiver

(6) Port 2 is a single-channel FPD-Link compatible input interface. FPD-Link is a defacto industry standard FPD interface, which uses the

high-bandwidth capabilities of LVDS signaling to serialize video and graphics data down to a couple wires to provide a low-wire count

and low-EMI interface. Port 2 supports source rates up to a maximum effective clock of 90 MHz. The port 2 input pixel data must adhere

to one of four supported data mapping formats (see Table 2). Given that port 2 inputs contain weak pulldown resistors, they can be left

floating when not used.

6

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Pin Functions (continued)

(2)

PIN⁽¹⁾

NAME

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NO.

POWER

TYPE

DMD INTERFACE

DMD_D0

A8

B8

DMD_D1

DMD_D2

C8

DMD_D3

D8

DMD_D4

B11

C11

D11

E11

C7

DMD_D5

DMD_D6

DMD_D7

DMD_D8

DMD_D9

B10

E7

DMD_D10

DMD data pins. DMD data pins are DDR signals that

are clocked on both edges of DMD_DCLK.

All 24 DMD data signals are use to interface to the

DLP4500.

DMD_D11

D10

VDD_DMD

O₇

DMD_DCLK

DMD_D12

A6

A12

B12

C12

D12

B7

DMD_D13

DMD_D14

DMD_D15

DMD_D16

DMD_D17

DMD_D18

A10

D7

DMD_D19

DMD_D20

B6

DMD_D21

E9

DMD_D22

C10

C6

DMD_D23

DMD_DCLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

DMD_DRC_BUS

DMD_DRC_STRB

A9

VDD_DMD

O₇

N/A

DMD data clock (DDR)

B9

DMD_DCLK

DMD data load signal (active-low)

DMD data serial control signal

DMD data toggle rate control

C9

D9

D5

DMD_SAC_CLK DMD reset control bus data

DMD_SAC_CLK DMD reset control bus strobe

C5

Requires a 30 to 51-kΩ

external pullup resistor to

VDD_DMD.

DMD_DRC_OE

B5

VDD_DMD

O₇

Async

DMD reset control enable (active low)

DMD_SAC_BUS

DMD_SAC_CLK

D6

A5

VDD_DMD

O7

O₇

DMD_SAC_CLK DMD stepped-address control bus data

N/A

DMD stepped-address control bus clock

DMD Power Enable control. This signal indicates to

an external regulator that the DMD is powered.

DMD_PWR_EN

EXRES

G20

A3

VDD_DMD

O₂

O

Async

DMD drive strength adjustment precision reference.

A ±1% external precision resistor should be

connected to this pin.

Async

FLASH INTERFACE

PM_CS_0

Reserved for future use. On the PCB, connect to

VDD33 through a pullup resistor.

U3

U2

U1

VDD33

O₂

Async

PM_CS_1

Boot flash (active low). Required for boot memory

Reserved for future use. On the PCB, connect to

VDD33 through a pullup resistor.

PM_CS_2

7

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Pin Functions (continued)

(2)

PIN⁽¹⁾

NAME

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NO.

V3

POWER

TYPE

PM_ADDR_22

PM_ADDR_21

PM_ADDR_20

PM_ADDR_19

PM_ADDR_18

PM_ADDR_17

PM_ADDR_16

PM_ADDR_15

PM_ADDR_14

PM_ADDR_13

PM_ADDR_12

PM_ADDR_11

PM_ADDR_10

PM_ADDR_9

PM_ADDR_8

PM_ADDR_7

PM_ADDR_6

PM_ADDR_5

PM_ADDR_4

PM_ADDR_3

PM_ADDR_2

PM_ADDR_1

PM_ADDR_0

PM_WE

B₂

W1

W2

Y1

AB2

AA3

Y4

W5

AB3

AA4

Y5

W6

AB4

AA5

Y6

VDD33

O₂

Async

Flash memory address bit

W7

AB5

AA6

Y7

AB6

W8

AA7

AB7

V2

VDD33

O₂

Async

Write enable (active low)

Output enable (active low)

Upper byte(15:8) enable

Lower byte(7:0) enable

PM_OE

U4

PM_BLS_1

AA8

AB8

M1

N1

PM_BLS_0

PM_DATA_15

PM_DATA_14

PM_DATA_13

PM_DATA_12

PM_DATA_11

PM_DATA_10

PM_DATA_9

PM_DATA_8

PM_DATA_7

PM_DATA_6

PM_DATA_5

PM_DATA_4

PM_DATA_3

PM_DATA_2

PM_DATA_1

PM_DATA_0

N2

N3

VDD33

B₂

Async

Data bits, upper byte

N4

P1

P2

P3

P4

R2

R3

R4

VDD33

B₂

Async

Data bits, lower byte

T1

T2

T3

T4

LED DRIVER INTERFACE

LEDR_PWM

LEDG_PWM

LEDB_PWM

LEDR_EN

K2

K3

K4

L3

L4

K1

LED red PWM output enable control

VDD33

O₂

Async

LED green PWM output enable control

LED blue PWM output enable control

LED red PWM output

LEDG_EN

LED green PWM output

LEDB_EN

LED blue PWM output

8

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Pin Functions (continued)

(2)

PIN⁽¹⁾

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

PERIPHERAL INTERFACE

UART_TXD

UART_RXD

L19

L21

VDD33

O₂

I₄

Async

Transmit data output. Reserved for debug messages

Receive data input. Reserved for debug messages

Ready to send hardware flow control output.

Reserved for debug messages

UART_RTS

UART_CTS

M19

L20

VDD33

O₂

I₄

Async

Clear to send hardware flow control input. Reserved

for debug messages

VDD33

(7)

GENERAL PURPOSE I/O (GPIO)

GPIO_37

GPIO_36

GPIO_35

GPIO_34

GPIO_33

GPIO_32

GPIO_31

GPIO_29

GPIO_28

GPIO_27

GPIO_25

GPIO_24

GPIO_23

GPIO_21

GPIO_20

GPIO_19

GPIO_18

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

GPIO_06

GPIO_05

GPIO_04

GPIO_03

GPIO_02

GPIO_00

K21

G1

VDD33

B₂

Async

None

H4

H3

H2

F22

G19

F20

E22

E21

D22

E20

D21

N20

N19

D18

C18

B19

B18

L2

M4

A19

C17

A18

D16

C16

B16

A17

C15

OTHER INTERFACES

Feedback from fan to indicate fan is connected and

running

FAN_LOCKED

FAN_PWM

B17

D15

VDD33

B₂

Async

Fan PWM speed control

BOARD LEVEL TEST AND DEBUG

TDI

P18

R18

V15

L18

VDD33

I₄

Includes internal pullup

TCK

N/A

JTAG serial data in⁽⁸⁾

JTAG serial data clock⁽⁸⁾

JTAG test mode select⁽⁸⁾

JTAG serial data out⁽⁸⁾

TCK

TMS1

TDO1

I₄

TCK

O₁

(7) GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate use

modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate

function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external pullup

to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure

stable operation before software is able to configure these ports.

(8) All JTAG signals are LVCMOS-compatible.

9

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Pin Functions (continued)

(2)

PIN⁽¹⁾

NAME

I/O

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NO.

POWER

TYPE

JTAG, RESET (active low). This pin should be pulled

high (or left unconnected) when the JTAG interface

is in use for boundary scan. Connect this pin to

ground otherwise. Failure to tie this pin low during

normal operation causes startup and initialization

problems.⁽⁸⁾

I₄

H

TRST

RTCK

V17

VDD33

Includes internal pullup

Async

G18

V6

VDD33

O₂

N/A

JTAG return clock⁽⁹⁾

Includes internal pull down.

External pulldown

recommended for added

protection.

I₄

H

IC Tri-State Enable (active high). Asserting high tri-

states all outputs except the JTAG interface.

ICTSEN

Async

(9) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

Functional Pin Descriptions (Reserved Pins)

(2)

PIN⁽¹⁾

I/O

CLK

INTERNAL TERMINATION

DESCRIPTION

SYSTEM

NAME

NO.

POWER

TYPE

I₄

H

RESERVED

V7

VDD33

Includes internal pulldown

N/A

Connect directly to ground on the PCB.

N22, M22,

P19, P20

I₄

Includes an internal pulldown

Includes an internal pullup

Reserved⁽¹⁾

RESERVED

V16

VDD33

I₄

N/A

D1, J2

F1, F2, G2,

G3, G4

RESERVED

VDD33

O₂

O₁

Includes internal pulldown

N/A

F3, J1, M21

Leave these pins unconnected⁽¹⁾

H20, M18,

M20

H21, H22,

J19, J20,

J21, J22,

K19, K20

RESERVED

VDD33

B₂

Includes internal pulldown

N/A

Reserved⁽¹⁾

Reserved

RESERVED

C1, D2, F4

E3, E2

VDD33

B₂

—

N/A

Async

(1) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

(2) I/O Type: I indicates input, O indicates output, B indicates bidirectional, and H indicates hysteresis. See Table 1 for subscript

explanation.

Table 1. I/O Type Subscript Definition

I/O

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

3.3-V LVCMOS I/O buffer, with 4-mA drive

3.3-V LVCMOS I/O buffer, with 8-mA drive

3.3-V LVCMOS I/O buffer, with 12-mA drive

3.3-V LVCMOS receiver

1

2

ESD diode to VDD33 and GND

N/A

3

4

5

3.3-V LVDS receiver (FPD-Link I/F)

None

6

7

1.9-V LPDDR output buffer (DMD I/F)

3.3-V I²C with 12-mA sink

ESD diode to VDD_DMD and GND

ESD diode to VDD33 and GND

8

10

OSC 3.3-V I/O compatible LVCMOS

10

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

6 Specifications

6.1 Absolute Maximum Ratings

over recommended operating free-air temperature (unless otherwise noted)

(1)

MIN

MAX

UNIT

ELECTRICAL

VDDC (core 1.2-V power)

VDD33 (CMOS I/O)

–0.5

–0.3

–0.5

–0.3

–0.5

1.7

3.8

2.3

1.7

3.8

1.7

2.3

3.6

2.0

3.6

VDD_DMD (DMD driver power)

VDD12_FPD (FPD-Link LVDS interface 1.2-V power)

VDD33_FPD (FPD-Link LVDS interface 3.3-V power)

VDD12_PLLD (DDR clock generator – digital)

VDD12_PLLM (master clock generator – digital)

VDD_18_PLLD (DDR clock generator – analog)

VDD_18_PLLM (master clock generator – analog)

OSC (BC1850)

Supply voltage⁽²⁾

V

LVCMOS (BT3350)

I²C (BT3350)

V_I

Input voltage⁽³⁾

Output voltage

LVDS (BT3350)

DMD LPDDR (BC1850)

V_O

LVCMOS (BT3350)

I²C (BT3350)

ENVIRONMENTAL

T_J

Operating junction temperature

Storage temperature

0

115

125

°C

T_stg

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Applies to external input and bidirectional buffers.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

Electrostatic

discharge

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

V_(ESD)

±500

±150

V

Machine model (MM)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

11

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

I/O⁽¹⁾

MIN

3.135

1.8

1.71

1.116

0

NOM

3.3

1.9

1.8

1.2

MAX

UNIT

V

VDD33

3.3-V supply voltage, I/O

1.9-V supply voltage, I/O

3.465

2

VDD_DMD

V

VDD_18_PLLD 1.8-V supply voltage, PLL analog

VDD_18_PLLM 1.8-V supply voltage, PLL analog

1.89

V

1.89

V

VDD12

1.2-V supply voltage, core logic

1.2-V supply voltage, PLL digital

1.26

V

VDD12_PLLD

VDD12_PLLM

1.26

V

1.26

V

OSC (10)

VDD33

2.2

3.3-V LVCMOS (1, 2, 3, 4)

3.3-V I²C (8)

0

V_I

Input voltage

V

0

3.3-V LVDS (5)

0.6

0

3.3-V LVCMOS (1, 2, 3, 4)

3.3-V I²C (8)

VDD33

VDD_DMD

55

V_O

Output voltage

0

V

1.9-V LPDDR (7)

0

(2)

T_A

T_C

T_J

Operating ambient temperature range

Operating top-center case temperature

Operating junction temperature

See

0

°C

(3)(4)

See

0

104

0

105

(1) The number inside each parenthesis for the I/O refers to the type defined in the I/O type subscript definition section.

(2) Assumes a minimum 1-m/s airflow along with the JEDEC thermal resistance and associated conditions as listed www.ti.com/packaging.

Thus, this is an approximate value that varies with environment and PCB design.

(3) Maximum thermal values assume maximum power of 3 W.

(4) Assume ψ_JTequals 0.33 C/W.

6.4 Thermal Information⁽¹⁾

DLPC6401

THERMAL METRIC⁽¹⁾

ZFF (BGA)

419 PINS

0.33

UNIT

ψ_JT

Junction-to-top characterization parameter

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application

Report, SPRA953.

12

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

6.5 Electrical Characteristics⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2

TYP

MAX UNIT

OSC (10)

High-level input

threshold voltage

3.3-V LVCMOS (1, 2, 3, 4)

3.3-V I²C (8)

2

V_IH

V

2.4

OSC (10)

0.8

Low-level input

threshold voltage

3.3-V LVCMOS (1, 2, 3, 4)

3.3-V I²C (8)

0.8

1

V_IL

V

Receiver input

impedance

RI

3.3-V LVDS (5)

VDDH = 3.3 V

90

–200

200

0.7

110

132

200

600

2.1

Ω

Input differential

threshold

Vidth

|Vid|

mV

Absolute input

differential voltage

At minimum absolute

input differential voltage

Input common mode

voltage range

VICM

V

At max absolute input

differential voltage

0.9

1.9

3.3-V LVCMOS (1, 2, 3, 4)

3.3-V I²C (8)

400

550

VHYS

V_OH

Hysteresis (VT+ – VT–)

mV

V

3.3-V LVCMOS (1, 2, 3)

1.9-V DMD LPDDR (7)

3.3-V LVCMOS (1, 2, 3)

3.3-V I²C (8)

I_OH= Max rated

I_OH= –0.1 mA

I_OL= 0.1 mA

2.8

High-level output

voltage

0.9 × VDD_DMD

0.1 × VDD_DMD

Low-level output

voltage

I_OL= Max rated

I_OL= 3-mA sink

0.4

V_OL

V

OSC (10)

10.0

3.3-V LVCMOS (1 to 4) (without

internal pulldown)

V_IH= VDD33

10

I_IH

High-level input current

µA

3.3 V LVCMOS (1 to 4) (with

internal pulldown)

V_IH= VDD33

200

3.3 V I²C (8)

OSC (10)

10

–10.0

3.3-V LVCMOS (1 to 4) (without

internal pullup)

V_OH= VDD33

–10

I_IL

Low-level input current

µA

3.3-V LVCMOS (1 to 4) (with

internal pullup)

–200

–10

3.3-V I²C (8)

V_OH= VDD33

V_O= 1.5 V

V_O= 2.4 V

V_O= 0.4 V

1.9-V DMD LPDDR (7)

3.3-V LVCMOS (1)

3.3-V LVCMOS (2)

3.3-V LVCMOS (3)

1.9-V DMD LPDDR (7)

3.3-V LVCMOS (1)

3.3-V LVCMOS (2)

3.3-V LVCMOS (3)

3.3-V I²C (8)

–4

–8

–12

4

High-level output

current

I_OH

mA

4

Low-level output

current

8

I_OL

12

3

3.3-V LVCMOS (1, 2, 3)

3.3-V I²C (8)

–10

2.8

2.7

3

10

4

High-impedance

leakage current

I_OZ

µA

pF

3.3-V LVCMOS (2)

3.3-V LVCMOS (4)

3.3-V I²C (8)

3.3

3.4

3.2

Input capacitance

(including package)

4.2

3.5

C_I

(1) The number inside each parenthesis for the I/O refers to the type defined in Table 1.

13

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

6.6 Electrical Characteristics (Normal Mode)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITION⁽¹⁾

Normal mode

MIN

TYP

600

30

MAX⁽²⁾UNIT

I_CC12

Supply voltage, 1.2-V core power

1020

50

mA

Supply voltage, 1.9-V I/O power (DMD LPDDR)

Supply voltage, 3.3-V (I/O) power

ICC19_DMD

I_CC33

40

70

I_{CC12_FPD}

I_{CC33_FPD}

I_{CC12_PLLD}

FPD-Link LVDS I/F supply voltage, 1.2-V power

FPD-Link LVDS I/F supply voltage, 3.3-V power

Supply voltage, PLL digital power (1.2 V)

60

100

85

50

9

15

Supply voltage, master clock generator PLL digital

power (1.2 V)

I_{CC12_PLLM}

I_{CC18_PLLD}

I_{CC18_PLLM}

P_TOT

Normal mode

9

10

15

16

mA

mW

Supply voltage, PLL analog power (1.8 V)

Supply voltage, master clock generator PLL analog

power (1.8 V)

10

16

Total power

1225

2200

(1) Normal mode refers to ASIC operation during full functionality, active product operation. Typical values correspond to power dissipated

on nominal process devices operating at nominal voltage and 70°C junction temperature (approximately 25°C ambient) displaying typical

video-graphics content from a high-frequency source. Maximim values correspond to power dissipated on fast process devices

operating at high voltage and 105°C junction temperature (approximately 55°C ambient) displaying typical video-graphics content from a

high-frequency source. The increased power dissipation observed on fast process devices operated at maximum recommended

temperature is primarily a result of increased leakage current.

(2) Maximum power values are estimates and may not reflect the actual final power consumption of DLPC6401 ASIC.

6.7 System Oscillators Timing Requirements

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

ƒ_clock

t_c

Clock frequency, MOSC⁽¹⁾

Cycle time, MOSC⁽¹⁾

31.9968 32.0032

MHz

ns

31.188 31.256

t_w(H)

t_w(L)

t_t

Pulse duration⁽²⁾, MOSC, high

Pulse duration⁽²⁾, MOSC, low

Transition time⁽²⁾, MOSC, t_t= t_f/ t_r

50% to 50% reference points (signal)

20% to 80% reference points (signal)

12.5

7.5

ns

Period jitter⁽²⁾, MOSC (that is, the deviation in period from ideal period due solely to high-frequency

jitter – not spread spectrum clocking)

t_jp

–100

100

ps

(1) The frequency range for MOSC is 32 MHz with ±100 PPM accuracy. (This includes impact to accuracy due to aging, temperature, and

trim sensitivity.) The MOSC input cannot support spread spectrum clock spreading.

(2) Applies only when driven by an external digital oscillator.

14

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

6.8 Test and Reset Timing Requirements

MIN

MAX

625

1

UNIT

µs

t_W1(L)

t_t1

t_W2(L)

t_t2

Pulse duration, inactive low, PWRGOOD

Transition time, PWRGOOD, t_t1= t_f/ t_r

Pulse duration, inactive low, POSENSE

Transition time, POSENSE, t_t2= t_f/ t_r

50% to 50% reference points (signal)

20% to 80% reference points (signal)

50% to 50% reference points (signal)

20% to 80% reference points (signal)

4

µs

500

µs

t_PH

Power hold time, POSENSE remains active after

PWGOOD is deasserted

µs

6.9 JTAG Interface: I/O Boundary Scan Application Timing Requirements

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_C

Clock frequency, TCK

10

Cycle time, TCK

100

40

t_W(H)

t_W(L)

t_t

Pulse duration, high

50% to 50% reference points (signal)

20% to 80% reference points (signal)

ns

Pulse duration, low

40

ns

Transition time, t_t= t_f/ t_r

Setup time, TDI valid before TCK↑

Hold time, TDI valid after TCK↑

Setup time, TMS1 valid before TCK↑

Hold time, TMS1 valid after TCK↑

5

ns

t_SU

t_h

t_SU

t_h

8

2

8

2

ns

15

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

MAX UNIT

6.10 Port 1 Input Pixel Interface Timing Requirements

MIN

12

ƒ_clock

t_c

t_w(H)

t_w(L)

Clock frequency, P1A_CLK, P1B_CLK, P1C_CLK

Cycle time, P1A_CLK, P1B_CLK, P1C_CLK

Pulse duration, high

150

MHz

ns

6.666

2.3

83.33

50% to 50% reference points (signal)

ns

Pulse duration, low

2.3

ns

Clock period jitter, P1A_CLK, P1B_CLK, P1C_CLK

(that is, the deviation in period from ideal period)

(1)

t_jp

t_t

Max ƒ_clock

See

ps

ns

Transition time, t_t= t_f/ t_r, P1A_CLK, P1B_CLK, P1C_CLK 20% to 80% reference points (signal)

0.6

2

3

Transition time, t_t= t_f/ t_r, P1_A(9-0), P1_B(9-0) , P1_C(9-

20% to 80% reference points (signal)

t_t

0), P1_HSYNC, P1_VSYNC, P1_DATEN

Transition time, t_t= t_f/ t_r, ALF_HSYNC, ALF_VSYNC,

20% to 80% reference points (signal)

ALF_CSYNC⁽²⁾

t_t

0.6

3

ns

SETUP AND HOLD TIMES⁽³⁾

t_su

t_h

Setup time, P1_A(9-0), valid before P1x_CLK↑↓

0.8

ns

Hold time, P1_A(9-0), valid after P1x_CLK↑↓

Setup time, P1_B(9-0), valid before P1x_CLK↑↓

Hold time, P1_B(9-0), valid after P1x_CLK↑↓

Setup time, P1_C(9-0), valid before P1x_CLK↑↓

Hold time, P1_C(9-0), valid after P1x_CLK↑↓

Setup time, P1_VSYNC, valid before P1x_CLK↑↓

Hold time, P1_VSYNC, valid after P1x_CLK↑↓

Setup time, P1_HSYNC, valid before P1x_CLK↑↓

Hold time, P1_HSYNC, valid after P1x_CLK↑↓

Setup time, P1_FIELD, valid before P1x_CLK↑↓

Hold time, P1_FIELD, valid after P1x_CLK↑↓

Setup time, P1_DATEN, valid before P1x_CLK↑↓

Hold time, P1_DATEN, valid after P1x_CLK↑↓

t_su

t_h

t_su

t_h

t_su

t_h

t_su

t_h

t_su

t_h

t_su

t_h

(1) Use the following formula to obtain the jitter: Maximum clock jitter = ±[(1 / ƒ_clock) – 5414 ps].

(2) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are asynchronous signals.

(3) Setup and hold times should be considered the same regardless of clock used [P1A_CLK, P1B_CLK, P1C_CLK].

6.11 Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing

Requirements^{(1)(2)(3)(4)(5)(6)}

MIN

MAX

90

UNIT

ƒ_clock

t_c

Clock frequency, P2_CLK (LVDS input clock)

Cycle time, P2_CLK (LVDS input clock)

Clock or data slew rate (ƒ_pxck< 90 MHz)

Clock or data slew rate (ƒ_pxck> 90 MHz)

Link start-up time (internal)

20

11.1

0.3

MHz

ns

50

V/ns

ms

t_slew

0.5

t_startup

1

(1) Minimize crosstalk and match traces on the PCB as close as possible.

(2) Maintain the common mode voltage as close to 1.2 V as possible.

(3) Maintain the absolute input differential voltage as high as possible.

(4) The LVDS open input detection is related to a low common mode voltage only. It is not related to a low-differential swing.

(5) LVDS power 3.3-V supply (VDD33_FPD) noise level should be below 100 mV_PP

(6) LVDS power 1.2-V supply (VDD12_FPD) noise level should be below 60 mV_PP

.

16

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

6.12 Synchronous Serial Port (SSP) Interface Timing Requirements

MIN

10

MAX

UNIT

ns

t_su

t_h

t_t

Setup time, SSP0_RXD valid before SSP0_ CLK↓

Hold time, SSP0_RXD valid after SSP0_ CLK↓

Transition time⁽¹⁾, SSP0_RXD, t_t= t_f/ t_r

10

ns

4

ns

t_su

t_h

t_t

Setup time, SSP1_RXD valid before SSP1_ CLK↓

Hold time, SSP1_RXD valid after SSP1_ CLK↓

Transition time⁽¹⁾, SSP1_RXD, t_t= t_f/ t_r

10

ns

(1) 20% to 80% reference points (signal)

6.13 Programmable Output Clocks Switching Characteristics

over operating free-air temperature range, C_L(min timing) = 5 pF, C_L(max timing) = 50 pF (unless otherwise noted) (see

Figure 5)

FROM

PARAMETER

ƒ_clockClock frequency, OCLKC⁽¹⁾

t_c

Cycle time, OCLKC⁽¹⁾

TO (OUTPUT)

MIN

MAX UNIT

(INPUT)

N/A

OCLKC

OCLKD

OCLKE

0.7759

20.83

48

MHz

ns

1288.8

t_w(H)Pulse duration, high 50% to 50% reference points (signal)

t_w(L)Pulse duration, low⁽²⁾50% to 50% reference points (signal)

ƒ_clockClock frequency, OCLKD⁽¹⁾

(t_c/ 2) – 2

0.7759

ns

48

MHz

ns

t_c

Cycle time, OCLKD

20.83

1288.8

t_w(H)Pulse duration, high⁽²⁾50% to 50% reference points (signal)

t_w(L)Pulse duration, low⁽²⁾50% to 50% reference points (signal)

ƒ_clockClock frequency, OCLKE⁽¹⁾

(t_c/ 2) – 2

0.7759

ns

48

MHz

ns

t_c

Cycle time, OCLKE

20.83

1288.8

t_w(H)Pulse duration, high⁽²⁾50% to 50% reference points (signal)

t_w(L)Pulse duration, low⁽²⁾50% to 50% reference points (signal)

(t_c/ 2) – 2

ns

(1) The frequency of OCLKC through OCLKE is programmable.

(2) The duty cycle of OCLKC through OCLKE is within ±2 ns of 50%.

17

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

6.14 Synchronous Serial Port (SSP) Interface Switching Characteristics

over recommended operating conditions, C_L(min timing) = 5 pF, C_L(max timing) = 35 pF (unless otherwise noted) (see

Figure 10)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

SSP0_CLK

MIN

0.287

0.107

48

MAX UNIT

(1)(2)

ƒ_clock

t_c

Clock frequency, SSP0_CLK

Cycle time, SSP0_CLK

N/A

9333

3483

kHz

us

t_w(H)

Pulse duration, high 50% to 50% reference points

(signal)

ns

t_w(L)

Pulse duration, low 50% to 50% reference points

(signal)

N/A

SSP0_CLK

48

ns

t_pd

Output propagation, clock to Q, SSP0_TXD

SSP0_CLK↑

N/A

SSP0_TXD

SSP1_CLK

–5

5

ns

kHz

us

(1)(2)

ƒ_clock

t_c

Clock frequency, SSP1_CLK

2.296 74667

Cycle time, SSP1_CLK

N/A

0.013

5.85

436

t_w(H)

Pulse duration, high 50% to 50% reference points

(signal)

N/A

ns

t_w(L)

t_pd

Pulse duration, low 50% to 50% reference points

(signal)

N/A

SSP1_CLK

SSP1_TXD

5.85

–2

ns

Output propagation, clock to Q, SSP1_TXD

SSP1_CLK↑

2

(1) SSP output timing supports both positive and negative clocking polarity. Figure 10 shows only positive clocking polarity. When the clock

polarity is configured through software to be negative, the data is transferred and captured on the opposite edge of the clock shown.

(2) The maximum rates shown apply to master mode operation only. Slave mode operation is limited to 1/6 of these rates.

6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics

Over operating free-air temperature range, C_L(min timing) = 5 pF, C_L(max timing) = 85 pF (unless otherwise noted)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

MIN

TYP

MAX

UNIT

t_pd

Output propagation, clock to Q

TCK↓

TDO1

3

12

ns

t_t

t_c

t_w(H)

t_w(L)

MOSC

80%

20%

80%

20%

50%

Figure 1. System Oscillators

Power Up

t_t1

80%

50%

20%

80%

50%

20%

80%

50%

20%

PWRGOOD

t_t1

t_w1(L)

80%

50%

20%

POSENSE

t_t2

DC Power Supplies

PWRGOOD has no impact on operation for 60 ms after rising edge of POSENSE.

Figure 2. Power Up

18

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Power Down

PWRGOOD

t_t1

80%

50%

20%

t_t2

POSENSE

80%

50%

20%

80%

50%

20%

t_w2(L)

t_PH

DC Power Supplies

Figure 3. Power Down

t_t

t_c

t_w(H)

ꢁ0%

t_w(L)

ꢁ0%

Ç/Y

(input)

80%

20%

ꢁ0%

t_h

t_su

Ç5L

Çꢀ{1

(inputs)

ëalid

t_pd(max)

Ç5h1

(outputs)

ëalid

Figure 4. I/O Boundary Scan

t_t

t_c

OCLKC

OCLKD

OCLKE

t_w(H)

50%

t_w(L)

80%

20%

80%

20%

50%

Figure 5. Programmable Output Clocks

19

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

t_t

t_c

t_w(L)

50%

t_w(H)

50%

80%

20%

Px_CLK

(input)

50%

t_h

t_su

Px_Data and

Px_Control

(inputs)

Valid

Figure 6. Input Port 1 Interface

Differential V(D0) - V(D1)

Vid(max)

Vid(min)

0 V

-Vid(min)

-Vid(max)

0.3 UI

200ps

0.3 UI

T_eye=0.4 UI

1UI

0

Figure 7. Input Port 2 (LVDS) Interface

Figure 8. (LVDS) Link Start-Up Timing

20

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Figure 9. (LVDS) Clock – Data Skew Definition

t_t

t_c

t_w(H)

50%

t_w(L)

SSP_CLK

(ASIC output)

80%

20%

50%

t_h

50%

t_su

SSP_TXD

(ASIC inputs)

Valid

t_pd(min)

t_pd(max)

SSP_RXD

(ASIC outputs)

Valid

Figure 10. Synchronous Serial Port Interface

DMD_D(23:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

tp1_h

tp1_su

DMD_DCLK

tp1_cwl

tp1_cwh

No relationship

DMD_SAC_CLK

tp2_cwl

tp2_cwh

tp2_h

DMD_SAC_BUS

DMD_DAD_OEZ

DMD_DAD_BUS

DMD_DAD_STRB

tp2_su

Figure 11. DMD LPDDR Interface

21

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The DLPC6401 is the display controller for the DLP4500 (.45 WXGA) DMD. DLPC6401 is part of the chipset

comprised of the DLPC6401 controller and DLP4500 (.45 WXGA) DMD. Both the controller and the DMD must

be used in conjunction with each other for reliable operation of the DLP4500 (.45 WXGA) DMD. The DLPC6401

display controller provides interfaces and data- and image-processing functions that are optimized for small form

factor, high-resolution, and high-brightness display applications. Applications include pico projectors, smart

projectors, screenless displays, interactive displays, wearable displays, and digital signage. Standalone

projectors must include a separate front-end chip to interface to the outside world (for example, video decoder,

HDMI receiver, triple ADC, or USB I/F chip).

7.2 Functional Block Diagram

AC

Power

DC

Power Supply

DC

I2C

LEDs

VGA

regulators

and LED

Drivers

Front End

Processing

Image Processing

Degamma

Primary Color Correction

Chroma Interpolation

Scaler

1D Keystone

On-screen Display

Overlap Color Processing

Formatter

Spatial-

Temporal

Multiplexing

Diamond

DMD

Analog

Front End

30-bit Parallel

Port +

10-bit BT656

Component

Video

30

ñ

Parallel

Port

ñ

Edge-adaptive

Deinterlacer

2D Y/C Decoder

Color Space

Conversion

Brightness

CVBS

30

ñ

DDR,

80 œ 120 MHz

DMD

I/F

Formatting

30-bit LVDS

Input Port

I2C

LVDS

ñ

USB/SD/MMC

(All Multimedia

Formats)

0.45 inch

WXGA

Multimedia

Chip

Embedded RAM 64Mb

Test Pattern

Generator

JTAG

Syncs

Peripherals

Input Clock/

Sync generator

Autolock

ARM

Flash

I/F

SSP

GPIO

I2C

UART

Internal Clock Circuit

CLOCK

Parallel

Flash

SSP

GPIO

(Keypad)

(Fans)

UART

I2C

EEPROM

Temp sensor

Tilt Sensor

(I2C,PWM)

22

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

7.3 Feature Description

Table 2. (LVDS) Receiver Supported Pixel Mapping Modes⁽¹⁾

MAPPING SELECTION

4⁽²⁾[18-Bit Mode]

LVDS RECEIVER INPUT MAPPING SELECTION 1 MAPPING SELECTION 2 MAPPING SELECTION 3

RA Input Channel

RDA(6)

RDA(5)

Map to GRN(4)

Map to RED(9)

Map to RED(8)

Map to RED(7)

Map to RED(6)

Map to RED(5)

Map to RED(4)

Map to GRN(2)

Map to RED(7)

Map to RED(6)

Map to RED(5)

Map to RED(4)

Map to RED(3)

Map to RED(2)

Map to GRN(0)

Map to RED(5)

Map to RED(4)

Map to RED(3)

Map to RED(2)

Map to RED(1)

Map to RED(0)

Map to GRN(4)

Map to RED(9)

Map to RED(8)

Map to RED(7)

Map to RED(6)

Map to RED(5)

Map to RED(4)

RDA(4)

RDA(3)

RDA(2)

RDA(1)

RDA(0)

RB Input Channel

RDB(6)

Map to BLU(5)

Map to BLU(4)

Map to GRN(9)

Map to GRN(8)

Map to GRN(7)

Map to GRN(6)

Map to GRN(5)

Map to BLU(3)

Map to BLU(2)

Map to GRN(7)

Map to GRN(6)

Map to GRN(5)

Map to GRN(4)

Map to GRN(3)

Map to BLU(1)

Map to BLU(0)

Map to GRN(5)

Map to GRN(4)

Map to GRN(3)

Map to GRN(2)

Map to GRN(1)

Map to BLU(5)

Map to BLU(4)

Map to GRN(9)

Map to GRN(8)

Map to GRN(7)

Map to GRN(6)

Map to GRN(5)

RDB(5)

RDB(4)

RDB(3)

RDB(2)

RDB(1)

RDB(0)

RC Input Channel

RDC(6)

Map to DEN

RDC(5)

Map to VSYNC

Map to HSYNC

RDC(4)

RDC(3)

Map to BLU(9)

Map to BLU(8)

Map to BLU(7)

Map to BLU(6)

Map to BLU(7)

Map to BLU(5)

Map to BLU(4)

Map to BLU(3)

Map to BLU(2)

Map to BLU(9)

Map to BLU(8)

Map to BLU(7)

Map to BLU(6)

RDC(2)

Map to BLU(6)

Map to BLU(5)

Map to BLU(4)

RDC(1)

RDC(0)

RD Input Channel

RDD(6)

Map to field (option 1 if applicable)

RDD(5)

Map to BLU(3)

Map to BLU(2)

Map to GRN(3)

Map to GRN(2)

Map to RED(3)

Map to RED(2)

Map to BLU(9)

Map to BLU(8)

Map to GRN(9)

Map to GRN(8)

Map to RED(9)

Map to RED(8)

Map to BLU(7)

Map to BLU(6)

Map to GRN(7)

Map to GRN(6)

Map to RED(7)

Map to RED(6)

No mapping

RDD(4)

RDD(3)

RDD(2)

RDD(1)

RDD(0)

RE Input Channel

RDE(6)

Map to field (option 2 if applicable)

RDE(5)

Map to BLU(1)

Map to BLU(0)

Map to GRN(1)

Map to GRN(0)

Map to RED(1)

Map to RED(0)

Map to BLU(9)

Map to BLU(8)

Map to GRN(9)

Map to GRN(8)

Map to RED(9)

Map to RED(8)

No mapping

RDE(4)

RDE(3)

RDE(2)

RDE(1)

RDE(0)

(1) Mapping options are selected by software.

(2) If mapping option 4 is the only mapping mode needed, and if, and only if, a 'Field 1' or 'Field 2' input is not needed, then the board

layout can leave the LVDS inputs for RD and RE channels floating.

23

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

7.3.1 System Reset Operation

7.3.1.1 Power-Up Reset Operation

Immediately following a power-up event, DLPC6401 hardware automatically brings up the master PLL and

places the ASIC in normal power mode. It then follows the standard system reset procedure (see System Reset

Operation).

7.3.1.2 System Reset Operation

Immediately following any type of system reset (power-up reset, PWRGOOD reset, watchdog timer timeout, and

so on), the DLPC6401 device automatically returns to NORMAL power mode and returns to the following state.

•

All GPIO tri-state and as a result, all GPIO-controlled voltage switches default to enabling power to all ASIC

supply lines. (Assume these outputs are externally pulled-high.)

•

The master PLL remains active (it is reset only after a power-up reset sequence) and most of the derived

clocks are active. However, only those resets associated with the ARM9 processor and its peripherals are

released. (The ARM9 is responsible for releasing all other resets.)

•

ARM9 associated clocks default to their full clock rates. (Boot-up is a full speed.)

All front-end derived clocks are disabled.

The PLL feeding the DDR DMD I/F (PLLD) defaults to its power-down mode and all derived clocks are

inactive with corresponding resets asserted. (The ARM9 is responsible for enabling these clocks and

releasing associated resets.)

•

DMD I/O (except DMD_DAD_OEZ) defaults to its outputs in a logic low state. DMD_DAD_OEZ defaults tri-

stated, but should be pulled high through an external 30- to 51-kΩ pullup resistor on the PCB.

•

All resets output by the DLPC6401 device remain asserted until released by the ARM9 (after boot-up).

The ARM9 processor boots-up from external flash.

When the ARM9 boots-up, the ARM9 API:

•

Configures the programmable DDR clock generator (DCG) clock rates (that is, the DMD LPDDR I/F rate)

Enables the DCG PLL (PLLD) while holding divider logic in reset

When the DCG PLL locks, ARM9 software sets DMD clock rates

API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks

Releases external resets

Application software then typically waits for a wake-up command (through the soft power switch on the projector)

from the end user. When the projector is requested to wake-up, the software places the ASIC back in normal

mode, re-initialize clocks, and resets as required.

24

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

RESETZ

(INIT_BUSY)

(ERR IRQ)

INIT_DONE

100 ms (max)

5 ms (max)

0 ms (min)

3 µs (min)

I²C or DBI-C

(SCL, SDA, CSZ

t1

t2

t3 t4

t5

t6

•

t2: device drives INIT_DONE high within 5 ms after reset is release. Indicates auto-initialization is busy

t3: I²C or DBI-C access to DLPC6401 device does not start until the INIT_BUSY flag (on INIT_DONE) goes low.

This can occur within 100 ms, but may take several seconds

•

t5: an active high pulse on INIT_DONE following the initialization period indicates a detected error condition. The

device reports the source of the error in the system status.

Figure 12. Internal Memory Test Diagram

7.3.1.3 Spread Spectrum Clock Generator Support

The DLPC6401 device supports limited, internally-controlled, spread spectrum clock spreading on the DMD

interface. The purpose is to frequency spread all signals on the high-speed, external interfaces to reduce EMI

emissions. Clock spreading is limited to triangular waveforms. The DLPC6401 device provides modulation

options of 0%, ±0.5%, and ±1.0% (center-spread modulation).

7.3.1.4 GPIO Interface

The DLPC6401 device provides 38 software-programmable, general-purpose I/O pins. Each GPIO pin is

individually configurable as either input or output. In addition, each GPIO output can be either configured as

push-pull or open-drain. Some GPIO have one or more alternate-use modes, which are also software

configurable. The reset default for all GPIO is as an input signal. However, any alternate function connected to

these GPIO pins, with the exception of general-purpose clocks and PWM generation, will be reset. When

configured as open-drain, the outputs must be externally pulled-up (to the 3.3-V supply). External pullup or

pulldown resistors may be required to ensure stable operation before software is able to configure these ports.

7.3.1.5 Source Input Blanking

Vertical and horizontal blanking requirements for both input ports are defined as follows (see 视频时序参数定义).

•

Minimum port 1 vertical blanking:

–

Vertical back porch: 370 µs

Vertical front porch: 2 lines

Total vertical blanking: 370 µs + 3 lines

Minimum port 2 vertical blanking:

–

Vertical back porch: 370 µs

Vertical front porch: 0 lines

Total vertical blanking: 370 µs + 3 lines

Minimum port 1 and port 2 horizontal blanking:

–

Horizontal back porch (HBP): 10 pixels

Horizontal front porch (HFP): 0 pixels

Total horizontal blanking (THB):

25

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

–

0.45 WXGA DMD: Roundup (154286 / Source_APPL, 0)

0.4 XGA DMD: Roundup (144686 / Source_APPL, 0) pixels

7.3.1.6 Video and Graphics Processing Delay

The DLPC6401 device introduces a fixed number of field and frame delays. For optimum audio and video

synchronization, this delay must be matched in the audio path. Table 3 defines the video delay to support audio

matching.

Frame and fields in Table 3 refer to source frames and fields.

Table 3. Primary Channel and Video-Graphics Processing Delay

2D VIDEO

DECODER

FORMATTER

BUFFER

TOTAL

DELAY

SOURCE

DE-INTERLACING

10 to 47 Hz

Non-interlaced graphics

Disabled

{0 frames}

Disabled

{0 frames}

Enabled

{1 frame}

1 frame

1 field

47 to 63 Hz

Non-interlaced graphics

Disabled

{0 frames}

Disabled

{0 frames}

Enabled

{1 frame}

63 to 120 Hz

Non-interlaced graphics

Disabled

{0 frames}

Disabled

{0 frames}

Enabled

{1 frame}

100 to 120 Hz

Display at native rate graphics

Disabled

{0 frames}

Disabled

{0 frames}

Enabled

{1 frame}

50 to 60 Hz interlaced

SDTV video (NTSC, PAL, SECAM)

Enabled

{0 fields}

Edge adaptive de-interlacing enabled

{0 fields}

Enabled

{1 field}

60 Hz interlaced

HDTV video (480i, 1080i)

Disabled

{0 fields}

Edge adaptive de-interlacing enabled

{0 fields}

Enabled

{1 field}

1 field

24 to 30 Hz interlaced

HDTV video (480i, 1080i)

Disabled

{0 fields}

Edge adaptive de-interlacing enabled

{0 fields}

Enabled

{1 field}

1 field

60 Hz progress

HDTV video (480p, 720p)

Disabled

{0 frames}

N/A

{0 frames}

Enabled

{1 frame}

1 frame

24 to 30 Hz Progress

HDTV video (480p, 720p)

Disabled

{0 frames}

N/A

{0 frames}

Enabled

{1 frame}

63 to 87 Hz

Interlaced graphics

≤1280 APPL and ≤75 MHz

Disabled

{0 fields}

Edge adaptive de-interlacing enabled

{0 fields}

Enabled

{1 field}

1 field

63 to 87 Hz

Interlaced graphics

>1280 APPL or >75 MHz

Disabled

{0 fields}

Field-dependent scaling enabled

{0 fields}

Enabled

{1 field}

7.3.2 Program Memory Flash/SRAM Interface

The DLPC6401 device provides three external program memory chip selects:

•

PM_CSZ_0 – Available for optional SRAM or flash device (≤128 Mb)

PM_CSZ_1 – Dedicated CS for boot flash device (that is standard NOR-type flash, ≤128 Mb)

PM_CSZ_2 – Available for optional SRAM or flash device (≤128 Mb)

Flash and SRAM access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 ns in

normal mode and 53.57 ns in low-power modes. Table 4 shows wait state program values for typical flash

access times.

Table 4. Wait State Program Values for Typical Flash Access Times

NORMAL MODE⁽¹⁾

= Roundup (Device_Access_Time / 6.7 ns)

207 ns

LOW-POWER MODE⁽¹⁾

= Roundup (Device_Access_Time / 53.57 ns)

1660 ns

Formula to Calculate the Required Wait

State Value

Max Supported Device Access Time

(1) Assumes a maximum single direction trace length of 75 mm.

26

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Note that when another device such as an SRAM or additional flash is used in conjunction with the boot flash,

care must be taken to keep stub length short and located as close as possible to the flash end of the route.

The DLPC6401 device provides enough Program Memory Address pins to support a flash or SRAM device up to

128 Mb. For systems not requiring this capacity, up to two address pins can be used as GPIO instead.

Specifically, the two most significant address bits (that is PM_ADDR_22 and PM_ADDR_21) are shared on pins

GPIO_16 and GPIO_17 respectively. Like other GPIO pins, these pins float in a high-impedance input state

following reset; therefore, if these GPIO pins are to be reconfigured as Program Memory Address pins, they

require board-level pulldown resistors to prevent any Flash address bits from floating until software is able to

reconfigure the pins from GPIO to Program Memory Address. Also note, that until software reconfigures the pins

from GPIO to Program Memory Address, upper portions of flash memory are not accessible.

Table 5 shows typical GPIO_16 and GPIO_17 pin configurations for various flash sizes.

Table 5. Typical GPIO_16 and GPIO_17 Pin Configurations for Various Flash Sizes

FLASH SIZE

32 Mb or less

64 Mb

GPIO_36 PIN CONFIGURATION

GPIO_17

GPIO_35 PIN CONFIGURATION

GPIO_16

GPIO_17

PM_ADDR_22(*)⁽¹⁾

PM_ADDR_21(*)⁽¹⁾

128 Mb

(1) (*) = Board-level pulldown resistor required

7.3.2.1 Calibration and Debug Support

The DLPC6401 device contains a test point output port, TSTPT_(7:0), which provides selected system calibration

support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs

when reset is released. The state of these signals is sampled upon the release of system reset and the captured

value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown

resistor and thus external pullups are used to modify the default test configuration. The default configuration

(x00) corresponds to the TSTPT(7:0) outputs being driven low for reduce switching activity during normal

operation. For maximum flexibility, TI recommends an option to jumper to an external pullup for TSTPT(0). Note

that adding a pullup to TSTPT(7:1) may have adverse affects for normal operation and TI does not recommend

it. Note that these external pullups are sampled only after a 0-to-1 transition on POSENSE and thus changing

their configuration after reset has been released does not have any affect until the next time reset is asserted

and released. Table 6 defines the test mode selection for two programmable scenarios defined by TSTPT_(0):

Table 6. Test Mode Selection

NO SWITCHING

ACTIVITY

ARM AHB DEBUG SIGNAL SET

TSTPT(3:0) CAPTURE

VALUE

x0

0

x1

TSTPT(0)

TSTPT(1)

TSTPT(2)

TSTPT(3)

TSTPT(4)

TSTPT(5)

TSTPT(6)

TSTPT(7)

ARM9 HREADY

0

HSEL for all external program memory

ARM9 HTRANS⁽¹⁾

0

PFC HREADY OUT (ARM9 R/W)

PFC EMI⁽²⁾request (ARM9 R/W)

PFC EMI⁽²⁾request accept (ARM9 R/W)

PFC EMI⁽²⁾access done (ARM9 R/W)

ARM9 Gate_The_Clk

0

(1) These are only the default output selections. Software can reprogram the selection at any time.

(2) PFC EMI is the parallel flash controller external memory interface

7.3.2.2 Board-Level Test Support

The in-circuit tri-state enable signal (ICTSEN) is a board-level test control signal. By driving ICTSEN to a logic-

high state, all ASIC outputs (except TDO1 and TDO2) are tri-stated.

The DLPC6401 device also provides JTAG boundary scan support on all I/O signals, non-digital I/O, and a few

special signals. Table 7 defines these exceptions.

27

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Table 7. DLPC6401 – Signals Not Covered by JTAG

SIGNAL NAME

TDO2

PKG BALL

M18

V16

TMS2

MOSC

A14

MOSCN

VPGM

A15

D17

A3

EXRES

RA_IN_P

RA_IN_N

RB_IN_P

RB_IN_N

RC_IN_P

RC_IN_N

RD_IN_P

RD_IN_N

RE_IN_P

RE_IN_N

RCK_IN_P

RCK_IN_N

AB10

AA10

Y11

W11

AB12

AA12

Y13

W13

AB14

AA14

Y9

W9

7.4 Device Functional Modes

DLPC6401 has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:

•

When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the

DMD.

•

When pin PROJ_ON is set low, the projector automatically powers down to save power.

28

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLCP6401 controller is required to be coupled with DLP4500 DMD to provide a reliable display solution for

various data and video display applications. The DMDs are spatial light modulators which reflect incoming light

from an illumination source to one of two directions, with the primary direction being into a projection or collection

optic. Each application is derived primarily from the optical architecture of the system and the format of the data

coming into the DLCP6401. Applications of interest include accessory projectors, smart projectors, screenless

display, embedded in display devices like notebooks, laptops, tablets, and hot spots. Other applications include

wearable (near-eye or head mounted) displays, interactive displays, low-latency gaming displays, and digital

signage.

8.2 Typical Application

A common application when using the DLPC6401 is for creating a pico-projector that can be used as an

accessory to a smartphone, tablet, or laptop. The DLPC6401 in the pico-projector receives images from a

multimedia front-end within the product as shown in Figure 13.

Parallel

Flash

VGA

EPROM

I2C

Analog

I2C

Front End

Composite, Component,

SVideo

DLP4500 DMD

(.45 WXGA)

Port 1

30 bit Parallel

HDMI

I2C

(R, G, B, HS, VS, clk)

Receiver/

Display Port

Receiver

DDR

24

DLPC6401

DLP Controller ASICLVDS

Display Port

I2C

(Internal Frame Memory)

(23mm x 23mm)

Port 2

LVDS (Flat Panel Display

Link Compatible)

Multimedia

Front End

GPIO

IR USB

RS232

Port

I2C

LED

Discrete LED Driver

(WiFi Display)

DLP specific hardware

Generic Front End Hardware

12V DC Supply

Regulators to generate different

power supply used in system.

3.3V, 5V, 1.2V, 1.9V, 8.5V, -10V, 16V

Figure 13. Typical Application Diagram

29

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Typical Application (continued)

8.2.1 Design Requirements

A pico-projector is created by using a DLP chipset comprised of DLP4500 DMD and a DLPC6401 controller. The

DLPC6401 controller does the digital image processing and the DLP4500 DMD is the display device for

producing the projected image. In addition to the these DLP chips in the chipset, other chips may be needed.

Typically a Flash part is needed to store the software and firmware. Additionally, a discrete LED driver solution is

required to provide the LED driver functionality for LED illumination. The illumination light that is applied to the

DMD is typically from red, green, and blue LEDs. These are often contained in three separate packages, but

sometimes more than one color of LED die may be in the same package to reduce the overall size of the pico-

projector. DLPC6401 controller provides either parallel- or LVDS-interface to connect the DLPC6401 controller to

the multimedia front-end for receiving images and video.

8.2.1.1 Recommended MOSC Crystal Oscillator Configuration

Table 8. Crystal Port Characteristics

PARAMETER

NOMINAL

3.9

UNIT

pF

MOSC to GND capacitance

MOSCZ to GND capacitance

3.8

pF

Table 9. Recommended Crystal Configuration⁽¹⁾

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

Crystal nominal frequency

32 MHz

Crystal frequency temperature stability

±30 PPM

Overall crystal frequency tolerance (including accuracy, stability,

aging, and trim sensitivity)

±100 PPM

Crystal ESR

50 (max)

Ω

pF

Ω

Crystal load

10

7 (max)

100

Crystal shunt load

RS drive resistor (nominal)

RFB feedback resistor (nominal)

CL1 external crystal load capacitor (MOSC)

CL2 external crystal load capacitor (MOSCN)

PCB layout

1

MΩ

pF

(1)

See

(1)

See

TI recommends a ground isolation ring around the crystal.

(1) Typical drive level with the TCX 9C32070001 crystal (ESRmax = 30 Ω) = 160 µW

30

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

MOSC

MOSCN

C_L= Crystal load capacitance (Farads)

C_L1= 2 * (C_Lœ C_Stray-MOSC

C_L2= 2 * (C_Lœ C_Stray-MOSCN

R_FB

)

R_S

C_Stray-MOSC= Sum of Package & PCB capacitance at

the crystal pin associated with ASIC signal MOSC.

C_Stray-MOSCN= Sum of Package & PCB capacitance at

the crystal pin associated with ASIC signal MOSCN.

Crystal

C_L1

C_L2

Figure 14. Recommended Crystal Oscillator Configuration

It is assumed that the external crystal oscillator will stabilize within 50 ms after stable power is applied.

8.2.2 Detailed Design Procedure

For connecting the DLPC6401 controller and the DLP4500 DMD together, see the reference design schematic.

Layout guidelines should be followed to achieve a reliable projector. To complete the DLP system, an optical

module or light engine is required that contains the DLP4500 DMD, associated illumination sources, optical

elements, and necessary mechanical components.

8.2.3 Application Curve

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

2

3

4

5

6

7

8

[ꢀꢁ /urrent (!)

Figure 15. Relative Output vs LED Current

31

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

9 Power Supply Recommendations

9.1 System Power Regulation

Table 10 shows the recommended power delivery budget for DC offset and AC noise as observed at the

corresponding DLPC6401 power pins.

Table 10. Recommended Power Delivery Budget for DC Offset and AC Noise

NOMINAL

VOLTAGE

TOTAL SUPPLY

MARGIN

ASIC POWER RAIL

USAGE

(1)

VDDC

ASIC core

Internal PLLs

1.2 V

1.8 V

1.9 V

3.3 V

1.2 V

3.3 V

±5%

VDD12_PLLM/ VDD12_PLLD

±5%

VDD_18_PLLM/ VDD18_PLLD Internal PLLs

±5%⁽²⁾

±5%

VDD_DMD

VDD33

DMD LPDDR I/O

LVCMOS I/O

±5%

VDD12_FPD

VDD33_FPD

FPD-Link LVDS I/F

±5%

(1) Total supply margin = DC offset budget + AC noise budget

(2) When possible, TI suggests that a tighter supply tolerance (±3%) be used for the 1.8-V power to the

PLLs to improve system noise immunity

TI strongly recommends that the VDD_18_PLLM and VDD_18_PLLD power feeding internal PLLs be derived

from an isolated linear regulator to minimize the AC noise component. It is acceptable for VDD12_PLLM and

VDD12_PLLD to be derived from the same regulator as the core VDD12, but they should be filtered.

9.2 System Power-Up Sequence

Although the DLPC6401 device requires an array of power supply voltages (1.2 V, 1.8 V, 1.9 V, and 3.3 V), there

are no restrictions regarding the relative order of power supply sequencing. This is true for both power-up and

power-down scenarios. Similarly, there is no minimum time between powering-up and powering-down the

different supplies feeding the DLPC6401 device. However, note that it is not uncommon for there to be power-

sequencing requirements for the devices that share the supplies with the DLPC6401 device. For example:

•

1.2-V core power should be applied whenever any I/O power is applied. This ensures the state of the

associated I/O that are powered are controlled to a known state. Thus, TI recommends to apply core power

first. Other supplies should be applied only after the 1.2-V ASIC core has ramped up.

•

All ASIC power should be applied before POSENSE is asserted to ensure proper power-up initialization is

performed. 1.8-V PLL power, 1.9-V I/O power, and 3.3-V I/O power should remain applied as long as 1.2-V

core power is applied and POSENSE is asserted.

It is assumed that all DLPC6401 device power-up sequencing is handled by external hardware. It is also

assumed that an external power monitor will hold the DLPC6401 device in system reset during power-up (that is,

POSENSE = 0). It should continue to assert system reset until all ASIC voltages have reached minimum

specified voltage levels. During this time, all ASIC I/O are either tri-stated or driven low. The master PLL (PLLM)

is released from reset upon the low-to-high transition of POSENSE, but the DLPC6401 device keeps the rest of

the ASIC in reset for an additional 100 ms to allow the PLL to lock and stabilize its outputs. After this 100-ms

delay, ARM9-related internal resets are de-asserted, causing the microprocessor to begin its boot-up routine.

Figure 16 shows the recommended DLPC6401 system power-up sequence.

32

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

System Power-Up Sequence (continued)

1.2 V

(VDDC ASIC Core)

3.3 V

(VDD33 ASIC I/O)

1.2 V and 1.8 V

(ASIC PLL)

1.2 V and 3.3 V

(FPD-Link

VDD12_FPD and

VDD33_FPD)

1.9 V

(VDD_DMD)

POSENSE

Figure 16. System Power-Up Sequence

9.3 Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the ASIC minimum supply voltage specification. Thus for

practical reasons, TI recommends that the external power monitor generating POSENSE target its threshold to

90% of the minimum supply voltage specifications and ensure that POSENSE remain low a sufficient amount of

time for all supply voltages to reach minimum ASIC requirements and stabilize. Note that the trip voltage for

detecting the loss of power is not critical for POSENSE and thus may be as low as 50% of rated supply voltages.

In addition, the reaction time to respond to a low voltage condition is not critical for POSENSE; however,

PWRGOOD does have much more critical requirements in these areas.

9.4 System Environment and Defaults

9.4.1 DLPC6401 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC6401 device performs a power-up initialization routine that defaults the

ASIC to its normal power mode, in which ARM9-related clocks are enabled at their full rate and associated resets

are released. Most other clocks default to disabled state with associated resets asserted until released by the

processor. These same defaults are also applied as part of all system reset events (watch dog timer timeout, and

so on) that occur without removing or cycling power.

Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it

enables the rest of the ASIC clocks. When system initialization is complete, application software determines if

and when to enter low-power mode.

9.4.2 1.2-V System Power

The DLPC6401 device can support a power delivery system with a single 1.2-V power source derived from a

switching regulator. The DLPC6401 main core should receive 1.2-V power directly from the regulator output and

the internal ASIC PLLs (VDDC, VDD12_PLLD, and VDD12_PLLM) should receive individually-filtered versions

of this 1.2-V power. For specific filter recommendations, see PCB Layout Guidelines for Internal ASIC Power.

9.4.3 1.8-V System Power

A single 1.8-V power source should be used to supply both DLPC6401 internal PLLs. To keep this power as

clean as possible, TI recommends that this power be sourced by a linear regulator that is individually filtered for

each PLL (VDD_18_PLLD and VDD_18PLLM). For specific filter recommendations, see PCB Layout Guidelines

for Internal ASIC Power.

33

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

System Environment and Defaults (continued)

9.4.4 1.9-V System Power

To maximize signal integrity, TI recommends to use an independent linear regulator to source the 1.9-V supply

that supports the DMD interface (VDD_DMD). To achieve maximum performance, this supply must be tightly

regulated to operating within a 1.9-V ±0.1 V range.

9.4.5 3.3-V System Power

The DLPC6401 device can support a power delivery system with a single 3.3-V power sources derived from a

switching regulator. This 3.3-V power supplies all of the LVCMOS I/O. 3.3-V power should remain active in all

power modes (VDD33) for which 1.2-V core power is applied.

9.4.6 FPD-Link Input LVDS System Power

The DLPC6401 device supports an FPD-Link compatible, LVDS input for an additional method of inputting video

or graphics data for display. This interface has some special ASIC power considerations that are separate from

the other ASIC 1.2- or 3.3-V power rails. Figure 17 shows a FPD-Link 1.2-V power pin (VDD12_FPD)

configuration example.

0.1 Ω DC/1 Ω at 2 Mhz Ferrite

Ex. TDK HF70ACB201209-TL

FPD12

1.2 V rail

(1.2 V)

10 uF

0.1 uF

Figure 17. FPD-Link

In addition, TI recommends to place 0.1-µF low equivalent series resistor (ESR) capacitors to ground as close to

the FPD-Link lower pins of the ASIC as possible. FPD-Link 3.3-V power pins (FPD33) should also use external

capacitors in the same manner as for VDD12_FPD pins.

When FPD-Link is not used, the user can omit the previously mentioned filtering. However, the corresponding

voltages must still be provided to avoid potential long-term reliability issues.

9.4.7 Power Good (PWRGOOD) Support

The PWRGOOD signal is defined as an early warning signal that alerts the ASIC 500 µs before DC supply

voltages drop below specifications. This allows the ASIC to park the DMD ensuring the integrity of future

operation. For practical reasons, TI recommends that the monitor sensing PWRGOOD be on the input side of

supply regulators.

9.4.8 5-V Tolerant Support

The DLPC6401 device does not support any 5-V tolerant I/O. However, note that source signals ALF_HSYNC,

ALF_VSYNC, and I²C typically have 5-V requirements and special measures must be taken to support them. TI

recommends the use of a 5- to 3.3-V level shifter.

34

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

10 Layout

10.1 Layout Guidelines

TI recommends 2-ounce copper (2.6-mil) power and ground planes in the PCB design to achieve needed thermal

connectivity.

10.1.1 PCB Layout Guidelines for Internal ASIC Power

TI recommends the following guidelines to achieve desired ASIC performance relative to internal PLLs:

•

The DLPC6401 device contains two PLLs (PLLM and PLLD), each of which has a dedicated 1.2-V digital and

1.8-V analog supply. These 1.2-V PLL pins should be individually isolated from the main 1.2-V system supply

through a ferrite bead. The impedance of the ferrite bead should be much greater than that of the capacitor at

frequencies where noise is expected. Specifically the impedance of the ferrite bead must be less than 0.5 Ω

in the frequency range of 100 to 300 kHz and greater than 10 Ω in the frequency range >100 MHz.

As a minimum, 1.8-V analog PLL power and ground pins should be isolated using an LC-filter with a ferrite

serving as the inductor and a 0.1-µF capacitor on the ASIC side of the ferrite. TI recommends that this 1.8-V

PLL power be supplied from a dedicated linear regulator and each PLL should be individually isolated from

the regulator. The same ferrite recommendations described for the 1.2-V digital PLL supply apply to the 1.8-V

analog PLL supplies.

When designing the overall supply filter network, take care to ensure no resonance occurs. Particularly take

care around the 1- to 2-mHz band, as this coincides with the PLL natural loop frequency.

Signal VIA

PCB Pad

VIA to Common Analo/g

Digital Board Power Plane

ASIC Pad

VIA to Common Analo/g

Digital Board Ground Plane

C

B

A

E

D

F

Local

Decoupling

for the PLL

Digital Supply

22

MOSC

Crystal

Oscillator

PLLM_

VSS

MOSC

N

15

PLLM_

VAS

PLLM_

VDD

PLLM_

VAD

PLLD_

VSS

10.0uF

MOSC

14

13

12

FB

PLLD_

VAS

PLLD_

VDD

PLLD_

VAD

10.0uF

FB

10.0uF

Figure 18. PLL Filter Layout

35

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Layout Guidelines (continued)

High-frequency decoupling is required for both 1.2-V and 1.8-V PLL supplies and should be provided as close as

possible to each of the PLL supply package pins. TI recommends placing decoupling capacitors under the

package on the opposite side of the board. Use high-quality, low-ESR, monolithic, surface mount capacitors.

Typically 0.1 µF for each PLL supply should be sufficient. The length of a connecting trace increases the

parasitic inductance of the mounting, and thus, where possible, there should be no trace, allowing the via to butt

up against the land itself. Additionally, the connecting trace should be made as wide as possible. Further

improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.

The location of bulk decoupling depends on the system design. Typically, a good ceramic capacitor in the 10-µF

range is adequate.

10.1.2 PCB Layout Guidelines for Quality Auto-Lock Performance

One of the most important factors in getting good performance from Auto-Lock is to design the PCB with the

highest-quality signal integrity possible. TI recommends the following:

•

Place the ADC chip as close to the VESA/video connectors as possible.

Avoid crosstalk to the analog signals by keeping them away from digital signals.

Do not place the digital ground or power planes under the analog area between the VESA connector to the

ADC chip.

•

Avoid crosstalk onto the RGB analog signals. Separate them from the VESA Hsync and Vsync signals.

Analog power should not be shared with the digital power directly.

Try to keep the trace lengths of the RGB as equal as possible.

Use good quality (1%) termination resistors for the RGB inputs to the ADC.

If the green channel must be connected to more than the ADC green input and ADC sync-on-green input,

provide a good-quality high-impendence buffer to avoid adding noise to the green channel.

10.1.3 DMD Interface Considerations

The DMD interface is modeled after the low-power DDR memory (LPDDR) interface. To minimize power

dissipation, the LPDDR interface is defined to be unterminated. This makes good PCB signal integrity

management imperative. In particular, impedance control and crosstalk mitigation is critical to robust operation.

LPDDR board design recommendations include 3× design rules (that is, trace spacing = 3× trace width), ±10%

impedance control, and signal routing directly over a neighboring reference plane (ground or 1.9-V plane).

DMD interface performance is also a function of trace length, so even with good board design, the length of the

line limits performance. The DLPC6401 device works over a very-narrow range of DMD signal routing lengths at

120 MHz only. The device provides the option to reduce the interface clock rate to facilitate a longer interface

(this includes 106.7-MHz, 96-MHz, 87.7-MHz, and 80-MHz programming options). However, note that reducing

the interface clock rate has the impact of increasing DMD load time, which in turn reduces image quality. Even

with a clock reduction, the edge rates required to achieve the fastest clock rates still exist and cause overshoot

and undershoot issues if there is excessive crosstalk, or the line is too short. Thus, ensuring positive timing

margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup margin = (DLPC6401 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)

(1)

Hold-time margin = (DLPC6401 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation) (2)

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously

switching output (SSO) noise, crosstalk, and inter-symbol interference (ISI). The DLPC6401 I/O timing

parameters can be found in their corresponding tables. Similarly, PCB routing mismatch can be budgeted and

met through controlled PCB routing. However, PCB SI degradation is not so straightforward.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these

recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements.

36

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Layout Guidelines (continued)

PCB design:

●

Configuration:

Asymmetric dual stripline

Signal routing layer thickness (T):

Single-ended signal impedance controlled:

Differential signal impedance controlled:

1.0-oz copper (1.2 mil)

50 Ω (±10%)

100-Ω differential (±10%)

PCB Stackup:

●

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the 1.9-V DMD I/O power plane or another ground plane.

Dielectric FR4, (Er):

4.3 at 1 GHz (nominal)

Signal trace distance to reference plane 1 (H1): 5 mil (nominal)

Signal trace distance to reference plane 2 (H2): 30.4 mil (nominal)

If additional routing layers are required, ensure they are adjacent to one of these reference planes

Reference Plane 1

H1

W

T

Trace

S

Trace

H2

Dielectric Er

H2

T

Trace

H1

Reference Plane 2

Figure 19. PCB Stackup Geometries

Flex design:

●

Configuration:

2-layer microstrip

The reference plane is assumed to be a ground plane for proper return path.

Vias: Max 2 per signal

37

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Layout Guidelines (continued)

●

Single trace width:

4 mil (min)

Signal routing layer thickness (T):

Single-ended signal impedance controlled:

0.5-oz copper (0.6 mil)

50 Ω (±10%)

Table 11. General PCB Routing (Applies to All Corresponding PCB Signal)

PARAMETER

APPLICATION

SINGLE-ENDED SIGNALS

REQUIREMENT

UNIT

4

(0.1)

mil

(mm)

Escape routing in ball field

Minimum

5

mil

(mm)

Line width (W)⁽¹⁾

PCB etch data or control

PCB etch clocks

Minimum

(0.13)

7

mil

(mm)

(0.18)

4

(0.1)

mil

(mm)

Escape routing in ball field

PCB etch data or control

PCB etch clocks

Minimum

Line spacing to other signals (S)

mil

(mm)

2× the line width⁽²⁾

mil

(mm)

3x the line width

(1) Line width is expected to be adjusted to achieve impedance requirements

(2) 3× line spacing is recommended for all signals to help achieve the desired signal integrity

Table 12. DMD I/F, PCB Interconnect Length Matching Requirements⁽¹⁾⁽²⁾

SIGNAL GROUP LENGTH MATCHING

I/F

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD_TRC,

DMD_SCTRL,

DMD_LOADB

DMD_D(23:0)

±200

(±5.08)

mil

(mm)

DMD (DDR)

DMD_DCLK

DMD_SAC_BUS,

DMD_DAD_OEZ,

DMD_DAD_STRB,

DMD_DAD_BUS

±200

(± 5.08)

mil

(mm)

DMD (SDR)

DMD_SAC_CLK

(1) These values apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC6401

or the DMD. Additional margin can be attained if internal DLPC6401 package skew is taken into account.

(2) To minimize EMI radiation, serpentine routes added to facilitate matching should be implemented on signal layers only, and between

reference planes.

Table 13. DMD I/F, PCB⁽¹⁾Interconnect Min and Max Length Limitations (Note Operating Frequency

Dependencies)⁽²⁾

SIGNAL ROUTING LENGTH

BUS

SIGNAL GROUP

MAX⁽³⁾⁽⁴⁾

UNIT

MIN⁽³⁾

120 MHz

106.7 MHz

96 MHz

87.7 MHz

DMD_DCLK,

DMD_TRC,

DMD_SCTRL,

DMD_LOADB

DMD_D(23:0)

2480

(63)

2953

(75)

3465

(88)

3937

(100)

3937

(100)

mil

(mm)

DMD (DDR)

(1) Signal lengths below the stated minimum likely result in excessive overshoot or undershoot (at any frequency).

(2) PCB layout assumes 2× design rules (that is, line spacing = 2× line width). However, 3× design rules reduce crosstalk and significantly

help performance.

(3) Minimum and maximum signal routing length includes escape routing.

(4) DMD-DDR maximum signal length is a function of the DMD_DCLK rate.

38

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Table 13. DMD I/F, PCB⁽⁾Interconnect Min and Max Length Limitations (Note Operating Frequency

Dependencies)⁽⁾(continued)

SIGNAL ROUTING LENGTH

BUS

SIGNAL GROUP

MAX⁽³⁾⁽⁴⁾

UNIT

MIN⁽³⁾

120 MHz

106.7 MHz 96 MHz

87.7 MHz

DMD_SAC_CLK,

DMD_SAC_BUS,

DMD_DAD_OEZ,

DMD_DAD_STRB,

DMD_DAD_BUS

512

(13)

5906

(150)

mil

(mm)

DMD (SDR)

spacer

•

Number of layer changes:

Minimize layer changes

Stubs:

Stubs should be avoided

–

•

–

Termination requirements:

DMD DDR data:

Specifically: DMD_D(23-0)

External [5-Ω] series termination (at the transmitter)

DMD DDR clock

Specifically: DMD_DCLK

External [5-Ω] series termination

DMD TRC, SCTRL, load: Specifically: DMD_TRC, DMD_SCTRL, DMD_LOADB

External [5-Ω] series termination (at the transmitter)

DMD SAC and

miscellaneous control:

Specifically: DMD_SAC_CLK, DMD_SAC_BUS, DMD_DAD_STRB,

DMD_DAD_BUS

External [5-Ω] series termination (at the transmitter)

DAD output enable:

Specifically: DMD_DAD_OEZ

External [0-Ω] series termination

Instead this signal must be externally pulled-up to VDD_DMD through a 30- to

51-kΩ resistor.

However, note that both the DLPC6401 output timing parameters and the DMD input timing parameters include

timing budget to account for their respective internal package routing skew. Thus, additional system margin can

be attained by comprehending the package variations and compensating for them in the PCB layout. To increase

system timing margin, TI recommends that DLPC6401 package variation be compensated for (by signal group),

but it may not be desirable to compensate for DMD package skew. Because, each DMD has a different skew

profile making the PCB layout DMD specific. Thus, if an OEM wants to use a common PCB design for different

DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB or the

package lengths for all applicable DMDs be considered. Table 14 provides the DLPC6401 package output delay

at the package ball for each DMD I/F signal. DMD internal routing skew data is contained in the DMD data sheet.

Table 14. DLPC6401 DMD I/F Package Routing Length

SIGNAL

DMD_D0

DMD_D1

DMD_D2

DMD_D3

DMD_D4

DMD_D5

DMD_D6

TOTAL DELAY (ps)

PACKAGE BALL

SIGNAL

DMD_D14

DMD_D15

DMD_D16

DMD_D17

DMD_D18

DMD_D19

DMD_D20

TOTAL DELAY (ps)

PACKAGE BALL

25.9

19.6

13.4

7.4

A8

B8

19

B12

C12

D12

B7

11.7

4.7

C8

D8

21.5

24.8

8.3

18.1

11.1

4.4

B11

C11

D11

A10

D7

23.9

B6

39

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Table 14. DLPC6401 DMD I/F Package Routing Length (continued)

SIGNAL

DMD_D7

DMD_D8

DMD_D9

DMD_D10

DMD_D11

DMD_D12

DMD_D13

TOTAL DELAY (ps)

PACKAGE BALL

SIGNAL

DMD_D21

TOTAL DELAY (ps)

PACKAGE BALL

0

E11

C7

1.6

10.7

16.7

24.8

18

E9

C10

C6

A9

14.8

18.4

6.4

DMD_D22

B10

E7

DMD_D23

DMD_DCLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

4.8

D10

A6

B9

29.8

25.7

11.4

4.6

C9

D9

A12

10.1.4 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused

ASIC input pins be tied through a pullup resistor to its associated power supply or a pulldown to ground. For

ASIC inputs with an internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown,

unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be

expected to drive the external line.

Unused output-only pins can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then they should be

pulled-up (or pulled-down) using an appropriate resistor.

40

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

10.2 Layout Example

Figure 20. Layer 3

41

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

Layout Example (continued)

Figure 21. Layer 4

10.3 Thermal Considerations

The underlying thermal limitation for the DLPC6401 device is that the maximum operating junction temperature

(T_J) not be exceeded (this is defined in the Recommended Operating Conditions). This temperature depends on

operating ambient temperature, airflow, PCB design (including the component layout density and the amount of

copper used), power dissipation of the DLPC6401 device, and power dissipation of surrounding components.

The DLPC6401 package is designed primarily to extract heat through the power and ground planes of the PCB,

thus copper content and airflow over the PCB are important factors.

42

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

Thermal Considerations (接下页)

The recommended maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC6401 power dissipation and R_θJAat 1 m/s of forced airflow, where R_θJAis the thermal

resistance of the package as measured using a JEDEC-defined standard test PCB. This JEDEC test PCB is not

necessarily representative of the DLPC6401 PCB, and thus the reported thermal resistance may not be accurate

in the actual product application. Although the actual thermal resistance may be different, it is the best

information available during the design phase to estimate thermal performance. However, after the PCB is

designed and the product is built, TI highly recommends that thermal performance be measured and validated.

To do this, the top-center case temperature should be measured under the worst-case product scenario

(maximum power dissipation, maximum voltage, and maximum ambient temperature) and validated not to

exceed the maximum recommended case temperature (T_C). This specification is based on the measured φ_JTfor

the DLPC6401 package and provides a relatively accurate correlation to junction temperature. Take care when

measuring this case temperature to prevent accidental cooling of the package surface. TI recommends a small

(approximately 40-gauge) thermocouple. The bead and the thermocouple wire should contact the top of the

package and be covered with a minimal amount of thermally-conductive epoxy. The wires should be routed

closely along the package and the board surface to avoid cooling the bead through the wires.

43

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

11.1.1.1 视频时序参数定义

每帧有效扫描行数 (ALPF) 定义一帧中包含可显示数据的行数：ALPF 是每帧总行数 (TLPF) 的子集。

每行有效像素 (APPL) 定义包含可显示数据的一行中的像素时钟数：APPL 是每行总像素 (TPPL) 的子集。

水平后沿 (HBP) 消隐水平同步之后，第一个有效像素之前的消隐像素时钟数量。注意：HBP 时间以各自同步信号

的前缘（有效）边沿为基准。

水平前沿 (HFP) 消隐最后一个有效时钟之后，水平同步之前的消隐像素时钟的数量。

水平同步 (HS) 定义水平间隔（行）开始的时序基准点。绝对基准点由 HS 信号的有效边沿定义。有效边沿（源定

义的上升沿或下降沿）是测量所有水平消隐参数的基准。

每帧总行数 (TLPF) 以行数定义垂直扫描时间（帧时间）：TLPF = 每帧总行数（有效和无效行）

每行总像素 (TPPL) 以像素时钟数定义水平行扫描时间：TPPL = 每行总像素时钟数（有效和无效像素时钟）

垂直后沿 (VBP) 消隐垂直同步后，第一个有效行之前的消隐行的数量。

垂直前沿 (VFP) 消隐最后有效行之后，垂直同步前的消隐行的数量。

垂直同步 (VS) 定义垂直间隔（帧）开始的时序基准点。这个绝对基准点由 VS 信号的有效边沿定义。有效边沿

（源定义的上升沿或下降沿）是测量所有垂直消隐参数的基准。

TPPL

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

(HBP)

(HFP)

ALPF

Vertical Front Porch (VFP)

图 22. 时序参数图

44

DLPC6401

www.ti.com.cn

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

器件支持 (接下页)

11.1.1.2 器件标记

标记定义：

第 1 行： DLP^®设备名称

第 2 行：铸造部件号

第 3 行：SSSSSSYYWW-QQ：封装组件信息

SSSSSS：制造工厂

YYWW：日期代码（YY = 年 :: WW = 周）

QQ：合格等级选项 – 工程样品在此处以 ES 后缀标记。

例如，TAIWAN1324-ES 表示在台湾制造的工程样品，制造日期是 2013 年第 24 周

第 4 行：LLLLLLL e1：半导体晶圆的铸造批次代码以及无铅焊锡球标记

LLLLLLL：铸造批次代码

e1：表示含 SnAgCu 的无铅焊锡球

45

DLPC6401

ZHCSC08C –DECEMBER 2013–REVISED AUGUST 2015

www.ti.com.cn

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

ARM926 is a trademark of ARM.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

46

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据

JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售

都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，

客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权

限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可。使用

此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行

复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明

示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。

客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法

律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障

及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而

对 TI 及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用

的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面

向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有

法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

产品

应用

www.ti.com.cn/telecom

数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

www.ti.com/energy

www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

汽车电子

视频和影像

www.ti.com.cn/industrial

www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

www.ti.com.cn/clockandtimers

www.ti.com.cn/interface

www.ti.com.cn/logic

逻辑

电源管理

www.ti.com.cn/power

www.ti.com.cn/microcontrollers

www.ti.com.cn/rfidsys

www.ti.com/omap

微控制器 (MCU)

RFID 系统

OMAP应用处理器

无线连通性

www.ti.com.cn/wirelessconnectivity

德州仪器在线技术支持社区

www.deyisupport.com

IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

重要声明

德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的 JESD48 提

供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。

TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其

他条款可能适用于其他类型 TI 产品及服务的使用或销售。

复制 TI 数据表上 TI 信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。TI 对该等复制文

件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去

相关 TI 产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。

买方和在系统中整合 TI 产品的其他开发人员（总称“设计人员”）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且

应全权负责并确保应用的安全性，及设计人员的应用（包括应用中使用的所有 TI 产品）应符合所有适用的法律法规及其他相关要求。设计

人员就自己设计的应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够 (1) 预见故障的危险后果，(2) 监视故障及其后

果，以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含 TI 产品的任何应用前，将彻底测试该等应用

和和该等应用所用 TI 产品的功能而设计。

TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称“TI 资

源”），旨在帮助设计人员开发整合了 TI 产品的应用，如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、

访问或使用任何特定的 TI 资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定 TI 资源。

TI 所提供的 TI 资源，并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明；也未导致 TI 承担任何额外的义务或责任。

TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外，TI 未进行任何其他测试。

设计人员只有在开发包含该等 TI 资源所列 TI 产品的应用时，才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或

其他法理授予您任何TI知识产权的任何其他明示或默示的许可，也未授予您 TI 或第三方的任何技术或知识产权的许可，该等产权包括但不限

于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务

的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权

的许可。

TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡

发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索，包括但不限于因组合产品所致或

与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关

的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管 TI 是否获悉可能会产生上述损害赔

偿，TI 概不负责。

除 TI 已明确指出特定产品已达到特定行业标准（例如 ISO/TS 16949 和 ISO 26262）的要求外，TI 不对未达到任何该等行业标准要求而承担

任何责任。

如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的符合相关功能安全标准和要求的

应用。在应用内使用产品的行为本身不会配有任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和标准而设计。设计人员

不可将任何 TI 产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗

设备是指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入

设备）。此类设备包括但不限于，美国食品药品监督管理局认定为 III 类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备

的所有医疗设备。

TI 可能明确指定某些产品具备某些特定资格（例如 Q100、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的

应用选择适合的产品，并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。

设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	DLPC6401ZFF
厂家：	TEXAS INSTRUMENTS
描述：	DLP® display controller for high-brightness portable displays \| ZFF \| 419 \| 0 to 55 外围集成电路
文件：	总50页 (文件大小：1284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC6401ZFF [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E