DLPC6540ZDC [TI]
DLP® display controller for DLP471TP (0.47 4K UHD) DMD | ZDC | 676 | 0 to 70;型号: | DLPC6540ZDC |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® display controller for DLP471TP (0.47 4K UHD) DMD | ZDC | 676 | 0 to 70 |
文件: | 总98页 (文件大小:2525K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLPC6540
ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
DLPC6540 高分辨率控制器
1 特性
2 应用
• DLPC6540 支持使用DLP471TP 数字微镜器件
(DMD) 的控制器
• 移动智能电视
• 移动投影仪
• 数字标牌
– 最高支持4K UHD (60Hz)
– 在240Hz (2D) 和120Hz (3D) 下,最高1080p
• 为单个V-by-One® HS 视频输入端口提供一个、两
个、四个或八个通道
3 说明
DLPC6540 是用于 TI DLP 产品 4K UHD 显示芯片组
的数字显示控制器。DLPC6540 显示控制器、
DLP471TP 数字微镜器件(DMD) 和DLPA3005 电源管
理IC (PMIC) 一起构成芯片组。该解决方案适合需要高
分辨率、高亮度和小巧外形的显示系统。为了确保可靠
运行,对于每个应用,DLPC6540 显示控制器必须始
终与 DLP471TP DMD 和 DLPA3005 电源管理集成电
路配合使用。
– 最高支持600MHz 像素时钟
– 最高3.0Gbps 输入传输速率
• 支持的输入格式
– RGB、YCbCr, 和ICtCp
– 4:4:4,4:2:2,4:2:0
• 带FPU 的内部Arm® Cortex® R4F 处理器
– 88 个可配置GPIO
– 可编程PWM 发生器
– 可编程捕捉和延迟计时器
– USB 2.0 高速OTG 控制器
– SPI 初级/次级控制器
– I2C 初级/次级控制器
器件信息(1)(2)
封装尺寸(标称值)
器件型号
封装
DLPC6540ZDC
P-HBGA (676) 31.00 mm × 31.00 mm
(1) 如需了解所有可用封装,请参阅可订购产品附录。
(2) 包括嵌入式散热板
– UART 和中断控制器
• 扭曲引擎
LS_Interface
– 改进了1D、2D, 和3D 梯形校正
– 光学失真校正(径向和横向颜色失真;例如对于
短投)
– 扭曲(多点手动扭曲和完全扭曲映射访问62 ×
32 点)
HSSI Macro A Data Pair
8
DMD DCLKA
HSSI Macro B Data Pair
8
DMD DCLKB
DLPC6540
Display
Vx1
DLP471TP
HSSI DMD
– 混合(手动混合和完全混合映射访问63 × 32
点)
• 其他图像处理
V
V
V
OFFSET
BIAS
Controller
SPI
Power
Management
– DynamicBlack
RESET
– TI DLP® BrilliantColor™ 技术
– 支持HDR10(PQ 和HLG)
– 帧速率转换
1.8 V
VREG
– 色彩坐标调整
– 白光色温调节
– 可编程degamma
典型的独立系统
– 空间-时间多路复用
– 针对3D 显示的集成支持
• 启动界面显示和捕获
• 集成了2G-bit 帧存储器,无需使用外部高速存储器
• 外部存储器支持
– 用于µP 和PWM 序列的并行闪存
– 用于启动界面捕获和扭曲的辅助闪存
• 系统控制
– DMD 电源和复位驱动器控制
– DMD 水平和垂直图像抖动
• 支持JTAG 边界扫描测试
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS168
DLPC6540
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ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
Table of Contents
6.20 JTAG Boundary Scan Interface Timing
Requirements (Debug Only)........................................50
6.21 JTAG ARM Multi-Ice Interface Timing
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 23
6.1 Absolute Maximum Ratings...................................... 23
6.2 ESD Ratings............................................................. 23
6.3 Recommended Operating Conditions.......................25
6.4 Thermal Information..................................................27
6.5 Power Electrical Characteristics............................... 28
6.6 Pin Electrical Characteristics.................................... 29
6.7 DMD HSSI Electrical Characteristics........................33
6.8 DMD Low-Speed LVDS Electrical Characteristics.... 33
6.9 V-by-One Interface Electrical Characteristics........... 34
6.10 USB Electrical Characteristics................................ 34
6.11 System Oscillator Timing Requirements................. 36
6.12 Power Supply and Reset Timing Requirements..... 37
6.13 DMD HSSI Timing Requirements........................... 42
6.14 DMD Low-Speed LVDS Timing Requirements....... 43
6.15 V-by-One Interface General Timing
Requirements (Debug Only)........................................51
6.22 Multi-Trace ETM Interface Timing Requirements... 52
7 Detailed Description......................................................53
7.1 Overview...................................................................53
7.2 Functional Block Diagram.........................................53
7.3 Feature Description...................................................54
7.4 Device Operational Modes........................................72
8 Power Supply Recommendations................................73
8.1 Power Supply Management......................................73
8.2 Hot Plug Usage.........................................................73
8.3 Power Supplies for Unused Input Source
Interfaces.....................................................................73
8.4 Power Supplies.........................................................73
9 Layout.............................................................................74
9.1 Layout Guidelines..................................................... 74
9.2 Thermal Considerations............................................86
10 Device and Documentation Support..........................87
10.1 Device Support....................................................... 87
10.2 接收文档更新通知................................................... 88
10.3 支持资源..................................................................88
10.4 Trademarks.............................................................88
10.5 Electrostatic Discharge Caution..............................88
10.6 术语表..................................................................... 88
11 Mechanical, Packaging, and Orderable
Requirements .............................................................43
6.16 Source Frame Timing Requirements...................... 45
6.17 Synchronous Serial Port Interface Timing
Requirements .............................................................46
6.18 Master and Slave I2C Interface Timing
Requirements .............................................................48
6.19 Programmable Output Clock Timing
Information.................................................................... 90
Requirements..............................................................48
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (August 2020) to Revision C (November 2022)
Page
• Updated SSP0_CSZ_0, 1, 2 pullup value 表5-9 ...............................................................................................3
• Updated 图6-6 ................................................................................................................................................ 37
• Updated 图6-7 ................................................................................................................................................ 37
• Updated 图6-8 ................................................................................................................................................ 37
• Updated 图6-9 ................................................................................................................................................ 37
• Updated Inter-lane skew 表9-5 .......................................................................................................................80
Changes from Revision A (June 2020) to Revision B (August 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• Added parameter tRAMP-DOWN-TOTAL to 节6.12 ................................................................................................37
• Added parameter tRDSD115 to 节6.12 .............................................................................................................. 37
• Added parameter tPROJ_ON to 节6.12 ..............................................................................................................37
• Added parameter tREFCLKA to 节6.12 ..............................................................................................................37
Changes from Revision * (May 2020) to Revision A (June 2020)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 1617 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
图5-1. ZDC Package 676-Pin PBGA Top View
表5-1. Initialization, Board Level Test, and Debug
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Power-On Sense: Signal provided from external voltage monitoring circuit
('0' = All controller supply voltages not at valid level, '1' = All controller supply
voltages have reached 90% specified minimum voltage)
Drive this signal to inactive (low) after the falling edge of PWRGOOD as
specified. See 节6.12 for specific timing requirements as well as the required
power up and power down sequence.
POSENSE
AE27
I8
This pin includes hysteresis.
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表5-1. Initialization, Board Level Test, and Debug (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Power Good: Signal provided from external power supply of voltage monitor
A high value indicates all power is within operating voltage specifications and
the system is safe to exit its reset state. A transition from high to low indicates
that the controller or DMD supply voltage drops below its rated minimum level.
This transition must occur prior to the supply voltage dropping per the timing
specified, as this is an early warning of an imminent power loss condition.
This warning is required to enhance long term DMD reliability. When
PWRGOOD goes low for the specified minimum time, a DMD park and full
Controller reset are performed, protecting the DMD. Note that both controller
and DMD supply voltages must be within operating voltage levels to successfully
execute the DMD park. The minimum PWRGOOD deassertion time is used to
protect the system input from glitches. When PWRGOOD is low, the Controller
is held in its reset state.
PWRGOOD
AG30
I8
See 节6.12 for specific timing requirements as well as the required power up
and power down sequence.
This pin includes hysteresis.
External Reset: General purpose reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low,
and remains low while POSENSE remains low. This signal remains low after
POSENSE is set high, until released by software. This signal is also asserted
low approximately 5 µs after the detection of PWRGOOD going low, or any
internally generated reset. In all cases, this signal remains active low for a
minimum of 2 ms.
EXT_ARSTZ
AF29
O8
Note: This signal can also be independently driven through the software register.
Color Wheel Motor Controller Reset: Color wheel motor controller reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low,
and remains low while POSENSE remains low. This signal remains low after
POSENSE is set high, until released by software. This signal is also asserted
low approximately 5 µs after the detection of PWRGOOD going low, or any
internally generated reset. In all cases, this signal remains active low for a
minimum of 2 ms.
MTR_ARSTZ
AF27
AK19
O8
Note: This signal can also be independently driven through the software register.
JTAG, ARM-ICE, and CPU MBIST Serial Data Clock.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST
(Manufacturing test only) operation
TCK
I8
Includes a weak internal pulldown
JTAG Test Mode Select
Includes a weak internal pullup
TMS1
TMS2
AH20
AJ20
I8
ARM-ICE Test Mode Select
For normal operation, this pin must be left open or unconnected. Includes a
weak internal pullup
I8
CPU MBIST Test Mode Select
TMS3
AK20
I8
For normal operation this pin must be left open or unconnected. Includes a weak
internal pullup
JTAG, ARM-ICE, and CPU MBIST Reset.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST
(Manufacturing test only) operation.
For normal operation, this pin must be pulled to ground through an external
resistor with value 8 kΩor less. Failure to pull this pin low during normal
operation causes start-up and initialization problems.
For JTAG Boundary Scan, ARM-ICE Debug operation, or CPU MBIST, this pin
must be pulled-up or left disconnected. Includes a weak internal pullup and
hysteresis
TRSTZ
AG21
I8
JTAG, ARM-ICE, and CPU MBIST: Serial Data In
Includes a weak internal pullup
TDI
AG20
AG19
I8
TDO1
O8
JTAG Serial Data Out
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表5-1. Initialization, Board Level Test, and Debug (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
ARM-ICE Serial Data Out
For normal operation, this pin must be left open or unconnected.
TDO2
AH19
O8
O8
CPU MBIST Serial Data Out
For normal operation, this pin must be left open or unconnected.
TDO3
AJ19
ETM_TRACECLK
ETM_TRACECTL
C30
D30
O8
O8
TI internal use. Must be left unconnected (clock for trace debug)
TI internal use. Must be left unconnected (control for trace debug)
IC Tristate Enable (Active high)
Asserting this signal transitions all outputs into tristate (except for the JTAG
interface).
Includes a weak internal pulldown, however, an external pulldown is
recommended for added protection. Also includes hysteresis
ICTSEN
ICTSE
K26
M26
E29
I8
TI internal use. Includes a weak internal pulldown, however, an external
pulldown is recommended for added protection. Also includes hysteresis
I8
Test pin 0
This pin requires an external pulldown or pullup resistor (depending on the
desired debug output as noted below) with a value of ≤10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for
debug use as described in 节7.3.7 .
TSTPT_0
B8
Test pin 1
This pin requires an external pulldown or pullup resistor (depending on the
desired debug output as noted below) with a value of ≤10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for
debug use as described in 节7.3.7 .
TSTPT_1
TSTPT_2
TSTPT_3
E30
F26
F27
B8
B8
B8
Test pin 2
This pin requires an external pulldown or pullup resistor (depending on the
desired debug output as noted below) with a value of ≤10 kΩ.
Tristated while PWRGOOD is asserted low. It can be driven as an output for
debug use as described in 节7.3.7 .
Test pin 3
This pin requires an external pulldown or pullup resistor (depending on the
desired debug output as noted below) with a value of ≤10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for
debug use as described in 节7.3.7 .
Test pin 4
This pin requires an external pulldown resistor (≤10 kΩ).
Tri-stated while PWRGOOD is asserted low. It can be driven as an output for
debug use as described in 节7.3.7 .
TSTPT_4
TSTPT_5
TSTPT_6
TSTPT_7
HWTEST_EN
F28
F29
G26
G28
L26
B8
B8
B8
B8
I8
Test pin 5
This pin requires an external pulldown resistor (≤10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for
debug use as described in 节7.3.7 .
Test pin 6
This pin requires an external pulldown resistor (≤10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for
debug use as described in 节7.3.7 .
Test pin 7
This pin requires an external pulldown resistor (≤10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for
debug use as described in 节7.3.7 .
Manufacturing test enable signal.
This signal must be connected directly to ground on the PCB for normal
operation.
Includes a weak internal pulldown and hysteresis
(1) See 表5-13 for more information on I/O definitions.
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表5-2. Analog Front End (Not Supported in DLPC6540)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
K2
K3
K4
K5
J1
AFE_ARSTZ
AFE_CLK
O8
O8
I8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AFE_IRQ
ALF_VSYNC
ALF_HSYNC
ALF_CSYNC
I8
I8
J2
I8
(1) See 表5-13 for more information on I/O definitions.
表5-3. V-by-One Interface Input Data and Control
PIN
TYPE(1)
DESCRIPTION(2) (3)
NAME
NO.
VX1_DATA0_P
VX1_DATA0_N
VX1_DATA1_P
VX1_DATA1_N
VX1_DATA2_P
VX1_DATA2_N
VX1_DATA3_P
VX1_DATA3_N
VX1_DATA4_P
VX1_DATA4_N
VX1_DATA5_P
VX1_DATA5_N
VX1_DATA6_P
VX1_DATA6_N
VX1_DATA7_P
VX1_DATA7_N
C18
D18
A19
B19
C20
D20
A21
B21
C22
D22
A23
B23
C24
D24
A25
B25
I1
V-by-One interface data lanes
V-by-One interface hot plug detect (controller receiver pulls this signal low to
indicate its presence to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at
the transmitter.
VX1_HTPDN
VX1_LOCKN
E17
E19
O4
O4
I1
V-by-One interface clock detect lock (controller receiver pulls this signal low to
indicate clock extraction lock to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at
the transmitter.
VX1_CM_CKREF0
VX1_CM_CKREF1
VX1_CM_CKREF2
VX1_CM_CKREF3
E20
E21
E23
E24
V-by-One reserved: Tie these reserved pins to ground.
VX1_CM_AMOUT0
VX1_CM_AMOUT1
VX1_CM_AMOUT2
VX1_CM_AMOUT3
F19
F21
F22
F23
O1
V-by-One reserved: These pins are reserved and must remain unconnected.
(1) See 表5-13 for more information on I/O definitions.
(2) The system supports 1-lane, 2-lane, 4-lane, or 8-lane operation, based on the bandwidth requirement of the input source. The inputs
for any unused data lanes must be left open.
(3) The V-by-One port supports limited lane remapping to help optimize board layout. The details are described in 节7.3.3.
表5-4. OpenLDI (FPD-Link I) (Not Supported in DLPC6540) Ports Input Data and Control
PIN
TYPE(1)
DESCRIPTION(2) (3)
NAME
NO.
FPDA_CLK_P
FPDA_CLK_N
H3
H4
I5
Reserved
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表5-4. OpenLDI (FPD-Link I) (Not Supported in DLPC6540) Ports Input Data and Control (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3)
NAME
NO.
FPDA_DATAA_P
FPDA_DATAA_N
FPDA_DATAB_P
FPDA_DATAB_N
FPDA_DATAC_P
FPDA_DATAC_N
FPDA_DATAD_P
FPDA_DATAD_N
FPDA_DATAE_P
FPDA_DATAE_N
G1
G2
F3
F4
E1
E2
D3
D4
C1
C2
I5
I5
I5
I5
I5
Reserved
Reserved
Reserved
Reserved
Reserved.
FPDB_CLK_P
FPDB_CLK_N
A4
B4
FPDB_DATAA_P
FPDB_DATAA_N
FPDB_DATAB_P
FPDB_DATAB_N
FPDB_DATAC_P
FPDB_DATAC_N
FPDB_DATAD_P
FPDB_DATAD_N
FPDB_DATAE_P
FPDB_DATAE_N
C5
D5
A6
B6
C7
D7
A8
B8
C9
D9
FPDC_CLK_P
FPDC_CLK_N
A10
B10
FPDC_DATAA_P
FPDC_DATAA_N
FPDC_DATAB_P
FPDC_DATAB_N
FPDC_DATAC_P
FPDC_DATAC_N
FPDC_DATAD_P
FPDC_DATAD_N
FPDC_DATAE_P
FPDC_DATAE_N
C11
D11
A12
B12
C13
D13
A14
B14
C15
D15
(1) See 表5-13 for more information on I/O definitions.
(2) Throughout this document the terms FPD and FPD-Link refer to OpenLDI (FPD-Link I).
(3) Tie the inputs for any unused port(s) to ground, or pull to ground through an external resistor.
表5-5. Parallel Port Input Data and Control (Not Supported in DLPC6540)
PIN
DESCRIPTION
PARALLEL RGB MODE
TYPE(1)
NAME
NO.
B6
PCLK (FPDB_DATAB_N)
VSYNC (FPDA_DATAE_P)
HSYNC (FPDA_DATAE_N)
DATEN (FPDB_DATAE_N)
FIELD (FPDC_DATAE_P)
3D_REF (FPDC_DATAE_N)
I6
I6
I6
I6
I6
I6
Reserved
Reserved
Reserved
Reserved (2)
Reserved
Reserved
C1
C2
D9
C15
D15
PDATA_A0 (FPDA_CLK_P)
PDATA_A1 (FPDA_CLK_N)
PDATA_A2 (FPDA_DATAA_P)
PDATA_A3 (FPDA_DATAA_N)
PDATA_A4 (FPDA_DATAB_P)
PDATA_A5 (FPDA_DATAB_N)
PDATA_A6 (FPDA_DATAC_P)
PDATA_A7 (FPDA_DATAC_N)
PDATA_A8 (FPDA_DATAD_P)
PDATA_A9 (FPDA_DATAD_N)
H3
H4
G1
G2
F3
F4
E1
E2
D3
D4
I6
Reserved
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表5-5. Parallel Port Input Data and Control (Not Supported in DLPC6540) (continued)
PIN
DESCRIPTION
PARALLEL RGB MODE
TYPE(1)
NAME
NO.
PDATA_B0 (FPDB_CLK_P)
PDATA_B1 (FPDB_CLK_N)
PDATA_B2 (FPDB_DATAA_P)
PDATA_B3 (FPDB_DATAA_N)
PDATA_B4 (FPDB_DATAB_P)
PDATA_B5 (FPDB_DATAC_P)
PDATA_B6 (FPDB_DATAC_N)
PDATA_B7 (FPDB_DATAD_P)
PDATA_B8 (FPDB_DATAD_N)
PDATA_B9 (FPDB_DATAE_P)
A4
B4
C5
D5
A6
C7
D7
A8
B8
C9
I6
Reserved
PDATA_C0 (FPDC_CLK_P)
PDATA_C1 (FPDC_CLK_N)
PDATA_C2 (FPDC_DATAA_P)
PDATA_C3 (FPDC_DATAA_N)
PDATA_C4 (FPDC_DATAB_P)
PDATA_C5 (FPDC_DATAB_N)
PDATA_C6 (FPDC_DATAC_P)
PDATA_C7 (FPDC_DATAC_N)
PDATA_C8 (FPDC_DATAD_P)
PDATA_C9 (FPDC_DATAD_N)
A10
B10
C11
D11
A12
B12
C13
D13
A14
B14
I6
Reserved
(1) See 表5-13 for more information on I/O definitions.
(2) If the DATEN is not actively driven, then it must be pulled up to 3.3 V with a weak pullup resistor (50-kΩ max).
表5-6. DMD Reset and Low Speed Interfaces
PIN
TYPE(1) DESCRIPTION
NAME
NO.
DMD_LS0_CLK_P
DMD_LS0_CLK_N
AH17
AG17
O2
O2
O2
DMD low speed differential interface, Port 0 Clock
DMD low speed differential interface, Port 0 Write Data
DMD low speed differential interface, Port 1 Clock (2)
DMD low speed differential interface, Port 1Write Data (2)
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
AK16
AJ16
DMD_LS1_CLK_P
DMD_LS1_CLK_N
AH15
AG15
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
AK14
AJ14
O2
I3
DMD_LS0_RDATA
AH13
DMD, low speed single ended serial interface, Port 0 Read Data (3)
DMD, low speed single ended serial interface, Port 1 Read Data (2) (3). If this
port is not used, this signal requires an external pullup or pulldown to keep
this input from floating.
DMD_LS1_RDATA
AG13
I3
DMD driver enable signal / Active Low Asynchronous Reset
('1' = Enabled, '0' = Reset)
This signal is driven low after the DMD is parked and before power is
removed from the DMD.
DMD_DEN_ARSTZ
AK12
O3
If the 1.8-V power to the DLPC6540 is independent of the 1.8-V power to the
DMD, then an external pulldown resistor must be used to hold the signal low
in the event the DLPC6540 power is inactive while DMD power is applied.
(1) See 表5-13 for more information on I/O definitions.
(2) DMD LS1 port is reserved for single controller, two DMD applications.
(3) All control interface reads make use of the single ended low speed signals. The read data is clocked by the low speed differential write
clock.
表5-7. DMD HSSI (High Speed Serial Interface)
PIN (1)
TYPE(2)
DESCRIPTION
NAME
NO.
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
AK25
AJ25
O7
DMD high speed serial interface, Port 0 Clock Lane
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表5-7. DMD HSSI (High Speed Serial Interface) (continued)
PIN (1)
TYPE(2)
DESCRIPTION
NO.
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
AK29
AJ29
AH28
AG28
AK27
AJ27
AH26
AG26
AH24
AG24
AK23
AJ23
AH22
AG22
AK21
AJ21
O7
DMD high speed serial interface, Port 0 Data Lanes
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
AH7
AG7
O7
DMD high speed serial interface, Port 1 Clock Lane
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
AH11
AG11
AK10
AJ10
AH9
AG9
AK8
AJ8
AK6
AJ6
AH5
AG5
AK4
AJ4
O7
DMD high speed serial interface, Port 1 Data Lanes
AK2
AJ2
HSSI_ATETEST
AJ12
O7
Manufacturing Test use only—Must be left open (that is, unconnected)
(1) A number of pin remapping options are available for the HSSI high speed channels to aid with optimizing board signal routing. See 节
7.3.4 for information on these pin remapping options.
(2) See 表5-13 for more information on I/O definitions.
表5-8. Program Memory (FLASH) Interface
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
T27
T28
T29
T30
U26
U27
U29
U30
V29
V28
V27
V26
W30
PM_CSZ_0
PM_CSZ_1
PM_CSZ_2
PM_ADDR_0
PM_ADDR_1
PM_ADDR_2
PM_ADDR_3
PM_ADDR_4
PM_ADDR_5
PM_ADDR_6
PM_ADDR_7
PM_ADDR_8
PM_ADDR_9
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
Chip select: boot FLASH only (Boot FLASH must use this chip select.)
Chip select: additional peripheral device
Chip select: additional peripheral device
Address bit (LSB)
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
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表5-8. Program Memory (FLASH) Interface (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
W29
W28
W26
Y30
PM_ADDR_10
PM_ADDR_11
PM_ADDR_12
PM_ADDR_13
PM_ADDR_14
PM_ADDR_15
PM_ADDR_16
PM_ADDR_17
PM_ADDR_18
PM_ADDR_19
PM_ADDR_20
PM_ADDR_21
PM_ADDR_22
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
O8
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Address bit
Y29
Y28
Y27
Y26
AA30
AA29
AA27
AA26
AB29
PM_ADDR_23
(GPIO_47)
AB28
B8
Address bit (MSB)(2)
PM_WEZ
PM_OEZ
R28
R29
O8
O8
Write enable (active low)
Output enable (active low)
Lower Byte (7:0) Enable (active low)—only applicable to devices using
PM_CSZ_1 or PM_CSZ_2
PM_BLSZ_0
PM_BLSZ_1
R30
T26
O8
O8
Upper Byte (15:8) Enable (active low)—only applicable to devices using
PM_CSZ_1 or PM_CSZ_2
PM_Data_0
PM_Data_1
PM_Data_2
PM_Data_3
PM_Data_4
PM_Data_5
PM_Data_6
PM_Data_7
PM_Data_8
PM_Data_9
PM_Data_10
PM_Data_11
PM_Data_12
PM_Data_13
PM_Data_14
PM_Data_15
L29
L30
L28
M27
M28
M29
M30
N26
N27
N29
N30
P26
P27
P28
P29
R26
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
(1) See 表5-13 for more information on I/O definitions.
(2) The Program Memory address bus can be extended by one bit to 24 bits by making use of GPIO_47. Add an external pulldown
resistor when this GPIO is configured for this purpose.
表5-9. Peripheral Interfaces
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
I2C Port 0 (master-slave), Typically slave for Host Command and Control to Controller, SCL
(bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this
pullup is 1 KΩ.
IIC0_SCL
E27
B13
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表5-9. Peripheral Interfaces (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
I2C Port 0 (master-slave), Typically slave for Host Command and Control to Controller, SDA.
(bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this
pullup is 1 KΩ.
IIC0_SDA
D29
B13
SSP0_TXD
SSP0_RXD
SSP0_CLK
AD27
AD29
AD28
O8
I8
SSP/SPI Port 0 Data Out (master): transmit data pin
SSP/SPI Port 0 Data In (master): Receive data pin
SSP/SPI Port 0 clock (master): clock pin
O8
SPI Port 0 chip select 2 (master): chip select (active low)
An external pullup resistor (≤100 kΩ) is suggested to avoid a floating chip select input to the
external device.
SSP0_CSZ_2
SSP0_CSZ_1
SSP0_CSZ_0
AC28
AC26
AB27
O8
O8
O8
SPI Port 0 chip select 1 (master): chip select (active low)
An external pullup resistor (≤100 kΩ) is suggested to avoid a floating chip select input to the
external device.
SPI Port 0 chip select 0 (master): chip select (active low)
An external pullup resistor (≤100 kΩ) is suggested to avoid a floating chip select input to the
external device.
UART Port 0 (slave): serial data transmit
This UART port is reserved for TI debug. An external pullup resistor (≤10 kΩ) is required.
UART0_TXD
UART0_RXD
UART0_RTSZ
UART0_CTSZ
P4
P5
N2
N3
O8
I8
UART Port 0 (slave): serial data receive
This UART port is reserved for TI debug. An external pullup resistor (≤10 kΩ) is required.
UART Port 0 (slave): ready to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤10 kΩ) is required.
O8
I8
UART Port 0 (slave): clear to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤10 kΩ) is required.
USB_DAT_P
USB_DAT_N
B27
A27
B11
B11
USB OTG Data Lane (master-slave)
USB_VBUS
USB_ID
D26
C27
USB OTG 5V Power Supply Detection (master-slave)
IOther USB OTG Mini Receptacle Identification (master-slave)
USB OTG Reference Resistor
An external reference resistor must be connected as shown in 节9.1.6 .
USB_TXRTUNE
USB_XI
C26
A29
B29
C28
BGND
USB OTG External Oscillator XI—Not used (clock provided internally)
For normal operation this pin must be connected to GND.
IGND
USB OTG External Oscillator XO—Not used (clock provided internally)
BGND
USB_XO
For normal operation this pin must be left open (unconnected).
USB OTG Manufacturing Test
BOther
USB_ANALOGTEST
This pin must be left open (unconnected).
PMD_INTZ
CW_PWM
CW_INDEX
AD26
AE30
AE29
I8
O8
I8
Reserved function. This signal requires an external pullup.
Reserved function
Reserved function
(1) See 表5-13 for more information on I/O definitions.
表5-10. GPIO Peripheral Interface
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 87: Options:
1. Alt 0: Reserved
GPIO_87
K1
B8
2. Alt 1: DAO_CLKIN (I)
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 86: Options:
1. Alt 0: Reserved
GPIO_86
GPIO_85
GPIO_84
GPIO_83
GPIO_82
GPIO_81
GPIO_80
GPIO_79
GPIO_78
GPIO_77
GPIO_76
L5
B8
2. Alt 1: DAO_DI_1 (I)
3. Optional GPIO
General purpose I/O 85: Options:
1. Alt 0: Reserved
L4
L3
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
2. Alt 1: DAO_DI_0 (I)
3. Optional GPIO
General purpose I/O 84: Options:
1. Alt 0: Reserved
2. Alt 1: HBT_CLKIN_2 (I)
3. Optional GPIO
General purpose I/O 83: Options:
1. Alt 0: Reserved
L2
2. Alt 1: HBT_DI_2 (I)
3. Optional GPIO
General purpose I/O 82: Options:
1. Alt 0: Reserved
M5
M4
M2
M1
N5
N4
AD5
2. Alt 1: HBT_CLKIN_1 (I)
3. Optional GPIO
General purpose I/O 81: Options:
1. Alt 0: Reserved
2. Alt 1: HBT_DI_1 (I)
3. Optional GPIO
General purpose I/O 80: Options:
1. Alt 0: Reserved
2. Alt 1: HBT_CLKIN_0 (I)
3. Optional GPIO
General purpose I/O 79: Options:
1. Alt 0: Reserved
2. Alt 1: HBT_DI_0 (I)
3. Optional GPIO
General purpose I/O 78: Options:
1. Alt 0: Reserved
2. Alt 1: SEQ_SYNC (B/ open drain)
3. Optional GPIO
General purpose I/O 77: Options:
1. Alt 0: Reserved
2. Alt 1: EFSYNC (O)/ DASYNC (I)
3. Optional GPIO
General purpose I/O 76: Options:
1. Alt 0: AWC1_DACD_PWMB_1 (O)
2. Alt 1: N/A
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 75: Options:
1. Alt 0: AWC1_DACS_PWMA_1 (O)
2. Alt 1: N/A
GPIO_75
GPIO_74
GPIO_73
GPIO_72
GPIO_71
GPIO_70
GPIO_69
GPIO_68
GPIO_67
GPIO_66
GPIO_65
AC1
B8
3. Optional GPIO
General purpose I/O 74: Options:
1. Alt 0: AWC1_DACD_PWMB_0 (O)
2. Alt 1: N/A
AC2
AC4
AC5
AD1
AD2
AD3
AD4
AF4
AE2
AE3
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
3. Optional GPIO
General purpose I/O 73: Options:
1. Alt 0: AWC1_DACS_PWMA_0 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 72: Options:
1. Alt 0: AWC1_DACCLK_0_1 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 71: Options:
1. Alt 0: AWC1_OUT_ENZ (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 70: Options:
1. Alt 0: AWC0_DACD_PWMB_1 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 69: Options:
1. Alt 0: AWC0_DACS_PWMA_1 (O)
2. Alt 1: MEMAUX_1 (O) (#2)
3. Optional GPIO
General purpose I/O 68: Options:
1. Alt 0: AWC0_DACD_PWMB_0 (O)
2. Alt 1: IIC2_SDA (B) (#3)
3. Optional GPIO
General purpose I/O 67: Options:
1. Alt 0: AWC0_DACS_PWMA_0 (O)
2. Alt 1: IIC2_SCL (B) (#3)
3. Optional GPIO
General purpose I/O 66: Options:
1. Alt 0: AWC0_DACCLK_0_1 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 65: Options:
1. Alt 0: AWC0_OUT_ENZ (O)
2. Alt 1: N/A
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 64: Options:
1. Alt 0: OCLKB (O)
2. Alt 1: N/A
GPIO_64
GPIO_63
GPIO_62
GPIO_61
GPIO_60
GPIO_59
GPIO_58
GPIO_57
GPIO_56
GPIO_55
GPIO_54
AE4
B8
3. Optional GPIO
General purpose I/O 63: Options:
1. Alt 0: Reserved
AG2
AG3
AF1
AF2
AG1
V1
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
2. Alt 1: OCLKD (O) (#2)
3. Optional GPIO
General purpose I/O 62: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 61: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 60: Options:
1. Alt 0: Reserved
2. Alt 1: UART2_RXD (I) (#2)
3. Optional GPIO
General purpose I/O 59: Options:
1. Alt 0: Reserved
2. Alt 1: UART2_TXD (O) (#2)
3. Optional GPIO
General purpose I/O 58: Options:
1. Alt 0: Reserved
2. Alt 1: Reserved
3. Optional GPIO
General purpose I/O 57: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
V2
3. Optional GPIO
General purpose I/O 56: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
W2
3. Optional GPIO
General purpose I/O 55: Options:
1. Alt 0: Reserved
K29
K28
2. Alt 1: Reserved
3. Optional GPIO
General purpose I/O 54: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 53: Options:
1. Alt 0: Reserved
GPIO_53
GPIO_52
GPIO_51
GPIO_50
GPIO_49
GPIO_48
GPIO_47
GPIO_46
GPIO_45
GPIO_44
GPIO_43
W3
B8
2. Alt 1: LED_DRIVER_ON (O)
3. Optional GPIO
General purpose I/O 52: Options:
1. Alt 0: Reserved
2. Alt 1: N/A
W4
V5
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
3. Optional GPIO
General purpose I/O 51: Options:
1. Alt 0: Reserved
2. Alt 1: DMD_PWR_EN (O)
3. Optional GPIO
General purpose I/O 50: Options:
1. Alt 0: SSP0_CSZ_3 (O)
2. Alt 1: N/A
AC29
AC30
AB26
AB28
K27
3. Optional GPIO
General purpose I/O 49: Options:
1. Alt 0: SSP0_CSZ_4 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 48: Options:
1. Alt 0: USB OTG External USB Switch Control (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 47: Options:
1. Alt 0: PM_ADDR_23 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 46: Options:
1. Alt 0: Reserved
2. Alt 1: SSP2_BC_CSZ (O-MST/I-SLV)
3. Optional GPIO
General purpose I/O 45: Options:
1. Alt 0: Reserved
J30
2. Alt 1: SSP2_CSZ_2 (O-MST/I-SLV)
3. Optional GPIO
General purpose I/O 44: Options:
1. Alt 0: OCLKC (O) (#1)
J29
2. Alt 1: SSP2_CSZ_1 (O-MST/I-SLV)
3. Optional GPIO
General purpose I/O 43: Options:
1. Alt 0: OCLKD (O) (#1)
J27
2. Alt 1: SSP2_CSZ_0 (O-MST/I-SLV)
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 42: Options:
1. Alt 0: IIC2_SDA (B) (#1)
2. Alt 1: SSP2_DO (O)
3. Optional GPIO
GPIO_42
GPIO_41
GPIO_40
GPIO_39
GPIO_38
GPIO_37
GPIO_36
GPIO_35
GPIO_34
GPIO_33
GPIO_32
J26
B8
General purpose I/O 41: Options:
1. Alt 0: IIC2_SCL (B) (#1)
2. Alt 1: SSP2_DI (I)
H30
H29
H28
H27
H26
G30
G29
Y1
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
3. Optional GPIO
General purpose I/O 40: Options:
1. Alt 0: MEMAUX_1 (O) (#1)
2. Alt 1: SSP2_SCLK (O-MST/I-SLV)
3. Optional GPIO
General purpose I/O 39: Options:
1. Alt 0: UART2_RXD (I) (#1)
2. Alt 1: HBT_CLKOUT (O)
3. Optional GPIO
General purpose I/O 38: Options:
1. Alt 0: UART2_TXD (O) (#1)
2. Alt 1: HBT_DO (O)
3. Optional GPIO
General purpose I/O 37: Options:
1. Alt 0: Reserved
2. Alt 1: DAO_CLKOUT (O)
3. Optional GPIO
General purpose I/O 36: Options:
1. Alt 0: Reserved
2. Alt 1: DAO_DO_1 (O)
3. Optional GPIO
General purpose I/O 35: Options:
1. Alt 0: OCLKC (O) (#2)
2. Alt 1: DAO_DO_0 (O)
3. Optional GPIO
General purpose I/O 34: Options:
1. Alt 0: WRP_CAMERA_TRIG (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 33: Options:
1. Alt 0: PAUX11 (O)
Y2
2. Alt 1: IIC2_SDA (B) (#2)
3. Optional GPIO
General purpose I/O 32: Options:
1. Alt 0: PAUX10 (O)
Y4
2. Alt 1: IIC2_SCL (B) (#2)
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 31: Options:
1. Alt 0: PAUX9 (O)
GPIO_31
GPIO_30
GPIO_29
GPIO_28
GPIO_27
GPIO_26
GPIO_25
GPIO_24
GPIO_23
GPIO_22
GPIO_21
Y5
B8
2. Alt 1: PAUX_INT3 (O)
3. Optional GPIO
General purpose I/O 30: Options:
1. Alt 0: PAUX8 (O)
AA1
AA2
AA3
AA4
AA5
AB2
AB3
AB4
AB5
P3
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
2. Alt 1: PAUX_INT2 (O)
3. Optional GPIO
General purpose I/O 29: Options:
1. Alt 0: PAUX7 (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 28: Options:
1. Alt 0: PAUX6 (O)
2. Alt 1: LEDSEL_4 (O)
3. Optional GPIO
General purpose I/O 27: Options:
1. Alt 0: PAUX5 (O)
2. Alt 1: LEDSEL_3 (O)
3. Optional GPIO
General purpose I/O 26: Options:
1. Alt 0: PAUX4 (O)
2. Alt 1: LEDSEL_2 (O)
3. Optional GPIO
General purpose I/O 25: Options:
1. Alt 0: PAUX3 (O)
2. Alt 1: LEDSEL_1 (O)
3. Optional GPIO
General purpose I/O 24: Options:
1. Alt 0: PAUX2 (O)
2. Alt 1: LEDSEL_0 (O)
3. Optional GPIO
General purpose I/O 23: Options:
1. Alt 0: PAUX1 (O) {SEQ Index}
2. Alt 1: PAUX_INT1 (O)
3. Optional GPIO
General purpose I/O 22: Options:
1. Alt 0: PAUX0 (O)
2. Alt 1: PAUX_INT0 (O)
3. Optional GPIO
General purpose I/O 21: Options:
1. Alt 0: PWM-IN1 (I)
2. Alt 1: N/A
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 20: Options:
1. Alt 0: PWM-IN0 (I)
2. Alt 1: N/A
GPIO_20
GPIO_19
GPIO_18
GPIO_17
GPIO_16
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
P2
B8
3. Optional GPIO
General purpose I/O 19: Options:
1. Alt 0: IR1 (I)
P1
R5
R4
R2
R1
T3
T4
T5
T2
V3
B8
B8
B8
B8
B8
B8
B8
B8
B8
B8
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 18: Options:
1. Alt 0: IR0 (I)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 17: Options:
1. Alt 0: N/A
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 16: Options:
1. Alt 0: UART1_RTSZ (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 15: Options:
1. Alt 0: UART1_CTSZ (I)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 14: Options:
1. Alt 0: UART1_RXD (I)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 13: Options:
1. Alt 0: UART1_TXD (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 12: Options:
1. Alt 0: IIC1_SDA (B)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 11: Options:
1. Alt 0: IIC1_SCL (B)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 10: Options:
1. Alt 0: SAS_INTGTR_EN (O)
2. Alt 1: N/A
3. Optional GPIO
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表5-10. GPIO Peripheral Interface (continued)
PIN
TYPE(1)
DESCRIPTION(2) (3) (4)
NAME
NO.
General purpose I/O 09: Options:
1. Alt 0: SAS_CSZ (O)
2. Alt 1: N/A
GPIO_09
GPIO_08
GPIO_07
GPIO_06
GPIO_05
GPIO_04
GPIO_03
GPIO_02
GPIO_01
GPIO_00
U1
B8
3. Optional GPIO
General purpose I/O 08: Options:
1. Alt 0: SAS_DO (O)
2. Alt 1: N/A
U2
U4
B8
B8
B8
B8
B8
B8
B8
B8
B8
3. Optional GPIO
General purpose I/O 07: Options:
1. Alt 0: SAS_DI (I)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 06: Options:
1. Alt 0: SAS_CLK (O)
2. Alt 1: N/A
V4
3. Optional GPIO
General purpose I/O 05: Options:
1. Alt 0: SSP1_CSZ_2 (O-MST/I-SLV)
2. Alt 1: N/A
A17
B17
B15
C16
D16
E16
3. Optional GPIO
General purpose I/O 04: Options:
1. Alt 0: SSP1_CSZ_1 (O-MST/I-SLV)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 03: Options:
1. Alt 0: SSP1_CSZ_0 (O-MST/I-SLV)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 02: Options:
1. Alt 0: SSP1_DO (O)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 01: Options:
1. Alt 0: SSP1_DI (I)
2. Alt 1: N/A
3. Optional GPIO
General purpose I/O 00: Options:
1. Alt 0: SSP1_SCLK (O-MST/I-SLV)
2. Alt 1: N/A
3. Optional GPIO
(1) See 表5-13 for more information on I/O definitions.
(2) This table defines the GPIO capabilities of the DLPC6540. Please see 节7.3.6 for specific product configuration allocations of these
GPIO.
(3) Most GPIO have at least one alternate hardware functional use in addition to being available as a general purpose I/O. Depending on
the product configuration, GPIO may be reserved specifically for use as an alternate hardware function (and would therefore not be
available as a general purpose I/O). More information on GPIO allocations for specific product configurations can be found in 节7.3.6.
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(4) All GPIO that are available as a general purpose I/O must be configured as an input, a standard output, or an open-drain output. This
is set in the flash configuration. Configure unused GPIO as a logic zero output and leave unconnected, otherwise an external pullup or
pulldown resistor is required to avoid a floating input. The reset default for all GPIO is as an input signal.
An external pullup resistor (≤10 kΩ) is required for each signal configured as open-drain output.
表5-11. Clock and Support
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AJ18
AK18
B16
REFCLKA_I
REFCLKA_O
REFCLKB_I
REFCLKB_O
I9
Crystal A Input: Reference clock crystal input(2) (3)
O10
I14
Crystal A Output: Reference clock crystal output(2)
Crystal B Input: Reference clock crystal input(2) (3)
Crystal B Output: Reference clock crystal output(2)
A16
O15
General Purpose Output Clock A (4)
Targeted for driving Color Wheel motor controller. Frequency is software programmable, with a
power-up default frequency of 0.77 MHz.
OCLKA
AD30
O8
Note: The output frequency is not affected by non-power-up reset operations (that is, the
system holds the last programmed value until system is power cycled).
(1) See 表5-13 for more information on I/O definitions.
(2) For more information on this signal see 节6.11.
(3) For applications where an external oscillator is used in place of a crystal, use an oscillator to drive this pin.
(4) For more information on this signal see 节6.19.
表5-12. Power and Ground
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1.15-V digital power for MCG (Master Clock Generator A)
PLL
VDD115_PLLMA
AE18
PWR
1.15-V digital power for MCG (Master Clock Generator B)
PLL
VDD115_PLLMB
VAD115_PLLS
VAD18_PLLMA
F15
PWR
PWR
PWR
F16
1.15-V analog power for SCG doubler PLL
1.8-V analog power for MCG (Master Clock Generator A)
PLL
AE19
1.8-V analog power for MCG (Master Clock Generator B)
PLL
VAD18_PLLMB
F14
PWR
VAD33_OSCA
VAD33_OSCB
VAD115_FPD
VDD33_FPD
VAD115_VX1
VAD18_VX1
VAD33_USB
VDD18_SCS
VDD121_SCS
Y18
L17
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
3.3-V analog power for Crystal-OSC
3.3-V analog power for Crystal-OSC
1.15-V analog power for FPD
3.3-V digital power for FPD
F7,F9,F11,J6,L12
E6,E8,E10,E12,E14,G6,L11,L13
F24,L18
1.15-V analog power for VX1
1.8-V analog power for VX1
E18,L19
D27,E26,F25
3.3-V analog power for USB
L16,R6,T25,AE16
L15,N11,P20,U11,V20,Y16
1.8-V digital power for SCS DRAM
1.21-V digital power for SCS SRAM
Y14,Y19,AF7,AF9,AF11,AF13AF21,A
F23,AF25
VAD115_HSSI
PWR
1.15-V analog power for HSSI interface
VAD115_HSSI0_PLL
VAD115_HSSI1_PLL
VDD33_HSSI
AE22
PWR
PWR
PWR
PWR
1.15-V analog power for HSSI-0 PLL
AE10
1.15-V analog power for HSSI-1 PLL
Y12,Y20,AE8,AE12,AE20,AE24
Y15,AE13,AE14
AF16
3.3-V digital power for HSSI interface
VAD18_LSIF
1.8-V analog power for DMD low-speed interface
Manufacturing test use only; must be left open-unconnected
LVDS_VREFTEST
L14,L20,M11,N20,P11,R20,T11,U20,
V11,W20,Y11,Y13,Y17
VDD115
PWR
1.15-V core power
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表5-12. Power and Ground (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
H25,K25,L6,M20,M25,N6,P25,R11,T
20,U6,V25,W6,W11,Y25,AA6,AB25,A
C6,AD25,AE6
VDD33
PWR
3.3-V digital power
A1,A2,A3,A5,A7,A9,A11,A13,A15,A1
8,A20,A22,A24,A26,A28,A30,B1,B2,
B3,B5,B7,B9,B11,B13,B18,B20,B22,
B24,B26,B28,B30,C3,C4,C6,C8,C10,
C12,C14,C17,C19,C21,C23,C25,C29
,D1,D2,D6,D8,D10,D12,D14,D17,D1
9,D21,D23,D25,D28,E3,E4,E5,E7,E9
,E11,E13,E15,E22,E25,E28,F1,F2,F5
,F6,F8,F10,F12,F13,F17,F18,F20,F3
0,G3,G4,G5,G27,H1,H2,H5,H6,J3,J4
,J5,J25.J28,K6,K30,L1,L25,L27,M3,
M6,(M12),(M13),(M14),(M15),(M16),
(M17),(M18),(M19),N1,(N12,(N13),
(N14),(N15),(N16),(N17),(N18),
(N19),N25,N28,P6,(P12),(P13),(P14),
(P15),(P16),(P17),(P18),
(P19),P30,R3,(R12),(R13),(R14),
(R15),(R16),(R17),(R18),
(R19),R25,R27,T1,T6,(T12),(T13),
(T14),(T15),(T16),(T17),(T18),
(T19),U3,U5,(U12),(U13),(U14),
(U15),(U16),(U17),(U18),
(U19),U25,U28,V6,(V12),(V13),(V14),
(V15),(V16),(V17),(V18),
GND for all power supplies. Ball numbers in parenthesis are
also used as thermal balls and are located within the
package center region.
VSS
RTN
(V19),V30,W1,W5,(W12),(W13),
(W14),(W15),(W16),(W17),(W18),
(W19),W25,W27,Y3,Y6,AA25,AA28,
AB1,AB6,AB30,AC3,AC25,AC27,AD
6,AE1,AE5,AE7,AE9,AE11,AE15,AE
17,AE21,AE23,AE25,AE26,AE28,AF
3,AF5,AF6,AF8,AF10,AF12,AF14,AF
15,AF17,AF18,AF19,AF20,AF22,AF2
4,AF26,AF28,AF30,AG4,AG6,AG8,A
G10,AG12,AG14,AG16,AG18,AG23,
AG25,AG27,AG29,AH1,AH2,AH3,AH
4,AH6,AH8,AH10,AH12,AH14,AH16,
AH18,AH21,AH23,AH25,AH27,AH29,
AH30,AJ1,AJ3,AJ5,AJ7,AJ9,AJ11,AJ
13,AJ15,AJ17,AJ22,AJ24,AJ26,AJ28
,AJ30,AK1,AK3,AK5,AK7,AK9,AK11,
AK13,AK15,AK17,AK22,AK24,AK26,
AK28,AK30
VPGM
G25
Manufacturing use only (efuse); must be tied to ground
(1) See 表5-13 for more information on I/O definitions.
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表5-13. I/O Type Subscript Definition
TYPE
SUPPLY REFERENCE
ESD STRUCTURE
SUBSCRIPT
DESCRIPTION
1
1.8 V SERDES (VX1)
VAD18_VX1
VAD18_LSIF
VAD18_LSIF
VDD33
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to GND
2
1.8-V LVDS (LS DMD)
3
1.8-V LMCMOS (LS DMD)
3.3-V OpenDrain (VX1)
3.3-V LVDS (FPD)
4
5
VDD33_FPD
VDD33_FPD
VAD115_HSSI
VDD33
6
3.3-V LVCMOS (PP)
7
1.15-V HSSI (HS DMD)
3.3-V LVCMOS I/O (8ma output drive - GPIO, etc. )
3.3-V LVCMOS I/O (OSC)
3.3-V LVCMOS I/O (OSC)
3.3-V USB (USB)
8
9
VAD33_OSCA
VAD33_OSCA
VAD33_USB
VAD33_USB
VDD33
10
ESD diode to supply rail and GND
ESD diode and LBJT to GND
ESD diode to supply rail and GND
ESD diode to supply rail and GND
ESD diode to GND
11
12
3.3-V LVCMOS (USB)
13
3.3-V OpenDrain (I2C)
14
3.3-V LVCMOS I/O (OSC)
3.3-V LVCMOS I/O (OSC)
VAD33_OSCB
VAD33_OSCB
15
ESD diode to supply rail and GND
TYPE
I
Input
O
Output
B
Bidirectional
Power
N/A
PWR
RTN
Ground return
表5-14. Internal Pullup and Pulldown Characteristics(1)
INTERNAL PULLUP AND PULLDOWN
RESISTOR CHARACTERISTICS
CONDITIONS
MIN
MAX
UNIT
19
12
50
39
VIN = 0.8 V, VDD33 = 3.3 V
VIN = 2.0 V, VDD33 = 3.3 V
kΩ
kΩ
Weak pullup resistance
(1) An external 5.7-kΩor less pullup or pulldown resistor (if needed) is sufficient for any voltage condition to correctly override any
associated internal pullup or pulldown resistance.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature (unless otherwise noted)(1)
SUPPLY VOLTAGE(2)
MIN
MAX
1.6
1.6
1.6
1.6
1.6
1.5
1.6
1.6
1.6
UNIT
V
V(VDD115) (Core)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.5
–0.3
–0.3
–0.3
–0.4
–0.3
–0.3
–0.5
–0.4
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V(VDD115_PLLMA) (Core)
V(VDD115_PLLMB) (Core)
V(VDD115_PLLS) (Core)
V(VAD115_FPD) (Core)
V(VAD115_VX1) (Core)
V(VAD115_HSSI) (Core)
V(VAD115_HSSI0_PLL) (Core)
V(VAD115_HSSI1_PLL) (Core)
V(VDD121_SCS) (Core)
V(VAD18_PLLMA) (Core)
V(VAD18_PLLMB) (Core)
V(VAD18_VX1) (I/O)
V
V
V
V
V
V
V
V
1.6
2.5
2.5
2.5
2.3
2.5
3.9
3.9
3.9
3.9
3.9
3.9
V
V
V
V
V(VDD18_SCS) (Core)
V(VDD18_LVDS) (I/O)
V(VDD33) (I/O)
V
V
V
V(VAD33_OSCA) (I/O)
V(VAD33_OSCB) (I/O)
V(VDD33_FPD) (I/O)
V
V
V
V(VAD33_USB) (I/O)
V
V(VDD33_HSSI) (I/O)
GENERAL
V
TJ
Operating junction temperature
0
0
115
108(3)
100
°C
°C
TC
Ilat
Operating case temperature
Latch-up
mA
°C
–100
-40
Tstg
Storage temperature range
125
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to GND.
(3) Value calculated using package parameters defined in 节6.4.
6.2 ESD Ratings
PARAMETER
VALUE
±1000
±750
UNIT
All pins (except
Vx1_CM_CKREF0, 1, 2, 3)
Human body model (HBM), per
ANSI-ESDA-JEDEC JS-001(1)
Vx1_CM_CKREF0, 1, 2, 3
Electrostatic
discharge
V(ESD)
All pins (except
Vx1_CM_CKREF0, 1, 2, 3)
V
±500
Charged device model (CDM),
per ANSI-ESDA-JEDEC
JS-002(2)
+500
-200
Vx1_CM_CKREF0, 1, 2, 3
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TOLERANCE
MIN
NOM
MAX
UNIT
V(VDD115) (Core)
V(VDD115_PLLMA) (Core)
1.15-V Power
± 4.35% tolerance
1.10
1.15
1.20
V
1.15-V Digital Power -
MCG-A PLL
(Master Clock
Generator)
+4.35/-9.13%
tolerance
1.045
1.045
1.15
1.15
1.20
1.20
V
V
V(VDD115_PLLMB) (Core)
1.15-V Digital Power -
MCG-B PLL
(Master Clock
Generator)
+4.35/-9.13%
tolerance
V(VDD115_PLLS) (Core)
V(VAD115_FPD) (Core)
V(VAD115_VX1) (Core)
V(VAD115_HSSI) (Core)
ΔV(VAD115_HSSI) (Core)
1.15-V Analog Power +4.35/-9.13%
- SCG Doubler PLL tolerance
1.045
1.045
1.045
1.045
1.15
1.15
1.15
1.15
1.20
1.20
1.20
1.20
V
V
V
V
1.15-V Analog Power +4.35/-9.13%
- FPD tolerance
1.15-V Analog Power +4.35/-9.13%
- VX1 tolerance
1.15-V Analog Power +4.35/-9.13%
- HSSI
tolerance
pk-pkVAD115_HSSI
supply noise @ 10
MHz (sine)
20
mV
V
V(VAD115_HSSI0_PLL) (Core)
1.15-V Analog Power +4.35/-9.13%
1.045
1.045
1.15
1.15
1.20
- HSSI0 PLL
tolerance
pk-
ΔV(VAD115_HSSI0_PLL) (Core)
pkVAD115_HSSI0_P
LL supply noise @ 10
MHz (sine)
20
mV
V
V(VAD115_HSSI1_PLL) (Core)
1.15-V Analog Power +4.35/-9.13%
1.20
20
- HSSI1 PLL
tolerance
pk-
ΔV(VAD115_HSSI1_PLL) (Core)
pkVAD115_HSSI1_P
LL supply noise @ 10
MHz (sine)
mV
V
1.21V Digital Power - +7.43/-4.95%
V(VDD121_SCS) (Core)
V(VAD18_PLLMA) (Core)
1.15
1.71
1.21
1.80
1.30
1.89
SCS DRAM
tolerance
1.8-V Analog Power -
MCG-A PLL
(Master Clock
Generator)
±5.0% tolerance
V
V(VAD18_PLLMB) (Core)
1.8-V Analog Power -
MCG-B PLL
±5.0% tolerance
1.71
1.80
1.89
V
(Master Clock
Generator)
V(VAD18_VX1) (I/O)
V(VDD18_SCS) (Core)
V(VDD18_LVDS) (I/O)
V(VDD33) (I/O)
1.8-V Analog Power -
VX1 Interface
±5.0% tolerance
±5.0% tolerance
±5.0% tolerance
1.71
1.71
1.71
1.80
1.80
1.80
1.89
1.89
1.89
V
V
V
1.8-V Digital Power -
SCS DRAM
1.8-V Analog Power -
DMD LS Interface
3.3-V Digital Power -
(All 3.3-V I/O without
dedicated 3.3-V
±5.0% tolerance
±5.0% tolerance
3.135
3.135
3.3
3.3
3.465
3.465
V
V
supply - e.g. GPIO)
V(VAD33_OSCA) (I/O)
3.3-V Analog Power -
Crystal-OSCA
Interface
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6.3 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TOLERANCE
MIN
NOM
MAX
UNIT
V(VAD33_OSCB) (I/O)
3.3-V Analog Power -
Crystal-OSCB
Interface
±5.0% tolerance
3.135
3.3
3.465
V
V(VDD33_FPD) (I/O)
V(VAD33_USB) (I/O)
V(VDD33_HSSI) (I/O)
ΔV(VDD33_HSSI) (I/O)
3.3-V Digital Power -
FPD interface
±5.0% tolerance
±5.0% tolerance
±5.0% tolerance
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
V
V
V
3.3-V Analog Power -
USB Interface
3.3-V Digital Power -
DMD HSSI Interface
pk-pkVDD33_HSSI
supply noise @ 10
MHz (sine)
60
mV
GENERAL
Operating junction
temperature
TJ
0
0
0
115
108
55
°C
°C
°C
Operating case
temperature
TC
TA
Operating ambient
temperature (1) (2)
(1) The operating ambient temperature range values were determined based on the board design parameters described in 节9.1.1 ,
rather than using a JEDEC JESD51 standard test card and environment, along with min and max estimated power dissipation across
process, voltage, and temperature. Ambient thermal conditions, which impact RθJA, vary by application. Thus, maximum operating
ambient temperature varies by application.
a. Ta_min = Tj_min –(Pd_min × RθJA) = 0°C –(host_min_valueW × host_value°C/W) = –host_calculated_value°C
b. Ta_max = Tj_max –(Pd_max × RθJA) = +115°C –(host_max_valueW × host_value°C/W) = +host_calculated_value°C
(2) Operating ambient temperature is dependent on system thermal design. Operating case temperature cannot exceed its specified
range across ambient temperature conditions.
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6.4 Thermal Information
ZDC
P-HBGA676
UNIT
THERMAL METRIC (1)
TEST CONDITIONS (2)
676 PINS (576
Populated)
0 m/s of forced airflow, without heat-sink
1 m/s of forced airflow, without heat-sink
2 m/s of forced airflow, without heat-sink
1 m/s of forced airflow, with heat-sink, 7 W
2 m/s of forced airflow, with heat-sink, 7 W
1 m/s of forced airflow, with heat-sink,15 W
2 m/s of forced airflow, with heat-sink, 15 W
7.4
6.3
6.0
5.3
4.8
4.0
3.5
Junction-to-air thermal
RθJA
°C/W
resistance (3)
Junction-to-case thermal
RJC
2.7
3.5
°C/W
°C/W
resistance (4)
Junction-to-board thermal
RJB
resistance (4)
Temperature variance from
junction to package top center
temperature, per unit power
dissipation.
0 m/s of forced airflow, without heat-sink
1 m/s of forced airflow, without heat-sink
2 m/s of forced airflow, without heat-sink
0.6
0.6
0.6
(5)
°C/W
W
ψJT
0 m/s of forced airflow, without heat-sink
8.10
9.52
10.00
PMAX
Package - Maximum Power(3) (6) 1 m/s of forced airflow, without heat-sink
2 m/s of forced airflow, without heat-sink
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) These test conditions also included a PCB sized at 101.3mm x 152.4mm incorporating the recommended PCB thermal enhancements
specified in 节9.1.1. In addition, airflow is parallel to the board surface directed at the device.
(3) See 表6-1 for thermal parameters based on the example heat-sinks listed below
a. Heatsink-7 W: S1525-7W, Size = 25 mm x 25 mm x 7 mm, Pins = 7 x7 = 49 (Vendor: Alpha, Type S Series)
b. Heatsink-15 W: S1530-15W, Size = 30 mm x 3 0mm x 15 mm, Pins = 8 x 8 = 64 (Vendor: Alpha, Type S Series)
(4) Due to the complex internal construction of the DLPC6540 controller, the RJC and RJB thermal coefficients do not always produce an
accurate junction temperature estimate. A limited set of comparison scenario data shows that the RJC and RJB modeled junction
temperature can have a +9% to -2% error vs the actual temperature. The amount of this error varies with the use and size of an
external heat sink as well as the amount of external air flow. Validate all thermal estimates based on RJC and RJB with an actual
temperature measurement at the top-center of the package plus the delta-temp defined by ψJT
(5) Example: Using the power we expect of 11.31 W
.
11.31 W * 0.6 °C/W = 6.786 °C = > TC-max = 115 °C - ~7 °C = 108 °C
(6) PMAX = (TJ-max - TA-max) / RθJA
表6-1. Thermal Examples using Two Different Heat-sinks
ZDC
THERMAL METRIC (1)
TEST CONDITIONS
P-HBGA676
UNIT
°C/W
W
676 PINS (576 Populated)
1 m/s of forced airflow, with heat-sink, 7 W
2 m/s of forced airflow, with heat-sink, 7 W
1 m/s of forced airflow, with heat-sink, 15 W
2 m/s of forced airflow, with heat-sink, 15 W
5.3
4.8
4.0
3.5
Junction-to-air thermal
resistance
RθJA
1 m/s of forced airflow, with heat-sink, 7 W
2 m/s of forced airflow, with heat-sink, 7 W
1 m/s of forced airflow, with heat-sink, 15 W
2 m/s of forced airflow, with heat-sink, 15 W
11.32
12.50
15.00
17.14
PMAX
Package - Maximum Power
(1) This table show examples of what is achievable based on the two example heat-sinks.
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6.5 Power Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(1)
UNIT
V(VDD115)
1.15-V Power
Maximum current at VDD115 = 1.2 V
5640
mA
V(VDD115_PLLMA) (Core) 1.15-V Digital Power
MCG-A PLL
Maximum current at VDD115_PLLMA =
1.2 V
6
mA
(Master Clock Generator)
V(VDD115_PLLMB) (Core) 1.15-V Digital Power
MCG-B PLL
Maximum current at VDD115_PLLMB =
1.2 V
6
3
mA
mA
mA
(Master Clock Generator)
V(VDD115_PLLS) (Core)
V(VAD115_FPD) (Core) (2)
1.15-V Analog Power
SCG Doubler PLL
Maximum current at VDD115_PLLS =
1.2 V
Maximum current at VAD115_FPD = 1.2
V
Ports A and B Active, Port C inactive
1.15-V Analog Power
FPD
99
V(VAD115_VX1) (Core) (2)
Maximum current at VAD115_VX1 = 1.2
V
8 Lanes, with total BW = 3.0Gbps)
1.15-V Analog Power
VX1
400
462
1
mA
mA
mA
V(VAD115_HSSI) (Core)
Maximum current at VDD115_HSSI =
1.2 V
Both ports active
1.15-V Digital Power
HSSI
V(VAD115_HSSI0_PLL)
(Core)
Maximum current at
VDD115_HSSI0_PLL = 1.2 V
Both ports active
1.15-V Digital Power
HSSI0 PLL
V(VAD115_HSSI1_PLL)
(Core)
Maximum current at
VDD115_HSSI1_PLL = 1.2 V
Both ports active
1.15-V Digital Power
HSSI1 PLL
1
mA
mA
mA
1.21V Digital Power
SCS DRAM
Maximum current at VDD121_SCS =
1.30 V
V(VDD121_SCS) (Core)
V(VAD18_PLLMA) (Core)
334
10
1.8-V Analog Power
MCG-A PLL
(Master Clock Generator)
Maximum current at VAD18_PLLMA =
1.89 V
V(VAD18_PLLMB) (Core)
1.8-V Analog Power
MCG-B PLL
(Master Clock Generator)
Maximum current at VAD18_PLLMB =
1.89 V
10
41
mA
mA
V(VAD18_VX1) (I/O) (2)
Maximum current at VAD18_VX1 = 1.89
V
8 Lanes, with total BW = 3.0Gbps
1.8-V Analog Power
VX1 Interface
V(VDD18_SCS) (Core)
V(VDD18_LVDS) (I/O)
V(VDD33) (I/O)
1.8-V Digital Power
SCS DRAM
Maximum current at VDD18_SCS =
1.89 V
327
31
mA
mA
1.8-V Analog Power
DMD LS Interface
Maximum current at VDD18_LVDS =
1.89 V
3.3-V Digital Power - (All
3.3-V I/O without
dedicated 3.3-V supply -
e.g. GPIO)
Maximum current at VDD33 = 3.3456 V
28
mA
V(VAD33_OSCA) (I/O)
V(VAD33_OSCB) (I/O)
V(VDD33_FPD) (I/O) (2)
3.3-V Analog Power
Crystal/OSCA Interface
Maximum current at VDD33_OSCA =
3.3456 V
5
5
mA
mA
3.3-V Analog Power
Crystal-OSCB Interface
Maximum current at VDD33_OSCB
=3.3456 V
Maximum current at VDD33_FPD =
3.3456 V
Ports A and B Active, Port C inactive
3.3-V Digital Power
FPD interface
102
78
mA
mA
V(VAD33_USB) (I/O)
3.3-V Analog Power
USB Interface
Maximum current at VDD33_USB
=3.3456 V
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Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(1)
UNIT
V(VDD33_HSSI) (I/O)
Maximum current at VDD33_HSSI =
3.3456 V
Both ports active, with total BW =
3.0Gbps
3.3-V Digital Power
DMD HSSI Interface
194
mA
(1) Vendor estimate for worst case power PVT condition = corner process, high voltage, high temperature (115°C junction).
(2) The V-by-One interface and FPD-Link receivers are never intended to be simultaneously enabled . Always disable one of these
interfaces.
6.6 Pin Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
1.05
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
3.3 V LVCMOS
0.8 ×
(I/O type 6 - FPD)
VDD33_FPD
3.3 V LVCMOS
(I/O type 6 - PP)
2.0
High-level input
threshold voltage
VIH
V
3.3 V LVCMOS
(I/O type 8 - GPIO)
2.0
2.0
3.3 V LVCMOS
(I/O type 9 - OSCA)
3.3 V LVCMOS
(I/O type 10 -
OSCB)
2.0
3.3 V OpenDrain
(I/O type 13 - I2C)
0.7 × VDD33
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
0.6
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
3.3 V LVCMOS
(I/O type 6 - FPD)
0.2 × VDD33_FPD
0.8
3.3 V LVCMOS
(I/O type 6 - PP)
Low-level input
threshold voltage
VIL
V
3.3 V LVCMOS
(I/O type 8 - GPIO)
0.8
0.8
3.3 V LVCMOS
(I/O type 9 - OSCA)
3.3 V LVCMOS
(I/O type 10 -
OSCB)
0.8
3.3 V OpenDrain
(I/O type 13 - I2C)
0.3 × VDD33
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6.6 Pin Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
VIN = VAD18_LSIF
10
–10
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
-10
N/A
10
3.3 V LVCMOS
(I/O type 6 - PP)
High-level input
current
3.3 V LVCMOS
(I/O type 8 - GPIO)
IIH
VIN = VDD33
VIN = VDD33
10
µA
µA
V
–10
–10
3.3 V LVCMOS
(I/O type 9 - OSCA)
10
3.3 V LVCMOS
(I/O type 10 -
OSCB)
VIN = VDD33
10
10
10
–10
–10
–10
3.3 V OpenDrain
(I/O type 13 - I2C)
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
VIN = VSS
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
–10
–10
–10
N/A
10
3.3 V LVCMOS
(I/O type 6 - PP)
Low-level input
current
3.3 V LVCMOS
(I/O type 8 - GPIO)
IIL
VIN = VSS
VIN = VSS
10
3.3 V LVCMOS
(I/O type 9 - OSCA)
10
3.3 V LVCMOS
(I/O type 10 -
OSCB)
VIN = VSS
10
10
–10
–10
3.3 V OpenDrain
(I/O type 13 - I2C)
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
VDD18 - 0.6
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
N/A
3.3 V LVCMOS
(I/O type 6 - PP)
High-level output
voltage
3.3 V LVCMOS
(I/O type 8 - GPIO)
VOH
IOH = 8 mA
VDD33 - 0.6
N/A
3.3 V LVCMOS
(I/O type 9 - OSCA)
3.3 V LVCMOS
(I/O type 10 -
OSCB)
N/A
N/A
3.3 V OpenDrain
(I/O type 13 - I2C)
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6.6 Pin Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
0.4
3.3 V OpenDrain
(I/O type 4 - VX1)
IOL = 8 mA
0.4
N/A
0.4
3.3 V LVCMOS
(I/O type 6 - PP)
Low-level output
voltage
3.3 V LVCMOS
(I/O type 8 - GPIO)
VOL
IOH
IOL
IOL = 8 mA
V
3.3 V LVCMOS
(I/O type 9 - OSCA)
N/A
3.3 V LVCMOS
(I/O type 10 -
OSCB)
N/A
0.4
3.3 V OpenDrain
(I/O type 13 - I2C)
3-mA sink
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
N/A
3.3 V OpenDrain
(I/O type 4 - VX1)
N/A
N/A
8
3.3 V LVCMOS
(I/O type 6 - PP)
High-level output
current
3.3 V LVCMOS
(I/O type 8 - GPIO)
VOH = VDD33 - 0.6 V
mA
3.3 V LVCMOS
(I/O type 9 - OSCA)
N/A
N/A
N/A
3.3 V LVCMOS
(I/O type 10 -
OSCB)
N/A
N/A
N/A
8
3.3 V OpenDrain
(I/O type 13 - I2C)
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
3.3 V OpenDrain
(I/O type 4 - VX1)
VOL = 0.4 V
VOL = 0.4 V
3.3 V LVCMOS
(I/O type 6 - PP)
N/A
Low-level output
current
3.3 V LVCMOS
(I/O type 8 - GPIO)
8
mA
3.3 V LVCMOS
(I/O type 9 - OSCA)
N/A
N/A
N/A
-
3.3 V LVCMOS
(I/O type 10 -
OSCB)
N/A
6
3.3 V OpenDrain
(I/O type 13 - I2C)
VOL = 0.6 V
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6.6 Pin Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.8 V LVCMOS
(I/O type 3 - LS
DMD)
N/A
3.3 V OpenDrain
(I/O type 4 - VX1)
10
10
–10
–10
–10
N/A
3.3 V LVCMOS
(I/O type 6 - PP)
High-impedance
leakage current
3.3 V LVCMOS
(I/O type 8 - GPIO)
IOZ
VOUT = VDD33
10
µA
3.3 V LVCMOS
(I/O type 9 - OSCA)
N/A
3.3 V LVCMOS
(I/O type 10 -
OSCB)
N/A
N/A
N/A
N/A
3.3 V OpenDrain
(I/O type 13 - I2C)
(1) The number inside each parenthesis for the I/O refers to the type defined in 表5-13.
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6.7 DMD HSSI Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
400
590
NOM
MAX
1000
1000
UNIT
Output Peak-to-Peak Differential (1)
VDIFF
Data
mVppd
mVppd
(into floating load RLOAD = 100 Ω)
Clock
Output common mode
VCM
200
700
mV
(into floating load RLOAD = 100 Ω)
Output differential voltage(1)
(into floating load RLOAD = 100 Ω)
Data
200
295
80
500
500
120
60
mV
mV
Ω
|VOD
|
Clock
RDIFF
Differential termination resistance
Single-ended termination resistance
100
50
RTERM
40
Ω
Differential output return loss
(100 MHz to 0.75 × Baud)
SDD22
SCC22
NCM
-8
-6
dB
dB
Common mode return loss
(100 MHz to 0.75 × Baud)
(7.5% × VDIFF) +
25 mV
Transmitter common mode noise
mVppd
DJDATA
DJCLOCK
DCD
Deterministic jitter data (non-DCD)
Deterministic jitter clock (non-DCD)
Duty cycle distortion
0.20
0.16
0.05
0.30
UI pp
UI pp
UI pp
UI pp
TJ
Total jitter (random + DJ)
(1) VDIFF-pp = (Vp - Vn)cycle_N - (Vp - Vn)cycle_N+1 = 2 × |VOD
|
See 图6-1.
Vp
|VOD/2|
|VOD/2|
|VOD/2|
|VOD/2|
VCM
Vn
|VOD|
图6-1. HSSI Differential Voltage Parameters
6.8 DMD Low-Speed LVDS Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
340
NOM
MAX
600
UNIT
mVppd
mV
Output peak-to-peak differential
(into RLOAD = 100 Ω)
VDIFF
VCM
VAD18_LSIF (I/O type 2)
Steady-state common mode voltage
VAD18_LSIF (I/O type 2)
VAD18_LSIF (I/O type 2)
1100
170
1200
1300
300
Differential output voltage
(into RLOAD = 100 Ω)
(1)
|VOD
|
mV
|VOD (Δ) |(2)
VCM (Δ)
VOH
VOD change (between logic states)
VCM change (between logic states)
Single-ended output voltage high (3)
Single-ended output voltage low (3)
Internal differential termination
VAD18_LSIF (I/O type 2)
VAD18_LSIF (I/O type 2)
VAD18_LSIF (I/O type 2)
VAD18_LSIF (I/O type 2)
25
25
mV
mV
mV
mV
Ω
1450
VOL
950
85
Txterm
100
115
(1) VDIFF-pp = (Vp - Vn)cycle_N - (Vp - Vn)cycle_N+1 = 2 × |VOD
|
See 图6-2
(2) |VOD (Δ)| = | | VOD|cycle _N - |VOD|cycle_N+1 |
(3) VOH = 1300 + 300/2 = 1450; VOL = 1100- 300/2 = 950
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Vp
VCM
Vn
|VOD/2|
|VOD/2|
|VOD/2|
|VOD/2|
|VOD|
图6-2. DMD Low-Speed Differential Voltage Parameters
6.9 V-by-One Interface Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
MIN
100
50
NOM
MAX
UNIT
mVppd
mV
VDIFF
|VID|
Input peak-to-peak differential
Differential input voltage
VAD18_VX1 (I/O type 1)
VAD18_VX1 (I/O type 1)
VAD18_VX1 (I/O type 1)
Rxterm
Internal differential termination
80
100
120
Ω
(1) See the V-by-One interface standard for more information
6.10 USB Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) (2)
MIN
NOM
MAX
UNIT
Low-Speed and Full Speed (Input Level)
Single-ended input voltage high
(driven)
VIH
2.0
2.7
V
V
Single-ended input voltage high
(floating)
VIHZ
3.6
0.8
VIL
Single-ended input voltage low
Differential input sensitivity
V
V
V
VDI
VCM
|(DP) - (DM)|
0.2
0.8
Differential common mode voltage
Includes VDI range
2.5
Low-Speed and Full Speed (Output Level)
VOL
Low-level output voltage
0.0
2.8
1.3
0.3
3.6
2.0
V
V
V
with 1.425 KΩpullup to 3.6 V
with 14.25 KΩpulldown
VOH
VCRS
High-level output voltage
Output signal crossover voltage
High-Speed (Input Level)
High-speed squelch detection
threshold
VHSSQ
100
150
mV
(differential signal amplitude)
High-speed disconnect detection
threshold
(differential signal amplitude)
VHSDSC
525
-50
626
500
mV
mV
High-speed data signal common mode
voltage
VHSCM
High-Speed (Output Level)
VHSOI
VHSOH
VHSOL
High-speed idle level
10.0
440
mV
mV
mV
–10.0
360
High-speed data signal - high
High-speed data signal - low
10.0
–10.0
High-speed chirp J level (differential
voltage)
VCHIRPJ
VCHIRPK
700
1100
-500
mV
mV
High-speed chirp K level (differential
voltage)
-900
Termination
RPU
Bus pullup resistor
1.425
14.25
1.575
15.75
KΩ
KΩ
RPD
Bus pulldown resistor
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6.10 USB Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) (2)
MIN
NOM
MAX
UNIT
ZHSDRV
High-speed driver output impedance
40.5
49.5
Ω
(1) Referenced to VAD33_USB (I/O type 11)
(2) When used as a master as part of USB OTG, the DLPC6540 requires an external USB switch to provide the USB 5-V power. The
example shown in 图6-3 uses a TI TPS2500/2501 device. The example figure does not describe the required ancillary components
(such as resistors and capacitors). For this information, refer to the USB switch logic data sheet for the selected device. The external
USB switch is not required for product configurations that support USB slave mode only.
1.8 V to 5.25 V
IN
EN
ENUSB
USB Power Switch
w/ Boost
Converter
USB
(TPS2500 or TPS2501)
GPIO_48
VBUS
Dœ
USB_VBUS
USB_DAT_N
USB_DAT_P
USB_ID
Micro
AB
Receptable
Controller
D+
ID
GND
图6-3. External USB Switch Example for DLPC6540 Controller as USB OTG Master
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6.11 System Oscillator Timing Requirements
PARAMETER
MIN
NOM
40.000
25.000
MAX
UNIT
MHz
ns
Clock frequency, REFCLKA(1) (2)
Cycle time, REFCLKA(1)
PLLA: 40 MHz
PLLA: 40 MHz
39.9960
24.9975
40.0040
25.0025
ƒclock
tc
PLLA: 40 MHz
50% to 50% reference points (signal)
tw(H) Pulse duration(3), REFCLKA, high
tw(L) Pulse duration(3), REFCLKA, low
11.25
11.25
ns
ns
ns
PLLA: 40 MHz
50% to 50% reference points (signal)
PLLA: 40 MHz
20% to 80% reference points (signal)
tt
Transition time(3), REFCLKA, tt = tƒ / tr
2.5
Long term periodic jitter(3), REFCLKA
(that is the deviation in period from
ideal period due solely to high
frequency jitter)
tjp
PLLA: 40 MHz
18
ps
fclock Clock frequency, REFCLKB(1)
tc
Cycle time, REFCLKB(1)
PLLB: 38 MHz
PLLB: 38 MHz
37.9962
26.3132
38.000
38.0038
MHz
ns
26.3157 26.3184
PLLB: 38 MHz
50% to 50% reference points (signal)
tw(H) Pulse duration(3), REFCLKB, high
tw(L) Pulse duration(3), REFCLKB, low
11.84
11.84
ns
ns
ns
PLLB: 38 MHz
50% to 50% reference points (signal)
PLLB: 38 MHz
20% to 80% reference points (signal)
tt
Transition time(3), REFCLKB, tt = tƒ / tr
2.63
18
Long term periodic jitter(3), REFCLKB
(that is the deviation in period from
ideal period due solely to high
frequency jitter)
tjp
PLLB: 38 MHz
ps
(1) The REFCLK inputs do not support spread spectrum clock spreading.
(2) Multi-controller systems require that a single oscillator be used to drive the REFCLKA input for all controllers in the system.
(3) Applies only when driven through an external digital oscillator. This is a 1-sigma RMS value.
tt
tt
tc
tw(H)
tw(L)
80%
20%
80%
20%
50%
50%
REFCLK
50%
图6-4. System Oscillators
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6.12 Power Supply and Reset Timing Requirements
PARAMETER
MIN
MAX
UNIT
Power supply ramp for each supply
Ramp-up time: TOV × 10% to TOV × 90%
TOV = Typical Operational Voltage
Power supply ramp-up time.
(1) 图6-5
tRAMP-UP
0.01
10
ms
Total time within which the 1.15-V, 1.8-V, 1.21-V,
and 3.3-V supplies must complete their ramp-up
from the start of the 1.15-V ramp-up.
Ramp-up time: TOV × 10% to TOV × 90%
TOV = Typical Operational Voltage
Total power supply ramp-up
time.(1)
tRAMP-UP-TOTAL
100
ms
Power supply ramp for each supply
Ramp-down time: TOV × 90% to TOV × 10%
TOV = Typical Operational Voltage
Power supply ramp-down
tRAMP-DOWN
0
100
100
ms
ms
time. (1) 图6-5 图6-6
tRAMP-DOWN-TOTAL Total power supply ramp-
down time.(1)
Total time within which the 1.15-V, 1.8-V, 1.21-V,
and 3.3-V supplies must complete their ramp-
down from the start of the 3.3-V ramp-up.
Ramp-down time: TOV × 90% to TOV × 10%
TOV = Typical Operational Voltage
1.8-V Supply Ramp-up Start
Delay from 1.15-V supply ramp start to 1.8-V
supply ramp start.
tRUSD18
See (3)
10
ms
ms
ms
ms
Delay (2) 图6-6
3.3-V Supply Ramp-up Start
Delay (2) 图6-6
Delay from 1.15-V supply ramp start to 3.3-V
supply ramp start
tRUSD33
50
1.21-V Supply Ramp-up Start
Delay (2) 图6-6
Delay from 1.8-V supply ramp start to 1.21-V
supply ramp start.
tRUSD12
See (4)
1.8-V Supply Ramp-down
Start Delay (2) 图6-6
Delay from 1.21-V supply ramp start to 1.8-V
supply ramp start.
tRDSD18
See (5)
See(8)
tRDSD115
1.15-V Supply Ramp-down
Start Delay (2) 图6-6
Delay from 3.3-V supply ramp start to 1.15-V
supply ramp start.
PWRGOOD goes inactive low (as an early
warning) prior to any power supply voltage going
below the controller specification
tEW
tPH
tw1
500
500(9)
4
µs
µs
µs
Early Warning Time 图6-8
Power Hold Time 图6-8
POSENSE remains active after PWRGOOD is
disabled
PWRGOOD inactive time while POSENSE is
active
50% to 50% reference points (signal)
Pulse duration, in-active low,
PWRGOOD 图6-7
1000 (6)
625
Transition time, PWRGOOD
tt1 = tƒ1 and tr1
图6-7
Rise and Fall time for PWRGOOD
20% to 80% reference points (signal)
tt1
µs
ms
µs
POSENCE inactive time while PWRGOOD is
inactive
50% to 50% reference points (signal)
Pulse duration, in-active low,
POSENSE 图6-8
tw2
100
Transition time, POSENSE
tt1 = tƒ1 and tr1
图6-8
Rise and Fall time for POSENSE (7)
20% to 80% reference points (signal)
tt2
25
60
Time after rising edge of POSENSE before
PWRGOOD effects DLPC6540 operation
PWRGOOD Start Delay 图
6-7
tPSD
51.5
10
ms
ms
tPROJ_ON
PROJ_ON fall time delay to
Fall Delay
PROJ_ON 80% to PWRGOOD 80% fall time
start
PWRGOOD 图6-8
tREFCLKA
Time to stable REFLCKA before POSENSE
See (10)
Time to stable REFCLKA 图
6-7
(1) It is assumed that all 1.15-V supplies come from the same source, although some can have additional filtering before entering the
DLPC6540. As such, it is expected these supplies to ramp together (aside from differences caused by filtering). This same expectation
is true for the 1.21-V, 1.8-V, and 3.3-V supplies.
(2) The DLPC6540 has specific power supply sequencing requirements, listed below, that include the timings specified in this table.
a. Power Up Order:
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i.
1.15-V (Core, Analog) » 1.8-V (I/O, SCS) » 1.21-V (SCS)
ii. 1.15-V (Core, Analog) » 3.3-V (I/O
b. Power Down Order:
i.
3.3-V (I/O) » 1.15-V (Core, Analog)
ii. 1.21-V (SCS) » 1.8-V (I/O, SCS) » 1.15-V (Core, Analog)
(3) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.15-V power
supply ramp-up is started, and the second event is when the 1.15-V supply ramp-up reaches 80% of TOV (at which point the 1.8-V
supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.15-V power supply,
the designer must determine the specific delay time.
(4) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.8-V power supply
ramp-up is started, and the second event is when the 1.8-V supply ramp-up reaches 80% of TOV (at which point the 1.21-V supply can
start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.8-V power supply, the designer
must determine the specific delay time.
(5) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.21-V power
supply ramp-down is started, and the second event is when the 1.21-V supply ramp-down reaches 20% of TOV (at which point the 1.8-
V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 1.21-V power
supply, the designer must determine the specific delay time. The intent of this delay time is to guarantee that the voltage level of the
1.8-V supply never falls lower than the voltage level of the 1.21-V supply during the ramp-down until the 1.2-V supply is below 300 mV.
(6) This max value is only applicable if the 1.8-V power remains ON while PWRGOOD is inactive. Otherwise, there is no maximum limit.
(7) As long as noise on this signal is below the hysteresis threshold
(8) This delay requirement parameter is defined as the time between two events. The first event is the point where the 3.3-V power supply
ramp-down is started, and the second event is when the 3.3-V supply ramp-down and 1.8-V supply ramp down reaches 10% of TOV
(at which point the 1.15-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific
design of the 3.3-V and 1.8-V power supply, the designer must determine the specific delay time.
(9) If PROJ_ON is used for power down then Power Hold Time (tPH) is not required.
(10) This delay requirement parameter is defined by design of RECLKA oscillator. Stable clock must be provided before releasing
POSENSE.
tRAMP-UP
tRAMP-DOWN
TOV
90%
90%
10%
10%
图6-5. Power Supply Ramp Time
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tRAMP-UP-TOTAL
tRAMP-DOWN-TOTAL
90%
80%
1.15V (Core/Analog)
tRDSD115
20%
10%
90%
80%
1.8V (I/O, SCS)
Note 1
tRUSD18
10%
10%
Note 2
90%
1.21V (SCS)
3.3V (I/O)
tRUSD12
20%
tRDSD18
10%
90%
90%
tRUSD33
10%
(10ms t 50ms)
10%
Note 1: No power up or power down timing dependency between 1.8V and 3.3V
Note 2: No power up or power down timing dependency between 1.21V and 3.3V
图6-6. Power Supply Ramp Sequencing Profiles
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tREFCLKA
DC Power
Supplies
tt2
80%
POSENSE
20%
tt1
tt1
80%
50%
80%
PWRGOOD
50%
20%
20%
tW1
tPSD
图6-7. Power Up Timing
tPROJ_ON
80%
PROJ_ON
(If applicable)
20%
tt1
80%
PWRGOOD
20%
tt2
tt2
80%
80%
50%
50%
POSENSE
20%
20%
tW2
tEW
DC Power
Supplies
Up to 35ms
图6-8. Power Down Timing—Normal
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PROJ_ON
tt1
80%
PWRGOOD
20%
tPH
tt2
tt2
80%
50%
80%
50%
POSENSE
20%
20%
tW2
tEW
DC Power
Supplies
图6-9. Power Down Timing—Fault
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6.13 DMD HSSI Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
2.4
312.5
50
NOM
MAX
3.2
UNIT
Gbps
ps
Baud
UI
Baud Rate
Unit Interval, 1/Baud
416.7
115
Differential output rise time (1) (2)
(0% to 100% of minimum eye mask height)
Data
Clock
Data
ps
tR
50
135
ps
Differential output fall time(1) (2)
(0% to 100% of minimum eye mask height)
50
115
ps
tF
Clock
50
135
ps
tX1
Maximum eye closure(3)
at zero crossing
0.15
0.375
UI
tX2
Maximum eye closure(3)
at minimum eye height
UI
tEYE
Differential Data Eye(3)
0.7
UI
tskln2ln
tskM2M
fSSCD
fMOD
Lane to lane skew within a macro(2)
Lane to lane skew macro to macro(2)
Spread Spectrum (down spreading only) (4)
Modulation Frequency (4)
|200|
|4UI+200|
1
ps
ps
When SSCD Enabled
When SSCD Enabled
%
78.125
KHz
(1) Rise and fall times are associated with VDIFF-pp as shown in 图6-10.
(2) Measured with an interconnect with an insertion loss of 3dB at 1.6 GHz
(3) See 图6-11
(4) When SSCD is enabled, the available modulation waveform is: Triangular
+V
/2
DIFF(PP)
100
90
V
OD(min)
80
70
V
DIFF(PP)
60
(0 V) 50
40
30
20
10
0
œV
OD(min)
/2
œV
DIFF(PP)
tF.
tR.
VCM is removed when signals are viewed differentially.
图6-10. HSSI Differential Timing Parameters
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VOD(max)
VOD(min)
0 V
œVOD(min)
œVOD(max)
tX2
tX2
tX1
tX1
tEYE
0
1 UI
图6-11. HSSI Eye Characteristics
6.14 DMD Low-Speed LVDS Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
fclock
119.966
120
120.034
MHz
Differential output rise time
(10% to 90%)
(1)
tR
250
ps
Differential output fall time
(10% to 90%)
(1)
tF
250
55
ps
%
DCD
Duty Cycle Distortion
45
(1) Rise and Fall times are associated with VDIFF-pp as shown in 图6-12
+V
/2
DIFF(PP)
100
90
80
70
V
DIFF(PP)
60
(0 V) 50
40
30
20
10
0
œV
/2
DIFF(PP)
tF .
tR.
VCM is removed when signals are viewed differentially
图6-12. DMD Low-Speed Differential Timing Parameters
6.15 V-by-One Interface General Timing Requirements
PARAMETER(1)
MIN
MAX
UNIT
40 (1 lane)
20 (1 lane with Pixel
Repeat) (2)
600 (8
lanes)
fclock
Source clock frequency
MHz
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6.15 V-by-One Interface General Timing Requirements (continued)
PARAMETER(1)
MIN
MAX
43
43
43
8 lanes
4 lanes
2 lanes
1 lane
75
85
85
85
flink-ck
Link clock frequency per lane (3)
MHz
43 (21.5 with Pixel
Repeat)
3-Byte Mode
4-Byte Mode
5-Byte Mode
2
2
2.15
2.55
3.0
3.0
flink
Link transfer rate (3)
Unit interval
Gbps
3-Byte Mode
4-Byte Mode
5-Byte Mode
392
294
294
500
500
500
ps
ps
ps
tRBIT
tA
Jitter Margin
0.25
0.05
0.5
UI
UI
tB
Rise / Fall Time
tEYE
Differential Data Eye
Allowable intra-pair skew
Allowable Inter-pair Skew
Allowable inter-pair frequency offset
Total jitter
UI
tskew_intra
tskew_inter
foskew_inter
Tj
0.3
5
UI
UI
300
0.5
0.2
0.2
0.1
ppm
UI
–300
—
-
Rj
Random jitter
10^12 UI
UI
Dj_ISI
Sj
Deterministic jitter (ISI)
Sinusoidal jitter
-
UI
-
UI
(1) V-by-One high-speed technology supports 1, 2, 4, or 8 lane operation, in addition to 3-byte, 4-byte, and 5-byte transfer modes.
(2) Pixel repeat is a method used to support slower clock rate sources, whereby, the source come at twice the original clock rate, with
each data pixel being repeated once, and blanking being doubled as well. This method must operate external to DLPC6540. Once
received, the DLPC6540 discards each duplicate data pixel and blanking clock. Pixel repeat is supported only during 1- lane operation.
(3) For V-by-One high-speed technology, both link clock rate and link transfer rate limits must be met for any source.
VID(max)
VID(min)
VDIFF
0 V
œVID(min)
œVID(max)
tA
tB
tB
tA
tEYE
0
1 UI
图6-13. V-by-One Timing
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6.16 Source Frame Timing Requirements
See 图6-14
PARAMETER (1)
MIN
MAX
UNIT
50% reference
points
tp_vsw
tp_vbp
tp_vƒp
tp_tvb
tp_hsw
tp_hbp
tp_hfp
tp_thb
VSYNC Active Pulse Width
Vertical back porch (VBP) (2)
Vertical front porch (VFP) (2)
Total vertical blanking (TVB) (2)
HSYNC Active Pulse Width
Horizontal back porch (HBP) (5)
Horizontal front porch (HFP) (5)
Total horizontal blanking (THB) (5)
1
127
lines
50% reference
points
2 (3)
lines
lines
50% reference
points
MAX[ (TVBMIN - 65 ), 1] (3)
50% reference
points
See (4)
16
lines
50% reference
points
PCLKs
PCLKs
PCLKs
PCLKs
50% reference
points
5 (Digital Video Sources)
65 (Analog Video Sources)
50% reference
points
2
50% reference
points
20 (Digital Video Sources)
80 (Analog Video Sources) (6)
fline
Horizontal line rate
37.354
640
K Hz
Pixels
Lines
APPL
ALPF
Active Pixels per Line
Active Lines per Frame
4096
480
2160 (Normal)
(1) The requirements in the table apply to all external sources
(2) Vertical Blanking Parameter Definitions:
a. Vertical Back Porch: Time from the leading edge of VSYNC to the leading edge of HSYNC for the first active line, and includes the
VSYNC pulse width tp_vsw
.
b. Vertical Front Porch: Time from the leading edge of HSYNC following the last active line in a frame to the leading edge of VSYNC
c. Total Vertical Blanking: The sum of VBP + VFP = TVB.
(3) The vertical blanking required (per TVB) can be allocated as desired as long as the VFP and VBP minimum values are met.
(4) The minimum TVB can be calculated using the following:
TVBmin = 11 + ROUNDUP(LLS_VFP_MIN × (Source_ALPF/VPS_ALPF)), where:
a. LLS_VFP_MIN (Normal Mode) = 22
b. Source_ALPF = Active Lines Per Frame of the incoming source
c. VPS_ALPF = 1080 (for 1920x1080 Native products and 3840x2160 4-way XPR products)
d. Less TVBmin blanking can be required depending on the video processing being done. The configurations that drive the worst
case minimum value are those configurations that combine the maximum (or near maximum) capabilities of functions such as
scaling, warping, and keystone correction.
e. This is applicable to all sources (节7.4). Other sources require directed testing in the end application.
f.
The minimum recommended TVB with CVT 1.2 sources is 23.
(5) Horizontal Blanking Parameter Definitions:
a. Horizontal Back Porch: Time from the leading edge of HSYNC to the rising edge of DATEN, and includes the HSYNC pulse width
tp_hsw
.
b. Horizontal Front Porch: Time from the falling edge of DATEN to the leading edge of HSYNC.
c. Total Horizontal Blanking: The sum of HBP + HFP = THB.
(6) The horizontal blanking required (per THB) can be allocated as desired as long as the HFP and HBP minimum values are met.
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1 Frame
tp_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
(This diagram assumes the HSYNC
active edge is the rising edge)
tp_hbp
tp_hfp
DATAEN_CMD
P
n-2
P
n-1
PDATA(23/15:0)
PCLK
P0
P1
P2
P3
Pn
图6-14. Source Frame Timing
6.17 Synchronous Serial Port Interface Timing Requirements
For SSP0, SSP1 and SSP2(1)(2)
PARAMETER
MIN
MAX
UNIT
SSP Master
fclock
tclock
tw(L)
tw(H)
tdelay
tsu
Clock frequency, SSPx_CLK
50% to 50% reference points
0.38
25.6
12.0
12.0
-2.5
15.0
0
39.0
MHz
ns
ns
ns
ns
ns
ns
ns
ps
ps
Clock Period, SSPx_CLK
50% to 50% reference points
50% to 50% reference points
50% to 50% reference points
3632
Pulse duration low, SSPx_CLK
Pulse duration high, SSPx_CLK
Output Delay –SSPx_TXD (MOSI)
Setup time –SSPx_RXD (MISO)
hold time –SSPx_RXD (MISO)
Transition time (tr and tf- SSPx_RXD
Clock Jitter, SSPx_CLK
2.5
50% to 50% reference points
50% to 50% reference points
20% to 80% reference points
th
tt
1.5
300
500
tclkjit
tdelay∆
SSP Slave
tdelay
tsu
Clock output delay ∆ { | tw(H) - tw(L) | }
0
2.5
2.5
15
ns
ns
ns
Output Delay –SSPx_TXD (MOSI)
Setup time –SSPx_RXD (MISO)
hold time –SSPx_RXD (MISO)
50% to 50% reference points
50% to 50% reference points
th
(1) The DLPC6540 SPI interfaces support SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock phases) as shown in 表
6-2 and 图6-15. As such, each SPI interface configuration must be setup to match the SPI mode being used.
(2) In most SPI applications, one clock edge is used by both master and slave devices for transmitting data while the other edge is use by
both for sampling received data. This is referred to as Standard SPI Protocol. To maximize the SPI_CLK frequency potential, SPI
masters can alternatively be designed to sample the data in (MISO) bit on the same clock edge used to transmit the next data out
(MOSI) bit. This is referred to as Enhanced SPI Protocol. The DLPC6540 SPI master implementation supports both protocols (part of
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SPI interface configuration), however, to be able to use the "Enhanced SPI Protocol", the slave device must meet the requirement
shown in 图6-16.
表6-2. SPI Clocking Modes
SPI Clocking Mode
SPI Clock Polarity
SPI Clock Phase
0
1
2
3
0
0
1
1
0
1
0
1
CSZ
CLK
(CPOL=0)
(CPOL=1)
(CPHA=0)
MSB
LSB
TXD/RXD
(CPHA=1)
LSB
MSB
图6-15. Timing Diagram for SPI Clocking Modes
SPI_CSZ
SPI_CLK
SPI_MISO
MSb
LSb
œ Data held until end of last clock cycle
œ Supports Enhanced SPI Protocol
Controller MISO Sampling Edges
SPI_CSZ
SPI_CLK
SPI_MISO
MSb
LSb
œ Data not held until end of last clock cycle
œ Only supports Standard SPI Protocol
Controller MISO Sampling Edges
图6-16. Requirement for Enhanced SPI Protocol
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tclock
tt
tw(H)
tw(L)
80%
SSPx_CLK
(Controller output)
50%
50%
50%
50%
20%
tdelay(max)
tdelay(min)
Valid
SSPx_TXD
(Controller output)
Valid
Valid
Valid
tsu
th
SSPx_RXD
(Controller input)
Valid
SSPx_RXD
(Controller input)
图6-17. Timing Diagram for SSP Master (Modes 0/3)
6.18 Master and Slave I2C Interface Timing Requirements
For IIC0, IIC1 and IIC2
PARAMETER(1)
MIN
MAX
400
100
200
UNIT
kHz
kHz
pF
fclock
Clock frequency, IICx_SCL(2)
(50% reference points)
Full speed
Standard mode
CL
Capacitive Load (for each bus line)
(1) Meets all I2C timing per the I2C Bus Specification (except for capacitive loading as specified). For reference, see Version 2.1 of the
Phillips-NXP specification.
(2) By definition, I2C transactions operate at the speed of the slowest device on the bus. Full speed operation requires all other I2C
devices on the bus support full-speed operation. The length of the line (due to its capacitance), as well as the value of the I2C pullup
resistors, can reduce the obtainable clock rate.
6.19 Programmable Output Clock Timing Requirements
PARAMETER
fclock
MIN
0.19
MAX
48.75
UNIT
MHz
ns
Clock frequency, OCLKA (1)
Clock period, OCLKA
tclock
20.52
5263.15
tw(H)
Pulse duration high, OCLKA
(50% reference points)
(tclock/2) - 2
ns
tw(L)
Pulse duration low, OCLKA
(50% reference points)
(tclock/2) - 2
ns
tcclkjit
fclock
tclock
tw(H)
Jitter, OCLKA
200
ps
MHz
ns
Clock frequency, OCLKB (1)
0.19
20.52
48.75
Clock period, OCLKB
5263.15
Pulse duration high, OCLKB
(50% reference points)
(tclock/2) - 2
ns
tw(L)
Pulse duration low, OCLKB
(50% reference points)
(tclock/2) - 2
ns
tcclkjit
fclock
tclock
tw(H)
Jitter, OCLKB
200
ps
MHz
ns
Clock frequency, OCLKC (1)
0.19
20.52
48.75
Clock period, OCLKC
5263.15
Pulse duration high, OCLKC
(50% reference points)
(tclock/2) - 2
ns
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PARAMETER
MIN
MAX
UNIT
tw(L)
Pulse duration low, OCLKC
(50% reference points)
(tclock/2) - 2
ns
tcclkjit
fclock
tclock
tw(H)
Jitter, OCLKC
200
ps
MHz
ns
Clock frequency, OCLKD (1)
0.19
20.52
48.75
Clock period, OCLKD
5263.15
Pulse duration high, OCLKD
(50% reference points)
(tclock/2) - 2
ns
tw(L)
Pulse duration low, OCLKD
(50% reference points)
(tclock/2) - 2
ns
ps
tcclkjit
Jitter, OCLKD
200
(1)
a. OCLKA is a dedicated pin, while OCLKB thru OCLKD are available via GPIO as alternate functions.
b. The frequency of OCLKA thru OCLKD is programmable, with each having a power-up default frequency of 0.77 MHz. This default
frequency is not that meaningful for OCLKB thru OCLKD since they must be configured to their alternate GPIO function before
they can be used as a clock output.
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6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
See 图6-18
PARAMETER
MIN
MAX
UNIT
MHz
ns
Clock frequency, TCK
20
ƒclock
tclock
tw(H)
tw(L)
ts
Clock period, TCK
50
23
Pulse duration low, TCK
50% reference points
50% reference points
50% reference points
50% reference points
50% reference points
50% reference points
20% to 80% reference points
60pF load
ns
Pulse duration high, TCK
27
ns
10
10
10
10
ns
Setup time –TDI valid before TCK↑
Hold time –TDI valid after TCK↑
Setup time –TMS1 valid before TCK↑
Hold time –TMS1 valid after TCK↑
Transition time (tr and tf)
th
ns
ts
ns
th
ns
tt
3
ns
tdelay
0
15
ns
Output delay, TCK↓to TDO1
tclock
tt
tw(H)
tw(L)
80%
TCK
(Controller input)
50%
50%
50%
20%
tsu
th
TDI / TMS1
(Controller input)
50%
Valid
tdelay
TDO1
(Controller output)
50%
Valid
图6-18. Timing Diagram for JTAG Boundary Scan
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6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
See 图6-19 .
PARAMETER
MIN
MAX
UNIT
MHz
ns
Clock frequency, TCK
8.33
ƒclock
tclock
tw(H)
tw(L)
ts
Clock period, TCK
120
50
50
15
15
15
15
Pulse duration low, TCK
50% reference points
50% reference points
50% reference points
50% reference points
50% reference points
50% reference points
20% to 80% reference points
ns
Pulse duration high, TCK
ns
ns
Setup time –TDI valid before TCK↑
Hold time –TDI valid after TCK↑
Setup time –TMS2 valid before TCK↑
Hold time –TMS2 valid after TCK↑
Transition time (tr and tf)
th
ns
ts
ns
th
ns
tt
5
ns
tdelay
0
15
ps
Output delay, TCK↓to TDO2
tclock
tt
tw(H)
tw(L)
80%
TCK
(Controller input)
50%
50%
50%
20%
tsu
th
TDI / TMS2
(Controller input)
Valid
50%
tdelay
TDO2
(Controller output)
50%
Valid
图6-19. Timing Diagram for JTAG ARM Multi-Ice
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6.22 Multi-Trace ETM Interface Timing Requirements
See 图6-20.
PARAMETER(1)
MIN
MAX
UNIT
MHz
ns
Clock frequency, ETM_TRACECLK
Clock period, ETM_TRACECLK
Pulse duration low, ETM_TRACECLK
41.56
ƒclock
tclock
tw(H)
tw(L)
24.1
11.2
11.2
3.0
50% reference points
ns
Pulse duration high, ETM_TRACECLK 50% reference points
ns
tdelay
9.0
9.0
ps
Output delay, ETM_TRACECLK↑to
"ETM_OUTPUTS" (2)
tdelay
3.0
ps
Output delay, ETM_TRACECLK↓to
"ETM_OUTPUTS" (2)
(1) The trace interface is a source synchronous DDR interface. TRACE_CLK has a programmable delay to provide for centering its edges
in the center of the trace data to optimize performance.
(2) "ETM_OUTPUTS" are: TSTPT_(7:0) and ETM_TRACECTL
tclock
tt
tw(H)
tw(L)
80%
20%
TRACECLK
(Internal / Undelayed)
50%
50%
50%
tdelay
^9Ça_hÜÇtÜÇ{_
(Controller outputs)
TRACECLK
(External / Delayed)
图6-20. Timing Diagram for Multi-Trace ETM
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7 Detailed Description
7.1 Overview
The DLP Products chipset consists of three components: the DLP471TP digital micromirror device (DMD) , the
DLPC6540 digital display controller, and the DLPA3005. The DLPC6540 is the display controller for the DMD
that formats incoming video and controls the timing of the DMD. It also controls DLPA3005 light source signal
timing to coordinate with DMD timing in order to synchronize light output with DMD mirror movement. The
DLPC6540 provides interfaces such as V-by-One and HSSI (DMD interface) to minimize power consumption
and EMI. Applications include mobile smart TV, digital signage, and mobile home cinema.
7.2 Functional Block Diagram
Fan or
programmable DC supply
DC
Supply
SYSPWR (14.5 V to 20 V)
DC
Reg
L5
L4
L3
VSPI
1.8 V
1.8 V @ 3 A for
DMD and DLPC6540
GPIO (PROJ_ON)
Flash (2)
1.8
Reg
ADDR
DATA
1.1 V @ 3 A
(23) (18)
SYSPWR
1.1
Reg
L2
VLED
PROJ_ON
L1
Front End
Device
I2C BUSY
DLPA3005
I2C
LED_SEL (2)
POSENSE
Vx1
Vx1:
3840 × 2160
@ 60Hz
EEPROM
I2C
RESETZ
INITZ
3.3 V @ 2 A
2.5 V
LDO 1
LDO 2
DLPC6540
Master
3D L/R
SPI (2)
PWRGOOD
(3)
VBIAS, VOFFSET, VRESET
RLIM current sense
SPI BUS (Ctrl) (4)
1.15 V
1.21 V
1.8 V
3.3 V
2-Port HSSI
USB Mux
GPIO
DLPC471TP
.47 4K UHD DMD
LS Interface
1.8 V
USB 2.0
TI DLP chipset
Actuator
Driver
4-Position
Actuator
USB Camera
Third party component
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7.3 Feature Description
7.3.1 Input Sources
表7-1. Supported Input Source Parameters
SOURCE RESOLUTION: 2D
SOURCE RESOLUTION: 3D (PER EYE) (1)
BITS/PIXEL
ACCEPTED (MAX) PROCESSED (MAX)
BITS/PIXEL
INTERFACE
V-by-One
MIN
MAX
4096 × 2160
MAX
12
10
640 × 480 (2)
1920 × 1080 (FS)
(1) FS = Frame Sequential (full resolution).
(2) The minimum clock rate and link rate for the V-by-One interface, as well as Byte Mode, limits the smallest resolution that can be
supported by this interface. This interface supports 3-byte, 4-byte, and 5-byte modes.
7.3.2 Processing Delays
The DLPC6540 introduces a variable number of field/frame delays dependent on the source type and selected
processing steps performed on the source. For optimum audio/video synchronization, this delay must be
matched in the audio path. The following tables define the various video delay scenarios to aid in audio
matching.
Because the input and output rates are different when frame rate conversion (FRC) is employed, the delay
through the FRC is variable.
表7-2. Normal Mode Video-Graphics Processing Delay (2-D Sources) (1)(2)
FRAME RATE
CONVERSION
(INCLUDES
WARPING)
FORMATTER
BUFFER
FRC TYPE(3) (4)
SOURCE EXAMPLE
DE-INTERLACING
TOTAL DELAY
10-47 Hz Progressive
Graphics
Disabled
(0 Frame)
(1 + N) to (1 + 2N)
Frames
1 to (1 + N) Frames
1 Frame
N Frames
1 Frame
N Frames
N Frame
1 Frame
ASYNC (↑)
SYNC (1:1)
ASYNC (↓)
SYNC (↑)
SYNC (1:1)
47-120 Hz Progressive
Graphics
Disabled
(0 Frame)
2 Frames
N to 2N Frames
2 + N Frames
3 Frames
63-120 Hz Progressive
Graphics
Disabled
(0 Frame)
0 to N Frames
1 Frame
24-30 Hz Progressive
Video
Enabled (5)
(1 Frame)
Enabled (5)
(1 Frame)
60 Hz Progressive Video
1 Frame
(1) "N" is defined to be the ratio of the source frame rate (or field rate for interlaced video) to the display frame/field rate.
(2) This table assumes that the resolution limits for input sources specified elsewhere in this document are adhered to.
(3) "ASYNC" is defined as an asynchronous source
(4) "SYNC" is defined as a synchronous source
(5) DEI noise reduction enabled
表7-3. Normal Mode Video-Graphics Processing Delay (3-D Sources) (1)(2)
FRAME RATE
CONVERSION
(INCLUDES WARPING)
FORMATTER
FRC TYPE
SOURCE EXAMPLE
DE-INTERLACING
TOTAL DELAY
BUFFER
M Frames
M Frames
30 Hz Frame Sequential
(30 Hz both eyes)
Disabled
(0 Frame)
SYNC(1:4)
SYNC(1:2)
1 Frame
1 Frame
1 + M Frames
1 + M Frames
60 Hz Frame Sequential
(60 Hz both eyes)
Disabled
(0 Frame)
(1) "M" is defined to be the ratio of the source frame rate (or field rate for interlaced video) required to obtain both the left and right image
of an eye pair, to the display frame/field rate (the rate at which each eye is displayed).
(2) This table assumes that the resolution limits for input sources specified elsewhere in this document are adhered to.
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7.3.3 V-by-One Interface
The DLPC6540 controller supports a single 8 lane V-by-One port that can be configured for 1, 2, 4, or 8 lane
use. This interface supports limited lane remapping, which is shown in 表 7-4 . Intra-lane remapping (that is,
swapping P with N) is not supported.
表7-4. V-by-One Interface Lane Remapping Options
V-BY-ONE PORT PHYSICAL LANES (1)
CONFIGURATIO
# OF LANES
LANE 7
LANE 6
LANE 5
LANE 4
LANE 3
LANE 2 LANE 1 LANE 0
N (1)
1
8
8
7
1
6
0
5
2
4
3
3
4
2
5
1
6
0
7
2
(1) There are two controller lane mapping options, with the option to use fewer than the full eight lanes for each of these.
Independent from the remapping of the physical V-by-One interface, the DLPC6540 supports a number of data
mappings onto the actual physical interface as specified by the standard. V-by-One sources must match at least
one of these mappings. These are shown in 表 7-5, 表 7-6, 表 7-7, 表 7-8, 表 7-9, 表 7-10, 表 7-11, 表 7-12, 表
7-13, and 表7-14.
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表7-5. V-by-One Data Mapping for 36bpp/30bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 0
36bpp RGB/YCbCr 4:4:4 (1)
V-by-One INPUT DATA BIT
30bpp RGB/YCbCr 4:4:4
R/Cr[2]
R/Cr[3]
R/Cr[4]
R/Cr(5]
R/Cr[6]
R/Cr[7]
R/Cr[8]
R/Cr[9]
G/Y[2]
MAPPER OUTPUT
D[0]
D[1]
R/Cr[4]
R/Cr[5]
R/Cr[6]
R/Cr[7]
R/Cr[8]
R/Cr[9]
R/Cr[10]
R/Cr[11]
G/Y[4]
G/Y[5]
G/Y[6]
G/Y[7]
G/Y[8]
G/Y[9]
G/Y[10]
G/Y[11]
B/Cb[4]
B/Cb[5]
B/Cb[6]
B/Cb[7]
B/Cb[8]
B/Cb[9]
B/Cb[10]
B/Cb[11]
-
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
G/Y[3]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
D[31]
G/Y[4]
G/Y[5]
G/Y[6]
G/Y[7]
G/Y[8]
G/Y[9]
B/Cb[2]
B/Cb[3]
B/Cb[4]
B/Cb[5]
B/Cb[6]
B/Cb[7]
B/Cb[8]
B/Cb[9]
-
-
-
-
B/Cb[2]
B/Cb[3]
G/Y[2]
G/Y[3]
R/Cr[2]
R/Cr[3]
B/Cb[1]
B/Cb[0]
G/Y[1]
C[0]
C[1]
A[0]
A[1]
B[0]
B[1]
G/Y[0]
R/Cr[1]
R/Cr[0]
(1) For 36-bit inputs, the 12 bits per color truncate to 10-bits per color with the two least significant bits per color being discarded.
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表7-6. V-by-One Data Mapping for 27bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 1
V-by-One INPUT DATA BIT
27bpp RGB/YCbCr 4:4:4 (1)
R/Cr[1]
R/Cr[2]
R/Cr[3]
R/Cr[4]
R/Cr[5]
R/Cr[6]
R/Cr[7]
R/Cr[8]
G/Y[1]
MAPPER OUTPUT
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
G/Y[2]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
'0'
G/Y[3]
G/Y[4]
G/Y[5]
G/Y[6]
G/Y[7]
G/Y[8]
B/Cb[1]
B/Cb[2]
B/Cb[3]
B/Cb[4]
B/Cb[5]
B/Cb[6]
B/Cb[7]
B/Cb[8]
-
-
-
C[0]
C[1]
A[0]
—
D[27]
'0'
B/Cb[0]
—
D[29]
'0'
G/Y[0]
A[1]
B[0]
—
D[31]
R/Cr[0]
B[1]
(1) For 27-bit inputs, the 9 bits for each color shifts up one bit, and the least significant bit of each color is set to '0'.
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表7-7. V-by-One Data Mapping for 24bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 2
V-by-One INPUT DATA BIT
24bpp RGB/YCbCr 4:4:4 (1)
MAPPER OUTPUT
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
'0'
R/Cr[0]
R/Cr[1]
R/Cr[2]
R/Cr[3]
R/Cr[4]
R/Cr[5]
R/Cr[6]
R/Cr[7]
G/Y[0]
G/Y[1]
G/Y[2]
G/Y[3]
G/Y[4]
G/Y[5]
G/Y[6]
G/Y[7]
B/Cb[0]
B/Cb[1]
B/Cb[2]
B/Cb[3]
B/Cb[4]
B/Cb[5]
B/Cb[6]
B/Cb[7]
-
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
-
-
C[0]
C[1]
A[0]
A[1]
B[0]
B[1]
—
'0'
—
'0'
—
'0'
—
'0'
—
'0'
—
(1) For 24-bit inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
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表7-8. V-by-One Data Mapping for 32bpp/24bpp/20bpp YCbCr 4:2:2 (1)
V-by-One DATA MAP MODE 3
V-by-One INPUT DATA
BIT
32bpp YCbCr 4:2:2 (2)
24bpp YCbCr 4:2:2 (3)
20bpp YCbCr 4:2:2
MAPPER OUTPUT
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
'0'
CbCr[8]
CbCr[9]
CbCr[10]
CbCr[11]
CbCr[12]
CbCr[13]
CbCr[14]
CbCr[15]
Y[8]
CbCr[4]
CbCr[5]
CbCr[6]
CbCr[7]
CbCr[8]
CbCr[8]
CbCr[10]
CbCr[11]
Y[4]
CbCr[2]
CbCr[3]
CbCr[4]
CbCr[5]
CbCr[6]
CbCr[7]
CbCr[8]
CbCr[9]
Y[2]
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
Y[9]
Y[5]
Y[3]
Y[10]
Y[6]
Y[4]
Y[11]
Y[7]
Y[5]
Y[12]
Y[8]
Y[6]
Y[13]
Y[9]
Y[7]
Y[14]
Y[10]
Y[8]
Y[15]
Y[11]
Y[9]
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
-
'0'
'0'
'0'
'0'
'0'
'0'
'0'
D[24]
D[25]
'0'
-
-
-
-
C[0]
C[1]
A[0]
A[1]
B[0]
B[1]
—
—
—
—
—
—
'0'
D[28]
D[29]
D[30]
D[31]
Y[6]
Y[2]
Y[2]
Y[7]
Y[3]
Y[3]
CbCr[6]
CbCr[7]
CbCr[2]
CbCr[3]
CbCr[2]
CbCr[3]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 32-bit inputs, the 16 bits per color truncate to 10-bit per color, with the six least significant bits per color discarded.
(3) For 24-bit inputs, the 12 bits per color truncate to 10-bit per color, with the two least significant bits per color discarded.
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表7-9. V-by-One Data Mapping for 18bpp YCbCr 4:2:2(1)
V-by-One DATA MAP MODE 4
V-by-One INPUT DATA BIT
18bpp YCbCr 4:2:2 (2)
CbCr[1]
CbCr[2]
CbCr[3]
CbCr[4]
CbCr[5]
CbCr[6]
CbCr[7]
CbCr[8]
Y[1]
MAPPER OUTPUT
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
'0'
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
—
—
—
—
—
—
—
—
-
'0'
'0'
'0'
'0'
'0'
'0'
'0'
D[24]
D[25]
'0'
-
-
C[0]
C[1]
A[0]
A[1]
B[0]
B[1]
—
—
'0'
'0'
—
D[29]
'0'
Y[0]
—
D[31]
CbCr[0]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 18-bit inputs, the 9 bits for each color shift up one bit, and the least significant bits of each color is set to '0'.
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表7-10. V-by-One Data Mapping for 16bpp YCbCr 4:2:2(1)
V-by-One DATA MAP MODE 5
V-by-One INPUT DATA BIT
16bpp YCbCr 4:2:2 (2)
CbCr[0]
CbCr[1]
CbCr[2]
CbCr[3]
CbCr[4]
CbCr[5]
CbCr[6]
CbCr[7]
Y[0]
MAPPER OUTPUT
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
'0'
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
—
—
—
—
—
—
—
—
-
'0'
'0'
'0'
'0'
'0'
'0'
'0'
D[24]
D[25]
'0'
-
-
C[0]
C[1]
A[0]
—
—
—
—
—
—
'0'
'0'
'0'
A[1]
'0'
B[0]
'0'
B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 16-bit inputs, the 8 bits for each color shift up one bit, and the least significant bit of each color is set to '0'.
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表7-11. V-by-One Data Mapping Example for 12bpp/10bpp YCbCr 4:2:0(1)
V-by-One DATA MAP MODE 6
V-by-One INPUT
DATA BIT
12bpp YCbCr 4:2:0
EVEN LINE(2)
12bpp YCbCr 4:2:0 10bpp YCbCr 4:2:0
10bpp YCbCr 4:2:0
ODD LINE
MAPPER OUTPUT
Odd Line (2)
Y01[4]
Y01[5]
Y01[6]
Y01[7]
Y01[8]
Y01[9]
Y01[10]
Y01[11]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Y00[8]
Y00[9]
Y00[10]
Y00[11]
Cr00[4]
Cr00[5]
Cr00[6]
Cr00[7]
Cr00[8]
Cr00[9]
Cr00[10]
Cr00[11]
-
EVEN LINE
Y01[2]
Y01[3]
Y01[4]
Y01[5]
Y01[6]
Y01[7]
Y01[8]
Y01[9]
Y00[2]
Y00[3]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Y00[8]
Y00[9]
Cb00[2]
Cb00[3]
Cb00[4]
Cb00[5]
Cb00[6]
Cb00[7]
Cb00[8]
Cb00[9]
-
D[0]
D[1]
Y01[4]
Y01[5]
Y01[6]
Y01[7]
Y01[8]
Y01[9]
Y01[10]
Y01[11]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Y00[8]
Y00[9]
Y00[10]
Y00[11]
Cb00[4]
Cb00[5]
Cb00[6]
Cb00[7]
Cb00[8]
Cb00[9]
Cb00[10]
Cb00[11]
-
Y11[2]
Y11[3]
Y11[4]
Y11[5]
Y11[6]
Y11[7]
Y11[8]
Y11[9]
Y10[2]
Y10[3]
Y10[4]
Y10[5]
Y10[6]
Y10[7]
Y10[8]
Y10[9]
Cr00[2]
Cr00[3]
Cr00[4]
Cr00[5]
Cr00[6]
Cr00[7]
Cr00[8]
Cr00[9]
-
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
-
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
D[31]
-
-
-
-
-
Cb00[2]
Cb00[3]
Y00[2]
Y00[3]
Y01[2]
Y01[3]
Cr00[2]
Cr00[3]
Y10[2]
Y10[3]
Y11[2]
Y11[3]
Cb00[0]
Cb00[1]
Y00[0]
Y00[1]
Y01[0]
Y01[1]
Cr00[0]
Cr00[1]
Y10[0]
Y10[1]
Y11[0]
Y11[1]
B[0]
B[1]
A[0]
A[1]
C[0]
C[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd
lines carry the Cr values.
(2) For 12bpp YCbCr 4:2:0 inputs, the 12 bits per color truncate to 10 bits per color with the two least significant bits per color discarded.
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表7-12. V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0(1)
V-by-One DATA MAP MODE 7
8bpp YCbCr 4:2:0
8bpp YCbCr 4:2:0
ODD LINE (2)
V-by-One INPUT DATA BIT
MAPPER OUTPUT
EVEN LINE (2)
Y01[0]
Y01[1]
Y01[2]
Y01[3]
Y01[4]
Y01[5]
Y01[6]
Y01[7]
Y00[0]
Y00[1]
Y00[2]
Y00[3]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Cb00[0]
Cb00[1]
Cb00[2]
Cb00[3]
Cb00[4]
Cb00[5]
Cb00[6]
Cb00[7]
-
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
'0'
Y11[0]
Y11[1]
Y11[2]
Y11[3]
Y11[4]
Y11[5]
Y11[6]
Y11[7]
Y10[0]
Y10[1]
Y10[2]
Y10[3]
Y10[4]
Y10[5]
Y10[6]
Y10[7]
Cr00[0]
Cr00[1]
Cr00[2]
Cr00[3]
Cr00[4]
Cr00[5]
Cr00[6]
Cr00[7]
-
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
-
-
-
-
B[0]
B[1]
A[0]
A[1]
C[0]
C[1]
—
—
'0'
—
—
'0'
—
—
'0'
—
—
'0'
—
—
'0'
—
—
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd
lines carry the Cr values.
(2) For 8bpp YCbCr 4:2:0 inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
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表7-13. V-by-One Data Mapping Example for 10bpp YCbCr 4:2:0 (1)
V-by-One DATA MAP MODE 8
10bpp YCbCr 4:2:0
10bpp YCbCr 4:2:0
ODD LINE
V-by-One INPUT DATA BIT
MAPPER OUTPUT
EVEN LINE
Y00[2]
Y003]
D[0]
D[1]
Y10[2]
Y10[3]
Y10[4]
Y10[5]
Y10[6]
Y10[7]
Y10[8]
Y10[9]
Cr00[2]
Cr00[3]
Cr00[4]
Cr00[5]
Cr00[6]
Cr00[7]
Cr00[8]
Cr00[9]
Y11[2]
Y11[3]
Y11[4]
Y11[5]
Y11[6]
Y11[7]
Y11[8]
Y11[9]
-
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
D[2]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Y00[8]
Y00[9]
Cb00[2]
Cb00[3]
Cb00[4]
Cb00[5]
Cb00[6]
Cb00[7]
Cb00[8]
Cb00[9]
Y01[2]
Y01[3]
Y01[4]
Y01[5]
Y01[6]
Y01[7]
Y01[8]
Y01[9]
-
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
D[31]
-
-
-
Y01[0]
Y01[1]
Cb00[0]
Cb00[1]
Y00[0]
Y00[1]
Y11[0]
Y11[1]
Cr00[0]
Cr00[1]
Y10[0]
Y10[1]
C[0]
C[1]
B[0]
B[1]
A[0]
A[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry Cb values, and odd lines
carry the Cr values.
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表7-14. V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0 (1)
V-by-One DATA MAP MODE 9
8bpp YCbCr 4:2:0
8bpp YCbCr 4:2:0
ODD LINE (2)
V-by-One INPUT DATA BIT
MAPPER OUTPUT
EVEN LINE (2)
Y00[0]
Y00[1]
Y00[2]
Y003]
Y00[4]
Y00[5]
Y00[6]
Y00[7]
Cb00[0]
Cb00[1]
Cb00[2]
Cb00[3]
Cb00[4]
Cb00[5]
Cb00[6]
Cb00[7]
Y01[0]
Y01[1]
Y01[2]
Y01[3]
Y01[4]
Y01[5]
Y01[6]
Y01[7]
-
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
'0'
Y10[0]
Y10[1]
Y10[2]
Y10[3]
Y10[4]
Y10[5]
Y10[6]
Y10[7]
Cr00[0]
Cr00[1]
Cr00[2]
Cr00[3]
Cr00[4]
Cr00[5]
Cr00[6]
Cr00[7]
Y11[0]
Y11[1]
Y11[2]
Y11[3]
Y11[4]
Y11[5]
Y11[6]
Y11[7]
-
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
-
-
-
-
C[0]
C[1]
B[0]
B[1]
A[0]
A[1]
—
—
'0'
—
—
'0'
—
—
'0'
—
—
'0'
—
—
'0'
—
—
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd
lines carry the Cr values.
(2) For 8bpp YCbCr 4:2:0 inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
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7.3.4 DMD (HSSI) Interface
The DLPC6540 Controller DMD interface supports two High Speed Serial Interface (HSSI) output-only interfaces
for data transmission, a single low speed LVDS output-only interface for command write transactions, as well as
a low speed single-ended input interface used for command read transactions. Each HSSI port supports full
data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique
data lane pair can only be mapped to one unique destination data lane pair, and Intra-lane remapping (i.e.
swapping P with N) is not supported. In addition, the two HSSI ports can also be swapped. Lane and port
remapping (specified in flash) can help with board layout as needed. The number of HSSI ports and number of
HSSI lanes/per HSSI port required are based on DMD type and DMD display resolution. 表 7-15 shows some
remapping examples. When both ports are used, they do not need to have the same pin mapping.
表7-15. Controller to DMD Pin Mapping Examples
DLPC6540 Controller PINS - REMAPPING EXAMPLES TO DMD PINS
SWAP HSSI0 PORT
DMD PINS
FLIP HSSI0 180
No FLIP HSSI1
SWAP HSSI0 PORT
WITH HSSI1 PORT
BASELINE
WITH HSSI1 PORT AND
MIXED REMAPPING
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
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7.3.5 Program Memory Flash Interface
The DLPC6540 provides three external program memory chip selects for devices to access the program
memory interface. These are detailed in 表7-16.
表7-16. Program Memory Interface Chip Selects
CHIP SELECT
NAME
MAXIMUM SIZE
SUPPORTED (1)
CHIP SELECT USE
DATA BUS WIDTH
ACCESS TIME
PM_CSZ_0
PM_CSZ_1
Boot FLASH only - Required (2)
16 bits
16 bits
< = 120ns
< = 120ns
256Mb
256Mb
Additional Peripheral Device (or additional
FLASH) - Optional
PM_CSZ_2
Additional Peripheral Device - Optional
16 bits
< = 120ns
256Mb
(1) Using GPIO_47 as additional address bit
(2) Boot FLASH type supported is Standard NOR parallel FLASH, single or multi-bank.
FLASH access timing is software programmable with up to 31 wait states. Additional information about read and
write wait state timing is provided in 表7-17 and 图7-1.
表7-17. Program Memory Wait State Timing
PARAMETER
EQUATION (1)
TWSR: Wait State Resolution
6ns
(2) (3)
Read Wait States
ROUNDUP(MAX(TACC, TCE,TOE)/TWSR-N)
(Number of Read Wait States for each CSz read access)
(2)
(2)
(2)
Write Wait States for TCSand TAS
(Time from CS/Address activation to WRZ assertion)
ROUNDUP(MAX(TCS+5ns, TAS+5ns)/TWSR-N
ROUNDUP(MAX(TWP+5ns, TDS+5ns)/TWSR-N
ROUNDUP(MAX(TCH+5ns, TDH+5ns)/TWSR-N
)
Write Wait States for TWP and TDS
(Time from WRZ assertion to WEZ de-assertion)
)
Write Wait States for TCHand TDH
)
(Time from CS/Address activation to WRZ assertion)
(1)
a. TACC: Read Access Time (ADDR to DATA valid) –(address valid to DATA valid)
b. TCE: Read Access Time (CSZ to DATA valid) –(chip select active to DATA valid)
c. TOE: Read Access Time (OEZ to DATA valid) –(output enable active to DATA valid)
d. TCS: CSZ Setup Time (Writes) –(chip select active before negedge(WEZ)
e. TCS: Address Setup Time (Writes) –(address valid before negedge(WEZ)
f.
TAS: Address Setup Time (Writes) –(address valid before negedge(WEZ)
g. TWP: Write Pulse Width (Writes) –(WEZ active low time)
h. TDS: Data Setup Time (Writes) –(DATA valid before posedge(WEZ)
i.
TCH: CSZ Hold Time (Writes) –(CSZ held active after posedge(WEZ)
j.
TDH: Data Hold Time (Writes) –(DATA held valid after posedge(WEZ)
(2) Requires a minimum of at least 1 wait state
(3) Assumes a maximum single direction trace length of 90 mm (3.5 inches)
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At least one turnaround cycle guaranteed
(to prevent data bus contention)
32-bit write
32-bit write
WRITE WS
READ WS
TH
TH
TWP
TWP
TS
TS
HW
HW
TRD
TRD
TWC
TWC
TRC
TWRC
CSZ
AR0
AR1
AW0
WD15:0
AW1
WD31:16
ADDR
DATA
TDH
RD15:0
RD31:16
TDS
TAH
TDF
TACC, TCE, TOE
WEZ
TWPH
TOEH
TAS, TCS
OEZ
TCH
TWP
UBZ (for SRAM)
LBZ (for SRAM)
图7-1. Program Memory Interface Timing Diagram
7.3.6 GPIO Supported Functionality
The DLPC6540 provides 88 general purpose I/O that are available to support a variety of functions for many
different product configurations. In general, most of these I/O pins support only one specific function based on a
specific product configuration, although that function can be different for a different product configuration. Most of
these I/O can also be made available for TI test and debug use. Each of the following GPIO tables provide
product specific details on the allocated use of each of the GPIO for a specific supported product configuration.
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表7-18. GPIO Supported Functionality - LED with DLPA3005 (1)
GPIO
SIGNAL NAME
DESCRIPTION
GPIO_00 SSP1_SCLK (I)
GPIO_01 SSP1_DI (I)
GPIO_02 SSP1_DO (O)
GPIO_03 SSP1_CSZ0 (I)
GPIO_04 SSP1_CSZ1 (I)
GPIO_05 SSP1_CSZ2 (I)
GPIO_06 SAS_CLK (O)
GPIO_07 SAS_DI (I)
SSP Master or Slave
SSP Master or Slave
SSP Master or Slave
SSP Master or Slave
SSP Master or Slave
SSP Master or Slave
GPIO_08 SAS_DO (O)
GPIO_09 SAS_CSZ (O)
GPIO_10 SAS_INTGTR_EN (O)
GPIO_11 IIC1_SCL (B)
GPIO_12 IIC1_SDA (B)
GPIO_13 UART1_TXD (O)
GPIO_14 UART1_RXD (I)
GPIO_15 UART1_CTSZ (I)
GPIO_16 UART1_RTSZ (O)
GPIO_17 General Purpose Input/Output
GPIO_18 IR0 (I)
Available for general host use via Host Commands
GPIO_19 IR1 (I)
GPIO_20 PWM-IN0 (I)
GPIO_21 PWM-IN1 (I)
GPIO_22 3D LR (I)
For 3D applications: Left or right 3D reference (left = 1, right = 0). To be
provided by the host when a 3D command is not provided. Must
transition in the middle of each frame (no closer than 1 ms to the active
edge of VSYNC)
GPIO_23 LL_FAULT (O)
GPIO_24 LEDSEL_0 (O)
GPIO_25 LEDSEL_1 (O)
GPIO_26 General Purpose Input/Output
GPIO_27 General Purpose Input/Output
GPIO_28 Heartbeat (O)
Available for general host use via Host Commands
Available for general host use via Host Commands
GPIO_29 General Purpose Input/Output
GPIO_30 VBIAS_MON (I)
Available for general host use via Host Commands
GPIO_31 HDMI_CEC (B)
GPIO_32 IIC2_SCL (B)
GPIO_33 IIC2_SDA (B)
GPIO_34 WRP_TRIG_OUT (O)
GPIO_35 DAO_DO_0 (O)
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表7-18. GPIO Supported Functionality - LED with DLPA3005 (1) (continued)
GPIO
SIGNAL NAME
DESCRIPTION
GPIO_36 DAO_DO_1 (O)
GPIO_37 DAO_CLKOUT (O)
GPIO_38 HBT_DO (O)
GPIO_39 HBT_CLKOUT (O)
GPIO_40 SSP2_SCLK (I)
SSP Master
GPIO_41 SSP2_DI (I)
SSP Master
GPIO_42 SSP2_DO (O)
SSP Master
GPIO_43 SSP2_CSZ0 (I)
SSP Master
GPIO_44 SSP2_CSZ1 (I)
SSP Master
GPIO_45 SSP2_CSZ2 (I)
SSP Master
GPIO_46 General Purpose Input/Output
GPIO_47 PM_ADDR_23 (O)
GPIO_48 USB OTG Charge Pump Enable (O)
GPIO_49 SSP0_CSZ4 (O)
Available for general host use via Host Commands
DLPA3005
GPIO_50 SSP0_CSZ3 (O)
GPIO_51 General Purpose Input/Output
GPIO_52 LED_Enable (O)
Available for general host use via Host Commands
GPIO_53 General Purpose Input/Output
GPIO_54 General Purpose Input/Output
GPIO_55 General Purpose Input/Output
GPIO_56 General Purpose Input/Output
GPIO_57 General Purpose Input/Output
GPIO_58 I2C_BUSY (O)
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
GPIO_59 General Purpose Input/Output
GPIO_60 General Purpose Input/Output
GPIO_61 General Purpose Input/Output
GPIO_62 General Purpose Input/Output
GPIO_63 PROJ_ON (I)
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
GPIO_64 HOLD_BOOTZ (I)
GPIO_65 4 way XPR (O)
GPIO_66 4 way XPR (O)
GPIO_67 4 way XPR (O)
GPIO_68 4 way XPR (O)
GPIO_69 4 way XPR (O)
GPIO_70 4 way XPR (O)
GPIO_71 4 way XPR (O)
GPIO_72 4 way XPR (O)
GPIO_73 4 way XPR (O)
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表7-18. GPIO Supported Functionality - LED with DLPA3005 (1) (continued)
GPIO
SIGNAL NAME
DESCRIPTION
GPIO_74 4 way XPR (O)
GPIO_75 4 way XPR (O)
GPIO_76 4 way XPR (O)
GPIO_77 General Purpose Input/Output
GPIO_78 General Purpose Input/Output
GPIO_79 General Purpose Input/Output
GPIO_80 General Purpose Input/Output
GPIO_81 General Purpose Input/Output
GPIO_82 General Purpose Input/Output
GPIO_83 General Purpose Input/Output
GPIO_84 General Purpose Input/Output
GPIO_85 General Purpose Input/Output
GPIO_86 General Purpose Input/Output
GPIO_87 General Purpose Input/Output
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
Available for general host use via Host Commands
(1) All GPIO that are listed as General Purpose Input/Output must be configured as an input, a standard output, or an open-drain output.
This is set in the flash configuration. It is suggested that all unused General Purpose Input/Output GPIO should be configured as a
logic zero output and be left unconnected, otherwise an external pull-up or pull-down will be required to avoid a floating input. It should
be noted that the reset default for all GPIO is as an input signal. It should also be noted that an external pull-up (≤10kΩ) is required
for each signal configured as open-drain output.
7.3.7 Debug Support
The DLPC6540 contains a test point output port, TSTPT_(7:0), which provides the Host with the ability to provide
for Controller debug support. For initial debug operation, the four signals (TSTPT(3:0)) are sampled as inputs
approximately 1.5 µs after PWRGOOD goes high (or after a system reset). Once their input state has been
sampled and captured, this information is used to setup the initial test mode output state of the TSTPT_(7:0)
bus. 表 7-19 defines the test mode selection for a few programmable output states for TSTPT_(7:0). Use the
default state of 0000 (defined by the required external pulldown resistors) for normal operation (that is, no debug
required).
To allow TI to make use of this debug capability, providing for the option of a jumper to an external pullup is
recommended for TSTPT(3:0), as well as providing access to allow observation of the TSTPT bus outputs.
表7-19. Examples of Test Mode Selection Outputs Defined by TSTPT(3:0)(1)
TSTPT(3:0) CAPTURED VALUES
TSTPT_(7:0)
OUTPUT
0000 (DEFAULT)
(NO SWITCHING
ACTIVITY)
0101
1000
CLOCK DEBUG SYSTEM CALIBRATION
TSTPT(0)
TSTPT(1)
TSTPT(2)
TSTPT(3)
TSTPT(4)
TSTPT(5)
TSTPT(6)
TSTPT(7)
0
0
0
0
0
0
0
0
HIGH
Vertical Sync
166.25 MHz
83.13 MHz
41.56 MHz
10.39 MHz
25.16 MHz
133.00 MHz
HIGH
Delayed CW Index
Sequence Index
CW Spoke Test Point
CW Revolution Test Point
Reset Sequence Aux Bit 0
Reset Sequence Aux Bit 1
Reset Sequence Aux Bit 2
(1) These are only the default output selections. Software can reprogram the selection at any time.
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7.4 Device Operational Modes
The DLPC6540 has two operational modes which are enabled via software command via the Host control
interface. These modes are Standby and Active.
7.4.1 Standby Mode
The system is powered up and active, however, most blocks within the Controller have been shut down to
conserve power. Only the µProcessor and its peripherals are active (supporting a dormant projector waiting to be
woken up). In this mode the DMD is parked and no image can be displayed.
7.4.2 Active Mode
The system is powered up and fully operational, capable of projecting internal or external source images.
7.4.2.1 Normal Configuration
This configuration enables the full functionality of the DLPC6540.
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8 Power Supply Recommendations
8.1 Power Supply Management
The DLPA3005 manages power for the DLPC6540 and DMD. See 节 6.12 for all power sequencing and timing
requirements.
8.2 Hot Plug Usage
While the V-by-One, FPD-Link, and USB interfaces support hot plug usage (i.e. these interfaces can be
connected and disconnected while the DLPC6540 is powered), the controller itself (and any DMD connected to
the system) do not support Hot Plug use. As such, power down the system prior to removing the controller or
DMD from any system.
8.3 Power Supplies for Unused Input Source Interfaces
While certain product configurations cannot offer or make use of all of the available input source interfaces (e.g.
V-by-One, FPD-Link), the power supplies that are associated with these unused input source interfaces must still
be provided as if the interface was actually being used. The only concession is that the ferrite based isolation
filters for these supplies can be simplified down to simple de-coupling caps.
8.4 Power Supplies
8.4.1 1.15-V Power Supplies
The DLPC6540 can support a low cost power delivery system with a single 1.15-V power source derived from a
switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1
µF) filtering for the core 1.15-V power rail (VDD115). Ensure that the the high-frequency capacitors are evenly
distributed amongst the power balls and that they are placed as close to the power balls as possible. Additional
filtering must be provided for each of the uniquely defined 1.15-V power pins (e.g. VDD115_PLLMA,
VAD115VX1). Filtering for the unique power pins is discussed further in 节9.1 of this document.
8.4.2 1.21V Power Supply
The DLPC6540 can support a low cost power delivery system with a single 1.21V power source derived from a
switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1
µF) filtering for the 1.21-V power rail (VDD121_SCS). Place the high-frequency filtering capacitors as close as
possible to the VDD121_SCS power balls.
8.4.3 1.8-V Power Supplies
The DLPC6540 can support a low cost power delivery system with a single 1.8-V power source derived from a
switching regulator. To enable this approach, appropriate filtering must be provided for each of the uniquely
defined 1.8-V power pins (e.g. VDD18_PLLMA, VAD18_VX1). See 节9.1 for more information.
8.4.4 3.3-V Power Supplies
The DLPC6540 can support a low cost power delivery system with a single 3.3-V power source derived from a
switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1
µF) filtering for the main 3.3-V I/O power rail (VDD33). Ensure that the the high-frequency capacitors are evenly
distributed amongst the power balls and that they are placed as close to the power balls as possible. Additional
filtering must be provided for each of the uniquely defined 3.3-V power pins (e.g. VAD33_USB, VDD33_FPD).
This is discussed further in 节9.1 of the document.
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9 Layout
9.1 Layout Guidelines
9.1.1 General Layout Guidelines
In order to meet the thermal loads associated with the DLPC6540, TI recommends the following enhanced PCB
design parameters.
• A minimum of 4 power and ground planes
– Power layers: 1-oz. copper; Ground layers: 2-oz. copper
• Copper coverage: 90%
– Top and bottom signal layers: minimum 0.5-oz copper
– Internal signal layers: 1-oz copper
• Thermal copper ground planes beneath the thermal ball array of package containing a via farm with the
following attributes
– Thermal via quantity to ground plane = 64 (as 8x8 array)
– Thermal via size = 0.229mm - 0.25 mm (9mils - 10 mils)
– Thermal via plating thickness = 0.025 mm (1 mil) wall thickness
For signal integrity reasons, FR370HR or equivalent high performance epoxy laminate and repreg is also
recommended.
9.1.2 Power Supply Layout Guidelines
The following filtering circuits are recommended for the power supply inputs listed below.
• VAD115_VX1
• VAD18_VX1
• VAD115_FPD
• VDD33_FPD
• VAD33_USB
• VDD18_SCS
Because the PBC layout is critical to the performance of the interfaces associated with these power supplies, it is
vital that these power supplies be treated like an analog signal. Specifically:
• Place high-frequency components (such as ferrites and capacitors) as close to the power ball(s) as possible.
• Choose high-frequency ceramic capacitors (such as those with a value of 0.1 µF, 0.01 µF, and 100 nF) that
have low ESR and ESL values. Design the leads as short as possible, and as such, place these capacitors
under the package on the opposite side of the board.
• For each power pin, a single trace (as wide as possible) must be used from the controller to the capacitor and
then through the series ferrite to the power source.
• For each power pin, add a 100-nF decoupling capacitor placed near the escape via. Add this decoupling
capacitance to the capacitance recommended for filters. These are minimum recommendations, so different
layouts could require additional capacitance.
• See 表9-1 for the recommended series ferrite component for these supplies.
Controller
1.15 V
FB
VAD115_VX1
100 mF
10 mF
200 mF 100 mF
22 mF
图9-1. VAD115_VX1 (V-by-One) Recommended Filter
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Controller
1.8 V
FB
VAD18_VX1
100 mF
10 mF
200 mF 100 mF
22 mF
图9-2. VAD18_VX1 (V-by-One) Recommended Filter
Controller
1.15 V
FB
VDD115_FPD
100 mF
10 mF
200 mF 100 mF
22 mF
图9-3. VAD115_FPD (FPD-Link) Recommended Filter
Controller
3.3 V
FB
VDD33_FPD
100 mF
10 mF
200 mF 100 mF
22 mF
图9-4. VDD33_FPD (FPD-Link) Recommended Filter
Controller
3.3 V
FB
10 mF
VAD33_USB
100 mF
0.1 mF 0.01 mF
10 mF
图9-5. VAD33_USB (USB) Recommended Filter
Controller
1.18 V
FB
VDD18_SCS
100 mF
10 mF
200 mF 100 mF
22 mF
图9-6. VDD18_SCS (SCS DRAM) Recommended Filter
9.1.3 Layout Guidelines for Internal Controller PLL Power
The following guidelines are recommended to achieve the desired Controller performance relative to the internal
PLLs. The DLPC6540 contains multiple internal PLLs which have dedicated 1.15-V supply pins and 1.8-V supply
pins which are listed below:
• VDD115_PLLMA
• VDD115_PLLMB
• VAD115_PLLS
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• VAD115_HSSI0_PLL
• VAD115_HSSI1_PLL
and
• VAD18_PLLMA
• VAD18_PLLMB
It is important that each of these 1.15-V and 1.8-V supply pins have individual high frequency filtering in the form
of a ferrite bead and a 0.1-µF ceramic capacitor. Ensure that the impedance of the ferrite bead is much greater
than that of the capacitor at frequencies above 10 MHz. Locate these components very close to the individual
PLL power supply balls. Recommended values, topology, and layout examples are shown in 表 9-1, 图 9-7 and
图9-8, and 图9-9 respectively.
表9-1. Recommended PLL and Crystal Power Supply Filter Components
COMPONENT
PARAMETER
RECOMMENDED VALUE UNIT
Shunt capacitor
Capacitance
0.1
µF
Ω
Ω
Impedance at 100 MHz
DC Resistance
> 100
< 0.40
Series ferrite
Controller
1.15 V
FB
VDD115_PLLMA
0.1 mF
FB
VDD115_PLLMB
VAD115_PLLS
0.1 mF
FB
0.1 mF
FB
VAD115_HSSI0_PLL
VAD115_HSSI1_PLL
0.1 mF
FB
0.1 mF
图9-7. 1.15-V PLL Power Supply Filter Topology
Controller
1.8 V
FB
FB
VAD18_PLLMA
VAD115_PLLMB
0.1 mF
0.1 mF
图9-8. 1.8-V PLL Power Supply Filter Topology
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Signal Via
PCB Pad
ASIC Pad
Via to Common Analog /
Digital Board Power Plane
Via to Common Analog /
Digital Board Ground Plane
F
A
B
C
D
E
30
GND
REF
CLKB_O
REF
CLKB_I
Crystal
Circuit
VAD115
_PLLS
16
15
14
FB
1.15 V
1.15 V
GND
VDD115
_PLLMB
VSS
FB
GND
VAD18
_PLLMB
FB
1.8 V
Local Decoupling
for PLL Supplies
(view from top of
board)
图9-9. PLL Power Supply Filter Layout Examples
Since the PCB layout is critical to PLL performance, it is vital that the PLL power is treated like an analog signal.
Additional design guidelines are as follows:
• Place all filter components as close to possible to each of the PLL supply package pins.
• Keep the leads of the high-frequency capacitors as short as possible, and as such, it is recommended that
these capacitors be placed under the package on the opposite side of the board.
• Use a surface mount capacitor that is of high quality, low ESR, and monolithic.
• For each PLL power pin, a single trace (as wide as possible) must be used from the DLPC6540 to the
capacitor and then through the series ferrite to the power source.
9.1.4 Layout Guideline for DLPC6540 Reference Clock
The DLPC6540 requires two external reference clocks to feed its internal PLLs. A crystal or oscillator can supply
these references. The recommended crystal configurations and reference clock frequencies are listed in 表 9-2,
with additional required discrete components shown in 图9-10 and defined in 表9-2.
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PLL_REFCLK_I
PLL_REFCLK_O
RFB
RS
Crystal
CL1
CL2
CL = Crystal load capacitance
RFB = Feedback Resistor
图9-10. Discrete Components Required for Crystal
9.1.4.1 Recommended Crystal Oscillator Configuration
表9-2. Recommended Crystal Configurations
PARAMETER
Crystal circuit configuration
CRYSTAL A
CRYSTAL B
UNIT
Parallel resonant
Fundamental (first harmonic)
40
Parallel resonant
Crystal type
Fundamental (first harmonic)
38
Crystal nominal frequency
Crystal frequency tolerance (1)
Crystal equivalent series resistance (ESR)
Crystal load capacitance
Crystal Shunt Load capacitance
Temperature range
MHz
PPM
±100 (200 p-p max)
60 (Max)
±100 (200 p-p max)
60 (Max)
Ω
pF
pF
20 (Max)
20 (Max)
7 (Max)
7 (Max)
°C
–40°C to +85°C
100 (Nominal)
1 Meg (Nominal)
–40°C to +85°C
100 (Nominal)
1 Meg (Nominal)
Drive level
µW
RFB feedback resistor (nominal)
CL1 external crystal load capacitor
CL2 external crystal load capacitor
Ω
pF
pF
See equation in (2)
See equation in (3)
.
.
See equation in (2)
See equation in (3)
.
.
A ground isolation ring around the
crystal is recommended.
A ground isolation ring around the
crystal is recommended.
PCB layout
(1) Crystal frequency tolerance to include accuracy, temperature, aging, and trim sensitivity. These are typically specified separately and
the sum of all required to meet this requirement.
(2) CL1 = 2 × (CL –Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin
associated with the Controller pin REFCLKx_I. See 表9-3.
(3) CL2 = 2 × (CL –Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin
associated with the Controller pin REFCLKx_O. See 表9-3.
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表9-3. Crystal Pin Capacitance
PARAMETER
MIN
NOM
MAX
UNITS
Sum of package and PCB stray capacitance
at REFCLKA_I
Cstray_pll_refclkA_i
Cstray_pll_refclkA_o
Cstray_pll_refclkB_i
Cstray_pll_refclkB_o
4.5
pF
Sum of package and PCB stray capacitance
at REFCLKA_O
4.5
4.5
4.5
pF
pF
pF
Sum of package and PCB stray capacitance
at REFCLKB_I
Sum of package and PCB stray capacitance
at REFCLKB_O
The crystal circuits in the DLPC6540 have dedicated power (VAD33_OSCA and VAD33_OSCB) pins, with the
recommended filtering for each shown in 图9-11, and recommended values shown in 表9-1.
Controller
FB
VAD33_OSCA
VAD33_OSCB
3.3V
0.1 …F
GND
FB
0.1 …F
GND
图9-11. Crystal Power Supply Filtering
表9-4. DLPC6540 Recommended Crystal Parts
FREQUENCY TOLERANCE,
FREQUENCY STABILITY,
AGING/YEAR
NOMINAL
FREQUENCY
LOAD
CAPACITANCE
OPERATING
TEMPERATURE
DRIVE
LEVEL
MANUFACTURER
PART NUMBER
ESR
Freq Tolerance:
±20 ppm
TXC
7M38070001 (1)
38 MHz
40 MHz
Freq Stability:
±20 ppm
12 pF
100 µW
100 µW
30-Ω max
–40°C to +85°C
–40°C to +85°C
Aging/Year: ±3 ppm
Freq Tolerance:
±20 ppm
TXC
7M40070041 (2)
Freq Stability:
±20 ppm
12 pF
30-Ω max
Aging/Year: ±3 ppm
(1) This device requires an RS resistor with value = 0.
(2) This device requires an RS resistor with value = 0.
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9.1.5 V-by-One Interface Layout Considerations
The DLPC6540 V-by-One SERDES differential interface waveform quality and timing is dependent on the total
length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and
how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention
to many factors.
DLPC6540 I/O timing parameters, V-by-One transmitter timing parameters, as well as Thine specific timing
requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted and met
through controlled PCB routing. PCB related requirements for V-by-One are provided in 表9-5 as a starting point
for the customer.
表9-5. V-by-One Interface PBC Related Requirements (1)
PARAMETER
MIN
TYP
MAX
UNIT
Intra-lane cross-talk
(between VX1_DATAx_P and VX1_DATAx_N)
< 1.5
mVpp
mVpp
Inter-lane cross-talk
(between data lane pairs)
< 1.5
Cross-talk between data lanes and other signals
Intra-lane skew
< 1.5
< 40
< 5
mVpp
ps
Inter-lane skew
UI
Differential Impedance
90
100
110
Ω
(1) If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical
to achieve the target 100 Ωimpedance (e.g. to reduce transmission line losses).
Additional V-by-One layout guidelines:
• Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the
number of necessary vias to two.
• Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration.
Ground guard traces are also recommended.
• Do not route the differential signal pairs over the slit of power or ground planes.
• Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew
requirements.
• Ensure that the bend angles associated with the differential signal pairs are between 135o and 225o(See 图
9-12).
Differential Pair
Shield
135o < Angle < 225o
Shield
图9-12. V-by-One Routing Example
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9.1.6 USB Interface Layout Considerations
The DLPC6540 USB differential interface waveform quality and timing is dependent on the total length of the
interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well
matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many
factors.
DLPC6540 I/O timing parameters, USB transmitter and receiver timing parameters, as well as USB specific
timing requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted
and met through controlled PCB routing. PCB related requirements for USB are provided in 表 9-6 as a starting
point for the customer.
表9-6. USB Interface PBC Related Requirements (1)(2)
PARAMETER
MIN
TYP
MAX
< 1.5
< 20
UNIT
mVpp
Cross-talk between data lane (USB_DAT_P, USB_DAT_N) and other signals
Intra-lane skew (USB_DAT_P, USB_DAT_N)
Differential Impedance (USB_DAT_P, USB_DAT_N)
Single Mode impedance (USB_DAT_P, USB_DAT_N)
Common Mode Impedance (USB_DAT_P, USB_DAT_N)
Parasitic resistance (USB_DAT_P, USB_DAT_N)
Total capacitance (USB_DAT_P, USB_DAT_N)
Differences of trace capacitance between USB_DAT_P, USB_DAT_N
TXRTUNE resistor
ps
76.5
21
90
45
30
103.5
Ω
Ω
Ω
Ω
pF
pF
39
≤0.5
< 4
< 1
172.26
174
175.74
Ω
(1) If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical
to achieve the target 100 Ωimpedance (e.g. to reduce transmission line losses).
(2) One pcb layout example for the differential pair is shown in 图9-13
Additional layout guidelines for USB_DAT_P/USB_DAT_N:
• Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the
number of necessary vias to two.
• Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration.
Ground guard traces are also recommended.
• Do not route the differential signal pairs over the slit of power or ground planes.
• Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew
requirements.
• Ensure that the bend angles associated with the differential signal pair are between 135o and 225o. (See 图
9-14).
• Minimize the length where the differential signal pair are parallel to clocks or digital signals.
• Do not route the differential signal pair under an IC that uses a quartz crystal, oscillator, clock synchronization
circuit, magnetic device, or clock.
Ground
guard trace
Ground
guard trace
3 × 0.35 mm
USB_DAT_P
0.35 mm
0.25 mm
0.35 mm
3 × 0.35 mm
USB_DAT_N
0.04 mm
FR4 Dielectric
Ground Layer
0.02 mm
图9-13. USB Layout Example
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Differential Pair
Shield
135o < Angle < 225o
Shield
图9-14. USB Routing Example
Additional USB layout guidelines for TXRTUNE
• Use the shortest possible connection lengths for the resistor between TXRTUNE and ground.
• Use ground layer and ground guard traces to shield the wires and resistor.
9.1.7 DMD Interface Layout Considerations
The DLPC6540 controller HSSI differential interface waveform quality and timing is dependent on the total length
of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well
matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many
factors.
DLPC6540 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding
data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB
design recommendations are provided in 表 9-7, 图 9-15, and the paragraph below as a starting point for the
customer.
表9-7. PCB Recommendations for DMD Interface (1)(2)
PARAMETER
MIN
MAX
UNIT
TW
Trace Width
5.7
mils
mils
mils
TS
Intra-lane Trace Spacing
Inter-lane trace spacing (3)
5.3
TSPP
48.3
(1) Recommendations to achieve the desired nominal differential impedance as specified by RDIFF in 节6.7.
(2) These parameters show recommendations based on the micro-strip design shown in 图9-15. This design minimizes signal loss to
support longer trace lengths at the expense of electromagnetic interference (EMI). The designer has the option to use of a stripline
design for shorter trace lengths and to target minimizing EMI at the expense of signal loss.
(3) A reduced inter-lane spacing can be used to escape the Controller ball field, however, widen this spacing to at least the stated
minimum after escape.
Tw
Ts
Tw
Tw
Ts
Tw
Tspp
Signal Traces
Differential Pair #1
Differential Pair #2
Ground Plane
图9-15. DMD Differential Layout Recommendations
Additional DMD interface layout guidelines:
• Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the
number of necessary vias to two. If two are required, place one at each end of the line (one at the controller
and one at the DMD).
• Route the differential signal pairs over a single ground or power plane using a Micro-strip line configuration.
• Do not route the differential signal pairs over the slit of power or ground planes.
• Ensure the bend angles associated with the differential signal pairs are between 135o and 225o.
• Route the single-ended signal in a way that to minimizes the number of vias required. Limit the number of
necessary vias to two. If two are required, place one at each end of the line (one at the controller and one at
the DMD).
• Avoid stubs.
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• No external termination resistors are required on the DMD_HSSI or DMD_LS differential signals.
• Include a series termination resistor (with a value of 30.1 Ω, for example) to the DMD_LS0_RDATA and
DMD_LS1_RDATA single-ended signal paths. Place the resistor as close as possible to the corresponding
DMD pin.
• The DMD_DEN_ARSTZ does not typically require a series resistor, however, for a long trace, one might be
needed to reduce undershoot or overshoot.
9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
To avoid potential damage to unused video source inputs and unused GPIO, the instructions specifically noted in
the associated 节 5 must be followed. For those unused inputs without specific instructions, TI recommends that
these input pins be tied through a pullup resistor to its associated power supply or a pulldown to ground. Unused
output-only pins can remain open. Never tie unused output-only pins directly to power or ground. For controller
inputs with an internal pullup or pulldown resistor, it is unnecessary to add an external pullup or pulldown unless
specifically recommended. Internal pullup and pulldown resistors are weak and cannot be expected to drive the
external line. When external pullup or pulldown resistors are needed for pins that have built-in weak pullups or
pulldowns, use the value specified in 表5-14.
There are also power supply considerations that must be followed for any unused video sources. These are
detailed in 节8.3.
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9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
表9-8. Max Pin-to-Pin PCB Interconnect Recommendations - DMD
Controller INTERFACE
SIGNAL INTERCONNECT TOPOLOGY (1) (2) (3)
UNIT
SINGLE BOARD SIGNAL ROUTING MULTI-BOARD SIGNAL ROUTING
DMD
LENGTH
LENGTH
Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
10 (254)
inch (mm)
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
10 (254)
10 (254)
10 (254)
inch (mm)
inch (mm)
inch (mm)
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_LS0_CLK_P
DMD_LS0_CLK_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS1_CLK_P
DMD_LS1_CLK_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
18
(457.2)
18
(457.2)
inch
(mm)
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS0_RDATA
DMD_LS1_RDATA
18
(457.2)
18
(457.2)
inch
(mm)
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表9-8. Max Pin-to-Pin PCB Interconnect Recommendations - DMD (continued)
Controller INTERFACE
SIGNAL INTERCONNECT TOPOLOGY (1) (2) (3)
UNIT
SINGLE BOARD SIGNAL ROUTING MULTI-BOARD SIGNAL ROUTING
DMD
LENGTH
LENGTH
inch
(mm)
DMD_DEN_ARSTZ
N/A
N/A
(1) Max signal routing length includes escape routing.
(2) Multi-board DMD routing lengths shown are the combination that was analyzed by TI.
(3) Due to board variations, create a SPICE simulation for all board designs with the Controller IBIS models to ensure signal routing
lengths do not exceed signal requirements.
表9-9. High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING (1) (2)
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH (3)
UNIT
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD (4)
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
±0.01
(±0.254)
inch
(mm)
DMD (5)
DMD_HSSI0_x_P
DMD_HSSI0_x_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD (4)
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
±0.01
(±0.254)
inch
(mm)
DMD (5)
DMD (6)
DMD (6)
DMD (4)
DMD_HSSI1_x_P
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
DMD_HSSI1_x_N
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
±0.05
(±1.27)
inch
(mm)
±0.05
(±1.27)
inch
(mm)
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
DMD_LS0_CLK_P
DMD_LS0_CLK_N
±1.0
(±25.4)
inch
(mm)
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表9-9. High Speed PCB Signal Routing Matching Requirements (continued)
SIGNAL GROUP LENGTH MATCHING (1) (2)
INTERFACE
DMD (5)
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH (3)
±0.025
(±0.635)
inch
(mm)
DMD_LS0_x_P
DMD_LS0_x_N
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
DMD_LS1_CLK_P
DMD_LS1_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD (4)
DMD (5)
DMD
±0.025
(±0.635)
inch
(mm)
DMD_LS1_x_P
DMD_LS1_x_N
DMD_LS0_RDATA
DMD_LS1_RDATA
inch
(mm)
N/A
N/A
N/A (7)
inch
(mm)
DMD
DMD_DEN_ARSTZ
N/A
(1) These routing requirements are specific to the PCB routing. Internal package routing mismatches in the DLPC6540 and DLP471TP
have already been accounted for in these requirements.
(2) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.
(3) This requirement must be maintained from the Controller to the DMD, even if the signals traverse multiple boards.
(4) This is an inter-pair specification (that is, differential pair to differential pair within the group).
(5) This is an intra-pair specification (that is, length mismatch between P and N for the same pair). This is applicable to both clock and
data.
(6) This is a channel to channel skew specification.
(7) The low speed read control interface from the DMD is single ended, and makes use of the differential write clock. As such, a routing
mismatch between these is not applicable.
9.2 Thermal Considerations
The underlying thermal requirement for the DLPC6540 is that the maximum operating junction temperature (TJ)
not be exceeded (defined in the 节 6.3). This temperature is dependent on operating ambient temperature,
heatsink, airflow, PCB design (including the component layout density and the amount of copper used), power
dissipation of the DLPC6540, and power dissipation of surrounding components. The DLPC6540’s package is
designed to extract heat via the package heat slug to the heatsink, via the thermal balls, and through the power
and ground planes of the PCB. Thus, heatsink, copper content, and airflow over the PCB are important factors.
The recommended maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC6540 power dissipation and RθJA at 0 m/s,1 m/s, and 2 m/s of forced airflow, where
RθJA is the thermal resistance of the package as measured using the test board described in 节 9.1.1. This test
PCB is not necessarily representative of the customers PCB and thus the reported thermal resistance can differ
from the actual product application. Although the actual thermal resistance can be different, it is the best
information available during the design phase to estimate thermal performance. TI highly recommends that once
the host PCB is designed and built that the thermal performance be measured and validated.
To do this, measure the top center case temperature under the worse case product scenario (max power
dissipation, max voltage, max ambient temperature) and validate that the maximum recommended case
temperature (TC) is not exceeded. This specification is based on the measured φJT for the DLPC6540 package
and provides a relatively accurate correlation to junction temperature. Take care when measuring this case
temperature to prevent accidental cooling of the package surface. TI recommends a small (approximately 40
gauge) thermocouple. Ensure that the bead and thermocouple wire contact the top of the package. Cover the
bead and thermocouple wire with a minimal amount of thermally conductive epoxy. Route the wires closely along
the package and the board surface to avoid cooling the bead through the wires.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Device Nomenclature
10.1.2.1 Device Markings
DLP®
XDLPC6540ZDC
XXXXXXXX-XXXXXX
TEXAS INSTRUMENTS
1
2
3
CCCCCC YYWW
4
LLLLL
TTTT
G1
Terminal A1 corner
Marking Definitions:
Line 1:
TI Part Number: Engineering
Samples
X = Engineering Samples
DLPC6540 = Device ID
blank or A, B, C ... = Part Revision
ZDC = Package designator
TI Part Number: Production
Vendor Information
DLPC6540 = Device ID
blank or A, B, C ... = Part Revision
ZDC = Package designator
Line 2:
Line 3:
XXXXXXX-XXXXXX
Vendor Country Year and Week
code
CCCCCC = Country
YY = Year
WW = Week
Vendor Lot and Trace Code
LLLLL = Lot code
TTTT = Trace code
Line 4:
10.1.2.2 Package Data
表10-1. Package Information
PARAMETER
Number of balls (signal/thermal)
Ball pitch
VALUE
612 / 64
1.00
UNITS
mm
mm
mm
mm
mm
mm3
g
UBM (under bump metallurgy)
BPD (ball pad diameter)
Body dimension
0.48 (See 图10-1)
0.58 (See 图10-1)
See Mechanical Drawing
See Mechanical Drawing
350 - 2000 (J-STD-20D)
5.64
Mold compound dimensions
Package volume class
Approximate weight
Substrate circuit
Pb-free
Package balls
Pb-free
Solder paste
Pb-free
Solder profile
TC =250°C, TP = 253°C (J-STD-20D)
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UNITS
ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
表10-1. Package Information (continued)
PARAMETER
Moisture sensitivity level
VALUE
MSL Level 3 (J-STD-20D)
SAC305
Solder ball composition
WIrebond
Cu
a) Hot air reflow (including the combination of long and/or medium
infrared ray reflow)
Mounting technique
b) Long or medium infrared ray reflow
Package side
Ball pad
UBM.
BPD.
Solder mask
图10-1. Package Ball Parameters
10.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.4 Trademarks
BrilliantColor™ and TI E2E™ are trademarks of Texas Instruments.
V-by-One® is a registered trademark of THine Electronics, Inc.
Arm® and Cortex® are registered trademarks of Arm Limited.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10.6.1 Video Timing Parameter Definitions
Active Lines Per Frame Defines the number of lines in a frame containing displayable data: ALPF is a subset
(ALPF)
Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data: APPL is a
(APPL) subset of the TPPL.
of the TLPF.
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Horizontal Back Porch Number of blank pixel clocks after horizontal sync but before the first active pixel.
(HBP) Blanking
Note: HBP times are reference to the leading (active) edge of the respective sync
signal.
Horizontal Front Porch Number of blank pixel clocks after the last active pixel but before Horizontal Sync.
(HFP) Blanking
Horizontal Sync (HS)
Timing reference point that defines the start of each horizontal interval (line). The
absolute reference point is defined by the active edge of the HS signal. The active
edge (either rising or falling edge as defined by the source) is the reference from
which all horizontal blanking parameters are measured.
Total Lines Per Frame Defines the vertical period (or frame time) in lines: TLPF = Total number of lines per
(TLPF)
frame (active and inactive).
Total Pixel Per Line
(TPPL)
Defines the horizontal line period in pixel clocks: TPPL = Total number of pixel clocks
per line (active and inactive).
Vertical Sync (VS)
Timing reference point that defines the start of the vertical interval (frame). The
absolute reference point is defined by the active edge of the VS signal. The active
edge (either rising or falling edge as defined by the source) is the reference from
which all vertical blanking parameters are measured.
Vertical Back Porch
(VBP) Blanking
Number of blank lines after vertical sync but before the first active line.
Number of blank lines after the last active line but before vertical sync.
TPPL
Vertical Front Porch
(VFP) Blanking
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
Horizontal
Front
Porch
TLPF
ALPF
(HBP)
(HFP)
Vertical Front Porch (VFP)
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ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
PACKAGE OUTLINE
ZDC0676A
PBGA - 2.4 mm max height
SCALE 0.500
PLASTIC BALL GRID ARRAY
31.1
30.9
B
A
BALL A1 CORNER
31.1
30.9
(
29)
4X (45 X 0.2)
C
(
23)
HEAT SLUG
(1.17)
0.35 C
2.40 MAX
0.6
SEATING PLANE
BALL TYP
TYP
0.2 C
0.4
29 TYP
SYMM
(1) TYP
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
(1) TYP
W
V
U
T
R
P
N
M
L
K
SYMM
676X
29
TYP
J
H
G
0.7
0.5
F
E
D
C
0.25
0.1
C A B
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
10 20
1
TYP
2
4
6
8
12
18
14 16 24 26
22
28
30
1
TYP
4224809/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
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ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
EXAMPLE BOARD LAYOUT
ZDC0676A
PBGA - 2.4 mm max height
PLASTIC BALL GRID ARRAY
(1) TYP
SYMM
676X ( 0.5)
1
20 21 22 23 24 25 26
2 3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19
29 30
27 28
9
A
(1) TYP
B
C
D
E
F
G
H
J
K
L
M
N
P
SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.5)
METAL
EXPOSED
(
0.5)
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224809/A 02/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
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ZHCSNH1C –MAY 2021 –REVISED NOVEMBER 2022
EXAMPLE STENCIL DESIGN
ZDC0676A
PBGA - 2.4 mm max height
PLASTIC BALL GRID ARRAY
(1) TYP
(1) TYP
676X ( 0.5)
10 11 12 13 14 15 16 17 18 19
1
20 21
2 3
4
5
6
7
8
22 23
24 25 26
29 30
27 28
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 4X
4224809/A 02/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPC6540ZDC
ACTIVE
BGA
ZDC
676
27
TBD
Call TI
Call TI
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
ZDC0676A
PBGA - 2.4 mm max height
SCALE 0.500
PLASTIC BALL GRID ARRAY
31.1
30.9
B
A
BALL A1 CORNER
31.1
30.9
(
29)
4X (45 X 0.2)
C
(
23)
HEAT SLUG
(1.17)
0.35 C
2.40 MAX
0.6
SEATING PLANE
BALL TYP
TYP
0.2 C
0.4
29 TYP
SYMM
(1) TYP
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
(1) TYP
W
V
U
SYMM
676X
T
29
TYP
R
P
N
M
L
K
J
0.7
0.5
H
G
F
0.25
0.1
C A B
E
D
C
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
1
TYP
2
4
6
8
10 20
12 14 16 18
22 24 26 28 30
1
TYP
4224809/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZDC0676A
PBGA - 2.4 mm max height
PLASTIC BALL GRID ARRAY
(1) TYP
(1) TYP
SYMM
676X ( 0.5)
1
21
22 23
2 3
4
5
6
8
10 11 12 13 14 15 16 17 18 19
20
24
25
26 27 28
29 30
7
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.5)
METAL
EXPOSED
(
0.5)
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224809/A 02/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
ZDC0676A
PBGA - 2.4 mm max height
PLASTIC BALL GRID ARRAY
(1) TYP
(1) TYP
676X ( 0.5)
1
21
22 23
2 3
4
5
6
8
10 11 12 13 14 15 16 17 18 19
20
24
25
26 27 28
29 30
7
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 4X
4224809/A 02/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022,德州仪器 (TI) 公司
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