DLPC900_技术文档

DLPC900

ZHCSD20F –OCTOBER 2014 –REVISED JUNE 2021

DLPC900 用于高级照明控制的数字控制器

1 特性

2 应用

• 可扩展控制器支持DLP6500、DLP9000、

DLP500YX 和DLP670S 数字微镜器件(DMD)，适

用于高分辨率工业和显示应用

• 支持多种高速模式速率

• 3D 机器视觉和光学检测

• 3D 打印和增材制造

• 眼科

• 针对四肢和皮肤测量的3D 扫描仪

• 智能和自适应照明

• 3D 成像显微镜

– 高达16129Hz（1 位预存储图形模式）

– 高达2016Hz（8 位预存储图形模式，具有照明

调制）

– 高达1008Hz（16 位预存储图形模式，具有照明

调制）

3 说明

DLPC900 是一款可扩展 DMD 控制器，支持

DLP6500、DLP9000、DLP500YX 和 DLP670S DMD

的可靠运行。这款高性能 DMD 控制器为先进光控制提

供了可编程的高速图形速率，特别适用于工业应用。

DLPC900 模式速率支持快速精确的 3D 扫描和 3D 打

印，以及高分辨率和智能成像应用。DLPC900 提供

128 兆字节嵌入式 DRAM，可便捷地缓存多达 400 个

1 位图形。输入和输出触发器可轻松连接并与各种摄像

机、传感器和其他外设实现同步。

• 128 兆字节内部DRAM

• 128 兆字节外部闪存最多可存储1066 个1 位二进

制图形或133 个8 位灰度图形（取决于图形压缩

率）

• 输入与微镜1 对1 映射

• 与摄像头和传感器轻松同步

– 两个可配置输入和输出触发器

• 完全可编程的GPIO 和PWM 信号

• 多个控制接口

进入 TI DLP® 光控制技术页面，了解如何开始使用

DLPC900。

– 一个USB 1.1 从端口和三个I²C 端口

– LED 使能和PWM 发生器

ti.com 上的 DLP 先进光控制资源可加快上市速度，这

些资源包括评估模块、参考设计、光学模块制造商和

DLP 设计网络合作伙伴。

• 视频模式

– 双通道24 位RGB 输入高达120Hz

– YUV，YCrCb 或RGB 数据格式

– 支持格式为SVGA 到WQXGA 的标准视频

– DLP9000 (WQXGA)、DLP500YX (2048 ☓

1200) 和DLP670S (2716 ☓ 1600) 需要两个

DLPC900 控制器

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

DLPC900

封装

BGA (516)

27.00mm × 27.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS037

DLPC900

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ZHCSD20F –OCTOBER 2014 –REVISED JUNE 2021

Table of Contents

7 Detailed Description......................................................39

7.1 Overview...................................................................39

7.2 Functional Block Diagram.........................................39

7.3 Feature Description...................................................40

7.4 Device Functional Modes..........................................50

8 Application and Implementation..................................53

8.1 Application Information............................................. 53

8.2 Typical Applications.................................................. 53

9 Power Supply Recommendations................................62

9.1 System Power Regulation.........................................62

9.2 System Environment and Defaults............................63

9.3 System Power-Up Sequence....................................63

9.4 System Reset Operation...........................................65

10 Layout...........................................................................66

10.1 Layout Guidelines................................................... 66

10.2 Layout Example...................................................... 77

10.3 Thermal Considerations..........................................78

11 Device and Documentation Support..........................80

11.1 Device Support........................................................80

11.2 Documentation Support.......................................... 81

11.3 接收文档更新通知................................................... 81

11.4 支持资源..................................................................82

11.5 Trademarks............................................................. 82

11.6 Electrostatic Discharge Caution..............................82

11.7 术语表..................................................................... 82

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................5

6 Specifications................................................................ 21

6.1 Absolute Maximum Ratings...................................... 21

6.2 ESD Ratings............................................................. 22

6.3 Recommended Operating Conditions.......................22

6.4 Thermal Information..................................................23

6.5 Electrical Characteristics...........................................23

6.6 System Oscillators Timing Requirements ⁽¹⁾............26

6.7 Power-Up and Power-Down Timing Requirements.. 27

6.8 JTAG Interface: I/O Boundary Scan Application

Timing Requirements.................................................. 30

6.9 JTAG Interface: I/O Boundary Scan Application

Switching Characteristics............................................ 30

6.10 Programmable Output Clocks Switching

Characteristics.............................................................31

6.11 Port 1 and 2 Input Pixel Interface Timing

Requirements..............................................................31

6.12 Two Pixels Per Clock (48-Bit Bus) Timing

Requirements..............................................................32

6.13 SSP Switching Characteristics................................33

6.14 DMD Interface Switching Characteristics ⁽¹⁾.......... 35

6.15 DMD LVDS Interface Switching Characteristics..... 36

6.16 Source Input Blanking Requirements..................... 38

Information.................................................................... 82

4 Revision History

Changes from Revision E (March 2020) to Revision F ( June 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Updated terminology to primary and secondary................................................................................................. 5

• Updated "DLP LightCrafter 9000 EVM" to "DLP LightCrafter Dual DLPC900 Evaluation Module (EVM)".........5

• Added 10 kΩpulldown resistor requirement to the FAULT-STATUS pin description.........................................5

• Updated H22, T22, and U23 to be Flash Address line extensions.....................................................................5

• Updated terminology to primary and secondary............................................................................................... 21

• DLPC900A ESD Human body model (HBM) and Charged device model (CDM) information added.............. 22

• Updated terminology to primary and secondary............................................................................................... 23

• Updated section to include DLP500YX and DLP670S DMDs.......................................................................... 39

• Updated terminology to primary and secondary............................................................................................... 42

• Included DLP500YX and DLP670S DMDs in section.......................................................................................42

• Modified section to update DLPC900 Memory Space diagram and add new information about design and

layout for larger flash devices up to 128-Megabytes........................................................................................ 43

• Updated Section 7.3.5.5.2.2 to "Combining Three Chip Selects with One 128-Megabyte Flash" ...................47

• Changed "LightCrafter 6500 and the LightCrafter 9000" to "Single DLPC900 Evaluation Module" and "Dual

DLPC900 Evaluation Module".......................................................................................................................... 49

• Added 2-Gigabit Flash Memory device to Micron and Spansion devices list................................................... 49

• Updated link to DLP® LightCrafter™ Single DLPC900 Evaluation Module (EVM) User's Guide (DLPU101) or

DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) User's Guide (DLPU102)............................. 50

• Updated Minimum Exposure in Any Pattern Mode table to include DLP500YX and DLP670S DMDs............ 50

2

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• Updated Minimum Exposures for Number of Active DMD Blocks table to include DLP500YX and DLP670S

DMDs................................................................................................................................................................50

• Updated Section to include DLP500YX and DLP670S DMDs..........................................................................53

• Updated terminology to primary and secondary. ............................................................................................. 53

• Updated section to include DLP500YX and DLP670S DMDs. ........................................................................ 53

• Updated Boot Flash Memory Layout to reflect updated flash design............................................................... 55

• Updated terminology to primary and secondary...............................................................................................65

• Updated Related Documents Table..................................................................................................................81

Changes from Revision D (March 2019) to Revision E (March 2020)

Page

• 更改了DMD 对常规器件型号的引用，以移除修订依赖项.................................................................................. 1

• 对器件型号进行了通用化，以移除修订依赖项....................................................................................................1

• Updated 节11.1.1 section to show additional identification for revisions......................................................... 80

• Updated 节11.1.2 section ................................................................................................................................80

Changes from Revision C (October 2016) to Revision D (March 2019)

Page

• 将“预载”更改为“使用预存储图形模式”....................................................................................................... 1

• 删除了“存储来自128Mbit 内部DRAM 的最多400 个1 位二进制图形或50 个8 位灰度图形”......................1

• 将DRAM 和外部闪存的单位从“MB”通篇更改为“Mbit”...............................................................................1

• 将应用中的“质量控制”更改为“自动光学检测”............................................................................................1

• 添加了“增材制造”........................................................................................................................................... 1

• 在应用中添加了“抬头显示”............................................................................................................................1

• Updated R_θJCdescription from 'Junction-to-air thermal resistance' to 'Junction-to-case thermal resistance'....

23

• Changed Firmware compatibility information to version 4 for all DMDs........................................................... 27

• Deleted Power-Down Method "A" to have one Method....................................................................................28

• Changed the DMD Full-Bus Connections reference link from the DLPC900 Programmer's Guide to the DLP

LightCrafter 6500 & 9000 EVM User's Guide................................................................................................... 41

• Added note clarifying number of patterns storable in External Flash memory. ................................................50

• Changed 节11.1.2 Lines 3 - 5 to TI proprietary information.............................................................................80

Changes from Revision B (September 2016) to Revision C (October 2016)

Page

• Updated description of POSENSE and PWRGOOD..........................................................................................5

• Changed Reset Timing Requirements to Power-Up and Power-Down Timing Requirements.........................27

• Added power-up and power-down requirements for revision "B" DMDs.......................................................... 27

• Updated the description of Power-On Sense (POSENSE) Support and added cross-reference to Power-Up

and Power-Down Timing Requirements........................................................................................................... 64

• Updated the description of Power Good (PWRGOOD) Support and added cross-reference to Power-Up and

Power-Down Timing Requirements.................................................................................................................. 64

Changes from Revision A (August 2015) to Revision B (September 2016)

Page

• 将“DLP9500”更改为“DLP9000”.................................................................................................................1

• 更改了48Mbit 外部闪存的图形数量....................................................................................................................1

• 添加了“或50 个8 位灰度图形”.......................................................................................................................1

• Added Memory Design Considerations section ...............................................................................................43

• Added "(pre-stored pattern mode, pattern on-the-fly mode, or video pattern mode),"......................................50

• Added "pattern on-the-fly mode."......................................................................................................................50

• Changed to "In video pattern mode, pre-stored pattern mode, and pattern on-the-fly mode,".........................50

• Added "For faster 8-bit pattern speeds, . . .".....................................................................................................50

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ZHCSD20F –OCTOBER 2014 –REVISED JUNE 2021

• Added link to "DLP6500 & 9000 EVM User's Guide"........................................................................................50

Changes from Revision * (October 2014) to Revision A (August 2015) Page

• 将输入像素端口的宽度更正为24 位................................................................................................................... 1

• Added I/O Type and Subscript Definition table...................................................................................................5

• Corrected maximum port width of Ports 1 and 2 in table note............................................................................5

• Updated ESD Ratings table title and value column..........................................................................................22

• ESD sensitivity machine model was removed..................................................................................................22

• Added note to clarify that Ports 1 and 2 are used as 24-bit buses................................................................... 31

• Changed section title to correct bus size to 48-bits.......................................................................................... 32

• Removed references to 30-bit RGB video........................................................................................................40

• Corrected minor typos...................................................................................................................................... 50

• Corrected video pattern mode timing diagram and description........................................................................ 50

• Corrected pre-stored pattern mode timing diagram and description................................................................ 50

• Corrected pre-stored pattern mode 3 pattern example diagram and description............................................. 50

• Updated Boot Flash Memory Layout image to reflect firmware version 2.0..................................................... 55

• Added note about firmware components..........................................................................................................55

• Corrected video data interface size to 24-bits.................................................................................................. 56

• Corrected video mode port maximum size to 24 bits........................................................................................57

• Corrected P1 and P2 signal description regarding 24-bit bus width.................................................................57

• Corrected spacing and formatting.....................................................................................................................65

• Corrected minor typo........................................................................................................................................ 74

• Changed the number of P1 and P2 lines to reflect 24 bit-width........................................................................74

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5 Pin Configuration and Functions

图5-1. ZPC Package 516-Pin BGA Bottom View

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表5-1. Initialization Pin Functions

I/O

POWER

I/O

CLK SYSTEM

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

NUMBER

Power-On Sense is an active high signal with hysteresis,

generated from an external voltage monitor circuit. This signal

is driven active high when all the controller supply voltages

have reached 90% of their specified minimum voltage. This

signal is driven inactive low after the falling edge of

PWRGOOD as shown in 图6-4 and 图6-5. Refer to 节6.7 for

more details.

I₄

H

POSENSE

P22

VDD33

Async

Power Good is an active high signal with hysteresis that is

provided from an external voltage monitor circuit. A high value

indicates all power is within operating voltage specifications

and the system is safe to exit its RESET state. Refer to 节6.7

for more details.

I₄

H

PWRGOOD

EXT_ARSTZ

T26

T24

General purpose active low reset output signal. This output is

driven low immediately after POSENSE is externally driven

low, placing the system in RESET and remains low while

POSENSE remains low. EXT_ARSTZ will continue to be held

low after POSENSE is driven high and released by the

controller firmware. EXT_ARSTZ is also driven low

approximately 5 µs after the detection of a PWRGOOD or any

internally generated reset. In all cases, it will remain active for

a minimum of 2 ms.

VDD33

O₂

Async

Controller active low reset output signal. This output is driven

low immediately after POSENSE is externally driven low and

remains low while POSENSE remains low. CTRL_ARSTZ will

continue to be held low after POSENSE is driven high and

released by the controller firmware. CTRL_ARSTZ is also

optionally asserted low approximately 5 µs after the detection

of a PWRGOOD or any internally generated reset. In all

cases it will remain active for a minimum of 2 ms.

CTRL_ARSTZ

T25

VDD33

O₂

Async

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

表5-2. DMD Control Pin Functions

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

DMD output-enable (active low). This signal does not apply to

the secondary controller in a two-controller system

configuration. On the secondary controller, this pin is reserved

and must be left unconnected.

DADOEZ

AE7

VDD33

O₅

Async

DADADDR_3

DADADDR_2

DADADDR_1

DADADDR_0

AD6

AE5

AF4

AB8

DMD address. This signal does not apply to the secondary

controller in a two-controller system configuration. On the

secondary controller, this pin is reserved and must be left

unconnected.

DMD mode. This signal does not apply to the secondary

controller in a two-controller system configuration. On the

secondary controller, this pin is reserved and must be left

unconnected.

DADMODE_1

DADMODE_0

AD7

AE6

DMD select. This signal does not apply to the secondary

controller in a two-controller system configuration. On the

secondary controller, this pin is reserved and must be left

unconnected.

DADSEL_1

DADSEL_0

AE4

AC7

DMD strobe. This signal does not apply to the secondary

controller in a two-controller system configuration. On the

secondary controller, this pin is reserved and must be left

unconnected.

DADSTRB

AF5

6

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表5-2. DMD Control Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

I₄

DMD interrupt (active low). Requires an external 1-kΩpullup

resistor.

DAD_INTZ

AC8

VDD33

Async

H

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

表5-3. DMD LVDS Interface Pin Functions

PIN^{(3) (4)}

CLK

I/O POWER

I/O TYPE⁽¹⁾

DESCRIPTION⁽²⁾

SYSTEM

NAME

NUMBER

DCKA_P

DCKA_N

V4

V3

DCKA_P

DCKA_N

VDD18

O₇

DMD, LVDS interface channel A, differential clock.

DMD, LVDS interface channel A, differential serial

SCA_P

SCA_N

V2

V1

DCKA_P

DCKA_N control.

DDA_P_15

DDA_N_15

DDA_P_14

DDA_N_14

DDA_P_13

DDA_N_13

DDA_P_12

DDA_N_12

DDA_P_11

DDA_N_11

DDA_P_10

DDA_N_10

DDA_P_9

DDA_N_9

DDA_P_8

DDA_N_8

P4

P3

P2

P1

R4

R3

R2

R1

T4

T3

T2

T1

U4

U3

U2

U1

DCKA_P

DCKA_N

VDD18

O₇

DMD, LVDS interface channel A, differential serial data.

DDA_P_7

DDA_N_7

DDA_P_6

DDA_N_6

DDA_P_5

DDA_N_5

DDA_P_4

DDA_N_4

DDA_P_3

DDA_N_3

DDA_P_2

DDA_N_2

DDA_P_1

DDA_N_1

DDA_P_0

DDA_N_0

W4

W3

W2

W1

Y2

Y1

Y4

Y3

AA2

AA1

AA4

AA3

AB2

AB1

AC2

AC1

DCKB_P

DCKB_N

J3

J4

DCKB_P

DCKB_N

VDD18

O₇

DMD, LVDS interface channel B, differential clock.

DMD, LVDS interface channel B, differential serial

SCB_P

SCB_N

J1

J2

DCKB_P

DCKB_N control.

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表5-3. DMD LVDS Interface Pin Functions (continued)

PIN^{(3) (4)}

CLK

I/O POWER

I/O TYPE⁽¹⁾

DESCRIPTION⁽²⁾

SYSTEM

NAME

NUMBER

DDB_P_15

DDB_N_15

DDB_P_14

DDB_N_14

DDB_P_13

DDB_N_13

DDB_P_12

DDB_N_12

DDB_P_11

DDB_N_11

DDB_P_10

DDB_N_10

DDB_P_9

DDB_N_9

DDB_P_8

DDB_N_8

N1

N2

N3

N4

M2

M1

M3

M4

L1

L2

L3

L4

K1

K2

K3

K4

DCKB_P

DCKB_N

VDD18

O₇

DMD, LVDS interface channel B, differential serial data.

DDB_P_7

DDB_N_7

DDB_P_6

DDB_N_6

DDB_P_5

DDB_N_5

DDB_P_4

DDB_N_4

DDB_P_3

DDB_N_3

DDB_P_2

DDB_N_2

DDB_P_1

DDB_N_1

DDB_P_0

DDB_N_0

H1

H2

H3

H4

G1

G2

G3

G4

F1

F2

F3

F4

E1

E2

D1

D2

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) Several options allow reconfiguration of the DMD interface in order to better optimize board layout. The DLPC900 can swap channel A

with channel B. The DLPC900 can also swap the data bit order within each channel independent of swapping the A and B channels.

(4) The DLPC900 is a full-bus DMD signaling interface. 图7-4 shows the controller connections for this configuration.

表5-4. Program Memory Flash Interface Pin Functions

PIN⁽³⁾

DESCRIPTION

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

CHIP SELECT 0

(ADDITIONAL

FLASH)

CHIP SELECT 1

(BOOT FLASH

ONLY) ^{(2) (3)}

CHIP SELECT 2

(ADDITIONAL

FLASH)

NAME

NUMBER

D13

Chip select

(active low)

PM_CSZ_0 ⁽⁴⁾

PM_CSZ_1 ⁽⁴⁾

PM_CSZ_2 ⁽⁴⁾

VDD33

O₅

Async

N/A

Boot flash chip

select

E12

N/A

(active low)

Chip select

(active low)

A13

A12

VDD33

O₅

B₅

Async

N/A

Address bit

(MSB)

PM_ADDR_22 ⁽⁵⁾

Address bit (MSB)

PM_ADDR_21 ⁽⁵⁾

PM_ADDR_20

PM_ADDR_19

PM_ADDR_18

PM_ADDR_17

E11

D12

C12

B11

A11

VDD33

B₅

O₅

Async

Address bit

8

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表5-4. Program Memory Flash Interface Pin Functions (continued)

PIN⁽³⁾

DESCRIPTION

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

CHIP SELECT 0

(ADDITIONAL

FLASH)

CHIP SELECT 1

(BOOT FLASH

ONLY) ^{(2) (3)}

CHIP SELECT 2

(ADDITIONAL

FLASH)

NAME

NUMBER

PM_ADDR_16

PM_ADDR_15

PM_ADDR_14

PM_ADDR_13

PM_ADDR_12

PM_ADDR_11

PM_ADDR_10

PM_ADDR_9

PM_ADDR_8

PM_ADDR_7

PM_ADDR_6

PM_ADDR_5

PM_ADDR_4

PM_ADDR_3

PM_ADDR_2

PM_ADDR_1

PM_ADDR_0

D11

C11

E10

D10

C10

B9

VDD33

O₅

O5

O₅

O5

O₅

Async

Address bit

A9

E9

D9

C9

B8

A8

D8

C8

B7

A7

C7

Address bit (LSB) Address bit (LSB) Address bit (LSB)

Write-enable

(active low)

Write-enable

(active low)

Write-enable

(active low)

PM_WEZ

PM_OEZ

B12

C13

VDD33

O₅

Async

Output-enable

(active low)

Output-enable

(active low)

Output-enable

(active low)

UpperByte(15:8)

enable

(active low)

UpperByte(15:8)

Enable

(active low)

PM_BLSZ_1

PM_BLSZ_0

B6

A6

VDD33

O₅

Async

N/A

LowerByte(7:0)

enable

LowerByte(7:0)

Enable

(active low)

PM_DATA_15

PM_DATA_14

PM_DATA_13

PM_DATA_12

PM_DATA_11

PM_DATA_10

PM_DATA_9

PM_DATA_8

PM_DATA_7

PM_DATA_6

PM_DATA_5

PM_DATA_4

PM_DATA_3

PM_DATA_2

PM_DATA_1

PM_DATA_0

C17

B16

A16

A15

B15

D16

C16

E14

D15

C15

B14

A14

E13

D14

C14

B13

VDD33

B₅

Async

Data bit (15)

Data bit (14)

Data bit (13)

Data bit (12)

Data bit (11)

Data bit (10)

Data bit (9)

Data bit (8)

Data bit (7)

Data bit (6)

Data bit (5)

Data bit (4)

Data bit (3)

Data bit (2)

Data bit (1)

Data bit (0)

Data bit (15)

Data bit (14)

Data bit (13)

Data bit (12)

Data bit (11)

Data bit (10)

Data bit (9)

Data bit (8)

Data bit (7)

Data bit (6)

Data bit (5)

Data bit (4)

Data bit (3)

Data bit (2)

Data bit (1)

Data bit (0)

Data bit (15)

Data bit (14)

Data bit (13)

Data bit (12)

Data bit (11)

Data bit (10)

Data bit (9)

Data bit (8)

Data bit (7)

Data bit (6)

Data bit (5)

Data bit (4)

Data bit (3)

Data bit (2)

Data bit (1)

Data bit (0)

(1) Refer to I/O Type and Subscript Definition (表5-15).

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(2) The default wait-state is set for a flash device of 120 ns access time. Therefore, the slowest flash access time supported is 120 ns.

Refer to the 节8.2.1.2.1.4.2 on how to program new wait-state values.

(3) Refer to the 图8-2 for the memory layout of the boot flash.

(4) Requires an external 10-kΩpullup resistor.

(5) Requires an external 10-kΩpulldown resistor.

表5-5. Port 1 and Port 2 Channel Data and Control Pin Functions

PIN ^{(3) (4) (5)}

I/O

POWER

I/O

CLK SYSTEM

DESCRIPTION⁽²⁾

TYPE⁽¹⁾

NAME

NUMBER

Input port data pixel write clock (selectable as rising or falling

edge triggered, and with which port it is associated (Port 1 or

Port 2 or (Port 1 and Port 2))).

I₄

D

P_CLK1

AE22

VDD33

N/A

Input port data pixel write clock (selectable as rising or falling

edge triggered, and with which port it is associated (Port 1 or

Port 2 or (Port 1 and Port 2))).

I₄

D

P_CLK2

W25

AF23

AF22

W24

N/A

Input port data pixel write clock (selectable as rising or falling

edge triggered, and with which port it is associated (Port 1 or

Port 2 or (Port 1 and Port 2))).

I₄

D

P_CLK3

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Active high data enable. Selectable as to which port it is

associated with (Port 1 or Port 2 or (Port 1 and Port 2)).

P_DATEN1

P_DATEN2

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Active high data enable. Selectable as to which port it is

associated with (Port 1 or Port 2 or (Port 1 and Port 2)).

P1_A9

P1_A8

P1_A7

P1_A6

P1_A5

P1_A4

P1_A3

P1_A2

P1_A1 ⁽³⁾

P1_A0 ⁽³⁾

AD15

AE15

AE14

AE13

AD13

AC13

AF14

AF13

AF12

AE12

Port 1 A channel input pixel data (bit weight 128)

Port 1 A channel input pixel data (bit weight 64)

Port 1 A channel input pixel data (bit weight 32)

Port 1 A channel input pixel data (bit weight 16)

Port 1 A channel input pixel data (bit weight 8)

Port 1 A channel input pixel data (bit weight 4)

Port 1 A channel input pixel data (bit weight 2)

Port 1 A channel input pixel data (bit weight 1)

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

VDD33

Unused, tie to 0

P1_B9

P1_B8

P1_B7

P1_B6

P1_B5

P1_B4

P1_B3

P1_B2

P1_B1 ⁽³⁾

P1_B0 ⁽³⁾

AF18

AB18

AC15

AC16

AD16

AE16

AF16

AF15

AC14

AD14

Port 1 B channel input pixel data (bit weight 128)

Port 1 B channel input pixel data (bit weight 64)

Port 1 B channel input pixel data (bit weight 32)

Port 1 B channel input pixel data (bit weight 16)

Port 1 B channel input pixel data (bit weight 8)

Port 1 B channel input pixel data (bit weight 4)

Port 1 B channel input pixel data (bit weight 2)

Port 1 B channel input pixel data (bit weight 1)

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Unused, tie to 0

P1_C9

P1_C8

P1_C7

P1_C6

P1_C5

P1_C4

P1_C3

P1_C2

P1_C1 ⁽³⁾

P1_C0 ⁽³⁾

AD20

AE20

AE21

AF21

AD19

AE19

AF19

AF20

AC19

AE18

Port 1 C channel input pixel data (bit weight 128)

Port 1 C channel input pixel data (bit weight 64)

Port 1 C channel input pixel data (bit weight 32)

Port 1 C channel input pixel data (bit weight 16)

Port 1 C channel input pixel data (bit weight 8)

Port 1 C channel input pixel data (bit weight 4)

Port 1 C channel input pixel data (bit weight 2)

Port 1 C channel input pixel data (bit weight 1)

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

B₂

D

Port 1 vertical sync. While intended to be associated with port

1, it can be programmed for use with port 2.

P1_VSYNC

P1_HSYNC

AC20

AD21

VDD33

P_CLK1,

P_CLK2, or

P_CLK3

B₂

D

Port 1 horizontal sync. While intended to be associated with

port 1, it can be programmed for use with port 2.

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表5-5. Port 1 and Port 2 Channel Data and Control Pin Functions (continued)

PIN ^{(3) (4) (5)}

I/O

POWER

I/O

CLK SYSTEM

DESCRIPTION⁽²⁾

TYPE⁽¹⁾

NAME

NUMBER

P2_A9

P2_A8

P2_A7

P2_A6

P2_A5

P2_A4

P2_A3

P2_A2

P2_A1 ⁽³⁾

P2_A0 ⁽³⁾

AD26

AD25

AB21

AC22

AD23

AB20

AC21

AD22

AE23

AB19

Port 2 A channel input pixel data (bit weight 128)

Port 2 A channel input pixel data (bit weight 64)

Port 2 A channel input pixel data (bit weight 32)

Port 2 A channel input pixel data (bit weight 16)

Port 2 A channel input pixel data (bit weight 8)

Port 2 A channel input pixel data (bit weight 4)

Port 2 A channel input pixel data (bit weight 2)

Port 2 A channel input pixel data (bit weight 1)

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

VDD33

Unused, tie to 0

P2_B9

P2_B8

P2_B7

P2_B6

P2_B5

P2_B4

P2_B3

P2_B2

P2_B1 ⁽³⁾

P2_B0 ⁽³⁾

Y22

Port 2 B channel input pixel data (bit weight 128)

Port 2 B channel input pixel data (bit weight 64)

Port 2 B channel input pixel data (bit weight 32)

Port 2 B channel input pixel data (bit weight 16)

Port 2 B channel input pixel data (bit weight 8)

Port 2 B channel input pixel data (bit weight 4)

Port 2 B channel input pixel data (bit weight 2)

Port 2 B channel input pixel data (bit weight 1)

Unused, tie to 0

AB26

AA23

AB25

AA22

AB24

AC26

AB23

AC25

AC24

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Unused, tie to 0

P2_C9

P2_C8

P2_C7

P2_C6

P2_C5

P2_C4

P2_C3

P2_C2

P2_C1 ⁽³⁾

P2_C0 ⁽³⁾

W23

V22

Y26

Y25

Y24

Port 2 C channel input pixel data (bit weight 128)

Port 2 C channel input pixel data (bit weight 64)

Port 2 C channel input pixel data (bit weight 32)

Port 2 C channel input pixel data (bit weight 16)

Port 2 C channel input pixel data (bit weight 8)

Port 2 C channel input pixel data (bit weight 4)

Port 2 C channel input pixel data (bit weight 2)

Port 2 C channel input pixel data (bit weight 1)

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

I₄

D

Y23

W22

AA26

AA25

AA24

Unused, tie to 0

P_CLK1,

P_CLK2, or

P_CLK3

B₂

D

Port 2 vertical sync. While intended to be associated with port

2, it can be programmed for use with port 1.

P2_VSYNC

P2_HSYNC

U22

VDD33

P_CLK1,

P_CLK2, or

P_CLK3

B₂

D

Port 2 horizontal sync. While intended to be associated with

port 2, it can be programmed for use with port 1.

W26

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) Port 1 and Port 2 are capable of 24-bits each. A maximum of 8-bits is available in each of the A, B, and C channels. The 8-bit color

inputs are connected to bits [9:2] of the corresponding A, B, C input channels. Sources feeding 8-bits or less per color component

channel are MSB justified when connected to the DLPC900, and the LSBs tied to ground along with the data lines 0 and 1 from every

channel. Three port clocks options (1, 2, and 3) are provided to improve the signal integrity.

(4) Ports 1 and 2 can be used separately as two 24-bit ports, or can be combined into one 48-bit port (typically, for high data rate sources)

for transmission of two pixels per clock.

(5) The A, B, C input data channels of ports 1 and 2 can be internally reconfigured or remapped for optimum board layout. Specifically

each channel can individually remapped to the internal GBR/ YCbCr channels. For example, G data can be connected to channel A, B,

or C and remapped to be appropriate channel internally. Port configuration and channel multiplexing is handled in the API software.

表5-6. Clock and PLL Support Pin Functions

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

MOSC

MOSCN

NUMBER

M26

System clock oscillator input (3.3-V LVTTL). MOSC must be

stable a maximum of 25 ms after POSENSE transitions from

low to high.

VDD33

I₁₀

N/A

N26

O₁₀

MOSC crystal return.

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表5-6. Clock and PLL Support Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

General-purpose output clock A. The frequency is software

programmable. Power-up default is 787 kHz and the output

frequency is maintained through all operations, except

power loss and reset.

OCLKA ⁽³⁾

AF6

VDD33

O₅

Async

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) This signal does not apply to the secondary controller in a two controller system configuration. On the secondary controller, this pin is

reserved and must be left unconnected. Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two

controller configuration.

表5-7. Board-Level Test and Debug Pin Functions

PIN ⁽³⁾

I/O

CLK

DESCRIPTION⁽²⁾

POWER

TYPE⁽¹⁾

SYSTEM

NAME

NUMBER

I₄

U

JTAG serial data in. Used in both Boundary Scan and ICE

modes.

TDI

N25

VDD33

TCK

N/A

I₄

D

JTAG serial data clock. Used in both Boundary Scan and ICE

modes.

TCK

N24

P25

P26

I₄

U

TMS1

TMS2

TCK

JTAG test mode select. Used in Boundary Scan mode.

JTAG-ICE test mode select. Used in ICE mode.

I₄

U

TDO1

TDO2

N23

N22

VDD33

O₅

TCK

JTAG serial data out. Used in Boundary Scan mode.

JTAG-ICE serial data out. Used in ICE mode.

JTAG Reset. Used in both Boundary Scan and ICE modes.

This pin is pulled high (or left unconnected) when the JTAG

interface is in use for boundary scan or debug. Connect this

to ground otherwise. Failure to tie this pin low during normal

operation will cause startup and initialization problems.

I₄

H

U

TRSTZ

M23

VDD33

Async

RTCK

E4

VDD33

O₂

N/A

JTAG return clock. Used in ICE mode.

IC tri-state enable (active high). Asserting high will tri-state all

outputs except the JTAG interface. Requires an external

4.7 kΩpulldown resistor.

I₄

H

D

ICTSEN

M24

Async

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) All JTAG signals are LVTTL compatible.

表5-8. Device Test Pin Functions

I/O

POWER

I/O

CLK

SYSTEM

DESCRIPTION⁽²⁾

TYPE⁽¹⁾

NAME

NUMBER

I₄

H

D

Device manufacturing test enable. This signal must be

connected to an external ground for normal operation.

HW_TEST_EN

M25

VDD33

N/A

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

表5-9. Peripheral Interface Pin Functions

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

I²C bus 0, clock. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

I2C0_SCL

A10

VDD33

B₈

N/A

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表5-9. Peripheral Interface Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

I²C bus 0, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

I2C0_SDA

B10

VDD33

B₈

B₂

I2C0_SCL

I2C1_SCL

N/A

I²C bus 1, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

I2C1_SDA ⁽³⁾

I2C1_SCL ⁽³⁾

I2C2_SDA ⁽³⁾

I2C2_SCL ⁽³⁾

E19

D20

C21

B22

I²C bus 1, clock. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

I²C bus 2, data. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

I2C2_SCL

I²C bus 2, clock. This bus supports 400 kHz, fast mode

operation. This input is not 5 V tolerant. This pin requires an

external pullup resistor to 3.3 V. The minimum acceptable

pullup value is 1 kΩresistor.

N/A

SSP0_CLK

SSP0_RXD

SSP0_TXD

AD4

AD5

AB7

AC5

VDD33

B₅

I₄

Synchronous serial port 0, clock

SSP0_CLK Synchronous serial port 0, receive data in

SSP0_CLK Synchronous serial port 0, transmit data out

SSP0_CLK Synchronous serial port 0, chip select 0 (active low)

O₅

B₅

SSP0_CSZ_0 ⁽³⁾

SSP0_CSZ_1 ⁽³⁾

SSP0_CSZ_2 ⁽³⁾

UART0_TXD

Synchronous serial port 0, chip select 1 (active low)

SSP0_CLK

AB6

AC3

AB3

VDD33

B₅

O₅

This signal connects to the DMD SCP_ENZ input

SSP0_CLK Synchronous serial port 0, chip select 2 (active low)

UART0, UART transmit data output. The firmware only

outputs debug messages on this port.

Async

UART0, UART receive data input. The firmware does not

support receiving data on this port.

UART0_RXD

UART0_RTSZ

AD1

AD2

VDD33

I₄

Async

UART0, UART ready to send hardware flow control output

(active low)

O₅

Async

UART0, UART clear to send hardware flow control input

UART0_CTSZ

AE2

VDD33

I₄

Async

(active low). This pin requires an external 10 kΩpulldown

resistor.

USB_DAT_N ⁽³⁾

USB_DAT_P

C5

D6

USB D–I/O

USB D+ I/O

B₉

Boot mode. When this pin is held low, the firmware boots-up

in bootload mode. When pin is held high, the firmware

boots-up in normal operating mode. This pin requires an

external 1 kΩpullup resistor.

HOLD_BOOTZ

F24

VDD33

B₂

Async

The firmware will use this pin to enable an external buffer on

the USB data lines after it has completed initialization.

USB_ENZ ⁽³⁾

FAULT_STATUS

HEARTBEAT

SEQ_INT2

E25

AC11

AB12

H26

VDD33

B₂

O₂

I₂

Async

This signal toggles or held high to indicate status faults. This

pin requires an external 10 kΩpulldown resistor.

This signal toggles to indicate the system is operational.

Period is approximately 1 second.

This signal serves as an interrupt for pattern sequencing

and must be connected to SEQ_AUX6.

This signal serves as an interrupt for pattern sequencing

and must be connected to SEQ_AUX7.

SEQ_INT1

G26

I₂

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表5-9. Peripheral Interface Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

This signal serves as an interrupt for pattern sequencing

and must be connected to SEQ_INT1.

SEQ_AUX7

F26

VDD33

O₂

Async

This signal serves as an interrupt for pattern sequencing

and must be connected to SEQ_INT2.

SEQ_AUX6

E26

K22

In a dual DLPC900 configuration, this pin connects to the

FPGA and could serve as a configuration pin. Otherwise

can be left unconnected.

TEST_FUNC_5 ⁽³⁾

TEST_FUNC_4 ⁽³⁾

VDD33

B₂

Async

In a dual DLPC900 configuration, this pin connects to the

FPGA and could serve as a configuration pin. Otherwise

can be left unconnected.

J26

J25

In a dual DLPC900 configuration, this pin connects to the

FPGA and serves as a configuration pin. This function

configures the 24-bit parallel data output of the FPGA to be

split between the primary and the secondary controllers.

The firmware will set this pin high by default.

TEST_FUNC_3 ⁽³⁾

VDD33

B₂

Async

In a dual DLPC900 configuration, this pin connects to the

FPGA and could serve as a configuration pin. Otherwise

can be left unconnected.

TEST_FUNC_2 ⁽³⁾

TEST_FUNC_1 ⁽³⁾

GPIO_08 ⁽³⁾

J24

J23

E21

V23

V24

U24

U25

A23

A22

B21

A21

VDD33

B₂

Async

In a dual DLPC900 configuration, this pin connects to the

FPGA and could serve as a configuration pin. Otherwise

can be left unconnected.

This pin can be configured as GPIO 8. An external pullup

resistor is required when this pin is configured as open-

drain. ⁽⁴⁾

This pin can be configured as GPIO 7. An external pullup

resistor is required when this pin is configured as open-

drain. ⁽⁴⁾

GPIO_07 ⁽³⁾

This pin can be configured as GPIO 6. An external pullup

resistor is required when this pin is configured as open-

drain. ⁽⁴⁾

GPIO_06 ⁽³⁾

This pin can be configured as GPIO 5. An external pullup

resistor is required when this pin is configured as open-

drain. ⁽⁴⁾

GPIO_05 ⁽³⁾

This pin can be configured as GPIO 4. An external pullup

resistor is required when this pin is configured as open-

drain. ⁽⁴⁾

GPIO_04 ⁽³⁾

This pin can be configured as GPIO 3 or PWM 3. An

external pullup resistor is required when this pin is

configured as open-drain. ⁽⁴⁾

GPIO_PWM_03 ⁽³⁾

GPIO_PWM_02 ⁽³⁾

GPIO_PWM_01 ⁽³⁾

GPIO_PWM_00 ⁽³⁾

This pin can be configured as GPIO 2 or PWM 2. An

external pullup resistor is required when this pin is

configured as open-drain. ⁽⁴⁾

This pin can be configured as GPIO 1 or PWM 1. An

external pullup resistor is required when this pin is

configured as open-drain. ⁽⁴⁾

This pin can be configured as GPIO 0 or PWM 0. An

external pullup resistor is required when this pin is

configured as open-drain. ⁽⁴⁾

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) This signal does not apply to the secondary controller in a two controller system configuration. On the secondary controller, this pin is

reserved and must be left unconnected. Refer to 节8.2.2 and 节8.2.1 for a description between a one controller and a two controller

configuration.

(4) GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more

alternative use modes, which are also software-configurable. The reset default for all GPIO signals is as an input signal. Refer to the

DLPC900 Programmer's Guide (DLPU018).

14

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表5-10. Trigger Control Pin Functions

PIN ⁽³⁾

I/O

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

POWER

NAME

NUMBER

In video pattern mode, this signal is used for advancing the

pattern display.

TRIG_IN_1

AF7

VDD33

I₄

Async

In video pattern mode, the rising edge of this signal is used

for starting the pattern display and the falling edge is used

for stopping the pattern display. It works along with the

software start stop command.

TRIG_IN_2

H25

I₂

TRIG_OUT_1

TRIG_OUT_2

E20

D22

VDD33

O₂

Async

Active high trigger output signal during pattern exposure.

Active high trigger output to indicate first pattern display.

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) These signals do not apply to the secondary controller in a two controller system configuration. On the secondary controller, these pins

are reserved and must be left unconnected. Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two

controller configuration.

表5-11. LED Control Pin Functions

PIN ⁽³⁾

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

C20

BLU_LED_PWM

GRN_LED_PWM

RED_LED_PWM

BLU_LED_EN

GRN_LED_EN

RED_LED_EN

VDD33

O₂

Async

Blue LED PWM current control signal.

Green LED PWM current control signal.

Red LED PWM current control signal.

Blue LED enable signal.

B20

B19

D24

C25

Green LED enable signal.

B26

Red LED enable signal.

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) These signals do not apply to the secondary controller in a two controller system configuration. On the secondary controller, these pins

are reserved and must be left unconnected. Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two

controller configuration.

表5-12. Two Controller Support Pin Functions

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

Sequence sync. This signal must be connected between the

primary and secondary controller in a two controller

configuration. Do not leave unconnected. This pin requires

an external 10-kΩpullup resistor.

SEQ_SYNC

AB9

VDD33

B₃

B₂

Async

This signal is used by the primary controller to communicate

with the secondary controller over the SSP interface. This

pin requires an external 4.7-kΩpullup resistor.

SSP0_CSZ4_SLV

U26

SSP0_CLK

FSD12_OUTPUT

DA_SYNC_INPUT

T23

R22

VDD33

B₂

Async

This pin must be connected to DA_SYNC_INPUT ⁽³⁾

This pin must be connected to FSD12_OUTPUT ⁽⁴⁾

This signal must be connected between the primary and

secondary controller in a two controller configuration. The

secondary controller will pull this signal high to inform the

primary controller that it is present and ready. This pin

requires an external 10-kΩpulldown resistor. Do not leave

unconnected.

SLV_CTRL_PRST

V25

VDD33

B₂

Async

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表5-12. Two Controller Support Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

When this pin is high, the controller operates as the primary

controller. When this pin is low the controller operates as the

secondary controller. Use an external 4.7-kΩpullup or

pulldown resistor to identify the controller. Do not leave

unconnected.

CTRL_MODE_CFG

V26

VDD33

B₂

Async

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

(3) The FSD12_OUTPUT of the secondary controller must be left unconnected.

(4) The DA_SYNC_INPUT of the secondary controller must be connected to the FSD12_OUTPUT of the primary controller.

表5-13. Reserved Pin Functions

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

NUMBER

Reserved. This pin requires an external 4.7-kΩpullup

resistor.

AFE_ARSTZ

AC12

VDD33

O₂

Async

RESERVED_AD12

AFE_IRQ

AD12

AB13

AF11

AD11

AE11

VDD33

O₆

I₄

N/A

Async

N/A

Reserved. Must be left unconnected.

RESERVED_AF11

RESERVED_AD11

RESERVED_AE11

I₄

N/A

I₄

N/A

Reserved. This pin requires an external 10-kΩpullup

resistor.

RESERVED_AE8

AE8

VDD33

I₄

N/A

RESERVED_AD8

RESERVED_AC9

AD8

AC9

VDD33

O₅

N/A

Reserved. Must be left unconnected.

Reserved. This pin Requires an external 10-kΩpulldown

resistor.

RESERVED_AF8

AF8

VDD33

I₄

N/A

RESERVED_E3

E3

VDD33

B₅

B₂

N/A

Reserved. Must be left unconnected.

RESERVED_AB10

RESERVED_AD9

RESERVED_AE9

RESERVED_AF9

RESERVED_AB11

RESERVED_AC10

RESERVED_AD10

RESERVED_AE10

RESERVED_AF10

RESERVED_K24

RESERVED_K23

RESERVED_J22

RESERVED_H24

RESERVED_H23

AB10

AD9

AE9

AF9

AB11

AC10

AD10

AE10

AF10

K24

K23

J22

H24

H23

Used for Flash memory address extension. Pull down to

GND with 10-kΩresistor.

RESERVED_H22

H22

VDD33

B₂

N/A

RESERVED_G25

RESERVED_F25

RESERVED_G24

RESERVED_G23

G25

F25

G24

G23

VDD33

B₂

N/A

Reserved. Must be left unconnected.

16

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表5-13. Reserved Pin Functions (continued)

I/O

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

POWER

NUMBER

Used for Flash memory address extension. Pull down to

GND with 10-kΩresistor.

RESERVED_T22

RESERVED_U23

T22

VDD33

B₂

N/A

Used for Flash memory address extension. Pull down to

GND with 10-kΩresistor.

U23

RESERVED_G22

RESERVED_F23

RESERVED_D26

RESERVED_E24

RESERVED_F22

RESERVED_D25

RESERVED_E23

RESERVED_C26

RESERVED_AB4

RESERVED_C23

RESERVED_D21

RESERVED_B24

RESERVED_C22

RESERVED_B23

RESERVED_A20

RESERVED_A19

RESERVED_E18

RESERVED_D19

RESERVED_C19

G22

F23

D26

E24

F22

D25

E23

C26

AB4

C23

D21

B24

C22

B23

A20

A19

E18

D19

C19

VDD33

B₂

B₅

B₂

N/A

Reserved. Must be left unconnected.

B₂

D

RESERVED_E8

RESERVED_B4

RESERVED_C4

RESERVED_E7

RESERVED_D5

RESERVED_E6

RESERVED_D3

RESERVED_C2

RESERVED_A4

RESERVED_B5

RESERVED_C6

RESERVED_A5

E8

B4

C4

E7

D5

E6

D3

C2

A4

B5

C6

A5

VDD33

N/A

Reserved. Must be left unconnected.

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

B₂

D

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表5-13. Reserved Pin Functions (continued)

I/O

POWER

I/O TYPE⁽¹⁾CLK SYSTEM

DESCRIPTION⁽²⁾

NAME

RESERVED_D7

NUMBER

B₂

N/A

D

D7

VDD33

Reserved. Must be left unconnected.

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller configuration.

表5-14. Power and Ground Pin Functions

PIN⁽³⁾

I/O TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

NUMBER

F20, F17, F11, F8, L21, R21, Y21,

AA19, AA16, AA10, AA7

VDD33

PWR

3.3-V I/O power

C1, F5, G6, K6, M5, P5, T5,

W6, AA5, AE1, H5, N6, T6,

AA13, U21, P21, H21, F14

F19, F16, F13, F10, F7, H6, L6,

P6, U6, Y6, AA8, AA11, AA14, AA17,

AA20, W21, T21, N21, K21, G21, L11,

T11, T16, L16

1.8-V internal DRAMVDD and LVDSAVD I/O power

(To shut this power down in a system low-power mode, see

the 节9.3.)

VDD18

VDDC

PWR

1.15-V core power

1.15-V DMD clock generator PLL

Digital power

PLLD_VDD

PLLD_VSS

PLLD_VAD

PLLD_VAS

PLLM1_VDD

PLLM1_VSS

PLLM1_VAD

PLLM1_VAS

PLLM2_VDD

PLLM2_VSS

PLLM2_VAD

PLLM2_VAS

PLLS_VAD

PLLS_VAS

L22

L23

K25

K26

L26

M22

L24

L25

P23

P24

R25

R26

R23

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

1.15-V DMD clock generator PLL

Digital GND

1.8-V DMD clock generator PLL

Analog power

1.8-V DMD clock generator PLL

Analog GND

1.15-V primary-LS clock generator PLL

Digital power

1.15-V primary-LS clock generator PLL

Digital GND

1.8-V primary-LS clock generator PLL

Analog power

1.8-V primary-LS clock generator PLL

Analog GND

1.15-V primary-HS clock generator PLL

Digital power

1.15-V primary-HS clock generator PLL

Digital GND

1.8-V primary-HS clock generator PLL

Analog power

1.8-V primary-HS clock generator PLL

Analog GND

1.15-V video-2X clock generator PLL

Analog power

1.15-V video-2X clock generator PLL

Analog GND

R24

B18, D18, B17, E17, A18, C18, A17,

L_VDQPAD_[7:0], D17, AE17, AC17, AF17, AC18, AB16,

DRAM direct test pins (for manufacturing use only). These

pins must be tied directly to ground for normal operation.

RES

R_VDQPAD_[7:0]

AD17,

AB17, AD18

18

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表5-14. Power and Ground Pin Functions (continued)

PIN⁽³⁾

I/O TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

NUMBER

DRAM direct test control pin (for manufacturing use only).

This pin must be tied directly to 3.3 I/O power (VDD33) for

normal operation.

CFO_VDD33

AE26

RES

DRAM direct test control pins (for manufacturing use only).

These pins must be tied directly to ground for normal

operation.

VTEST1, VTEST2,

VTEST3, VTEST4

AB14, AB15, E15, E16

RES

LVDS_AVS1,

LVDS_AVS2

Dedicated ground for LVDS bandgap reference. These pins

must be tied directly to ground for normal operation.

V5, K5

AC6

PWR

Fuse programming pin (for manufacturing use only). This pin

must be tied directly to ground for normal operation.

VPGM

A26, A25, A24, B25, C24, D23,

E22, F21, F18, F15, F12, F9, F6,

E5, D4, C3, B3, A3, B2, A2,

B1, A1, G5, J5, J6, L5, M6,

N5, R5, R6, U5, V6, W5, Y5,

AA6, AB5, AC4, AD3, AE3, AF3, AF2,

AF1, AA9, AA12, AA15, AA18, AA21,

AB22,

GND

Common ground

AC23, AD24, AE24, AF24, AE25,

AF25, AF26,

V21, M21, J21, L15, L14, L13, L12,

M16, M15, M14, M13, M12, M11, N16,

N15, N14, N13, N12, N11, P16, P15,

P14, P13, P12, P11, R16, R15, R14,

R13, R12, R11, T15, T14, T13, T12

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表5-15. I/O Type and Subscript Definition

I/O

ESD STRUCTURE

(SUBSCRIPT)

DESCRIPTION

(3)

1

2

3

4

5

N/A

3.3 LVTTL I/O buffer, with 8-mA drive

3.3 LVTTL I/O buffer, with 12-mA drive

3.3 LVTTL receiver

3.3 LVTTL I/O buffer, with 8-mA drive, with slew rate control

3.3 LVTTL I/O buffer, with programmable 4-, 8-, or 12-mA

drive

ESD diode to V_DD33and

GND

6

7

1.8-V LVDS (DMD interface)

3.3-V I²C with 3-mA sink

8

9

USB-compatible (3.3 V)

10

OSC 3.3-V I/O compatible LVTTL

(TYPE)

I

Input

O

B

H

U

D

Output

Bidirectional

N/A

Hysteresis

Includes an internal termination pullup resistor

Includes an internal termination pulldown resistor

(1) Refer to I/O Type and Subscript Definition (表5-15).

(2) Refer to the 节8.2.2 and the 节8.2.1 for a description between a one controller and a two controller

configuration.

(3) Refer to the 节10.1.7 for instructions on handling unused pins.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (see⁽¹⁾

)

MIN

–0.3

–0.5

–1

MAX

1.6

2.5

3.9

1.6

2.5

1.4

5.25

UNIT

VDDC (core)

VDD18 (LVDSAVD I/O and internal DRAMVDD)

VDD33 (I/O)

PLLD_VDD (1.15 V DMD clock generator –digital)

PLLM1_VDD (1.15 V primary-LS clock generator –digital)

PLLM2_VDD (1.15 V primary-HS clock generator –digital)

PLLD_VAD (1.8 V DMD clock generator –analog)

PLLM1_VAD (1.8 V primary-LS clock generator –analog)

PLLM2_VAD (1.8 V primary-HS clock generator –analog)

PLLS_VAD (1.15 V video-2X –analog)

USB

Supply voltage ^{(2) (3)}

V

OSC

VDD33 +

0.3 V

–0.3

V_I

Input voltage ⁽⁴⁾

Output voltage

V

3.3 LVTTL

3.3 I²C

3.6

3.8

5.25

2.2

3.6

3.8

–0.3

–0.5

–1

USB

1.8 LVDS

3.3 LVTTL

3.3 I²C

–0.3

–0.5

V_O

T_J

Operating junction

temperature

0

111

125

°C

T_stg

Storage temperature

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.

Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

(2) All voltage values are with respect to GND.

(3) All of the 3.3-V, 1.8-V, and 1.15-V power must be applied and removed per the procedure defined in 节9.3. Overlap currents, if allowed

to continue flowing unchecked not only increase total power dissipation in a circuit, but degrade the circuit reliability, thus shortening its

usual operating life.

(4) Applies to external input and bidirectional buffers.

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6.2 ESD Ratings

VALUE UNIT

V_(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins ⁽¹⁾

DLPC900

±2000

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins ⁽²⁾

±300

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins ^{(1) (4)}

DLPC900A

±1000

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins ^{(2) (3)}

+500 /

-300

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) CDM passes to -500-V on all digital pins, however the PLL pins pass only to -300V, failing at -350-V.

(4) HBM includes power supply combinations only. Non-supply pin to non-supply pin combinations not performed in accordance with

qualification plan.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this

data sheet is achieved when operating the device by the Recommended Operating Conditions. No level of performance is

implied when operating the device above or below the Recommended Operating Conditions limits.

I/O ⁽¹⁾

MIN

NOM

MAX UNIT

V_DD33

V_DD18

3.3 V supply voltage, I/O

3.135

3.3

3.465

1.8 V supply voltage, LVDSAVD and

DRAMVDD

1.71

1.8

1.89

VDDC

1.15 V supply voltage, Core logic

1.8 V supply voltage, PLL analog

1.15 V supply voltage, PLL analog

1.15 V supply voltage, PLL digital

1.100

1.15

1.8

1.200

1.89

PLLD_V_DD

PLLM1_V_DD

PLLM2_V_DD

PLLS_V_DD

PLLD_V_DD

PLLM1_V_DD

PLLM2_V_DD

1.71

1.8

1.89

V

1.71

1.8

1.090

1.15

1.200

VDD33

VDD18

55

1.090

USB (9)

0

OSC (10)

V_I

Input voltage

V

3.3 V LVTTL (1, 2, 3, 4)

3.3 V I²C (8)

USB (8)

3.3 V LVTTL (1, 2, 3, 4)

3.3 V I²C (8)

V_O

Output voltage

1.8 V LVDS (7)

See ⁽²⁾and ⁽³⁾

T_A

T_C

T_J

Operating ambient temperature range

Operating top-center case temperature

Operating junction temperature

°C

See ⁽³⁾and ⁽⁴⁾

109.16

111

(1) The number inside the parentheses for the I/O refers to the I/O type defined in 表5-15.

(2) Assumes minimum 1 m/s airflow.

(3) Maximum thermal values assume max power of 4.76 W (total for controller).

(4) Assume φ_JTequals 0.4°C/W.

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6.4 Thermal Information

DLPC900

THERMAL METRIC

ZPC (BGA)

516 PINS

4.4

UNIT

(1)

R_θJC

Junction-to-case thermal resistance

°C/W

R

_θJAat 0 m/s of forced airflow ⁽²⁾Junction-to-air thermal resistance

14.4

_θJAat 1 m/s of forced airflow ⁽²⁾Junction-to-air thermal resistance

9.5

_θJAat 2 m/s of forced airflow ⁽²⁾Junction-to-air thermal resistance

9.0

(3)

Temperature variance from junction to package top center

temperature, per unit power dissipation

φ_JT

0.4

°C/W

(1)

R

_θJCanalysis assumptions: The heat generated in the chip flows into overmold (top side) and also into the package laminate (bottom

side) and then into PCB via package solder balls. Used for heat sink analysis only.

(2) Thermal coefficients abide by JEDEC Standard 51. R_θJAis the thermal resistance of the package as measured using a JEDEC

defined standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC900 PCB and thus the reported thermal

resistance can be inaccurate in the actual product application. Although the actual thermal resistance can be different, it is the best

information available during the design phase to estimate thermal performance.

(3) Example: (3.2 W) × (0.4 C/W) ≈1.28°C temperature rise.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS ⁽⁴⁾

MIN

2

TYP

MAX UNIT

USB (9)

OSC (10)

2

High-level input

threshold voltage

V_IH

V

3.3-V LVTTL (1, 2, 3, 4)

3.3-V I²C (8)

2

2.4

VDD33 + 0.5

USB (9)

0.8

1

OSC (10)

Low-level input

threshold voltage

V_IL

V

3.3-V LVTTL (1, 2, 3, 4)

3.3-V I²C (8)

–0.5

Differential input

sensitivity

(Differential input

voltage)

V_DIS

V_ICM

V_OH

USB (9)

200

mV

V

Input common mode

range

(Differential cross

point voltage)

0.8

2.5

USB (9)

2.8

1.52

2.7

0

High-level output

voltage

1.8-V LVDS (7)

3.3-V LVTTL (1, 2, 3)

USB (9)

V

I_OH= Max rated

0.3

0.88

0.4

1.8-V LVDS (7)

3.3-V LVTTL (1, 2, 3)

3.3-V I²C (8)

Low-level output

voltage

V_OL

V

I_OL= Max rated

I_OL= 3-mA sink

0.4

Output differential

voltage

V_OD

1.8-V LVDS (7)

0.065

0.44

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS ⁽⁴⁾

MIN

TYP

MAX UNIT

USB (9)

200

10

OSC (10)

–10

3.3-V LVTTL (1 to 4)

(without internal pulldown)

High-level input

current

V_IH= VDD33

10

I_IH

µA

3.3-V LVTTL (1 to 4) (with

internal pulldown)

V_IH= VDD33

10

200

3.3-V I²C (8)

10

USB (9)

–10

OSC (10)

3.3-V LVTTL (1-4) (without

internal pullup)

V_OH= VDD33

10

–10

I_IL

Low-level input current

µA

3.3-V LVTTL (1-4) (with

internal pullup)

V_OH= VDD33

–200

–10

3.3-V I²C (8)

USB (9)

–18.4

–6.5

1.8-V LVDS (7)

(V_OD= 300 mV)

VO = 1.4 V

High-level output

current ⁽²⁾

I_OH

mA

3.3-V LVTTL (1)

3.3-V LVTTL (2)

3.3-V LVTTL (3)

USB (9)

VO = 2.4 V

–4

–8

–12

19.1

1.8-V LVDS (7)

(V_OD= 300 mV)

VO = 1 V

6.5

Low-level output

current ⁽³⁾

3.3-V LVTTL (1)

3.3-V LVTTL (2)

3.3-V LVTTL (3)

3.3-V I²C (8)

USB (9)

VO = 0.4 V

4

8

I_OL

mA

12

3

10

–10

11.84

3.75

5.26

LVDS (7)

10

µA

10

High-impedance

leakage current

I_OZ

3.3-V LVTTL (1, 2, 3)

3.3-V I²C (8)

USB (9)

10

17.07

5.52

3.3-V LVTTL (1)

3.3-V LVTTL (2)

3.3-V LVTTL (4)

3.3-V I²C (8)

Input capacitance

(including package)

C_I

5.52

6.54

pF

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER ⁽¹⁾

TEST CONDITIONS ⁽⁴⁾

MIN

TYP

MAX UNIT

I_CC11

I_CC18

Supply voltage, 1.15-V core power

Normal mode

2368

1005

mA

Supply voltage, 1.8-V power (LVDS I/O and

internal DRAM)

I_CC33

Supply voltage, 3.3-V I/O power

Normal mode

33

mA

I_{CC11_PLLD}

Supply voltage, DMD PLL digital power (1.15 V)

4.4

6.2

Supply voltage, primary-LS clock generator PLL

digital power (1.15 V)

I_{CC11_PLLM1}

Normal mode

6.2

mA

Supply voltage, primary-HS clock generator PLL

digital power (1.15 V)

I_{CC11_PLLM2}

I_{CC18_PLLD}

I_{CC18_PLLM1}

Normal mode

4.4

8

6.2

10.2

mA

Supply voltage, DMD PLL analog power (1.8 V)

Supply voltage, primary-LS clock generator PLL

analog power (1.8 V)

8

Supply voltage, primary-HS clock generator PLL

analog power (1.8 V)

I_{CC18_PLLM2}

I_{CC11_PLLS}

Normal mode

8

10.2

mA

Supply voltage, video-2X PLL analog power

(1.15 V)

2.9

mA

W

Total Power in Normal Mode

4.76

(1) The number inside the parentheses for the I/O refers to the I/O type defined in 表5-15.

(2) VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT –VDDQ) / I_OHmust be < 21 Ωfor values of VOUT between VDDQ and VDDQ –280 mV.

(3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / I_OLmust be < 21 Ωfor values of VOUT between 0 V and 280 mV.

(4) Normal mode refers to DLPC900 operation during full functionality. Typical values correspond to power dissipated on nominal process

devices operating at nominal voltage and 70°C junction temperature (approximately 25°C ambient) displaying typical video-graphics

content from a high-frequency source. Max values correspond to power dissipated on fast-process devices operating at high voltage

and 105°C junction temperature (approximately 55°C ambient) displaying typical video-graphics content from a high-frequency source.

The increased power dissipation observed on fast-process devices operated at max recommended temperature is primarily a result of

increased leakage current.

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6.6 System Oscillators Timing Requirements ⁽¹⁾

MIN

MAX

UNIT

Clock frequency, MOSC1

ƒ_clock

19.998

100

20.002

100

MHz

ppm

Stability and Tolerance. Crystal frequency 20 MHz. ⁽²⁾

t_c

Cycle time, MOSC1

49.995

20

50.005

ns

50% to 50% reference points

(signal)

t_w(H)

Pulse duration2, MOSC, high

50% to 50% reference points

(signal)

t_w(L)

t_t

Pulse duration2, MOSC, low

20

ns

20% to 80% reference points

(signal)

Transition time2, MOSC, t_t= t_ƒ/ t_r

Period jitter2, MOSC

12

18

t_jp

ps

(The deviation in period from ideal period due solely to high-frequency jitter –not spread

spectrum clocking)

(1) Applies only when driven through an external digital oscillator. The MOSC input cannot support spread spectrum clock spreading.

(2) Including impact to accuracy due to aging, temperature, and trim sensitivity.

t

C

t

T

t

T

t

W(L)

W(H)

80%

20%

50%

MOSC

图6-1. System Oscillators

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6.7 Power-Up and Power-Down Timing Requirements

All DMDs supported by the DLPC900 controller require Firmware Version 4.0.0 or later.

表6-1. Power-Up and Power-Down Timing Requirements

MIN

MAX UNIT

t_w1(L)

Pulse duration, inactive low, PWRGOOD 50% to 50% reference points (signal)

Pulse duration with 1.8 V on, inactive

4

µs

1000

ms

low, PWRGOOD

t_w1(L)

50% to 50% reference points (signal)

Pulse duration with 1.8 V off, inactive

indefinite

low, PWRGOOD

t_t1

Transition time, PWRGOOD, t_t1= t_ƒ/t_r

20% to 80% reference points (signal)

625

µs

t_w2(L)

Pulse duration, inactive low, POSENSE 50% to 50% reference points (signal)

Pulse duration with 1.8 V on, inactive

500

1000

ms

low, POSENSE

t_w2(L)

50% to 50% reference points (signal)

Pulse duration with 1.8 V off, inactive

indefinite

low, POSENSE

t_t2

Transition time, POSENSE, t_t2= t_ƒ/t_r

20% to 80% reference points (signal)

25 ⁽¹⁾

µs

ms

µs

Power hold time, POSENSE remains

active after PWGOOD is deasserted.

t_PH

t_ePH

t_EW

500

20

Extended power hold time for revision "B" and later DMDs.

Early warning time, PWRGOOD goes inactive low before any power supply voltage

goes below its specification

500

The sum of PWRGOOD and POSENSE inactive time with 1.8 V on

The sum of PWRGOOD and POSENSE inactive time with 1.8 V off

1050

ms

t_w1(L)+ t_w2(L)

indefinite

(1) As long as noise on this signal is below the hysteresis threshold.

6.7.1 Power-Up

POSENSE and PWRGOOD are active high signals that are generated by an external voltage monitor circuit.

POSENSE must only be driven active high when all the controller and DMD supply voltages have reached 90%

of their specified minimum voltage. The DLPC900 is safe to exit its RESET state once PWRGOOD is driven

high. PWRGOOD has no impact on operation for 60 ms after rising edge of POSENSE.

t_t1

80%

50%

20%

80%

50%

20%

80%

50%

20%

PWRGOOD

t_t1

t_w1(L)

80%

50%

20%

POSENSE

t_t2

DC Power Supplies

图6-2. Power Up Timing Diagram

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6.7.2 Power-Down

PWRGOOD cannot be used as an early warning signal. DMDs require an enhanced power down where the

DLPC900 performs a sequence of memory loads to the DMD followed by the mirror park instruction so that the

mirrors end up in an un-landed state.

There are two scenarios to consider when powering down DMDs supported by the DLPC900. 图 6-3 shows a

power distribution layout for a typical system, which provides the mechanisms for both scenarios.

The first scenario is an anticipated power down, which is during a typical power down of the system. Anticipated

Power Down Timing Diagram shows a timing diagram where an external host sends a power down command to

the microprocessor (µP). The µP must send a Power Standby command to the DLPC900. The DLPC900

then performs the necessary power down sequence on the DMD. The power can be safely removed once the

minimum t_ePHis met.

The second scenario is an unanticipated power loss. In this case a power loss detection circuit must provide a

means of triggering a power loss. 图6-5 shows a timing diagram where the power loss detection circuit detects a

power loss and asserts PWRLOSS to the µP. The µP must send a Power Standby command to the

DLPC900. The DLPC900 then performs the necessary power down sequence on the DMD. The power supplies

can be allowed to drop below their specifications once the minimum t_ePHis met.

Refer to the DLPC900 Programmer's Guide for a description of the Power Standby command.

图6-3. Power Distribution Layout Example

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图6-4. Anticipated Power Down Timing Diagram

图6-5. Unanticipated Power Loss Timing Diagram

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6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements

MIN

MAX

UNIT

MHz

ns

Clock frequency, TCK

10

5

ƒ_clock

t_c

Cycle time, TCK

100

40

t_w(H)

t_w(L)

t_t

Pulse duration, high

50% to 50% reference points (signal)

20% to 80% reference points (signal)

ns

Pulse duration, low

40

ns

Transition time, t_t= t_f/ t_r

ns

t_su

t_h

t_su

t_h

8

2

8

2

ns

Setup time, TDI valid before TCK↑

Hold time, TDI valid after TCK↑

Setup time, TMS1 valid before TCK↑

Hold time, TMS1 valid after TCK↑

ns

6.9 JTAG Interface: I/O Boundary Scan Application Switching Characteristics

Switching characteristics over recommended operating conditions, C_L(min timing) = 5 pF, C_L(max timing) = 85 pF (unless

otherwise noted)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

MIN

MAX

UNIT

t_pd

Output propagation, clock to Q

TDO1

3

12

ns

TCK↑

t_t

t_c

t_w(H)

t_w(L)

TCK

(input)

80%

20%

50%

t_su

t_h

TDI

TMS1

(inputs)

Valid

t_pd(max)

TDO1

(outputs)

Valid

图6-6. I/O Boundary Scan

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6.10 Programmable Output Clocks Switching Characteristics

Switching characteristics over recommended operating conditions, C_L(min timing) = 5 pF, C_L(max timing) = 50 pF (unless

otherwise noted)

PARAMETER

Clock frequency, OCLKA ⁽¹⁾

Cycle time, OCLKA

FROM (INPUT)

TO (OUTPUT)

MIN

0.787

20.00

MAX

UNIT

MHz

ns

N/A

OCLKA

50.00

ƒ_clock

t_c

OCLKA

1270.6

Pulse duration, high ⁽²⁾

50% to 50% reference points (signal)

t_w(H)

t_w(L)

N/A

OCLKA

ns

(t_c/ 2) –2

Pulse duration, low ⁽²⁾

50% to 50% reference points (signal)

N/A

OCLKA

ns

ps

Jitter

350

(1) The frequency of OCLKA is programmable.

(2) The duty cycle of OCLKA will be within ±2 ns of 50%.

t

C

t

w(L)

w(H)

80%

50%

20%

OCLKA

图6-7. Programmable Output Clocks

6.11 Port 1 and 2 Input Pixel Interface Timing Requirements

MIN

MAX

UNIT

12

175

MHz

ƒ_clock

Clock frequency, P_CLK1, P_CLK2, P_CLK3 (24-bit bus 节7.3.5.6)

Clock frequency, P_CLK1, P_CLK2, P_CLK3 (48-bit bus 节7.3.5.6)

See 节6.12.

12

141

MHz

t_c

Cycle time, P_CLK1, P_CLK2, P_CLK3

5.714

2.3

83.33

ns

t_w(H)

t_w(L)

Pulse duration, high

Pulse duration, low

50% to 50% reference points (signal)

2.3

Clock period jitter P_CLK1, P_CLK2, P_CLK3

(that is, the deviation in period from ideal

period)

t_jp

Max f_clock

See ⁽¹⁾

2.0

ps

ns

Transition time, t_t= t_f/ t_r, P_CLK1, P_CLK2,

P_CLK3

t_t

20% to 80% reference points (signal)

0.6

Transition time, t_t= t_f/ t_r, P1_A(9:0), P1_B(9:0) ,

P1_C(9:0), P1_HSYNC, P1_VSYNC,

P1_DATEN

t_t

20% to 80% reference points (signal)

3.0

t_t

Transition time, t_t= t_f/ t_r

0.6

0.8

ns

t_su

t_h

Setup time, P1_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P1_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P1_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P1_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P1_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P1_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P1_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P1_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P1_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P1_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.

t_su

t_h

t_su

t_h

t_su

t_h

t_su

t_h

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MIN

0.8

1

MAX

UNIT

t_su

t_h

Setup time, P2_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P2_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P2_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P2_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P2_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P2_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P2_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P2_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P2_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P2_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P_DATEN1, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P_DATEN1, valid after P_CLK1, P_CLK2, or P_CLK3.

Setup time, P_DATEN2, valid before P_CLK1, P_CLK2, or P_CLK3.

Hold time, P_DATEN2, valid after P_CLK1, P_CLK2, or P_CLK3.

VSYNC active pulse duration

ns

t_su

t_h

ns

t_su

t_h

ns

t_su

t_h

ns

t_su

t_h

ns

t_su

t_h

ns

t_su

t_h

ns

t_w(A)

Video line

Pixel

clocks

t_w(A)

HSYNC active pulse duration

16

(1) For frequencies (ƒ_clock) less than 175 MHz, use the following formula to obtain the jitter: Max clock jitter = ± [(1 / ƒ_clock) –5414 ps].

t_t

t_c

t_w(H)

t_w(L)

P_CLKx or

Px_CLK

(input)

80%

20%

50%

t_su

t_h

Px_Data and

Px_Control

(inputs)

Valid

图6-8. Input Port 1 and 2 Interface

6.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements

When operating in two pixels per clock mode, the pixel clock must be maintained below 141 MHz. A typical video source

requiring two pixels per clock is shown in the following table and must have reduced blanking to stay below the maximum

pixel clock.

PIXEL CLOCK ACHIEVED

SOURCE

RATE (Hz)

TOTAL PIXELS PER LINE ⁽¹⁾

TOTAL LINES PER FRAME ⁽¹⁾

(MHz)

1080p

120

2060

1120

138.4

(1) Values chosen for front and back porches must meet the timing requirements in 节6.16.

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6.13 SSP Switching Characteristics

Switching characteristics over recommended operating conditions, C_L(min timing) = 5 pF, C_L(max timing) = 50 pF (unless

otherwise noted)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

MIN

73.00

0.040

MAX

25000

13.6

UNIT

kHz

µs

Clock frequency, SSPx_CLK

Cycle time, SSPx_CLK

N/A

SSPx_CLK

ƒ_clock

t_c

N/A

SSPx_CLK

Pulse duration, high

50% to 50% reference points (signal)

t_w(H)

40%

Pulse duration, low

50% to 50% reference points (signal)

t_w(L)

N/A

SSPx_CLK

SSP MASTER

SSPx_DO ^{(1) (2)}

SSPx_DO ^{(1) (3)}

5

ns

SSPx_CLK↓^{(1) (2)}

SSPx_CLK↑^{(1) (3)}

–5

Output propagation, clock to Q,

SSPx_DO

t_pd

SSP SLAVE

SSPx_DO ^{(1) (2)}

SSPx_DO ^{(1) (3)}

0

34

ns

SSPx_CLK↓^{(1) (2)}

SSPx_CLK↑^{(1) (3)}

Output propagation, clock to Q,

SSPx_DO

t_pd

(1) The SSP is configured into four different modes of operation by the controller firmware. These modes are shown in 表6-2, 图6-10,

and 图6-11.

(2) Modes 0 and 3

(3) Modes 1 and 2

表6-2. SSP Clock Operational Modes

SPI CLOCKING

MODE

SPI CLOCK

POLARITY (CPOL)

SPI CLOCK PHASE

(CPHA)

0

1

2

3

0

1

0

1

0

1

CSZ

CLK

(CPOL = 0)

(CPOL = 1)

(CPHA = 0)

(CPHA = 1)

MSB

LSB

DI/DO

LSB

图6-9. SSP Clock Mode Timing Diagram

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t_t

t_c

t_w(H)

t_w(L)

SSPx_CLK

(ASIC output)

80%

20%

50%

t_pd(min)

t_pd(max)

SSPx_DO

(ASIC output)

Valid

t_su

t_h

SSPx_DI

(ASIC input)

Valid

SSPx_CSZ

图6-10. Synchronous Serial Port Interface –Master (Modes 0/3)

t_t

t_c

t_w(H)

t_w(L)

SSPx_CLK

(ASIC output)

80%

20%

50%

t_pd(min)

t_pd(max)

SSPx_DO

(ASIC output)

Valid

t_su

t_h

SSPx_DI

(ASIC input)

Valid

SSPx_CSZ

图6-11. Synchronous Serial Port Interface –Slave (Modes 0/3)

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6.14 DMD Interface Switching Characteristics ⁽¹⁾

over recommended operating conditions, C_L(min timing) = 5 pF, C_L(max timing) = 50 pF (unless otherwise noted)

PARAMETER

FROM

TO

MIN

MAX UNIT

DMD TIMING MODE 0 ⁽²⁾

t_w(H)

t_w(L)

DMD strobe high pulse duration

DMD strobe low pulse duration

N/A

DADSTRB

29

ns

Output data valid window,

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

with respect to DADSTRB

DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

DADSTRB↑

T_odv-min

ns

–27

(1)

Output data valid window,

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

with respect to DADSTRB

DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

DADSTRB↑

T_odv-max

27

(1)

DMD TIMING MODE 1 ⁽²⁾

t_w(H)

t_w(L)

DMD strobe pulse duration

N/A

DADSTRB

14

ns

DMD strobe low pulse duration

Output data valid window,

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

with respect to DADSTRB

DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

DADSTRB↑

T_odv-min

ns

–12

(1)

Output data valid window,

DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0)

with respect to DADSTRB

DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

DADSTRB↑

T_odv-max

12

(1)

(1) DMD control signals are captured on the rising edge of DADSTRB within the DMD.

(2) The DMD timing mode is controlled by the controller firmware.

DADADDR_(3:0)

DADMODE_(1:0)

DADSEL_(1:0)

t_odv-min

t_odv-max

DADSTRB

50%

t_w(H)

图6-12. DMD Interface Timing

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6.15 DMD LVDS Interface Switching Characteristics

Switching characteristics over recommended operating conditions ^{(1) (2) (3) (4) (5) (6)}

PARAMETER

Clock frequency, DCK_A

Cycle time, DCK_A1

FROM (INPUT)

TO (OUTPUT)

MIN

100

N/A

DCK_A

400

MHz

ps

ƒ_clock

t_c

DCK_A

2475.3

1093

t_w(H)

Pulse duration, high 5 (50% to 50% reference

points)

DCK_A

ps

t_w(L)

t_t

Pulse duration, low 5 (50% to 50% reference

points)

N/A

DCK_A

1093

100

ps

Transition time, t_t= t_ƒ/ t_r(20% to 80% reference

points)

400

t_osu

t_oh

ƒ_clock

t_c

Output setup time at max clock rate3

Output hold time at max clock rate3

Clock frequency, DCK_B

SCA, DDA(15:0)

DCK_B

438

ps

DCK_A↑↓

N/A

100

MHz

ps

Cycle time, DCK_B1

N/A

DCK_B

2475.3

1093

t_w(H)

Pulse duration, high 5 (50% to 50% reference

points)

N/A

DCK_B

ps

t_w(L)

t_t

Pulse duration, low 5 (50% to 50% reference

points)

N/A

DCK_B

1093

100

ps

Transition time, t_t= t_ƒ/ t_r(20% to 80% reference

points)

400

250

t_osu

t_oh

t_sk

Output setup time at max clock rate3

Output hold time at max clock rate3

Output skew, channel A to channel B

SCB, DDB(15:0)

DCK_B↑

438

ps

DCK_B↑↓

DCK_A↑

(1) The minimum cycle time (t_c) for DCK_A and DCK_B includes 1.0% spread spectrum modulation.

(2) The DMD LVDS interface uses a double data rate (DDR) clock, thus both rising and falling edges of DCK_A and DCK_B are used to

clock data into the DMD. As a result, the minimum t_w(H)and t_w(L)parameters determine the worse-case DDR clock cycle time.

(3) Output setup and hold times for DMD clock frequencies below the maximum can be calculated as follows:

t_osu(ƒ_clock) = t_osu(ƒ_max) + 250000 × (1 / ƒ_clock–1 / 400) and t_oh(ƒ_clock) = t_oh(ƒ_max) + 250000 × (1 / ƒ_clock–1 / 400) where ƒ_clockis in

MHz.

(4) The DLPC900 is a Full-Bus DMD signaling interface. 图7-4 shows the controller connections for this configuration.

(5) The pulse duration minimum for any clock rate can be calculated using the following formulas.

a. Pulse duration minimum when using spread spectrum

i.

Duty cycle % = 49.06 –[0.01335 × clock frequency (MHz)]

ii. Minimum pulse duration = 1 / clock frequency × DC%

1. Example: At 400 MHz: DC% = 49.06 –[0.01335 × 400] = 43.72%

2. MPW = 1 / 400 MHz × 0.4372 = 1093.0 ps

b. Pulse duration minimum when not using spread spectrum

i.

Duty cycle % = 49.00 –[0.01055 × clock frequency (MHz)]

ii. Minimum pulse duration = 1 / clock frequency × DC%

1. Example: At 400 MHz: DC% = 49.00 –[0.01055 × 400] = 44.78%

2. MPW = 1 / 400 MHz × 0.448 = 1119.5 ps

(6) A duty cycle specification is not provided because the key limiting factor to clock frequency is the minimum pulse duration (that is, if the

other half of the clock period is larger than the minimum, it is not limiting the clock frequency).

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t_t

t_c

t_w(H)

t_w(L)

DCKA

DCKB

(output)

80%

50%

20%

t_su

t_h

t_su

t_h

SCA, DDA(15:0)

SCB, DDB(15:0)

(outputs)

Valid

图6-13. DMD LVDS Interface

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6.16 Source Input Blanking Requirements

PORT

PARAMETER ⁽¹⁾

MINIMUM BLANKING

VBP

370 µs

1 Line

Port 1 Vertical Blanking

Port 2 Vertical Blanking

VFP

Total vertical blanking

370 µs + 2 lines

370 µs

VBP

VFP

Total vertical blanking

HBP

1 line

370 µs + 2 lines

10 pixels

0 pixels

Port 1 and 2 Horizontal Blanking

HFP

Total horizontal blanking

80 pixels

(1) Refer to 节11.1.3.

TPPL

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

ALPF

(HBP)

(HFP)

Vertical Front Porch (VFP)

图6-14. Video Timing Parameters

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7 Detailed Description

7.1 Overview

The DLPC900 controller processes the digital input image and converts the data into the digital format needed

by the DLP500YX, DLP670S, DLP9000, or the DLP6500. The DLP500YX, DLP670S, DLP9000, and the

DLP6500 reflect light by using binary pulse-width-modulation (PWM) for each micromirror. For further details,

refer to the DLP500YX, DLP670S, DLP9000, or the DLP6500 data sheets.

The DLPC900 combined with a DLP6500 supports a wide variety of resolutions from SVGA to 1080p. When

accurate pattern display is needed, a native 1080p resolution source is used for a one-to-one association with

the corresponding micromirror on the DLP6500.

Two DLPC900 controllers combined with a DLP500YX, DLP670S, or DLP9000 supports only native resolution

for a one-to-one association with the corresponding micromirror on the DMD. All combinations are well-suited for

structured light, additive manufacturing, or digital exposure applications.

7.2 Functional Block Diagram

图7-1. Functional Block Diagram

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7.3 Feature Description

The DLPC900 controller takes as input 16-, 20-, or 24-bit RGB data at up to 120-Hz frame rate. For example, a

120-Hz 24-bit frame is composed of three colors (red, green, and blue) with each color equally divided in the

120-Hz frame rate. Thus, each color has a 2.78-ms time slot allocated. Because each color has an 8-bit depth,

each color time slot is further divided into bit-planes. A bit-plane is the 2-dimensional arrangement of one-bit

extracted from all the pixels in the full color 2D image to implement dynamic depth (see 图7-2).

图7-2. Bit Slices

The length of each bit-plane in the time slot is weighted by the corresponding power of two of its binary

representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has

three colors (R, G, & B) with 8-bit depth each. Each color time slot is then divided into eight bit-planes, with the

sum of the weight of all bit planes in the time slot equal to 256. 图 7-3 illustrates the time partition of the bits in

one 8-bit color time slot within a 24-bit RGB frame.

图7-3. 24-Bit RGB Frame Bit Partition

Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on

or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With binary pulse-

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width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on.

For a 24-bit RGB frame image inputted to the DLPC900 controller, the DLPC900 controller creates 24 bit-planes,

stores them in internal embedded DRAM, and sends them to the DMD, one bit-plane at a time. The bit weight

controls the amount of time the mirror is on. To improve image quality in video frames, these bit-planes, time

slots, and color frames are shuffled and interleaved within the pixel processing functions of the DLPC900

controller.

7.3.1 DMD Configurations

图 7-4 shows the controller connections for full-bus normal or swapped. Refer to the Firmware section of the

DLP® LightCrafter™ Single DLPC900 Evaluation Module (EVM) User's Guide (DLPU101) or DLP® LightCrafter

™ Dual DLPC900 Evaluation Module (EVM) User's Guide (DLPU102) for details on how to select the bus swap

settings to match the board layout connections.

DLPC900

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

15

14

13

12

11

10

9

8

7

6

Full-Bus

A Port Normal

Full-Bus

A Port Swapped

9

10

11

12

13

14

15

10

11

12

13

14

15

10

11

12

13

14

15

5

4

3

2

1

0

图7-4. Controller to DMD Full-Bus Connections

7.3.2 Video Timing Input Blanking Specification

The DLPC900 controller requires a minimum horizontal and vertical blanking for both Port 1 and Port 2 as shown

in 节 6.16. These parameters indicate the time allocated to retrace the signal at the end of each line and field of

a display. Refer to 节11.1.3.

7.3.3 Board-Level Test Support

The In-Circuit Tri-State Enable signal (ICTSEN) is a board-level test control signal. By driving ICTSEN to a logic

high state, all controller outputs (except TDO1 and TDO2) will be configured as tri-state outputs.

The DLPC900 also provides JTAG boundary scan support on all I/O except non-digital I/O and a few special

signals. 表7-1 lists these exceptions.

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表7-1. DLPC900 –

Signals Not Covered by

JTAG ⁽¹⁾

SIGNAL NAME

PACKAGE

BALL

HW_TEST_EN

M25

MOSC

M26

N26

MOSCN

USB_DAT_N

USB_DAT_P

C5

D6

TCK

N24

N25

M23

N23

N22

P25

P26

TDI

TRSTZ

TDO1

TDO2

TMS1

TMS2

(1) There is no JTAG connection

to power or no-connect pins.

7.3.4 Two Controller Considerations

When two DLPC900 controllers drive a single DLP500YX, DLP670S, or DLP9000 DMD, each controller is used

to drive half of the DMD, as shown in Two Controllers Connected to DLP9000 DMD. Each controller must

operate in two pixels per clock, and the pixel clock must be maintained below the maximum two pixel per clock

frequency. Only native resolution is supported when two DLPC900 controllers are matched with a DLP500YX,

DLP670S, or DLP9000 DMD.

图7-5. Two Controllers Connected to DLP9000 DMD

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7.3.5 Memory Design Considerations

7.3.5.1 Flash Memory Optimization

The DLPC900 memory configuration can be optimized for different applications. The operating mode chosen

and the application implementation will determine how much optimization can be performed.

7.3.5.2 Operating Modes

The DLPC900 firmware offers four operating modes which can be selected when designing a product for a

particular application.

1. Video Mode: streamed over parallel RGB interface.

2. Video Pattern Mode: streamed over parallel RGB interface.

3. Pre-Stored Pattern Mode: patterns loaded from stored memory.

4. Pattern On-The-Fly Mode: patterns loaded over USB or I²C interface.

Depending on the application design requirements, the memory required for each operating mode can be

optimized for both performance and cost. This includes reducing the number of flash memory components,

which reduces PCB size and lowers overall product cost. In addition, having fewer components reduces the

power supply requirements hence lowering total power consumption.

7.3.5.3 DLPC900 Memory Space

The memory space of the DLPC900 consists of three chip-selects:

1. CS0

2. CS1 - Power-up boot chip select

3. CS2

The DLPC900 is capable of accessing up to 16-megabytes of memory on each chip-select for a total of 48-

megabytes. CS1 contains the firmware, and it is the power-up boot chip-select.

The memory space shown in 图 7-6 displays how the DLPC900 accesses the memory when memory is present

on all three chip selects. Although the chip-selects are numbered 0, 1, and 2, the way the DLPC900 accesses

the memory is not in this order. Notice that the boot flash is located on chip select CS1.

0xF9FFFFFF

0xFAFFFFFF

0xF8FFFFFF

0xF8F00000

RESERVED

Image

storage

Image

storage

Image

storage

Main Application

Bootloader

0xF9000000

0xFA000000

0xF8000000

Boot Flash

CS1

CS0

CS2

图7-6. DLPC900 Memory Space

During the power-up initialization, the DLPC900 firmware performs a query on each chip-select to determine

whether there is memory present. If there is no memory present on CS1, then the DLPC900 will not boot up.

Therefore, flash memory and the firmware must exist on CS1.

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Notice carefully that the addresses from CS2 to CS0 are not ascending linearly in 图 7-6. Therefore, an image

cannot span across CS2 and CS0. If an image cannot entirely fit in CS2, then the entire image must be moved

and stored in CS0.

If more memory space is required, the DLPC900 memory space can also be organized into a single flash

memory device larger than 48-megabytes. By using the architecture shown in 图 7-7, a flash memory device up

to 128-megabytes can be attached to the DLPC900. 表 7-2 describes the memory space layout of a 128-

megabyte flash device. Similar to memories attached directly to chip selects, an image also cannot span

across memory blocks when using a single large flash memory with the DLPC900.

图7-7. One 128-Megabyte Flash Device

表7-2. Flash Device Layout

Memory Block

Address Space (Start and End)

0xF9000000 - 0xF901FFFF

0xF9020000 - 0xF913FFFF

Single Flash Memory Addressed

0x00000000 - 0x0001FFFF

0x00020000 - 0x0013FFFF

Megabytes

0 - 0.128

Contents

Bootloader

0

0.128 - 1.15

Application binary,

Sequences / Patterns

0xF9140000 - 0xF923FFFF

0xF9240000 - 0xF9FFFFFF

0x00140000 - 0x0023FFFF

0x00240000 - 0x00FFFFFF

1.15 - 2.15

2.15 - 15

Reserved space

Patterns only

1

2

3

4

5

6

7

0xFA000000 - 0xFAFFFFFF

0xF8000000 - 0xF8FFFFFF

0x03000000 - 0x03FFFFFF

0x04000000 - 0x04FFFFFF

0x05000000 - 0x05FFFFFF

0x06000000 - 0x06FFFFFF

0x07000000 - 0x07FFFFFF

0x01000000 - 0x01FFFFFF

0x02000000 - 0x02FFFFFF

0x03000000 - 0x03FFFFFF

0x04000000 - 0x04FFFFFF

0x05000000 - 0x05FFFFFF

0x06000000 - 0x06FFFFFF

0x07000000 - 0x07FFFFFF

16 - 31

32 - 47

48 - 63

64 - 79

80 - 95

96 - 111

112 - 127

Patterns only

The design for a single 128-megabyte flash device for storing the firmware consists of the bootloader, the main

application, sequences/images stored in flash (optional), and 1-megabyte of reserved space. The bootloader is

located at the beginning of the flash memory block 0. The size of the bootloader is 128-kilobytes, beginning at

address 0xF9000000. The bootloader is necessary for operation. If the bootloader becomes corrupted in some

way it can render the device inoperable. The bootloader is followed by the main application and then sequence/

image data. As mentioned above, patterns must not span memory block boundaries. If a pattern does not fit

in a given block, the entire 24-bit image (or composite image) must be moved in the next block. Additionally, the

1-megabyte of reserved space in memory block 0 from 0xF9140000 to 0xF923FFFF is necessary for operation

and must not be overwritten.

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7.3.5.4 Minimizing Memory Space

Depending on the application design requirements of the product, the amount of memory can be reduced. This

can include reducing the number of flash memory components or the memory size of the flash memory

component.

As depicted in 图 7-8, the firmware resides in CS1, and the amount of memory the firmware occupies is usually

less than 128-kilobytes. With this in mind, the design engineer can conclude that memory is only required to be

present on CS1 if no images are needed for the design.

For example, if the application design only requires the DLPC900 to operate in Video Mode, then the flash

memory components on CS0 and CS2 are not required and can be left out. Moreover, since the firmware only

occupies about 128-kilobytes of memory, then a smaller density flash memory component can be used such as

a 4-megabyte rather than a 16-megabyte component. One 4-Megabyte Flash Memory shows the memory space

for this example.

图7-8. One 4-Megabyte Flash Memory

The same memory space shown in One 4-Megabyte Flash Memory also applies to Video Pattern Mode. In this

mode, the images are streamed from an external video source directly in to the internal memory of the

DLPC900. Another operating mode that can use this same memory configuration is Pattern On-The-Fly Mode

because the images are streamed over the USB or I²C interfaces directly into the internal memory of the

DLPC900. These three operating modes are excellent opportunities for minimizing the flash memory because

they don't require images to be stored in flash memory.

However, there exists one mode that can require additional memory because this mode requires images to be

stored in flash memory. When the DLPC900 is operating in Pre-Stored Pattern Mode, the DLPC900 reads all the

required images from flash memory into its internal memory when the pattern sequence is started. The amount

of flash memory depends on the needs of the application.

For example, if the application design requires only a few images, and the images and firmware can fit in one 4-

megabyte flash component, then the memory space in One 4-Megabyte Flash Memory can be used. However, if

more memory is needed, then one 8-megabyte or one 16-megabyte flash component can be used as shown in

One 8-Megabyte Flash Memory and One 16-Megabyte Flash Memory.

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图7-9. One 8-Megabyte Flash Memory

图7-10. One 16-Megabyte Flash Memory

When the memory requirement is greater than 16-megabytes but less than 32-megabytes, then two 16-

megabyte flash components can be used as shown in Two 16-Megabyte Flash Memory Components. Use CS1

and CS2 when using only two flash components.

图7-11. Two 16-Megabyte Flash Memory Components

When memory requirement exceeds 32-megabytes, use the flash memory space shown in 图 7-11 or use a

single large flash device as described in 节 7.3.5.5.2. Notice that in all examples, there is a 1-megabyte space

reserved at the end of the Firmware space. The default and maximum size of this reserved space is 1-megabyte;

however, depending on the operating mode, the reserved space is customizable and can be reduced by the

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design engineer when configuring the firmware. Whatever size is chosen, this reserved area must be taken into

consideration when calculating the required amount of memory.

7.3.5.5 Minimizing Board Size

Reducing the number of flash components saves valuable board area and reduces the cost of the PCB. There

are two additional ways to reduce cost: package selection and using larger density flash.

7.3.5.5.1 Package Selection

The first way is to use a smaller package type for the flash memory. Most of the flash memory components that

can be used with the DLPC900 also come in alternate packages. For example, selecting a BGA package can be

more than 50% smaller compared to a TSOP package.

7.3.5.5.2 Large Density Flash

The second way is to use a larger density flash memory component to combine two or all three flash memory

components into one flash component. However, using this method requires some additional low cost external

logic gates to combine the chip-selects and create and invert signals for the extra address lines. The other

requirement is the flash memory component must contain uniform sectors where each sector is 128-

kilobytes in size.

7.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash

One use case is when the memory requirement for a design is greater than 16-megabytes but less than 32-

megabytes. In this case, rather than using two 16-megabyte flash components, use only one 32-megabyte

component. One 32-Megabyte Flash Component shows a block diagram describing how to combine CS1 and

CS2 with external logic gates, as well as the connections between the DLPC900 and the flash component.

图7-12. One 32-Megabyte Flash Component

7.3.5.5.2.1.1 Combining Three Chip-Selects with One 64-Megabyte Flash

Another use case is when the memory requirement exceeds 32-megabytes but is less than 64-megabytes. In

this case, a single flash device up to 64-megabytes can be used. 图7-13 shows a block diagram describing how

to combine CS0, CS1, CS2, and GPIO45 with external logic gates, as well as the connections between the

DLPC900 and the flash component.

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图7-13. One 64-Megabyte Flash Component

7.3.5.5.2.2 Combining Three Chip-Selects with One 128-Megabyte Flash

The other use case is when the memory requirement exceeds 64-megabytes. In this case, a single flash device

up to 128-megabytes can be used. 图7-14 shows a block diagram describing how to combine CS0, CS1, CS2,

GPIO45, and GPIO46 with the required external logic gates and the connections between the DLPC900 and the

flash component.

图7-14. One 128-Megabyte Flash Component

Note

Flash devices that are larger than 128-megabytes can also be used with the DLPC900, but the

DLPC900 is only capable of accessing 128-megabytes. The other sectors within the flash device will

go unused.

Note

GPIO45, GPIO46, and GPIO60 are exclusively used by the DLPC900 as extended flash address

lines. These GPIO are not to be utilized for any other purpose.

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7.3.5.6 Minimizing Board Space

图7-15 shows how to minimize board space by selecting the next larger density of flash memory. For example, if

two 4-megabyte flash components are needed, then selecting one 8-megabyte flash component can be

considered. This will save board space because only one component takes up space on the board rather than

two components.

图7-15. Selecting Next Larger Density for Board Space Savings

When calculating the appropriate amount of memory to use, do not mix densities to come up with the exact

amount of memory that is calculated. Always use the same densities of flash memory even if it exceeds the

amount of memory that is calculated.

7.3.5.7 Flash Memory

Flash changes will require a change to the flash parameters file. This file must be changed to match the flash

device info for the selected device including the sector mapping of the device.

The following is a list of flash memory that was used and tested on the DLP^®LightCrafter^™Single DLPC900

Evaluation Module and DLP^®LightCrafter^™Dual DLPC900 Evaluation Module. The reader can consult the

datasheet for alternate package types that exist for each of the components listed. There are other flash

memories that can be substituted, and the reader must consult the datasheets to ensure compatibility.

Micron

MT28EW256ABA1LJS¹

MT28EW512ABA1LJS¹

MT28FW02GBBA1HPC¹

Cypress

S29GL032N90TFI010

S29GL064N90TFI010

S70GL02GS12FHIV10¹

¹These flash components must have uniform sectors, where each sector is 128-kilobytes in size

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7.4 Device Functional Modes

7.4.1 Structured Light Application

For structured light applications, the DLPC900 can be commanded to enter the following high speed sequential

pattern modes.

1. Video Pattern Mode

2. Pre-Stored Pattern Mode

3. Pattern On-The-Fly Mode

In each mode a specific set of patterns are selected with a maximum of 24 bits per pixel. The bit-depth of the

patterns are then allocated into the corresponding time slots. Furthermore, an output trigger signal is also

synchronized with these time slots to indicate when the image is displayed.

These pattern modes provide the capability to display a set of patterns and signal a camera to capture these

patterns overlaid on an object. The DLPC900 controller is capable of pre-loading up to 400 1-bit binary patterns

into internal memory from the external flash memory or from the USB or I²C interfaces. These pre-loaded binary

patterns are then streamed to the DMD at high speed.

Note

The DLPC900 internal DRAM is capable of holding 400 1-bit images. However, when using Pre-

Stored Pattern Mode the number of patterns that can be stored in External Flash depends on the size

of the external flash and level of compression achievable.

The DLPC900 controller is capable of synchronizing a camera to the displayed patterns. In video pattern mode,

the vertical sync is used as trigger input. In pre-stored pattern mode and pattern on-the-fly mode, an internal

user configurable trigger or a TRIG_IN_1 pulse indicates to the DLPC900 controller to advance to the next

pattern, while TRIG_IN_2 starts and stops the pattern sequence. In all pattern modes, TRIG_OUT_1 frames the

exposure time of the pattern, while TRIG_OUT_2 indicates the start of the pattern sequence.

图 7-16 shows an example timing diagram of video pattern mode. The VSYNC starts the pattern sequence

display. The pattern sequence consists of a series of four patterns followed by a series of three patterns and

then repeats. The first pattern sequence consists of P1, P2, P3, and P4. The second pattern sequence consists

of P5, P6, and P7. TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 indicates the start of each

pattern in the sequence. If the pattern sequence is configured without dark time between patterns, then the

TRIG_OUT_1 output would be high for the entire pattern sequence.

图7-16. Video Pattern Mode Timing Diagram

图 7-17 shows an example of a pre-stored pattern mode timing diagram. Pattern sequences of four are

displayed. TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 indicates the start of each pattern in

the sequence. If the pattern sequence is configured without dark time between patterns, then the TRIG_OUT_1

output would be high for the entire pattern sequence.

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图7-17. Pre-Stored Pattern Mode Timing Diagram

Another example of a pre-stored pattern mode timing diagram is shown in 图 7-18, where pattern sequences of

three are displayed. TRIG_OUT_1 frames each pattern displayed, while TRIG_OUT_2 indicates the start of each

pattern. TRIG_IN_2 serves as a start and stop signal. When high, the pattern sequence starts or continues.

Note, in the middle of displaying the P4 pattern, TRIG_IN_2 is low, so the sequence stops displaying P4. When

TRIG_IN_2 is raised, the pattern sequence continues where it stopped by re-displaying P4.

图7-18. Pre-Stored Pattern Mode Timing Diagram for 3-Patterns

表 7-3 shows the allowed pattern combinations in relation to the bit depth of the pattern. If the pattern sequence

is configured without dark time between patterns, then the TRIG_OUT_1 output would be high for the entire

pattern sequence. For faster 8-bit pattern speeds, the illumination source can be modulated to shorten the

smallest bits, and thus the larger bits. This method will introduce dark time into the pattern and affect the

brightness, but it is capable of 8-bit pattern speeds up to four times faster than patterns without illumination

modulation. More information on illumination modulation can be found in the DLP® LightCrafter™ Single

DLPC900 Evaluation Module (EVM) User's Guide (DLPU101) or DLP® LightCrafter™ Dual DLPC900 Evaluation

Module (EVM) User's Guide (DLPU102).

表7-3. Minimum Exposure in Any Pattern Mode

DLP6500

(µs)

DLP9000

(µs)

DLP500YX

(µs)

DLP670S

(µs)

BIT DEPTH

1

2

105

304

105

304

62

184

269

458

682

807

1083

2263

496

105

343

3

394

380

438

4

823

733

768

5

1215

1487

1998

4046

969

1215

1487

1998

4046

969

1299

1488

2000

4046

969

6

7

8

8⁽¹⁾

(1) Minimum achievable exposure using illumination modulated

light source.

表7-4 shows the minimum pattern exposure time for a 1-bit pattern in relation to the number of active DMD

blocks.

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表7-4. Minimum Exposures for Number of Active

DMD Blocks

ACTIVE

BLOCKS

DLP6500

(µs)

DLP9000

(µs)

DLP500YX

(µs)

DLP670S

(µs)

1

2

24

45

24

42

45

51

56

61

67

72

77

83

88

93

99

105

30

27

33

38

49

55

61

66

72

77

83

89

94

100

3

45

30

4

45

30

5

48

34

6

54

38

7

60

42

8

66

46

9

72

50

10

11

12

13

14

15

16

78

54

84

58

90

62

96

N/A

101

105

N/A

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DLPC900 controller is required to be coupled with the DLP6500, DLP9000, DLP500YX, or DLP670S DMDs

to provide a reliable display solution for video display and structure light applications. The DLPC900 converts the

digital input data into the digital format needed by the DLP6500, DLP9000, DLP500YX, or DLP670S DMDs. The

DMDs consist of an array of micromirrors which reflect incoming light to one of two directions by using binary

pulse-width-modulation (PWM) for each micromirror, where the primary direction being into a projection or

collection optics. Applications of interest include 3D machine vision, 3D printing, direct imaging lithography, and

intelligent lighting.

8.2 Typical Applications

8.2.1 Typical Two Controller Chipset

A typical embedded system application using the DLPC900 controller and DLP9000, DLP500YX, or DLP670S

DMD is shown in 图 8-1. This configuration requires two DLPC900 controllers to drive a DLP9000, DLP500YX,

or DLP670S DMD and supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or

processor. In this configuration, the 24-bit parallel RGB input data is split between the primary and the secondary

controller as described in 节7.3.4 using an FPGA or some other mechanism.

This system supports both still and motion video sources with the input resolution native to the DLP9000,

DLP500YX, or DLP670S DMD. However, the controller supports only sources with periodic synchronization

pulses. This support is ideal for motion video sources, but can also be used for still images by maintaining

periodic syncs and sending a new frame of data only when needed. The still image must be fully contained

within a single video frame and meet the frame timing constraints. The DLPC900 controller refreshes the

displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame

has been received.

This configuration also supports the high-speed sequential pattern modes mentioned in the 节 7.4.1. The

patterns can be from the video source, from the USB or I²C interface, or pre-stored in external flash, and have a

maximum of 24 bits per pixel. The patterns are pre-loaded into the internal embedded DRAM and then streamed

to the DLP9000, DLP500YX, or DLP670S DMD at high speeds.

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图8-1. Typical Application Schematic for DLP9000, DLP500YX, or DLP670S

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8.2.1.1 Design Requirements

All applications require both the controller and DMD components for reliable operation. The system uses an

external parallel flash memory device loaded with the DLPC900 configuration and support firmware. The

external boot flash must contain a minimum of 2 sectors, where the first sector starts at address 0xF9000000

which is the power-up reset start address. The first 128-kilobytes is reserved for the bootloader image and must

be in its own sector and can be made up of several smaller contiguous sectors that add up to 128-kilobytes as

shown in 图8-2. The remaining sectors contains the rest of the firmware. The default wait-states is set for a flash

device of 120-ns access time. For a faster flash access time, refer to the 节8.2.1.2.1.4.2 on how to program new

wait-state values.

图8-2. Boot Flash Memory Layout

Note

The bootloader, the main application, and any images stored in flash (if present) are considered the

firmware.

The chipset has the following interfaces and support circuitry:

• DLPC900 System Interfaces

– Control Interfaces

– Trigger Interface

– Input Data Interfaces

– Illumination Interface

• DLPC900 Support Circuitry and Interfaces

– Reference Clock

– PLL

– Program Memory Flash Interface

• DMD Interface

– DLPC900 to DLP6500/DLP9000/DLP500YX/DLP670S Digital Data

– DLPC900 to DLP6500/DLP9000/DLP500YX/DLP670S Control and Clock Interface

– DLPC900 to DLP6500/DLP9000/DLP500YX/DLP670S Serial Communication Interface

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 DLPC900 System Interfaces

The DLPC900 chipset supports a 24-bit parallel RGB interface for image data transfers from another device and

a 24-bit interface for video data transfers. The system input requires proper generation of the PWRGOOD and

POSENSE inputs to ensure reliable operation. There are two primary output interfaces: illumination driver control

interface and sync outputs.

8.2.1.2.1.1 Control Interface

The DLPC900 chipset supports I²C or USB commands through the control interface. The control interface allows

another primary processor to send commands to the DLPC900 controller to query system status or perform real-

time operations, such as, LED driver current settings. The DLPC900 allows the user to set a different I²C slave

address for the host port. Refer to the DLPC900 Programmer's Guide to set a different I²C master and slave

addresses.

表8-1. Active Signals –I²C Interfaces

SIGNAL NAME

I2C2_SCL

DESCRIPTION

I²C clock. Bidirectional open-drain signal. I²C master clock to external devices.

I²C data. Bidirectional open-drain signal. I²C master to transfer data to external devices.

I²C clock. Bidirectional open-drain signal. I²C master clock to external devices.

I²C data. Bidirectional open-drain signal. I²C master to transfer data to external devices.

I²C clock. Bidirectional open-drain signal. I²C slave clock input from the external processor.

I2C2_SDA

I2C1_SCL

I2C1_SDA

I2C0_SCL ⁽¹⁾

I²C data. Bidirectional open-drain signal. I²C slave to accept commands or transfer data to and from the external

processor.

I2C0_SDA ⁽¹⁾

(1) This interface is the host port.

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8.2.1.2.1.2 Input Data Interfaces

The data interface has a Parallel RGB input port and has a nominal I/O voltage of 3.3 V. Maximum and minimum

input timing specifications for both components are provided in the Interface Timing Requirements. Each parallel

RGB port can support up to 24 bits in Video Mode.

表8-2. Active Signals –Data Interface

SIGNAL NAME

DESCRIPTION

RGB Parallel Interface Port 1

24-bit data inputs, 8 bits for each of the red, green, and blue channels. When interfacing to a system with 8-bits per

color or less, connect the bus of the red, green, and blue channels to the upper bits of the DLPC900 10-bit bus.

P1_(A, B, C)_[2:9] ⁽¹⁾

P_CLK1

Pixel clock; all input signals on data interface are synchronized with this clock.

P1_VSYNC

P1_HSYNC

P_DATAEN1

Vertical sync

Horizontal sync

Input data valid

RGB Parallel Interface Port 2

24-bit data inputs, 8 bits for each of the red, green, and blue channels. When interfacing to a system with 8-bits per

color or less, connect the bus of the red, green, and blue channels to the upper bits of the DLPC900 10-bit bus.

P2_(A, B, C)_[0:9] ⁽¹⁾

P_CLK2

Pixel clock; all input signals on data interface are synchronized with this clock.

P2_VSYNC

P2_HSYNC

P_DATAEN2

Optional Pixel Clock 3

P_CLK3

Vertical sync

Horizontal sync

Input data valid

Pixel clock; all input signals on data interface are synchronized with this clock.

(1) The A, B, and C input data channels of Port 1 and 2 can be internally swapped for optimum board layout. Refer to the DLPC900

Programmers Guide for details on how to configuring the port settings to match the board layout connections.

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8.2.1.2.1.3 DLPC900 System Output Interfaces

DLPC900 system output interfaces include the illumination interface as well as the trigger and sync interface.

8.2.1.2.1.3.1 Illumination Interface

An illumination interface is provided that supports up to a three (3) channel LED driver. The illumination interface

provides signals that support: LED driver enable, LED enable, LED enable select, and PWM signals to control

the LED current.

表8-3. Active Signals - Illumination Interface

SIGNAL NAME

HEARTBEAT

DESCRIPTION

Signal toggles continuously to indicate system is running fine.

FAULT_STATUS

RED_LED_EN

GRN_LED_EN

BLU_LED_EN

Signal toggles or held high indicating system faults

Red LED enable

Green LED enable

Blue LED enable

RED_LED_PWM

GRN_LED_PWM

BLU_LED_PWM

Red LED PWM signal used to control the LED current

Green LED PWM signal used to control the LED current

Blue LED PWM signal used to control the LED current

8.2.1.2.1.3.2 Trigger and Sync Interface

The DLPC900 outputs a trigger signal for synchronizing displayed patterns with a camera, sensor, or other

peripherals. The sync output supporting signals are: horizontal sync, vertical sync, two input triggers, and two

output triggers. Depending on the application, these signals control how the pattern is displayed.

表8-4. Active Signals - Trigger and Sync Interface

SIGNAL NAME

P1_HSYNC

P1_VSYNC

TRIG_IN_1

DESCRIPTION

Horizontal Sync

Vertical Sync

Depending on the mode, advances the pattern display.

Depending on the mode, starts or stops the pattern display.

Active high during pattern exposure

TRIG_IN_2

TRIG_OUT_1

TRIG_OUT_2

Active high pulse to indicate first pattern display

8.2.1.2.1.4 DLPC900 System Support Interfaces

8.2.1.2.1.4.1 Reference Clock and PLL

The DLPC900 controller requires a 20-MHz 3.3-V external input from an oscillator. This signal serves as the

DLPC900 chipset reference clock from which the majority of the interfaces derive their timing. This includes

DMD interfaces and serial interfaces.

Refer to 节10.1.2 on PLL guidelines.

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8.2.1.2.1.4.2 Program Memory Flash Interface

The DLPC900 provides three external program memory chip selects for standard NOR-type flash:

• PM_CSZ_0 –flash device (≤16-megabytes )

• PM_CSZ_1 –dedicated CS for boot flash device (≤16-megabytes ). Refer to the 图8-2 for the memory

layout of the boot flash.

• PM_CSZ_2 –flash device (≤16-megabytes )

Flash access timing is programmable up to 19 wait-states. 表 8-5 contains the formulas to calculate the required

wait-states for each of the parameters shown in 图 8-3 for a typical flash device. Refer to the DLPC900

Programmers Guide for details on how to set new wait-state values.

表8-5. Flash Wait-States

PARAMETER

FORMULA ⁽¹⁾

DEFAULT

T_CS(CSZ low to WEZ low )

T_WP(WEZ low to WEZ high)

T_CH(WEZ high to CSZ high )

T_ACC(CSZ low to Output Valid ) ⁽²⁾

Maximum supported wait-states

= Roundup((T_CS+ 5 ns) / 6.7 ns)

= Roundup((T_WP+ 5 ns) / 6.7 ns)

= Roundup((T_CH+ 5 ns) / 6.7 ns)

= Roundup((T_ACC+ 5 ns) / 6.7 ns)

2

11

2

19

19 (120ns) ⁽³⁾

(1) Assumes a maximum single direction trace length of 75 mm.

(2) In some flash device data sheets, the read access time can also be represented as T_OE, T_E, T_RC, or T_CE. Use the largest of these

values to calculate the wait-states for the read access time.

(3) For each parameter.

READ

WRITE

TCS

TWP

TCH

CSZ

WEZ

OEZ

TACC

RD31:16

DATA

RD15:0

WD15:0

WD31:16

图8-3. Flash Interface Timing Diagram

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8.2.1.2.1.4.3 DMD Interface

The DLPC900 controller provides the pattern data to the DMD over a double data rate (DDR) interface. 表 8-6

describes the signals used for this interface.

表8-6. Active Signals - DLPC900 to DMD Digital Data Interface

SIGNAL NAME

DDA(15:0)

DDB(15:0)

DCKA

DESCRIPTION

DMD, LVDS interface channel A, differential serial data

DMD, LVDS interface channel B, differential serial data

DMD, LVDS interface channel A, differential clock

DMD, LVDS interface channel B, differential clock

DMD, LVDS interface channel A, differential serial control

DMD, LVDS interface channel B, differential serial control

DCKB

SCA

SCB

The DLPC900 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the

DMD.

表8-7. Active Signals - DLPC900 to DMD Control Interface

SIGNAL NAME

DESCRIPTION

DADOEZ

DMD output-enable (active low)

DADADDR(3:0) DMD address

DADMODE(1:0) DMD mode

DADSEL(1:0)

DADSTRB

DAD_INTZ

DMD select

DMD strobe

DMD interrupt (active low). This signal requires an external 1-KΩpullup and uses hysteresis.

The DLPC900 controls the micromirror control interface signals in a manner to ensure proper and reliable

operation of the DMD.

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8.2.2 Typical Single Controller Chipset

A typical embedded system application using the DLPC900 controller and DLP6500 is shown in 图 8-4. This

configuration uses one DLPC900 controller to operate with a DLP6500 and supports a 24-bit parallel RGB input,

typical of LCD interfaces, from an external source or processor.

This system supports both still and motion video sources. However, the controller only supports sources with

periodic synchronization pulses. This is ideal for motion video sources, but can also be used for still images by

maintaining periodic syncs and only sending a new frame of data when needed. The still image must be fully

contained within a single video frame and meet the frame timing constraints. The DLPC900 controller refreshes

the displayed image at the source frame rate and repeats the last active frame for intervals in which no new

frame has been received.

This configuration also supports the high speed sequential pattern modes mentioned in the 节 7.4.1. The

patterns can be from the video source, from the USB or I²C interface, or pre-stored in external flash, and have a

maximum of 24 bits per pixel. The patterns are pre-loaded into the internal embedded DRAM and then streamed

to the DLP6500 at high speeds.

图8-4. Typical Application Schematic for DLP6500

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9 Power Supply Recommendations

9.1 System Power Regulation

The PLLD_VAD, PLLM1_VAD, and PLLM2_VAD power feeding internal PLLs must be derived from an isolated

linear regulator with filter as recommended in 节10.1.2 to minimize the AC noise component.

It is acceptable to derive PLLD_VDD, PLLM1_VDD, PLLM2_VDD, and PLLS_VAD from the same regulator as

the core VDDC, but they must be filtered as recommended in the 节10.1.2.

DLPC900

Regulator

Vout

1.15V

1.15V Core & eDRAM I/O

1.15V PLLs

Filter

Regulator

Vout

1.8V

1.8V PLLs

Regulator

Vout

1.8V DMD I/O & eDRAM

Regulator

Vout

3.3V

Voltage

Monitors

DC

PWRGOOD

POSENSE

PWRGOOD

POSENSE

GND

图9-1. Power Regulation

9.1.1 Power Distribution System

9.1.1.1 1.15-V System Power

The DLPC900 can support a low-cost power delivery system with a single 1.15-V power source derived from a

switching regulator. The main core can receive 1.15 V power directly from the regulator output, and the internal

DLPC900 PLLs (PLLD_VDD, PLLM1_VDD, PLLM2_VDD, and PLLS_VAD) must receive individually filtered

versions of this 1.15 V power. For specific filter recommendations, refer to the 节10.1.2.

9.1.1.2 1.8-V System Power

The DLPC900 power delivery system provides two independent 1.8-V power sources. One of the 1.8-V power

sources is used to supply 1.8-V power to the DLPC900 LVDS I/O and internal DRAM. Power for these functions

must always be fed from a common source, which is recommended as a linear regulator. The second 1.8-V

power source is used (along with appropriate filtering as discussed in the 节10.1.2) to supply all of the DLPC900

internal PLLs (PLLD_VAD, PLLM1_VAD, and PLLM2_VAD). To keep this power as clean as possible, a

dedicated linear regulator is highly recommended for the 1.8-V power to the PLLs.

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9.1.1.3 3.3-V System Power

The DLPC900 can support a low-cost power delivery system with a single 3.3-V power source derived from a

switching regulator. This 3.3-V power will supply all LVTTL I/O and the crystal oscillator cell. The 3.3-V power

must remain active in all power modes for which 1.15-V core power is applied.

9.2 System Environment and Defaults

9.2.1 DLPC900 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC900 will perform a power-up initialization routine that will default the

controller to its normal power mode in which all blocks are powered, all processor clocks will be enabled at their

full rate and associated resets will be released. Most other clocks will default disabled with associated resets

asserted until released by the processor. These same defaults will also be applied as part of all system reset

events that occur without removing or cycling power. The 1.8-V power must be applied prior to releasing the

reset so that the LVDS I/O and the internal embedded DRAM are enabled before the DLPC900 begins executing

its system initialization routines.

9.3 System Power-Up Sequence

Although the DLPC900 requires an array of power supply voltages, for example, 1.15 V, 1.8 V, and 3.3 V, there

are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC900, as

long as the system is held in reset during power supply sequencing. This is true for both power-up (reset

controlled by POSENSE) and power-down (reset controlled by PWRGOOD) scenarios. Similarly, there is no

minimum time between powering-up or powering-down the different supplies feeding the DLPC900. However,

power-sequencing requirements are common for the devices that share the supplies with the DLPC900.

Power-sequencing recommendations to ensure proper operation are:

• 1.15-V core power must be applied whenever any I/O power is applied. This ensures the state of the

associated I/O that are powered are set to a known state. Thus, applying core power first is recommended.

• All DLPC900 power must be applied before POSENSE is asserted to ensure proper power-up initialization is

performed.

It is assumed that all DLPC900 power-up sequencing is handled by external hardware. It is also assumed that

an external power monitor will hold the DLPC900 in system reset during power-up (that is, POSENSE = 0).

During this time all controller I/O's will be tri-stated. The primary PLL (PLLM1) will be released from reset upon

the low-to-high transition of POSENSE, but the DLPC900 will be kept in reset for an additional 60 ms to allow the

PLL to lock and stabilize its outputs. After this delay the DLPC900 internal resets will be deasserted, thus

causing the processor to begin its boot-up routine.

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图9-2 shows the recommended DLPC900 system power-up sequence of the regulators:

图9-2. Power Sequencing

9.3.1 Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the controller minimum supply voltage specification. Thus

for practical reasons, the external power monitor generating POSENSE must target its threshold to 90% of the

minimum supply voltage specifications and ensure that POSENSE remains low a sufficient amount of time for all

supply voltages to reach minimum DLPC900 and DMD requirements and stabilize. The trip voltage for detecting

the loss of power, as well as the reaction time to respond to a low voltage condition is critical for powering down

the DMD. Refer to 节6.7 for details on powering up and powering down the DLPC900 and the DMD.

9.3.2 Power Good (PWRGOOD) Support

The PWRGOOD signal is defined as an early warning signal that alerts the DLPC900 of the DC supply voltages

will drop below specifications. This warning lets the DLPC900 park the DMD mirrors and place the system into

reset. For revision "B" DMDs and later, PWRGOOD can no longer be used as an early warning signal, and must

follow the power-down requirements in 节6.7.

9.3.3 5-V Tolerant Support

With the exception of USB_DAT, the DLPC900 does not support any other 5-V tolerant I/O. However, I²C

typically have 5V requirements and special measures must be taken to support them. It is recommended that a

5-V to 3.3-V level shifter be used.

It is strongly recommended that a 0.5-W external series resistance (of 22 Ω) to limit the potential impact of a

continuous short circuit between either USB D+ or USB D– to either Vbus, GND, the other data line, or the

cable. For additional protection, also add an optional 200-mA Schottky diode from USB_DAT to VDD33.

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9.4 System Reset Operation

9.4.1 Power-Up Reset Operation

Immediately after a power-up event, DLPC900 hardware will automatically bring up the primary PLL and place

the controller in normal power mode. It will then follow the standard system reset procedure (see 节9.4.2).

9.4.2 System Reset Operation

Immediately after any type of system reset (power-up reset, PWRGOOD reset, watchdog timer time-out, and so

forth), the DLPC900 automatically returns to normal power mode and returns to the following state:

• All GPIO will tri-state.

• The primary PLL will remain active (it is only reset on a power-up reset) and most of the derived clocks will be

active. However, only those resets associated with the DLPC900 processor and its peripherals will be

released. (The DLPC900 firmware is responsible for releasing all other resets).

• The DLPC900 associated clocks will default to their full clock rates (boot-up is at full speed).

• The PLL feeding the LVDS DMD interface (PLLD) will default to its power-down mode and all derived clocks

will be inactive with corresponding resets asserted. (The DLPC900 firmware is responsible for enabling these

clocks and releasing associated resets).

• LVDS I/O will default to its power-down mode with tri-stated outputs.

• All resets output by the DLPC900 will remain asserted until released by the firmware (after boot-up).

• The DLPC900 processor will boot-up from external flash.

Once the DLPC900 processor boots-up, the DLPC900 firmware will:

• Configure the programmable DDR clock generator (DCG) clock rates (that is, the DMD LVDS interface rate)

• Enable the DCG PLL (PLLD) while holding divider logic in reset

• After the DCG PLL locks, the processor software will set DMD clock rates

• API software will then release DCG divider logic resets, which in turn, will enable all derived DCG clocks

• Release external resets

The LVDS I/O is reset by a system reset event and remains in reset until released by the DLPC900 firmware.

Thus, the software is responsible for waiting until power is restored to these components before releasing reset.

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10 Layout

10.1 Layout Guidelines

10.1.1 General PCB Recommendations

Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.

10.1.2 PCB Layout Guidelines for Internal Controller PLL Power

The following are guidelines to achieve desired controller performance relative to internal PLLs:

The DLPC900 contains four PLLs (PLLM1, PLLM2, PLLD, and PLLS), each of which have a dedicated 1.15 V

digital supply; three of these PLLs (PLLM1, PLLM2, and PLLD) have a dedicated 1.8 V analog supply. It is

important to have filtering on the supply pins that covers a broad frequency range. Each 1.15 V PLL supply pin

must have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor. These

components must be located very close to the individual PLL supply balls. The impedance of the ferrite bead

should far exceed that of the capacitor at frequencies above 10 MHz. The 1.15 V to the PLL supply pins must

also have low frequency filtering in the form of an RC filter. This filter can be common to all the PLLs. The

voltage drop across the resistor is limited by the 1.15 V regulator tolerance and the DLPC900 voltage tolerance.

A resistance of 0.36 Ω and a 100 µF ceramic are recommended. 图 10-1 shows the recommended filter

topology.

Regulator

Vout

DLPC900

1.15V Core

1.15V

DC

R=0.36

F

1.15V PLL1

1.15V PLL2

1.15V PLL3

VPLL

GND

100 ꢀF

0.1 ꢀF

GND

F

0.1 ꢀF

GND

0.1 ꢀF

GND

F

0.1 ꢀF

GND

图10-1. Recommended Filter Topology for PLL 1.15-V Supplies

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The analog 1.8-V PLL power pins must have a similar filter topology as the 1.15-V. In addition, it is

recommended that a dedicated linear regulator generates the 1.8-V. 图 10-2 shows the recommended filtering

topology.

DLPC900

Regulator

R=1

1.8V

Vout

F

1.8V PLL1

1.8V PLL2

1.8V PLL3

DC

100 ꢀF

0.1 ꢀF

GND

0.1 ꢀF

GND

0.1 ꢀF

GND

图10-2. Recommended Filter Topology for PLL 1.8-V Supplies

When designing the overall supply filter network, care must be taken to ensure no resonance occurs. Specific

care is required around the 1- to 2-MHz band, as this coincides with the PLL natural loop frequency.

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Signal VIA

PCB Pad

VIA to Common Analog /

Digital Board Power Plane

ASIC Pad

VIA to Common Analog /

Digital Board Ground Plane

22

23

24

25

26

Local

Decoupling for

PLL Supplies

(view from top

of board)

A

FB

PLLD_

VAS

PLLD_

VAD

K

PLLD_

VDD

PLLD_

VSS

PLLM1_

VDD

PLLM1_

VAS

PLLM1_

VAD

L

M

N

P

R

FB

PLLM1_

VSS

MOSC

MOSC Crystal

Oscillator

MOSCN

PLLM2_

VDD

PLLM2_

VSS

FB

PLLM2_

VAS

PLLS_

VAD

PLLS_

VAS

PLLM2_

VAD

FB

图10-3. High Frequency Decoupling

High-frequency decoupling is required for 1.15-V and 1.8-V PLL supplies and must be provided as close as

possible to each of the PLL supply package pins as shown in 图 10-3. Placing decoupling capacitors under the

package on the opposite side of the board is recommended. High-quality, low-ESR, monolithic, surface-mount

capacitors are recommended for use. Typically, 0.1 µF for each PLL supply should be sufficient. The length of a

connecting trace increases the parasitic inductance of the mounting, and thus, where possible, there can be no

trace, allowing the via to butt up against the land. Additionally, the connecting trace must be made as wide as

possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the

number of vias.

The location of bulk decoupling depends on the system design.

10.1.3 PCB Layout Guidelines for Quality Video Performance

One of the most important factors to gain good performance is designing the PCB with the highest quality signal

integrity possible. Here are a few recommendations:

1. Minimize the trace lengths between the video digital receiver and the DLPC900 port inputs.

2. Analog power must not be shared with the digital power directly.

3. Try to keep the trace lengths of the RGB as equal as possible.

4. Impedance matching between the digital receiver and the DLPC900 is important.

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10.1.4 Recommended MOSC Crystal Oscillator Configuration

A recommended crystal oscillator configuration is shown in 图10-4.

It is assumed that the external crystal oscillator will stabilize within 50 ms after stable power is applied.

表10-1. Crystal Port Characteristics

PARAMETER

MOSC-to-GND capacitance

MOSCZ-to-GND capacitance

NOMINAL

UNIT

pF

1.5

pF

表10-2. Recommended Crystal Configuration ⁽¹⁾

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

Crystal nominal frequency

Crystal temperature stability

20

MHz

PPM

± 30

Crystal frequency tolerance (including accuracy,

temperature, aging, and trim sensitivity)

± 100

Crystal equivalent series resistance (ESR)

Crystal load

50 max

20

Ω

pF

Crystal shunt load

7 max

100

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor (MOSC)

C_L2external crystal load capacitor (MOSCN)

PCB layout

Ω

MΩ

pF

1

See 方程式1

See 方程式2

pF

A ground isolation ring around the crystal is recommended

(1) Typical drive level with the XSA020000FK1H-OCX crystal (ESR_max= 40 Ω) = 50 µW

C_L1= 2 × (C_L–C_Stray-MOSC

)

(1)

(2)

(3)

C_L2= 2 × (C_L–C_Stray-MOSCN

where

• C_L= Crystal load capacitance (Farads)

• C_Stray-MOSC= Sum of package and PCB capacitance at the crystal pin associated with controller signal

MOSC.

• C_Stray-MOSCN= Sum of package and PCB capacitance at the crystal pin associated with controller signal

MOSCN.

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MOSC

MOSCN

R_FB

R_S

(Crystal)

C_L1

C_L2

图10-4. Crystal Oscillator Configuration

10.1.5 Spread Spectrum Clock Generator Support

DLPC900 supports limited, internally controlled, spread spectrum clock spreading on the DMD interface. The

purpose is to frequency-spread all signals on this high-speed external interface to reduce EMI emissions. Clock

spreading is limited to triangular waveforms. The DLPC900 provides modulation options of 0%, ±0.5%, and

±1.0% (center-spread modulation).

10.1.6 GPIO Interface

The DLPC900 provides 9 software-programmable, general-purpose I/O pins. Each GPIO pin is individually

configurable as either input or output. In addition, each GPIO output can be either configured as push-pull or

open-drain. Some GPIO have one or more alternative use modes, which are also software configurable. The

reset default for all GPIO is as an input signal. However, any alternative function connected to these GPIO pins,

with the exception of general-purpose clocks and PWM generation, will be reset. When configured as open-

drain, the outputs must be externally pulled-up (to the 3.3-V supply). External pullup or pulldown resistors can be

required to ensure stable operation before software can configure these ports.

10.1.7 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, it is recommended tying unused

controller input pins through a pullup resistor to its associated power supply or through a pulldown to ground

unless noted in the Pin Functions. For controller inputs with an internal pullup or pulldown resistor, it is

unnecessary to add an external pullup or pulldown unless specifically recommended. Internal pullup and

pulldown resistors are weak and must not be expected to drive the external line.

Unused output-only pins can be left open.

When possible, it is recommended to configure unused bidirectional I/O pins to their output state such that the

pin can be left open. If this control is not available and the pins become an input, then they must be pulled-up (or

pulled-down) using an appropriate resistor unless noted in the Pin Functions.

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10.1.8 DMD Interface Considerations

High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface)

is dependent on the following factors:

• Total length of the interconnect system

• Spacing between traces

• Characteristic impedance

• Etch losses

• How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup Margin = (controller output setup) –(DMD input setup) –(PCB routing mismatch) –(PCB SI degradation) (4)

Hold-time Margin = (controller output hold) –(DMD input hold) –(PCB routing mismatch) –(PCB SI degradation) (5)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as

simultaneously switching output (SSO) noise, crosstalk, and intersymbol interference (ISI) noise.

DLPC900 I/O timing parameters, as well as DMD I/O timing parameters, can be easily found in their

corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB

routing. However, PCB SI degradation is not as easy-to-determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these

recommendations can work, but must be confirmed with PCB signal integrity analysis or lab measurements.

PCB design: Refer to the 图10-5.

Configuration:

Etch thickness (T):

Flex etch thickness (T):

Single-ended signal impedance:

Differential signal impedance:

Asymmetric dual stripline

1.0-oz copper (1.2 mil)

0.5-oz copper (0.6 mil)

50 Ω(±10%)

100 Ω(±10%)

PCB stackup: Refer to the 图10-5.

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the I/O power plane or ground.

Dielectric FR4, (Er):

4.2 (nominal)

Signal trace distance to reference plane 1 (H1):

Signal trace distance to reference plane 2 (H2):

5.0 mil (nominal)

34.2 mil (nominal)

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Reference Plane 1

H1

H2

W

T

Trace

S

Trace

Dielectric Er

H2

T

Trace

H1

Reference Plane 2

图10-5. PCB Stackup Geometries

表10-3. General PCB Routing (Applies to All Corresponding PCB Signals, Refer to 图10-5)

SINGLE-ENDED

PARAMETER

APPLICATION

Escape routing in ball field

PCB etch data or control

PCB etch clocks

DIFFERENTIAL PAIRS UNIT

SIGNALS

4

(0.1)

4

mil

(0.1)

(mm)

7

4.25

mil

Line width (W)

(0.18)

(0.11)

(mm)

7

4.25

mil

(0.18)

(0.11)

(mm)

5.75 ⁽¹⁾

(0.15)

mil

(mm)

PCB etch data or control

PCB etch clocks

N/A

Differential signal pair spacing (S)

5.75 ⁽¹⁾

(0.15)

mil

(mm)

20

(0.51)

mil

(mm)

PCB etch data or control

PCB etch clocks

Minimum differential pair-to-pair spacing (S)

20

(0.51)

mil

(mm)

4

(0.1)

4

(0.1)

mil

(mm)

Escape routing in ball field

PCB etch data or control

PCB etch clocks

10

(0.25)

20

(0.51)

mil

(mm)

Minimum line spacing to other signals (S)

20

(0.51)

20

(0.51)

mil

(mm)

12

(0.3)

mil

(mm)

Total data

N/A

Maximum differential pair P-to-N length

mismatch

12

(0.3)

mil

(mm)

Total clock

(1) Spacing can vary to maintain differential impedance requirements.

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表10-4. DMD Interface Specific PCB Routing

SIGNAL GROUP LENGTH MATCHING

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD

(LVDS)

SCA_P/ SCA_N

DDA_P_(15:0)/ DDA_N_(15:0)

± 150

(± 3.81)

mil

(mm)

DCKA_P/ DCKA_N

DMD

(LVDS)

SCB_P/ SCB_N

DDB_P_(15:0)/ DDB_N_(15:0)

± 150

(± 3.81)

mil

(mm)

DCKB_P/ DCKB_N

When routing the DMD Interface signals it is recommended to:

• Minimize the number of layer changes for Single-ended signals.

• Individual differential pairs can be routed on different layers but the signals of a given pair must not change

layers.

表10-5. DMD Signal Routing Length⁽¹⁾

BUS

MIN

MAX

UNIT

DMD

(LVDS)

50

375

mm

(1) Max signal routing length includes escape routing.

Stubs: Stubs are to be avoided.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω

internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements can be used:

• Differential crosstalk: < 5%

• Differential impedance: 75 to 125-Ω

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs must be routed

in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference

for each row must be accounted for on associated PCB etch lengths.

These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4-

ps, assuming 175 ps/inch FR4 propagation delay.

These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold

margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.

Both the DLPC900 output timing parameters and the DMD input timing parameters include timing budget to

account for their respective internal package routing skew.

10.1.8.1 Flex Connector Plating

Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of

electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel.

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10.1.9 PCB Design Standards

PCB designed and built in accordance with the following industry specifications:

表10-6. Industry Design Specification

INDUSTRY SPECIFICATION

IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility

IPC-6011 and IPC-6012, Class 2

APPLICABLE TO

Board Design

PWB Fabrication

Finished PWB Solder mask

Finished PWB

IPC-SM-840, Class 3, Color Green

UL94V-0 Flammability Rating and Marking

UL796 Rating and Marking

Finished PWB

10.1.10 Signal Layers

The PCB signal layers must follow typical good practice guidelines including:

• Layer changes must be minimized for single-ended signals.

• Individual differential pairs can be routed on different layers, but the signals of a given pair must not change

layers.

• Stubs are to be avoided.

• Only voltage or low-frequency signals can be routed on the outer layers, except as noted previously in this

document.

• Double data rate signals must be routed first.

• Pin swapping on components is not allowed.

The PCB must have a solder mask on the top and bottom layers. The mask must not cover the vias.

• Except for fine pitch devices (pitch ≤0.032 inches), the copper pads and the solder mask cutout are to be of

the same size.

• Solder mask between pads of fine pitch devices must be removed.

• In the BGA package, the copper pads and the solder mask cutout must be of the same size.

10.1.11 Trace Widths and Minimum Spacing

BGA escape routing can be routed with 4-mils width and 4-mils spacing, as long as the escape nets are less

than 1 inch long, to allow 2 traces fit between vias. After signals escape the BGA field, trace widths can be

widened to achieve the desired impedance and spacing.

All single-ended 50-Ω signal must have a minimum spacing of 10mils relative to other signals. Other special

trace spacing requirements are listed in 表10-7.

表10-7. Traces Widths and Minimum Spacing

SIGNAL ON PIN

VDDC, VDD18, VDD33

MINIMUM WIDTH

MINIMUM SPACE

0.020

0.015

0.005

0.015

GND

0.015 ⁽¹⁾

PLLS_VAD, PLLM2_VDD, PLLD_VDD,

PLLM1_VDD, PLLM1_VAD, PLLM2_VAD,

PLLD_VAD

0.012 (keep length less than 260 mils)

MOSCP, OCLKA

0.020 ⁽²⁾

0.030 ⁽²⁾

SCA_(P,N), DDA_(P,N)_(15:00), SCB_(P,N),

DDB_(P,N)_(15:00), DCKA_(P,N),

DCKB_(P,N)

USB_DAT_(P,N)

0.030 ⁽²⁾

(1) Make width of GND trace as wide as the pin it is connected to, when possible.

(2) Trace spacing of these signals/signal-pairs relative to other signals.

10.1.12 Trace Impedance and Routing Priority

For best performance, it is recommended that the trace impedance for differential signals as in 表10-8.

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All signals must be 50-Ωcontrolled impedance unless otherwise noted in 表10-8.

表10-8. Trace Impedance

SIGNAL ON PIN

DIFFERENTIAL IMPEDANCE

DCKA_(P,N)

100 Ω±10%

SCA_(P,N)

DDA_(P,N)_(15:00)

DCKB_(P,N)

100 Ω±10%

SCB_(P,N)

DDB_(P,N)_(15:00)

USB_DAT_(P,N)

USB_(P,N)

90 Ω±10%

All other Differential Signals

100 Ω±10%

表10-9 lists the signals’routing priority assignment.

表10-9. Routing Priority

SIGNAL ON PIN

PRIORITY

DCKA_(P,N) SCA_(P,N) DDA_(P,N)_(15:00) DCKB_(P,N) SCB_(P,N) 1 ^{(1) (2) (3)}

DDB_(P,N)_(15:00)

USB_(P,N) USB_DAT_(P,N)

2 ⁽¹⁾

P1(A,B,C)(9:2),P2(A,B,C)(9:2), P_CLK1, P_CLK2, P_CLK3,

P_DATEN1, P_DATEN2, P1_VSYNC, P2_VSYNC, P1_HSYNC,

P2_HSYNC

3 ^{(1) (2) (3)}

OCLKA, MOSCP

4 ⁽⁴⁾

(1) Refer to Table 8 for length matching requirement

(2) Switching layers must not be done except at the beginning and end of the trace

(3) Maximum routing length of 2 inches for each signal/pair, includes escape routing

(4) Keep routing length under 0.35 inches

10.1.13 Power and Ground Planes

For best performance, the following are recommendations:

• Solid ground planes between each signal routing layer

• Two solid power planes for voltages

• Power and ground pins must be connected to these planes through a via for each pin

• All device pin and via connections to these planes must use a thermal relief with a minimum of four spokes

• Trace lengths for the component power and ground pins must be minimized to 0.03 inches or less

• Vias should be spaced out to avoid forming slots on the power planes

• High speed signals must not cross over a slot in the adjacent power planes

• Vias connecting all the digital layers are recommended for placement around the edge of the rigid PCB

regions 0.03 inches from the board edges with 0.1 inch spacing prior to routing

• Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of

devices

• All signal routing and signal vias must be inside the perimeter ring of ground vias

10.1.14 Power Vias

Power and Ground pins of each component must be connected to the power and ground planes with a via for

each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for

component power and ground pins must be minimized (ideally, less than 0.100”). Unused or spare device pins

that are connected to power or ground can be connected together with a single via to power or ground. The

minimum spacing between vias shall be 0.050”to prevent slots from being developed on the ground plane.

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10.1.15 Decoupling

Decoupling capacitors must be located as near as possible to the DLPC900 voltage supply pins. Capacitors

must not share vias. The DLPC900 power pins can be connected directly to the decoupling capacitor (no via) if

the trace is less than 0.03”. Otherwise the component must be tied to the voltage or ground plane through a

separate via. All capacitors must be connected to the power planes with trace lengths less than 0.05”. Mount

decoupling capacitors connecting to power rail VDDC (1.15-V) using “via on sides” geometry as shown below

in 图 10-6. If “via on the side” is not possible, 1.15-V decoupling capacitors can be mounted using “via at

ends” method, providing traces between the vias and decoupling capacitors’ pads be as short and wide (at

least 15-mils wide) as possible.

图10-6. Decoupling Via Placement

10.1.16 Fiducials

Fiducials for automatic component insertion are placed on the board according to the following guidelines or on

recommendation from manufacturer:

• Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PCB

• Fiducials shall be 0.050”copper with 0.100”cutout (antipad).

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10.2 Layout Example

The DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) PCB is targeted at 14 layers with layer stack

up shown in 图 10-7. The PCB layer stack can vary depending on system design. However, careful attention is

required to meet design considerations. Layers 1 and 14 consist of the component layers. Layers 2, 4, 6, 9, 11,

and 13 consist of solid ground planes. Layers 7 and 8 consist of solid power planes. Layers 1, 3, 5, 10, 12, and

14 are used as the primary routing layers. Routing on external layers must be less than 0.25 inches for priority

one and two signals. Refer to the 表10-9 for signal priority groups. Board material must be FR-370HR or similar.

PCB must be designed for lead-free assembly with the stackup geometry shown in 图10-7 and 图10-8.

图10-7. Board Layer Stack

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图10-8. Board Trace Geometry

Refer to 节 10.2 for a complete set of documentation for the DLP® LightCrafter™ Dual DLPC900 Evaluation

Module (EVM) reference design.

10.3 Thermal Considerations

The thermal limitation for the DLPC900 is that the maximum operating junction temperature (T_J) must not be

exceeded (this is defined in 节 6.3). This temperature is dependent on operating ambient temperature, airflow,

PCB design (including the component layout density and the amount of copper used), power dissipation of the

DLPC900, and power dissipation of surrounding components. The DLPC900 device package is designed

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primarily to extract heat through the power and ground planes of the PCB, thus copper content and airflow over

the PCB are important factors.

The recommended maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC900 power dissipation and R_θJAat 1 m/s of forced airflow, where R_θJAis the thermal

resistance of the package as measured using a JEDEC-defined standard test PCB. This JEDEC test PCB is not

necessarily representative of the DLPC900 PCB, and thus the reported thermal resistance can be inaccurate in

the actual product application. Although the actual thermal resistance can be different, it is the best information

available during the design phase to estimate thermal performance. However after the PCB is designed and the

product is built, it is highly recommended thermal performance be measured and validated.

To do this, the top-center case temperature must be measured under the worst case product scenario (max

power dissipation, max voltage, max ambient temp) and validated not to exceed the maximum recommended

case temperature (T_C). This specification is based on the measured φ_JTfor the DLPC900 package and provides

a relatively accurate correlation to junction temperature. Care must be taken when measuring this case

temperature to prevent accidental cooling of the package surface. It is recommended to use a small

(approximately 40 gauge) thermocouple. The bead and the thermocouple wire must be covered with a minimal

amount of thermally conductive epoxy and contact the top of the package. The wires are routed closely along

the package and the board surface to avoid cooling the bead through the wires.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

DLPC900

ZPC

Package

Revision

Device Descriptor

图11-1. Device Number Description

11.1.2 Device Markings

R

DLP

TEXAS INSTRUMENTS

Part Number

DLPC900_ZPC

PPPPPPPP-000R

SSSSSSYYWWQQ

LLLLLLL

TI Proprietary data

G1

Location A1

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11.1.3 DEFINITIONS - Video Timing Parameters

Active Lines Per Frame Defines the number of lines in a frame containing displayable data: ALPF is a subset

(ALPF) of the TLPF.

Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data: APPL is a

(APPL) subset of the TPPL.

Horizontal Back Porch Number of blank pixel clocks after horizontal sync but before the first active pixel.

(HBP) Blanking

Note: HBP times are reference to the leading (active) edge of the respective sync

signal.

Horizontal Front Porch Number of blank pixel clocks after the last active pixel but before Horizontal Sync.

(HFP) Blanking

Horizontal Sync (HS)

Timing reference point that defines the start of each horizontal interval (line). The

absolute reference point is defined by the active edge of the HS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all horizontal blanking parameters are measured.

Total Lines Per Frame Defines the vertical period (or frame time) in lines: TLPF = Total number of lines per

(TLPF)

frame (active and inactive).

Total Pixel Per Line

(TPPL)

Defines the horizontal line period in pixel clocks: TPPL = Total number of pixel clocks

per line (active and inactive).

Vertical Back Porch

(VBP) Blanking

Number of blank lines after vertical sync but before the first active line.

Vertical Front Porch

(VFP) Blanking

Number of blank lines after the last active line but before vertical sync.

Vertical Sync (VS)

Timing reference point that defines the start of the vertical interval (frame). The

absolute reference point is defined by the active edge of the VS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all vertical blanking parameters are measured.

11.2 Documentation Support

11.2.1 Related Documentation

The following documents contain additional information related to the use of the DLPC900 device.

表11-1. Related Documents

DOCUMENT

DLP6500FLQ DMD Data Sheet

DOCUMENT LINK

DLPS040

DLP6500FYE DMD Data Sheet

DLP9000 DMD Data Sheet

DLP500YX DMD Data Sheet

DLP670S DMD Data Sheet

DLPC900 Programmer's Guide

DLPS053

DLPS036

DLPS193

DLPS194

DLPU018

DLP® LightCrafter™ Single DLPC900 Evaluation Module (EVM) User's

Guide

DLPU101

DLPU102

DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) User's

Guide

Reference Design Documentation

DLPLCR900EVM DLPLCR900DEVM DLPLCR65EVM

DLPLCR50XEVM DLPLCR67EVM DLPLCR90EVM

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

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11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

LightCrafter^™are trademarks of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

DLP^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

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型号：	DLPC900
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DLP6500、DLP670S、DLP500YX 和 DLP9000 数字微镜器件的数字控制器控制器
文件：	总86页 (文件大小：3383K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC900 [TI]

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