DLPC910ZYR_技术文档

DLPC910

ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

DLPC910 数字DMD 控制器

1 特性

3 说明

• 运行以下DLP^®DMD 芯片

DLPC910 是适用于 DLP9000X、DLP9000XUV 和

DLP6500 三个 DMD 器件的数字控制器。DLPC910 为

客户提供用于 DMD 的高速数据和控制接口，从而使

DLP9000X/DLP9000XUV DMD 的二进制图形速率高

达 15kHz，使 DLP6500 DMD 的二进制图形速率高达

11.5kHz。如此快速的模式速率使得 DLP 技术力压同

类其他空间照明调制器脱颖而出，并且可满足客户设备

对于快速、精确和可编程光源控制功能的需求，从而使

客户获得战略性优势。DLPC910 为 DMD 提供所需的

镜时钟脉冲和时序信息。DLPC910 器件具备独特的功

能和价值，非常适合为各种平版印刷、工业和高级显示

应用提供支持。

– DLP9000X DMD

– DLP9000XUV DMD

– DLP6500 DMD

• 用户可选择的输入时钟速率

– DLP9000X 和DLP9000XUV 为400MHz 或

480MHz

– DLP6500 为400MHz

• 连续流式输入数据

– DLP9000X 和DLP9000XUV 高达61Gb/s

– DLP6500 高达24Gb/s

• 启用高速图形速率

– DLP9000X 和DLP9000XUV 每秒高达15kHz

二进制图形

– DLP6500 每秒高达11.5kHz 二进制图形

• 8 位灰度图形速率

在基于 DLP 的电子解决方案中，从 DLPC910 输入端

口到被投影图像的图像数据是 100% 数字化的数据。

图像始终保持数字格式，永远不会转换为模拟信号。

DLPC910 会处理数字输入图像并将数据转换为 DMD

所需的图像格式，以确保正确显示。DMD 随后会将光

线导向载入DMD 中的像素数据所确定的位置。

– DLP9000X 和DLP9000XUV 采用调制照明时高

达1.8kHz

– DLP6500 采用调制照明时高达1.4kHz

• 64 位2x LVDS 数据总线接口

• 随机DMD 行寻址和Load4 加载

• 与多种用户定义的应用处理器或FPGA 兼容

• 用于控制和状态查询的I²C 接口

有关 DLPC910 的完整电气和机械规格，请参阅

Virtex^®-5 产品规格（网址为www.xilinx.com）。

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

DLPC910

封装

FCBGA (676)

27.00mm × 27.00mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 平版印刷

– 直接成像

– 平板显示器

– 印刷电路板制造

• 工业类

– 3D 打印

– 用于机器视觉的3D 扫描仪

– 质量控制

• 显示器

– 3D 成像

– 增强现实和信息覆盖

典型应用图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS064

DLPC910

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

Table of Contents

8 Application and Implementation..................................47

8.1 Application Information............................................. 47

8.2 Typical Application.................................................... 47

9 Power Supply Recommendations................................52

9.1 Power Supply Distribution and Requirements.......... 52

9.2 Power Down Requirements...................................... 52

10 Layout...........................................................................53

10.1 Layout Guidelines................................................... 53

10.2 Layout Example...................................................... 57

11 Device and Documentation Support..........................59

11.1 Device Support........................................................59

11.2 Documentation Support.......................................... 59

11.3 支持资源..................................................................59

11.4 Trademarks............................................................. 59

11.5 静电放电警告...........................................................60

11.6 术语表..................................................................... 60

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

Pin Functions.................................................................... 5

6 Specifications................................................................ 15

6.1 Absolute Maximum Ratings...................................... 15

6.2 ESD Ratings............................................................. 15

6.3 Recommended Operating Conditions.......................15

6.4 Thermal Information..................................................16

6.5 Electrical Characteristics...........................................16

6.6 Timing Requirements................................................16

7 Detailed Description......................................................18

7.1 Overview...................................................................18

7.2 Functional Block Diagram.........................................18

7.3 Feature Description...................................................18

7.4 Device Functional Modes..........................................26

7.5 Register Map.............................................................40

Information.................................................................... 60

4 Revision History

Changes from Revision C (March 2020) to Revision D (September 2020)

Page

• Updated Description section for DDC_DCLK_(A,B,C,D)_DP(N,P), DDC_DIN_(A,B,C,D)(1-15)_DP(N,P), and

DVALID_(A,B,C,D)_DP(N,P) from "100-Ωinternal LVDS termination." to "100-Ωexternal LVDS termination

required...............................................................................................................................................................5

• Updated I/O Type section for LOAD4_ENZ from LVCMOS33_I to LVCMOS25_I..............................................5

• Updated I/O Type section for DMD_IRQ from LVCMOS33_O to LVCMOS25_O...............................................5

• Corrected HBM and CDM values. ................................................................................................................... 15

• Corrected "...during which time RST_ACTIVE is asserted." to "...during which time RST_ACTIVE is NOT

asserted."..........................................................................................................................................................21

• Updated section name from "DMD Power Down" to "DMD Mirror Float". Removed outdated information about

power down...................................................................................................................................................... 21

• Removed "After PWR_FLOAT is asserted, a Mirror Clocking Pulse is issued, or a mirror Float operation is

requested" ........................................................................................................................................................23

• Updated I²C terminology to "primary" and "secondary" throughout section. ................................................... 24

• Updated performance plot for DLP6500 DMD (图8-4) ....................................................................................50

• Updated performance plot for DLP9000X/DLP9000XUV DMD (图8-3)...........................................................50

Changes from Revision B (November 2016) to Revision C (March 2020)

Page

• 将标题从DLPC910 数字控制器更改为DLPC910 数字DMD 控制器................................................................. 1

• 添加了新的DLP9000XUV DMD 作为DLPC910 支持的DMD（多个位置）......................................................1

• Updated "DDC_IIC_x" signal names to "DDC_I2C_x" in multiple locations....................................................... 5

• Added missing DLPC_DOUTBUSY pin to complete the listing of all 676 pins of DLPC910.............................. 5

• Added missing unconnected pins to complete the listing of all 676 pins of DLPC910....................................... 5

• Corrected signal name RESETZ to RESET_RSTZ .........................................................................................18

• Deleted package code FLS from DMD callout for readability ..........................................................................18

• Added section describing DDC_Version output pins ....................................................................................... 23

• Corrected I²C version from 1.0-1995 to 1.0-1992. ...........................................................................................24

• Combined Figure 8 and Figure 9 into new 图7-6 to incorporate Application Note/Tech Advisory dlpa092

(DLPC910 / DLPR910A - Continuous Row Command Operation). .................................................................34

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• Added DLP9000XUV to DMD Characteristics Table ....................................................................................... 35

• Changed "Connected DMD ID" to "Connected DMD TYPE" to match nomenclature of DMD_TYPE_[3:0] input

pins .................................................................................................................................................................. 40

• Added explanation that DDC_VERSION_(2:0) output values are mirrored in DESTOP_VERSION register... 43

• Corrected signal name RESETZ to RESET_RSTZ in DLP9000X block diagram ........................................... 47

• Corrected signal name RESETZ to RESET_RSTZ in DLP6500 block diagram ..............................................47

• Added DLP9000XUV to 图9-1 - changed previous sentence to clarify one DMD per DLPC910/DLPR910....52

• Added DLP9000XUV link to Related Documentation section ..........................................................................59

Changes from Revision A (October 2015) to Revision B (November 2016)

Page

• 简化了数据表标题...............................................................................................................................................1

• 在节1 中添加了支持的DMD 系列......................................................................................................................1

• Updated supply current values in 节6.5. .........................................................................................................16

• Indicated how SPEED_SEL should be set when DLP6500 is used in 节7.3.2 ...............................................18

• Added reference to the 节9.2 in 节7.3.6.4 ..................................................................................................... 21

• Replaced DMD part number and row count with variable VRes in 节7.3.6.5.1 .............................................. 22

• Indicated how SPEED_SEL should be set when DLP6500 is used in 节7.3.10.3 ..........................................25

• Added cross reference to 表7-11 in 节7.4 ......................................................................................................26

• Added cross reference to 表7-11 in 节7.4.1 ...................................................................................................26

• Added pixel mapping tables for both DMDs in 节7.4.1 ...................................................................................26

• Added single row write example for the DLP6500 in 节7.4.1.1 ...................................................................... 34

• Added DLP6500 to 表7-11 ..............................................................................................................................35

• Added the number of row cycles required to clear the entire DMD for the DLP6500 in 节7.4.3 .....................37

• Added DLP6500 to 表7-13 ..............................................................................................................................37

• Added cross reference to 表7-11 in 节7.4.4 ...................................................................................................37

• Added additional description for activating buses in 节7.5.1.9 ....................................................................... 45

• Added DLP6500 DMD to application details to 节8.2 .....................................................................................47

• Added cross reference to 表7-11 in 节8.2.1.1 ................................................................................................49

• Replaced references to part numbers with DMD in 节8.2.1.2 ........................................................................ 49

• Associated performance plot with appropriate DMD (图8-3)........................................................................... 50

• Added performance plot for DLP6500 DMD (图8-4)........................................................................................50

• Added power down requirements and increased the minimum 300 µs to 500 µs for maintaining power levels

in 节9.2 ........................................................................................................................................................... 52

• Added 表9-1, 图9-2, 图9-3 ............................................................................................................................52

Changes from Revision * (September 2015) to Revision A (October 2015)

Page

• 将器件状态从“产品预发布”更改为“量产数据”.............................................................................................1

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5 Pin Configuration and Functions

图5-1. ZYR Package 676-Pin FCBGA Top View

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I/O Type Descriptions

I/O TYPE

DESCRIPTION

PWR

Power

GND

Ground

LVDS_25_NI

LVDS_25_PI

LVDS_25_NO

LVDS_25_PO

LVCMOS25_I

LVCMOS25_O

LVCMOS25_B

LVCMOS33_I

LVCMOS33_O

LVCMOS33_B

LVDCI_33_O

NC

LVDS 2.5-V negative input

LVDS 2.5-V positive input

LVDS 2.5-V negative output

LVDS 2.5-V positive output

LVCMOS 2.5-V input

LVCMOS 2.5-V output

LVCMOS 2.5-V bidirectional

LVCMOS 3.3-V input

LVCMOS 3.3-V output

LVCMOS 3.3-V bidirectional

Low-voltage digitally controlled impedance 3.3-V output

No connection

Pin Functions

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

CTRL_RSTZ

F9

LVCMOS25_I

LVCMOS33_I

Lo = 0

-

DLPC910 Reset.

DLPC910 Secondary I²C Address Lo =

0x34, Hi = 0x36. Includes Internal pull-up.

DDC_I2C_ADDR_SEL

DDC_I2C_SCL

AA10

Y8

Hi = 1

DLPC910 Secondary I²C Clock.

Requires an external 1-kΩ pull-up

resistor.

LVCMOS33_B

-

DLPC910 Secondary I²C Data. Requires

an external 1-kΩ pull-up resistor.

DDC_I2C_SDA

AA8

DDC_I2C_SCL

CLKIN_R

E10

LVCMOS25_I

LVDCI_33_O

LVCMOS33_I

-

Reference clock

50-MHz Reference Clock

Connect to DMD RESET_ADDR0

Connect to DMD RESET_ADDR1

Connect to DMD RESET_ADDR2

Connect to DMD RESET_ADDR3

Connect to DMD RESET_MODE0

Connect to DMD RESET_MODE1

Connect to DMD RESET_SEL0

Connect to DMD RESET_SEL1

Connect to DMD RESET_STROBE

Connect to DMD RESET_OEZ

Connect to DMD RESET_IRQZ

RESET_ADDR0

RESET_ADDR1

RESET_ADDR2

RESET_ADDR3

RESET_MODE0

RESET_MODE1

RESET_SEL0

RESET_SEL1

RESET_STROBE

RESET_OEZ

AD18

AC18

AC17

AC16

AC13

AD13

AD15

AC14

AD10

AD14

AD8

Hi

Lo

-

RESET_IRQZ

Connect to DMD PWRDNZ and RESETZ

inputs

RESET_RSTZ

AB10

LVDCI_33_O

Lo

-

SCPCLK

AC7

AC8

AC9

AB9

G11

G12

H11

H12

E12

D13

E13

F13

H13

LVDCI_33_O

LVCMOS33_I

LVDCI_33_O

LVCMOS25_O

LVCMOS25_I

-

Connect to DMD SCP_CLK

Connect to DMD SCP_DO

Connect to DMD SCP_DI

Connect to DMD SCP_ENZ

Attached DMD Type bit 0

Attached DMD Type bit 1

Attached DMD Type bit 2

Attached DMD Type bit 3

Block Address bit 0

SCPDI

-

SCPCLK

SCPDO

-

SCPCLK

DMD_SCPENZ

DMD_TYPE_0

DMD_TYPE_1

DMD_TYPE_2

DMD_TYPE_3

BLKAD_0

Lo

Hi

SCPCLK

-

DDC_DCLK_[A,B,C,D]

BLKAD_1

Block Address bit 1

BLKAD_2

Block Address bit 2

BLKAD_3

Block Address bit 3

BLKMD_0

Block Mode Bit 0

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ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

H14

D14

D15

E15

F14

G14

E16

F15

G15

E17

F17

G16

H17

H16

B21

C21

A7

BLKMD_1

LVCMOS25_I

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NI

Hi

-

DDC_DCLK_[A,B,C,D]

Block Mode Bit 1

ROWAD_0

-

DMD Row Address bit 0

DMD Row Address bit 1

DMD Row Address bit 2

DMD Row Address bit 3

DMD Row Address bit 4

DMD Row Address bit 5

DMD Row Address bit 6

DMD Row Address bit 7

DMD Row Address bit 8

DMD Row Address bit 9

DMD Row Address bit 10

DMD Row Mode bit 0

DMD Row Mode bit 1

ROWAD_1

-

ROWAD_2

-

ROWAD_3

-

ROWAD_4

-

ROWAD_5

-

ROWAD_6

-

ROWAD_7

-

ROWAD_8

-

ROWAD_9

-

ROWAD_10

-

ROWMD_0

-

ROWMD_1

-

DDC_DCLK_A_DPN

DDC_DCLK_A_DPP

DDC_DCLK_B_DPN

DDC_DCLK_B_DPP

DDC_DCLK_C_DPN

DDC_DCLK_C_DPP

DDC_DCLK_D_DPN

DDC_DCLK_D_DPP

DDC_DCLKOUT_A_DPN

DDC_DCLKOUT_A_DPP

DDC_DCLKOUT_B_DPN

DDC_DCLKOUT_B_DPP

DDC_DCLKOUT_C_DPN

DDC_DCLKOUT_C_DPP

DDC_DCLKOUT_D_DPN

DDC_DCLKOUT_D_DPP

DDC_DIN_A0_DPN

-

Input Bus A Clock. 100-Ωexternal LVDS

termination required.

-

Input Bus B Clock. 100-Ωexternal LVDS

termination required.

B7

-

K20

K21

L5

-

Input Bus C Clock. 100-Ωexternal LVDS

termination required.

-

Input Bus D Clock. 100-Ωexternal LVDS

termination required.

K5

-

N1

-

Output Bus A Clock to DMD.

Output Bus B Clock to DMD.

Output Bus C Clock to DMD.

Output Bus D Clock to DMD.

M1

-

Y5

-

Y6

-

AA22

AB22

M26

M25

A15

-

DDC_DCLK_A

Input Bus A Data bit 0.

100-Ωexternal LVDS termination

required.

DDC_DIN_A0_DPP

DDC_DIN_A1_DPN

DDC_DIN_A1_DPP

DDC_DIN_A2_DPN

DDC_DIN_A2_DPP

DDC_DIN_A3_DPN

DDC_DIN_A3_DPP

DDC_DIN_A4_DPN

DDC_DIN_A4_DPP

DDC_DIN_A5_DPN

DDC_DIN_A5_DPP

DDC_DIN_A6_DPN

DDC_DIN_A6_DPP

DDC_DIN_A7_DPN

DDC_DIN_A7_DPP

DDC_DIN_A8_DPN

DDC_DIN_A8_DPP

DDC_DIN_A9_DPN

DDC_DIN_A9_DPP

DDC_DIN_A10_DPN

DDC_DIN_A10_DPP

A14

B14

C14

B16

B15

C16

D16

A17

B17

C17

D18

A19

A18

C18

B19

D19

C19

B20

A20

A22

B22

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

-

DDC_DCLK_A

Input Bus A Data bit 1.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 2.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 3.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 4.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 5.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 6.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 7.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 8.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 9.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 10.

100-Ωexternal LVDS termination

required.

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ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

DDC_DIN_A11_DPN

A24

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

-

DDC_DCLK_A

DDC_DCLK_B

DDC_DCLK_C

Input Bus A Data bit 11.

100-Ωexternal LVDS termination

required.

DDC_DIN_A11_DPP

DDC_DIN_A12_DPN

DDC_DIN_A12_DPP

DDC_DIN_A13_DPN

DDC_DIN_A13_DPP

DDC_DIN_A14_DPN

DDC_DIN_A14_DPP

DDC_DIN_A15_DPN

DDC_DIN_A15_DPP

DDC_DIN_B0_DPN

DDC_DIN_B0_DPP

DDC_DIN_B1_DPN

DDC_DIN_B1_DPP

DDC_DIN_B2_DPN

DDC_DIN_B2_DPP

DDC_DIN_B3_DPN

DDC_DIN_B3_DPP

DDC_DIN_B4_DPN

DDC_DIN_B4_DPP

DDC_DIN_B5_DPN

DDC_DIN_B5_DPP

DDC_DIN_B6_DPN

DDC_DIN_B6_DPP

DDC_DIN_B7_DPN

DDC_DIN_B7_DPP

DDC_DIN_B8_DPN

DDC_DIN_B8_DPP

DDC_DIN_B9_DPN

DDC_DIN_B9_DPP

DDC_DIN_B10_DPN

DDC_DIN_B10_DPP

DDC_DIN_B11_DPN

DDC_DIN_B11_DPP

DDC_DIN_B12_DPN

DDC_DIN_B12_DPP

DDC_DIN_B13_DPN

DDC_DIN_B13_DPP

DDC_DIN_B14_DPN

DDC_DIN_B14_DPP

DDC_DIN_B15_DPN

DDC_DIN_B15_DPP

DDC_DIN_C0_DPN

DDC_DIN_C0_DPP

DDC_DIN_C1_DPN

DDC_DIN_C1_DPP

DDC_DIN_C2_DPN

DDC_DIN_C2_DPP

A23

C23

B24

C24

D24

A25

B25

C26

B26

A12

A13

B12

C13

D10

D11

C12

C11

A10

B11

D9

Input Bus A Data bit 12.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 13.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 14.

100-Ωexternal LVDS termination

required.

Input Bus A Data bit 15.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 0.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 1.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 2.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 3.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 4.

100-Ωexternal LVDS termination

required.

Input Bus B Data bit 5.

100-Ωexternal LVDS termination

required.

C9

B10

B9

Input Bus B Data bit 6.

100-Ωexternal LVDS termination

required.

A8

Input Bus B Data bit 7.

100-Ωexternal LVDS termination

required.

A9

D6

Input Bus B Data bit 8.

100-Ωexternal LVDS termination

required.

D5

C7

Input Bus B Data bit 9.

100-Ωexternal LVDS termination

required.

C6

B6

Input Bus B Data bit 10.

100-Ωexternal LVDS termination

required.

B5

D4

Input Bus B Data bit 11.

100-Ωexternal LVDS termination

required.

D3

B4

Input Bus B Data bit 12.

100-Ωexternal LVDS termination

required.

C4

C3

Input Bus B Data bit 13.

100-Ωexternal LVDS termination

required.

C2

A3

Input Bus B Data bit 14.

100-Ωexternal LVDS termination

required.

A2

B2

Input Bus B Data bit 15.

100-Ωexternal LVDS termination

required.

B1

E20

E21

F20

G20

H19

J19

Input Bus C Data bit 0.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 1.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 2.

100-Ωexternal LVDS termination

required.

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

DDC_DIN_C3_DPN

E23

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

-

DDC_DCLK_C

DDC_DCLK_D

Input Bus C Data bit 3.

100-Ωexternal LVDS termination

required.

DDC_DIN_C3_DPP

DDC_DIN_C4_DPN

DDC_DIN_C4_DPP

DDC_DIN_C5_DPN

DDC_DIN_C5_DPP

DDC_DIN_C6_DPN

DDC_DIN_C6_DPP

DDC_DIN_C7_DPN

DDC_DIN_C7_DPP

DDC_DIN_C8_DPN

DDC_DIN_C8_DPP

DDC_DIN_C9_DPN

DDC_DIN_C9_DPP

DDC_DIN_C10_DPN

DDC_DIN_C10_DPP

DDC_DIN_C11_DPN

DDC_DIN_C11_DPP

DDC_DIN_C12_DPN

DDC_DIN_C12_DPP

DDC_DIN_C13_DPN

DDC_DIN_C13_DPP

DDC_DIN_C14_DPN

DDC_DIN_C14_DPP

DDC_DIN_C15_DPN

DDC_DIN_C15_DPP

DDC_DIN_D0_DPN

DDC_DIN_D0_DPP

DDC_DIN_D1_DPN

DDC_DIN_D1_DPP

DDC_DIN_D2_DPN

DDC_DIN_D2_DPP

DDC_DIN_D3_DPN

DDC_DIN_D3_DPP

DDC_DIN_D4_DPN

DDC_DIN_D4_DPP

DDC_DIN_D5_DPN

DDC_DIN_D5_DPP

DDC_DIN_D6_DPN

DDC_DIN_D6_DPP

DDC_DIN_D7_DPN

DDC_DIN_D7_DPP

DDC_DIN_D8_DPN

DDC_DIN_D8_DPP

DDC_DIN_D9_DPN

DDC_DIN_D9_DPP

DDC_DIN_D10_DPN

DDC_DIN_D10_DPP

E22

F23

F22

G22

G21

J20

J21

H22

H21

J23

H23

K22

K23

M19

M20

M21

M22

N19

P19

N21

N22

P20

P21

N23

P23

T3

Input Bus C Data bit 4.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 5.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 6.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 7.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 8.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 9.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 10.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 11.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 12.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 13.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 14.

100-Ωexternal LVDS termination

required.

Input Bus C Data bit 15.

100-Ωexternal LVDS termination

required.

Input Bus D Data bit 0.

100-Ωexternal LVDS termination

required.

R3

R5

Input Bus D Data bit 1.

100-Ωexternal LVDS termination

required.

R6

R7

Input Bus D Data bit 2.

100-Ωexternal LVDS termination

required.

P6

N3

Input Bus D Data bit 3.

100-Ωexternal LVDS termination

required.

P3

P4

Input Bus D Data bit 4.

100-Ωexternal LVDS termination

required.

P5

N6

Input Bus D Data bit 5.

100-Ωexternal LVDS termination

required.

N7

N4

Input Bus D Data bit 6.

100-Ωexternal LVDS termination

required.

M4

M7

Input Bus D Data bit 7.

100-Ωexternal LVDS termination

required.

L7

K7

Input Bus D Data bit 8.

100-Ωexternal LVDS termination

required.

K6

J4

Input Bus D Data bit 9.

100-Ωexternal LVDS termination

required.

J5

H7

Input Bus D Data bit 10.

100-Ωexternal LVDS termination

required.

J6

8

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

DDC_DIN_D11_DPN

G4

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

-

DDC_DCLK_D

Input Bus D Data bit 11.

100-Ωexternal LVDS termination

required.

DDC_DIN_D11_DPP

DDC_DIN_D12_DPN

DDC_DIN_D12_DPP

DDC_DIN_D13_DPN

DDC_DIN_D13_DPP

DDC_DIN_D14_DPN

DDC_DIN_D14_DPP

DDC_DIN_D15_DPN

DDC_DIN_D15_DPP

H4

G5

H6

G7

G6

F4

F5

E5

E6

Input Bus D Data bit 12.

100-Ωexternal LVDS termination

required.

Input Bus D Data bit 13.

100-Ωexternal LVDS termination

required.

Input Bus D Data bit 14.

100-Ωexternal LVDS termination

required.

Input Bus D Data bit 15.

100-Ωexternal LVDS termination

required.

DDC_DOUT_A0_DPN

DDC_DOUT_A0_DPP

DDC_DOUT_A1_DPN

DDC_DOUT_A1_DPP

DDC_DOUT_A2_DPN

DDC_DOUT_A2_DPP

DDC_DOUT_A3_DPN

DDC_DOUT_A3_DPP

DDC_DOUT_A4_DPN

DDC_DOUT_A4_DPP

DDC_DOUT_A5_DPN

DDC_DOUT_A5_DPP

DDC_DOUT_A6_DPN

DDC_DOUT_A6_DPP

DDC_DOUT_A7_DPN

DDC_DOUT_A7_DPP

DDC_DOUT_A8_DPN

DDC_DOUT_A8_DPP

DDC_DOUT_A9_DPN

DDC_DOUT_A9_DPP

DDC_DOUT_A10_DPN

DDC_DOUT_A10_DPP

DDC_DOUT_A11_DPN

DDC_DOUT_A11_DPP

DDC_DOUT_A12_DPN

DDC_DOUT_A12_DPP

DDC_DOUT_A13_DPN

DDC_DOUT_A13_DPP

DDC_DOUT_A14_DPN

DDC_DOUT_A14_DPP

DDC_DOUT_A15_DPN

DDC_DOUT_A15_DPP

DDC_DOUT_B0_DPN

DDC_DOUT_B0_DPP

DDC_DOUT_B1_DPN

DDC_DOUT_B1_DPP

DDC_DOUT_B2_DPN

DDC_DOUT_B2_DPP

DDC_DOUT_B3_DPN

DDC_DOUT_B3_DPP

DDC_DOUT_B4_DPN

DDC_DOUT_B4_DPP

DDC_DOUT_B5_DPN

DDC_DOUT_B5_DPP

AE2

AF2

AD1

AE1

AC1

AC2

AB1

AB2

Y2

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

-

DDC_DCLKOUT_A

DDC_DCLKOUT_B

Output Bus A Data bit 0 to DMD.

Output Bus A Data bit 1 to DMD.

Output Bus A Data bit 2 to DMD.

Output Bus A Data bit 3 to DMD.

Output Bus A Data bit 4 to DMD.

Output Bus A Data bit 5 to DMD.

Output Bus A Data bit 6 to DMD.

Output Bus A Data bit 7 to DMD.

Output Bus A Data bit 8 to DMD.

Output Bus A Data bit 9 to DMD.

Output Bus A Data bit 10 to DMD.

Output Bus A Data bit 11 to DMD.

Output Bus A Data bit 12 to DMD.

Output Bus A Data bit 13 to DMD.

Output Bus A Data bit 14 to DMD.

Output Bus A Data bit 15 to DMD.

Output Bus B Data bit 0 to DMD.

Output Bus B Data bit 1 to DMD.

Output Bus B Data bit 2 to DMD.

Output Bus B Data bit 3 to DMD.

Output Bus B Data bit 4 to DMD.

Output Bus B Data bit 5 to DMD.

AA2

W1

Y1

V1

V2

U1

U2

R2

T2

N2

M2

K1

L2

K2

K3

J3

H3

H2

J1

H1

G1

G2

F2

AE5

AE6

AD3

AD4

AD5

AD6

AC3

AC4

AB5

AB6

AB7

AC6

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

AA5

AA4

AA7

Y7

DDC_DOUT_B6_DPN

DDC_DOUT_B6_DPP

DDC_DOUT_B7_DPN

DDC_DOUT_B7_DPP

DDC_DOUT_B8_DPN

DDC_DOUT_B8_DPP

DDC_DOUT_B9_DPN

DDC_DOUT_B9_DPP

DDC_DOUT_B10_DPN

DDC_DOUT_B10_DPP

DDC_DOUT_B11_DPN

DDC_DOUT_B11_DPP

DDC_DOUT_B12_DPN

DDC_DOUT_B12_DPP

DDC_DOUT_B13_DPN

DDC_DOUT_B13_DPP

DDC_DOUT_B14_DPN

DDC_DOUT_B14_DPP

DDC_DOUT_B15_DPN

DDC_DOUT_B15_DPP

DDC_DOUT_C0_DPN

DDC_DOUT_C0_DPP

DDC_DOUT_C1_DPN

DDC_DOUT_C1_DPP

DDC_DOUT_C2_DPN

DDC_DOUT_C2_DPP

DDC_DOUT_C3_DPN

DDC_DOUT_C3_DPP

DDC_DOUT_C4_DPN

DDC_DOUT_C4_DPP

DDC_DOUT_C5_DPN

DDC_DOUT_C5_DPP

DDC_DOUT_C6_DPN

DDC_DOUT_C6_DPP

DDC_DOUT_C7_DPN

DDC_DOUT_C7_DPP

DDC_DOUT_C8_DPN

DDC_DOUT_C8_DPP

DDC_DOUT_C9_DPN

DDC_DOUT_C9_DPP

DDC_DOUT_C10_DPN

DDC_DOUT_C10_DPP

DDC_DOUT_C11_DPN

DDC_DOUT_C11_DPP

DDC_DOUT_C12_DPN

DDC_DOUT_C12_DPP

DDC_DOUT_C13_DPN

DDC_DOUT_C13_DPP

DDC_DOUT_C14_DPN

DDC_DOUT_C14_DPP

DDC_DOUT_C15_DPN

DDC_DOUT_C15_DPP

DDC_DOUT_D0_DPN

DDC_DOUT_D0_DPP

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

-

DDC_DCLKOUT_B

DDC_DCLKOUT_C

DDC_DCLKOUT_D

Output Bus B Data bit 6 to DMD.

Output Bus B Data bit 7 to DMD.

Output Bus B Data bit 8 to DMD.

Output Bus B Data bit 9 to DMD.

Output Bus B Data bit 10 to DMD.

Output Bus B Data bit 11 to DMD.

Output Bus B Data bit 12 to DMD.

Output Bus B Data bit 13 to DMD.

Output Bus B Data bit 14 to DMD.

Output Bus B Data bit 15 to DMD.

Output Bus C Data bit 0 to DMD.

Output Bus C Data bit 1 to DMD.

Output Bus C Data bit 2 to DMD.

Output Bus C Data bit 3 to DMD.

Output Bus C Data bit 4 to DMD.

Output Bus C Data bit 5 to DMD.

Output Bus C Data bit 6 to DMD.

Output Bus C Data bit 7 to DMD.

Output Bus C Data bit 8 to DMD.

Output Bus C Data bit 9 to DMD.

Output Bus C Data bit 10 to DMD.

Output Bus C Data bit 11 to DMD.

Output Bus C Data bit 12 to DMD.

Output Bus C Data bit 13 to DMD.

Output Bus C Data bit 14 to DMD.

Output Bus C Data bit 15 to DMD.

Output Bus D Data bit 0 to DMD.

Y3

W3

W4

V4

W6

W5

V7

V6

U4

V3

T4

T5

U6

U5

U7

T7

T22

T23

R20

R21

T19

T20

U21

U22

U20

U19

V23

V24

V22

V21

W19

V19

W23

W24

Y22

Y23

Y20

Y21

AA24

AA23

AA19

AA20

AC24

AB24

AC19

AD19

AC22

AC23

AB26

AC26

10

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

AA25

AB25

Y26

Y25

W26

W25

U26

V26

U25

U24

T25

T24

R26

R25

P24

P25

N24

M24

L25

L24

K26

K25

J26

DDC_DOUT_D1_DPN

DDC_DOUT_D1_DPP

DDC_DOUT_D2_DPN

DDC_DOUT_D2_DPP

DDC_DOUT_D3_DPN

DDC_DOUT_D3_DPP

DDC_DOUT_D4_DPN

DDC_DOUT_D4_DPP

DDC_DOUT_D5_DPN

DDC_DOUT_D5_DPP

DDC_DOUT_D6_DPN

DDC_DOUT_D6_DPP

DDC_DOUT_D7_DPN

DDC_DOUT_D7_DPP

DDC_DOUT_D8_DPN

DDC_DOUT_D8_DPP

DDC_DOUT_D9_DPN

DDC_DOUT_D9_DPP

DDC_DOUT_D10_DPN

DDC_DOUT_D10_DPP

DDC_DOUT_D11_DPN

DDC_DOUT_D11_DPP

DDC_DOUT_D12_DPN

DDC_DOUT_D12_DPP

DDC_DOUT_D13_DPN

DDC_DOUT_D13_DPP

DDC_DOUT_D14_DPN

DDC_DOUT_D14_DPP

DDC_DOUT_D15_DPN

DDC_DOUT_D15_DPP

DDC_SCTRL_AN

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NO

LVDS_25_PO

LVDS_25_NI

-

DDC_DCLKOUT_D

DDC_DCLKOUT_A

DDC_DCLKOUT_B

DDC_DCLKOUT_C

DDC_DCLKOUT_D

DDC_DCLK_A

Output Bus D Data bit 1 to DMD.

Output Bus D Data bit 2 to DMD.

Output Bus D Data bit 3 to DMD.

Output Bus D Data bit 4 to DMD.

Output Bus D Data bit 5 to DMD.

Output Bus D Data bit 6 to DMD.

Output Bus D Data bit 7 to DMD.

Output Bus D Data bit 8 to DMD.

Output Bus D Data bit 9 to DMD.

Output Bus D Data bit 10 to DMD.

Output Bus D Data bit 11 to DMD.

Output Bus D Data bit 12 to DMD.

Output Bus D Data bit 13 to DMD.

Output Bus D Data bit 14 to DMD.

Output Bus D Data bit 15 to DMD.

Output Bus A Serial Control to DMD.

Output Bus B Serial Control to DMD.

Output Bus C Serial Control to DMD.

Output Bus D Serial Control to DMD.

J25

J24

H24

H26

G26

G25

G24

R1

DDC_SCTRL_AP

P1

DDC_SCTRL_BN

AA3

AB4

W20

W21

N26

P26

D20

DDC_SCTRL_BP

DDC_SCTRL_CN

DDC_SCTRL_CP

DDC_SCTRL_DN

DDC_SCTRL_DP

DVALID_A_DPN

Input Bus A Data Valid Signal.

100-Ωexternal LVDS termination

required.

DVALID_A_DPP

DVALID_B_DPN

DVALID_B_DPP

DVALID_C_DPN

DVALID_C_DPP

DVALID_D_DPN

DVALID_D_DPP

D21

C8

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

LVDS_25_NI

LVDS_25_PI

-

DDC_DCLK_A

DDC_DCLK_B

DDC_DCLK_C

DDC_DCLK_D

Input Bus B Data Valid Signal.

100-Ωexternal LVDS termination

required.

D8

L19

L20

L3

Input Bus C Data Valid Signal.

100-Ωexternal LVDS termination

required.

Input Bus D Data Valid Signal.

100-Ωexternal LVDS termination

required.

L4

DDC_VERSION_0

DDC_VERSION_1

DDC_VERSION_2

SPEED_SEL_0

F18

G17

H18

H8

LVCMOS25_O

LVCMOS25_I

Hi

-

DLPC910 Firmware Rev Number bit 0

DLPC910 Firmware Rev Number bit 1

DLPC910 Firmware Rev Number bit 2

SPEED_SEL[1:0]

= 00 400MHz

= 01 480MHz

= 10, 11 Reserved Includes internal pull-

ups. SPEED_SEL[1:0] must be set to 00

when connecting the DLPC910 with a

DLP6500.

SPEED_SEL_1

H9

LVCMOS25_I

Hi

-

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

Reserved. Do not connect. Includes

internal pull-up.

VSP_ENABLE

E8

LVCMOS25_I

LVCMOS25_O

Hi

-

DLPR910 Initialization complete.

Connected to LED.

ECP2_FINISHED

E25

VLED0

VLED1

AA17

AB17

LVCMOS25_O

Hi = On

-

Power Indicator LED Output.

Heartbeat Indicator LED Output.

DMD Reset Pulse Watchdog Timer

Enable

WDT_ENBLZ

F25

LVCMOS25_I

Lo

-

PWR_FLOAT

NS_FLIP

G9

LVCMOS25_I

LVCMOS25_O

LVCMOS25_I

Hi

-

Park DMD mirrors.

F19

G19

E26

G10

E18

-

Top/Bottom image flip on DMD

Compliment Data (0 <--> 1)

COMP_DATA

INIT_ACTIVE

RST_ACTIVE

RST2BLKZ

DDC_DCLK_[A,B,C,D]

-

DLPC910 Initialization Routine Active

DMD Mirror Clocking Pulse in progress

Dual and Quad Block control

No connect. For access to test point

output route to test via.

TST_PT_0

Y12

AA12

Y13

AA13

AA14

AB14

AA15

AB15

C1

LVCMOS33_O

LVCMOS25_O

DCI Reference Voltage

LVCMOS25_I

-

No connect. For access to test point

output route to test via.

TST_PT_1

No connect. For access to test point

output route to test via.

TST_PT_2

-

No connect. For access to test point

output route to test via.

TST_PT_3

-

No connect. For access to test point

output route to test via.

TST_PT_4

-

No connect. For access to test point

output route to test via.

TST_PT_5

-

No connect. For access to test point

output route to test via.

TST_PT_6

-

No connect. For access to test point

output route to test via.

TST_PT_7

-

No connect. For access to test point

output route to test via.

TST_PT_8

-

No connect. For access to test point

output route to test via.

TST_PT_9

D1

-

No connect. For access to test point

output route to test via.

TST_PT_10

TST_PT_11

TST_PT_12

TST_PT_13

TST_PT_14

TST_PT_15

DLPC_VRN_BANK4

DLPC_VRP_BANK4

LOAD4_ENZ

DMD_IRQ

E1

-

No connect. For access to test point

output route to test via.

E2

-

No connect. For access to test point

output route to test via.

E3

-

No connect. For access to test point

output route to test via.

F3

-

No connect. For access to test point

output route to test via.

E7

-

No connect. For access to test point

output route to test via.

F7

-

Requires an external 49.9-Ωpull-up

resistor to 3.3 V.

AB12

AC11

D25

D26

K18

-

Requires an external 49.9-Ωpull-down

resistor to GND.

-

Signal enables the Load-4 functionality of

the DMD. Includes internal pull-up.

Lo

Hi

-

Signal indicates a DMD voltage is

inactive. Includes internal pull-up

LVCMOS25_O

LVCMOS33_I

DLPC910 VBATT reference. Connect to

GND.

DLPC_VBATT

DLPC910 Initialization configuration

complete. Connect to DLPR910 CEZ pin.

Requires 4.7-kΩpull-up to 3.3 V.

DLPC_DONE

K10

L18

LVCOMS33_O

LVCMOS33_I

-

DLPC910 Configuration. Requires 4.7-

kΩpull-up to 3.3 V.

DLPC_HSWAPEN

DDC_M0

DDC_M1

DDC_M2

W18

Y17

V18

LVCMOS33_I

-

DLPC910 Configuration. Connect to GND

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ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

DLPC910 Configuration. Connect to

DLPR910 OE/RESET. Requires 4.7-kΩ

pull-up to 3.3 V.

INTB_DDC

J11

LVCMOS25_O

Hi

-

DLPC910 Configuration. Connect to

DLPR910 CF. Requires 4.7-kΩpull-up

to 3.3 V.

PROGB_DDC

J18

J10

LVCMOS25_O

-

Configuration PROM Clock. Connect to

DLPR910 CLK. Connects to center of

voltage divider (100/100-Ω3.3 V and

GND).

PROM_CCK_DDC

-

PROM_CCK_DDC

Configuration PROM Data in. Connected

to DLPR910 Data 0 (D0)

PROM_D0_DDC

DLPC_DOUTBUSY

RDWR_B

K11

W11

P18

LVCMOS25_I

-

PROM_CCK_DDC

Configuration PROM Busy. Connect to

test via for debug only.

-

DLPC910 Configuration. Requires 1-kΩ

pull-down to ground.

JTAG Clock. Connects to DLPC910,

DLPR910, and JTAG header TCK (if user

has JTAG they must build their chain

accordingly)

TCK_JTAG

U11

LVCMOS33_I

-

TCK_JTAG

JTAG Data out of DLPC910. Connects to

JTAG return TDO on JTAG header

TDO_DDC

W10

V11

LVCMOS33_O

LVCMOS33_I

-

TCK_JTAG

JTAG Data out of DLPR910 to DLPC910.

Connects to DLPR910 TDO (DLPC910

internal signal TDI_0)

TDO_XCF16DDC

JTAG. Connects to DLPC910, DLPR910,

and JTAG

TMS_JTAG

VCCAUX

V12

LVCMOS33_I

PWR

Hi

-

TCK_JTAG

-

header TMS

J8, K17, L8, M17, N8, P17,

R8, T17, U8, V17, W8, W16

Aux Power. VCC_2P5V

H15, J12, J14, J16, K9, K13,

K15, L10, L12, L14, L16, M9,

M11, M15, N10, N12, N16,

P9, P11, P15, R10, R12,

R16, T9, T11, T13, T15, U10,

U12, U14, U16, V9, V13,

V15, W14, Y15

VCCINT

PWR

-

Power. VCC_1P0V

Power. VCC_3P3V

VCCO_0

VCCO_2

VCCO_4

VCCO_1

VCCO_3

VCCO_11

VCCO_12

VCCO_13

VCCO_14

VCCO_15

VCCO_16

VCCO_17

VCCO_18

VCCO_21

Y9, W12

AA16, AD17

AB13, AC10

C10, F11

PWR

-

D17, E14

F21, H25, J22

H5, J2, L6

M23, N20, R24

R4, V5, W2

Power. VCC_2P5V

B23,C20, E24

D7, E4, G8

T21, V25, W22

AA6, AB3, AD7

AC20, AB23, AE24

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ACTIVE

(HI OR LO)

I/O TYPE

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

A1, A6, A11, A16, A21, A26,

AA1, AA11, AA21, AA26,

AB8, AB18, AC5, AC15,

AC25, AD2, AD12, AD22,

AE4, AE9, AE14, AE19, AF1,

AF6, AF11, AF16, AF21,

AF26, B3, B8, B13, B18, C5,

C15, C25, D2, D12, D22, E9,

E19, F1, F6, F16, F26, G3,

G13, G18, G23, H10, H20,

J7, J9, J13, J15, J17, K4, K8,

K12, K14, K16, K19, K24,

L1, L9, L11, L13, L15, L17,

L21, L26, M3, M8, M10,

GND

-

M12, M16, M18, N5, N9,

N11, N15, N17, N25, P2, P7,

P8, P10, P12, P16, P22, R9,

R11, R15, R17, R19, T1, T6,

T8, T10, T12, T14, T16, T26,

U3, U9, U13, U15, U17, U18,

U23, V8, V10, V14, V16,

V20, W7, W9, W13, W15,

W17, Y4, Y14, Y16, Y19,

Y24, M13, M14, N13, N14,

P13, P14, R13, R14, N18,

R18, T18

RESERVED_AC12

RESERVED_AD11

RESERVED_AA9

RESERVED_Y10

RESERVED_Y11

RESERVED_AB11

RESERVED_F10

RESERVED_F8

AC12

AD11

AA9

Y10

Y11

LVCMOS33_O

LVCMOS33_I

-

Route to via for access to pin output.

Includes internal pull-up

AB11

F10

Includes internal pull-up

F8

Includes internal pull-up

A4, A5, AA18, AB16, AB19,

AB20, AB21, AC21, AD9,

AD16, AD20, AD21, AD23,

AD24, AD25, AD26, AE3,

AE7, AE8, AE10, AE11,

AE12, AE13, AE15, AE16,

AE17, AE18, AE20, AE21,

AE22, AE23, AE25, AE26,

AF3, AF4, AF5, AF7, AF8,

AF9, AF10, AF12, AF13,

AF14, AF15, AF17, AF18,

AF19, AF20, AF22, AF23,

AF24, AF25, C22, D23, E11,

F12, F24, L22, L23, M5, M6,

R22, R23, Y18

No Connection.

Unused Pins.

UNUSED

NC

-

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6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

MIN

MAX

UNIT

ELECTRICAL

V_CCINT

1.1

3.75

–0.50

–0.95

–0.75

–0.30

V_CCO

Supply voltage range ⁽²⁾

V

V_CCAUX

3.0

3.3 V

2.5 V

3.3 V

2.5 V

4.05

V_I

Input voltage range ⁽³⁾

Output voltage range ⁽⁴⁾

V

V_CCO+ 0.50

V

_CCO–0.40

V_O

V

ENVIRONMENTAL

T_J

Junction temperature

Storage temperature (ambient)

125

150

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to GND.

(3) Applies to external input and bidirectional buffers.

(4) Applies to external output and bidirectional buffers.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001-2010, all pins ⁽¹⁾

+ 2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins ⁽²⁾

+ 400

(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM

allows safe manufacturing with a standard ESD control process.

(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

ELECTRICAL

V_CCINT1-V supply voltage, core logic

0.95

1.14

3.0

1.00

2.50

1.05

3.45

V

V_CCO

2.5-V supply voltage, I/O for VCCO_1,3,11,12,13,14,15,16,17,18,21

3.3-V supply voltage, I/O for VCCO_0,2,4

3.30

3.45

V_CCAUX2.5-V supply voltage, I/O

3.3-V DCI and CMOS for VCCO_0,2,4

2.375

0

2.500

2.625

V_CCO

2. 5-V CMOS for

VCCO_1,3,11,12,13,14,15,16,17,18,21

V_I

Input voltage

0

V_CCO

V

2.5-V LVDS

0.3

0

2.2

3.3-V DCI and CMOS for VCCO_0,2,4

V_CCO

2.5-V CMOS for

VCCO_1,3,11,12,13,14,15,16,17,18,21

V_O

Output voltage

0

V_CCO

1.675

2.5-V LVDS

0.825

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

T_A

Operating ambient temperature

0

85

°C

ENVIRONMENTAL

P_D

Continuous total power dissipation

6

W

6.4 Thermal Information

DLPC910

ZYR (FCBGA)

676 PINS

12.1

THERMAL METRIC ⁽¹⁾

UNIT

R_θJA

R_θJC

R_θJB

Junction-to-ambient thermal resistance ⁽²⁾

Junction-to-case thermal resistance

Junction-to-board thermal resistance

°C/W

3.2

0.19

(1) Refer to the XC5VLX30 product specifications at www.xilinx.com for complete thermal specifications.

(2) In still air.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

V_IH

V_IL

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

3.3-V CMOS

2.0

V

3.3-V CMOS

0.8

0.4

0.7

V

V_OH

V_OL

V_IH

V_IL

3.3-V DCI and CMOS

2.5-V CMOS

2.9

1.7

2.5-V CMOS

V_CCO

–

2.5-V interface

0.4

V_OH

High-level output voltage

V

2.5-V LVDS

2.5-V interface

2.5-V LVDS

2.5-V interface

2.5-V LVDS

1.38

0.4

V_OL

Low-level output voltage

Input capacitance

V

1.03

8

C_I

pF

8

I_CCINT

1V Supply voltage range, core supply

2.5V Supply voltage range, I/O supply

3.3V Supply voltage range, I/O supply

1430

2100

2300

180

mA

I_CCO

+

1650

I_CCAUX

I_CCO

6.6 Timing Requirements

(see ⁽¹⁾

)

MIN

NOM

MAX

UNIT

f_cd

Clock frequency, DCLKIN_n ⁽²⁾

400

480

MHz

f_cr

t_c

Clock frequency, CLK_R

Cycle time, DCLKIN_n

50

MHz

ns

f_cd= 400 MHz

f_cd= 480 MHz

f_cd= 400 MHz

f_cd= 480 MHz

2.5

2.083

1.25

t_w(H)

Pulse duration, high

50% to 50% reference

points (signal)

ns

1.042

16

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(see ⁽¹⁾

)

MIN

NOM

MAX

1.25

1.042

0.6

UNIT

t_w(L)

Pulse duration, low

50% to 50% reference

points (signal)

f_cd= 400 MHz

f_cd= 480 MHz

f_cd= 400 MHz

f_cd= 480 MHz

ns

t_t

Transition time, tt = tf /tr

20% to 80% reference

points (signal)

ns

ps

0.5

t_jp

Period Jitter DCLKIN_n ⁽³⁾

100

Skew, DIN_A(15-0) to DCLKIN_A

Skew, DIN_B(15-0) to DCLKIN_B

Skew, DIN_C(15-0) to DCLKIN_C

Skew, DIN_D(15-0) to DCLKIN_D

Skew, DVALID_n to DCLKIN_n↑

-100

100

t_sk

ps

Skew, BLKMD BLKAD to

DCLKIN_n↑⁽⁴⁾

Skew, ROWMD or ROWAD to

-100

100

DCLKIN_n↑⁽⁴⁾

Skew, STEPVCC to DCLKIN↑⁽⁴⁾

(1) It is recommended that the COMP_DATA, NS_FLIP and RST2BLK flags be set to one value and not adjusted during normal system

operation.

(2) Preferred DDC_DCLK _n duty cycle = 50%

(3) This is the deviation in period from ideal period due solely to high frequency jitter.

(4) First edge of DDC_DIN*, ROW*, and BLK* should be synchronous to DVALID rising edge.

t_sk

t_t

t_c

t_w(H)

50%

t_w(L)

50%

Cycle 1

80%

20%

DCLKIN

DVALID

50%

Cycle#CLKS/

ROW

DDR Data

Control

图6-1. Input Interface Timing

备注

Dynamic changes to RST2BLK, NS_FLIP and COMP_DATA during normal operation are not

recommended.

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7 Detailed Description

7.1 Overview

The DLPC910 digital controller provides a reliable high speed data pipe to the DMD, where the digital input on

the LVDS interface is configured for the required timing requirements of the DMD. The DMD reflects light by

using 1-bit binary encoded patterns, where each mirror is a pixel-to-mirror mapping of the pattern.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input LVDS Interface

The data input interface consists of four input data buses: DDC_DIN_A, DDC_DIN_B, DDC_DIN_C, and

DDC_DIN_D. Each bus contains 16 differential pairs which are synchronous to the rising and falling edges of its

associated DDC_DCLK signal.

7.3.2 Data Clock

The data clock interface consists of four differential pairs: DDC_DCLK_A, DDC_DCLK_B, DDC_DCLK_C, and

DDC_DCLK_D. Each must operate continuously. All signals associated with the data clock should be

synchronous to these signals. For example, DDC_DIN_A and DVALID_A should be synchronous to the rising

edge of DDC_DCLK_A. This clock should be valid prior to releasing CTRL_RSTZ. DDC_DCLK is a DDR clock

with data loaded on both rising and falling edges of DDC_DCLK. The jitter on this clock is specified in Timing

Requirements. When connecting the DLPC910 with a DLP6500, SPEED_SEL[1:0] inputs must be set to

"00".

7.3.3 Data Valid

The data valid interface consists of four differential pairs: DVALID_A, DVALID _B, DVALID _C, and DVALID _D.

The DVALID signal should be asserted synchronous to the data it is meant to frame. DVALID can be asserted

as:

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• Framing individual row loads with breaks between rows, or

• Framing block loads - for example, the DLP9000X/DLP9000XUV with 16 blocks allows framing 100

contiguous row loads, or

• Framing the entire DMD load where the DVALID stays active for all DMD row loads with zero invalid data

between rows.

If the DVALID frames DMD blocks or the entire DMD, assure that the block and row control signals are adjusted

at the proper locations in the data stream. Refer to Block Mode Operation for further information.

7.3.4 Interface Training

The DLPC910 detects the phase differences between the ½ speed clock (used in the device driving the LVDS

data) and the internally generated ½ speed data clocks to select a clock phase for data capture. This is done by

supplying a simple repeating pattern on all of the data inputs while the INIT_ACTIVE output of the DLPC910 is

high/active. The details of the training pattern are described below.

图7-1 shows a simple block diagram of the training pattern insertion logic.

Sys Clk

IO Clk

System Data

0

1

4:1 Serdes

Dout

Training Data

(0100)

Din 3:0

INIT_ACTIVE

图7-1. Block Diagram of Training Pattern Logic

The expected training pattern is 0100. In 图7-2, the data input to the 4:1 SERDES cells is captured on the rising

edge of the ½ speed system clock. The output latency shown is based on the documentation for the Xilinx

SERDES cells. Individual implementation may vary depending on the type of cells, technology, and design

technique used.

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½ Speed

System CLK

Full Speed

IO CLK

4:1

SERDES Data

(at the interface)

0100

Output Data

图7-2. Training Pattern Alignment

备注

In Xilinx FPGAs (due to the construction of the ISERDES and OSERDES cells) a pattern of 0010

needs to be applied to the output/transmitting SERDES cells data pins (D1 = 0, D2 = 0, D3 = 1, D4 =

0) in order to receive a result of 0100 (Q1 = 0, Q2 = 1, Q3 = 0, Q4 = 0) at the input/receiving SERDES

cell.

The patterns should be applied on all of the data and DVALID pins. In this respect, the interface is treated as a

17 bit interface with DVALID being the 17th data bit. The receiving logic in the DLPC910 adjusts the clock phase

until the correct pattern is seen at the inputs. This allows DLPC910 to correctly select a clock phase for data

capture and will contribute to a more robust interface. It is important that the training pattern is applied to the

DVALID and data inputs of the DLPC910 before reset to the device is de-asserted, as training commences

immediately on the de-assertion of reset. The INIT_ACTIVE signal is asserted while the device is held in reset in

order to help facilitate this behavior.

7.3.5 Row and Block Interface

7.3.5.1 Row Mode

The DMD incorporates single row write operations using a row address counter that is randomly addressable.

ROWMD(1:0) determines the single row write count mode and ROWAD(10:0) determines the single row write

address. ROWMD and ROWAD must be asserted and de-asserted synchronously with DVALID. Row address

orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to Related

Documentation for the DMD datasheet regarding orientation of rows, columns, and Mirror Clocking Pulse (MCP)

blocks. The row address counter does not automatically wrap-around when using the increment row address

pointer instruction. After the final row is addressed, the row address pointer must be cleared to 0.

7.3.5.2 Block Mode

The signals RST2BLKZ, BLKMD and BLKAD are used to designate which mirror block(s) is to be issued a MCP

or a Block Clear.

7.3.6 Control Interface

7.3.6.1 Complement Data

By setting the COMP_DATA input high (logic 1), the user is able to command the DMD to internally complement

its data inputs prior to loading the data into the mirror array. At least 0.6 ms is needed for the signal to be loaded.

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This signal should not be used to invert data on a row basis. When used with the Clear command, the mirrors

are still set to zero regardless of the COMP_DATA bit. The COMP_DATA signal should be kept low during

initialization to ensure proper setup of the system.

7.3.6.2 North South Flip

The NS_FLIP signal allows the user to specify the loading direction of rows in the DMD when used with ROWMD

= 01. This control has no effect if ROWMD = 10. 表 7-1 and 表 7-2 describe the effect of N/S flip. If NS_FLIP is

set, this does not reverse the direction of MCP groups. For example, the normal case is to MCP blocks 0 – 15

in order. When NS_FLIP is set, the order of block MCPs must be reversed to 15 – 0. The NS_FLIP signal

should be kept low during initialization to ensure proper setup of the system.

表7-1. Row Write Modes - N/S Flip Flag = 0

ROWM

ROWAD

D

ACTION

1

0

10

9

8

7

6

5

4

3

2

1

0

None

Increment row address pointer and write

the concurrent data into that row

0

1

0

Set row address pointer to R and write the

concurrent data into that row.

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Clear row address pointer to 0 and write

concurrent data into first row

(that is, row 0).

1

0

表7-2. Row Write Modes - N/S Flip Flag = 1

ROWM

D

ROWAD

ACTION

1

0

10

9

8

7

6

5

4

3

2

1

0

None

Decrement the row address pointer and

write the concurrent data into that row

0

1

0

Set the row address pointer to R and write

the concurrent data into that row.

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Set row address pointer to row = last row

and write concurrent data into last row

(that is, the last row = 1599 or 1079).

1

0

7.3.6.3 Watchdog

The DLPC910 contains a watchdog timer that initiates a global DMD MCP in the event that any DMD reset block

has not received a MCP within 10 seconds. This auto-MCP function can be disabled by asserting WDT_ENBLZ

high. Disabling the watchdog is not recommended unless the user ensures that a MCP to the entire DMD occurs

within 10 seconds. During the time when the DLPC910 is in idle mode or is not operating, it is recommended to

exercise the DMD mirrors by continuously loading alternating all-on/all-off patterns.

7.3.6.4 DMD Mirror Float

To avoid leaving a static image on the DMD without removing power, a mirror FLOAT operation can be issued to

the DMD. A mirror FLOAT sequence begins by asserting the proper BLKMD and BLKAD as described in 表

7-12. During the following row cycle, the DMD releases the tension under each mirror so that all mirrors are in a

relatively flat position. The FLOAT operation takes approximately 500 μs to complete, during which time

RST_ACTIVE is NOT asserted. Normal operation may then continue without resetting or cycling power to the

DLPC910 or the DMD.

7.3.6.5 Load4

Load4 functionality provides improved global binary pattern rates for applications that can trade diminished

vertical resolution for higher pattern rates. Examples of these types of applications are shutter or chopper

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applications and vertical structured light patterns. Asserting LOAD4_ENZ causes the attached DMD to load 4

rows for every row of data sent, reducing the pattern load time to ¼ of a full DMD load. It does not reduce the

MCP timing.

7.3.6.5.1 Load4 Row Addressing

In Load4 mode, automatic increment mode and row address mode can still be used as before, however the

largest addressable row is (VRes/4) - 1, where VRes = the vertical resolution of the DMD. The addressable

vertical resolution is reduced by four, although the physical resolution is unchanged.

Automatic increment address mode will automatically increment the row address input by one (or decrement by

one for N/S flip). The row address input will be re-mapped as shown in 表7-3.

表7-3. Load4 Row Address Mapping

ROW ADDRESS INPUT

PHYSICAL ROWS LOADED ON DMD

0

0, 1, 2, 3

1

4, 5, 6, 7

2

8, 9, 10, 11

3

N

12, 13, 14, 15

4N, 4N+1, 4N+2, 4N+3

VRes-4, VRes-3, VRes-2, VRes-1

(VRes/4) -1

Data Sent

Data Loaded

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

图7-3. Example Load4 Row Address Mapping

7.3.6.5.2 Load4 Block Clears

While Load4 is enabled, Block Clear requests will be ignored. To load using Load4 followed by Block Clear

request(s), simply de-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the Block Clear

request(s). Re-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the next desired Load4

operation. This will ensure that the DLPC910 controller has sufficient time to disable or enable LOAD4_ENZ

before data is loaded or Block Clear(s) are requested. Refer to Block Clear regarding block clear operation.

7.3.7 Status Interface

7.3.7.1 ECP2 Finished

When power is applied, the ECP2_FINISHED signal goes high to indicate the DLPC910 has completed loading

the configuration from the DLPR910 PROM.

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7.3.7.2 Initialization Active

The initialization active signal INIT_ACTIVE indicates that the DMD and the DLPC910 digital controller are in an

initialization state after power is applied. During this initialization period, the DLPC910 is calibrating the data

interface, and initializing the DMD by setting all internal registers to their correct states. Monitoring the

INIT_ACTIVE signal should not begin until ECP2_FINISHED goes high. When this signal goes low, the system

has completed initialization. System initialization takes approximately 4 ms to complete. Data and command

write cycles must not be asserted during the initialization. This signal is driven by a CLK_R register and should

be considered an asynchronous signal. Standard synchronization techniques should be applied if monitoring this

signal with a synchronous circuit clocked by a clock other than CLK_R. After initialization is complete, a delay of

at least 64 clocks should be observed before the first DVALID is asserted (to ensure a clean start up process).

备注

The RST2BLKZ, COMP_DATA, and NS_FLIP signals should be kept low during initialization to ensure

proper setup of the system.

7.3.7.3 Reset Active

The reset active signal RST_ACTIVE goes high for approximately 4 µs, indicating a MCP operation is in

progress. During this time, no additional MCPs will be accepted by the DLPC910 until RST_ACTIVE returns low.

RST_ACTIVE does not return to low unless continuous no-op or data loading row cycles are issued.

RST_ACTIVE is asserted to indicate that the operation is in progress. Each RST_ACTIVE pulse applies to one

or more MCPs depending on the reset block operation chosen from 表7-12. RST_ACTIVE is synchronized to an

internal version of DDC_DCLK. As such, circuits in the application FPGA should consider this signal

asynchronous and use standard synchronization techniques to assure reliable registering of this signal.

7.3.7.4 DMD_TYPE

During initialization, the DLPC910 queries the attached DMD for its DMD Type information. This information can

then be monitored by an external processor via the status output pins DMD_TYPE_[3:0], or can be read via

software over the I²C interface from the 节 7.5.1.4. The DMD types supported by the DLPC910 are listed in 表

7-4.

表7-4. DMD Type Information

DMD_TYPE_[3:0] output

DESTOP_DMD_ID_REG value

Type of DMD identified by DLPC410

pins

Value upon reset condition. Once read = unsupported

DMD or DMD not connected

'0000'

0x00000000

'1110'

'1111'

0x0000000E

0x0000000F

invalid

DLP6500

DLP9000X or DLP9000XUV

invalid

all other values

备注

If the DMD type is unsupported by the DLPC910 or the DMD type is unable to be read from the DMD,

then the DLPC910 will not allow bit plane images to be displayed on the DMD.

7.3.7.5 DDC_Version(2:0)

These three output pins of the DLPC910 identify the version of the DLPC910 firmware as determined by the

contents of DLPR910 PROM. If a problem is encountered which encourages you to contact a Texas Instruments

representative, please provide the version number along with the detailed information of the issue. The current

state of these output pins can also be acquired over the I²C bus by reading the DESTOP_VERSION Register.

See the DLPR910 datasheet link located in 节 11.2.1 for the expected version numbers related to DLPR910

revisions.

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7.3.7.6 DMD_IRQ

The DMD_IRQ signal indicates a DMD power fault of one of the bias, offset, or reset power supplies. If the

customer interface wishes to monitor this signal, it must first be enabled in the DESTOP_INTERRUPT Register.

The cause of the fault should be determined and resolved prior to a system reset to continue operation. The

customer interface can also monitor this event by polling the DESTOP_INTERRUPT Register via the I²C

interface.

7.3.7.7 LED Indicators

7.3.7.7.1 VLED0

The VLED0 signal is typically connected to an LED to show that the DLPC910 is operating normally. The signal

is 1 Hz with 50% duty cycle, otherwise known as the heartbeat.

7.3.7.7.2 VLED1

The VLED1 signal is typically connected to an LED indicator to show the status of system initialization and the

status of the clock circuits. The VLED1 signal is asserted only when system initialization is complete and clock

circuits are initialized. Logically, these signals are ANDed together to show an indication of the health of the

system. If the Phase Locked Loop (PLL) connected to the data clock and the DMD clock are functioning correctly

after system initialization, the LED will be illuminated.

7.3.8 Reset and System Clock

7.3.8.1 Controller Reset

The controller reset input CTRL_RSTZ is an active low, asynchronous reset. This reset can be sourced from a

voltage supervisor or from the customer interface. Users should note that the chipset will not operate correctly if

all DLPC910 power supplies are not in range at the time this reset is released.

7.3.8.2 Main Oscillator Clock

The reference clock, CLKIN_R, supplied from an oscillator must be 50 MHz. This is required for the precise

timing used to perform the DMD MCP. This clock should be valid prior to releasing CTRL_RSTZ.

7.3.9 I²C Interface

The I²C interface is compliant to I²C specification version 1.0 – 1992, and operates between 100 kHz and 400

kHz clock rate. The interface allows the user to set controller configuration and provides status information such

as:

• Controller and DMD identification

• DMD Type

• Versions

• Controller operating status

• Controller operating modes

Each I²C clock and data I/O requires an external 1K-Ω pull-up resistor to 3.3 V. Depending on the speed that is

selected and the loading of the interface, a different pull-up resistor may be required.

7.3.9.1 Configuration Pins

The DDC_I2C_ADDR_SEL input signal allows the user to select the DLPC910 I²C slave address. When this pin

is low, the slave address is 0x34 and when high the slave address is 0x36. If pin is left unconnected, the default

slave address is 0x36.

The DDC_I2C_SCL is the master controller input clock. The DDC_I2C_SDA is the bidirectional data signal. Both

these signals require a 1-kΩ pull-up resistor.

7.3.9.2 Communications Interface

Communications is performed over the I²C interface where the DLPC910 is the slave device. The DLPC910

slave address consists of a 7-bit address plus 1 R/W bit. Communicating with the DLPC910 involves writing to or

reading from the registers listed in Register Map.

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7.3.9.2.1 Command Format

All register addresses are 32-bit in size, where each register contains a 32-bit value. The actual valid bits are

shown in each respective register. Most registers contain spare or unused bits. These bits should be treated as

don't-care during a read operation unless otherwise specified. When writing to spare or unused bits, these bits

MUST be set to 0. Both the register address and the data require the least-significant byte to be first and most-

significant byte last. A SUB CMD must precede the register address to indicate the type of operation, where a

0xF1 indicates a write operation and a 0xF2 indicates a read operation. The following figures show examples of

writing and reading to the DESTOP_BUS_SWAP register.

图 7-4 shows an I²C master writing data to the DLPC910, where 0xF1 is required as the SUB CMD followed by

the register address and finally the register data.

图7-4. Example I²C Master Writing DLPC910 Register Data

图 7-5 shows an I²C master reading data from the DLPC910, where 0xF2 is required as the SUB CMD followed

by the register address. Then the master performs STOP followed by a START to read the register data.

图7-5. Example I²C Master Reading DLPC910 Register Data

7.3.10 DMD Interface

Refer to 表7-11 to obtain the required LVDS buses needed for each supported DMD.

7.3.10.1 DDC_DOUT

The controller provides four (A, B, C, D) 16-bit wide 2x LVDS output data buses to the DMD with a user

selectable bus frequency of 400 or 480 MHz.

7.3.10.2 DDC_SCTRL

The controller provides four (A, B, C, D) control output buses to the DMD. Each bus provides the necessary

control data for the different operating modes of the DMD.

7.3.10.3 DDC_DCLKOUT

The controller provides four (A, B, C, D) clock outputs to the DMD with a clock frequency of 400 or 480 MHz

(user selectable). Both DDC_DOUT and DDC_SCTRL are clocked into the DMD on both the rising and falling

edges of the DDC_DCLKOUT. When connecting the DLPC910 with a DLP6500, SPEED_SEL[1:0] inputs

must be set to "00".

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7.3.10.4 DMD Reset Interface

7.3.10.4.1 Mirror Reset Control

The controller provides the necessary mirror reset control signals to the DMD, which are:

• RESET_ADDR(3:0) –Reset Driver Address Select.

• RESET_MODE(3:0) –Reset Driver Mode Select.

• RESET_SEL(1:0) –Reset Driver Level Select.

• RESET_STRB –Reset Address, Mode, and Level Select latched on rising-edge.

7.3.10.5 Enable and Interrupt Signals

The controller provides the necessary outputs for DMD enables and an input interrupt from the DMD, which are:

• RESET_RSTZ –Active-low reset output to the DMD PWRDNZ and RESETZ inputs.

• RESET_OEZ –Active-low output enable for the DMD reset driver circuits.

• RESET_IRQZ –Active-low input interrupt from the DMD.

7.3.10.6 Serial Control Port

The DLPC910 communicates with the DMD over the SCP bus to perform initialization, set configuration, and

retrieve identification information.

7.3.11 Flash PROM Interface

7.3.11.1 JTAG Interface

The JTAG interface has multiple purposes that can be used in the following manner:

• Program the configuration bit stream directly into the DLPC910

• Perform boundary test and debug of the DLPC910

• Program the configuration bit stream directly into the DLPR910 Flash PROM (not user configurable)

7.3.11.2 PGM Interface

The PGM(4:0) interface is used by the DLPC910 to read in the configuration bit stream from the attached

DLPR910 PROM.

7.4 Device Functional Modes

The following section focuses on the operation of the DLP9000X/DLP9000XUV DMDs. The DLP6500 operates

similar to the DLP9000X/DLP9000XUV. Refer to 表7-11 for the differences between the supported DMDs.

7.4.1 DMD Row Operation

The DMD data is loaded one row at a time with the LVDS buses into the DMD SRAM array. All DMD data buses

are required for correct operation. Refer to 表 7-11 to obtain the required LVDS buses for each DMD supported.

Each bus consists of a differential clock (DDC_DCLKOUT), a differential control signal (DDC_SCTRL), and 16

differential pairs of LVDS signals (DDC_DOUT[15:0]) that are output from the DLPC910. Data and control are

clocked into the DMD on both the rising and falling edges of the DDC_DCLKOUT clocks. Data loading does not

cause mirror switching until a MCP operation is completed.

The number of clocks to load a row can be calculated as:

C = P / (D × E)

(1)

where

• C = number of clocks per row

• P = number of pixels per row

• D = data bus bit width

• E = 2. (Data is clocked on both the rising and falling edge of DCLK.)

Example:

C = 2560 / (64 × 2) = 20 clocks per row

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Row address orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to

Related Documentation for the DMD datasheet regarding orientation of rows, columns, and MCP blocks. The

row address counter does not automatically wrap-around when using the increment row address pointer

instruction. After the final row is addressed, the row address pointer must be cleared to 0.

备注

The pin names in the following Pixel Mapping tables have been shortened to allow the tables to fit on

the page. For example: D_A(0) = DDC_DIN_A0, D_A(1) = DDC_DIN_A1, and so on.

表7-5. DLP9000X/DLP9000XUV Pixel Mapping for D_A(x)

DCLK

EDGE

D_A(0) D_A(1)

D_A(2)

D_A(3)

D_A(4)

D_A(5) D_A(6)

D_A(7)

D_A(8)

D_A(9)

D_A(10) D_A(11) D_A(12) D_A(12) D_A(14) D_A(15)

0

1

2

3

4

5

6

7

8

9

10

42

11

43

12

44

13

14

15

1

32

33

34

35

36

37

38

39

40

41

45

46

47

2

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

3

96

97

98

99

100

132

164

196

228

260

292

324

356

388

420

452

484

516

548

580

612

644

676

708

740

772

804

836

868

900

932

964

996

1028

1060

1092

1124

1156

1188

1220

1252

101

133

165

197

229

261

293

325

357

389

421

453

485

517

549

581

613

645

677

709

741

773

805

837

869

901

933

965

997

1029

1061

1093

1125

1157

1189

1221

1253

102

134

166

198

230

262

294

326

358

390

422

454

486

518

550

582

614

646

678

710

742

774

806

838

870

902

934

966

998

1030

1062

1094

1126

1158

1190

1222

1254

103

135

167

199

231

263

295

327

359

391

423

455

487

519

551

583

615

647

679

711

743

775

807

839

871

903

935

967

999

1031

1063

1095

1127

1159

1191

1223

1255

104

136

168

200

232

264

296

328

360

392

424

456

488

520

552

584

616

648

680

712

744

776

808

840

872

904

936

968

1000

1032

1064

1096

1128

1160

1192

1224

1256

105

137

169

201

233

265

297

329

361

393

425

457

489

521

553

585

617

649

681

713

745

777

809

841

873

905

937

969

1001

1033

1065

1097

1129

1161

1193

1225

1257

106

138

170

202

234

266

298

330

362

394

426

458

490

522

554

586

618

650

682

714

746

778

810

842

874

906

938

970

1002

1034

1066

1098

1130

1162

1194

1226

1258

107

139

171

203

235

267

299

331

363

395

427

459

491

523

555

587

619

651

683

715

747

779

811

108

140

172

204

236

268

300

332

364

396

428

460

492

524

556

588

620

652

684

716

748

780

812

844

876

908

940

972

1004

1036

1068

1100

1132

1164

1196

1228

1260

109

141

173

205

237

269

301

333

365

397

429

461

493

525

557

589

621

653

685

717

749

781

813

845

877

909

941

973

1005

1037

1069

1101

1133

1165

1197

1229

1261

110

142

174

206

238

270

302

334

366

398

430

462

494

526

558

590

622

654

686

718

750

782

814

846

878

910

942

974

1006

1038

1070

1102

1134

1166

1198

1230

1262

111

4

128

160

192

224

256

288

320

352

384

416

448

480

512

544

576

608

640

672

704

736

768

800

832

864

896

928

960

992

1024

1056

1088

1120

1152

1184

1216

1248

129

161

193

225

257

289

321

353

385

417

449

481

513

545

577

609

641

673

705

737

769

801

833

865

897

929

961

993

1025

1057

1089

1121

1153

1185

1217

1249

130

162

194

226

258

290

322

354

386

418

450

482

514

546

578

610

642

674

706

738

770

802

834

866

898

930

962

994

1026

1058

1090

1122

1154

1186

1218

1250

131

163

195

227

259

291

323

355

387

419

451

483

515

547

579

611

643

675

707

739

771

803

835

867

899

931

963

995

1027

1059

1091

1123

1155

1187

1219

1251

143

175

207

239

271

303

335

367

399

431

463

495

527

559

591

623

655

687

719

751

783

815

847

879

911

943

975

1007

1039

1071

1103

1135

1167

1199

1231

1263

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

843

875

907

939

971

1003

1035

1067

1099

1131

1163

1195

1227

1259

表7-6. DLP9000X/DLP9000XUV Pixel Mapping for D_B(x)

DCLK

EDGE

D_B(0) D_B(1)

16 17

D_B(2)

D_B(3)

D_B(4)

D_B(5) D_B(6)

D_B(7)

D_B(8)

D_B(9)

D_B(10) D_B(11) D_B(12) D_B(12) D_B(14) D_B(15)

0

18

19

20

21 22

23

24

25

26 27 28 29 30 31

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表7-6. DLP9000X/DLP9000XUV Pixel Mapping for D_B(x) (continued)

DCLK

EDGE

D_B(0) D_B(1)

D_B(2)

D_B(3)

D_B(4)

D_B(5) D_B(6)

D_B(7)

D_B(8)

D_B(9)

D_B(10) D_B(11) D_B(12) D_B(12) D_B(14) D_B(15)

1

48

80

49

50

51

52

53

54

55

56

57

58

90

59

91

60

92

61

62

63

2

81

82

83

84

85

86

87

88

89

93

94

95

3

112

113

114

115

116

117

118

119

120

152

184

216

248

280

312

344

376

408

440

472

504

536

568

600

632

664

696

728

760

792

824

856

888

920

952

984

1016

1048

1080

1112

1144

1176

1208

1240

1272

121

153

185

217

249

281

313

345

377

409

441

473

505

537

569

601

633

665

697

729

761

793

825

857

889

921

953

985

1017

1049

1081

1113

1145

1177

1209

1241

1273

122

154

186

218

250

282

314

346

378

410

442

474

506

538

570

602

634

666

698

730

762

794

826

858

890

922

954

986

1018

1050

1082

1114

1146

1178

1210

1242

1274

123

155

187

219

251

283

315

347

379

411

124

156

188

220

252

284

316

348

380

412

444

476

508

540

572

604

636

668

700

732

764

796

828

860

892

924

956

988

1020

1052

1084

1116

1148

1180

1212

1244

1276

125

157

189

221

253

285

317

349

381

413

445

477

509

541

573

605

637

669

701

733

765

797

829

861

893

925

957

989

1021

1053

1085

1117

1149

1181

1213

1245

1277

126

158

190

222

254

286

318

350

382

414

446

478

510

542

574

606

638

670

702

734

766

798

830

862

894

926

958

990

1022

1054

1086

1118

1150

1182

1214

1246

1278

127

159

191

223

255

287

319

351

383

415

447

479

511

4

144

176

208

240

272

304

336

368

400

432

464

496

528

560

592

624

656

688

720

752

784

816

848

880

912

944

976

1008

1040

1072

1104

1136

1168

1200

1232

1264

145

177

209

241

273

305

337

369

401

433

465

497

529

561

593

625

657

689

721

753

785

817

849

881

913

945

977

1009

1041

1073

1105

1137

1169

1201

1233

1265

146

178

210

242

274

306

338

370

402

434

466

498

530

562

594

626

658

690

722

754

786

818

850

882

914

946

978

1010

1042

1074

1106

1138

1170

1202

1234

1266

147

179

211

148

180

212

244

276

308

340

372

404

436

468

500

532

564

596

628

660

692

724

756

788

820

852

884

916

948

980

1012

1044

1076

1108

1140

1172

1204

1236

1268

149

181

213

245

277

309

341

373

405

437

469

501

533

565

597

629

661

693

725

757

789

821

853

885

917

949

981

1013

1045

1077

1109

1141

1173

1205

1237

1269

150

182

214

246

278

310

342

374

406

438

470

502

534

566

598

630

662

694

726

758

790

822

854

886

918

950

982

1014

1046

1078

1110

1142

1174

1206

1238

1270

151

183

215

247

279

311

5

6

7

243

275

307

339

371

403

435

467

499

531

563

595

627

659

691

723

755

787

819

851

883

915

947

979

1011

1043

1075

1107

1139

1171

1203

1235

1267

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

343

375

407

439

471

503

535

567

599

631

663

695

727

759

791

823

855

887

919

951

983

1015

1047

1079

1111

1143

1175

1207

1239

1271

443

475

507

539

571

603

635

667

699

731

763

795

827

859

891

923

955

987

1019

1051

1083

1115

1147

1179

1211

1243

1275

543

575

607

639

671

703

735

767

799

831

863

895

927

959

991

1023

1055

1087

1119

1151

1183

1215

1247

1279

28

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DLPC910

www.ti.com.cn

ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

表7-7. DLP9000X/DLP9000XUV Pixel Mapping for D_C(x)

DCLK

EDGE

D_C(0) D_C(1)

D_C(2)

D_C(3)

D_C(4)

D_C(5) D_C(6)

D_C(7)

D_C(8)

D_C(9)

D_C(10) D_C(11) D_C(12) D_C(12) D_C(14) D_C(15)

0

1280

1312

1344

1376

1408

1440

1472

1504

1536

1568

1600

1632

1664

1696

1728

1760

1792

1824

1856

1888

1920

1952

1984

2016

2048

2080

2112

2144

2176

2208

2240

2272

2304

2336

2368

2400

2432

2464

2496

2528

1281

1313

1345

1377

1409

1441

1473

1505

1537

1569

1601

1633

1665

1697

1729

1761

1793

1825

1857

1889

1921

1953

1985

2017

2049

2081

2113

2145

2177

2209

2241

2273

2305

2337

2369

2401

2433

2465

2497

2529

1282

1314

1346

1378

1410

1442

1474

1506

1538

1570

1602

1634

1666

1698

1730

1762

1794

1826

1858

1890

1922

1954

1986

2018

2050

2082

2114

2146

2178

2210

2242

2274

2306

2338

2370

2402

2434

2466

2498

2530

1283

1315

1347

1379

1411

1443

1475

1507

1539

1571

1603

1635

1667

1699

1731

1763

1795

1827

1859

1891

1923

1955

1987

2019

2051

2083

2115

2147

2179

2211

2243

2275

2307

2339

2371

2403

2435

2467

2499

2531

1284

1316

1348

1380

1412

1444

1476

1508

1540

1572

1604

1636

1668

1700

1732

1764

1796

1828

1860

1892

1924

1956

1988

2020

2052

2084

2116

2148

2180

2212

2244

2276

2308

2340

2372

2404

2436

2468

2500

2532

1285

1317

1349

1381

1413

1445

1477

1509

1541

1573

1605

1637

1669

1701

1733

1765

1797

1829

1861

1893

1925

1957

1989

2021

2053

2085

2117

2149

2181

2213

2245

2277

2309

2341

2373

2405

2437

2469

2501

2533

1286

1318

1350

1382

1414

1446

1478

1510

1542

1574

1606

1638

1670

1702

1734

1766

1798

1830

1862

1894

1926

1958

1990

2022

2054

2086

2118

2150

2182

2214

2246

2278

2310

2342

2374

2406

2438

2470

2502

2534

1287

1319

1351

1383

1415

1447

1479

1511

1543

1575

1607

1639

1671

1703

1735

1767

1799

1831

1863

1895

1927

1959

1991

2023

2055

2087

2119

2151

2183

2215

2247

2279

2311

2343

2375

2407

2439

2471

2503

2535

1288

1320

1352

1384

1416

1448

1480

1512

1544

1576

1608

1640

1672

1704

1736

1768

1800

1832

1864

1896

1928

1960

1992

2024

2056

2088

2120

2152

2184

2216

2248

2280

2312

2344

2376

2408

2440

2472

2504

2536

1289

1321

1353

1385

1417

1449

1481

1513

1545

1577

1609

1641

1673

1705

1737

1769

1801

1833

1865

1897

1929

1961

1993

2025

2057

2089

2121

2153

2185

2217

2249

2281

2313

2345

2377

2409

2441

2473

2505

2537

1290

1322

1354

1386

1418

1450

1482

1514

1546

1578

1610

1642

1674

1706

1738

1770

1802

1834

1866

1898

1930

1962

1994

2026

2058

2090

2122

2154

2186

2218

2250

2282

2314

2346

2378

2410

2442

2474

2506

2538

1291

1323

1355

1387

1419

1451

1483

1515

1547

1579

1611

1643

1675

1707

1739

1771

1803

1835

1867

1899

1931

1963

1995

2027

2059

2091

2123

2155

2187

2219

2251

2283

2315

2347

2379

2411

2443

2475

2507

2539

1292

1324

1356

1388

1420

1452

1484

1516

1548

1580

1612

1644

1676

1708

1740

1772

1804

1836

1868

1900

1932

1964

1996

2028

2060

2092

2124

2156

2188

2220

2252

2284

2316

2348

2380

2412

2444

2476

2508

2540

1293

1325

1357

1389

1421

1453

1485

1517

1549

1581

1613

1645

1677

1709

1741

1773

1805

1837

1869

1901

1933

1965

1997

2029

2061

2093

2125

2157

2189

2221

2253

2285

2317

2349

2381

2413

2445

2477

2509

2541

1294

1326

1358

1390

1422

1454

1486

1518

1550

1582

1614

1646

1678

1710

1742

1774

1806

1838

1870

1902

1934

1966

1998

2030

2062

2094

2126

2158

2190

2222

2254

2286

2318

2350

2382

2414

2446

2478

2510

2542

1295

1327

1359

1391

1423

1455

1487

1519

1551

1583

1615

1647

1679

1711

1743

1775

1807

1839

1871

1903

1935

1967

1999

2031

2063

2095

2127

2159

2191

2223

2255

2287

2319

2351

2383

2415

2447

2479

2511

2543

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

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29

DLPC910

www.ti.com.cn

ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

表7-8. DLP9000X/DLP9000XUV Pixel Mapping for D_D(x)

DCLK

EDGE

D_D(0) D_D(1)

D_D(2)

D_D(3)

D_D(4)

D_D(5) D_D(6)

D_D(7)

D_D(8)

D_D(9)

D_D(10) D_D(11) D_D(12) D_D(12) D_D(14) D_D(15)

0

1296

1328

1360

1392

1424

1456

1488

1520

1552

1584

1616

1648

1680

1712

1744

1776

1808

1840

1872

1904

1936

1968

2000

2032

2064

2096

2128

2160

2192

2224

2256

2288

2320

2352

2384

2416

2448

2480

2512

2544

1297

1329

1361

1393

1425

1457

1489

1521

1553

1585

1617

1649

1681

1713

1745

1777

1809

1841

1873

1905

1937

1969

2001

2033

2065

2097

2129

2161

2193

2225

2257

2289

2321

2353

2385

2417

2449

2481

2513

2545

1298

1330

1362

1394

1426

1458

1490

1522

1554

1586

1618

1650

1682

1714

1746

1778

1810

1842

1874

1906

1938

1970

2002

2034

2066

2098

2130

2162

2194

2226

2258

2290

2322

2354

2386

2418

2450

2482

2514

2546

1299

1331

1363

1395

1427

1459

1491

1523

1555

1587

1619

1651

1683

1715

1747

1779

1811

1843

1875

1907

1939

1971

2003

2035

2067

2099

2131

2163

2195

2227

2259

2291

2323

2355

2387

2419

2451

2483

2515

2547

1300

1332

1364

1396

1428

1460

1492

1524

1556

1588

1620

1652

1684

1716

1748

1780

1812

1844

1876

1908

1940

1972

2004

2036

2068

2100

2132

2164

2196

2228

2260

2292

2324

2356

2388

2420

2452

2484

2516

2548

1301

1333

1365

1397

1429

1461

1493

1525

1557

1589

1621

1653

1685

1717

1749

1781

1813

1845

1877

1909

1941

1973

2005

2037

2069

2101

2133

2165

2197

2229

2261

2293

2325

2357

2389

2421

2453

2485

2517

2549

1302

1334

1366

1398

1430

1462

1494

1526

1558

1590

1622

1654

1686

1718

1750

1782

1814

1846

1878

1910

1942

1974

2006

2038

2070

2102

2134

2166

2198

2230

2262

2294

2326

2358

2390

2422

2454

2486

2518

2550

1303

1335

1367

1399

1431

1463

1495

1527

1559

1591

1623

1655

1687

1719

1751

1783

1815

1847

1879

1911

1943

1975

2007

2039

2071

2103

2135

2167

2199

2231

2263

2295

2327

2359

2391

2423

2455

2487

2519

2551

1304

1336

1368

1400

1432

1464

1496

1528

1560

1592

1624

1656

1688

1720

1752

1784

1816

1848

1880

1912

1944

1976

2008

2040

2072

2104

2136

2168

2200

2232

2264

2296

2328

2360

2392

2424

2456

2488

2520

2552

1305

1337

1369

1401

1433

1465

1497

1529

1561

1593

1625

1657

1689

1721

1753

1785

1817

1849

1881

1913

1945

1977

2009

2041

2073

2105

2137

2169

2201

2233

2265

2297

2329

2361

2393

2425

2457

2489

2521

2553

1306

1338

1370

1402

1434

1466

1498

1530

1562

1594

1626

1658

1690

1722

1754

1786

1818

1850

1882

1914

1946

1978

2010

2042

2074

2106

2138

2170

2202

2234

2266

2298

2330

2362

2394

2426

2458

2490

2522

2554

1307

1339

1371

1403

1435

1467

1499

1531

1563

1595

1627

1659

1691

1723

1755

1787

1819

1851

1883

1915

1947

1979

2011

2043

2075

2107

2139

2171

2203

2235

2267

2299

2331

2363

2395

2427

2459

2491

2523

2555

1308

1340

1372

1404

1436

1468

1500

1532

1564

1596

1628

1660

1692

1724

1756

1788

1820

1852

1884

1916

1948

1980

2012

2044

2076

2108

2140

2172

2204

2236

2268

2300

2332

2364

2396

2428

2460

2492

2524

2556

1309

1341

1373

1405

1437

1469

1501

1533

1565

1597

1629

1661

1693

1725

1757

1789

1821

1853

1885

1917

1949

1981

2013

2045

2077

2109

2141

2173

2205

2237

2269

2301

2333

2365

2397

2429

2461

2493

2525

2557

1310

1342

1374

1406

1438

1470

1502

1534

1566

1598

1630

1662

1694

1726

1758

1790

1822

1854

1886

1918

1950

1982

2014

2046

2078

2110

2142

2174

2206

2238

2270

2302

2334

2366

2398

2430

2462

2494

2526

2558

1311

1343

1375

1407

1439

1471

1503

1535

1567

1599

1631

1663

1695

1727

1759

1791

1823

1855

1887

1919

1951

1983

2015

2047

2079

2111

2143

2175

2207

2239

2271

2303

2335

2367

2399

2431

2463

2495

2527

2559

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

30

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

表7-9. DLP6500 Pixel Mapping for D_A(x)

DCLK

EDGE

D_A(0) D_A(1)

D_A(2)

D_A(3)

D_A(4)

D_A(5) D_A(6)

D_A(7)

D_A(8)

D_A(9)

D_A(10) D_A(11) D_A(12) D_A(12) D_A(14) D_A(15)

0

Not visible

1

2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

3

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

4

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

5

96

97

98

99

100

101

102

103

135

167

199

231

263

295

327

359

391

423

455

487

519

551

583

615

647

679

711

104

105

106

107

108

109

110

111

6

128

129

161

193

225

257

289

321

353

385

417

449

481

513

545

577

609

641

673

705

737

769

801

833

865

897

929

961

993

1025

1057

1089

1121

1153

1185

1217

1249

1281

1313

1345

1377

1409

1441

1473

1505

1537

1569

1601

1633

130

162

194

226

258

290

322

354

386

418

450

482

514

546

578

610

642

674

706

738

770

802

834

866

898

930

962

994

1026

1058

1090

1122

1154

1186

1218

1250

1282

1314

1346

1378

1410

1442

1474

1506

1538

1570

1602

1634

131

163

195

227

259

291

323

355

387

419

451

483

515

547

579

611

132

133

134

136

137

138

139

140

141

142

143

7

160

164

165

166

168

169

170

171

172

173

174

175

8

192

196

197

198

200

201

202

203

204

205

206

207

9

224

228

229

230

232

233

234

235

236

237

238

239

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

256

260

261

262

264

265

266

267

268

269

270

271

288

292

293

294

296

297

298

299

300

301

302

303

320

324

325

326

328

329

330

331

332

333

334

335

352

356

357

358

360

361

362

363

364

365

366

367

384

388

389

390

392

393

394

395

396

397

398

399

416

420

421

422

424

425

426

427

428

429

430

431

448

452

453

454

456

457

458

459

460

461

462

463

480

484

485

486

488

489

490

491

492

493

494

495

512

516

517

518

520

521

522

523

524

525

526

527

544

548

549

550

552

553

554

555

556

557

558

559

576

580

581

582

584

585

586

587

588

589

590

591

608

612

613

614

616

617

618

619

620

621

622

623

640

643

675

707

739

771

803

835

867

899

931

963

995

1027

1059

1091

1123

1155

1187

1219

1251

1283

1315

1347

1379

1411

1443

1475

1507

1539

1571

1603

1635

644

645

646

648

649

650

651

652

653

654

655

672

676

677

678

680

681

682

683

684

685

686

687

704

708

709

710

712

713

714

715

716

717

718

719

736

740

741

742

743

775

807

839

871

903

935

967

999

1031

1063

1095

1127

1159

1191

1223

1255

1287

1319

1351

1383

1415

1447

1479

1511

1543

1575

1607

1639

744

745

746

747

748

749

750

751

768

772

773

774

776

777

778

779

780

781

782

783

800

804

805

806

808

809

810

811

812

813

814

815

832

836

837

838

840

841

842

843

844

845

846

847

864

868

869

870

872

873

874

875

876

877

878

879

896

900

901

902

904

905

906

907

908

909

910

911

928

932

933

934

936

937

938

939

940

941

942

943

960

964

965

966

968

969

970

971

972

973

974

975

992

996

997

998

1000

1032

1064

1096

1128

1160

1192

1224

1256

1288

1320

1352

1384

1416

1448

1480

1512

1544

1576

1608

1640

1001

1033

1065

1097

1129

1161

1193

1225

1257

1289

1321

1353

1385

1417

1449

1481

1513

1545

1577

1609

1641

1002

1034

1066

1098

1130

1162

1194

1226

1258

1290

1322

1354

1386

1418

1450

1482

1514

1546

1578

1610

1642

1003

1035

1067

1099

1131

1163

1195

1227

1259

1291

1323

1355

1387

1419

1451

1483

1515

1547

1579

1611

1643

1004

1036

1068

1100

1132

1164

1196

1228

1260

1292

1324

1356

1388

1420

1452

1484

1516

1548

1580

1612

1644

1005

1037

1069

1101

1133

1165

1197

1229

1261

1293

1325

1357

1389

1421

1453

1485

1517

1549

1581

1613

1645

1006

1038

1070

1102

1134

1166

1198

1230

1262

1294

1326

1358

1390

1422

1454

1486

1518

1550

1582

1614

1646

1007

1039

1071

1103

1135

1167

1199

1231

1263

1295

1327

1359

1391

1423

1455

1487

1519

1551

1583

1615

1647

1024

1056

1088

1120

1152

1184

1216

1248

1280

1312

1344

1376

1408

1440

1472

1504

1536

1568

1600

1632

1028

1060

1092

1124

1156

1188

1220

1252

1284

1316

1348

1380

1412

1444

1476

1508

1540

1572

1604

1636

1029

1061

1093

1125

1157

1189

1221

1253

1285

1317

1349

1381

1413

1445

1477

1509

1541

1573

1605

1637

1030

1062

1094

1126

1158

1190

1222

1254

1286

1318

1350

1382

1414

1446

1478

1510

1542

1574

1606

1638

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表7-9. DLP6500 Pixel Mapping for D_A(x) (continued)

DCLK

EDGE

D_A(0) D_A(1)

D_A(2)

D_A(3)

D_A(4)

D_A(5) D_A(6)

D_A(7)

D_A(8)

D_A(9)

D_A(10) D_A(11) D_A(12) D_A(12) D_A(14) D_A(15)

54

55

56

57

58

59

60

61

62

63

1664

1696

1728

1760

1792

1824

1856

1888

1665

1697

1729

1761

1793

1825

1857

1889

1666

1698

1730

1762

1794

1826

1858

1890

1667

1699

1731

1763

1795

1827

1859

1891

1668

1700

1732

1764

1796

1828

1860

1892

1669

1701

1733

1765

1797

1829

1861

1893

1670

1702

1734

1766

1798

1830

1862

1894

1671

1703

1735

1767

1799

1831

1863

1895

1672

1704

1736

1768

1800

1832

1864

1896

1673

1705

1737

1769

1801

1833

1865

1897

1674

1706

1738

1770

1802

1834

1866

1898

1675

1707

1739

1771

1803

1835

1867

1899

1676

1708

1740

1772

1804

1836

1868

1900

1677

1709

1741

1773

1805

1837

1869

1901

1678

1710

1742

1774

1806

1838

1870

1902

1679

1711

1743

1775

1807

1839

1871

1903

Not visible

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表7-10. DLP6500 Pixel Mapping for D_B(x)

DCLK

EDGE

D_B(0) D_B(1)

D_B(2)

D_B(3)

D_B(4)

D_B(5) D_B(6)

D_B(7)

D_B(8)

D_B(9)

D_B(10) D_B(11) D_B(12) D_B(12) D_B(14) D_B(15)

0

Not visible

1

2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

3

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

4

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

5

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

6

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

7

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

8

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

9

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

656

657

658

659

660

661

662

663

664

665

666

667

668

669

670

671

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

752

753

754

755

756

757

758

759

760

761

762

763

764

765

766

767

784

785

786

787

788

789

790

791

792

793

794

795

796

797

798

799

816

817

818

819

820

821

822

823

824

825

826

827

828

829

830

831

848

849

850

851

852

853

854

855

856

857

858

859

860

861

862

863

880

881

882

883

884

885

886

887

888

889

890

891

892

893

894

895

912

913

914

915

916

917

918

919

920

921

922

923

924

925

926

927

944

945

946

947

948

949

950

951

952

953

954

955

956

957

958

959

976

977

978

979

980

981

982

983

984

985

986

987

988

989

990

991

1008

1040

1072

1104

1136

1168

1200

1232

1264

1296

1328

1360

1392

1424

1456

1488

1520

1552

1584

1616

1648

1009

1041

1073

1105

1137

1169

1201

1233

1265

1297

1329

1361

1393

1425

1457

1489

1521

1553

1585

1617

1649

1010

1042

1074

1106

1138

1170

1202

1234

1266

1298

1330

1362

1394

1426

1458

1490

1522

1554

1586

1618

1650

1011

1043

1075

1107

1139

1171

1203

1235

1267

1299

1331

1363

1395

1427

1459

1491

1523

1555

1587

1619

1651

1012

1044

1076

1108

1140

1172

1204

1236

1268

1300

1332

1364

1396

1428

1460

1492

1524

1556

1588

1620

1652

1013

1045

1077

1109

1141

1173

1205

1237

1269

1301

1333

1365

1397

1429

1461

1493

1525

1557

1589

1621

1653

1014

1046

1078

1110

1142

1174

1206

1238

1270

1302

1334

1366

1398

1430

1462

1494

1526

1558

1590

1622

1654

1015

1047

1079

1111

1143

1175

1207

1239

1271

1303

1335

1367

1399

1431

1463

1495

1527

1559

1591

1623

1655

1016

1048

1080

1112

1144

1176

1208

1240

1272

1304

1336

1368

1400

1432

1464

1496

1528

1560

1592

1624

1656

1017

1049

1081

1113

1145

1177

1209

1241

1273

1305

1337

1369

1401

1433

1465

1497

1529

1561

1593

1625

1657

1018

1050

1082

1114

1146

1178

1210

1242

1274

1306

1338

1370

1402

1434

1466

1498

1530

1562

1594

1626

1658

1019

1051

1083

1115

1147

1179

1211

1243

1275

1307

1339

1371

1403

1435

1467

1499

1531

1563

1595

1627

1659

1020

1052

1084

1116

1148

1180

1212

1244

1276

1308

1340

1372

1404

1436

1468

1500

1532

1564

1596

1628

1660

1021

1053

1085

1117

1149

1181

1213

1245

1277

1309

1341

1373

1405

1437

1469

1501

1533

1565

1597

1629

1661

1022

1054

1086

1118

1150

1182

1214

1246

1278

1310

1342

1374

1406

1438

1470

1502

1534

1566

1598

1630

1662

1023

1055

1087

1119

1151

1183

1215

1247

1279

1311

1343

1375

1407

1439

1471

1503

1535

1567

1599

1631

1663

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ZHCSE90D –SEPTEMBER 2015 –REVISED SEPTEMBER 2020

表7-10. DLP6500 Pixel Mapping for D_B(x) (continued)

DCLK

EDGE

D_B(0) D_B(1)

D_B(2)

D_B(3)

D_B(4)

D_B(5) D_B(6)

D_B(7)

D_B(8)

D_B(9)

D_B(10) D_B(11) D_B(12) D_B(12) D_B(14) D_B(15)

54

55

56

57

58

59

60

61

62

63

1680

1712

1744

1776

1808

1840

1872

1904

1681

1713

1745

1777

1809

1841

1873

1905

1682

1714

1746

1778

1810

1842

1874

1906

1683

1715

1747

1779

1811

1843

1875

1907

1684

1716

1748

1780

1812

1844

1876

1908

1685

1717

1749

1781

1813

1845

1877

1909

1686

1718

1750

1782

1814

1846

1878

1910

1687

1719

1751

1783

1815

1847

1879

1911

1688

1720

1752

1784

1816

1848

1880

1912

1689

1721

1753

1785

1817

1849

1881

1913

1690

1722

1754

1786

1818

1850

1882

1914

1691

1723

1755

1787

1819

1851

1883

1915

1692

1724

1756

1788

1820

1852

1884

1916

1693

1725

1757

1789

1821

1853

1885

1917

1694

1726

1758

1790

1822

1854

1886

1918

1695

1727

1759

1791

1823

1855

1887

1919

Not visible

7.4.1.1 Data and Command Write Cycle

Once initialization completes (INIT_ACTIVE = 0), the user is free to send bit plane data and control information

to the DLPC910. The row write cycle begins with the assertion of DVALID. DVALID, all bit plane data, and all

DMD control information must be presented to the DLPC910 synchronous to the input clock DCLKIN. When the

user asserts a DVALID signal, the DLPC910 begins sampling the LVDS data inputs and control inputs and

synchronously sends this information to the DMD along with row address control information.

The DMD incorporates single row write operations using a row address counter that is randomly addressable.

The Row Mode and Row address must be presented synchronous to the DCLKIN at this beginning of each row

cycle. As shown in 表 7-1 and 表 7-2, ROWMD(1:0) determines the single row write count mode and

ROWAD(10:0) determines the single row write address. ROWMD and ROWAD must be asserted synchronously

with DVALID and must be valid synchronous to the beginning of the bit plane data as shown in 图7-6.

图 7-6 shows an example of data written to the DLPC910 for two consecutive row cycles. This diagram applies

to the DLPC910 for all compatible DMDs with a difference between DMD bus widths and number of clock cycles

per row. For the DLP9000X/DLP9000XUV DMDs, data is written to the DLPC910 64 bits on each clock edge (16

Bus A bits + 16 Bus B bits + 16 Bus C bits + 16 Bus D bits) for 20 clock cycles (N=40) to complete one row

cycle. For the DLP6500 DMD, only Bus A and Bus B are used (32 bits total) for 32 clock cycles (N=64) to

complete one row cycle. An entire row of data must be written for data to be properly latched into the DMD

memory. To complete the first row cycle (k), DVALID should be de-asserted (logic '0') two full clock cycles prior to

the completion of the row cycle. The assertion of DVALID back high ('1') indicates the beginning of the next row

cycle (k+1). For non-consecutive row cycles, keep DVALID low until the next row cycles is to begin, at which

point DVALID should be taken high to start the next row cycle. This is for all row cycle operations including No-

Op row cycles.

备注

Setting DVALID to LOW for the last clock cycle does not affect data read in the last two clock

transitions. The firmware will finish the correct number data reads from DIN_(A/B/C/D) for the specific

DMD, started by the rising edge of DVALID at the beginning of the row cycle.

34

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Row cycle k

Row cycle k+1

DCLKIN

DVALID

Low for last two

full clocks in row

ROWMD/ROWAD

BLK_MD/BLK_AD

NS_FLIP/COMP_DATA

4

0

1

2

3

N-6

N-5

0

N-4

N-3

N-2

N-1

1

DIN_A/B/C/D

图7-6. DLPC910 Input Consecutive Single Row Write Cycles

7.4.2 Block Mode Operation

The DMD mirrors and corresponding SRAM pixels are organized into blocks and each block is broken into rows

per BLK as described in 表 7-11. Mirror blocks are addressed for either the Mirror Clocking Pulse or Block Clear

functions by asserting block control signals at the start of each row data load. RST2BLKZ, BLKMD and BLKAD

are used as shown in 表7-12 to designate which mirror block(s) is to be issued a MCP or a Block Clear. Refer to

Related Documentation for the DMD datasheet regarding block location information.

• The clear operation sets all of the SRAM pixels in the designated block to logic zero during the current row

cycle.

• It is possible to issue a MCP to a block while loading a different block.

• It is not possible to clear a block while writing to a different block.

• It is not necessary to clear a block if it is going to be reloaded with new data (just like a normal memory cell).

• It is recommended that RST2BLKZ, COMP, and NS_FLIP be set to one value and not adjusted during normal

system operation.

• A change in RST2BLKZ is not immediately effective and will require more than one row load cycle to

complete.

备注

RST2BLK needs to be kept low during initialization for proper setup of the system. Dynamic changes

to RST2BLK during normal operation are not recommended.

表7-11. DMD Characteristics

ROWS PER CLKS PER

Required Output

LVDS Buses

Required Input

LVDS Buses

TYPE

COLS ROWS BLKS

#DATA IN

BLK

ROW

DLP9000X - 0.9 WQXGA

Type A

2560

1600

16

100

20

64

A, B, C, and D

DLP9000XUV - 0.9

WQXGA Type A

100

20

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表7-11. DMD Characteristics (continued)

ROWS PER CLKS PER

Required Output

LVDS Buses

Required Input

LVDS Buses

TYPE

COLS ROWS BLKS

1920 1080 15

#DATA IN

BLK

ROW

DLP6500 - 0.65 1080p

Type A and S600

72

32

A and B⁽¹⁾

or

A and B

C and D

(1) By default data and serial control outputs are active on buses A and B. Refer to 节7.5.1.9 to activate data and serial control outputs on

buses C and D.

表7-12. Block Operations

RST2BKLZ

BLKMD_1

BLKMD_2

BLKAD_3

BLKAD_2

BLKAD_1

BLKAD_0

OPERATION

None

X

0

1

0

1

0

1

X

0

1

0

1

0

X

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Clear block 00

Clear block 01

Clear block 02

Clear block 03

Clear block 04

Clear block 05

Clear block 06

Clear block 07

Clear block 08

Clear block 09

Clear block 10

Clear block 11

Clear block 12

Clear block 13

Clear block 14

Clear block 15 ⁽¹⁾

Reset block 00

Reset block 01

Reset block 02

Reset block 03

Reset block 04

Reset block 05

Reset block 06

Reset block 07

Reset block 08

Reset block 09

Reset block 10

Reset block 11

Reset block 12

Reset block 13

Reset block 14

Reset block 15 ⁽¹⁾

Reset blocks 00-01

Reset blocks 02-03

Reset blocks 04-05

Reset blocks 06-07

Reset blocks 08-09

Reset blocks 10-11

Reset blocks 12-13

Reset blocks 14-15

0

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表7-12. Block Operations (continued)

RST2BKLZ

BLKMD_1

BLKMD_2

BLKAD_3

BLKAD_2

BLKAD_1

BLKAD_0

OPERATION

1

X

1

0

1

0

1

0

1

0

1

0

1

X

Reset blocks 00-03

Reset blocks 04-07

Reset blocks 08-11

Reset blocks 12-15

Reset blocks 00-15

Float blocks 00-15

(1) Not applicable on DLP6500.

7.4.3 Block Clear

The DMD incorporates block clear operations using the BLKMD and BLKAD signals as shown in 表 7-12. The

block address does not automatically increment and must be set to the desired block to be cleared. The Block

clear operation writes logic zero data to all the SRAM cells in one DMD block regardless of the COMP_DATA

input state. It is not possible to clear a DMD block while writing to a different block. BLKMD and BLKAD are

asserted to perform a MCP on the block(s) that have been cleared. The customer interface should introduce a

delay on the last block(s) that were issued a MCP to allow the mirrors to become stable. Each Block Clear

operation must be followed by two no-op row load cycles. For the DLP9000X/DLP9000XUV there are 16

total Block Clear commands and 32 total no-op row cycles that are required to clear the entire DMD array. For

the DLP6500 there are 15 total Block Clear commands and 30 total no-op row cycles that are required to clear

the entire DMD array.

7.4.4 Mirror Clocking Pulse

A Mirror Clocking Pulse (MCP) sequence begins by asserting BLKMD and BLKAD for a single, dual, quad, or

global block operation as defined in 表 7-12. A MCP causes a reset on the block(s), and the data stored in the

block(s) takes effect on the mirrors of the DMD. Shortly after a MCP has been issued, RST_ACTIVE goes high

for approximately 4 μs, indicating a MCP operation is in progress. During this time, no additional MCPs may be

initiated until RST_ACTIVE returns low. RST_ACTIVE does not return to low unless continuous no-op or data

loading row cycles are issued. A typical single block load phased sequence in which consecutive DMD blocks

are loaded is illustrated in 图7-8. A MCP time is identical for single, dual, quad or global block operations.

Note that it may take longer to complete a MCP on a block than it does to load a block. The block load time may

be calculated as:

Block Load Time = Clock Period × number CLKS per ROW × number ROWS per BLK

表7-13. DMD Block Load Time

DMD

MINIMUM BLOCK LOAD TIME

DCLKIN (MHz)

DLP9000X

DLP9000XUV

DLP6500

4.167 µsec

480

400

4.167 µsec

5.76 µsec

For any case which involves sending a MCP or a Block Clear without data loading, the customer interface must

send no-op row cycles. This can be accomplished by asserting DVALID, while holding ROWMD at 00 and

BLKMD at 00 for the number of clocks per row in the DMD, as in 图7-7. Refer to 表7-11 to obtain the number of

clocks per row. Following the loading of all rows in a block or the entire DMD, at least one no-op row cycle must

be completed to initiate the MCP. If the MCP is asserted prior to loading all rows in a block or the entire DMD,

rows which were not updated will show old data. Additional MCP operations may not be initiated until

RST_ACTIVE is low. Block Clear operations for the DMD must be followed by two consecutive no-op row cycle

commands.

To obtain full utilization of the DMD bandwidth, load four blocks and then issue a MCP to the four blocks

concurrently by setting RST2BLKZ to 1 and BLKMD to 11 with the appropriate address in BLKAD. This is

illustrated in 图7-10.

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It is possible to load other blocks while the block(s) previously issued a MCP is settling. This is illustrated in 图

7-9 and 图 7-10, where blocks are reloaded while the mirror setting time is occurring. It is also possible to load

other blocks while previously loaded block(s) have an outstanding RST_ACTIVE. This is illustrated in 图 7-10,

where block 0 is loaded while RST_ACTIVE is asserted for blocks 12-15.

备注

While RST_ACTIVE is high for 4 μs, the data for the block(s) being issued a MCP should not be

changed to allow the mirrors to become stable. The RST_ACTIVE does not include the mirror settling

period. A short delay of 6 μs should be introduced during the last block(s) that is issued a MCP. The

mirror settling time is illustrated in 图 7-8, 图 7-9, 图 7-10, and 图 7-11, where the customer interface

introduces a delay on the last block(s) that were issued a MCP to allow the mirrors to become stable.

图 7-8, 图 7-9, 图 7-10, and 图 7-11 all show an exposure period. Once the customer interface has issued all

required MCPs and the proper mirror settling time has been applied, the customer interface may pulse an

illumination source onto the DMD during this period. The exposure period is user adjustable; however, increasing

the exposure period decreases the pattern rate. Refer to Application Curves regarding exposure period.

图 7-7, 图 7-8, 图 7-9, 图 7-10, and 图 7-11 show timing for the DLP9000X/DLP9000XUV. Refer to 表 7-11 to

obtain the number of reset blocks and clocks per row for the DLP6500 DMD.

0

1

37

38

39

DCLKIN

DVALID

00

ROWMD

BLK_MD

00

XXXX

BLK_AD

XXXX

图7-7. DMD No-op Row Cycle

Mirror

Settling Time

for Block 15

Exposure Period

Load Block 0

Load Block 15

Reset Block 14

Block 13

Block 12

Load Block 14

Reset Block 13

Load Block 1

Reset Block 0

DIN_A/B/C/D

Reset Block 15

BLK_MD/BLK_AD

RST_ACTIVE

图7-8. Single Block Load Phased Sequence

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Mirror Settling

Time for Blocks

14 and 15

Exposure Period

Load Block 1

Load Block 2

DIN_A/B/C/D

Load Block 15

Load Block 0

Reset Blocks 0-1

Reset Blocks 14-15

BLK_MD/BLK_AD

RST_ACTIVE

图7-9. Dual Block Load Phased Sequence

Mirror Settling

Time for Blocks

12 - 15

Exposure Period

Load Block 15

Load Block 2

Load Block 3

Load Block 4

DIN_A/B/C/D

Load Block 0

Load Block 1

Reset Blocks 12-15

BLK_MD/BLK_AD

RST_ACTIVE

Reset Blocks 0-3

图7-10. Quad Block Load Phased Sequence

Mirror Settling

Time for All

Blocks

Exposure Period

Load Block 1

Load Block 15

DIN_A/B/C/D

Load Block 0

Load Block 15

Load Block 0

Reset All

BLK_MD/BLK_AD

RST_ACTIVE

Reset All

图7-11. Full DMD Global Load Sequence

Note: After a MCP or Block Clear command is given, RST_ACTIVE may not be asserted until up to 60 ns

(depending on the clock frequency) after the command. While RST_ACTIVE is asserted, no other command

should be given.

7.4.5 DMD Array Subset

It is possible to use a subset of the DMD array including individual MCP blocks. The driving software/hardware

MUST ensure that the MCP rate for the number of blocks in the subset plus the mirror settling time does not

exceed 50 kHz.

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Load4 functionality is primarily intended to be used with global MCPs. However, it is possible to use a subset of

the DMD array including individual MCP blocks. The driving software/hardware MUST ensure that the MCP rate

for the number of blocks in the Load4 subset plus the mirror settling time does not exceed 50 kHz.

7.4.6 Global Mirror Clocking Pulse Consideration

A Global MCP (BLKMD = 11 and BLKAD = 10XX), takes the same amount of time as the single, dual, and quad

block MCP. In addition to requiring a no-op row cycle to initiate a global MCP, a row cycle (either no-op or data

loading) is also required to complete the operation. If the customer interface is monitoring RST_ACTIVE to

determine when to send a subsequent row cycle, it will never see RST_ACTIVE transition low. One method of

operation would be to continue sending no-op row cycles until RST_ACTIVE goes low then continue loading

data with real row cycles. Another method of operation is to delay greater than 10 μs, then start loading new

data to DMD.

7.5 Register Map

7.5.1 Register Table Overview

表 7-14 lists the I²C accessible memory mapped registers for the DLPC910. Access to the I²C registers should

not begin until INIT_ACTIVE has transitioned low (logic 0).

表7-14. Communication Registers

ADDRESS

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

REGISTER NAME

DESCRIPTION

SIZE

DESTOP_INTERRUPT

DESTOP Interrupt Status

32

MAIN_STATUS

DESTOP_CAL

Main Status

32

DESTOP input calibration status

Connected DMD Type

DESTOP_DMD_ID_REG

DESTOP_CATBITS_REG

DESTOP_910VERSION_REG

DESTOP_RESET_REG

DESTOP_INFIFO_STATUS

DESTOP_BUS_SWAP

DESTOP_DMDCTRL

DESTOP_BIT_FLIP

Connected DMD fuse catalog bits

DLPC910 Version Number

Reset status signals

Input interface FIFO status

Output bus swap

DMD Control Register

Output data bus bit reversal/flip

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7.5.1.1 DESTOP_INTERRUPT Register

The DESTOP_INTERRUPT register is used for controlling the interrupt source. Interrupts can be enabled,

disabled, cleared and read independently.

表7-15. DESTOP_INTERRUPT Register

ADDRESS ^{(1) (2) (3) (4)}

BITS

DESCRIPTION

RESET

0x0

TYPE

R/W

R

0

1

SPARE

0x0

A DMD IRQZ event occurred. The only existing source for this event is a

DMD power fault indicating bias, offset, or reset power supplies have

become inactive. The cause of the fault should be determined and

resolved prior to a system reset to continue operation. ⁽⁵⁾

0x0000

0x0004

0x0008

2

0x0

R/W

3

SPARE

0x0

R

31:4

UNUSED

(1) Interrupt status can be obtained by reading 0x0000 or 0x0004 address.

(2) Interrupt bits are asserted either by the corresponding H/W events or by S/W writing a 1 to the target bit of 0x0004 address.

(3) Interrupt bits are cleared by S/W writing a 1 to the target bit in 0x0000 address.

(4) Interrupts are enabled by setting the appropriate bits in register 0x0008.

(5) This bit must be cleared after a power cycle or a reset to the DLPC910.

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7.5.1.2 MAIN_STATUS Register

The MAIN_STATUS register is used for reading the status of the DLPC910. The register can be polled during

operation to obtain the current state of the DLPC910.

表7-16. MAIN_STATUS Register

ADDRESS

BITS

DESCRIPTION

DMD initialization in progress flag

0 - No DMD initialization activity

RESET

TYPE

0

0x0

R

1 - DMD initialization in progress

DMD initialization in progress flag 1

0 - No DMD stage 1 initialization activity

1 - DMD stage 1 initialization activity in progress

DMD initialization in progress flag 2

0 - No DMD stage 2 initialization activity

1 - DMD stage 2 initialization activity in progress

DMD supports AB channels

1

2

0x0

R

3

0 - Operation of DMD AB buses not enabled

1 - Operation of DMD AB buses enabled

DMD supports CD channels

4

0 - Operation of DMD CD buses not enabled

1 - Operation of DMD CD buses enabled

Input interface calibration in progress

0 - Input interface calibration inactive

1 - Input interface calibration in progress

DVALID alignment on interface A ok

0 - DVALID alignment invalid on channel A

1 - DVALID alignment correct on channel A

DVALID alignment on interface B ok

0 - DVALID alignment invalid on channel B

1 - DVALID alignment correct on channel B

DVALID alignment on interface C ok

0 - DVALID alignment invalid on channel C

1 - DVALID alignment correct on channel C

DVALID alignment on interface D ok

0 - DVALID alignment invalid on channel D

1 - DVALID alignment correct on channel D

System PLL locked flag

5

0x000C

6

7

8

9

10

0 - PLL not locked

1 - PLL locked

Reference PLL locked flag

11

0 - PLL not locked

0x0

R

1 - PLL locked

31:12

UNUSED

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7.5.1.3 DESTOP_CAL Register

The DESTOP_CAL register is used for reading the calibration state of the LVDS input buses of the DLPC910.

The calibration occurs during the initialization after power is applied to the DLPC910.

表7-17. DESTOP_CAL Register

ADDRESS

BITS

DESCRIPTION

Input Channel A Calibration complete:

0 - Channel A Calibration in progress

1 - Channel A Calibration complete

Input Channel B Calibration complete:

0 - Channel B Calibration in progress

1 - Channel B Calibration complete

Input Channel C Calibration complete:

0 - Channel C Calibration in progress

1 - Channel C Calibration complete

Input Channel D Calibration complete:

0 - Channel D Calibration in progress

1 - Channel D Calibration complete

UNUSED

RESET

TYPE

0

0x0

R

1

2

0x0

R

0x0010

3

0x0

R

31:04:00

7.5.1.4 DESTOP_DMD_ID_REG Register

The DESTOP_DMD_ID_REG register is used for reading the identification of the DMD Type connected to the

DLPC910. If the DLPC910 determines the DMD is not supported, the DLPC910 will halt all operations. See 表

7-4 for more information on valid DMD types.

表7-18. DESTOP_DMD_ID_REG Register

ADDRESS

BITS

DESCRIPTION

RESET

0x0

TYPE

Read-only register containing the DMD Type as provided

on input pins DMD_TYPE_[3:0]

3:0

R

0x0014

31:4

UNUSED

0x0

7.5.1.5 DESTOP_CATBITS_REG Register

The DESTOP_CATBITS_REG register is used for reading the remainder of identification of the DMD connected

to the DLPC910. If the DLPC910 determines the DMD is not supported, the DLPC910 will halt all operations.

表7-19. DESTOP_CATBITS_REG Register

ADDRESS

BITS

DESCRIPTION

RESET

0x0

TYPE

Read-only register containing the 4 remaining ID bits of

the connected DMD.

3:0

R

0x0018

31:4

UNUSED

0x0

7.5.1.6 DESTOP_VERSION Register

The DESTOP_VERSION is used for obtaining the DLPR910 PROM configuration program version.

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表7-20. DESTOP_VERSION Register

DESCRIPTION

(Read-only register of the DLPC910 version number)

ADDRESS

BITS

RESET

3:0

7:4

Major

0x1

0x0

R

Minor

0x001C

15:8

31:16

Revision

UNUSED

The Major version identifier bits "DESTOP_VERSION(2:0)" are also mirrored on the hardware output bits

DDC_Version(2:0). Since the DLPC910 firmware is configured by the binary data from the DLPR910 PROM at

power up/initialization, the version identifiers for each revision are found in the DLPR910 datasheet. See the

DLPR910 datasheet for more information on the DDC_VERSION and DESTOP_VERSION expected values.

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7.5.1.7 DESTOP_RESET_REG Register

The DESTOP_RESET_REG register is used for reading the current state of the MCP. Reading this register while

the DLPC910 is loading data to the DMD may always indicate a “1”. It is best to monitor the actual

RST_ACTIVE output signal of the DLPC910 to obtain the real state of the MCP.

表7-21. DESTOP_RESET_REG Register

ADDRESS

BITS

0

DESCRIPTION

RESET

0x0

TYPE

RESET Operation in progress bit: (Mirror clocking pulse)

0 - Reset inactive

R

0x0020

1 - Reset active

31:1

UNUSED

0x0

7.5.1.8 DESTOP_INFIFO_STATUS Register

The DESTOP_INFIFO_STATUS register is used for validating there is data in the input bus FIFO buffers. An

empty FIFO buffer may indicate that the DVALID is not properly set for the data on the input data bus.

表7-22. DESTOP_INFIFO_STATUS Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

Channel A input FIFO status:

0

0 - Channel A FIFO has data

1 - Channel A FIFO is empty

0x0

R

Channel B input FIFO status:

0 - Channel B FIFO has data

1 - Channel B FIFO is empty

1

2

0x0

R

0x0024

Channel C input FIFO status:

0 - Channel C FIFO has data

1 - Channel C FIFO is empty

Channel D input FIFO status:

0 - Channel D FIFO has data

1 - Channel D FIFO Is empty

3

0x0

R

31:4

UNUSED

7.5.1.9 DESTOP_BUS_SWAP Register

The DESTOP_BUS_SWAP register is used for configuring the DLPC910 output LVDS buses to the DMD. To

simplify board layout design, swapping the buses may reduce routing constraints. If the buses are swapped in

hardware, then the appropriate setting that matches the hardware must be set after a power cycle or a reset to

the DLPC910.

表7-23. DESTOP_BUS_SWAP Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

Enables Bus swap for A and B output DMD buses. SCTRLs

for A and B output buses are also swapped.

0 = un-swapped (default)

0

0x0

R/W

1 = swapped

Enables Bus swap for C and D output DMD buses. SCTRLs

for C and D output buses are also swapped.

0 = un-swapped (default)

1

0x0

R/W

1 = swapped

0x0028

3:2

7-4

UNUSED

0x0

R

Enable data and serial control output on buses. Valid only

when DLPC910 is connected to a DLP6500 DMD.

0 = A and B active (default). C and D are deactivated.

1 = C and D active. A and B are deactivated.

8

0x0

R/W

R

31:9

UNUSED

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7.5.1.10 DESTOP_DMDCTRL Register

The DESTOP_DMDCTRL register can be used in place of the external DLPC910 control inputs to control the

functions described. Bit-0 must be set to “1”to gain control of the functions. Bit-5 is available regardless of the

state of bit-0.

表7-24. DESTOP_DMDCTRL Register

ADDRESS

BITS

DESCRIPTION ⁽¹⁾

RESET

TYPE

Enables DMD control of the functions that are normally

controlled on external pins.

0

0x0

R/W

0 = Controlled from external pins (default)

1 = Controlled from the I²C interface

NS_FLIP. Sets the orientation of the top and bottom of the

DMD.

1

2

0x0

R/W

0 = Un-flipped (default)

1 = Flipped

DATA_COMP. Sets a DMD mode that inverts all of the

incoming data.

0x002C

0 = Normal (default)

1 = Data is inverted at the DMD

LOAD_FOUR. Activates the Load4 function of the DMD.

Each row written is loaded to 4 consecutive locations.

3

4

0x1

R/W

0 = Load4 mode is active

1 = Normal (default)

RST2BLKZ. Activates the RST2BLKZ function of the DMD.

Refer to 表7-12 for setting RST2BLKZ.

(1) When bit 0 is set to 1, bits 1, 2, 3, and 4 override their respective external control inputs.

7.5.1.11 DESTOP_BIT_FLIP Register

The DESTOP_BIT_FLIP register is used for configuring the DLPC910 output LVDS buses to the DMD. To

simplify board layout design, flipping individual buses may reduce routing constraints. If the buses are flipped in

hardware, then the appropriate setting that matches the hardware must be set after a power cycle or a reset to

the DLPC910.

表7-25. DESTOP_BIT_FLIP Register

ADDRESS

BITS

DESCRIPTION

Reverses the Data bits for bus A (b'15 = b'0, b'0 = b'15)

0 = un-flipped (default)

RESET

TYPE

0

0x0

R/W

1 = flipped

Reverses the Data bits for bus B (b'15 = b'0, b'0 = b'15)

0 = un-flipped (default)

1

2

0x0

R/W

1 = flipped

0x0030

Reverses the Data bits for bus C (b'15 = b'0, b'0 = b'15)

0 = un-flipped (default)

1 = flipped

Reverses the Data bits for bus D (b'15 = b'0, b'0 = b'15)

0 = un-flipped (default)

3

0x0

R/W

R

1 = flipped

31:4

UNUSED

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not

warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components

for their purposes. Customers should validate and test their design implementation to confirm system

functionality.

8.1 Application Information

The DLPC910 controller verifies the DMD connected in the application system, uses that information to select

appropriate configuration data for the DMD, and then initializes the DMD to ready it for operation.

The DLPC910 controller receives streaming parallel input data and associated syncs from an external

applications processor and passes the data on to the DMD with the appropriate DMD timing and control

information. It also receives embedded instructions from the applications processor to assist in determination of

which DMD rows to load and which DMD mirror blocks to activate at any given moment in time.

8.2 Typical Application

Direct-write digital imaging is regularly used in high-end lithography printing. This mask-less technology offers

continuous run of printing by changing the digitally created patterns without stopping the imaging head. The

DLPR910 PROM configures the DLPC910 digital controller to reliably operate with the DLP9000X, the

DLP9000XUV, or the DLP6500 DMD. These chipset combinations provide an ideal back-end imager that takes

in digital images at [2560 × 1600] or [1920 x 1080] resolution to achieve speeds greater than 61 Gigabits per

second (Gbps) and 24 Gbps respectively.

8.2.1 High Speed Lithography Application

As high-end lithography pushes the high speed printing envelope, providing a higher resolution imager is a must

to achieve the demanding through-put of present and future printing technology. 图 8-1 and 图 8-2 show two

systems that offer both a speed boost and a four million and two million pixel DMDs. The main chipset

components that make up these systems are the DLPC910ZYR, the DLPR910, and one of the DLP9000X,

DLP9000XUV, or DLP6500 DMDs. With a few additional discrete components for power regulation and clock

circuitry, a compact, and yet high performance design can be achieved.

图8-1. Typical DLP9000X/DLP9000XUV High Speed Application

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图8-2. Typical DLP6500 High Speed Application

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8.2.1.1 Design Requirements

The DLPC910 interface is made up of several buses and controls signals as shown in the following list. The

LVDS input buses provide the means of loading data to the DLPC910. The LVDS output buses provide the data

to the DMD. Each input and output LVDS bus has an associated clock which clocks the data into the DLPC910

or into the DMD. Row and Block control signals define the type of mirror clock pulse to use after all the data is

loaded into the DMD. Refer to 表7-11 to obtain the required LVDS buses for each DMD supported.

• LVDS differential inputs

– DDC_DCLK 4 buses

– DVALID 4 buses

– DDC_DIN 4 buses

• LVDS differential outputs. Refer to LVDS Output Bus Skew for recommendations on trace lengths.

– DDC_DOUT 4 buses

– DDC_DCLKOUT 4 buses

– DDC_SCTRL 4 buses

• Control output signals

– DMD RESET

– DMD SCP

• Row and Block control input signals

– ROWMD

– ROWAD

– BLKMD

– BLKAD

– RST2BLKZ

• Control input signals

– COMP_DATA

– NS_FLIP

– WDT_ENBLZ

– PWR_FLOAT

– LOAD4_ENZ

• Status output signals

– RST_ACTIVE

– INIT_ACTIVE

– ECP2_FINISHED

– DMD_IRQ

• Controller reset

– CTRL_RSTZ

• DLPR910 interface

– PGM(4:0)

– JTAG(3:0)

8.2.1.2 Detailed Design Procedure

After power is applied to the DLPC910, the APPS FPGA should monitor the ECP2_FINISHED signal to

determine when the DLPC910 has completed loading the configuration from the DLPR910. The APPS FPGA

next monitors the INIT_ACTIVE signal to determine when the DLPC910 has completed its internal initialization

routines and has configured the DMD for normal operation. An alternate method is to request the initialization

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status using the I²C interface. Information regarding initialization, versions, and IDs can be requested through

this interface.

Prior to activating the DVALID signals to the DLPC910, the ROWMD, ROWAD, BLKMD, BLKAD, and

RST2BLKZ control input signals must be in the desired state for the desired operation to take effect on the DMD.

Once the control signals are set, the Apps FPGA activates DVALID and starts loading data using the DDC_DIN

and DDC_DCLK buses. After all data is loaded for the desired DMD operation, the DVALID signal is de-

asserted, and the BLKMD, BLKAD, and RST2BLKZ control signals are set prior to the assertion of the next

DVALID. When DVALID is activated, the MCP causes the prior data to take effect on the mirrors of the DMD.

The Apps FPGA should then monitor the RST_ACTIVE pin to determine when the mirror clock pulse has

completed in order to perform the next MCP. During the time that the RST_ACTIVE is asserted, the Apps FPGA

could be loading data into DMD rows that do not belong to the same block of rows that currently has an

outstanding MCP.

8.2.1.3 Application Curves

In these particular applications, the performance plots shown in 图 8-3 and 图 8-4 show the maximum loaded

and displayed pixels per second when the exposure period is set to its minimum for the different reset modes.

When the exposure period is increased, the pixels per second will decrease. Refer to Mirror Clocking Pulse for

more information regarding exposure period.

图8-3. DLP9000X/DLP9000XUV Performance Plot at 480 MHz DDC_DCLK

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图8-4. DLP6500 Performance Plot at 400 MHz DDC_DCLK

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9 Power Supply Recommendations

9.1 Power Supply Distribution and Requirements

The DLPC910, the DLPR910, and one of the DLP9000X, DLP9000XUV, or DLP6500 DMDs are powered by a

power distribution method as shown in 图 9-1. The DMD power inputs will depend on which DMD is being used

in the application.

Power Management

12V

AC/DC

3.3V

3.45V

2.5V

1.0V

3.3V

1.8V

DLP9000X

DLP9000XUV

VCCO

VCC_AUX

VCC

VCC0

VCCINT

DLP6500

DLPR910

DLPC910

图9-1. Power Distribution

9.2 Power Down Requirements

For correct power down operation of the DMD, the following power down procedure must be executed.

Prior to an anticipated power removal, assert PWR_FLOAT for a minimum of 500 μs to allow the DLPC910 to

complete the power down procedure. This procedure will assure the DMD mirrors are in a flat state. Following

this 500 μs time delay, power can be safely removed from the DLP chipset as shown in 图9-2.

In the event of an unanticipated power loss, the power management system must detect the input power loss,

assert PWR_FLOAT to the DLPC910, and maintain all operating power levels to the DLPC910 and the DMD for

a minimum of 500 μs to allow the DLPC910 to complete the power down procedure.

To restart after assertion of PWR_FLOAT without removing power, the DLPC910 must be reset by setting

CTRL_RSTZ low (logic 0) for 50 ms, and then back to high (logic 1) as shown in 图 9-3, or power to the

DLPC910 must be cycled.

表9-1. Power Down Timing Requirements

PARAMETER

MIN

500

50

MAX

UNIT

µs

t_pf

t_cr

PWR_FLOAT high time.

CTRL_RSTZ low time.

ms

Minimum delay from PWR_FLOAT inactive

to CTRL_RSTZ active.

t_pc

0

ms

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t_pf

PWR_FLOAT

CTRL_RSTZ

¸ ¸

DC Power Supplies

图9-2. Removing Power After Asserting PWR_FLOAT

t_pc

t_pf

PWR_FLOAT

CTRL_RSTZ

¸ ¸

t_cr

¸ ¸

DC Power Supplies

图9-3. Restart Without Removing Power

10 Layout

10.1 Layout Guidelines

One of the most important factors to gain good performance is designing the PCB with the highest quality signal

integrity possible. The following PCB design guidelines provide a reference of an interconnect system.

10.1.1 PCB Design Standards

PCBs should be designed and built in accordance with the industry specifications shown in 表10-1.

表10-1. Industry Design Specifications

INDUSTRY SPECIFICATION

IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility

IPC-6011 and IPC-6012, Class 2

APPLICABLE TO

Board design

PWB fabrication

IPC-SM-840, Class 3, Color Green

Finished PWB solder mask

Finished PWB

UL94V-0 Flammability Rating and Marking

UL796 Rating and Marking

Finished PWB

PCB Fabrication:

• Configuration: Asymmetric dual strip-line

• Etch thickness : 1.0-oz copper (1.2 mil)

• Flex etch thickness: 0.5-oz copper (0.6 mil)

• Single-ended signal impedance: 50 Ω(±10%)

• Differential signal impedance: 100 Ω(±10%)

PCB Stack-up:

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• Ground planes for proper return path.

• Power planes for proper supply to circuits.

• Dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent, (Er): 3.8 (nominal).

10.1.2 Signal Layers

The PCB signal layers should follow typical good practice guidelines including:

• Layer changes should be minimized for single-ended signals.

• Individual differential pairs can be routed on different layers, but the signals of a given pair should not change

layers.

• Stubs should be avoided.

• Low-frequency signals should be routed on the outer layers.

• Differential pair signals should be routed first.

• Pin swapping on components is not allowed.

• Polarized capacitors should have the same orientation.

The PCB should have a solder mask on the top and bottom layers.

• The mask should not cover the vias.

• Except for fine pitch devices (pitch ≤0.032 inches). The copper pads and the solder mask cutout should be

of the same size.

• Solder mask between pads of fine pitch devices should be removed.

• In the BGA package, the copper pads and the solder mask cutout should be of the same size.

High-speed connectors that meet the following requirements should be used:

• Differential crosstalk: < 5%

• Differential impedance: 90 to 110 Ωfor all LVDS signal pairs

Routing requirements for right-angle connectors:

• When using right-angle connectors, LVDS signal P-N pairs should be routed in the same row to minimize

delay mismatch.

• When using right-angle connectors, propagation delay difference for each row should be accounted for on

associated PCB etch lengths.

10.1.3 General PCB Routing

Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad).

Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

10.1.3.1 Trace Minimum Spacing

BGA escape routing can be routed with 3.7-mils width and 4.3-mils spacing, as long as the escape nets are less

than 1-inch long, to allow two traces to fit between vias. After signals escape the BGA field, trace width should

be widened to achieve the desired impedance and spacing.

All single-ended 50-Ω signals must have a minimum spacing of 10 mils relative to other signals. Other special

trace spacing requirements are listed in 表10-2.

表10-2. Trace Minimum Spending

DIFFERENTIAL

SIGNAL

PWR

GND

SINGLE-ENDED ⁽¹⁾

UNIT

PAIRS

Pair-to-Pair ⁽²⁾

PWR

20 ⁽³⁾

10

15

5

15

5

mils

GND

CLKIN_R

15

5

30

DDC_DCLK_[A,B,C,D]_DP[N,P]

15

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表10-2. Trace Minimum Spending (continued)

DIFFERENTIAL

PAIRS

SIGNAL

PWR

GND

SINGLE-ENDED ⁽¹⁾

UNIT

mils

DDC_DCLKOUT_[A,B,C,D]_DP[N

,P]

15

5

30

DDC_DIN_[A,B,C,D]

[0:15]_DP[N,P]

15

DDC_DOUT_[A,B,C,D]

[0:15]_DP[N,P]

15

DDC_SCTRL_[A,B,C,D][N,P]

DVALID_[A,B,C,D]_DP[N,P]

Escape routing in ball field

All other signals

15

5

30

4.3

30

4.3

30

mils

(1) Signal spacing relative to other single-end signals.

(2) Signal spacing relative to other differential pairs.

(3) PWR relative to other power sources. Not same power source.

10.1.3.2 Trace Widths and Lengths

表10-3. Trace Widths and Lengths

MAXIMUM TRACE MISMATCH

SIGNAL

MIN WIDTHS

MAX LENGTHS ⁽²⁾

UNIT

N-to-P

Pair-to-pair

PWR

25

15 ⁽¹⁾

7

mils

GND

CLKIN_R

350

DDC_DCLK_[A,B,C,D]_DP[N,P]

DDC_DIN_[A,B,C,D][0:15]_DP[N,P]

DVALID_[A,B,C,D]_DP[N,P]

10

50 ⁽³⁾

Layout specific ⁽⁴⁾

Layout specific ⁽⁵⁾

DDC_DCLKOUT_[A,B,C,D]_DP[N,P]

DDC_DOUT_[A,B,C,D][0:15]_DP[N,P]

DDC_SCTRL_[A,B,C,D][N,P]

All other signals

50 ⁽³⁾

7

(1) Make width of GND trace as wide as the pin it is connected to, when possible.

(2) Signal routing length includes escape routing.

(3) Relative to its clock system. Refer to the Pin Functions Table to identify the clock system associated with the signals.

(4) Minimum widths to achieve impedance matching.

(5) Keep lengths as short as possible.

10.1.3.2.1 LVDS Output Bus Skew

To minimize instantaneous AC current switching in the DMD, the LVDS output bus trace lengths should differ to

produce a recommended 100-200 ps skew from one bus to another. 表10-4shows two examples how buses can

be skewed assuming 180-200 ps per 1000 mils. Keep in mind the total skew from one bus to another should be

kept below the maximum skew for the DMD. Refer to Related Documentation for the DMD datasheet regarding

maximum DMD LVDS input bus skew.

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表10-4. Example LVDS Output Bus Skew

Example 1

Example 2

Bus Group

DDC_DCLKOUT_A

UNIT

Bus Group Trace Lengths

DDC_DOUT_A

DDC_SCTRL_A

7454

5257

6936

5886

7454

5257

mils

DDC_DCLKOUT_B

DDC_DOUT_B

DDC_SCTRL_B

DDC_DCLKOUT_C

DDC_DOUT_C

DDC_SCTRL_C

DDC_DCLKOUT_D

DDC_DOUT_D

DDC_SCTRL_D

10.1.3.3 Trace Impedance and Routing Priority

For best performance, it is recommended that the trace impedance for differential signals as in 表10-5.

All signals should be 50-Ωcontrolled impedance unless otherwise noted in 表10-5.

表10-5. Trace Impedance

SIGNALS

DIFFERENTIAL IMPEDANCE

DDC_DCLK_[A,B,C,D]_DP[N,P]

100 Ω ± 10%

DDC_DCLKOUT_[A,B,C,D]_DP[N,P]

DDC_DIN_[A,B,C,D][0:15]_DP[N,P]

DDC_DOUT_[A,B,C,D][0:15]_DP[N,P]

DDC_SCTRL_[A,B,C,D][N,P]

DVALID_[A,B,C,D]_DP[N,P]

表10-6 lists the routing priority and layer assignments of the signals.

表10-6. Routing Priority

SIGNALS

PRIORITY

DDC_DCLKOUT_[A,B,C,D]_DP[N,P]

DDC_DOUT_[A,B,C,D][0:15]_DP[N,P]

DDC_SCTRL_[A,B,C,D][N,P]

1

2

3

4

DDC_DCLK_[A,B,C,D]_DP[N,P]

DDC_DIN_[A,B,C,D][0:15]_DP[N,P]

DVALID_[A,B,C,D]_DP[N,P]

BLKAD_[0:3], BLKMD_[0:1], ROWAD_[0:10], ROWMD_[0:1]

RESET_ADDR[0:3], RESET_MODE[0:1], RESET_SEL[0:1],

RESET_STROBE, RESET_OEZ, RESET_IRQZ, RESET_RSTZ

5

SCPCLK, SCPDI, SCPDO, DMD_SCPENZ

CLKIN_R

6

7

8

All other single-ended signals

10.1.4 Power and Ground Planes

The following are recommendations for best performance:

• Solid ground planes between each signal routing layer.

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• Solid power planes for voltages.

• Power and ground pins should be connected to these planes through a via for each pin.

• Trace lengths for the component power and ground pins should be minimized to 0.100 inches or less.

• Vias should be spaced out to avoid forming slots on the power planes.

• High speed signals should not cross over a slot in the adjacent power planes.

• Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of

devices.

10.1.5 Power Vias

Power and Ground pins of each component shall be connected to the power and ground planes with a via for

each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for

component power and ground pins should be minimized (ideally, less than 0.100 inch). Unused or spare device

pins that are connected to power or ground may be connected together with a single via to power or ground. The

minimum spacing between vias shall be 0.050 inch to prevent slots from being developed on the ground plane.

10.1.6 Decoupling

Decoupling capacitors must be located as near as possible to the DLPC910 voltage supply pins. Capacitors

should not share vias. The DLPC910 power pins can be connected directly to the decoupling capacitor (no via) if

the trace is less than 0.03 inches. Otherwise the component should be tied to the voltage or ground plane

through a separate via. All capacitors should be connected to the power planes with trace lengths less than 0.05

inches.

10.1.7 Flex Connector Plating

For designs using the Texas Instruments designed reference flex cable, plate all the pad area on the top layer of

flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of

100 micro-inches of electrolytic nickel.

10.2 Layout Example

The PCB layer design may vary depending on system design. However, careful attention is required to meet

design considerations. 表 10-7 shows a layer signal definition and 图 10-1 shows a PCB stack-up. The PCB

stack-up uses Hitachi 679gs as the dielectric material to improve the signal slew rate. Although the material

shown is Rogers Theta, it is the same material as the Hitachi 679gs.

表10-7. Layer Definition

Top:

2:

Signal

GND

3:

Signal

GND

4:

5:

Signal

GND

6:

7:

Signal

GND

8:

9:

Split Power

GND

10:

11:

12:

13:

14:

15:

16:

17:

Signal

GND

Signal

GND

Signal

GND

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表10-7. Layer Definition (continued)

Top:

Signal

Bottom:

Signal

Calc

Thickness

Description

Primary Stack

Layer

Dk / Df

Taiyo 4000-BN

½ oz Sig (std Plt)

Theta

½ oz P/G

Theta

2.70 / 0.0330

3.90 / 0.0097

3.97 / 0.0095

3.90 / 0.097

0.0005

0.0020

0.0030

Layer - 1

1078

0.0006

0.0050

(2-1080)

Layer - 2

Layer - 3

0.0006

0.0057

½ oz P/G

Theta

1078

0.0006

0.0050

Layer - 4

Layer - 5

½ oz P/G

Theta

0.0050

(2-1080)

3.97 / 0.0095

3.90 / 0.0097

3.97 / 0.0095

0.0006

0.0057

½ oz P/G

Theta

1078

½ oz P/G

Theta

0.0006

0.0050

0.0006

0.0050

(2-1080)

Layer - 6

Layer - 7

½ oz P/G

Theta

1078

0.0057

3.90 / 0.0097

0.0006

0.0035

Layer - 8

Layer - 9

½ oz P/G

Theta

0.0035

(1-3313)

3.98 / 0.0094

3.85 / 0.0100

0.0006

½ oz P/G

Theta

1037

0.0039

0.0006

0.0035

Layer - 10

Layer - 11

½ oz P/G

Theta

0.0035

(1-3313)

3.98 / 0.0094

3.90 / 0.0097

0.0006

½ oz P/G

Theta

1078

0.0057

0.0006

0.0050

Layer - 12

Layer - 13

½ oz P/G

Theta

0.0050

(2-1080)

3.97 / 0.0095

3.90 / 0.0097

0.0006

½ oz P/G

Theta

1078

0.0057

½ oz P/G

Theta

0.0006

0.0050

Layer - 14

Layer - 15

0.0050

(2-1080)

3.97 / 0.0095

3.90 / 0.0097

0.0006

½ oz P/G

Theta

1078

0.0057

½ oz P/G

Theta

0.0006

0.0050

Layer - 16

Layer - 17

0.0050

(2-1080)

3.97 / 0.0095

3.90 / 0.0097

0.0006

0.0030

½ oz P/G

Theta

1078

0.0020

0.0005

½ oz Sig (std Plt)

Taiyo 4000-BN

Layer - 18

2.70 / 0.0330

图10-1. PCB Stack-Up

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

表11-1. Part Number Description

TI PART NUMBER

DESCRIPTION

DLPC910ZYR

DLPC910 digital controller

11.1.2 Device Markings

Device markings are controlled by TI's supplier. TI packaging includes TI part number designation.

Pin 1

Logo

Family Brand

Device Type

Package Type

Speed Grade

Data Code

Lot Code

Operating Range

图11-1. DLPC910 Device Markings

11.2 Documentation Support

11.2.1 Related Documentation

The following documents contain additional information related to the chipset components used with the

DLPC910:

• DLPR910 PROM Data Sheet (DLPS065)

• DLP9000(X) DMD Data Sheet (DLPS036)

• DLP9000XUV DMD Data Sheet (DLPS036)

• DLP6500 Type A DMD Data Sheet (DLPS040)

• DLP6500 S600 DMD Data Sheet (DLPS053)

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

^®is a registered trademark of Texas Instruments.

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Virtex^®is a registered trademark of Xilinx, Inc.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC910ZYR
厂家：	TEXAS INSTRUMENTS
描述：	Digital controller for DLP6500FLQ, DLP6500FYE & DLP9000X/9000XUV digital micromirror devices \| ZYR \| 676 \| 0 to 85 外围集成电路
文件：	总63页 (文件大小：2955K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC910ZYR [TI]

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