DLPS026 [TI]

DLPR410 Configuration PROM;


型号：	DLPS026
厂家：	TEXAS INSTRUMENTS
描述：	DLPR410 Configuration PROM 可编程只读存储器
文件：	总21页 (文件大小：906K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPR410

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

DLPR410 Configuration PROM

1 Features

3 Description

•

Pre-programmed Xilinx^®PROM configures the

DLPC410ZYR DMD digital controller

I/O pins compatible with 1.8 V to 3.3 V

1.8 V core supply voltage

The DLPR410 device is a programmed PROM used

to properly configure the DLPC410ZYR Controller

to operate five different digital micromirror device

(DMD) options: DLP650LNIRFYL, DLP7000FLP,

DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN

DMDs. The firmware in this device enables the

DLPC410ZYR Controller to provide system data

throughput rates up to 48 Gigabits per second

(Gbps) with the options for random row addressing

and Load4 capabilities. Often this family of chips is

designed into high speed UV and NIR optical systems

such as direct imaging lithography, 3D printing and

laser marking equipment that need fast throughput

and pixel accurate control.

•

–40°C to 85°C operating temperature range

2 Applications

Lithography

•

Direct imaging

Flat panel display

Printed circuit board manufacturing

Industrial

•

3D printing

3D scanners for machine vision

Quality control

Get started with TI DLP® light-control technology

page to learn how to get started with the

DLPC410ZYR. The DLP advanced light control

resources on ti.com accelerate time to market, which

include evaluation modules, reference designs, optical

modules manufacturers, and DLP design network

partners.

Displays

•

3D imaging

Intelligent and adaptive lighting

Augmented reality and information overlay

Device Information⁽¹⁾

PART

NUMBER

PACKAGE

BODY SIZE (NOM)

DLPR410

DSBGA (48)

8.00 mm × 9.00 mm × 1.20 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

LEDs / LASERs /

PWMs/Triggers

LED/LASER/Lamp Driver

Lamp

Op cal Power Sense

Op cal Sensor

LVDS Data Bus(A,B)

LVDS Data Bus(C,D)

LVDS Data Bus

Row, Block Signals

Control Signals

DLPC410 Info Signals

DLPC410ZYR

DMDs

DLP650LNIR

DLP7000

DLP7000UV

DLP9500

DLPA200 Control

MBRST

JTAG

DLPA200

Clk

DONE

DLPA200 Control

SCP Bus

DLPR410

DLP9500UV

OSC

Power Management

TI Components

Figure 3-1. Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Supply Voltage Requirements for Power-On

Reset and Power-Down................................................ 7

6.7 Timing Requirements..................................................7

7 Detailed Description........................................................8

7.1 Overview.....................................................................8

7.2 Functional Block Diagram...........................................8

7.3 Feature Description.....................................................8

7.4 Device Functional Modes............................................9

8 Application and Implementation.................................. 11

8.1 Application Information..............................................11

8.2 Typical Application.................................................... 11

9 Power Supply Recommendations................................13

10 Layout...........................................................................13

10.1 Layout Guidelines................................................... 13

11 Device and Documentation Support..........................15

11.1 Device Support........................................................15

11.2 Documentation Support.......................................... 17

11.3 Receiving Notification of Documentation Updates..17

11.4 Support Resources................................................. 17

11.5 Trademarks............................................................. 17

11.6 Electrostatic Discharge Caution..............................17

11.7 Glossary..................................................................17

12 Mechanical, Packaging, and Orderable

Information.................................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (January 2020) to Revision G (August 2021)

Page

•

Updated all references to DLPC410 Controller in data sheet to DLPC410ZYR Controller................................ 1

Updated Applications List................................................................................................................................... 1

Updated Simplified Application Diagram in Description section......................................................................... 1

Moved Xilinx XCF specifications link to top of Specifications section.................................................................1

Removed numbers appended to all DNC signals in Pin Functions table........................................................... 4

Added entry for V_CCJto Absolute Maximum Ratings..........................................................................................6

Removed footnote reference to JEDEC Standard JESD22-A114A in ESD Ratings.......................................... 6

Added entry for V_CCJto Recommended Operating Conditions.......................................................................... 6

Updated DLPC410ZYR and DLPR410 Connection Schematic........................................................................10

Updated DLPR410 and DLPC410ZYR with DMD Example Block Diagram .................................................... 11

Added Application Curves section....................................................................................................................12

Added 0.047-μF decoupling capacitor to GND for all Power Pins in Power Supply Recommendations..........13

Added Layout Example section........................................................................................................................ 14

Added DLPR410BYVA to Device Compatibility table.......................................................................................15

Added DLPR410BYVA to Part Number Description table................................................................................ 15

Added DLPR410B Device Markings.................................................................................................................15

Changes from Revision E (December 2018) to Revision F (January 2020)

Page

•

Corrected Max Tstg per Xilinx data sheet ..........................................................................................................6

Pulled in specific layout information from referenced document and removed reference................................ 13

Corrected DDC_Version(3:0) bus width to DDC_Version(2:0). ....................................................................... 15

Changes from Revision D (April 2015) to Revision E (December 2018)

Page

•

Updated Applications and Description to include new DLP650LNIR, removed data transfer rate .................... 1

Corrected Min Tstg per Xilinx data sheet ...........................................................................................................6

Corrected Min VCCO per Xilinx data sheet ....................................................................................................... 6

Added support information for new DLP650LNIR DMD (multiple places).......................................................... 8

Updated Section 7.2 .......................................................................................................................................... 8

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

•

Corrected improper "DLPC910" reference to "DLPC410" ................................................................................11

Updated Figure 8-1 ..........................................................................................................................................11

Added Section 11.1.1 table...............................................................................................................................15

Updated Section 11.1.2 ....................................................................................................................................15

Updated Section 11.1.3 section........................................................................................................................15

Added DLP650LNIR to Table 11-2 section....................................................................................................... 17

Deleted DLP Discovery 4100 Chipset reference in Table 11-2 ........................................................................17

Changes from Revision C (March 2013) to Revision D (October 2015)

Page

•

Updated Features, Applications, and Description ..............................................................................................1

Deleted DLPR4101 (enhanced functionality PROM part number) throughout document ................................. 1

Added ESD Rating table, Feature Description section, Device Functional Modes, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1

Deleted 1.8 V and 3.3 V operation values from V_CCO, V_IL, and V_IH- this implementation is 2.5 V ....................6

Changed Device Marking Image ..................................................................................................................... 15

Deleted DLP® Discovery™ 4100 Chipset Datasheet from Related Documentation .......................................17

Added Link to XCF16P data sheet at xilinx.com ..............................................................................................17

•

Changes from Revision B (March 2013) to Revision C (April 2013)

Page

•

Added Top View of Device..................................................................................................................................1

Added DLPR4101 "Load 4" enhanced functionality to Features........................................................................ 1

Added DLPR410 and DLPR4101 (enhanced functionality PROM part number) to DLPR410 throughout

document ...........................................................................................................................................................1

Added a link to the data sheet............................................................................................................................ 1

Added the Version column to the Ordering Information table.............................................................................4

Updated DLPC and DLP7000 / DLP7000UV Embedded Example Block Diagram.......................................... 11

Added DLP7000UV and DLP9500UV well suited for direct imaging lithography, 3D printing, and UV

applications ......................................................................................................................................................12

Added DLPR4101YVA as equivalent to TI part number 2510442-0006 ..........................................................15

Added Reference to DLPC410 data sheet....................................................................................................... 15

Added DLPR410 to Figure 11-2 .......................................................................................................................15

Added Top View of Device to device marking ..................................................................................................15

Added DLP7000UV Related Documentation....................................................................................................17

Added DLP9500UV Related Documentation....................................................................................................17

•

Changes from Revision A (September 2012) to Revision B (March 2013)

Page

•

Changed the top-side marking in the Ordering Information table.......................................................................4

Changes from Revision * (August 2012) to Revision A (September 2012)

Page

•

Changed the device From: Product Preview To: Production.............................................................................. 1

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

5 Pin Configuration and Functions

Figure 5-1. YVA Package 48-Pin DSBGA Top View

Table 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

GND

NO.

Ground

GND

Output Enable/ RESET (Open-Drain I/O). When Low, this input holds the address

counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.

This is a bidirectional open-drain pin that is held Low while the PROM completes the

internal power-on reset sequence. Polarity is not programmable. Pin must be pulled

OE/ RESET

I/O

High using an external 4.7-kΩ pull-up to V_CCO

DNC

—

Do Not Connect. Leave unconnected.

VCCINT1

VCCO1

CLK

Positive 1.8-V supply voltage for internal logic.

Positive supply voltage connected to the output voltage drivers and internal buffers.

Do Not Connect. Leave unconnected.

Chip Enable Input. When CE is High, the device is put into low-power standby mode,

the address counter is reset, and the DATA and CLKOUT outputs are placed in a high

impedance state. Pin must be pulled High using an external 4.7-kΩ pull-up to V_CCO

—

Do Not Connect. Leave unconnected.

Ground

GND

BUSY

—

Do Not Connect. Leave unconnected.

Configuration clock output. Each rising edge on the CLK input increments the internal

address counter. Pin must be pulled High and Low using an external 100-Ω pull-up

to V_CCOand an external 100-Ω pull-down to Ground. Place resistors close to pin.

CLKOUT

—

DNC

—

Do Not Connect. Leave unconnected.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

Table 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

VCCO2

Positive supply voltage connected to the output voltage drivers and internal buffers.

Configuration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up

to V_CCO. Selects serial mode configuration.

CEO

—

Do Not Connect. Leave unconnected.

DNC

Do Not Connect. Leave unconnected.

DNC

Do Not Connect. Leave unconnected.

VCCO4

VCCINT2

TMS

Positive supply voltage connected to the output voltage drivers and internal buffers.

Positive 1.8-V supply voltage for internal logic.

JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to V_CCJ

Do Not Connect. Leave unconnected.

DNC

—

DNC

Do Not Connect. Leave unconnected.

DNC

Do Not Connect. Leave unconnected.

TDO

JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to V_CCJ.

GND

DNC

Ground

Do Not Connect. Leave unconnected.

Ground

DNC

GND

TDI

Ground

JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to V_CCJ

Do Not Connect. Leave unconnected.

DNC

—

REV_SEL0

Revision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins

are used to select the design revision to be enabled. The Revision Select [1:0] inputs

have an internal 50-kΩ resistive pull-up to V_CCO. The REV_SEL0 pin must be pulled

Low using an external 4.7-kΩ pull-down to Ground. The REV_SEL1 pin must be

pulled Low using an external 4.7-kΩ pull-down to Ground.

REV_SEL1

VCCO3

VCCINT3

GND

Positive supply voltage connected to the output voltage drivers and internal buffers.

Positive 1.8-V supply voltage for internal logic.

Ground

Positive 2.5-V JTAG I/O supply voltage connected to the TDO output voltage driver and

TCK, TMS and TDI input buffers.

VCCJ

JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and

all the JTAG test and programming electronics.

TCK

External Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to V_CCO

EN_EXT_SEL

The EN_EXT_SEL pin must be connected to Ground.

—

Do Not Connect. Leave unconnected.

DATA output pin to provide data for configuring the DLPC410ZYR in serial mode.

(1) P = Power, G = Ground, I = Input, O = Output

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

6 Specifications

For complete electrical and mechanical specifications of the DLPR410, see the XCF16P product specification

listed in Related Documentation.

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (see ^{(1) (2)}

)

MIN

–0.5

MAX

2.7

4.0

3.6

125

150

UNIT

V_CCINT

V_CCO

V_CCJ

Internal supply voltage

I/O supply voltage

Relative to ground

V_CCO< 2.5 V

JTAG I/O supply voltage

V_IN

Input voltage with respect to ground

V_CCO≥ 2.5 V

V_CCO< 2.5 V

V_TS

Voltage applied to high-impedance output

V_CCO≥ 2.5 V

T_J

Junction temperature

°C

T_stg

Storage temperature, ambient

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

(2) Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA. During transitions, the device pins can undershoot to

–2 V or overshoot to 7 V, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200

mA.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

V_(ESD)

2000

(2)

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.65

2.3

NOM

1.8

MAX

2.0

UNIT

V_CCINT

V_CCO

V_CCJ

V_IL

Internal voltage supply

Supply voltage for output drivers

JTAG I/O Supply voltage

Low-level input voltage

High-level input voltage

Output voltage

2.5-V operation

2.5

2.7

2.5

2.7

0.7

V_IH

1.7

3.6

V_O

V_CCO

500

t_IN

Input signal transition time (measured between 10% V_CCOand 90% V_CCO

Operating ambient temperature

)

°C

T_A

–40

6.4 Thermal Information

Refer to the XCF16P product specifications.

6.5 Electrical Characteristics

Refer to the XCF16P product specifications at www.xilinx.com.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

6.6 Supply Voltage Requirements for Power-On Reset and Power-Down

(see ⁽¹⁾

)

MIN

0.2

0.5

MAX

UNIT

t_VCC

V_CCPOR

t_OER

V_CCINTrise time from 0 V to nominal voltage ⁽²⁾

POR threshold for V_CCINTsupply

–

OE/ RESET release delay following POR ⁽³⁾

V_CCPD

Power-down threshold for V_CCINTsupply

0.5

Time required to trigger a device reset when the V_CCINTsupply drops below the

maximum V_CCPDthreshold

t_RST

(1) V_CCINT, V_CCO, and V_CCJsupplies can be applied in any order.

(2) At power-up, the device requires the V_CCINTpower supply to monotonically rise to the nominal operating voltage within the specified

t_VCCrise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See

Platform Flash PROM Power-Up Requirements, in the Xilinx XCF16P (v2.19) Product Specification for more information.

(3) If the V_CCINTand V_CCOsupplies do not reach their respective recommended operating conditions before the OE/ RESET pin is

released, then the configuration data from the PROM is not available at the recommended threshold levels. The configuration

sequence must be delayed until both V_CCINTand V_CCOhave reached their recommended operating conditions.

6.7 Timing Requirements

Refer to the XCF16P product specifications at www.xilinx.com.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

7 Detailed Description

7.1 Overview

The configuration bit stream stored in the DLPR410 device supports reliable operation of the DLPC410ZYR

device with the DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN DMDs.

DMDs. The DLPC410ZYR digital controller loads this configuration bit stream from the DLPR410 device.

7.2 Functional Block Diagram

TCK

TDI

TMS

OE/RESET

CLKOUT

CEO

TDO

DLPR410

EN_EXT_SEL

REV_SEL0

REV_SEL1

Figure 7-1. Functional Block Diagram

7.3 Feature Description

7.3.1 Data Interface

7.3.1.1 Data Outputs

The DLPR410 device is configured for serial mode operation, where D0 is the data output pin. D0 output

pin provides a serial connection to the DLPC410ZYR controller, where the configuration is read out by the

DLPC410ZYR controller.

7.3.1.2 Configuration Clock Input

The configuration CLK is connected to the DLPC410ZYR controller in Primary Serial mode, where the

DLPC410ZYR controller provides the clock pulses to read the configuration from the DLPR410 device.

7.3.1.3 Output Enable and Reset

When the OE/ RESET input is held low, the address counter is reset and the Data (D0) and CLKOUT outputs

are placed in high-impedance state. OE/ RESET must be pulled High using an external 4.7-kΩ pull-up to

V_CCO

7.3.1.4 Chip Enable

The CE input is asserted by the DLPC410ZYR controller to enable the Data (D0) and CLKOUT outputs. When

CE is held high, the DLPR410 device address counter is reset, and the Data and CLKOUT outputs are placed in

high-impedance states.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

7.3.1.5 Configuration Pulse

The DLPR410 device is configured in serial mode when it holds configuration pulse pin, CF, high and it enables

the CE and OE pins. New data is available a short time after each rising clock edge.

7.3.1.6 Revision Selection

The device uses the REV_SEL0, REV_SEL1, and EN_EXT_SEL signals to select a revision to act as the

default. Setting all three signals to GND defaults to revision 0 for simple DLPR410 device setup.

7.4 Device Functional Modes

To successfully program the DLPC410ZYR controller upon power-up, the DLPR410 device must be configured

and connected to the DLPC410ZYR controller as shown in Figure 7-2.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

VCC_2P5V

VCC_1P8V

Master Serial

Config Mode

M0_0 W18

M2_0 V18

M1_0 Y17

DDC_M0

Y9 VCC_0_1

VCC_0_2

CLK

W12

CLKOUT

OE/RESET

PROG

JTAG

MODE

D_IN_0 K11

CCLK_0 J10

DONE_0 K10

INT_B_0 J11

PROM_D0_DDC

PROM_CCK_DDC

DONE_DDC

DNC11 D4

BUSY

N14 VP_0

VN_0

DNC10 D3

DNC9 G2

DNC8 F4

DNC7 F3

DNC6 F2

DNC5 E4

DNC4 E3

DNC3 C4

DNC2 C3

DNC1 A4

P13

INTB_DDC

R14 DXP_0

R13 DXN_0

CS_B_0 N18

PROGRAM _B_0 J18

RWDR_B_0 P18

D_OUT_BUSY_0 W11

HSWAPEN_0 L18

PROGB_DDC

DLPR410

M14 AVDD_0

M13 AVSS_0

P14

VREFP_0

N13 VREFN_0

TCK_0 U11

TMS_0 V12

TDI_0 V11

TDO_0 W10

TCK_JTAG

TMS_JTAG

TDO_XCF16DDC

TDO_DDC

REV_SEL0

REV_SEL1

EN_EXT_SEL

CEO

TMS

TDO

TDI

TMS_JTAG

TDO_XCF16DDC

TDI_DDC

R18 RSVD7

T18

RSVD8

TCK

TCK_JTAG

DLPC410ZYR

Figure 7-2. DLPC410ZYR and DLPR410 Connection Schematic

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The DLPR410 device configuration PROM ships pre-programmed with configuration code for the DLPC410ZYR

controller. Upon power-up, the DLPC410ZYR controller and the DLPR410 device connect to enable

configuration information to be sent from the DLPR410 device to the DLPC410ZYR controller, such that the

DLPC410ZYR controller can configure itself for proper operation within the application. Without the DLPR410

device properly connected to the DLPC410ZYR controller in the application system, the DLPC410ZYR controller

does not boot and the system remains inoperable.

8.2 Typical Application

A typical embedded system application using the DLPR410 device to program the DLPC410 controller (to drive

one of 5 different DMDs) is shown in Figure 8-1. For complete details of this typical application refer to the

DLPC410 controller data sheet listed in Table 11-2.

LEDs / LASERs /

Lamp

PWMs/Triggers

LED/LASER/Lamp Driver

Op cal Sensor

Op cal Power Sense

LVDS Data Bus(A,B)

LVDS Data Bus(C,D)

LVDS Data Bus

Row, Block Signals

Control Signals

DLPC410 Info Signals

JTAG

DLPC410ZYR

DMDs

DLP650LNIR

DLP7000

DLP7000UV

DLP9500

DLP9500UV

DLPA200 Control

MBRST

DLPA200

Clk

DLPA200 Control

SCP Bus

DLPR410

DONE

OSC

Power Management

TI Components

Figure 8-1. DLPR410 and DLPC410ZYR with DMD Example Block Diagram

8.2.1 Design Requirements

The DLPR410 is part of a multi-chipset solution, and it is required to be coupled with the DLPC410ZYR

controller for reliable operation of the DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and,

DLP9500UVFLN DMDs. DMDs. For more information, refer to the DLPC410ZYR datasheet listed in Section

11.2.1.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

8.2.2 Detailed Design Procedure

The DMDs are designed to be operated by the DLPC410ZYR Digital Controller:

•

The DLP7000FLP and DLP9500FLN DMDs are well suited for visible light applications requiring fast, spatially

programmable light patterns using the micromirror array.

The DLP7000UVFLP and DLP9500UVFLN DMDs are well suited for direct imaging lithography, 3D printing

applications, and other applications requiring ultraviolet light (UVA).

The DLP650LNIRFYL DMD enables high-power NIR laser illumination for dynamic digital printing, sintering

and marking solutions.

Connections between the DLPC410ZYR Digital Controller, the DLPR410 Configuration PROM, and the

DLPA200 DMD micromirror driver(s) must follow the layout guidelines for reliability.

8.2.3 Application Curves

Figure 8-2. DLP7000 and DLP9500 Transmittance

Figure 8-3. DLP7000UV and DLP9500UV

Transmittance (UV Window)

(Visible Window)

100

AOI = 0°

600

800

1000

1200

1400

1600

1800

2000

Wavelength (nm)

Figure 8-4. DLP650LNIR Transmittance (NIR Window)

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

9 Power Supply Recommendations

The DLPR410 uses two power supply rails as shown in Table 9-1.

Table 9-1. DLPR410 Power Supply Rails

SUPPLY

POWER PINS

COMMENTS

All V_CCINTpins must be connected with a 0.1-µF and a

0.047-μF decoupling capacitor to GND.

1.8 V

V_CCINT1, V_CCINT2, and V_CCINT3

All V_CCOand V_CCJpins must be connected with a 0.1-

µF and a 0.047-μF decoupling capacitor to GND.

2.5 V

V_CCO1,V_CCO2,V_CCO3, V_CCO4, and V_CCJ

10 Layout

10.1 Layout Guidelines

The DLPR410 is part of a multi-chipset solution. It is required to be used with the DLPC410ZYR Controller to

provide reliable control of any attached DMDs. These guidelines are targeted at designing a PCB board with the

DLPR410.

10.1.1 Component Placement

The DLPR410 must be placed adjacent to the DLPC410ZYR Controller with a maximum electrical distance of 4

inches (10 cm).

10.1.2 Impedance Requirements

Signals between the DLPR410 and the DLPC410ZYR Controller must be routed to have a matched impedance

of 50 Ω ±10%.

10.1.3 PCB Signal Routing

When designing a PCB board which includes the DLPR410 and the DLPC410ZYR Controller, the following are

recommended:

Signal trace corners must be no sharper than 45°. Adjacent signal layers must have the predominate traces

routed orthogonal to each other.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces must not cross over slots in adjacent power and/or ground planes.

10.1.4 Fiducials

Fiducials for automatic component insertion must be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials

for optical auto insertion are placed on three corners of both sides of the PCB.

10.1.5 PCB Decoupling Guidelines

Decoupling capacitors must be utilized to provide instantaneous current sources to components and to help

mitigate ground bounce.

10.1.5.1 Bulk Decoupling

Bulk decoupling capacitors for the board must be distributed around the PCB and be sized to handle the current

demands for the board.

10.1.5.1.1 DLPR410 Decoupling Capacitors

Decoupling capacitors (0.1 µF recommended) are placed to minimize the distance from the decoupling capacitor

to the supply and ground pins of the component. It is recommended that the placement of and routing for the

decoupling capacitors meet the following guidelines:

•

The supply voltage pin of the capacitor must be located close to the device supply voltage pin(s). The

decoupling capacitor must have vias to ground and voltage planes. The device can be connected directly to

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component must be

tied to the voltage or ground plane through separate vias.

•

The trace lengths of the voltage and ground connections for decoupling capacitors and components must be

less than 0.1 inch to minimize inductance.

The trace width of the power and ground connection to decoupling capacitors and components must be as

wide as possible to minimize inductance.

Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance

and improve noise performance. Via sharing between components (discreet or integrated) is discouraged.

Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

10.1.6 Layout Example

Please refer to the DLPLCRC410EVM Design files for an example of how to layout the DLPR410 Configuration

PROM.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Compatibility

TI PART NUMBER

DLPR410YVA

DDC_Version(2:0)⁽²⁾

Compatible DMDs ⁽¹⁾

DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN DMDs.

DLPR410AYVA

DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN

DMDs.

DLPR410BYVA

DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN

DMDs.

(1) Refer to each individual DMD datasheet under Device and Documentation Support for more DMD information.

(2) Refers to the DDC_Version(2:0) output pins of the DLPC410 Controller once configured by this Configuration PROM. See the

DLPC410 datasheet (DLPS024) for more information.

11.1.2 Device Nomenclature

The device nomenclature is as shown in Figure 11-1. The part number description for previously and currently

available part numbers is shown in Table 11-1.

DLPR410 A YVA

Package Type

Revision

Device Descriptor

Figure 11-1. Device Nomenclature

Table 11-1. Part Number Description

TI PART NUMBER

DLPR410YVA

DESCRIPTION

REFERENCE NUMBER

2510442-0005

DLPR410 Configuration PROM

DLPR410AYVA

DLPR410BYVA

DLPR410A Configuration PROM (Added compatibility with DLP650LNIR)

DLPR410B Configuration PROM (Compatibile with DLP650LNIR)

DLPR410AYVA

DLPR410BYVA

11.1.3 Device Markings

Figure 11-2 shows the previous device marking for the DLPR410 device. For the DLPR410A and DLPR410B,

this device marking nomenclature has been updated to use the DLPR410A and DLPR410B device part numbers

instead of the previous 2510442 marking, as shown in Figure 11-3 and Figure 11-4.

2510442-0005

YY/WW

Pin 1

Figure 11-2. DLPR410 Device Markings

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

DLPR410A

YVA YY/WW

Pin 1

Figure 11-3. DLPR410A Device Markings

DLPR410B

YVA YY/WW

Pin 1

Figure 11-4. DLPR410B Device Markings

Where YY/WW is the year/week the part was programmed.

Submit Document Feedback

Product Folder Links: DLPR410

DLPR410

www.ti.com

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

Table 11-2. Related Documentation

DOCUMENT

TI LITERATURE NUMBER

DLP650LNIR 0.65 NIR WXGA S450 DMD data sheet

DLP7000 DLP 0.7 XGA 2xLVDS Type A DMD data sheet

DLP7000UV DLP 0.7 UV XGA 2xLVDS Type-A DMD data sheet

DLP9500 DLP 0.95 1080p 2xLVDS Type-A DMD data sheet

DLP9500UV DLP 0.95 UV 1080p 2xLVDS Type-A DMD data sheet

DLPA200 DMD Micromirror Driver data sheet

DLPS136

DLPS026

DLPS061

DLPS025

DLPS033

DLPS015

DLPC410 DMD Digital Controller data sheet

DLPS024

XCF16P data sheet

available at www.xilinx.com

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Xilinx^®is a registered trademark of Xilinx, Inc.

All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this datasheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: DLPR410

PACKAGE OPTION ADDENDUM

www.ti.com

15-Aug-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLPR410AYVA

DLPR410BYVA

ACTIVE

DSBGA

YVA

TBD

Call TI

-40 to 85

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

15-Aug-2021

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DLPS026 [TI]

相关型号：

DLPS033

DLPS061

DLPSLDM-100

DLPSLDM-1000

DLPSLDM-150

DLPSLDM-200

DLPSLDM-250

DLPSLDM-300

DLPSLDM-350

DLPSLDM-400

DLPSLDM-450

DLPSLDM-500