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DM3730_14 [TI]

Digital Media Processors;
DM3730_14
型号： DM3730_14
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Digital Media Processors
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DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
DM3730, DM3725  
Applications Processor  
Check for Samples: DM3730, DM3725  
1 DM3730, DM3725 Applications Processor  
1.1 Features  
1234  
•
Additional C64x+TM Enhancements  
• DM3730/25 Applications Processor:  
– Compatible with OMAP™ 3 Architecture  
– MPU Subsystem  
–
–
Protected Mode Operation  
Expectations Support for Error  
Detection and Program Redirection  
•
•
Up to 1-GHz ARM CortexTM-A8 Core  
NEON SIMD Coprocessor  
–
Hardware Support for Modulo Loop  
Operation  
– High Performance Image, Video, Audio  
– C64x+TM L1/L2 Memory Architecture  
(IVA2.2TM) Accelerator Subsystem  
Up to 800-MHz TMS320C64x+TM DSP Core  
Enhanced Direct Memory Access (EDMA)  
Controller (128 Independent Channels)  
•
•
•
•
32K-Byte L1P Program RAM/Cache  
(Direct Mapped)  
80K-Byte L1D Data RAM/Cache (2-Way  
Set- Associative)  
64K-Byte L2 Unified Mapped RAM/Cache  
(4- Way Set-Associative)  
32K-Byte L2 Shared SRAM and 16K-Byte  
L2 ROM  
•
•
•
Video Hardware Accelerators  
– POWERVR SGX™ Graphics Accelerator  
(DM3730 only)  
•
Tile Based Architecture Delivering up to  
20 MPoly/sec  
– C64x+TM Instruction Set Features  
•
Universal Scalable Shader Engine:  
Multi-threaded Engine Incorporating Pixel  
and Vertex Shader Functionality  
•
•
•
•
•
•
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
Compact 16-Bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
•
•
•
Industry Standard API Support:  
OpenGLES 1.1 and 2.0, OpenVG1.0  
Fine Grained Task Switching, Load  
Balancing, and Power Management  
Programmable High Quality Image  
Anti-Aliasing  
– External Memory Interfaces:  
– Advanced Very-Long-Instruction-Word  
•
SDRAM Controller (SDRC)  
(VLIW) TMS320C64x+TM DSP Core  
–
16, 32-bit Memory Controller With  
1G-Byte Total Address Space  
•
•
Eight Highly Independent Functional  
Units  
Six ALUs (32-/40-Bit); Each Supports  
Single 32- bit, Dual 16-bit, or Quad 8-bit,  
Arithmetic per Clock Cycle  
–
–
Interfaces to Low-Power SDRAM  
SDRAM Memory Scheduler (SMS) and  
Rotation Engine  
•
General Purpose Memory Controller  
(GPMC)  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
16-bit Wide Multiplexed Address/Data  
Bus  
–
Up to 8 Chip Select Pins With  
128M-Byte Address Space per Chip  
Select Pin  
•
Load-Store Architecture With  
Non-Aligned Support  
•
•
•
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
–
Glueless Interface to NOR Flash,  
NAND Flash (With ECC Hamming  
Code Calculation), SRAM and  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
4
POWERVR SGX is a trademark of Imagination Technologies Ltd.  
OMAP is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the formative  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
Copyright © 2010, Texas Instruments Incorporated  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Pseudo-SRAM  
Configurable Priority)  
–
–
Flexible Asynchronous Protocol  
Control for Interface to Custom Logic  
(FPGA, CPLD, ASICs, etc.)  
Nonmultiplexed Address/Data Mode  
(Limited 2K-Byte Address Space)  
– Comprehensive Power, Reset, and Clock  
Management  
•
•
SmartReflexTM Technology  
Dynamic Voltage and Frequency Scaling  
(DVFS)  
– ARM CortexTM-A8 Core  
– 1.8-V I/O and 3.0-V (MMC1 only),  
0.9-V to 1.2-V Adaptive Processor Core  
Voltage  
•
ARMv7 Architecture  
–
–
–
Trust Zone  
0.9-V to 1.1-V Adaptive Core Logic Voltage  
Note: These are default Operating  
Performance Point (OPP) voltages and could  
be optimized to lower values using  
SmartReflex AVS.  
Thumb®-2  
MMU Enhancements  
•
In-Order, Dual-Issue, Superscalar  
Microprocessor Core  
•
•
•
NEON Multimedia Architecture  
Over 2x Performance of ARMv6 SIMD  
Supports Both Integer and Floating Point  
SIMD  
Jazelle® RCT Execution Environment  
Architecture  
Dynamic Branch Prediction with Branch  
Target Address Cache, Global History  
Buffer, and 8-Entry Return Stack  
Embedded Trace Macrocell (ETM)  
Support for Non-Invasive Debug  
– Commercial and Extended Temperature  
Grades  
– Serial Communication  
•
5 Multichannel Buffered Serial Ports  
(McBSPs)  
•
•
–
–
–
512 Byte Transmit/Receive Buffer  
(McBSP1/3/4/5)  
5K-Byte Transmit/Receive Buffer  
(McBSP2)  
SIDETONE Core Support (McBSP2 and  
3 Only) For Filter, Gain, and Mix  
Operations  
•
– ARM Cortex-A8 Memory Architecture:  
–
–
Direct Interface to I2S and PCM Device  
and T Buses  
128 Channel Transmit/Receive Mode  
•
•
•
32K-Byte Instruction Cache (4-Way  
Set-Associative)  
32K-Byte Data Cache (4-Way  
Set-Associative)  
•
•
•
Four Master/Slave Multichannel Serial  
Port Interface (McSPI) Ports  
256K-Byte L2 Cache  
High-Speed/Full-Speed/Low-Speed USB  
OTG Subsystem (12-/8-Pin ULPI Interface)  
High-Speed/Full-Speed/Low-Speed  
Multiport USB Host Subsystem  
– 32K-Byte ROM  
– 64K-Byte Shared SRAM  
– Endianess:  
•
•
•
ARM Instructions - Little Endian  
ARM Data – Configurable  
DSP Instructions/Data - Little Endian  
–
12-/8-Pin ULPI Interface or 6-/4-/3-Pin  
Serial Interface  
•
•
One HDQ/1-Wire Interface  
• Removable Media Interfaces:  
Four UARTs (One with Infrared Data  
Association [IrDA] and Consumer Infrared  
[CIR] Modes)  
Three Master/Slave High-Speed  
Inter-Integrated Circuit (I2C) Controllers  
– Three Multimedia Card (MMC)/ Secure Digital  
(SD) With Secure Data I/O (SDIO)  
• Test Interfaces  
•
– IEEE-1149.1 (JTAG) Boundary-Scan  
Compatible  
– Camera Image Signal Processing (ISP)  
– Embedded Trace Macro Interface (ETM)  
– Serial Data Transport Interface (SDTI)  
• 12 32-bit General Purpose Timers  
• 2 32-bit Watchdog Timers  
•
•
•
CCD and CMOS Imager Interface  
Memory Data Input  
BT.601/BT.656 Digital YCbCr 4:2:2  
(8-/10-Bit) Interface  
• 1 32-bit Secure Watchdog Timer  
• 1 32-bit 32-kHz Sync Timer  
• Up to 188 General-Purpose I/O (GPIO) Pins  
(Multiplexed With Other Device Functions)  
•
•
Glueless Interface to Common Video  
Decoders  
Resize Engine  
–
–
Resize Images From 1/4x to 4x  
Separate Horizontal/Vertical Control  
• 45-nm CMOS Technology  
• Package-On-Package (POP) Implementation for  
Memory Stacking (Not Available in CUS  
– System Direct Memory Access (SDMA)  
Controller (32 Logical Channels With  
2
DM3730, DM3725 Applications Processor  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Package)  
• Packages:  
– 515-pin s-PBGA package (CBC Suffix),  
.65mm Ball Pitch (Top), .5mm Ball Pitch  
(Bottom)  
– 423-pin s-PBGA package (CUS Suffix)  
– 515-pin s-PBGA package (CBP Suffix), .5mm  
Ball Pitch (Top), .4mm Ball Pitch (Bottom)  
Copyright © 2010, Texas Instruments Incorporated  
DM3730, DM3725 Applications Processor  
3
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
1.2 Description  
The DM37x family of high-performance, applications processors are based on the enhanced device  
architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed  
to provide best in class ARM and Graphics performance while delivering low power consumption. This  
balance of performance and power allow the device to support the following example applications:  
•
•
•
•
•
•
•
•
•
•
Portable Data Terminals  
Navigation  
Auto Infotainment  
Gaming  
Medical Imaging  
Home Automation  
Human Interface  
Industrial Control  
Test and Measurement  
Single board Computers  
The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded  
CE which are available directly from TI. Additionally, the device is fully backward compatible with previous  
CortexTM-A8 Sitara and OMAP processors.  
This DM3730/25 Applications Processor data manual presents the electrical and mechanical specifications  
for the DM3730/25 Applications Processor. The information contained in this data manual applies to both  
the commercial and extended temperature versions of the DM3730/25 Applications Processor unless  
otherwise indicated. It consists of the following sections:  
•
A description of the DM3730/25 terminals: assignment, electrical characteristics, multiplexing, and  
functional description  
•
A presentation of the electrical characteristics requirements: power domains, operating conditions,  
power consumption, and dc characteristics  
•
•
The clock specifications: input and output clocks, DPLL and DLL  
A description of thermal characteristics, device nomenclature, and mechanical data about the available  
packaging  
4
DM3730, DM3725 Applications Processor  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
1.3 Functional Block Diagram  
The functional block diagram of the DM3730/25 Applications Processor is shown below.  
Applications Processor  
CVBS  
or  
LCD Panel S-Video  
Camera  
(Parallel)  
MPU  
Subsystem  
IVA 2.2 Subsystem  
TMS320DM64x+ DSP  
Imaging Video and  
Audio Processor  
32K/32K L1$  
48K L1D RAM  
64K L2$  
32K L2 RAM  
16K L2 ROM  
Video Hardware  
Amp  
ARM Cortex-  
Parallel  
TV  
Camera  
ISP  
Image  
Capture  
Hardware  
Image  
A8TM Core  
TrustZone  
32K/32K L1$  
HS USB  
Host  
HS  
USB  
OTG  
Dual Output 3-Layer  
Display Processor  
(1xGraphics, 2xVideo)  
Temporal Dithering  
SDTV®QCIF Support  
POWERVRTM  
SGX  
Graphics  
Accelerator  
32  
Channel  
System  
DMA  
Pipeline  
L2$  
256K  
64  
Async  
64  
32  
32  
64  
64  
64  
32  
32  
32 32  
32  
64  
32  
Async  
64  
L3 Interconnect Network-Hierarchial, Performance, and Power Driven  
32 64 32 32  
SMS:  
32  
32  
L4 Interconnect  
SDRAM  
Memory  
Scheduler/  
Rotation  
GPMC:  
32KB  
On-Chip  
ROM  
64KB  
On-Chip  
RAM  
General  
Purpose  
Memory  
Controller  
NAND/  
System  
Controls  
PRCM  
Peripherals: 4xUART,  
3xHigh-Speed I2C, 5xMcBSP  
(2x with Sidetone/Audio Buffer)  
4xMcSPI, 6xGPIO  
2xSmartReflexTM  
Control  
Module  
NOR  
Flash,  
SRAM  
SDRC:  
SDRAM  
Memory  
Controller  
3xHigh-Speed MMC/SDIO  
HDQ/1 Wire, 6xMailboxes  
12xGPTimers, 2xWDT,  
32K Sync Timer  
External  
Peripherals  
Interfaces  
Emulation  
Debug: SDTI, ETM, JTAG  
External and  
Stacked Memories  
Figure 1-1. DM3730/25 Functional Block Diagram  
Copyright © 2010, Texas Instruments Incorporated  
DM3730, DM3725 Applications Processor  
5
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
2 TERMINAL DESCRIPTION  
2.1 Terminal Assignment  
Figure 2-1 through Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array  
(s-PBGA) packages. Table 2-1 through Table 2-25 indicate the signal names and ball grid numbers for  
both packages.  
Note: There are no balls present on the top of the 423-ball s-PBGA package.  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11  
13  
17  
19  
21  
23  
25  
27  
15  
2
4
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
030-001  
Figure 2-1. DM3730/25 Applications Processor CBP s-PBGA-N515 Package (Bottom View)  
6
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
 
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
L
J
M
K
H
G
E
C
A
F
D
B
23  
19  
17  
15  
13  
11  
9
7
5
3
1
21  
22  
20  
18  
16  
14  
12  
10  
8
6
4
2
030-002  
Figure 2-2. DM3730/25 Applications Processor CBP s-PBGA-N515 Package (Top View)  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
7
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
AF  
AE  
AD  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26  
6 8  
Figure 2-3. DM3730/25 Applications Processor CBC s-PBGA-515 Package (Bottom View)  
8
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
Figure 2-4. DM3730/25 Applications Processor CBC s-PBGA-515 Package (Top View)  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
9
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
AD  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
Figure 2-5. DM3730/25 Applications Processor CUS s-PBGA-N423 Package (Bottom View)  
2.2 Pin Assignments  
2.2.1 Pin Map (Top View)  
The following pin maps show the top views of the 515-pin sPBGA package [CBP], the 515-pin sPBGA  
package [CBC], and the 423-pin sPBGA package [CUS] pin assignments in four quadrants (A, B, C, and  
D).  
Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins  
must be left unconnected.  
10  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
vdds_mem  
vdds_mem  
vdds_mem  
NC  
NC  
A
vss  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
vdds_mem  
NC  
vdds_mem  
vdds_mem  
NC  
NC  
NC  
NC  
B
C
D
E
F
G
H
J
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
vss  
NC  
NC  
NC  
vss  
vss  
NC  
NC  
NC  
NC  
vss  
vss  
NC  
vdd_core  
vdd_core  
NC  
NC  
NC  
vss  
gpmc_nadv  
_ale  
gpmc_nwe  
vdds_mem vdds_mem  
gpmc_noe  
NC  
gpmc_nbe0  
_cle  
gpmc_ncs0  
gpmc_nwp  
NC  
NC  
NC  
NC  
vss  
vss  
NC  
vss  
NC  
gpmc_d8 gpmc_ncs1 vdd_core  
vdd_mpu vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
gpmc_wait3  
gpmc_wait2  
gpmc_wait1  
gpmc_wait0  
vdds_mem vdds_mem  
vss  
vdd_core  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vss  
vss  
gpmc_d0  
gpmc_d1  
gpmc_d9 gpmc_a10 gpmc_a4  
K
L
vdd_mpu vdd_mpu  
_iva _iva  
gpmc_d2  
gpmc_a9  
gpmc_a3  
vdd_mpu vdd_mpu  
_iva  
pop_k2  
_m2  
pop_y23  
_m1  
gpmc_a8  
gpmc_a7  
gpmc_a2  
gpmc_a1  
M
N
_iva  
pop_u1  
_n1  
pop_l2  
_n2  
vdd_mpu  
_iva  
gpmc_ncs7  
gpmc_ncs6  
vss  
gpmc_d10 gpmc_d3  
vss  
vss  
vss  
vss  
P
A. Top Views are provided to assist in hardware debugging efforts.  
Figure 2-6. CBP Pin Map [Quadrant A - Top View]  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
11  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
pop_a12  
_a15  
cam_vs  
NC  
NC  
vdds_mem  
vdds_mem  
cam_hs  
cam_d5  
vss  
A
pop_a22  
_a27  
NC  
NC  
NC  
pop_a23  
_a28  
cam_wen  
cam_fld  
pop_b12  
_b15  
NC  
NC  
NC  
NC  
vdds_mem  
vdds_mem  
vss  
cam_d2  
cam_d3  
cam_d10 cam_xclkb  
cam_xclka cam_d11  
vss  
NC  
vss  
vss  
NC  
NC  
NC  
NC  
NC  
vss  
pop_b23  
_b28  
B
C
D
E
F
G
H
J
NC  
vdds_mem  
cam_pclk vdds_mem  
NC  
NC  
vdd_core vdds_mem  
vdd_core vdd_core  
cam_d4 cam_strobe dss_hsync dss_vsync dss_pclk  
vdd_core dss_data6 dss_acbias dss_data20  
vdds  
vdds  
dss_data8 dss_data7  
dss_data16 dss_data9  
vss  
vdds_mem  
vdds  
uart3_tx  
_irtx  
uart3_cts  
_rctx  
uart3_rts  
_sd  
uart3_rx  
_irrx  
NC  
NC  
vss  
vss  
NC  
vss  
vss  
dss_data19 dss_data18 dss_data17  
vdd_mpu  
_iva  
pop_k1  
_j28  
vdd_core  
vdd_core  
vdd_core  
vdd_core  
vss  
i2c1_sda  
i2c1_scl  
hdq_sio dss_data21 pop_h22  
_j27  
vdda_dplls  
_dll  
vdd_core  
vss  
vdds_  
mmc1  
mcbsp1_fsx cam_d8  
cam_d6  
cam_d7  
vss  
K
L
cap_vdd  
_sram_core  
vss  
vdd_core  
vdd_core  
vss  
cam_d9  
mmc1  
_cmd  
vss  
vdd_core  
mcbsp2_dx  
pop_k22  
_m26  
M
N
mcbsp2  
_clkx  
mmc1  
_dat2  
mmc1  
_dat1  
mmc1  
_dat0  
mmc1  
_clk  
vdd_core vdd_core  
mmc1  
_dat3  
vss  
vdd_core mcbsp2_fsx  
vdds_x  
gpio_127 gpio_126  
P
Figure 2-7. CBP Pin Map [Quadrant B - Top View]  
12  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
vdd_mpu vdd_mpu  
_iva _iva  
gpmc_d11 gpmc_d12 gpmc_a6 vdds_mem  
gpmc_ncs5  
R
vdd_mpu vdd_mpu  
_iva  
gpmc_d4 gpmc_d13 gpmc_a5 gpmc_clk  
gpmc_ncs4  
gpmc_ncs3  
T
_iva  
cap_vdd  
_bb_mpu  
_iva  
vdd_mpu  
_iva  
vdds_mem  
gpmc_d5  
vss  
gpmc_nbe1  
vss  
U
cap_vdd  
_sram  
_mpu_iva  
mcspi2  
_cs1  
gpmc_d6  
gpmc_ncs2  
uart1_cts  
uart1_rx  
vss  
vss  
vss  
V
W
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
gpmc_d14 gpmc_d7  
vss  
vss  
vss  
vss  
vdds  
mcspi2  
_somi  
mcspi2  
_cs0  
vdd_mpu vdd_mpu  
_iva _iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
mcspi2_  
simo  
gpmc_d15  
vss  
Y
pop_aa1  
_aa1  
mcspi1  
_somi  
vdda_wkup  
_bg_bb  
pop_aa2 mcspi2_clk  
_aa2  
uart1_tx  
uart1_rts jtag_emu1 jtag_emu0 jtag_rtck  
jtag_tck  
AA  
AB  
AC  
AD  
AE  
AF  
mcspi1  
_cs2  
mcspi1  
mcspi1_clk  
_cs3  
mcspi1  
_simo  
mcbsp4  
_fsx  
mcspi1  
_cs0  
mcspi1_cs1 vdd_core  
mcbsp4_dr mcbsp4_dx  
vdds  
vdds  
mcbsp4  
mmc2  
_clkx  
mmc2  
_dat7  
mmc2  
_dat4  
mcbsp3_fsx mcbsp3_dr etk_d10  
vdds  
vdds  
vdd_core  
etk_d8  
etk_ctl  
etk_clk  
etk_d4  
etk_d0  
vss  
vss  
etk_d3  
etk_d6  
sys_boot2  
i2c3_scl  
_clk  
mcbsp3  
pop_ac8  
pop_u2  
_af1  
mmc2  
_dat6  
mmc2  
_dat3  
mcbsp3_dx etk_d11  
_clkx  
_af2  
mmc2  
_dat2  
mmc2  
_cmd  
pop_ab9  
_ag11  
pop_ab11  
_ag13  
vss  
vss  
vss  
etk_d12  
etk_d14  
etk_d9  
pop_ab8  
_ag10  
etk_d1  
i2c3_sda  
AG pop_ab1  
_ag1  
mmc2  
_dat5  
mmc2  
_dat1  
mmc2  
_dat0  
pop_ac13  
_ah10  
pop_ac11  
_ah13  
pop_ac9  
_ah11  
pop_ac2  
_ah2  
pop_ac1  
AH  
_ah1  
vdds_mem etk_d13  
etk_d15  
8
etk_d5  
9
etk_d2  
12  
etk_d7  
14  
1
2
3
4
5
6
7
10  
11  
13  
Figure 2-8. CBP Pin Map [Quadrant C - Top View]  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
13  
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vss  
vss  
vss  
mcbsp2_dr  
mcbsp_clks  
vss  
hsusb0_dir  
hsusb0_clk  
gpio_129  
gpio_128  
R
vdd_core  
hsusb0_stp hsusb0_nxt hsusb0  
_data0  
T
hsusb0  
_data4  
hsusb0  
_data3  
hsusb0  
_data2  
hsusb0  
_data1  
U
vdd_core vdd_core mcbsp1_dr  
vss  
vss  
vdd_core mcbsp1_dx  
vdda_dac  
vss  
hsusb0  
_data7  
hsusb0  
_data6  
hsusb0  
_data5  
V
cvideo1  
_rset  
cvideo2  
_vfb  
cvideo2  
_out  
vdd_mpu  
vdds_sram  
_iva  
mcbsp1  
vdd_core  
vss  
vdd_core  
vdd_core  
W
_clkx  
sys_  
xtalgnd  
cvideo1  
_vfb  
cvideo1  
_out  
vdd_mpu  
vdd_core  
_iva  
vss  
vssa_dac  
NC  
vdd_core vdd_core  
mcbsp1  
_clkr  
Y
cap_vddu  
_wkup  
_logic  
jtag_tms  
_tmsc  
jtag_tdo  
jtag_tdi  
dss_  
data15  
vdda_dpll  
_per  
jtag_ntrst  
mcbsp1_fsr  
uart2_tx  
uart2_rts  
dss_  
data14  
AA  
AB  
AC  
AD  
AE  
AF  
AG  
uart2_cts dss_data13 dss_data12  
dss_  
data22  
dss_  
data23  
vss  
vss  
uart2_rx  
sys_32k  
i2c4_scl dss_data11 dss_data10  
pop_aa23  
i2c4_sda  
i2c2_sda  
i2c2_scl  
vdds  
vdds  
sys_xtalin vdd_core vdd_core  
sys_xtalout sys_boot3 sys_boot4  
gpio_112  
vss  
vss  
sys_boot5 sys_clkout2  
vdds  
vdds  
vdd_core  
NC  
_ae28  
pop_h23  
_af28  
sys_boot6  
vdds  
sys_off  
_mode  
sys  
_nreswarm  
sys_clkreq sys_nirq  
pop_aa22  
_af27  
dss_data2  
pop_ab13  
_ag15  
dss_data0  
dss_data4 sys_clkout1 sys_boot1  
pop_ab23  
_ag28  
vdds  
vdds  
vss  
cam_d0  
gpio_114  
pop_l1  
_ah15  
cap_vddu  
_array  
pop_ac14  
_ah16  
sys  
_nrespwron  
pop_ac23  
_ah28  
pop_ac22  
_ah27  
dss_data3  
23  
cam_d1  
17  
gpio_113  
19  
vss  
21  
dss_data1  
22  
dss_data5  
24  
sys_boot0  
26  
gpio_115  
18  
AH  
15  
16  
20  
25  
27  
28  
Figure 2-9. CBP Pin Map [Quadrant D - Top View]  
14  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
pop_a1  
_a1  
gpmc  
_a11  
gpmc_  
ncs2  
A
NC  
vss  
NC  
vss  
NC  
NC  
NC  
NC  
vss  
NC  
gpmc_  
wait2  
gpmc_  
ncs4  
gpmc_  
ncs6  
gpmc_  
ncs3  
vss  
B
C
D
E
F
G
H
J
NC  
NC  
NC  
vss  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
vss  
vss  
NC  
NC  
sys_  
boot2  
gpmc_  
ncs5  
gpmc_  
ncs7  
gpmc_  
wait3  
I2C2_SDA i2c2_scl  
vdds  
cap_  
vdd_bb  
_mpu_iva  
gpmc  
_a9  
gpmc  
_a10  
vdd_mpu  
_iva  
sys_  
boot1  
sys_  
boot6  
NC  
vdds  
NC  
gpmc  
_a7  
gpmc  
_a8  
sys_  
boot3  
sys_  
boot4  
gpmc  
_a5  
gpmc  
_a6  
sys_  
boot0  
NC  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
gpmc  
_a4  
vdd_  
core  
sys_  
boot5  
vdds  
vss  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
vss  
NC  
vss  
NC  
NC  
NC  
NC  
NC  
gpmc  
_a2  
gpmc  
_a3  
uart1  
_rx  
vdd_mpu  
_iva  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
gpmc  
_nbe1  
gpmc  
_a1  
NC  
NC  
NC  
gpmc  
_nbe0  
_cle  
vdd_mpu  
_iva  
vdda_  
dplls_  
dll  
mmc2  
_dat7  
K
L
vss  
pop_j1  
_l1  
gpmc  
_d14  
mmc2  
_dat6  
uart1  
_tx  
vdd_mpu  
_iva  
vdds  
vdd_mpu vdd_mpu  
_iva  
gpmc  
_nwe  
gpmc  
_d15  
mmc2  
_dat5  
vdd_  
core  
vdds  
vss  
M
N
_iva  
cap_vdd  
_sram  
_mpu_iva  
vdd_mpu vdd_mpu  
_iva _iva  
gpmc  
_clk  
gpmc  
_noe  
mcbsp3  
_dr  
vss  
A. Top Views are provided to assist in hardware debugging efforts.  
Figure 2-10. CBC Pin Map [Quadrant A - Top View]  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
15  
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14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
pop_  
a20_a25  
pop_  
A
NC  
NC  
NC  
pop_b16  
_a20  
NC  
vdds  
NC  
cam_wen  
cam_d2  
NC  
NC  
a21_a26  
pop_  
b21_b26  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
vss  
cam_fld  
cam_hs  
cam_vs  
NC  
cam_d3  
cam_d5  
cam_d4  
vdds  
vss  
B
cam_  
xclka  
cam_  
C
pclk  
vdd_  
core  
cam_  
D
vss  
cam_d10  
strobe  
cam_  
xclkb  
cam_d11  
E
F
G
H
J
uart3_  
cts_  
rctx  
uart3_  
rts_sd  
dss_  
data20  
dss_  
acbias  
uart3_  
tx_  
irtx  
vdd_  
core  
dss_  
pclk  
dss_  
data6  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
vss  
NC  
NC  
NC  
vss  
vss  
NC  
uart3_  
rx_  
irrx  
vdd_  
core  
dss_  
data7  
dss_  
data8  
NC  
vdds  
vss  
NC  
dss_  
data9  
vdds  
hdq_sio  
NC  
i2c1_sda  
i2c1_scl  
vss  
NC  
cap_vddu_  
wkup_  
logic  
cap_vdd  
_sram_  
core  
pop_  
h21_k26  
mmc1_  
dat2  
dss_  
hsync  
NC  
vss  
K
L
mmc1_  
cmd  
dss_  
data16  
dss_  
data17  
vdds  
vdds  
vss  
NC  
vdd_  
core  
mmc1_  
dat1  
mmc1_  
dat0  
dss_  
data18  
dss_  
vsync  
dss_  
data19  
gpio_126  
M
N
mmc1_  
clk  
mmc1_  
dat3  
vdds_  
mmc1  
dss_  
data21  
cam_d8  
cam_d9  
vss  
NC  
Figure 2-11. CBC Pin Map [Quadrant B - Top View]  
16  
TERMINAL DESCRIPTION  
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gpmc  
_d13  
mcbsp3  
_dx  
mcspi1  
_somi  
mcspi1  
_simo  
mcspi1  
_clk  
vdd_mpu  
_iva  
P
R
NC  
NC  
vss  
uart1  
_rts  
mcbsp4  
_dx  
mcspi1  
_cs0  
mcspi1  
_cs1  
mcspi1  
_cs2  
mmc2  
_cmd  
vss  
gpmc  
_d10  
pop_n2  
_t2  
mcbsp4  
_fsx  
mcspi1  
_cs3  
mmc2  
_dat1  
mmc2  
_dat0  
vdd_  
core  
vdds  
T
U
gpmc  
_d12  
gpmc  
_d11  
mcbsp3  
_clkx  
mcbsp4  
_dr  
vdd_mpu  
_iva  
mcspi2  
_somi  
mmc2  
_dat3  
mmc2  
_dat2  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdds_  
sram  
sys_  
nresp  
wron  
gpmc  
_d8  
mcbsp4  
_clkx  
vdd_mpu  
_iva  
mcspi2  
_cs0  
mcspi2  
_cs1  
mmc2  
_dat4  
vdd_mpu  
_iva  
sys_off  
_mode  
etk_d9  
V
NC  
vss  
uart1  
_cts  
mcbsp3  
_fsx  
mcspi2  
_clk  
mcspi2  
_simo  
vdd_mpu  
_iva  
mmc2  
_clk  
sys_  
clkout2  
jtag_  
rtck  
vss  
NC  
W
gpmc  
_d9  
pop_t2  
_y2  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_  
core  
vdd_  
core  
jtag_  
tdo  
etk_d4  
etk_d3  
etk_ctl  
etk_d0  
etk_d2  
etk_d6  
vdds  
vss  
Y
vss  
gpmc  
_d1  
gpmc  
_d0  
etk_d8  
i2c3_scl  
i2c3_sda  
etk_d1  
etk_d10  
AA  
AB  
AC  
AD  
AE  
etk_d5  
etk_clk  
vss  
gpmc  
_d3  
gpmc  
_d2  
gpmc  
_d7  
gpmc  
_nwp  
gpmc  
_wait1  
gpmc  
_wait0  
vdds  
NC  
NC  
vss  
NC  
NC  
NC  
NC  
NC  
NC  
sys_  
nres  
warm  
gpmc  
_ncs1  
gpmc  
_d6  
gpmc  
_d5  
gpmc  
_ncs0  
gpmc_  
nadv_ale  
etk_d7  
NC  
NC  
pop_w2  
_ae2  
gpmc  
_d4  
etk_d12  
etk_d15  
vdds  
NC  
vss  
NC  
pop_y2  
_af4  
pop_aa6  
_af5  
pop_y7_  
_af8  
pop_y9_  
_af10  
pop_aa10 pop_aa11  
_af13  
etk_d11  
6
NC  
1
NC  
2
NC  
3
etk_d13  
7
etk_d14  
9
NC  
11  
AF  
_af12  
4
5
8
10  
12  
13  
Figure 2-12. CBC Pin Map [Quadrant C - Top View]  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
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mcbsp1  
_fsx  
vdds_x  
cam_d6  
NC  
cam_d7  
gpio_127 gpio_128  
mcbsp2  
gpio_129  
NC  
NC  
P
R
mcbsp2  
_dx  
vdd_  
core  
NC  
vss  
NC  
NC  
NC  
vss  
_clkx  
mcbsp1  
_clkx  
mcbsp2  
_dr  
mcbsp  
_clks  
mcbsp1  
_dr  
vdds  
NC  
T
cvideo2  
_vfb  
pop_  
p21_u26  
mcbsp1  
_dx  
mcbsp2  
_fsx  
mcbsp1  
_clkr  
hsusb0  
_stp  
vdda_  
dpll_per  
jtag_  
ntrst  
jtag_tdi  
sys_nirq  
i2c4_sda  
vss  
vss  
U
jtag_tms  
_tmsc  
cvideo1  
_rset  
cvideo2  
_out  
mcbsp1  
_fsr  
hsusb0  
_data2  
hsusb0  
_dir  
hsusb0  
_data0  
vssa_  
dac  
vdda_  
dac  
V
jtag_tck  
vdda_  
wkup_  
bg_bb  
cvideo1  
_vfb  
cvideo1  
_out  
hsusb0  
_data4  
hsusb0  
_nxt  
hsusb0  
_clk  
hsusb0  
_data3  
sys_  
clkreq  
vdds  
vss  
NC  
NC  
NC  
NC  
W
uart2  
_cts  
hsusb0  
_data7  
hsusb0  
_data5  
hsusb0  
_data6  
hsusb0  
_data1  
jtag_  
emu1  
jtag_  
emu0  
dss_  
data13  
vss  
Y
AA  
AB  
AC  
AD  
AE  
AF  
uart2  
_rts  
dss_  
data12  
dss_  
data14  
dss_  
data23  
dss_  
data15  
vss  
NC  
vdds  
vdds  
vdd_  
core  
dss_  
data22  
dss_  
data10  
vdds  
vss  
vdds  
vdds  
vss  
NC  
vss  
NC  
NC  
vdds  
uart2  
_rx  
uart2  
_tx  
dss_  
data4  
dss_  
data5  
dss_  
data11  
i2c4_scl  
cam_d1  
gpio_113  
cam_d0  
gpio_112  
gpio_115  
vdds  
vss  
cap  
_vddu  
_array  
sys_  
clkout1  
pop_y20  
_ae25  
pop_y21  
_ae26  
dss_  
data0  
dss_  
data1  
dss_  
data2  
dss_  
data3  
gpio_114  
sys_32k  
pop_aa21  
_af26  
pop_aa12 pop_aa13 pop_aa14  
_af14  
pop_y14 pop_aa17  
_af17  
pop_y17  
_af21  
pop_  
sys  
aa19_af22 _xtalgnd  
pop_y19  
_af24  
pop_aa20  
_af25  
sys_  
xtalin  
sys_  
xtalout  
_af15  
_af16  
_af18  
19  
14  
15  
16  
17  
18  
20  
21  
22 23  
24  
25  
26  
Figure 2-13. CBC Pin Map [Quadrant D - Top View]  
18  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
1
2
3
4
5
6
7
8
9
10  
11  
12  
sdrc  
_dqs0  
sdrc  
_dm2  
sdrc  
_dqs2  
sdrc  
_clk  
sdrc  
_nclk  
A
sdrc_a0  
NC  
NC  
sdrc  
_dm0  
sdrc_a4  
sdrc_a3  
sdrc_a5  
sdrc_a1  
sdrc_d3  
sdrc_d1  
sdrc_d7  
sdrc_d6  
sdrc_d0  
sdrc_a10  
sdrc_a13  
sdrc_a12  
sdrc_d18  
sdrc_d19  
sdrc_d16  
sdrc_d4  
sdrc_a9  
sdrc_a14  
sdrc_d21  
sdrc_d20  
sdrc_d5  
sdrc_a8  
sdrc_d8  
sdrc_d10  
sdrc_d9  
B
C
D
E
F
G
H
J
NC  
gpmc  
_wait0  
gpmc  
_wait3  
sdrc_d2  
sdrc_a2  
gpmc  
_ncs3  
sdrc_d22  
sdrc_d17  
gpmc  
_nwp  
gpmc  
_ncs0  
sdrc_a6  
gpmc  
_nadv  
_ale  
gpmc  
_noe  
gpmc  
_ncs6  
gpmc  
_ncs4  
vdd_  
core  
sdrc_a7  
vdd_mpu  
_iva  
vdd_mpu vdd_mpu  
_iva _iva  
gpmc  
_a10  
gpmc  
_nwe  
gpmc  
_ncs7  
gpmc  
_ncs5  
vdd_  
core  
sdrc_a11  
vdd_mpu vdd_mpu  
_iva _iva  
gpmc  
_a8  
gpmc  
_a9  
vdd_  
core  
vss  
vss  
vss  
vdds_x  
vdds  
_mem  
vdds  
_mem  
vdds  
_mem  
vdd_mpu vdd_mpu  
_iva  
gpmc  
_a7  
gpmc  
_a6  
gpmc  
_a5  
gpmc  
_a4  
vss  
_iva  
gpmc_  
nbe0_cle  
vdds  
_mem  
vdds  
_mem  
vdds  
_mem  
gpmc  
_a3  
gpmc  
_a2  
gpmc  
_a1  
vss  
K
L
gpmc_  
nbe1  
gpmc  
_d0  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vss  
vss  
vss  
mcspi2  
_cs0  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
gpmc  
_d1  
gpmc  
_d2  
gpmc  
_d4  
mcspi2  
_cs1  
vss  
vss  
M
A. Top Views are provided to assist in hardware debugging efforts.  
Figure 2-14. CUS Pin Map [Quadrant A - Top View]  
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TERMINAL DESCRIPTION  
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13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
uart3_  
_cts_  
rctx  
sdrc_  
dqs1  
sdrc_  
d14  
sdrc_  
dqs3  
sdrc_  
ncs0  
sdrc_  
nwe  
sdrc_  
dm3  
cam_hs  
hdq_si0  
A
uart3_  
_rts_  
sd  
uart3_  
_rx_  
irrx  
sdrc_  
dm1  
sdrc_  
d13  
sdrc_  
d15  
sdrc_  
d27  
sdrc_  
d30  
sdrc_  
d31  
sdrc_  
ncs1  
sdrc_  
cke0  
cam_  
xclka  
cam_d5  
B
C
D
E
F
G
H
J
uart3_  
_tx_  
irtx  
sdrc_  
d12  
sdrc_  
d26  
sdrc_  
d28  
sdrc_  
ba0  
sdrc_  
ncas  
sdrc_  
cke1  
cam_  
xclkb  
sdrc_  
d11  
sdrc_  
d25  
sdrc_  
d29  
sdrc_  
ba1  
sdrc_  
nras  
dss_  
data20  
dss_  
data6  
sdrc_  
d23  
sdrc_  
d24  
vdds_  
mem  
dss_  
hsync  
dss_  
data7  
dss_  
data8  
cam_vs  
vdd_  
core  
vdds_  
mem  
vdds_  
mem  
dss_  
vsync  
dss_  
data9  
cam_wen  
cam_d3  
cam_d2  
cam_d10  
cam_d11  
vdda  
_dplls  
_dll  
vdd_  
core  
vdds_  
mem  
vdds_  
mem  
dss_  
pclk  
dss_  
data17  
dss_  
data18  
cam_d4  
cap_vdd  
_sram  
_core  
vdd_  
core  
vdds_  
mem  
dss_  
data19  
cam_fld  
vss  
vss  
vss  
vss  
vss  
vdd_  
core  
vdd_  
core  
cam_  
pclk  
cam_  
strobe  
dss_  
acbias  
dss_  
data16  
cam_d8  
cam_d9  
vss  
vss  
vss  
vdd_  
core  
vdd_  
core  
vdd_  
core  
dss_  
data21  
i2c1_scl  
i2c1_sda  
cam_d7  
cam_d6  
K
L
vdd_  
core  
vdd_  
core  
mmc1_  
cmd  
vss  
vss  
vss  
vdd_  
core  
vdd_  
core  
mmc1_  
dat2  
mmc1_  
dat1  
mmc1_  
dat0  
mmc1_  
clk  
vdds  
vdds  
vdds  
vss  
M
Figure 2-15. CUS Pin Map [Quadrant B - Top View]  
20  
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SPRS685–AUGUST 2010  
gpmc  
_d3  
mcspi2  
_somi  
mcspi2  
_simo  
mcspi2  
_clk  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
N
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
gpmc  
_d5  
gpmc  
_d6  
P
R
vss  
gpmc  
_d7  
gpmc  
_d8  
gpmc  
_d11  
mcspi1  
_simo  
mcbsp1  
_cs3  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
vss  
gpmc  
_d9  
gpmc  
_d12  
mcspi1  
_somi  
mcspi1  
_clk  
mcspi1  
_cs0  
vdd_mpu  
_iva  
vdd_mpu  
_iva  
T
vss  
vss  
vss  
vss  
cap_vdd  
_sram_  
mpu_iva  
gpmc  
_d10  
gpmc  
_d13  
vdd_mpu  
_iva  
vdds  
vdds  
vdds  
U
gpmc  
_d14  
gpmc  
_d15  
mmc2  
_dat3  
mcbsp3  
_fsx  
mcbsp3  
_dr  
mcbsp3  
_dx  
uart1  
_rx  
vdd_mpu  
_iva  
vdds  
vdds  
vdds  
V
uart1  
_tx  
vdd_mpu  
_iva  
gpmc  
_clk  
mmc2  
_dat2  
mcbsp3  
_clkx  
uart1  
_rts  
W
Y
sys_  
nres  
warm  
cap_vddu_  
wkup_logic  
mmc2  
_clk  
mmc2  
_dat6  
mmc2  
_dat1  
sys_  
clkout1  
sys_  
nres  
pwron  
mmc2  
_dat7  
mmc2  
_dat5  
sys_  
clkout2  
jtag_tms  
_tmsc  
jtag_  
rtck  
vdds_  
sram  
AA  
AB  
AC  
mmc2  
_dat4  
mmc2  
_dat0  
mmc2  
_cmd  
jtag_  
tck  
jtag_  
ntrst  
jtag_  
tdo  
jtag_  
tdi  
sys_  
boot0  
uart1_  
cts  
etk_clk  
etk_d10  
etk_d8  
etk_d4  
etk_d1  
etk_d2  
etk_d6  
etk_d11  
etk_d12  
etk_d14  
i2c3_sda  
etk_d5  
2
etk_ctl  
3
etk_d9  
5
etk_d0  
6
etk_d3  
8
etk_d7  
9
etk_d13  
11  
etk_d15  
12  
NC  
1
AD  
4
7
10  
Figure 2-16. CUS Pin Map [Quadrant C - Top View]  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
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cap_vdd  
_bb_mpu  
_iva  
cap_vddu  
_array  
mmc1_  
dat3  
vdds_  
mmc1  
N
vdds  
gpio_126  
vdds  
vss  
vdds  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
vss  
hsusb0  
_dir  
gpio_129  
P
R
mcbsp2  
_dx  
hsusb0  
_clk  
hsusb0  
_nxt  
hsusb0  
_stp  
vdd_  
core  
vdd_  
core  
vdd_  
core  
mcbsp2  
_clkx  
hsusb0  
_data7  
hsusb0  
_data1  
hsusb0  
_data0  
vdd_  
core  
vdd_  
core  
vdd_  
core  
vdd_  
core  
T
vss  
vss  
vss  
vss  
vdda_  
dpll  
_per  
hsusb0  
_data3  
hsusb0  
_data2  
U
vdd_mpu  
_iva  
vdd_mpu  
_iva  
mcbsp1  
_clkx  
mcbsp2  
_dr  
mcbsp2  
_fsx  
hsusb0  
_data5  
dss_  
data22  
dss_  
data15  
V
mcbsp1  
_clkr  
hsusb0  
_data6  
hsusb0  
_data4  
vdd_mpu  
_iva  
mcbsp1  
_dx  
sys_  
nirq  
dss_  
data23  
dss_  
data14  
sys_  
xtalgnd  
W
Y
mcbsp1  
_dr  
cvideo2  
_vfb  
cvideo1  
_rset  
sys_  
clkreq  
dss_  
data13  
i2c4_sda  
i2c4_scl  
sys_32k  
vdda_  
wkup  
_bg_bb  
mcbsp  
_clks  
mcbsp1  
_fsx  
cvideo2  
_out  
sys_  
boot6  
AA  
AB  
AC  
mcbsp1  
_fsr  
cvideo1  
_vfb  
cvideo1  
_out  
vdda_  
dac  
sys_  
boot5  
dss_  
data1  
dss_  
data12  
vssa_dac  
i2c2_scl  
cam_d0  
cam_d1  
sys_  
boot1  
sys_  
boot4  
dss_  
data0  
dss_  
data3  
dss_  
data5  
dss_  
data10  
dss_  
data11  
jtag_  
emu0  
i2c3_scl  
i2c2_sda  
sys_off  
_mode  
sys_  
xtaout  
sys_  
xtalin  
sys_  
boot2  
sys_  
boot3  
dss_  
data2  
dss_  
data4  
jtag_  
emu1  
AD  
17  
13  
14  
15  
16  
18  
19  
20  
21  
22  
23  
24  
Figure 2-17. CUS Pin Map [Quadrant D - Top View]  
22  
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SPRS685–AUGUST 2010  
2.3 Ball Characteristics  
Table 2-1 through Table 2-3 describe the terminal characteristics and the signals multiplexed on each pin  
for the CBP, CBC, and CUS packages, respectively. The following list describes the table column  
headers.  
1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.  
2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top.  
3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the  
signal name in mode 0).  
Note: Table 2-1 through Table 2-3 do not take into account subsystem pin multiplexing options.  
Subsystem pin multiplexing options are described in Section 2.5, Signal Descriptions.  
4. MODE: Multiplexing mode number.  
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin  
corresponds to the name of the pin. There is always a function mapped on the primary mode.  
Notice that primary mode is not necessarily the default mode.  
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE  
column.  
(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively  
used for alternate functions, while some modes are not used and do not correspond to a functional  
configuration.  
5. TYPE: Signal direction  
–
–
–
–
–
–
–
–
I = Input  
O = Output  
I/O = Input/Output  
D = Open drain  
DS = Differential  
A = Analog  
PWR = Power  
GND = Ground  
Note: In the safe_mode, the buffer is configured in high-impedance.  
6. BALL RESET STATE: The state of the terminal at the power-on reset.  
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)  
0(PD): The buffer drives VOL with an active pulldown resistor.  
1: The buffer drives VOH (pulldown/pullup resistor not activated)  
1(PU): The buffer drives VOH with an active pullup resistor.  
Z: High-impedance  
–
–
–
–
L: High-impedance with an active pulldown resistor  
H : High-impedance with an active pullup resistor  
7. BALL RESET REL. STATE: The state of the terminal at the release of the System Control Module  
reset (PRCM CORE_RSTPWRON_RET reset signal).  
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)  
0(PD): The buffer drives VOL with an active pulldown resistor.  
1: The buffer drives VOH (pulldown/pullup resistor not activated)  
1(PU): The buffer drives VOH with an active pullup resistor.  
Z: High-impedance  
–
–
–
–
L: High-impedance with an active pulldown resistor  
H : High-impedance with an active pullup resistor  
8. RESET REL. MODE: The mode is automatically configured at the release of the System Control  
Module reset (PRCM CORE_RSTPWRON_RET reset signal).  
9. POWER: The voltage supply that powers the terminal’s I/O buffers.  
10. HYS: Indicates if the input buffer is with hysteresis.  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
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11. BUFFER STRENGTH: Drive strength of the associated output buffer.  
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and  
pulldown resistors can be enabled or disabled via software.  
Note: The pullup/pulldown drive strength is equal to minimum = 50mA, typical = 100 mA, maximum =  
250 mA (unless otherwise specified), except for CBP balls P27, P26, R27, and R25, and CUS balls  
N22 and P24, which the pulldown drive strength is equal to 1.8 kΩ.  
13. IO CELL: IO cell information.  
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.  
This can be easily prevented with the proper software configuration.  
NOTE  
In the DM3730/25 device, new Far End load Settings registers are added for some IOs. This  
new feature configures the IO according to the transmission line and the  
application/peripheral load. For a full description on these registers, see the System Control  
Module / SCM Functional Description / Functional Register Description / Signal Integrity  
Parameter Control Registers with Pad Group Assignment section of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-1. Ball Characteristics (CBP Pkg.)(3)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
(10)  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
J2  
sdrc_d0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(10)  
J1  
sdrc_d1  
4
(10)  
G2  
sdrc_d2  
4
(10)  
G1  
sdrc_d3  
4
(10)  
F2  
sdrc_d4  
4
(10)  
F1  
sdrc_d5  
4
(10)  
D2  
sdrc_d6  
4
(10)  
D1  
sdrc_d7  
4
(10)  
B13  
A13  
B14  
A14  
B16  
A16  
B19  
A19  
B3  
sdrc_d8  
4
(10)  
sdrc_d9  
4
(10)  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
A3  
4
(10)  
B5  
4
(10)  
A5  
4
(10)  
B8  
4
(10)  
A8  
4
(10)  
B9  
4
(10)  
A9  
4
(10)  
B21  
A21  
D22  
D23  
E22  
E23  
G22  
G23  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
(10)  
4
24  
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BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
(12)  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AB21  
AC21  
N22  
N23  
P22  
P23  
R22  
R23  
T22  
T23  
U22  
U23  
V22  
V23  
W22  
W23  
Y22  
M22  
M23  
A11  
B11  
J22  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
7
0
0
0
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO  
O
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
L
1
H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem Yes  
vdds_mem No  
vdds_mem Yes  
4
NA  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(12)  
4
NA  
(12)  
4
NA  
(12)  
sdrc_a1  
4
NA  
(12)  
sdrc_a2  
4
NA  
(12)  
sdrc_a3  
4
NA  
(12)  
sdrc_a4  
4
NA  
(12)  
sdrc_a5  
4
NA  
(12)  
sdrc_a6  
4
NA  
(12)  
sdrc_a7  
4
NA  
(12)  
sdrc_a8  
4
NA  
(12)  
sdrc_a9  
4
NA  
(12)  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
4
NA  
(12)  
4
NA  
(12)  
4
NA  
(12)  
4
NA  
(12)  
4
NA  
(12)  
4
NA  
(12)  
4
NA  
(12)  
4
PU/ PD  
NA  
(12)  
sdrc_nclk  
sdrc_cke0  
safe_mode_out1(13)  
sdrc_cke1  
safe_mode_out1(13)  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
gpmc_a1  
gpio_34  
4
(12)  
4
PU/ PD  
(12)  
NA  
J23  
O
H
1
7
vdds_mem NA  
4
PU/ PD  
LVCMOS  
(12)  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
N4  
L23  
L22  
K23  
C1  
O
1
1
1
0
0
0
0
L
L
L
L
L
1
1
1
0
0
0
0
Z
Z
Z
Z
L
0
0
0
0
0
0
0
0
0
0
0
7
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem No  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
4
NA  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(12)  
O
4
NA  
(12)  
O
4
NA  
(12)  
O
4
NA  
(12)  
A17  
A6  
O
4
NA  
(12)  
O
4
NA  
(12)  
A20  
C2  
O
4
NA  
(12)  
IO  
IO  
IO  
IO  
O
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
(12)  
B17  
B6  
4
(12)  
4
(12)  
B20  
AC15  
4
8
8
8
8
8
8
IO  
safe_mode  
gpmc_a2  
gpio_35  
M4  
L4  
AB15  
AC16  
AB16  
AC17  
AB17  
O
L
L
L
L
H
L
L
L
L
H
7
7
7
7
7
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_a3  
gpio_36  
O
IO  
safe_mode  
gpmc_a4  
gpio_37  
K4  
T3  
R3  
O
IO  
safe_mode  
gpmc_a5  
gpio_38  
O
IO  
safe_mode  
gpmc_a6  
gpio_39  
O
IO  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
25  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
N3  
M3  
L3  
AC18  
gpmc_a7  
gpio_40  
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
7
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
4
7
O
H
H
H
H
H
H
7
7
7
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_a8  
gpio_41  
AB18  
AC19  
O
IO  
safe_mode  
gpmc_a9  
sys_ndmareq2  
gpio_42  
O
I
IO  
safe_mode  
gpmc_a10  
sys_ndmareq3  
gpio_43  
K3  
AB19  
O
I
H
H
7
vdds_mem Yes  
8
PU/ PD  
LVCMOS  
IO  
safe_mode  
gpmc_a11  
safe_mode  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpio_44  
NA  
AC20  
O
L
L
7
vdds_mem Yes  
8
PU/ PD  
LVCMOS  
K1  
L1  
M2  
M1  
N2  
N1  
R2  
R1  
T2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
L2  
P2  
T1  
V1  
V2  
W2  
H2  
T1  
AB3  
safe_mode  
gpmc_d9  
gpio_45  
K2  
P1  
R1  
R2  
T2  
W1  
Y1  
AC3  
AB4  
AC4  
AB6  
AC6  
AB7  
AC7  
IO  
IO  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_d10  
gpio_46  
IO  
IO  
safe_mode  
gpmc_d11  
gpio_47  
IO  
IO  
safe_mode  
gpmc_d12  
gpio_48  
IO  
IO  
safe_mode  
gpmc_d13  
gpio_49  
IO  
IO  
safe_mode  
gpmc_d14  
gpio_50  
IO  
IO  
safe_mode  
gpmc_d15  
gpio_51  
IO  
IO  
safe_mode  
gpmc_ncs0  
gpmc_ncs1  
gpio_52  
G4  
H3  
Y2  
Y1  
O
1
1
1
0
0
vdds_mem NA  
vdds_mem Yes  
8
8
NA  
LVCMOS  
LVCMOS  
O
H
PU/ PD  
IO  
safe_mode  
26  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
V8  
U8  
NA  
gpmc_ncs2  
gpio_53  
0
4
7
0
1
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
4
7
0
0
0
0
4
7
0
4
7
0
4
7
0
0
4
7
0
2
4
7
O
H
H
H
H
7
7
vdds_mem Yes  
vdds_mem Yes  
8
PU/ PD  
LVCMOS  
IO  
safe_mode  
gpmc_ncs3  
sys_ndmareq0  
gpio_54  
NA  
NA  
O
I
8
PU/ PD  
LVCMOS  
IO  
safe_mode  
gpmc_ncs4  
sys_ndmareq1  
mcbsp4_clkx  
gpt_9_pwm_evt  
gpio_55  
T8  
R8  
P8  
N8  
T4  
O
I
H
H
H
H
L
H
H
H
H
0
7
7
7
7
0
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
vdds_mem Yes  
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
IO  
safe_mode  
gpmc_ncs5  
sys_ndmareq2  
mcbsp4_dr  
gpt_10_pwm_evt  
gpio_56  
NA  
NA  
NA  
W2  
O
I
I
IO  
IO  
safe_mode  
gpmc_ncs6  
sys_ndmareq3  
mcbsp4_dx  
gpt_11_pwm_evt  
gpio_57  
O
I
IO  
IO  
IO  
safe_mode  
gpmc_ncs7  
gpmc_io_dir  
mcbsp4_fsx  
gpt_8_pwm_evt  
gpio_58  
O
O
IO  
IO  
IO  
safe_mode  
gpmc_clk  
O
gpio_59  
IO  
safe_mode  
gpmc_nadv_ale  
gpmc_noe  
gpmc_nwe  
gpmc_nbe0_cle  
gpio_60  
F3  
G2  
F4  
G3  
W1  
V2  
O
O
O
O
IO  
0
1
1
L
0
1
1
0
0
0
0
0
vdds_mem NA  
vdds_mem NA  
vdds_mem NA  
vdds_mem Yes  
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
V1  
AC12  
safe_mode  
gpmc_nbe1  
gpio_61  
U3  
H1  
NA  
O
L
L
L
0
7
0
vdds_mem Yes  
vdds_mem Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_nwp  
gpio_62  
AB10  
O
IO  
safe_mode  
gpmc_wait0  
gpmc_wait1  
gpio_63  
M8  
L8  
AB12  
AC10  
I
H
H
H
H
0
7
vdds_mem Yes  
vdds_mem Yes  
NA  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
safe_mode  
gpmc_wait2  
uart4_tx  
K8  
NA  
I
H
H
7
vdds_mem Yes  
8
PU/ PD  
LVCMOS  
O
IO  
gpio_64  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
27  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
J8  
NA  
gpmc_wait3  
sys_ndmareq1  
uart4_rx  
0
1
2
4
7
0
4
5
7
0
4
5
7
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
2
4
5
7
0
2
4
5
7
I
H
H
7
vdds_mem Yes  
8
PU/ PD  
LVCMOS  
I
I
gpio_65  
IO  
safe_mode  
dss_pclk  
D28  
D26  
NA  
NA  
O
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_66  
IO  
O
hw_dbg12  
safe_mode  
dss_hsync  
gpio_67  
O
IO  
O
hw_dbg13  
safe_mode  
dss_vsync  
gpio_68  
D27  
NA  
NA  
NA  
O
H
L
L
H
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_acbias  
gpio_69  
E27  
O
IO  
safe_mode  
dss_data0  
uart1_cts  
gpio_70  
AG22  
IO  
I
8
NA  
8
IO  
safe_mode  
dss_data1  
uart1_rts  
8
AH22  
NA  
IO  
O
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
8
gpio_71  
IO  
8
safe_mode  
dss_data2  
gpio_72  
8
AG23  
AH23  
AG24  
NA  
NA  
NA  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
8
safe_mode  
dss_data3  
gpio_73  
8
IO  
IO  
8
8
safe_mode  
dss_data4  
uart3_rx_irrx  
gpio_74  
8
IO  
I
8
NA  
8
IO  
safe_mode  
dss_data5  
uart3_tx_irtx  
gpio_75  
8
AH24  
E26  
NA  
NA  
IO  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
8
IO  
8
safe_mode  
dss_data6  
uart1_tx  
8
IO  
O
8
gpio_76  
IO  
O
hw_dbg14  
safe_mode  
dss_data7  
uart1_rx  
F28  
NA  
IO  
I
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
gpio_77  
IO  
O
hw_dbg15  
safe_mode  
28  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
F27  
NA  
dss_data8  
uart3_rx_irrx  
gpio_78  
0
2
4
5
7
0
2
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
IO  
I
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
LVCMOS  
IO  
O
hw_dbg16  
safe_mode  
dss_data9  
uart3_tx_irtx  
gpio_79  
G26  
NA  
IO  
O
L
L
7
vdds  
Yes  
8
PU/ PD  
IO  
O
hw_dbg17  
safe_mode  
dss_data10  
gpio_80  
AD28  
AD27  
AB28  
AB27  
AA28  
AA27  
G25  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data11  
gpio_81  
IO  
IO  
safe_mode  
dss_data12  
gpio_82  
IO  
IO  
safe_mode  
dss_data13  
gpio_83  
IO  
IO  
safe_mode  
dss_data14  
gpio_84  
IO  
IO  
safe_mode  
dss_data15  
gpio_85  
IO  
IO  
safe_mode  
dss_data16  
gpio_86  
IO  
IO  
safe_mode  
dss_data17  
gpio_87  
H27  
IO  
IO  
safe_mode  
dss_data18  
mcspi3_clk  
dss_data0  
gpio_88  
H26  
IO  
IO  
IO  
IO  
safe_mode  
dss_data19  
mcspi3_simo  
dss_data1  
gpio_89  
H25  
E28  
J26  
NA  
NA  
NA  
IO  
IO  
IO  
IO  
L
H
L
L
H
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data20  
mcspi3_somi  
dss_data2  
gpio_90  
O
IO  
IO  
IO  
safe_mode  
dss_data21  
mcspi3_cs0  
dss_data3  
gpio_91  
O
IO  
IO  
IO  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
29  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
AC27  
AC28  
NA  
dss_data22  
mcspi3_cs1  
dss_data4  
gpio_92  
0
2
3
4
7
0
3
4
7
0
0
0
0
0
0
4
5
7
0
4
5
7
0
4
7
0
4
5
7
0
2
4
5
7
0
4
7
0
4
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
O
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
O
IO  
IO  
safe_mode  
dss_data23  
dss_data5  
gpio_93  
NA  
O
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
IO  
IO  
safe_mode  
cvideo2_out  
cvideo1_out  
cvideo1_vfb  
cvideo2_vfb  
cvideo1_rset  
cam_hs  
W28  
Y28  
Y27  
W27  
W26  
A24  
NA  
NA  
NA  
NA  
NA  
NA  
AO  
AO  
AO  
AO  
AIO  
IO  
0
0
0
0
0
L
0
0
0
0
0
0
7
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdds  
NA  
NA  
NA  
NA  
No  
NA(4)  
NA(4)  
NA(10)  
NA(10)  
NA  
NA  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
LVCMOS  
0
NA  
NA  
NA  
NA  
L
NA  
NA  
NA  
Yes  
4
PU/ PD  
gpio_94  
IO  
hw_dbg0  
safe_mode  
cam_vs  
O
A23  
NA  
IO  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
gpio_95  
hw_dbg1  
safe_mode  
cam_xclka  
gpio_96  
C25  
C27  
NA  
NA  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
cam_pclk  
gpio_97  
I
IO  
O
hw_dbg2  
safe_mode  
cam_fld  
C23  
NA  
IO  
IO  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
cam_global_reset  
gpio_98  
hw_dbg3  
safe_mode  
cam_d0  
AG17  
AH17  
B24  
NA  
NA  
NA  
I
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
NA  
NA  
8
PU/PD  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_99  
safe_mode  
cam_d1  
I
I
gpio_100  
safe_mode  
cam_d2  
I
gpio_101  
hw_dbg4  
safe_mode  
cam_d3  
IO  
O
C24  
D24  
NA  
NA  
NA  
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_102  
hw_dbg5  
safe_mode  
cam_d4  
IO  
O
I
gpio_103  
hw_dbg6  
safe_mode  
cam_d5  
IO  
O
A25  
I
gpio_104  
IO  
30  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
hw_dbg7  
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
5
7
0
4
5
7
0
4
7
0
2
4
5
7
0
4
5
7
4
7
4
7
4
7
4
7
0
4
7
0
4
7
0
4
7
0
4
7
O
safe_mode  
cam_d6  
K28  
L28  
K27  
L27  
B25  
NA  
NA  
NA  
NA  
NA  
I
I
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
NA  
NA  
NA  
NA  
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_105  
safe_mode  
cam_d7  
I
I
gpio_106  
safe_mode  
cam_d8  
I
I
gpio_107  
safe_mode  
cam_d9  
I
I
gpio_108  
safe_mode  
cam_d10  
gpio_109  
hw_dbg8  
I
IO  
O
safe_mode  
cam_d11  
gpio_110  
hw_dbg9  
C26  
NA  
I
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
IO  
O
safe_mode  
cam_xclkb  
gpio_111  
safe_mode  
cam_wen  
cam_shutter  
gpio_167  
hw_dbg10  
safe_mode  
cam_strobe  
gpio_126  
hw_dbg11  
safe_mode  
gpio_112  
safe_mode  
gpio_113  
safe_mode  
gpio_114  
safe_mode  
gpio_115  
safe_mode  
mcbsp2_fsx  
gpio_116  
safe_mode  
mcbsp2_clkx  
gpio_117  
safe_mode  
mcbsp2_dr  
gpio_118  
safe_mode  
mcbsp2_dx  
gpio_119  
safe_mode  
B26  
B23  
NA  
NA  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
I
O
IO  
O
D25  
NA  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
O
AG19  
AH19  
AG18  
AH18  
P21  
NA  
NA  
NA  
NA  
NA  
I
I
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
NA  
NA  
NA  
NA  
4
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
I
-
I
-
IO  
IO  
N21  
R21  
M21  
NA  
NA  
NA  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
I
IO  
IO  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
31  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
N28  
M27  
N27  
N26  
N25  
P28  
NA  
mmc1_clk  
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
4
7
4
7
4
7
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
7
0
1
4
7
0
1
4
7
0
1
3
4
7
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
1
1
1
1
1
1
PU/ PD(5)  
PU/ PD(5)  
PU/ PD (5)  
PU/ PD(5)  
PU/ PD (5)  
PU/ PD (5)  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_120 (1)  
safe_mode  
mmc1_cmd  
gpio_121 (1)  
safe_mode  
mmc1_dat0  
gpio_122 (1)  
safe_mode  
mmc1_dat1  
gpio_123(1)  
safe_mode  
mmc1_dat2  
gpio_124(1)  
safe_mode  
mmc1_dat3  
gpio_125(1)  
safe_mode  
gpio_126(1)  
safe_mode  
gpio_127(1)  
safe_mode  
gpio_128(1)  
safe_mode  
gpio_129(1)  
safe_mode  
mmc2_clk  
NA  
NA  
NA  
NA  
NA  
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
P27  
P26  
R27  
R25  
AE2  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
vdds_x  
vdds_x  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
1
1
4
1
4
PU/ PD (5)  
PU/ PD(5)  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
vdds_x  
vdds  
PU/ PD(5)  
PU/ PD  
IO  
IO  
IO  
mcspi3_clk  
gpio_130  
safe_mode  
mmc2_cmd  
mcspi3_simo  
gpio_131  
AG5  
AH5  
NA  
NA  
O
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
IO  
safe_mode  
mmc2_dat0  
mcspi3_somi  
gpio_132  
IO  
IO  
IO  
safe_mode  
mmc2_dat1  
gpio_133  
AH4  
AG4  
NA  
NA  
IO  
IO  
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_dat2  
mcspi3_cs1  
gpio_134  
IO  
O
IO  
safe_mode  
mmc2_dat3  
mcspi3_cs0  
gpio_135  
AF4  
AE4  
NA  
NA  
IO  
IO  
IO  
H
L
H
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_dat4  
mmc2_dir_dat0  
mmc3_dat0  
gpio_136  
IO  
O
IO  
IO  
safe_mode  
32  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
AH3  
NA  
mmc2_dat5  
mmc2_dir_dat1  
cam_global_reset  
mmc3_dat1  
gpio_137  
0
1
2
3
4
6
7
0
1
2
3
4
7
0
1
3
4
6
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
2
4
7
0
1
2
4
7
0
1
2
4
7
0
1
2
4
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
IO  
IO  
IO  
mm3_rxdp  
safe_mode  
mmc2_dat6  
mmc2_dir_cmd  
cam_shutter  
mmc3_dat2  
gpio_138  
AF3  
NA  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
O
IO  
IO  
safe_mode  
mmc2_dat7  
mmc2_clkin  
mmc3_dat3  
gpio_139  
AE3  
NA  
IO  
I
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
IO  
IO  
mm3_rxdm  
safe_mode  
mcbsp3_dx  
uart2_cts  
AF6  
AE6  
AF5  
AE5  
AB26  
NA  
NA  
NA  
NA  
NA  
IO  
I
L
L
L
L
H
L
L
L
L
H
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_140  
IO  
safe_mode  
mcbsp3_dr  
uart2_rts  
I
O
IO  
gpio_141  
safe_mode  
mcbsp3_clkx  
uart2_tx  
IO  
O
gpio_142  
IO  
safe_mode  
mcbsp3_fsx  
uart2_rx  
IO  
I
gpio_143  
IO  
safe_mode  
uart2_cts  
I
mcbsp3_dx  
gpt_9_pwm_evt  
gpio_144  
IO  
IO  
IO  
safe_mode  
uart2_rts  
AB25  
AA25  
AD25  
NA  
NA  
NA  
O
I
H
H
H
H
H
H
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
mcbsp3_dr  
gpt_10_pwm_evt  
gpio_145  
IO  
IO  
safe_mode  
uart2_tx  
O
mcbsp3_clkx  
gpt_11_pwm_evt  
gpio_146  
IO  
IO  
IO  
safe_mode  
uart2_rx  
I
mcbsp3_fsx  
gpt_8_pwm_evt  
gpio_147  
IO  
IO  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
33  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
safe_mode  
uart1_tx  
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
4
6
7
0
4
6
7
0
4
6
7
0
4
6
7
0
1
4
7
0
2
4
7
0
1
2
4
7
0
1
2
4
7
0
2
4
5
7
AA8  
AA9  
W8  
Y8  
NA  
O
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_148  
IO  
safe_mode  
uart1_rts  
NA  
NA  
NA  
O
gpio_149  
IO  
safe_mode  
uart1_cts  
I
gpio_150  
IO  
safe_mode  
uart1_rx  
I
mcbsp1_clkr  
mcspi4_clk  
gpio_151  
IO  
IO  
IO  
safe_mode  
mcbsp4_clkx  
gpio_152  
AE1  
AD1  
AD2  
AC1  
Y21  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mm3_txse0  
safe_mode  
mcbsp4_dr  
gpio_153  
I
IO  
IO  
mm3_rxrcv  
safe_mode  
mcbsp4_dx  
gpio_154  
IO  
IO  
IO  
mm3_txdat  
safe_mode  
mcbsp4_fsx  
gpio_155  
IO  
IO  
IO  
mm3_txen_n  
safe_mode  
mcbsp1_clkr  
mcspi4_clk  
gpio_156  
IO  
IO  
IO  
safe_mode  
mcbsp1_fsr  
cam_global_reset  
gpio_157  
AA21  
V21  
IO  
IO  
IO  
safe_mode  
mcbsp1_dx  
mcspi4_simo  
mcbsp3_dx  
gpio_158  
IO  
IO  
IO  
IO  
safe_mode  
mcbsp1_dr  
mcspi4_somi  
mcbsp3_dr  
gpio_159  
U21  
T21  
NA  
NA  
I
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
IO  
I
IO  
safe_mode  
mcbsp_clks  
cam_shutter  
gpio_160  
I
PU/ PD  
O
IO  
I
uart1_cts  
safe_mode  
34  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
K26  
NA  
mcbsp1_fsx  
mcspi4_cs0  
mcbsp3_fsx  
gpio_161  
0
1
2
4
7
0
2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
IO  
IO  
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp1_clkx  
mcbsp3_clkx  
gpio_162  
W21  
NA  
IO  
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
safe_mode  
uart3_cts_rctx  
gpio_163  
H18  
H19  
H20  
H21  
T28  
T25  
R28  
T26  
T27  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
H
H
H
H
L
H
H
H
H
L
7
7
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
8
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
uart3_rts_sd  
gpio_164  
O
IO  
safe_mode  
uart3_rx_irrx  
gpio_165  
I
IO  
safe_mode  
uart3_tx_irtx  
gpio_166  
O
IO  
safe_mode  
hsusb0_clk  
gpio_120  
I
IO  
safe_mode  
hsusb0_stp  
gpio_121  
O
H
L
H
L
IO  
safe_mode  
hsusb0_dir  
gpio_122  
I
IO  
safe_mode  
hsusb0_nxt  
gpio_124  
I
L
L
IO  
safe_mode  
hsusb0_data0  
uart3_tx_irtx  
gpio_125  
IO  
O
L
L
IO  
O
uart2_tx  
safe_mode  
hsusb0_data1  
uart3_rx_irrx  
gpio_130  
U28  
U27  
U26  
U25  
NA  
NA  
NA  
NA  
IO  
I
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
uart2_rx  
safe_mode  
hsusb0_data2  
uart3_rts_sd  
gpio_131  
IO  
O
IO  
O
uart2_rts  
safe_mode  
hsusb0_data3  
uart3_cts_rctx  
gpio_169  
IO  
IO  
IO  
I
uart2_cts  
safe_mode  
hsusb0_data4  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
35  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
gpio_188  
4
7
0
4
7
0
4
7
0
4
7
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
1
7
0
1
7
0
1
2
3
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
IO  
safe_mode  
hsusb0_data5  
gpio_189  
V28  
V27  
V26  
NA  
NA  
NA  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
hsusb0_data6  
gpio_190  
IO  
IO  
safe_mode  
hsusb0_data7  
gpio_191  
IO  
IO  
safe_mode  
i2c1_scl  
K21  
J21  
NA  
NA  
NA  
OD  
IOD  
OD  
IO  
H
H
H
H
H
H
0
0
7
vdds  
vdds  
vdds  
NA  
3
3
3
4
PU/ PD(6)(7) Open Drain  
i2c1_sda  
Yes  
Yes  
PU/ PD(6)(7) Open Drain  
(8)  
AF15  
i2c2_scl  
PU/ PD(6)  
PU/ PD(6)  
PU/ PD(6)  
PU/ PD(6)  
Open Drain  
Open Drain  
Open Drain  
Open Drain  
gpio_168  
safe_mode  
i2c2_sda  
(8)  
(8)  
(8)  
AE15  
AF14  
AG14  
AD26  
AE26  
J25  
NA  
NA  
NA  
NA  
NA  
NA  
IOD  
IO  
H
H
H
H
H
H
H
H
H
H
H
H
7
7
7
0
0
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
3
4
gpio_183  
safe_mode  
i2c3_scl  
OD  
IO  
3
4
gpio_184  
safe_mode  
i2c3_sda  
IOD  
IO  
3
4
gpio_185  
safe_mode  
i2c4_scl  
OD  
O
3
4
PU/ PD(6)(7) Open Drain  
PU/ PD(6)(7) Open Drain  
sys_ nvmode1  
safe_mode  
i2c4_sda  
IOD  
O
3
4
sys_ nvmode2  
safe_mode  
hdq_sio  
IOD  
I
4
PU/ PD  
LVCMOS  
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
gpio_170  
OD  
OD  
IO  
safe_mode  
mcspi1_clk  
mmc2_dat4  
gpio_171  
AB3  
AB4  
AA4  
AC2  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
IO  
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcspi1_ simo  
mmc2_dat5  
gpio_172  
IO  
IO  
IO  
L
L
safe_mode  
mcspi1_ somi  
mmc2_dat6  
gpio_173  
IO  
IO  
IO  
L
L
safe_mode  
mcspi1_cs0  
mmc2_dat7  
gpio_174  
IO  
IO  
IO  
H
H
H
H
safe_mode  
mcspi1_cs1  
AC3  
O
36  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
mmc3_cmd  
gpio_175  
3
4
7
0
3
4
7
0
3
4
5
7
0
3
4
7
0
1
3
4
7
0
1
3
4
7
0
1
3
4
7
0
1
3
4
5
7
0
0
O
IO  
safe_mode  
mcspi1_cs2  
mmc3_clk  
AB1  
AB2  
NA  
NA  
O
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
IO  
gpio_176  
safe_mode  
mcspi1_cs3  
hsusb2_ data2  
gpio_177  
O
IO  
IO  
IO  
mm2_txdat  
safe_mode  
mcspi2_clk  
hsusb2_ data7  
gpio_178  
AA3  
Y2  
NA  
NA  
IO  
IO  
IO  
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcspi2_ simo  
gpt_9_pwm_evt  
hsusb2_ data4  
gpio_179  
IO  
IO  
IO  
IO  
safe_mode  
mcspi2_ somi  
gpt_10_pwm_evt  
hsusb2_ data5  
gpio_180  
Y3  
Y4  
V3  
NA  
NA  
NA  
IO  
IO  
IO  
IO  
L
H
L
L
H
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcspi2_cs0  
gpt_11_pwm_evt  
hsusb2_ data6  
gpio_181  
IO  
IO  
IO  
IO  
safe_mode  
mcspi2_cs1  
gpt_8_pwm_evt  
hsusb2_ data3  
gpio_182  
O
IO  
IO  
IO  
IO  
mm2_txen_n  
safe_mode  
sys_32k  
AE25  
AE17  
NA  
NA  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
NA  
NA  
PU/ PD  
No  
LVCMOS  
sys_xtalin  
AI  
LVCMOS  
Analog  
AF17  
AF25  
NA  
NA  
sys_xtalout  
0
AO  
Z
0
0
0
0
vdds  
vdds  
NA  
NA  
4
NA  
LVCMOS  
Analog  
sys_clkreq  
gpio_1  
0
4
7
0
4
7
0
0
4
7
0
3
4
IO  
IO  
See (11)  
Yes  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
sys_nirq  
AF26  
NA  
I
H
H
7
vdds  
Yes  
4
PU/ PD  
gpio_0  
IO  
safe_mode  
sys_nrespwron  
sys_nreswarm  
gpio_30  
AH25  
AF24  
NA  
NA  
I
Z
0
Z
1
0
0
vdds  
vdds  
Yes  
Yes  
NA  
4
No  
LVCMOS  
LVCMOS  
Open Drain  
IOD  
IO  
PU/ PD  
safe_mode  
sys_boot0  
dss_data18  
gpio_2  
AH26  
NA  
I
Z
Z
0
vdds  
Yes  
8
PU/ PD  
LVCMOS  
IO  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
37  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
safe_mode  
sys_boot1  
dss_data19  
gpio_3  
7
0
3
4
7
0
4
7
0
3
4
7
0
1
3
4
7
0
1
3
4
7
0
3
4
7
0
4
7
0
4
7
0
4
7
0
0
0
0
0
0
0
4
7
0
4
7
0
1
2
3
4
5
7
AG26  
NA  
I
Z
Z
0
vdds  
Yes  
8
PU/ PD  
LVCMOS  
IO  
IO  
safe_mode  
sys_boot2  
gpio_4  
AE14  
AF18  
NA  
NA  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
sys_boot3  
dss_data20  
gpio_5  
I
O
IO  
safe_mode  
sys_boot4  
mmc2_dir_dat2  
dss_data21  
gpio_6  
AF19  
AE21  
AF21  
NA  
NA  
NA  
I
Z
Z
Z
Z
Z
Z
0
0
0
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
O
O
IO  
safe_mode  
sys_boot5  
mmc2_dir_dat3  
dss_data22  
gpio_7  
I
O
O
IO  
safe_mode  
sys_boot6  
dss_data23  
gpio_8  
I
O
IO  
safe_mode  
sys_off_mode  
gpio_9  
AF22  
AG25  
AE22  
NA  
NA  
NA  
O
0
L
L
L
L
L
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
sys_clkout1  
gpio_10  
O
7(14)  
IO  
safe_mode  
sys_clkout2  
gpio_186  
safe_mode  
jtag_ntrst  
jtag_tck  
O
7
IO  
AA17  
AA13  
AA12  
AA18  
AA20  
AA19  
AA11  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
I
L
L
0
0
0
0
0
0
0
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
NA  
NA  
NA  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
I
L
L
jtag_rtck  
O
IO  
I
L
0
jtag_tms_tmsc  
jtag_tdi  
H
H
L
H
H
Z
H
Yes  
Yes  
NA  
4
NA  
4
jtag_tdo  
O
IO  
IO  
jtag_emu0  
gpio_11  
H
Yes  
4
safe_mode  
jtag_emu1  
gpio_31  
AA10  
AF10  
NA  
NA  
IO  
IO  
H
H
H
H
0
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
etk_clk  
O
mcbsp5_ clkx  
mmc3_clk  
hsusb1_stp  
gpio_12  
IO  
IO  
O
IO  
IO  
O
mm1_rxdp  
hw_dbg0  
38  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
[2]  
TYPE [12]  
STATE [7]  
AE10  
NA  
etk_ctl  
0
2
3
4
7
0
1
2
3
4
5
7
0
1
3
4
5
7
0
1
3
4
5
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
5
O
H
H
4
vdds  
Yes  
4
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_cmd  
hsusb1_clk  
gpio_13  
O
O
IO  
O
hw_dbg1  
AF11  
NA  
etk_d0  
O
H
H
4
vdds  
Yes  
4
PU/ PD  
mcspi3_ simo  
mmc3_dat4  
hsusb1_ data0  
gpio_14  
IO  
IO  
IO  
IO  
IO  
O
mm1_rxrcv  
hw_dbg2  
AG12  
AH12  
AE13  
AE11  
AH9  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
etk_d1  
O
H
H
H
L
H
H
H
L
4
4
4
4
4
4
4
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_ somi  
hsusb1_ data1  
gpio_15  
IO  
IO  
IO  
IO  
O
mm1_txse0  
hw_dbg3  
etk_d2  
O
mcspi3_cs0  
hsusb1_ data2  
gpio_16  
IO  
IO  
IO  
IO  
O
mm1_txdat  
hw_dbg4  
etk_d3  
O
mcspi3_clk  
mmc3_dat3  
hsusb1_ data7  
gpio_17  
IO  
IO  
IO  
IO  
O
hw_dbg5  
etk_d4  
O
mcbsp5_dr  
mmc3_dat0  
hsusb1_ data4  
gpio_18  
I
IO  
IO  
IO  
O
hw_dbg6  
etk_d5  
O
L
L
mcbsp5_fsx  
mmc3_dat1  
hsusb1_ data5  
gpio_19  
IO  
IO  
IO  
IO  
O
hw_dbg7  
AF13  
etk_d6  
O
L
L
mcbsp5_dx  
mmc3_dat2  
hsusb1_ data6  
gpio_20  
O
IO  
IO  
IO  
O
hw_dbg8  
AH14  
etk_d7  
O
L
L
mcspi3_cs1  
mmc3_dat7  
hsusb1_ data3  
gpio_21  
O
IO  
IO  
IO  
IO  
mm1_txen_n  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
39  
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Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
hw_dbg9  
etk_d8  
7
0
2
3
4
7
0
2
3
4
5
7
0
2
3
4
7
0
3
4
5
7
0
3
4
7
0
3
4
5
7
0
3
4
5
7
0
3
4
5
7
0
0
0
0
0
0
0
0
O
AF9  
AG9  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
PU/ PD  
LVCMOS  
mmc3_dat6  
hsusb1_dir  
gpio_22  
IO  
I
IO  
O
hw_dbg10  
etk_d9  
NA  
O
4
PU/ PD  
LVCMOS  
mmc3_dat5  
hsusb1_nxt  
gpio_23  
IO  
I
IO  
IO  
O
mm1_rxdm  
hw_dbg11  
etk_d10  
AE7  
AF7  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
uart1_rx  
I
hsusb2_clk  
gpio_24  
O
IO  
O
hw_dbg12  
etk_d11  
O
PU/ PD  
hsusb2_stp  
gpio_25  
O
IO  
IO  
O
mm2_rxdp  
hw_dbg13  
etk_d12  
AG7  
AH7  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_dir  
gpio_26  
I
IO  
O
hw_dbg14  
etk_d13  
O
hsusb2_nxt  
gpio_27  
I
IO  
IO  
O
mm2_rxdm  
hw_dbg15  
etk_d14  
AG8  
AH8  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_ data0  
gpio_28  
IO  
IO  
IO  
O
mm2_rxrcv  
hw_dbg16  
etk_d15  
O
PU/ PD  
hsusb2_ data1  
gpio_29  
IO  
IO  
IO  
O
mm2_txse0  
hw_dbg17  
vss  
AH21  
AG16  
M28  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vss  
vss  
AH20  
AG20  
AG21  
H28  
cap_vddu_array  
vdds  
vdds  
vdds  
P25  
vdds_x  
40  
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BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
[2]  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
TYPE [12]  
STATE [7]  
AE9, AE18, NA  
AE19, AE24,  
AC4, Y16,  
Y18, Y19,  
Y20, W18,  
W20, V20,  
U19, U20,  
T19, P20,  
N19, N20,  
M19, M25,  
L25, K18,  
K20, J4,  
vdd_core  
0
PWR  
-
-
-
-
-
-
-
-
J18, J19,  
J20, H4,  
E25, D8, D9,  
D15, D22,  
D23  
Y9, Y10,  
NA  
vdd_mpu_iva  
0
PWR  
-
-
-
-
-
-
-
-
Y11, Y14,  
Y15, W9,  
W11, W12,  
W15, U10,  
T9, T10, R9,  
R10, N10,  
M9, M10,  
L9, L10,  
K11, K14,  
K13, J9,  
J10, J11,  
J14, J15  
AH6, U1,  
AC5, P1,  
vdds_mem  
0
PWR  
-
-
-
-
-
-
-
-
R4, J1, J2, H1, F23, E1,  
G28, F1, F2, C23, A4, A7,  
D16, C16,  
A10, A15,  
C28, B5, B8, A18  
B12, B18,  
B22, A5, A8,  
A12, A18,  
A22  
AG27, AF8, NA  
AF16, AF23,  
AE8, AE16,  
AE23, AD3,  
AD4, W4,  
vdds  
0
PWR  
-
-
-
-
-
-
-
-
F25, F26  
W16  
K15  
NA  
NA  
NA  
NA  
vdds_sram  
0
0
0
0
PWR  
PWR  
PWR  
PWR  
vdda_dplls_dll  
vdda_dpll_per  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AA16  
AA14  
vdda_wkup_  
bg_bb  
K25  
V25  
Y26  
NA  
NA  
NA  
vdds_mmc1  
vdda_dac  
vssa_dac  
0
0
0
PWR  
PWR  
GND  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
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Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
BOTTOM  
[1]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
/DOWN  
TYPE [12]  
BALL TOP  
[2]  
IO CELL  
[13]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
STATE [7]  
AG2, AG3, B4, B7, B10, vss  
AG6, AF12, B15, B18,  
AF20, AE12, C22, E2,  
0
GND  
-
-
-
-
-
-
-
-
AE20,  
AC25,  
F22, H2, P2,  
AB5, AB14,  
AC26, Y12, AB20  
Y13, Y25,  
W3, W10,  
W13, W14,  
W17, W19,  
W25, V9,  
V10, V19,  
U2, U9, T20,  
R19, R20,  
R26, P3, P4,  
P9, P10,  
P19, N9,  
M20, L19,  
L20, L26,  
K9, K10,  
K12, K16,  
K17, K19,  
J3, J12, J13,  
J16, J17,  
G27, E3,E4,  
D7, D10,  
D13, D19,  
D21, C7,  
C10, C13,  
C19, C22,  
B2, B27, A3,  
A26  
AA15  
NA  
cap_vddu_wkup_  
logic  
0
-
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AH10,  
AH11,  
AH13,  
AH15,  
AH16,  
AG11,  
A12, AA1,  
Feed-Through  
AA23, AB11, Pins(9)  
AB9, AC11,  
AC13,  
AC14, AC8,  
AC9, H23,  
AG13, AF1, K1, L1, U1,  
AF28, AE28, Y23, A1, A2,  
AA1, N1,  
M1, J28,  
A15, M2,  
A22, A23,  
AB1, AB23,  
AC1, AC2,  
N2, A1, A2, AC22,  
A27, A28,  
AC23, B1,  
AG1, AG28, B23, AA2,  
AH1, AH2, U2, AA22,  
AH27,  
AB8, AB13,  
B12, H22,  
K2, K22, L2  
AH28, B1,  
B28, AA2,  
AF2, AF27,  
AG10,  
AG15, B15,  
J27, M26  
42  
TERMINAL DESCRIPTION  
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BALL  
SPRS685–AUGUST 2010  
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)  
BALL  
RESET  
REL.  
BUFFER  
STRENG  
TH (mA)  
[11]  
BALL  
RESET  
STATE [6]  
RESET  
PULLUP  
IO CELL  
/DOWN  
[13]  
BALL TOP  
[2]  
BOTTOM  
[1]  
PIN NAME [3]  
MODE [4]  
TYPE [5]  
REL. MODE POWER [9] HYS [10]  
[8]  
TYPE [12]  
STATE [7]  
G1, A13,  
A14,A16,  
AB2, AB22, No Connect(2)  
B2, B22  
-
-
A17, B14,  
B16, B17,  
C14, C15,  
C17, D17,  
D18, H9,  
H10, H11,  
H12, H13,  
H14, H15,  
H16, H17,  
A4, A6, A7,  
A9, A10,  
A11, A19,  
A20, A21,  
B3, B4, B6,  
B7, B9, B10,  
B11, B13,  
B19, B20,  
B21, C1,C2,  
C3, C4,C5,  
C6, C8,C9,  
C11, C12,  
C18, C20,  
C21, D1,  
D2, D3, D4,  
D5,D6, D11,  
D12,D14,  
D20, E1,E2,  
AA26,AE27,  
A27, A28,  
B28, AG1,  
AG28, AH1,  
AH2,AH27,  
AH28  
Y17  
U4  
NA  
NA  
sys_xtalgnd  
0
0
GND  
PWR  
cap_vdd_bb_  
mpu_iva  
V4  
NA  
NA  
cap_vdd_sram  
_mpu_iva  
0
0
PWR  
PWR  
L21  
cap_vdd_sram_core  
(1) The usage of this GPIO is strongly restricted. For more information, see the GPIO chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
(2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior.  
(3) NA in this table stands for "Not Applicable".  
(4) The drive strength is fixed regardless of the load. The driver is designed to drive 75-ohm for video applications.  
(5) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode.  
For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in  
the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
PD: 30 to 150 kΩ.  
(6) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described below:  
Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load range  
of 5 pF to 15 pF.  
(7) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive  
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,  
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module / SCM Programming Model / Feature Settings section  
and the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4) to modify the IO settings if required by the targeted interface application.  
(8) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see  
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and  
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the  
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to  
modify the IO settings if required by the targeted interface application.  
(9) These signals are feed-through balls. For more information, see Table 2-28.  
(10) In buffer mode, the drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications. In bypass  
mode, the drive strength is 0.47 mA.  
(11) Depending on the sys_clkreq direction the corresponding reset released state value can be:  
–
–
Z if sys_clkreq is used as input  
1 if sys_clkreq is used as output  
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For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
(12) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full  
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
(13) In the safe_mode_out1, the buffer is configured to drive 1.  
(14) Mux0 if sys_boot6 is pulled down (clock master).  
Table 2-2. Ball Characteristics (CBC Pkg.)(5)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
AE16  
NA  
cam_d0  
0
4
7
0
4
7
4
7
4
7
4
7
4
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
7
0
0
0
0
0
0
0
0
0
0
0
I
L
L
7
vdda  
vdda  
Yes  
Yes  
NA  
PU/ PD  
LVCMOS  
gpio_99  
I
safe_mode  
cam_d1  
-
AE15  
NA  
I
L
L
7
NA  
PU/ PD  
LVCMOS  
gpio_100  
safe_mode  
gpio_112  
safe_mode  
gpio_114  
safe_mode  
gpio_113  
safe_mode  
gpio_115  
safe_mode  
sdrc_a0  
I
-
AD17  
AE18  
AD16  
NA  
NA  
NA  
I
L
L
L
L
L
L
7
7
7
vdda  
vdda  
vdda  
Yes  
Yes  
Yes  
NA  
NA  
NA  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
-
I
-
I
-
I
AE17  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
-
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
vdda  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(1)  
G20  
K20  
J20  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
4
sdrc_a1  
4(1)  
(1)  
sdrc_a2  
4
(1)  
J21  
sdrc_a3  
4
(1)  
U21  
R20  
M21  
M20  
N20  
K21  
Y16  
N21  
R21  
AA15  
Y12  
AA18  
V20  
Y15  
sdrc_a4  
4
(1)  
sdrc_a5  
4
(1)  
sdrc_a6  
4
(1)  
sdrc_a7  
4
(1)  
sdrc_a8  
4
(1)  
sdrc_a9  
4
(1)  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ba0  
sdrc_ba1  
sdrc_cke0  
safe_mode_out1(6)  
sdrc_cke1  
safe_mode_out1(6)  
sdrc_clk  
4
4(1)  
(1)  
4
(1)  
4
(1)  
4
(1)  
4
4(1)  
(1)  
4
(1)  
NA  
Y13  
O
H
1
7
vdds  
NA  
4
PU/ PD  
LVCMOS  
(1)  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
A12  
D1  
G1  
G2  
E1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(1)  
sdrc_d0  
4
(1)  
sdrc_d1  
4
(1)  
sdrc_d2  
4
sdrc_d3  
4(1)  
(1)  
D2  
E2  
sdrc_d4  
4
(1)  
sdrc_d5  
4
(1)  
B3  
sdrc_d6  
4
(1)  
B4  
sdrc_d7  
4
(1)  
A10  
B11  
sdrc_d8  
4
(1)  
sdrc_d9  
4
44  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
 
 
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
TYPE [12]  
(1)  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AE21  
A11  
B12  
A16  
A17  
B17  
B18  
B7  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
sdrc_ncas  
sdrc_nclk  
sdrc_ncs0  
sdrc_ncs1  
sdrc_nras  
sdrc_nwe  
dss_data0  
uart1_cts  
gpio_70  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
2
4
7
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0
0
0
0
L
L
L
L
1
1
1
1
1
1
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
Z
Z
Z
Z
1
1
1
1
1
1
L
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdda  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
NA  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
4(1)  
(1)  
4
(1)  
4
(1)  
4
(1)  
4
(1)  
4
(1)  
A5  
4
(1)  
B6  
4
(1)  
A6  
4
(1)  
A8  
4
B9  
4(1)  
(1)  
A9  
4
(1)  
B10  
C21  
D20  
B19  
C20  
D21  
E20  
E21  
G21  
H1  
4
(1)  
4
(1)  
4
(1)  
4
(1)  
4
4(1)  
(1)  
4
(1)  
4
4(1)  
(1)  
4
(1)  
A14  
A4  
O
NA  
4
O
NA  
4(1)  
(1)  
A18  
C2  
O
NA  
4
(1)  
IO  
IO  
IO  
IO  
O
Yes  
Yes  
Yes  
Yes  
NA  
4
(1)  
B15  
B8  
4
(1)  
4
(1)  
A19  
U20  
B13  
T21  
T20  
V21  
Y18  
NA  
4
(1)  
4
(1)  
O
NA  
4
(1)  
O
NA  
4
(1)  
O
NA  
4
(1)  
O
NA  
4
(1)  
O
NA  
4
IO  
I
Yes  
8
8
IO  
-
safe_mode  
dss_data1  
uart1_rts  
gpio_71  
AE22  
NA  
IO  
O
L
L
7
vdda  
Yes  
PU/ PD  
LVCMOS  
IO  
-
safe_mode  
dss_data2  
gpio_72  
AE23  
AE24  
AD23  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
7
7
7
vdda  
vdda  
vdda  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data3  
gpio_73  
IO  
IO  
-
safe_mode  
dss_data4  
uart3_rx_irrx  
gpio_74  
IO  
I
IO  
-
safe_mode  
dss_data5  
AD24  
NA  
IO  
L
L
7
vdda  
Yes  
8
PU/ PD  
LVCMOS  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
45  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
uart3_tx_irtx  
gpio_75  
2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
2
3
4
7
0
3
4
7
0
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
O
IO  
-
safe_mode  
dss_data10  
gpio_80  
AC26  
AD26  
AA25  
Y25  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
H
L
L
L
L
L
L
H
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data11  
gpio_81  
IO  
IO  
-
safe_mode  
dss_data12  
gpio_82  
IO  
IO  
-
safe_mode  
dss_data13  
gpio_83  
IO  
IO  
-
safe_mode  
dss_data14  
gpio_84  
AA26  
AB26  
F25  
IO  
IO  
-
safe_mode  
dss_data15  
gpio_85  
IO  
IO  
-
safe_mode  
dss_data20  
mcspi3_somi  
dss_data2  
gpio_90  
O
IO  
IO  
IO  
-
safe_mode  
dss_data22  
mcspi3_cs1  
dss_data4  
gpio_92  
AC25  
NA  
O
O
IO  
IO  
-
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
safe_mode  
dss_data23  
dss_data5  
gpio_93  
AB25  
G25  
NA  
NA  
O
IO  
IO  
-
L
L
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
dss_pclk  
O
IO  
O
-
H
H
gpio_66  
hw_dbg12  
safe_mode  
gpmc_a1  
gpio_34  
J2  
NA  
NA  
NA  
NA  
NA  
NA  
O
IO  
-
L
L
L
L
L
H
L
L
L
L
L
H
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_a2  
gpio_35  
H1  
H2  
G2  
F1  
O
IO  
-
safe_mode  
gpmc_a3  
gpio_36  
O
IO  
-
safe_mode  
gpmc_a4  
gpio_37  
O
IO  
-
safe_mode  
gpmc_a5  
gpio_38  
O
IO  
-
safe_mode  
gpmc_a6  
F2  
O
46  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
gpio_39  
4
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
4
7
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
4
7
IO  
-
safe_mode  
gpmc_a7  
gpio_40  
E1  
E2  
D1  
NA  
NA  
NA  
O
IO  
-
H
H
H
H
H
H
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_a8  
gpio_41  
O
IO  
-
7
safe_mode  
gpmc_a9  
sys_ndmareq2  
gpio_42  
O
I
7
IO  
-
safe_mode  
gpmc_a10  
sys_ndmareq3  
gpio_43  
D2  
N1  
NA  
L1  
O
I
H
L
H
0
7
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
-
safe_mode  
gpmc_clk  
gpio_59  
O
IO  
-
safe_mode  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpio_44  
AA2  
AA1  
AC2  
AC1  
AE5  
AD6  
AD5  
AC5  
V1  
U2  
U1  
V2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
V1  
AA3  
AA4  
Y3  
Y4  
R1  
safe_mode  
gpmc_d9  
gpio_45  
Y1  
T1  
U2  
U1  
P1  
L2  
T1  
N1  
P2  
P1  
M1  
J2  
IO  
IO  
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_d10  
gpio_46  
IO  
IO  
-
safe_mode  
gpmc_d11  
gpio_47  
IO  
IO  
-
safe_mode  
gpmc_d12  
gpio_48  
IO  
IO  
-
safe_mode  
gpmc_d13  
gpio_49  
IO  
IO  
-
safe_mode  
gpmc_d14  
gpio_50  
IO  
IO  
-
safe_mode  
gpmc_d15  
gpio_51  
M2  
K2  
IO  
IO  
-
safe_mode  
gpmc_nadv_ale  
gpmc_nbe0_cle  
gpio_60  
AD10  
K2  
AA9  
NA  
O
O
IO  
-
0
L
0
0
0
0
vdds  
vdds  
NA  
8
8
NA  
LVCMOS  
LVCMOS  
Yes  
PU/ PD  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
47  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
J1  
NA  
gpmc_nbe1  
gpio_61  
0
4
7
0
0
4
7
0
4
7
0
1
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
0
0
4
7
0
0
4
7
0
2
4
7
0
1
2
4
O
IO  
-
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
safe_mode  
gpmc_ncs0  
gpmc_ncs1  
gpio_52  
AD8  
AD1  
AA8  
W1  
O
O
IO  
-
1
1
1
0
0
vdds  
vdds  
NA  
8
8
NA  
LVCMOS  
LVCMOS  
H
Yes  
PU/ PD  
safe_mode  
gpmc_ncs2  
gpio_53  
A3  
B6  
NA  
NA  
O
IO  
-
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_ncs3  
sys_ndmareq0  
gpio_54  
O
I
IO  
-
safe_mode  
gpmc_ncs4  
sys_ndmareq1  
mcbsp4_clkx  
gpt_9_pwm_evt  
gpio_55  
B4  
C4  
B5  
C5  
NA  
NA  
NA  
NA  
O
I
H
H
H
H
H
H
H
H
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
IO  
-
safe_mode  
gpmc_ncs5  
sys_ndmareq2  
mcbsp4_dr  
gpt_10_pwm_evt  
gpio_56  
O
I
I
IO  
IO  
-
safe_mode  
gpmc_ncs6  
sys_ndmareq3  
mcbsp4_dx  
gpt_11_pwm_evt  
gpio_57  
O
I
IO  
IO  
IO  
-
safe_mode  
gpmc_ncs7  
gpmc_io_dir  
mcbsp4_fsx  
gpt_8_pwm_evt  
gpio_58  
O
O
IO  
IO  
IO  
-
safe_mode  
gpmc_noe  
gpmc_nwe  
gpmc_nwp  
gpio_62  
N2  
L2  
K1  
Y5  
O
O
O
IO  
-
1
1
L
1
1
0
0
0
0
vdds  
vdds  
vdds  
NA  
NA  
Yes  
8
8
8
NA  
LVCMOS  
LVCMOS  
LVCMOS  
M1  
NA  
AC6  
PU/ PD  
safe_mode  
gpmc_wait0  
gpmc_wait1  
gpio_63  
AC11  
AC8  
Y10  
Y8  
I
H
H
H
H
0
7
vdds  
vdds  
Yes  
Yes  
NA  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
IO  
-
safe_mode  
gpmc_wait2  
uart4_tx  
B3  
C6  
NA  
NA  
I
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
-
gpio_64  
safe_mode  
gpmc_wait3  
sys_ndmareq1  
uart4_rx  
I
I
I
gpio_65  
IO  
48  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
safe_mode  
hsusb0_clk  
gpio_120  
7
0
4
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
0
0
0
0
0
4
7
0
-
W19  
V20  
NA  
I
L
L
L
L
7
vdds  
vdds  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
-
safe_mode  
hsusb0_data0  
uart3_tx_irtx  
gpio_125  
NA  
NA  
NA  
NA  
IO  
O
IO  
O
-
7
7
7
7
4
4
4
4
uart2_tx  
safe_mode  
hsusb0_data1  
uart3_rx_irrx  
gpio_130  
Y20  
V18  
W20  
IO  
I
L
L
L
L
L
L
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
uart2_rx  
safe_mode  
hsusb0_data2  
uart3_rts_sd  
gpio_131  
-
IO  
O
IO  
O
-
uart2_rts  
safe_mode  
hsusb0_data3  
uart3_cts_rctx  
gpio_169  
IO  
IO  
IO  
I
uart2_cts  
safe_mode  
hsusb0_data4  
gpio_188  
-
W17  
Y18  
Y19  
Y17  
V19  
W18  
U20  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
H
L
L
L
L
L
L
H
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
hsusb0_data5  
gpio_189  
IO  
IO  
-
safe_mode  
hsusb0_data6  
gpio_190  
IO  
IO  
-
safe_mode  
hsusb0_data7  
gpio_191  
IO  
IO  
-
safe_mode  
hsusb0_dir  
gpio_122  
I
IO  
-
safe_mode  
hsusb0_nxt  
gpio_124  
I
IO  
-
safe_mode  
hsusb0_stp  
gpio_121  
O
IO  
-
safe_mode  
jtag_ntrst  
U15  
W13  
V14  
U16  
Y13  
V15  
N19  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
I
L
L
L
H
L
H
L
L
0
L
H
Z
H
L
0
0
0
0
0
0
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
NA  
NA  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD(3)  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
jtag_rtck  
O
I
jtag_tck  
Yes  
Yes  
NA  
NA  
NA  
4
jtag_tdi  
I
jtag_tdo  
O
IO  
IO  
IO  
-
jtag_tms_tmsc  
mmc1_clk  
gpio_120(8)  
safe_mode  
mmc1_cmd  
Yes  
4
vdds_mmc1 Yes  
1
L18  
NA  
O
L
L
7
vdds_mmc1 Yes  
1
PU/ PD(3)  
LVCMOS  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
49  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
gpio_121(8)  
safe_mode  
mmc1_dat0  
gpio_122(8)  
safe_mode  
mmc1_dat1  
gpio_123(8)  
safe_mode  
mmc1_dat2  
gpio_124(8)  
safe_mode  
mmc1_dat3  
gpio_125(8)  
safe_mode  
gpio_126(8)  
safe_mode  
gpio_127(8)  
safe_mode  
gpio_128(8)  
safe_mode  
gpio_129(8)  
safe_mode  
i2c1_scl  
4
7
0
4
7
0
4
7
0
4
7
0
4
7
4
7
4
7
4
7
4
7
0
0
IO  
-
M19  
M18  
K18  
N20  
NA  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
L
L
7
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
1
1
1
1
PU/ PD(3)  
PU/ PD(3)  
PU/ PD(3)  
PU/ PD(3)  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
-
7
IO  
IO  
-
7
IO  
IO  
-
7
M20  
P17  
P18  
P19  
NA  
NA  
NA  
NA  
IO  
-
L
L
L
L
L
L
L
L
7
7
7
7
vdds_x  
vdds_x  
vdds  
Yes  
Yes  
Yes  
Yes  
1
1
4
1
PU/PD(3)  
PU/PD(3)  
PU/PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
-
IO  
-
(3)  
IO  
-
vdds_x  
PU/PD  
(10)  
J25  
J24  
NA  
NA  
OD  
IOD  
H
H
H
H
0
0
vdds  
vdds  
NA  
3
3
PU/ PD(9)  
PU/ PD(9)  
Open Drain  
(10)  
i2c1_sda  
Yes  
LVCMOS  
Open Drain  
C2  
NA  
NA  
NA  
NA  
NA  
i2c2_scl  
0
OD  
H
H
H
H
L
H
H
H
H
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
3
PU/ PD(9)(11) LVCMOS  
Open Drain  
gpio_168  
safe_mode  
i2c2_sda  
4
7
0
IO  
-
4
4
3
C1  
IOD  
PU/ PD(9)(11) LVCMOS  
Open Drain  
gpio_183  
safe_mode  
i2c3_scl  
4
7
0
IO  
-
4
4
3
AB4  
AC4  
U19  
OD  
PU/ PD(9)(11) LVCMOS  
Open Drain  
gpio_184  
safe_mode  
i2c3_sda  
4
7
0
IO  
-
4
4
3
IOD  
PU/ PD(9)(11) LVCMOS  
Open Drain  
gpio_185  
4
7
0
1
4
7
0
2
4
7
0
1
2
4
7
0
1
2
IO  
-
4
4
4
safe_mode  
mcbsp1_clkr  
mcspi4_clk  
gpio_156  
IO  
IO  
IO  
-
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp1_clkx  
mcbsp3_clkx  
gpio_162  
T17  
T20  
NA  
NA  
IO  
IO  
IO  
-
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
safe_mode  
mcbsp1_dr  
mcspi4_somi  
mcbsp3_dr  
gpio_159  
I
IO  
I
IO  
-
safe_mode  
mcbsp1_dx  
mcspi4_simo  
mcbsp3_dx  
U17  
NA  
IO  
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
50  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
gpio_158  
4
7
0
2
4
7
0
1
2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
3
4
7
0
1
4
7
0
1
4
7
0
3
4
7
0
1
3
4
7
0
1
3
IO  
-
safe_mode  
mcbsp1_fsr  
cam_global_reset  
gpio_157  
V17  
P20  
NA  
IO  
IO  
IO  
-
L
L
L
L
7
vdds  
vdds  
Yes  
Yes  
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp1_fsx  
mcspi4_cs0  
mcbsp3_fsx  
gpio_161  
NA  
IO  
IO  
IO  
IO  
-
7
4
safe_mode  
mcbsp2_clkx  
gpio_117  
R18  
T18  
R19  
U18  
P9  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp2_dr  
gpio_118  
I
IO  
-
safe_mode  
mcbsp2_dx  
gpio_119  
IO  
IO  
-
safe_mode  
mcbsp2_fsx  
gpio_116  
IO  
IO  
-
safe_mode  
mcspi1_clk  
mmc2_dat4  
gpio_171  
IO  
IO  
IO  
-
safe_mode  
mcspi1_cs0  
mmc2_dat7  
gpio_174  
R7  
R9  
P8  
P7  
W7  
V8  
NA  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
IO  
-
H
H
L
H
H
L
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcspi1_cs2  
mmc3_clk  
O
IO  
IO  
-
gpio_176  
safe_mode  
mcspi1_simo  
mmc2_dat5  
gpio_172  
IO  
IO  
IO  
-
safe_mode  
mcspi1_somi  
mmc2_dat6  
gpio_173  
IO  
IO  
IO  
-
L
L
safe_mode  
mcspi2_clk  
hsusb2_data7  
gpio_178  
IO  
IO  
IO  
-
L
L
safe_mode  
mcspi2_cs0  
gpt_11_pwm_evt  
hsusb2_data6  
gpio_181  
IO  
IO  
IO  
IO  
-
H
H
safe_mode  
mcspi2_simo  
gpt_9_pwm_evt  
hsusb2_data4  
W8  
NA  
IO  
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
51  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
gpio_179  
4
7
0
1
3
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
7
0
1
4
7
0
1
4
7
0
1
3
4
7
0
4
7
0
2
3
4
7
0
4
7
0
1
2
4
7
0
1
2
4
IO  
-
safe_mode  
mcspi2_somi  
gpt_10_pwm_evt  
hsusb2_data5  
gpio_180  
U8  
NA  
IO  
IO  
IO  
IO  
-
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
safe_mode  
mmc2_clk  
mcspi3_clk  
gpio_130  
W10  
R10  
T10  
NA  
NA  
NA  
IO  
IO  
IO  
-
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_cmd  
mcspi3_simo  
gpio_131  
O
IO  
IO  
-
H
H
H
H
safe_mode  
mmc2_dat0  
mcspi3_somi  
gpio_132  
IO  
IO  
IO  
-
safe_mode  
mmc2_dat1  
gpio_133  
T9  
NA  
NA  
IO  
IO  
-
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_dat2  
mcspi3_cs1  
gpio_134  
U10  
IO  
O
IO  
-
safe_mode  
mmc2_dat3  
mcspi3_cs0  
gpio_135  
U9  
NA  
NA  
IO  
IO  
IO  
-
H
L
H
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_dat4  
mmc2_dir_dat0  
mmc3_dat0  
gpio_136  
V10  
IO  
O
IO  
IO  
-
safe_mode  
uart1_rts  
R2  
H3  
NA  
NA  
O
IO  
-
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_149  
safe_mode  
uart1_rx  
I
mcbsp1_clkr  
mcspi4_clk  
gpio_151  
IO  
IO  
IO  
-
safe_mode  
uart1_tx  
L4  
NA  
NA  
O
IO  
-
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_148  
safe_mode  
uart2_cts  
Y24  
I
H
H
mcbsp3_dx  
gpt_9_pwm_evt  
gpio_144  
IO  
IO  
IO  
-
safe_mode  
uart2_rts  
AA24  
NA  
O
I
H
H
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
mcbsp3_dr  
gpt_10_pwm_evt  
gpio_145  
IO  
IO  
52  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
safe_mode  
uart2_rx  
7
0
1
2
4
7
0
1
2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
-
AD21  
NA  
I
H
H
7
vdds  
vdds  
Yes  
Yes  
4
PU/ PD  
LVCMOS  
mcbsp3_fsx  
gpt_8_pwm_evt  
gpio_147  
IO  
IO  
IO  
-
safe_mode  
uart2_tx  
AD22  
NA  
O
IO  
IO  
IO  
-
H
H
7
4
PU/ PD  
LVCMOS  
mcbsp3_clkx  
gpt_11_pwm_evt  
gpio_146  
safe_mode  
uart3_cts_rctx  
gpio_163  
F23  
F24  
H24  
G24  
J23  
NA  
NA  
NA  
NA  
NA  
IO  
IO  
-
H
H
H
H
H
H
H
H
H
H
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
uart3_rts_sd  
gpio_164  
O
IO  
-
safe_mode  
uart3_rx_irrx  
gpio_165  
I
IO  
-
safe_mode  
uart3_tx_irtx  
gpio_166  
O
IO  
-
safe_mode  
hdq_sio  
IOD  
LVCMOS  
Open Drain  
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
gpio_170  
safe_mode  
i2c4_scl  
1
2
3
4
7
0
I
OD  
OD  
IO  
-
(10)  
AD15  
W16  
F3  
NA  
NA  
NA  
OD  
H
H
Z
H
H
Z
0
0
0
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
3
PU/ PD(9)  
PU/ PD(9)  
PU/ PD  
LVCMOS  
Open Drain  
sys_nvmode1  
safe_mode  
i2c4_sda  
1
7
0
O
4
4
3
-
(10)  
IOD  
LVCMOS  
Open Drain  
sys_nvmode2  
safe_mode  
sys_boot0  
dss_data18  
gpio_2  
1
7
0
3
4
7
0
3
4
7
0
4
7
0
3
4
7
0
1
3
O
-
4
4
8
I
LVCMOS  
LVCMOS  
IO  
IO  
-
safe_mode  
sys_boot1  
dss_data19  
gpio_3  
D3  
NA  
I
Z
Z
0
vdds  
Yes  
8
PU/ PD  
IO  
IO  
-
safe_mode  
sys_boot2  
gpio_4  
C3  
E3  
NA  
NA  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
-
safe_mode  
sys_boot3  
dss_data20  
gpio_5  
I
O
IO  
-
safe_mode  
sys_boot4  
mmc2_dir_dat2  
dss_data21  
E4  
NA  
I
Z
Z
0
vdds  
Yes  
8
PU/ PD  
LVCMOS  
O
O
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
53  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
gpio_6  
4
7
0
1
3
4
7
0
3
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
4
7
0
4
7
0
IO  
-
safe_mode  
sys_boot5  
mmc2_dir_dat3  
dss_data22  
gpio_7  
G3  
D4  
NA  
I
Z
Z
Z
Z
0
vdds  
vdds  
Yes  
Yes  
8
PU/ PD  
LVCMOS  
LVCMOS  
O
O
IO  
-
safe_mode  
sys_boot6  
dss_data23  
gpio_8  
NA  
I
0
8
PU/ PD  
O
IO  
-
safe_mode  
sys_clkout1  
gpio_10  
AE14  
W11  
W15  
V16  
NA  
NA  
NA  
NA  
O
IO  
-
L
L
0
H
L
7(12)  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
sys_clkout2  
gpio_186  
O
IO  
-
L
7
safe_mode  
sys_clkreq  
gpio_1  
IO  
IO  
-
see (7)  
0
safe_mode  
sys_nirq  
I
H
7
gpio_0  
IO  
-
safe_mode  
sys_nrespwron  
sys_nreswarm  
gpio_30  
V13  
AD7  
NA  
I
Z
0
Z
1
0
0
vdds  
vdds  
Yes  
Yes  
NA  
4
No  
LVCMOS  
LVCMOS  
Open Drain  
AA5  
IOD  
IO  
-
PU/ PD  
safe_mode  
sys_off_mode  
gpio_9  
V12  
NA  
NA  
O
IO  
-
0
Z
L
Z
7
0
vdds  
vdds  
Yes  
Yes  
4
PU/ PD  
NA  
LVCMOS  
safe_mode  
sys_xtalin  
AF19  
AI  
NA  
LVCMOS  
Analog  
AF20  
W26  
V26  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
sys_xtalout  
cvideo1_out  
cvideo2_out  
cvideo1_vfb  
cvideo2_vfb  
cvideo1_rset  
sys_32k  
0
0
0
0
0
0
0
0
4
5
7
0
4
5
7
0
4
5
7
0
4
5
7
AO  
AO  
AO  
AO  
AO  
AIO  
I
Z
0
0
0
0
Z
Z
L
0
0
0
0
0
0
0
0
7
vdds  
NA  
NA  
NA  
NA  
NA  
No  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
8
NA  
Analog  
0
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdds  
NA  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
LVCMOS  
LVCMOS  
0
NA  
W25  
U24  
V23  
NA  
NA  
NA  
Z
NA  
NA  
NA  
AE20  
A24  
Yes  
Yes  
PU/ PD  
PU/ PD  
cam_d2  
I
L
vdds  
gpio_101  
hw_dbg4  
safe_mode  
cam_d3  
IO  
O
-
B24  
D24  
C24  
NA  
NA  
NA  
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_102  
hw_dbg5  
safe_mode  
cam_d4  
IO  
O
-
I
gpio_103  
hw_dbg6  
safe_mode  
cam_d5  
IO  
O
-
I
gpio_104  
hw_dbg7  
safe_mode  
IO  
O
-
54  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
D25  
E26  
B23  
NA  
cam_d10  
gpio_109  
hw_dbg8  
safe_mode  
cam_d11  
gpio_110  
hw_dbg9  
safe_mode  
cam_fld  
0
4
5
7
0
4
5
7
0
2
4
5
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
5
7
0
2
4
5
7
0
4
7
I
L
L
L
L
L
L
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
-
NA  
NA  
I
7
7
8
4
IO  
O
-
IO  
IO  
IO  
O
-
cam_global_reset  
gpio_98  
hw_dbg3  
safe_mode  
cam_hs  
C23  
C26  
D26  
NA  
NA  
NA  
IO  
IO  
O
-
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_94  
hw_dbg0  
safe_mode  
cam_pclk  
gpio_97  
I
IO  
O
-
hw_dbg2  
safe_mode  
cam_strobe  
gpio_126  
hw_dbg11  
safe_mode  
cam_xclka  
gpio_96  
O
IO  
O
-
C25  
E25  
P25  
P26  
N25  
N26  
D23  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
O
IO  
-
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
NA  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
SubLVDS  
SubLVDS  
SubLVDS  
SubLVDS  
LVCMOS  
safe_mode  
cam_xclkb  
gpio_111  
safe_mode  
cam_d6  
O
IO  
-
4
I
NA  
NA  
NA  
NA  
4
gpio_105  
safe_mode  
cam_d7  
I
-
I
gpio_106  
safe_mode  
cam_d8  
I
-
I
gpio_107  
safe_mode  
cam_d9  
I
-
I
NA  
gpio_108  
safe_mode  
cam_vs  
I
-
IO  
IO  
O
-
Yes  
gpio_95  
hw_dbg1  
safe_mode  
cam_wen  
cam_shutter  
gpio_167  
hw_dbg10  
safe_mode  
dss_acbias  
gpio_69  
A23  
F26  
NA  
NA  
I
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
8
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
O
-
O
IO  
-
PU/ PD  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
55  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
G26  
H25  
H26  
J26  
NA  
dss_data6  
uart1_tx  
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
4
7
0
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
0
4
5
7
0
4
7
0
3
4
7
0
3
4
IO  
O
IO  
O
-
L
L
L
L
L
L
L
L
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_76  
hw_dbg14  
safe_mode  
dss_data7  
uart1_rx  
NA  
NA  
NA  
IO  
I
7
7
7
8
8
8
gpio_77  
IO  
O
-
hw_dbg15  
safe_mode  
dss_data8  
uart3_rx_irrx  
gpio_78  
IO  
I
IO  
O
-
hw_dbg16  
safe_mode  
dss_data9  
uart3_tx_irtx  
gpio_79  
IO  
O
IO  
O
-
hw_dbg17  
safe_mode  
dss_data16  
gpio_86  
L25  
L26  
M24  
NA  
NA  
NA  
IO  
IO  
-
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data17  
gpio_87  
IO  
IO  
-
safe_mode  
dss_data18  
mcspi3_clk  
dss_data0  
gpio_88  
IO  
IO  
IO  
IO  
-
safe_mode  
dss_data19  
mcspi3_simo  
dss_data1  
gpio_89  
M26  
N24  
K24  
NA  
NA  
NA  
IO  
IO  
IO  
IO  
-
L
L
H
L
L
H
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data21  
mcspi3_cs0  
dss_data3  
gpio_91  
O
IO  
IO  
IO  
-
safe_mode  
dss_hsync  
gpio_67  
O
IO  
O
-
hw_dbg13  
safe_mode  
dss_vsync  
gpio_68  
M25  
R8  
NA  
NA  
O
IO  
-
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcspi1_cs1  
mmc3_cmd  
gpio_175  
O
O
IO  
-
safe_mode  
mcspi1_cs3  
hsusb2_data2  
gpio_177  
T8  
NA  
O
IO  
IO  
H
H
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
56  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
mm2_txdat  
safe_mode  
mcspi2_cs1  
gpt_8_pwm_evt  
hsusb2_data3  
gpio_182  
5
7
0
1
3
4
5
7
0
2
4
5
7
0
1
2
3
4
5
7
0
2
3
4
7
0
1
2
3
4
5
7
0
1
3
4
5
7
0
1
3
4
5
7
0
1
2
3
4
7
0
1
2
3
4
IO  
-
V9  
NA  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
IO  
IO  
IO  
-
mm2_txen_n  
safe_mode  
mcbsp_clks  
cam_shutter  
gpio_160  
T19  
AB2  
NA  
NA  
I
L
L
7
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
I
uart1_cts  
safe_mode  
etk_clk  
-
O
H
H
PU/ PD  
mcbsp5_clkx  
mmc3_clk  
hsusb1_stp  
gpio_12  
IO  
IO  
O
IO  
IO  
O
mm1_rxdp  
hw_dbg0  
AB3  
AC3  
NA  
NA  
etk_ctl  
O
H
H
H
H
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_cmd  
hsusb1_clk  
gpio_13  
O
O
IO  
O
hw_dbg1  
etk_d0  
O
PU/ PD  
mcspi3_simo  
mmc3_dat4  
hsusb1_data0  
gpio_14  
IO  
IO  
IO  
IO  
IO  
O
mm1_rxrcv  
hw_dbg2  
AD4  
AD3  
AA3  
Y3  
NA  
NA  
NA  
NA  
etk_d1  
O
H
H
H
L
H
H
H
L
4
4
4
4
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_somi  
hsusb1_data1  
gpio_15  
IO  
IO  
IO  
IO  
O
mm1_txse0  
hw_dbg3  
etk_d2  
O
mcspi3_cs0  
hsusb1_data2  
gpio_16  
IO  
IO  
IO  
IO  
O
mm1_txdat  
hw_dbg4  
etk_d3  
O
mcspi3_clk  
mmc3_dat3  
hsusb1_data7  
gpio_17  
IO  
IO  
IO  
IO  
O
hw_dbg5  
etk_d4  
O
mcbsp5_dr  
mmc3_dat0  
hsusb1_data4  
gpio_18  
I
IO  
IO  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
57  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
hw_dbg6  
etk_d5  
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
5
7
0
2
3
4
7
0
2
3
4
5
7
0
2
3
4
7
0
3
4
5
7
0
3
4
7
0
3
4
5
7
0
3
4
5
7
O
AB1  
AE3  
AD2  
NA  
O
L
L
L
L
L
L
4
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
mcbsp5_fsx  
mmc3_dat1  
hsusb1_data5  
gpio_19  
IO  
IO  
IO  
IO  
O
hw_dbg7  
etk_d6  
NA  
O
4
4
mcbsp5_dx  
mmc3_dat2  
hsusb1_data6  
gpio_20  
O
IO  
IO  
IO  
O
hw_dbg8  
etk_d7  
NA  
O
4
4
mcspi3_cs1  
mmc3_dat7  
hsusb1_data3  
gpio_21  
O
IO  
IO  
IO  
IO  
O
mm1_txen_n  
hw_dbg9  
etk_d8  
AA4  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_dat6  
hsusb1_dir  
gpio_22  
IO  
I
IO  
O
hw_dbg10  
etk_d9  
V2  
O
PU/ PD  
mmc3_dat5  
hsusb1_nxt  
gpio_23  
IO  
I
IO  
IO  
O
mm1_rxdm  
hw_dbg11  
etk_d10  
AE4  
AF6  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
uart1_rx  
I
hsusb2_clk  
gpio_24  
O
IO  
O
hw_dbg12  
etk_d11  
O
PU/ PD  
hsusb2_stp  
gpio_25  
O
IO  
IO  
O
mm2_rxdp  
hw_dbg13  
etk_d12  
AE6  
AF7  
NA  
NA  
O
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_dir  
gpio_26  
I
IO  
O
hw_dbg14  
etk_d13  
O
hsusb2_nxt  
gpio_27  
I
IO  
IO  
O
mm2_rxdm  
hw_dbg15  
etk_d14  
AF9  
NA  
O
L
L
4
vdds  
Yes  
4
PU/ PD  
LVCMOS  
hsusb2_data0  
gpio_28  
IO  
IO  
IO  
O
mm2_rxrcv  
hw_dbg16  
58  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
AE9  
NA  
etk_d15  
0
3
4
5
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
6
7
0
4
6
7
0
4
6
7
0
4
6
7
0
1
2
3
4
6
7
0
1
2
3
4
O
IO  
IO  
IO  
O
IO  
IO  
-
L
L
4
vdds  
Yes  
4
PU/ PD  
LVCMOS  
hsusb2_data1  
gpio_29  
mm2_txse0  
hw_dbg17  
jtag_emu0  
gpio_11  
Y15  
Y14  
U3  
NA  
NA  
NA  
H
H
L
H
H
L
0
0
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
jtag_emu1  
gpio_31  
IO  
IO  
-
safe_mode  
mcbsp3_clkx  
uart2_tx  
IO  
O
IO  
-
gpio_142  
safe_mode  
mcbsp3_dr  
uart2_rts  
N3  
P3  
W3  
V3  
U4  
R3  
T3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
I
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
O
IO  
-
gpio_141  
safe_mode  
mcbsp3_dx  
uart2_cts  
IO  
I
gpio_140  
IO  
-
safe_mode  
mcbsp3_fsx  
uart2_rx  
IO  
I
gpio_143  
IO  
-
safe_mode  
mcbsp4_clkx  
gpio_152  
IO  
IO  
IO  
-
mm3_txse0  
safe_mode  
mcbsp4_dr  
gpio_153  
I
IO  
IO  
-
mm3_rxrcv  
safe_mode  
mcbsp4_dx  
gpio_154  
IO  
IO  
IO  
-
mm3_txdat  
safe_mode  
mcbsp4_fsx  
gpio_155  
IO  
IO  
IO  
-
mm3_txen_n  
safe_mode  
mmc2_dat5  
mmc2_dir_dat1  
cam_global_reset  
mmc3_dat1  
gpio_137  
M3  
IO  
O
IO  
IO  
IO  
IO  
-
mm3_rxdp  
safe_mode  
mmc2_dat6  
mmc2_dir_cmd  
cam_shutter  
mmc3_dat2  
gpio_138  
L3  
NA  
IO  
O
O
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
59  
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Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
safe_mode  
mmc2_dat7  
mmc2_clkin  
mmc3_dat3  
gpio_139  
mm3_rxdm  
safe_mode  
uart1_cts  
gpio_150  
safe_mode  
vss  
7
0
1
3
4
6
7
0
4
7
0
0
0
0
0
0
0
0
0
-
K3  
NA  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
I
IO  
IO  
IO  
-
W2  
NA  
I
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
-
AC16  
AD18  
L19  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
GND  
PWR  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
vdds  
vss  
AC19  
AD19  
L20  
vss  
vdds  
vdds  
P23  
vdds_x  
AE19  
cap_vddu_array  
vdd_core  
AC21, D15, NA  
G11, G18,  
H20, M7,  
M17, R20,  
T7, Y8, Y12  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D13, G9,  
G12, H7,  
K11, L9, M9,  
M10, N7,  
N8, P10,  
U7, U11,  
U13, V7,  
V11, W9,  
Y9, Y11  
NA  
vdd_mpu_iva  
0
PWR  
-
A18, AC7,  
AC15,  
A3, A15, B5, vdds  
F2, F21,  
0
PWR  
-
-
-
-
-
-
-
-
AC18,  
L20, W21  
AC24,  
AD20,  
AE10, C11,  
D9, E24,  
G4, J15,  
J18, L7,  
L24, M4, T4,  
T24, W24,  
Y4, AB24  
U12  
K13  
U14  
W14  
N23  
V25  
V24  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
vdds_sram  
0
0
0
0
0
0
0
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vdda_dplls_dll  
vdda_dpll_per  
vdda_wkup_bg_bb  
vdds_mmc1  
vdda_dac  
vssa_dac  
60  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
A6, A8, A13, A7, A13,  
vss  
0
GND  
-
-
-
-
-
-
-
-
AB5, AB22, B14, C1, F1,  
AC10,  
AD14,  
F20, H2,  
H20, L21,  
AD25, AE7, M2, P20,  
B2, B25,  
C12, D7,  
D10, D12,  
D14, D18,  
D20, E22,  
G1, G8,  
R2, W20 Y6,  
Y11, AA7,  
AA16  
G10, G20,  
G23, H4,  
K1, K15,  
K25, L10,  
L17, L23,  
N4, N10,  
N17, R1,  
R4, R17,  
T23, U25,  
W1, W4,  
W23, Y7,  
Y10, Y16,  
Y26  
K14  
NA  
cap_vddu_wkup_log 0  
ic  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A1, L1, T2, A1, J1, N2, Feed-Through  
Y2, AE2,  
AF4, AF5,  
-
T2, W2, Y2, Pins(4)  
AA6, Y7,  
AF8, AF10, Y9, AA10,  
AF12, AF13, AA11,  
AF14, AF15, AA12,  
AF17, AF16, AA13, Y14,  
A20, AF21, AA14, B16,  
AF18, AF24, Y17, AA17,  
AF22, A25, Y19, AA19,  
AE25, AF25, A20, Y20,  
A26, B26,  
K26, U26,  
AA20, A21,  
B21, H21,  
AE26, AF26 P21, Y21,  
AA21  
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TERMINAL DESCRIPTION  
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Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)  
BALL  
BOTTOM  
[1]  
BALL TOP PIN NAME [3]  
[2]  
MODE [4]  
TYPE [5]  
BALL  
RESET  
STATE [6] [7]  
BALL RESET RESET  
REL. STATE REL. MODE  
POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
IO CELL  
[13]  
[8]  
TYPE [12]  
A2, AF1,  
A2, AA1,  
No Connect(2)  
-
-
-
-
-
-
-
-
-
-
B1,D5, K23, AA2,B1, B2,  
A5, A7, A9, B20, Y1  
A10, A11,  
A12, A14,  
A15, A16,  
A17, A19,  
A21, A22,  
AA23,  
AB23, AC9,  
AC12,  
AC13,  
AC14,  
AC17,  
AC20,  
AC22,  
AC23, AD9,  
AD11,  
AD12,  
AD13, AE1,  
AE8, AE11,  
AE12,  
AE13, AF2,  
AF3, AF11,  
B7, B8, B9,  
B10, B11,  
B12, B13,  
B14, B15,  
B16, B17,  
B18, B19,  
B20, B21,  
B22, C7,  
C8, C9,  
C10, C13,  
C14, C15,  
C16, C17  
C18, C19,  
C20, C21,  
C22, D8,  
D11, D16,  
D17, D19,  
D21, D22,  
E23, F4, G7,  
G13, G14,  
G15, G16,  
G17, G19,  
H8, H9,  
H10, H11,  
H12, H13,  
H14, H15,  
H16, H17,  
H18, H19,  
H23, J3, J4,  
J7, J8, J9,  
J10, J11,  
J12, J13,  
J14, J16,  
J17, J19,  
J20, K4, K7,  
K8, K9, K10,  
K12, K16,  
K17, K19,  
L8, M8,  
M23, N18,  
P2, P4, P24,  
R23, R24,  
R25, R26,  
T25, T26,  
U23, V4,  
W12, Y23  
AF23  
A4  
NA  
NA  
sys_xtalgnd  
gpmc_a11  
safe_mode  
0
0
7
0
GND  
O
L
L
7
vdds  
Yes  
8
PU/PD  
LVCMOS  
D6  
NA  
NA  
NA  
cap_vdd_bb_mpu_i  
va  
PWR  
PWR  
PWR  
N9  
cap_vdd_sram_mpu  
_iva  
0
0
K20  
cap_vdd_sram_core  
62  
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(1) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full  
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
(2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior.  
(3) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode.  
For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in  
the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
PD: 30 to 150 kΩ.  
(4) These signals are feed-through balls. For more information, see Table 2-27.  
(5) NA in this table stands for "Not Applicable".  
(6) In the safe_mode_out1, the buffer is configured to drive 1.  
(7) Depending on the sys_clkreq direction the corresponding reset released state value can be:  
–
–
Z if sys_clkreq is used as input  
1 if sys_clkreq is used as output  
For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
(8) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(9) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described as  
follows: Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load  
range of 5 pF to 15 pF.  
(10) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive  
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,  
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module chapter of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application.  
(11) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see  
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and  
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the  
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to  
modify the IO settings if required by the targeted interface application.  
(12) Mux0 if sys_boot6 is pulled down (clock master).  
Table 2-3. Ball Characteristics (CUS Pkg.)(1)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
TYPE [12]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
(mA) [11]  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
D7  
sdrc_d0  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
C5  
C6  
B5  
D9  
D10  
C7  
B7  
B11  
C12  
B12  
D13  
C13  
B14  
A14  
B15  
C9  
E12  
B8  
B9  
C10  
B10  
D12  
E13  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
63  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
TYPE [12]  
(mA) [11]  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
E15  
D15  
C15  
B16  
C16  
D16  
B17  
B18  
C18  
D18  
A4  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
7
0
0
0
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
L
L
L
L
L
L
L
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
L
1
H
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Yes  
NA  
NA  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
(8)  
4
4(8)  
4(8)  
4(8)  
O
O
(8)  
B4  
sdrc_a1  
O
4
D6  
sdrc_a2  
O
4(8)  
4(8)  
4(8)  
4(8)  
B3  
sdrc_a3  
O
B2  
sdrc_a4  
O
C3  
sdrc_a5  
O
(8)  
E3  
sdrc_a6  
O
4
F6  
sdrc_a7  
O
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
E10  
E9  
sdrc_a8  
O
sdrc_a9  
O
E7  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
O
G6  
O
G7  
O
F7  
O
F9  
O
A19  
B19  
A10  
A11  
B20  
O
O
IO  
O
sdrc_nclk  
sdrc_cke0  
safe_mode_out1(9)  
sdrc_cke1  
safe_mode_out1(9)  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
gpmc_a1  
gpio_34  
O
C20  
O
H
1
7
vdds_mem  
NA  
4(8)  
PU/ PD  
LVCMOS  
D19  
C19  
A20  
B6  
O
1
1
1
0
0
0
0
L
L
L
L
L
1
1
1
0
0
0
0
Z
Z
Z
Z
L
0
0
0
0
0
0
0
0
0
0
0
7
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
NA  
4(8)  
4(8)  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
O
NA  
(8)  
O
NA  
4
O
NA  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
4(8)  
8
B13  
A7  
O
NA  
O
NA  
A16  
A5  
O
NA  
IO  
IO  
IO  
IO  
O
Yes  
Yes  
Yes  
Yes  
Yes  
A13  
A8  
A17  
K4  
IO  
safe_mode  
gpmc_a2  
gpio_35  
K3  
K2  
J4  
O
L
L
L
L
L
L
7
7
7
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_a3  
gpio_36  
O
IO  
safe_mode  
gpmc_a4  
gpio_37  
O
IO  
64  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
safe_mode  
gpmc_a5  
gpio_38  
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
J3  
J2  
J1  
H1  
H2  
O
L
L
7
7
7
7
7
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_a6  
gpio_39  
O
H
H
H
H
H
H
H
H
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
IO  
safe_mode  
gpmc_a7  
gpio_40  
O
IO  
safe_mode  
gpmc_a8  
gpio_41  
O
IO  
safe_mode  
gpmc_a9  
sys_ndmareq2  
gpio_42  
O
I
IO  
safe_mode  
gpmc_a10  
sys_ndmareq3  
gpio_43  
G2  
O
I
H
H
7
vdds_mem  
Yes  
8
PU/ PD  
LVCMOS  
IO  
safe_mode  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpio_44  
L2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
M1  
M2  
N2  
M3  
P1  
P2  
R1  
R2  
safe_mode  
gpmc_d9  
gpio_45  
T2  
U1  
R3  
T3  
U2  
V1  
V2  
IO  
IO  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_d10  
gpio_46  
IO  
IO  
safe_mode  
gpmc_d11  
gpio_47  
IO  
IO  
safe_mode  
gpmc_d12  
gpio_48  
IO  
IO  
safe_mode  
gpmc_d13  
gpio_49  
IO  
IO  
safe_mode  
gpmc_d14  
gpio_50  
IO  
IO  
safe_mode  
gpmc_d15  
gpio_51  
IO  
IO  
safe_mode  
gpmc_ncs0  
gpmc_ncs3  
E2  
D2  
O
O
1
1
0
7
vdds_mem  
vdds_mem  
NA  
8
8
NA  
LVCMOS  
LVCMOS  
H
H
Yes  
PU/ PD  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
65  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
sys_ndmareq0  
gpio_54  
1
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
4
7
0
0
0
0
4
7
0
4
7
0
4
7
0
0
1
2
4
7
0
4
5
7
0
4
5
I
IO  
safe_mode  
gpmc_ncs4  
sys_ndmareq1  
mcbsp4_ clkx  
gpt_9_pwm_evt  
gpio_55  
F4  
O
I
H
H
7
7
7
7
0
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
IO  
safe_mode  
gpmc_ncs5  
sys_ndmareq2  
mcbsp4_dr  
gpt_10_pwm_evt  
gpio_56  
G5  
O
I
H
H
H
L
H
H
H
0
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
I
IO  
IO  
safe_mode  
gpmc_ncs6  
sys_ndmareq3  
mcbsp4_dx  
gpt_11_pwm_evt  
gpio_57  
F3  
O
I
IO  
IO  
IO  
safe_mode  
gpmc_ncs7  
gpmc_io_dir  
mcbsp4_fsx  
gpt_8_pwm_evt  
gpio_58  
G4  
O
O
IO  
IO  
IO  
safe_mode  
gpmc_clk  
W2  
O
gpio_59  
IO  
safe_mode  
gpmc_nadv_ale  
gpmc_noe  
gpmc_nwe  
gpmc_nbe0_cle  
gpio_60  
F1  
F2  
G3  
K5  
O
O
O
O
IO  
0
1
1
L
0
1
1
0
0
0
0
0
vdds_mem  
vdds_mem  
vdds_mem  
vdds_mem  
NA  
NA  
NA  
Yes  
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
gpmc_nbe1  
gpio_61  
L1  
E1  
O
L
L
L
0
7
0
vdds_mem  
vdds_mem  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
gpmc_nwp  
gpio_62  
O
IO  
safe_mode  
gpmc_wait0  
gpmc_wait3  
sys_ndmareq1  
uart4_rx  
C1  
C2  
I
H
H
H
H
0
7
vdds_mem  
vdds_mem  
Yes  
Yes  
NA  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
I
I
I
gpio_65  
IO  
safe_mode  
dss_pclk  
G22  
E22  
O
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
gpio_66  
IO  
O
hw_dbg12  
safe_mode  
dss_hsync  
gpio_67  
O
IO  
O
hw_dbg13  
66  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
safe_mode  
dss_vsync  
gpio_68  
7
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
2
4
7
0
2
4
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
4
7
0
4
7
F22  
O
H
L
L
H
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
dss_acbias  
gpio_69  
J21  
O
L
L
PU/ PD  
PU/ PD  
IO  
safe_mode  
dss_data0  
uart1_cts  
gpio_70  
AC19  
IO  
I
8
NA  
8
IO  
safe_mode  
dss_data1  
uart1_rts  
AB19  
IO  
O
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
gpio_71  
IO  
safe_mode  
dss_data2  
gpio_72  
AD20  
AC20  
AD21  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data3  
gpio_73  
IO  
IO  
safe_mode  
dss_data4  
uart3_rx_ irrx  
gpio_74  
IO  
I
IO  
safe_mode  
dss_data5  
uart3_tx_ irtx  
gpio_75  
AC21  
D24  
IO  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
NA  
8
IO  
safe_mode  
dss_data6  
uart1_tx  
IO  
O
8
8
8
8
gpio_76  
IO  
O
hw_dbg14  
safe_mode  
dss_data7  
uart1_rx  
E23  
E24  
F23  
IO  
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_77  
IO  
O
hw_dbg15  
safe_mode  
dss_data8  
uart3_rx_irrx  
gpio_78  
IO  
I
IO  
O
hw_dbg16  
safe_mode  
dss_data9  
uart3_tx_irtx  
gpio_79  
IO  
O
IO  
O
hw_dbg17  
safe_mode  
dss_data10  
gpio_80  
AC22  
AC23  
IO  
IO  
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
dss_data11  
gpio_81  
IO  
IO  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
67  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
AB22  
Y22  
W22  
V22  
J22  
dss_data12  
gpio_82  
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
0
2
3
4
7
0
3
4
7
0
0
0
0
0
0
4
5
IO  
IO  
L
L
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
8
8
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data13  
gpio_83  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
safe_mode  
dss_data14  
gpio_84  
IO  
IO  
safe_mode  
dss_data15  
gpio_85  
IO  
IO  
safe_mode  
dss_data16  
gpio_86  
IO  
IO  
safe_mode  
dss_data17  
gpio_87  
G23  
G24  
IO  
IO  
safe_mode  
dss_data18  
mcspi3_clk  
dss_data0  
gpio_88  
IO  
IO  
IO  
IO  
safe_mode  
dss_data19  
mcspi3_simo  
dss_data1  
gpio_89  
H23  
D23  
K22  
V21  
W21  
IO  
IO  
IO  
IO  
L
H
L
L
L
L
H
L
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
8
8
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
dss_data20  
mcspi3_somi  
dss_data2  
gpio_90  
O
IO  
IO  
IO  
safe_mode  
dss_data21  
mcspi3_cs0  
dss_data3  
gpio_91  
O
IO  
IO  
IO  
safe_mode  
dss_data22  
mcspi3_cs1  
dss_data4  
gpio_92  
O
O
IO  
IO  
safe_mode  
dss_data23  
dss_data5  
gpio_93  
O
IO  
IO  
safe_mode  
cvideo2_out  
cvideo1_out  
cvideo1_vfb  
cvideo2_vfb  
cvideo1_rset  
cam_hs  
AA23  
AB24  
AB23  
Y23  
AO  
AO  
AO  
AO  
AIO  
IO  
0
0
0
0
0
L
0
0
0
0
0
0
7
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdda_dac  
vdds  
NA  
NA  
NA  
NA  
No  
NA(6)  
NA(6)  
NA(7)  
NA(7)  
NA  
NA  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
10-bit DAC  
LVCMOS  
0
NA  
NA  
NA  
NA  
L
NA  
NA  
Y24  
NA  
A22  
Yes  
4
PU/ PD  
gpio_94  
IO  
hw_dbg0  
O
68  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
safe_mode  
cam_vs  
7
0
4
5
7
0
4
7
0
4
5
7
0
2
5
4
7
0
4
7
0
4
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
5
7
E18  
IO  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
gpio_95  
hw_dbg1  
safe_mode  
cam_ xclka  
gpio_96  
B22  
J19  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
cam_pclk  
gpio_97  
I
IO  
O
hw_dbg2  
safe_mode  
cam_fld  
H24  
IO  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
cam_global_reset  
hw_dbg3  
gpio_98  
IO  
safe_mode  
cam_d0  
AB18  
AC18  
G19  
I
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
NA  
NA  
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_99  
safe_mode  
cam_d1  
I
I
gpio_100  
safe_mode  
cam_d2  
I
gpio_101  
hw_dbg4  
safe_mode  
cam_d3  
IO  
O
F19  
G20  
B21  
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
8
8
8
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_102  
hw_dbg5  
safe_mode  
cam_d4  
IO  
O
I
gpio_103  
hw_dbg6  
safe_mode  
cam_d5  
IO  
O
I
gpio_104  
hw_dbg7  
safe_mode  
cam_d6  
IO  
O
L24  
K24  
J23  
K23  
F21  
I
I
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
NA  
NA  
NA  
NA  
8
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_105  
safe_mode  
cam_d7  
I
I
gpio_106  
safe_mode  
cam_d8  
I
I
gpio_107  
safe_mode  
cam_d9  
I
I
gpio_108  
safe_mode  
cam_d10  
gpio_109  
hw_dbg8  
safe_mode  
I
IO  
O
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
69  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
G21  
cam_d11  
0
4
5
7
0
4
7
0
2
4
5
7
0
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
4
7
4
7
0
1
4
7
0
I
L
L
7
vdds  
Yes  
8
PU/ PD  
LVCMOS  
gpio_110  
IO  
O
hw_dbg9  
safe_mode  
cam_ xclkb  
gpio_111  
C22  
F18  
O
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
cam_wen  
I
cam_ shutter  
gpio_167  
O
IO  
O
hw_dbg10  
safe_mode  
cam_ strobe  
gpio_126  
J20  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
O
hw_dbg11  
safe_mode  
mcbsp2_fsx  
gpio_116  
V20  
T21  
V19  
R20  
M23  
L23  
IO  
IO  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
1
1
1
1
1
1
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp2_ clkx  
gpio_117  
IO  
IO  
PU/ PD  
safe_mode  
mcbsp2_dr  
gpio_118  
I
PU/ PD  
IO  
safe_mode  
mcbsp2_dx  
gpio_119  
IO  
IO  
PU/ PD  
safe_mode  
mmc1_clk  
gpio_120 (5)  
safe_mode  
mmc1_cmd  
gpio_121 (5)  
safe_mode  
mmc1_dat0  
gpio_122 (5)  
safe_mode  
mmc1_dat1  
gpio_123(5)  
safe_mode  
mmc1_dat2  
gpio_124(5)  
safe_mode  
mmc1_dat3  
gpio_125(5)  
safe_mode  
gpio_126(5)  
safe_mode  
gpio_129(5)  
safe_mode  
mmc2_clk  
mcspi3_clk  
gpio_130  
IO  
IO  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
vdds_mmc1 Yes  
PU/ PD (4)  
PU/ PD(4)  
PU/ PD(4)  
PU/ PD(4)  
PU/ PD(4)  
PU/ PD(4)  
O
IO  
M22  
M21  
M20  
N23  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
N22  
P24  
Y1  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds_x  
vdds_x  
vdds  
Yes  
Yes  
Yes  
1
1
4
PU/ PD(4)  
PU/ PD (4)  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
IO  
IO  
safe_mode  
mmc2_ cmd  
AB5  
O
H
H
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
70  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
mcspi3_ simo  
gpio_131  
1
4
7
0
1
4
7
0
4
7
0
1
4
7
0
1
4
7
0
1
3
4
7
0
1
2
3
4
6
7
0
1
2
3
4
7
0
1
3
4
6
7
0
1
4
7
0
1
4
7
0
1
4
7
0
IO  
IO  
safe_mode  
mmc2_ dat0  
mcspi3_ somi  
gpio_132  
AB3  
IO  
IO  
IO  
H
H
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
safe_mode  
mmc2_ dat1  
gpio_133  
Y3  
IO  
IO  
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_ dat2  
mcspi3_cs1  
gpio_134  
W3  
IO  
O
IO  
safe_mode  
mmc2_ dat3  
mcspi3_cs0  
gpio_135  
V3  
IO  
IO  
IO  
H
L
H
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mmc2_ dat4  
mmc2_dir_dat0  
mmc3_dat0  
gpio_136  
AB2  
IO  
O
IO  
IO  
safe_mode  
mmc2_ dat5  
mmc2_dir_dat1  
cam_global_reset  
mmc3_dat1  
gpio_137  
AA2  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
IO  
IO  
IO  
mm3_rxdp  
safe_mode  
mmc2_dat6  
mmc2_dir_cmd  
cam_shutter  
mmc3_dat2  
gpio_138  
Y2  
IO  
O
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
O
IO  
IO  
safe_mode  
mmc2_dat7  
mmc2_clkin  
mmc3_dat3  
gpio_139  
AA1  
IO  
I
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
IO  
IO  
IO  
mm3_rxdm  
safe_mode  
mcbsp3_dx  
uart2_cts  
V6  
V5  
W4  
V4  
IO  
I
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_140  
IO  
safe_mode  
mcbsp3_dr  
uart2_rts  
I
O
IO  
gpio_141  
safe_mode  
mcbsp3_ clkx  
uart2_tx  
IO  
O
gpio_142  
IO  
safe_mode  
mcbsp3_fsx  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
71  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
uart2_rx  
1
4
7
0
4
7
0
4
7
0
4
7
0
2
3
4
7
0
1
4
7
0
2
4
7
0
1
2
4
7
0
1
2
4
7
0
2
4
5
7
0
1
2
4
7
0
2
4
7
0
4
7
0
4
7
I
gpio_143  
IO  
safe_mode  
uart1_tx  
W7  
W6  
AC2  
V7  
O
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
gpio_148  
IO  
safe_mode  
uart1_rts  
O
gpio_149  
IO  
safe_mode  
uart1_cts  
I
gpio_150  
IO  
safe_mode  
uart1_rx  
I
mcbsp1_ clkr  
mcspi4_clk  
gpio_151  
IO  
IO  
IO  
safe_mode  
mcbsp1_ clkr  
mcspi4_clk  
gpio_156  
W19  
AB20  
W18  
IO  
IO  
IO  
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcbsp1_fsr  
cam_global_reset  
gpio_157  
IO  
IO  
IO  
safe_mode  
mcbsp1_dx  
mcspi4_ simo  
mcbsp3_dx  
gpio_158  
IO  
IO  
IO  
IO  
safe_mode  
mcbsp1_dr  
mcspi4_ somi  
mcbsp3_dr  
gpio_159  
Y18  
I
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
IO  
safe_mode  
mcbsp_clks  
cam_ shutter  
gpio_160  
AA18  
AA19  
V18  
I
O
IO  
I
uart1_cts  
safe_mode  
mcbsp1_fsx  
mcspi4_cs0  
mcbsp3_fsx  
gpio_161  
IO  
IO  
IO  
IO  
safe_mode  
mcbsp1_ clkx  
mcbsp3_ clkx  
gpio_162  
IO  
IO  
IO  
safe_mode  
uart3_cts_ rctx  
gpio_163  
A23  
B23  
IO  
IO  
H
H
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
uart3_rts_ sd  
gpio_164  
O
IO  
safe_mode  
72  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
B24  
C23  
R21  
R23  
P23  
R22  
T24  
uart3_rx_ irrx  
gpio_165  
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
2
4
5
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
0
4
7
I
H
H
7
7
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
8
4
4
4
4
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
safe_mode  
uart3_tx_ irtx  
gpio_166  
O
H
L
H
L
L
L
H
L
H
L
L
L
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
IO  
safe_mode  
hsusb0_clk  
gpio_120  
I
IO  
safe_mode  
hsusb0_stp  
gpio_121  
O
IO  
safe_mode  
hsusb0_dir  
gpio_122  
I
IO  
safe_mode  
hsusb0_nxt  
gpio_124  
I
IO  
safe_mode  
hsusb0_ data0  
uart3_tx_ irtx  
gpio_125  
IO  
O
IO  
O
uart2_tx  
safe_mode  
hsusb0_ data1  
uart3_rx_ irrx  
gpio_130  
T23  
U24  
U23  
IO  
I
L
L
L
L
L
L
7
7
7
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
I
uart2_rx  
safe_mode  
hsusb0_ data2  
uart3_rts_ sd  
gpio_131  
IO  
O
IO  
O
uart2_rts  
safe_mode  
hsusb0_ data3  
uart3_cts_ rctx  
gpio_169  
IO  
IO  
IO  
I
uart2_cts  
safe_mode  
hsusb0_ data4  
gpio_188  
W24  
V23  
W23  
T22  
IO  
IO  
L
L
L
L
L
L
L
L
7
7
7
7
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
hsusb0_ data5  
gpio_189  
IO  
IO  
safe_mode  
hsusb0_ data6  
gpio_190  
IO  
IO  
safe_mode  
hsusb0_ data7  
gpio_191  
IO  
IO  
safe_mode  
i2c1_scl  
K20  
OD  
IOD  
OD  
IO  
H
H
H
H
H
H
0
0
7
vdds  
vdds  
vdds  
NA  
3
3
3
4
PU/ PD(10)(11) Open Drain  
PU/ PD(10)(11) Open Drain  
PU/ PD(10)(12) Open Drain  
K21  
i2c1_sda  
Yes  
Yes  
AC15  
i2c2_scl  
gpio_168  
safe_mode  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
73  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
AC14  
AC13  
AC12  
Y16  
i2c2_sda  
0
4
7
0
4
7
0
4
7
0
1
7
0
1
7
0
1
2
3
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
3
4
5
7
0
3
4
7
0
1
3
4
7
0
1
3
4
IOD  
IO  
H
H
7
7
7
0
0
7
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
3
4
PU/ PD(10)(12) Open Drain  
gpio_183  
safe_mode  
i2c3_scl  
OD  
IO  
H
H
H
H
H
H
H
H
H
H
3
4
PU/ PD(10)(12) Open Drain  
PU/ PD(10)(12) Open Drain  
PU/ PD(10)(11) Open Drain  
PU/ PD(10)(11) Open Drain  
gpio_184  
safe_mode  
i2c3_sda  
IOD  
IO  
3
4
gpio_185  
safe_mode  
i2c4_scl  
OD  
O
3
4
sys_nvmode1  
safe_mode  
i2c4_sda  
Y15  
IOD  
O
3
4
sys_nvmode2  
safe_mode  
hdq_sio  
A24  
IOD  
I
4
PU/ PD  
LVCMOS  
sys_altclk  
i2c2_sccbe  
i2c3_sccbe  
gpio_170  
OD  
OD  
IO  
safe_mode  
mcspi1_clk  
mmc2_dat4  
gpio_171  
T5  
R4  
T4  
T6  
R5  
IO  
IO  
IO  
L
L
7
7
7
7
7
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
safe_mode  
mcspi1_ simo  
mmc2_dat5  
gpio_172  
IO  
IO  
IO  
L
L
safe_mode  
mcspi1_ somi  
mmc2_dat6  
gpio_173  
IO  
IO  
IO  
L
L
safe_mode  
mcspi1_cs0  
mmc2_dat7  
gpio_174  
IO  
IO  
IO  
H
H
H
H
safe_mode  
mcspi1_cs3  
hsusb2_ data2  
gpio_177  
O
IO  
IO  
IO  
mm2_txdat  
safe_mode  
mcspi2_clk  
hsusb2_ data7  
gpio_178  
N5  
N4  
IO  
IO  
IO  
L
L
L
L
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
mcspi2_ simo  
gpt_9_pwm_evt  
hsusb2_ data4  
gpio_179  
IO  
IO  
IO  
IO  
safe_mode  
mcspi2_ somi  
gpt_10_pwm_evt  
hsusb2_ data5  
gpio_180  
N3  
IO  
IO  
IO  
IO  
L
L
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
74  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
safe_mode  
mcspi2_cs0  
gpt_11_pwm_evt  
hsusb2_ data6  
gpio_181  
7
0
1
3
4
7
0
1
3
4
5
7
0
0
0
0
4
7
0
4
7
0
0
4
7
0
3
4
7
0
3
4
7
0
4
7
0
3
4
7
0
1
3
4
7
0
1
3
4
7
0
3
4
7
0
M5  
M4  
IO  
IO  
IO  
IO  
H
H
7
7
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
safe_mode  
mcspi2_cs1  
gpt_8_pwm_evt  
hsusb2_ data3  
gpio_182  
O
L
L
PU/ PD  
LVCMOS  
IO  
IO  
IO  
IO  
mm2_txen_n  
safe_mode  
sys_32k  
AA16  
AD15  
AD14  
Y13  
I
Z
Z
Z
0
Z
0
0
0
0
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
NA  
NA  
NA  
NA  
4
PU/ PD  
No  
LVCMOS  
Analog  
sys_xtalin  
sys_xtalout  
sys_clkreq  
gpio_1  
AI  
AO  
IO  
IO  
Z
0
NA  
Analog  
see (3)  
Yes  
PU/ PD  
LVCMOS  
safe_mode  
sys_nirq  
W16  
I
H
H
7
vdds  
Yes  
4
PU/ PD  
LVCMOS  
gpio_0  
IO  
safe_mode  
sys_nrespwron  
sys_nreswarm  
gpio_30  
AA10  
Y10  
I
Z
0
Z
1
0
0
vdds  
vdds  
Yes  
Yes  
NA  
4
No  
LVCMOS  
LVCMOS  
IOD  
IO  
PU/ PD  
safe_mode  
sys_boot0  
dss_data18  
gpio_2  
AB12  
AC16  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
IO  
safe_mode  
sys_boot1  
dss_data19  
gpio_3  
I
IO  
IO  
safe_mode  
sys_boot2  
gpio_4  
AD17  
AD18  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
IO  
safe_mode  
sys_boot3  
dss_data20  
gpio_5  
I
O
IO  
safe_mode  
sys_boot4  
mmc2_dir_dat2  
dss_data21  
gpio_6  
AC17  
AB16  
I
Z
Z
Z
Z
0
0
vdds  
vdds  
Yes  
Yes  
8
8
PU/ PD  
LVCMOS  
LVCMOS  
O
O
IO  
safe_mode  
sys_boot5  
mmc2_dir_dat3  
dss_data22  
gpio_7  
I
PU/ PD  
O
O
IO  
safe_mode  
sys_boot6  
dss_data23  
gpio_8  
AA15  
AD23  
I
Z
0
Z
L
0
7
vdds  
vdds  
Yes  
Yes  
8
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
O
IO  
safe_mode  
sys_off_ mode  
O
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
75  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
PU/ PD  
PU/ PD  
TYPE [12]  
gpio_9  
4
7
0
4
7
0
4
7
0
0
0
0
0
0
0
4
7
0
4
7
0
1
2
3
4
5
7
0
2
3
4
7
0
1
2
3
4
5
7
0
1
3
4
5
7
0
1
3
4
5
7
0
1
2
3
IO  
safe_mode  
sys_clkout1  
gpio_10  
Y7  
O
L
L
L
L
7(13)  
vdds  
vdds  
Yes  
Yes  
4
4
LVCMOS  
LVCMOS  
IO  
safe_mode  
sys_clkout2  
gpio_186  
safe_mode  
jtag_ntrst  
jtag_tck  
AA6  
O
7
IO  
AB7  
AB6  
AA7  
AA9  
AB10  
AB9  
AC24  
I
L
L
0
0
0
0
0
0
0
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
NA  
NA  
NA  
4
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
I
L
L
jtag_rtck  
O
IO  
I
L
0
jtag_tms_tmsc  
jtag_tdi  
H
H
L
H
H
Z
H
Yes  
Yes  
NA  
4
NA  
4
jtag_tdo  
O
IO  
IO  
jtag_emu0  
gpio_11  
H
Yes  
4
safe_mode  
jtag_emu1  
gpio_31  
AD24  
AC1  
IO  
IO  
H
H
H
H
0
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
safe_mode  
etk_clk  
O
mcbsp5_ clkx  
mmc3_clk  
hsusb1_stp  
gpio_12  
IO  
IO  
O
IO  
IO  
O
mm1_rxdp  
hw_dbg0  
AD3  
AD6  
etk_ctl  
O
H
H
H
H
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_cmd  
hsusb1_clk  
gpio_13  
O
O
IO  
O
hw_dbg1  
etk_d0  
O
PU/ PD  
mcspi3_ simo  
mmc3_dat4  
hsusb1_ data0  
gpio_14  
IO  
IO  
IO  
IO  
IO  
O
mm1_rxrcv  
hw_dbg2  
AC6  
AC7  
AD8  
etk_d1  
O
H
H
H
H
H
H
4
4
4
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
4
4
4
PU/ PD  
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
mcspi3_ somi  
hsusb1_ data1  
gpio_15  
IO  
IO  
IO  
IO  
O
mm1_txse0  
hw_dbg3  
etk_d2  
O
mcspi3_cs0  
hsusb1_ data2  
gpio_16  
IO  
IO  
IO  
IO  
O
mm1_txdat  
hw_dbg4  
etk_d3  
O
mcspi3_clk  
mmc3_dat3  
hsusb1_ data7  
IO  
IO  
IO  
76  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
gpio_17  
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
5
7
0
2
3
4
7
0
2
3
4
5
7
0
2
3
4
7
0
3
4
5
7
0
3
4
7
0
3
4
IO  
O
O
I
hw_dbg5  
etk_d4  
AC5  
AD2  
AC8  
AD9  
L
L
4
4
4
4
vdds  
vdds  
vdds  
vdds  
Yes  
Yes  
Yes  
Yes  
4
4
4
4
PU/ PD  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
mcbsp5_dr  
mmc3_dat0  
hsusb1_ data4  
gpio_18  
IO  
IO  
IO  
O
O
IO  
IO  
IO  
IO  
O
O
O
IO  
IO  
IO  
O
O
O
IO  
IO  
IO  
IO  
O
O
IO  
I
hw_dbg6  
etk_d5  
L
L
L
L
L
L
PU/ PD  
PU/ PD  
PU/ PD  
mcbsp5_fsx  
mmc3_dat1  
hsusb1_ data5  
gpio_19  
hw_dbg7  
etk_d6  
mcbsp5_dx  
mmc3_dat2  
hsusb1_ data6  
gpio_20  
hw_dbg8  
etk_d7  
mcspi3_cs1  
mmc3_dat7  
hsusb1_ data3  
gpio_21  
mm1_txen_n  
hw_dbg9  
etk_d8  
AC4  
AD5  
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
mmc3_dat6  
hsusb1_dir  
gpio_22  
IO  
O
O
IO  
I
hw_dbg10  
etk_d9  
PU/ PD  
mmc3_dat5  
hsusb1_nxt  
gpio_23  
IO  
IO  
O
O
I
mm1_rxdm  
hw_dbg11  
etk_d10  
AC3  
AC9  
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
uart1_rx  
hsusb2_clk  
gpio_24  
O
IO  
O
O
O
IO  
IO  
O
O
I
hw_dbg12  
etk_d11  
PU/ PD  
hsusb2_stp  
gpio_25  
mm2_rxdp  
hw_dbg13  
etk_d12  
AC10  
AD11  
L
L
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_dir  
gpio_26  
IO  
O
O
I
hw_dbg14  
etk_d13  
hsusb2_nxt  
gpio_27  
IO  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
77  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
PULLUP  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
BOTTOM [1]  
STATE [6]  
REL. STATE MODE [8]  
[7]  
STRENGTH /DOWN  
(mA) [11]  
TYPE [12]  
mm2_rxdm  
hw_dbg15  
etk_d14  
5
7
0
3
4
5
7
0
3
4
5
7
0
IO  
O
AC11  
AD12  
O
L
L
4
4
vdds  
vdds  
Yes  
Yes  
4
4
PU/ PD  
LVCMOS  
LVCMOS  
hsusb2_ data0  
gpio_28  
IO  
IO  
IO  
O
mm2_rxrcv  
hw_dbg16  
etk_d15  
O
L
L
PU/ PD  
hsusb2_ data1  
gpio_29  
IO  
IO  
IO  
O
mm2_txse0  
hw_dbg17  
vdds_mem  
E16, F15,  
F16, G15,  
G16, H15, J6,  
J7, J8, K6,  
K7, K8  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F12, F13,  
G12, G13,  
H12, H13,  
J17, J18,  
K17, K18,  
K19, L14,  
L15, M14,  
M15, R17,  
R18, R19,  
T17, T18,  
T19, T20  
vdd_core  
0
PWR  
F10, G9,  
vdd_mpu_iva  
0
PWR  
-
-
-
-
-
-
-
-
G10, H9,  
H10, J9, J10,  
L11, L12, M6,  
M7, M8, M12,  
N6, N7, N8,  
R6, R7, R8,  
T7, T8, U12,  
U13, V12,  
V13, W12,  
W13  
H8  
vdds_x  
vdds  
0
0
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M17, M18,  
M19, N17,  
N18, N19,  
U10, V9, V10,  
W9, W10, Y9  
N24  
Y12  
vdds_mmc1  
0
0
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
cap_vddu_  
wkup_logic  
U8  
cap_vdd_sram_mpu_ 0  
iva  
PWR  
-
-
-
-
-
-
-
-
H17  
cap_vdd_sram_core  
vdda_dplls_dll  
0
0
0
0
0
0
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G18  
U17  
vdda_dpll_per  
AA12  
AA13  
N21  
vdds_sram  
vdda_wkup_bg_bb  
cap_vdd_bb_mpu_iv  
a
N20  
cap_vddu_array  
vssa_dac  
0
0
0
PWR  
GND  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AB15  
AB13  
vdda_dac  
78  
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SPRS685–AUGUST 2010  
Table 2-3. Ball Characteristics (CUS Pkg.)(1) (continued)  
BALL  
BOTTOM [1]  
BALL TOP [2]  
PIN NAME  
[3]  
MODE [4]  
TYPE [5]  
BALL RESET BALL RESET RESET REL. POWER [9] HYS [10]  
BUFFER  
STRENGTH /DOWN  
(mA) [11]  
PULLUP  
STATE [6]  
REL. STATE MODE [8]  
[7]  
TYPE [12]  
H11, H14,  
H16, J11,  
J12, J13, J14,  
J15, J16,  
vss  
0
GND  
-
-
-
-
-
-
-
-
K10, K11,  
K14, K15, L8,  
L10, L13,  
L17, M9,  
M10, M11,  
M13, M16,  
N9, N10,  
N11, N12,  
N13, N14,  
N15, N16,  
P8, P10, P11,  
P12, P13,  
P14, P15,  
P17, R10,  
R11, R14,  
R15, T9, T10,  
T11, T12,  
T13, T14,  
T15, T16, U9,  
U11, U14,  
U15, U16,  
V15, V16  
AD1, A1, A2, No Connect(2)  
B1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W15  
sys_xtalgnd  
0
GND  
(1) NA in this table stands for "Not Applicable".  
(2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior.  
(3) Depending on the sys_clkreq direction the corresponding reset released state value can be:  
–
–
Z if sys_clkreq is used as input  
1 if sys_clkreq is used as output  
For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
(4) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode. For a full description of the pull-up drive strength  
programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in the System Control Module chapter of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). PD: 30 to 150 kΩ.  
(5) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(6) The drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications.  
(7) In buffer mode, the drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications. In bypass  
mode, the drive strength is 0.47 mA.  
(8) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full  
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
(9) In the safe_mode_out1, the buffer is configured to drive 1.  
(10) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described below:  
Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load range  
of 5 pF to 15 pF.  
(11) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive  
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,  
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module / SCM Programming Model / Feature Settings section  
and the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4) to modify the IO settings if required by the targeted interface application.  
(12) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see  
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and  
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the  
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to  
modify the IO settings if required by the targeted interface application.  
(13) Mux0 if sys_boot6 is pulled down (clock master).  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
79  
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2.4 Multiplexing Characteristics  
provides a description of the multiplexing on the CBP, CBC, and CUS packages, respectively.  
Note: The following does not take into account subsystem pin multiplexing options. Subsystem pin  
multiplexing options are described in Section 2.5, Signal Description. For more information, see the  
System Control Module / System Control Module Functional Description / Pad Functional Multiplexing and  
Configuration section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Table 2-4. Multiplexing Characteristics  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
Top  
Bottom  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
J2  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
D1  
D7  
sdrc_d0  
J1  
G1  
C5  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
sdrc_a1  
sdrc_a2  
sdrc_a3  
sdrc_a4  
sdrc_a5  
sdrc_a6  
sdrc_a7  
sdrc_a8  
sdrc_a9  
G2  
G1  
F2  
F1  
D2  
D1  
G2  
C6  
E1  
B5  
D2  
D9  
E2  
D10  
C7  
B3  
B4  
B7  
B13  
A10  
B11  
A11  
B12  
A16  
A17  
B17  
B18  
B7  
B11  
C12  
B12  
D13  
C13  
B14  
A14  
B15  
C9  
A13  
B14  
A14  
B16  
A16  
B19  
A19  
B3  
A3  
A5  
E12  
B8  
B5  
B6  
A5  
A6  
B9  
B8  
A8  
C10  
B10  
D12  
E13  
E15  
D15  
C15  
B16  
C16  
D16  
B17  
B18  
C18  
D18  
A4  
A8  
B9  
B9  
A9  
A9  
B10  
C21  
D20  
B19  
C20  
D21  
E20  
E21  
G21  
B21  
A21  
D22  
D23  
E22  
E23  
G22  
G23  
AB21  
AC21  
N22  
N23  
P22  
P23  
R22  
R23  
T22  
AA18  
V20  
G20  
K20  
J20  
B4  
D6  
J21  
B3  
U21  
R20  
M21  
M20  
N20  
K21  
B2  
C3  
E3  
T23  
F6  
U22  
U23  
E10  
E9  
80  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
Top  
Bottom  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
V22  
V23  
W22  
W23  
Y22  
M22  
M23  
A11  
B11  
J22  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Y16  
E7  
sdrc_a10  
N21  
R21  
G6  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_clk  
G7  
AA15  
Y12  
T21  
T20  
A12  
B13  
Y15  
F7  
F9  
A19  
B19  
A10  
A11  
B20  
sdrc_nclk  
sdrc_cke0  
safe_mo  
de_out1  
NA  
J23  
NA  
Y13  
C20  
sdrc_cke1  
safe_mo  
de_out1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
N4  
L23  
L22  
K23  
C1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
J2  
V21  
U20  
Y18  
H1  
D19  
C19  
A20  
B6  
sdrc_nras  
sdrc_ncas  
sdrc_nwe  
sdrc_dm0  
sdrc_dm1  
sdrc_dm2  
sdrc_dm3  
sdrc_dqs0  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
gpmc_a1  
A17  
A6  
A14  
A4  
B13  
A7  
A20  
C2  
A18  
C2  
A16  
A5  
B17  
B6  
B15  
B8  
A13  
A8  
B20  
A19  
NA  
A17  
K4  
AC15  
AB15  
AC16  
AB16  
AC17  
AB17  
AC18  
AB18  
AC19  
AB19  
AC20  
gpio_34  
safe_mo  
de  
M4  
L4  
H1  
H2  
G2  
F1  
F2  
E1  
E2  
D1  
D2  
A4  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
K3  
K2  
J4  
gpmc_a2  
gpmc_a3  
gpmc_a4  
gpmc_a5  
gpmc_a6  
gpmc_a7  
gpmc_a8  
gpmc_a9  
gpmc_a10  
gpmc_a11  
gpio_35  
gpio_36  
gpio_37  
gpio_38  
gpio_39  
gpio_40  
gpio_41  
gpio_42  
gpio_43  
safe_mo  
de  
safe_mo  
de  
K4  
T3  
R3  
N3  
M3  
L3  
safe_mo  
de  
J3  
safe_mo  
de  
J2  
safe_mo  
de  
J1  
safe_mo  
de  
H1  
H2  
G2  
NA  
safe_mo  
de  
sys_ndmareq  
2
safe_mo  
de  
K3  
NA  
sys_ndmareq  
3
safe_mo  
de  
safe_mo  
de  
K1  
L1  
M2  
M1  
N2  
N1  
R2  
R1  
T2  
AA2  
AA1  
AC2  
AC1  
AE5  
AD6  
AD5  
AC5  
V1  
U2  
U1  
V2  
L2  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
M1  
M2  
N2  
M3  
P1  
P2  
R1  
R2  
L2  
P2  
T1  
V1  
V2  
W2  
H2  
V1  
AA3  
AA4  
Y3  
T1  
Y4  
AB3  
R1  
gpio_44  
gpio_45  
gpio_46  
safe_mo  
de  
K2  
P1  
AC3  
AB4  
Y1  
T1  
T1  
N1  
T2  
U1  
gpmc_d9  
safe_mo  
de  
gpmc_d10  
safe_mo  
de  
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TERMINAL DESCRIPTION  
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Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
Top  
Bottom  
Top  
R1  
R2  
T2  
AC4  
AB6  
AC6  
AB7  
AC7  
U2  
U1  
P1  
L2  
P2  
R3  
T3  
U2  
V1  
V2  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
gpio_47  
safe_mo  
de  
P1  
M1  
J2  
gpio_48  
gpio_49  
gpio_50  
gpio_51  
safe_mo  
de  
safe_mo  
de  
W1  
Y1  
safe_mo  
de  
M2  
K2  
safe_mo  
de  
G4  
H3  
Y2  
Y1  
AD8  
AD1  
AA8  
W1  
E2  
gpmc_ncs0  
gpmc_ncs1  
NA  
gpio_52  
gpio_53  
gpio_54  
safe_mo  
de  
V8  
U8  
T8  
R8  
P8  
N8  
T4  
F3  
NA  
NA  
NA  
NA  
NA  
NA  
W2  
W1  
A3  
NA  
NA  
NA  
NA  
NA  
NA  
L1  
NA  
D2  
F4  
gpmc_ncs2  
gpmc_ncs3  
gpmc_ncs4  
gpmc_ncs5  
gpmc_ncs6  
gpmc_ncs7  
gpmc_clk  
safe_mo  
de  
B6  
sys_ndmareq  
0
safe_mo  
de  
B4  
sys_ndmareq mcbsp4_clkx  
1
gpt_9_pwm gpio_55  
_evt  
safe_mo  
de  
C4  
B5  
G5  
F3  
sys_ndmareq mcbsp4_dr  
2
gpt_10_pw gpio_56  
m_evt  
safe_mo  
de  
sys_ndmareq mcbsp4_dx  
3
gpt_11_pw gpio_57  
m_evt  
safe_mo  
de  
C5  
N1  
AD10  
G4  
W2  
F1  
gpmc_io_dir mcbsp4_fsx  
gpt_8_pwm gpio_58  
_evt  
safe_mo  
de  
gpio_59  
safe_mo  
de  
AA9  
gpmc_nadv_a  
le  
G2  
F4  
G3  
V2  
V1  
N2  
M1  
K2  
L2  
F2  
G3  
K5  
gpmc_noe  
gpmc_nwe  
K1  
NA  
AC12  
gpmc_nbe0_c  
le  
gpio_60  
gpio_61  
gpio_62  
safe_mo  
de  
U3  
H1  
NA  
J1  
NA  
Y5  
L1  
E1  
gpmc_nbe1  
safe_mo  
de  
AB10  
AC6  
gpmc_nwp  
safe_mo  
de  
M8  
L8  
AB12  
AC10  
AC11  
AC8  
Y10  
Y8  
C1  
NA  
gpmc_wait0  
gpmc_wait1  
gpio_63  
gpio_64  
gpio_65  
gpio_66  
gpio_67  
gpio_68  
gpio_69  
gpio_70  
gpio_71  
gpio_72  
gpio_73  
gpio_74  
gpio_75  
gpio_76  
safe_mo  
de  
K8  
J8  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
B3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
gpmc_wait2  
uart4_tx  
safe_mo  
de  
C6  
C2  
gpmc_wait3 sys_ndmareq uart4_rx(3)  
1
safe_mo  
de  
D28  
G25  
K24  
G22  
E22  
F22  
J21  
dss_pclk  
hw_dbg12  
hw_dbg13  
safe_mo  
de  
D26  
dss_hsync  
dss_vsync  
dss_acbias  
safe_mo  
de  
D27  
M25  
F26  
safe_mo  
de  
E27  
safe_mo  
de  
AG22  
AH22  
AG23  
AH23  
AG24  
AH24  
E26  
AE21  
AE22  
AE23  
AE24  
AD23  
AD24  
G26  
AC19  
AB19  
AD20  
AC20  
AD21  
AC21  
D24  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
uart1_cts  
uart1_rts  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
uart3_rx_irrx  
uart3_tx_irtx  
uart1_tx  
safe_mo  
de  
safe_mo  
de  
hw_dbg14  
safe_mo  
de  
82  
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Product Folder Link(s): DM3730 DM3725  
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SPRS685–AUGUST 2010  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
F28  
Top  
Bottom  
H25  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
E23  
E24  
F23  
dss_data7  
dss_data8  
dss_data9  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
dss_data14  
dss_data15  
dss_data16  
dss_data17  
dss_data18  
dss_data19  
dss_data20  
dss_data21  
dss_data22  
dss_data23  
uart1_rx  
gpio_77  
hw_dbg15  
hw_dbg16  
hw_dbg17  
safe_mo  
de  
F27  
H26  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
uart3_rx_irrx  
uart3_tx_irtx  
gpio_78  
gpio_79  
gpio_80  
gpio_81  
gpio_82  
gpio_83  
gpio_84  
gpio_85  
gpio_86  
gpio_87  
safe_mo  
de  
G26  
J26  
safe_mo  
de  
AD28  
AD27  
AB28  
AB27  
AA28  
AA27  
G25  
AC26  
AD26  
AA25  
Y25  
AC22  
AC23  
AB22  
Y22  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
AA26  
AB26  
L25  
W22  
V22  
safe_mo  
de  
safe_mo  
de  
J22  
safe_mo  
de  
H27  
L26  
G23  
G24  
H23  
D23  
K22  
safe_mo  
de  
H26  
M24  
M26  
F25  
mcspi3_clk  
mcspi3_simo  
mcspi3_somi  
mcspi3_cs0  
mcspi3_cs1  
dss_data0 gpio_88  
dss_data1 gpio_89  
dss_data2 gpio_90  
dss_data3 gpio_91  
dss_data4 gpio_92  
dss_data5 gpio_93  
safe_mo  
de  
H25  
safe_mo  
de  
E28  
safe_mo  
de  
J26  
N24  
safe_mo  
de  
AC27  
AC28  
AC25  
AB25  
V21  
safe_mo  
de  
W21  
safe_mo  
de  
W28  
Y28  
Y27  
W27  
W26  
A24  
NA  
NA  
NA  
NA  
NA  
NA  
V26  
W26  
W25  
U24  
V23  
C23  
NA  
NA  
NA  
NA  
NA  
NA  
AA23  
AB24  
AB23  
Y23  
cvideo2_out  
cvideo1_out  
cvideo1_vfb  
cvideo2_vfb  
cvideo1_rset  
cam_hs  
Y24  
A22  
gpio_94  
hw_dbg0  
hw_dbg1  
safe_mo  
de  
A23  
C25  
C27  
C23  
AG17  
AH17  
B24  
C24  
D24  
A25  
K28  
L28  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
D23  
C25  
C26  
B23  
AE16  
AE15  
A24  
B24  
D24  
C24  
P25  
P26  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
E18  
B22  
J19  
cam_vs  
cam_xclka  
cam_pclk  
cam_fld  
cam_d0  
cam_d1  
cam_d2  
cam_d3  
cam_d4  
cam_d5  
cam_d6  
cam_d7  
gpio_95  
safe_mo  
de  
gpio_96  
safe_mo  
de  
gpio_97  
hw_dbg2  
hw_dbg3  
safe_mo  
de  
H24  
AB18  
AC18  
G19  
F19  
G20  
B21  
L24  
cam_global_res  
et  
gpio_98  
safe_mo  
de  
gpio_99(1)  
gpio_100(1)  
gpio_101  
gpio_102  
gpio_103  
gpio_104  
gpio_105(1)  
gpio_106(1)  
safe_mo  
de  
safe_mo  
de  
hw_dbg4  
hw_dbg5  
hw_dbg6  
hw_dbg7  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
K24  
safe_mo  
de  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
83  
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Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
K27  
Top  
Bottom  
N25  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
J23  
K23  
F21  
G21  
C22  
F18  
J20  
NA  
cam_d8  
gpio_107(1)  
gpio_108(1)  
gpio_109  
safe_mo  
de  
L27  
N26  
D25  
E26  
E25  
A23  
D26  
AD17  
AD16  
AE18  
AE17  
U18  
R18  
T18  
R19  
N19  
L18  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
cam_d9  
safe_mo  
de  
B25  
C26  
B26  
B23  
D25  
AG19  
AH19  
AG18  
AH18  
P21  
N21  
R21  
M21  
N28  
M27  
N27  
N26  
N25  
P28  
P27  
P26  
R27  
R25  
AE2  
AG5  
AH5  
AH4  
AG4  
AF4  
AE4  
AH3  
cam_d10  
cam_d11  
cam_xclkb  
cam_wen  
cam_strobe  
hw_dbg8  
hw_dbg9  
safe_mo  
de  
gpio_110  
safe_mo  
de  
gpio_111  
safe_mo  
de  
cam_shutter  
gpio_167  
hw_dbg10  
hw_dbg11  
safe_mo  
de  
gpio_126  
safe_mo  
de  
gpio_112(1)  
gpio_113(1)  
gpio_114(1)  
gpio_115(1)  
gpio_116  
safe_mo  
de  
NA  
safe_mo  
de  
NA  
safe_mo  
de  
NA  
safe_mo  
de  
V20  
T21  
V19  
R20  
M23  
L23  
M22  
M21  
M20  
N23  
N22  
NA  
mcbsp2_fsx  
mcbsp2_clkx  
mcbsp2_dr  
mcbsp2_dx  
mmc1_clk  
safe_mo  
de  
gpio_117  
safe_mo  
de  
gpio_118  
safe_mo  
de  
gpio_119  
safe_mo  
de  
gpio_120(2)  
gpio_121(2)  
gpio_122(2)  
gpio_123(2)  
gpio_124(2)  
gpio_125(2)  
gpio_126(2)  
gpio_127(2)  
gpio_128(2)  
gpio_129(2)  
gpio_130  
safe_mo  
de  
mmc1_cmd  
mmc1_dat0  
mmc1_dat1  
mmc1_dat2  
mmc1_dat3  
safe_mo  
de  
M19  
M18  
K18  
N20  
M20  
P17  
P18  
P19  
W10  
R10  
T10  
T9  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
NA  
safe_mo  
de  
P24  
Y1  
safe_mo  
de  
mmc2_clk  
mcspi3_clk  
safe_mo  
de  
AB5  
AB3  
Y3  
mmc2_cmd  
mmc2_dat0  
mmc2_dat1  
mmc2_dat2  
mmc2_dat3  
mmc2_dat4  
mmc2_dat5  
mcspi3_simo  
mcspi3_somi  
gpio_131  
safe_mo  
de  
gpio_132  
safe_mo  
de  
gpio_133  
safe_mo  
de  
U10  
U9  
W3  
mcspi3_cs1  
mcspi3_cs0  
gpio_134  
safe_mo  
de  
V3  
gpio_135  
safe_mo  
de  
V10  
M3  
AB2  
AA2  
mmc2_dir_dat  
0
mmc3_dat0 gpio_136  
safe_mo  
de  
mmc2_dir_dat cam_global_res mmc3_dat1 gpio_137  
et  
mm3_rxdp safe_mo  
de  
1
84  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
AF3  
Top  
Bottom  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
L3  
NA  
Y2  
mmc2_dat6  
mmc2_dat7  
mcbsp3_dx  
mcbsp3_dr  
mmc2_dir_cm cam_shutter  
d
mmc3_dat2 gpio_138  
mmc3_dat3 gpio_139  
gpio_140  
safe_mo  
de  
AE3  
AF6  
AE6  
AF5  
AE5  
AB26  
AB25  
AA25  
AD25  
AA8  
AA9  
W8  
K3  
P3  
N3  
U3  
W3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AA1  
V6  
mmc2_clkin  
uart2_cts  
uart2_rts  
mm3_rxdm safe_mo  
de  
safe_mo  
de  
V5  
gpio_141  
safe_mo  
de  
W4  
V4  
mcbsp3_clkx uart2_tx  
mcbsp3_fsx uart2_rx  
gpio_142  
safe_mo  
de  
gpio_143  
safe_mo  
de  
Y24  
AA24  
AD22  
AD21  
L4  
NA  
NA  
NA  
NA  
W7  
W6  
AC2  
V7  
uart2_cts  
uart2_rts  
uart2_tx  
mcbsp3_dx  
mcbsp3_dr  
gpt_9_pwm_evt  
gpio_144  
safe_mo  
de  
gpt_10_pwm_e  
vt  
gpio_145  
safe_mo  
de  
mcbsp3_clkx gpt_11_pwm_e  
vt  
gpio_146  
safe_mo  
de  
uart2_rx  
mcbsp3_fsx gpt_8_pwm_evt  
gpio_147  
safe_mo  
de  
uart1_tx  
gpio_148  
safe_mo  
de  
R2  
uart1_rts  
uart1_cts  
uart1_rx  
gpio_149  
safe_mo  
de  
W2  
gpio_150  
safe_mo  
de  
Y8  
H3  
mcbsp1_clkr  
mcspi4_clk gpio_151  
gpio_152  
safe_mo  
de  
AE1  
AD1  
AD2  
AC1  
Y21  
AA21  
V21  
U21  
T21  
V3  
NA  
NA  
NA  
NA  
W19  
mcbsp4_clkx  
mcbsp4_dr  
mcbsp4_dx  
mcbsp4_fsx  
mm3_txse0 safe_mo  
de  
U4  
gpio_153  
mm3_rxrcv safe_mo  
de  
R3  
gpio_154  
mm3_txdat safe_mo  
de  
T3  
gpio_155  
mm3_txen_ safe_mo  
n
de  
U19  
V17  
U17  
T20  
T19  
P20  
T17  
F23  
F24  
H24  
G24  
W19  
U20  
V19  
W18  
mcbsp1_clkr mcspi4_clk  
mcbsp1_fsr  
gpio_156  
safe_mo  
de  
AB20  
W18  
Y18  
cam_global_res  
et  
gpio_157  
safe_mo  
de  
mcbsp1_dx  
mcspi4_simo mcbsp3_dx  
gpio_158  
safe_mo  
de  
mcbsp1_dr  
mcspi4_somi mcbsp3_dr  
gpio_159  
safe_mo  
de  
AA18  
AA19  
V18  
mcbsp_clks  
cam_shutter  
mcbsp3_fsx  
mcbsp3_clkx  
gpio_160  
uart1_cts  
safe_mo  
de  
K26  
W21  
H18  
H19  
H20  
H21  
T28  
mcbsp1_fsx mcspi4_cs0  
mcbsp1_clkx  
uart3_cts_rctx  
uart3_rts_sd  
uart3_rx_irrx  
uart3_tx_irtx  
hsusb0_clk  
gpio_161  
safe_mo  
de  
gpio_162  
safe_mo  
de  
A23  
gpio_163  
safe_mo  
de  
B23  
gpio_164  
safe_mo  
de  
B24  
gpio_165  
safe_mo  
de  
C23  
R21  
R23  
P23  
gpio_166  
safe_mo  
de  
gpio_120  
safe_mo  
de  
T25  
hsusb0_stp  
gpio_121  
safe_mo  
de  
R28  
T26  
hsusb0_dir  
gpio_122  
safe_mo  
de  
R22  
hsusb0_nxt  
gpio_124  
safe_mo  
de  
Copyright © 2010, Texas Instruments Incorporated  
TERMINAL DESCRIPTION  
85  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
SPRS685–AUGUST 2010  
www.ti.com  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
T27  
Top  
Bottom  
V20  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
T24  
T23  
U24  
U23  
W24  
V23  
W23  
T22  
hsusb0_data0  
hsusb0_data1  
hsusb0_data2  
hsusb0_data3  
hsusb0_data4  
hsusb0_data5  
hsusb0_data6  
hsusb0_data7  
uart3_tx_irtx  
uart3_rx_irrx  
uart3_rts_sd  
uart3_cts_rctx  
gpio_125  
uart2_tx  
uart2_rx  
uart2_rts  
uart2_cts  
safe_mo  
de  
U28  
U27  
U26  
U25  
V28  
V27  
V26  
Y20  
V18  
W20  
W17  
Y18  
Y19  
Y17  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
gpio_130  
gpio_131  
gpio_169  
gpio_188  
gpio_189  
gpio_190  
gpio_191  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
safe_mo  
de  
K21  
J21  
NA  
NA  
NA  
J25  
J24  
C2  
NA  
NA  
NA  
K20  
K21  
i2c1_scl  
i2c1_sda  
i2c2_scl  
AF15  
AC15  
AC14  
AC13  
AC12  
Y16  
Y15  
A24  
T5  
gpio_168  
gpio_183  
gpio_184  
gpio_185  
safe_mo  
de  
AE15  
AF14  
AG14  
AD26  
AE26  
J25  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
C1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
i2c2_sda  
i2c3_scl  
i2c3_sda  
i2c4_scl  
i2c4_sda  
hdq_sio  
safe_mo  
de  
AB4  
AC4  
AD15  
W16  
J23  
P9  
safe_mo  
de  
safe_mo  
de  
sys_nvmode1  
sys_nvmode2  
sys_altclk  
safe_mo  
de  
safe_mo  
de  
i2c2_sccbe  
i2c3_sccbe gpio_170  
gpio_171  
safe_mo  
de  
AB3  
AB4  
AA4  
AC2  
AC3  
AB1  
AB2  
AA3  
Y2  
mcspi1_clk  
mmc2_dat4  
safe_mo  
de  
P8  
R4  
mcspi1_simo mmc2_dat5  
mcspi1_somi mmc2_dat6  
gpio_172  
safe_mo  
de  
P7  
T4  
gpio_173  
safe_mo  
de  
R7  
T6  
mcspi1_cs0  
mcspi1_cs1  
mcspi1_cs2  
mcspi1_cs3  
mcspi2_clk  
mmc2_dat7  
gpio_174  
safe_mo  
de  
R8  
NA  
mmc3_cmd gpio_175  
mmc3_clk gpio_176  
safe_mo  
de  
R9  
NA  
safe_mo  
de  
T8  
R5  
hsusb2_dat gpio_177  
a2  
mm2_txdat  
safe_mo  
de  
W7  
W8  
U8  
N5  
hsusb2_dat gpio_178  
a7  
safe_mo  
de  
N4  
mcspi2_simo gpt_9_pwm_e  
vt  
hsusb2_dat gpio_179  
a4  
safe_mo  
de  
Y3  
N3  
mcspi2_somi gpt_10_pwm_  
evt  
hsusb2_dat gpio_180  
a5  
safe_mo  
de  
Y4  
V8  
M5  
mcspi2_cs0  
gpt_11_pwm_  
evt  
hsusb2_dat gpio_181  
a6  
safe_mo  
de  
V3  
V9  
M4  
mcspi2_cs1  
gpt_8_pwm_e  
vt  
hsusb2_dat gpio_182  
a3  
mm2_txen_  
n
safe_mo  
de  
AE25  
AE17  
AF17  
AF25  
NA  
NA  
NA  
NA  
AE20  
AF19  
AF20  
W15  
NA  
NA  
NA  
NA  
AA16  
AD15  
AD14  
Y13  
sys_32k  
sys_xtalin  
sys_xtalout  
sys_clkreq  
gpio_1  
gpio_0  
safe_mo  
de  
AF26  
AH25  
NA  
NA  
V16  
V13  
NA  
NA  
W16  
sys_nirq  
safe_mo  
de  
AA10  
sys_nrespwro  
n
86  
TERMINAL DESCRIPTION  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): DM3730 DM3725  
DM3730, DM3725  
www.ti.com  
SPRS685–AUGUST 2010  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
AF24  
Top  
Bottom  
AD7  
Top  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AA5  
Y10  
sys_nreswar  
m
gpio_30  
safe_mo  
de  
AH26  
AG26  
AE14  
AF18  
AF19  
AE21  
AF21  
AF22  
AG25  
AE22  
F3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AB12  
AC16  
AD17  
AD18  
AC17  
AB16  
AA15  
AD23  
Y7  
sys_boot0  
sys_boot1  
sys_boot2  
sys_boot3  
sys_boot4  
sys_boot5  
sys_boot6  
sys_off_mode  
sys_clkout1  
sys_clkout2  
dss_data18 gpio_2  
dss_data19 gpio_3  
gpio_4  
safe_mo  
de  
D3  
safe_mo  
de  
C3  
safe_mo  
de  
E3  
dss_data20 gpio_5  
dss_data21 gpio_6  
dss_data22 gpio_7  
dss_data23 gpio_8  
gpio_9  
safe_mo  
de  
E4  
mmc2_dir_dat  
2
safe_mo  
de  
G3  
mmc2_dir_dat  
3
safe_mo  
de  
D4  
safe_mo  
de  
V12  
AE14  
W11  
safe_mo  
de  
gpio_10  
safe_mo  
de  
AA6  
gpio_186  
safe_mo  
de  
AA17  
AA13  
AA12  
AA18  
NA  
NA  
NA  
NA  
U15  
V14  
W13  
V15  
NA  
NA  
NA  
NA  
AB7  
AB6  
AA7  
AA9  
jtag_ntrst  
jtag_tck  
jtag_rtck  
jtag_tms_tms  
c
AA20  
AA19  
AA11  
NA  
NA  
NA  
U16  
Y13  
Y15  
NA  
NA  
NA  
AB10  
AB9  
jtag_tdi  
jtag_tdo  
jtag_emu0  
AC24  
gpio_11  
gpio_31  
safe_mo  
de  
AA10  
AF10  
AE10  
AF11  
AG12  
AH12  
AE13  
AE11  
AH9  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Y14  
AB2  
AB3  
AC3  
AD4  
AD3  
AA3  
Y3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AD24  
AC1  
AD3  
AD6  
AC6  
AC7  
AD8  
AC5  
AD2  
AC8  
AD9  
AC4  
AD5  
AC3  
AC9  
AC10  
AD11  
jtag_emu1  
etk_clk  
etk_ctl  
safe_mo  
de  
mcbsp5_clkx mmc3_clk  
mmc3_cmd  
hsusb1_stp gpio_12  
hsusb1_clk gpio_13  
mm1_rxdp  
hw_dbg  
0
hw_dbg  
1
etk_d0  
etk_d1  
etk_d2  
etk_d3  
etk_d4  
etk_d5  
etk_d6  
etk_d7  
etk_d8  
etk_d9  
etk_d10  
etk_d11  
etk_d12  
etk_d13  
mcspi3_simo mmc3_dat4  
mcspi3_somi  
hsusb1_dat gpio_14  
a0  
mm1_rxrcv  
mm1_txse0  
mm1_txdat  
hw_dbg  
2
hsusb1_dat gpio_15  
a1  
hw_dbg  
3
mcspi3_cs0  
hsusb1_dat gpio_16  
a2  
hw_dbg  
4
mcspi3_clk  
mcbsp5_dr  
mmc3_dat3  
mmc3_dat0  
hsusb1_dat gpio_17  
a7  
hw_dbg  
5
hsusb1_dat gpio_18  
a4  
hw_dbg  
6
AB1  
AE3  
AD2  
AA4  
V2  
mcbsp5_fsx mmc3_dat1  
hsusb1_dat gpio_19  
a5  
hw_dbg  
7
AF13  
AH14  
AF9  
mcbsp5_dx  
mcspi3_cs1  
mmc3_dat2  
mmc3_dat7  
mmc3_dat6  
mmc3_dat5  
uart1_rx  
hsusb1_dat gpio_20  
a6  
hw_dbg  
8
hsusb1_dat gpio_21  
a3  
mm1_txen_  
n
hw_dbg  
9
hsusb1_dir gpio_22  
hsusb1_nxt gpio_23  
hsusb2_clk gpio_24  
hsusb2_stp gpio_25  
hsusb2_dir gpio_26  
hsusb2_nxt gpio_27  
hw_dbg  
10  
AG9  
mm1_rxdm  
mm2_rxdp  
mm2_rxdm  
hw_dbg  
11  
AE7  
AE4  
AF6  
AE6  
AF7  
hw_dbg  
12  
AF7  
hw_dbg  
13  
AG7  
hw_dbg  
14  
AH7  
hw_dbg  
15  
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Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
AG8  
Top  
Bottom  
AF9  
Top  
NA  
NA  
NA  
AC11  
etk_d14  
hsusb2_dat gpio_28  
a0  
mm2_rxrcv  
mm2_txse0  
hw_dbg  
16  
AH8  
AE9  
NA  
NA  
AD12  
etk_d15  
hsusb2_dat gpio_29  
a1  
hw_dbg  
17  
AC4, J4, H4, NA  
D8, AE9, D9,  
D15, Y16,  
AE18, Y18,  
W18, K18,  
J18, AE19,  
Y19, U19,  
T19, N19,  
AC21, D15,  
G11, G18,  
H20, M7,  
M17, R20, T7,  
Y8, Y12  
F12, F13,  
G12, G13,  
H12, H13,  
J17, J18,  
K17, K18,  
K19, L14,  
L15, M14,  
M15, R17,  
R18, R19,  
T17, T18,  
T19, T20  
vdd_core  
M19, J19,  
Y20, W20,  
V20, U20,  
P20, N20,  
K20, J20,  
D22, D23,  
AE24, M25,  
L25, E25  
Y9, W9, T9, NA  
R9, M9, L9,  
J9, Y10, U10,  
T10, R10,  
N10, M10,  
L10, J10,  
D13, G9,  
NA  
F10, G9, G10, vdd_mpu_iva  
H9, H10, J9,  
J10, L11, L12,  
M6, M7, M8,  
M12, N6, N7,  
N8, R6, R7,  
G12, H7, K11,  
L9, M9, M10,  
N7, N8, P10,  
U7, U11, U13,  
V7, V11, W9,  
Y9, Y11  
Y11, W11,  
K11, J11,  
R8, T7, T8,  
U12, U13,  
W12, K13,  
Y14, K14,  
V12, V13,  
W12, W13  
J14, Y15,  
W15, J15  
U4  
NA  
NA  
D6  
NA  
NA  
N21  
Y12  
cap_vdd_bb_  
mpu_iva  
AA15  
K14  
cap_vddu_wk  
up_logic  
K15  
NA  
NA  
NA  
K13  
NA  
NA  
G18  
vdda_dplls_dll  
vdds_sram  
vdds  
W16  
U12  
AA12  
AD3, AD4,  
W4, AF8,  
A18, AC7,  
AC15, AC18, ,F21,L20,W21 M19, N17,  
A3,A15,B5,F2 M17, M18,  
AE8, AF16,  
AE16, AF23,  
AE23, F25,  
F26, AG27  
AC24, AD20,  
AE10, C11,  
D9, E24, G4,  
J15, J18, L7,  
L24, M4, T4,  
T24, W24,  
N18, N19,  
U10, V9, V10,  
W9, W10, Y9  
Y4, AB24  
U1, J1, F1,  
J2, F2, R4,  
B5, A5, AH6, A4, A7, A10,  
B8, A8, B12, A15, A18  
A12, D16,  
AC5, P1, H1, NA  
F23, E1, C23,  
NA  
E16, F15,  
F16, G15,  
G16, H15, J6,  
J7, J8, K6,  
K7, K8  
vdds_mem  
C16, B18,  
A18, B22,  
A22, G28,  
C28  
AA16  
AA14  
NA  
NA  
U14  
NA  
NA  
U17  
vdda_dpll_per  
W14  
AA13  
vdda_wkup_b  
g_bb  
88  
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SPRS685–AUGUST 2010  
Table 2-4. Multiplexing Characteristics (continued)  
CBP  
CBC  
CUS  
MODE 0  
MODE 1  
MODE 2  
MODE 3  
MODE 4  
MODE 5  
MODE 6  
MODE  
7
Bottom  
Top  
Bottom  
Top  
AG2, U2, B2, B4, B7, B10, A6, A8, A13, A7, A13, B14, H11, H14,  
vss  
AG3, W3, P3, B15, B18, AB5, AB22, C1, F1, F20, H16, J11,  
J3, E3, A3, C22, E2, F22, AC10, AD14, H2, H20, L21, J12, J13, J14,  
P4, E4, AG6, H2, P2, AB5, AD25, AE7, M2, P20, R2, J15, J16,  
D7, C7, V9, AB14, AB20 B2, B25, C12, W20 Y6, Y11, K10, K11,  
U9, P9, N9,  
K9, W10,  
D7, D10, D12, AA7, AA16  
D14, D18,  
K14, K15, L8,  
L10, L13,  
V10, P10,  
K10, D10,  
C10, AF12,  
AE12, Y12,  
K12, J12,  
Y13, W13,  
J13, D13,  
C13, W14,  
K16, J16,  
W17, K17,  
J17, W19,  
V19, R19,  
P19, L19,  
K19, D19,  
C19, AF20,  
AE20, T20,  
AG15, AF2,  
AF27, B15,  
J27, M2, M26,  
N2, AA2,  
D20, E22, G1,  
G8, G10,  
G20, G23,  
H4, K1, K15,  
K25, L10,  
L17, L23, N4,  
N10, N17, R1,  
R4, R17, T23,  
U25, W1, W4,  
W23, Y7,  
L17, M9,  
M10, M11,  
M13, M16,  
N9, N10, N11,  
N12, N13,  
N14, N15,  
N16, P8, P10,  
P11, P12,  
P13, P14,  
P15, P17,  
R10, R11,  
R14, R15, T9,  
T10, T11,  
T12, T13,  
T14, T15,  
T16, U9, U11,  
U14, U15,  
U16, V15,  
V16  
Y10, Y16,  
Y26  
AG10, AC25,  
AC26, Y25,  
W25, M20,  
L20, L26,  
G27, D21,  
C22, B27,  
A26, R20,  
R26  
V25  
NA  
NA  
NA  
NA  
NA  
NA  
V25  
NA  
NA  
NA  
NA  
NA  
NA  
AB13  
AB15  
N24  
H8  
vdda_dac  
vssa_dac  
vdds_mmc1  
vdds_x  
Y26  
V24  
K25  
N23  
P25  
P23  
AG21  
AH20  
AD19  
AE19  
NA  
vdds  
N20  
cap_vddu_arr  
ay  
AH21  
AG16  
AG20  
M28  
H28  
NA  
NA  
NA  
NA  
NA  
NA  
AC19  
AC16  
AD18  
L19  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
U8  
vss  
vss  
vdds  
vss  
L20  
vdds  
V4  
N9  
cap_vdd_sra  
m_mpu_iva  
L21  
Y17  
NA  
NA  
K20  
NA  
NA  
H17  
cap_vdd_sra  
m_core  
AF23  
W15  
sys_xtalgnd  
(1) This GPIO is only an input (and not an output).  
(2) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(3) UART4 is only available on CBP and CBC packages.  
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2.5 Signal Description  
Many signals are available on multiple pins according to the software configuration of the pin multiplexing  
options.  
1. SIGNAL NAME: The signal name  
2. DESCRIPTION: Description of the signal  
3. TYPE: Type = Ball type for this specific function:  
–
–
–
–
–
–
I = Input  
O = Output  
Z = High-impedance  
D = Open Drain  
DS = Differential  
A = Analog  
4. BALL BOTTOM: Associated ball(s) bottom  
5. BALL TOP: Associated ball(s) top  
6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the  
module/subsystem level. The pin function is selected at the module/system level.  
Note: The Subsystem Multiplexing Signals are not described in the following tables. For more  
information, see the System Control Module / System Control Module Functional Description / Pad  
Functional Multiplexing and Configuration section of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
2.5.1 External Memory Interfaces  
NOTE  
For more information, see Memory Subsystem / General-Purpose Memory Controller /  
GPMC Environment section of the AM/DM37x Multimedia Device Technical Reference  
Manual (literature number SPRUGN4).  
Table 2-5. External Memory Interfaces – GPMC Signals Description(1)  
SIGNAL NAME  
[1]  
DESCRIPTION [2]  
TYPE  
[3]  
BALL  
BOTTOM  
(CBP  
BALL  
TOP  
(CBP  
BALL BOTTOM  
(CBC Pkg.) [4]  
BALL TOP  
(CBC Pkg.) [5]  
BALL  
BOTTOM  
(CUS  
SUBSYSTEM  
PIN  
MULTIPLEXING  
[6]  
Pkg.) [4]  
Pkg.) [5]  
Pkg.) [4]  
gpmc_a1  
gpmc_a2  
gpmc_a3  
gpmc_a4  
gpmc_a5  
gpmc_a6  
gpmc_a7  
gpmc_a8  
GPMC output address bit 1 /  
extended multiplexed address  
gpmc_a17  
O
O
O
O
O
O
O
O
N4 / K1  
M4 / L1  
L4 / L2  
K4 / P2  
T3 / T1  
R3 / V1  
N3 / V2  
M3 / W2  
AC15 / M2  
AB15 / M1  
AC16 / N2  
AB16 / N1  
AC17 / R2  
AB17 / R1  
AC18 / T2  
AB18 / T1  
J2 / AA2  
H1 / AA1  
H2 / AC2  
G2 / AC1  
F1 / AE5  
F2 / AD6  
E1 / AD5  
E2 / AC5  
NA / U2  
NA / U1  
NA / V2  
NA / V1  
NA / AA3  
NA / AA4  
NA / Y3  
NA / Y4  
K4 / L2  
K3 / M1  
K2 / M2  
J4 / N2  
J3 / M3  
J2/ P1  
- / gpmc_d0  
- / gpmc_d1  
- / gpmc_d2  
- / gpmc_d3  
- / gpmc_d4  
- / gpmc_d5  
- / gpmc_d6  
- / gpmc_d7  
GPMC output address bit 2 /  
extended multiplexed address  
gpmc_a18  
GPMC output address bit 3 /  
extended multiplexed address  
gpmc_a19  
GPMC output address bit 4 /  
extended multiplexed address  
gpmc_a20  
GPMC output address bit 5 /  
extended multiplexed address  
gpmc_a21  
GPMC output address bit 6 /  
extended multiplexed address  
gpmc_a22  
GPMC output address bit 7 /  
extended multiplexed address  
gpmc_a23  
J1/ P2  
GPMC output address bit 8 /  
extended multiplexed address  
gpmc_a24  
H1/ R1  
90  
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SPRS685–AUGUST 2010  
Table 2-5. External Memory Interfaces – GPMC Signals Description(1) (continued)  
SIGNAL NAME  
[1]  
DESCRIPTION [2]  
TYPE  
[3]  
BALL  
BOTTOM  
(CBP  
BALL  
TOP  
(CBP  
BALL BOTTOM  
(CBC Pkg.) [4]  
BALL TOP  
(CBC Pkg.) [5]  
BALL  
BOTTOM  
(CUS  
SUBSYSTEM  
PIN  
MULTIPLEXING  
[6]  
Pkg.) [4]  
Pkg.) [5]  
Pkg.) [4]  
gpmc_a9  
gpmc_a10  
gpmc_a11  
GPMC output address bit 9 /  
extended multiplexed address  
gpmc_a25  
O
O
O
L3 / H2  
K3 / K2  
NC / P1  
AC19 /  
AB3  
D1 / V1  
D2 / Y1  
A4 / T1  
NA / R1  
T1  
H2/ R2  
G2/ T2  
NA  
- / gpmc_d8  
- / gpmc_d9  
- / gpmc_d10  
GPMC output address bit 10 /  
extended multiplexed address  
gpmc_a26  
AB19 /  
AC3  
GPMC output address bit 11 /  
extended multiplexed address  
gpmc_a27  
AC20 /  
AB4  
- / N1  
gpmc_a12  
gpmc_a13  
gpmc_a14  
gpmc_a15  
gpmc_a16  
gpmc_a17  
gpmc_a18  
gpmc_a19  
gpmc_a20  
gpmc_a21  
gpmc_a22  
gpmc_a23  
gpmc_a24  
gpmc_a25  
gpmc_a26  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpmc_d9  
General-purpose memory address  
bit 12  
O
O
R1  
R2  
T2  
W1  
Y1  
N4  
M4  
L4  
AC4  
AB6  
AC6  
AB7  
AC7  
AC15  
AB15  
AC16  
AB16  
AC17  
AB17  
AC18  
AB18  
AC19  
AB19  
M2  
U2  
U1  
P2  
P1  
R3  
T3  
U2  
V1  
V2  
K4  
K3  
K2  
J4  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
gpmc_a1  
gpmc_a2  
gpmc_a3  
gpmc_a4  
gpmc_a5  
gpmc_a6  
gpmc_a7  
gpmc_a8  
gpmc_a9  
gpmc_a10  
gpmc_d0  
gpmc_d1  
gpmc_d2  
gpmc_d3  
gpmc_d4  
gpmc_d5  
gpmc_d6  
gpmc_d7  
gpmc_d8  
gpmc_d9  
General-purpose memory address  
bit 13  
General-purpose memory address  
bit 14  
O
P1  
M1  
J2  
General-purpose memory address  
bit 15  
O
L2  
General-purpose memory address  
bit 16  
O
M2  
J2  
K2  
General-purpose memory address  
bit 17  
O
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
U2  
U1  
V2  
General-purpose memory address  
bit 18  
O
H1  
General-purpose memory address  
bit 19  
O
H2  
General-purpose memory address  
bit 20  
O
K4  
T3  
R3  
N3  
M3  
L3  
G2  
General-purpose memory address  
bit 21  
O
F1  
J3  
General-purpose memory address  
bit 22  
O
F2  
J2  
General-purpose memory address  
bit 23  
O
E1  
J1  
General-purpose memory address  
bit 24  
O
E2  
H1  
H2  
G2  
L2  
General-purpose memory address  
bit 25  
O
D1  
General-purpose memory address  
bit 26  
O
K3  
K1  
L1  
D2  
GPMC data bit 0 / multiplexed  
address gpmc_a1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AA2  
AA1  
AC2  
AC1  
AE5  
AD6  
AD5  
AC5  
V1  
GPMC data bit 1 / multiplexed  
address gpmc_a2  
M1  
M1  
M2  
N2  
M3  
P1  
P2  
R1  
R2  
T2  
GPMC data bit 2 / multiplexed  
address gpmc_a3  
L2  
N2  
GPMC data bit 3 / multiplexed  
address gpmc_a4  
P2  
T1  
V1  
V2  
W2  
H2  
K2  
N1  
V1  
GPMC data bit 4 / multiplexed  
address gpmc_a5  
R2  
AA3  
AA4  
Y3  
GPMC data bit 5 / multiplexed  
address gpmc_a6  
R1  
GPMC data bit 6 / multiplexed  
address gpmc_a7  
T2  
GPMC data bit 7 / multiplexed  
address gpmc_a8  
T1  
Y4  
GPMC data bit 8 / multiplexed  
address gpmc_a9  
AB3  
AC3  
R1  
T1  
GPMC data bit 9 / multiplexed  
address gpmc_a10  
Y1  
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Table 2-5. External Memory Interfaces – GPMC Signals Description(1) (continued)  
SIGNAL NAME  
[1]  
DESCRIPTION [2]  
TYPE  
[3]  
BALL  
BOTTOM  
(CBP  
BALL  
TOP  
(CBP  
BALL BOTTOM  
(CBC Pkg.) [4]  
BALL TOP  
(CBC Pkg.) [5]  
BALL  
BOTTOM  
(CUS  
SUBSYSTEM  
PIN  
MULTIPLEXING  
[6]  
Pkg.) [4]  
Pkg.) [5]  
Pkg.) [4]  
gpmc_d10  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
GPMC data bit 10 / multiplexed  
address gpmc_a11  
IO  
IO  
IO  
IO  
IO  
IO  
P1  
R1  
R2  
T2  
AB4  
AC4  
AB6  
AC6  
AB7  
AC7  
T1  
U2  
U1  
P1  
L2  
N1  
P2  
P1  
M1  
J2  
U1  
R3  
T3  
U2  
V1  
V2  
gpmc_d10  
gpmc_d11  
gpmc_d12  
gpmc_d13  
gpmc_d14  
gpmc_d15  
GPMC data bit 11 / multiplexed  
address gpmc_a12  
GPMC data bit 12 / multiplexed  
address gpmc_a13  
GPMC data bit 13 / multiplexed  
address gpmc_a14  
GPMC data bit 14 / multiplexed  
address gpmc_a15  
W1  
Y1  
GPMC data bit 15 / multiplexed  
address gpmc_a16  
M2  
K2  
gpmc_ncs0  
gpmc_ncs1  
gpmc_ncs2  
gpmc_ncs3  
gpmc_ncs4  
gpmc_ncs5  
gpmc_ncs6  
gpmc_ncs7  
gpmc_io_dir  
GPMC Chip Select bit 0  
GPMC Chip Select bit 1  
GPMC Chip Select bit 2  
GPMC Chip Select bit 3  
GPMC Chip Select bit 4  
GPMC Chip Select bit 5  
GPMC Chip Select bit 6  
GPMC Chip Select bit 7  
O
O
O
O
O
O
O
O
O
G4  
H3  
V8  
U8  
T8  
R8  
P8  
N8  
N8  
Y2  
Y1  
AD8  
AD1  
A3  
AA8  
W1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
E2  
NA  
NA  
D2  
F4  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
B6  
NA  
B4  
NA  
C4  
B5  
G5  
F3  
NA  
NA  
C5  
C5  
G4  
G4  
NA  
GPMC IO direction control for use  
with external transceivers  
gpmc_ncs7  
gpmc_clk  
GPMC clock  
O
O
T4  
F3  
W2  
W1  
N1  
L1  
W2  
F1  
NA  
NA  
gpmc_nadv_ale Address Valid or Address Latch  
Enable  
AD10  
AA9  
gpmc_noe  
gpmc_nwe  
Output Enable  
Write Enable  
O
O
O
G2  
F4  
G3  
V2  
V1  
N2  
M1  
K2  
L2  
K1  
NA  
F2  
G3  
K5  
NA  
NA  
NA  
gpmc_nbe0_cle Lower Byte Enable. Also used for  
Command Latch Enable  
AC12  
gpmc_nbe1  
gpmc_nwp  
gpmc_wait0  
gpmc_wait1  
gpmc_wait2  
gpmc_wait3  
Upper Byte Enable  
O
O
I
U3  
H1  
M8  
L8  
NA  
AB10  
AB12  
AC10  
NA  
J1  
AC6  
AC11  
AC8  
B3  
NA  
Y5  
L1  
E1  
C1  
NA  
NA  
C2  
NA  
NA  
NA  
NA  
NA  
NA  
Flash Write Protect  
External indication of wait  
External indication of wait  
External indication of wait  
External indication of wait  
Y10  
Y8  
I
I
K8  
J8  
NA  
NA  
I
NA  
C6  
(1) NA in table stands for "Not Applicable".  
(2) For a list of pins not supported on a particular package, see TBD.  
NOTE  
For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem /  
SDRC Subsystem Environment section of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
92  
TERMINAL DESCRIPTION  
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SPRS685–AUGUST 2010  
Table 2-6. External Memory Interfaces – SDRC Signals Description(1)  
SIGNAL  
NAME  
DESCRIPTION  
TYPE(2)  
BALL  
BOTTOM  
(CBP Pkg.)  
BALL TOP  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL TOP  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
sdrc_d0  
sdrc_d1  
sdrc_d2  
sdrc_d3  
sdrc_d4  
sdrc_d5  
sdrc_d6  
sdrc_d7  
sdrc_d8  
sdrc_d9  
sdrc_d10  
sdrc_d11  
sdrc_d12  
sdrc_d13  
sdrc_d14  
sdrc_d15  
sdrc_d16  
sdrc_d17  
sdrc_d18  
sdrc_d19  
sdrc_d20  
sdrc_d21  
sdrc_d22  
sdrc_d23  
sdrc_d24  
sdrc_d25  
sdrc_d26  
sdrc_d27  
sdrc_d28  
sdrc_d29  
sdrc_d30  
sdrc_d31  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
sdrc_a1  
sdrc_a2  
sdrc_a3  
sdrc_a4  
sdrc_a5  
sdrc_a6  
sdrc_a7  
sdrc_a8  
sdrc_a9  
sdrc_a10  
sdrc_a11  
sdrc_a12  
sdrc_a13  
sdrc_a14  
sdrc_ncs0  
SDRAM data bit 0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
J2  
J1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
D1  
G1  
D7  
C5  
SDRAM data bit 1  
SDRAM data bit 2  
G2  
G2  
C6  
SDRAM data bit 3  
G1  
E1  
B5  
SDRAM data bit 4  
F2  
D2  
D9  
SDRAM data bit 5  
F1  
E2  
D10  
C7  
SDRAM data bit 6  
D2  
B3  
SDRAM data bit 7  
D1  
B4  
B7  
SDRAM data bit 8  
B13  
A13  
B14  
A14  
B16  
A16  
B19  
A19  
B3  
A10  
B11  
A11  
B12  
A16  
A17  
B17  
B18  
B7  
B11  
C12  
B12  
D13  
C13  
B14  
A14  
B15  
C9  
SDRAM data bit 9  
SDRAM data bit 10  
SDRAM data bit 11  
SDRAM data bit 12  
SDRAM data bit 13  
SDRAM data bit 14  
SDRAM data bit 15  
SDRAM data bit 16  
SDRAM data bit 17  
SDRAM data bit 18  
SDRAM data bit 19  
SDRAM data bit 20  
SDRAM data bit 21  
SDRAM data bit 22  
SDRAM data bit 23  
SDRAM data bit 24  
SDRAM data bit 25  
SDRAM data bit 26  
SDRAM data bit 27  
SDRAM data bit 28  
SDRAM data bit 29  
SDRAM data bit 30  
SDRAM data bit 31  
SDRAM bank select 0  
SDRAM bank select 1  
SDRAM address bit 0  
SDRAM address bit 1  
SDRAM address bit 2  
SDRAM address bit 3  
SDRAM address bit 4  
SDRAM address bit 5  
SDRAM address bit 6  
SDRAM address bit 7  
SDRAM address bit 8  
SDRAM address bit 9  
SDRAM address bit 10  
SDRAM address bit 11  
SDRAM address bit 12  
SDRAM address bit 13  
SDRAM address bit 14  
Chip select 0  
A3  
A5  
E12  
B8  
B5  
B6  
A5  
A6  
B9  
B8  
A8  
C10  
B10  
D12  
E13  
E15  
D15  
C15  
B16  
C16  
D16  
B17  
B18  
C18  
D18  
A4  
A8  
B9  
B9  
A9  
A9  
B10  
C21  
D20  
B19  
C20  
D21  
E20  
E21  
G21  
AA18  
V20  
G20  
K20  
J20  
J21  
U21  
R20  
M21  
M20  
N20  
K21  
Y16  
N21  
R21  
AA15  
Y12  
T21  
B21  
A21  
D22  
D23  
E22  
E23  
G22  
G23  
AB21  
AC21  
N22  
N23  
P22  
P23  
R22  
R23  
T22  
T23  
U22  
U23  
V22  
V23  
W22  
W23  
Y22  
M22  
O
O
O
B4  
O
D6  
O
B3  
O
B2  
O
C3  
O
E3  
O
F6  
O
E10  
E9  
O
O
E7  
O
G6  
O
G7  
O
F7  
O
F9  
O
A19  
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TERMINAL DESCRIPTION  
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Table 2-6. External Memory Interfaces – SDRC Signals Description(1) (continued)  
SIGNAL  
NAME  
DESCRIPTION  
TYPE(2)  
BALL  
BOTTOM  
(CBP Pkg.)  
BALL TOP  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL TOP  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
sdrc_ncs1  
sdrc_clk  
Chip select 1  
O
IO  
O
O
O
O
O
NA  
NA  
NA  
NA  
NA  
NA  
NA  
M23  
A11  
B11  
J22  
J23  
L23  
L22  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
T20  
A12  
B13  
Y15  
Y13  
V21  
U20  
B19  
A10  
A11  
B20  
C20  
D19  
C19  
Clock  
sdrc_nclk  
sdrc_cke0  
sdrc_cke1  
sdrc_nras  
sdrc_ncas  
Clock Invert  
Clock Enable 0  
Clock Enable 1  
SDRAM Row Access  
SDRAM column  
address strobe  
sdrc_nwe  
sdrc_dm 0  
sdrc_ dm1  
sdrc_ dm2  
sdrc_dm 3  
sdrc_dqs0  
sdrc_dqs1  
sdrc_dqs2  
sdrc_dqs3  
SDRAM write enable  
Data Mask 0  
O
O
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
K23  
C1  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Y18  
H1  
A20  
B6  
Data Mask 1  
O
A17  
A6  
A14  
A4  
B13  
A7  
Data Mask 2  
O
Data Mask 3  
O
A20  
B17  
NA  
A18  
C2  
A16  
A5  
Data Strobe 0  
Data Strobe 1  
Data Strobe 2  
Data Strobe 3  
IO  
IO  
IO  
IO  
B15  
B8  
A13  
A8  
NA  
B20  
A19  
A17  
(1) NA in this table stands for "Not Applicable".  
(2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
(3) For a list of pins not supported on a particular package, see TBD.  
94  
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SPRS685–AUGUST 2010  
2.5.2 Video Interfaces  
Table 2-7. Video Interfaces – CAM Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
cam_hs  
Camera Horizontal Synchronization  
Camera Vertical Synchronization  
Camera Clock Output a  
IO  
IO  
O
O
I
A24  
A23  
C23  
D23  
A22  
E18  
cam_vs  
cam_xclka  
cam_xclkb  
cam_d0  
cam_d1  
cam_d2  
cam_d3  
cam_d4  
cam_d5  
cam_d6  
cam_d7  
cam_d8  
cam_d9  
cam_d10  
cam_d11  
cam_fld  
C25  
C25  
B22  
Camera Clock Output b  
B26  
E25  
C22  
Camera digital image data bit 0  
Camera digital image data bit 1  
Camera digital image data bit 2  
Camera digital image data bit 3  
Camera digital image data bit 4  
Camera digital image data bit 5  
Camera digital image data bit 6  
Camera digital image data bit 7  
Camera digital image data bit 8  
Camera digital image data bit 9  
Camera digital image data bit 10  
Camera digital image data bit 11  
Camera field identification  
AG17  
AH17  
B24  
AE16  
AE15  
A24  
AB18  
AC18  
G19  
I
I
I
C24  
B24  
F19  
I
D24  
D24  
G20  
I
A25  
C24  
B21  
I
K28  
P25  
L24  
I
L28  
P26  
K24  
I
K27  
N25  
J23  
I
L27  
N26  
K23  
I
B25  
D25  
F21  
I
C26  
E26  
G21  
IO  
I
C23  
B23  
H24  
cam_pclk  
cam_wen  
cam_strobe  
Camera pixel clock  
C27  
C26  
J19  
Camera Write Enable  
I
B23  
A23  
F18  
Flash strobe control signal  
O
IO  
D25  
D26  
J20  
cam_global_reset Global reset is used strobe  
synchronization  
C23 / AH3 / AA21  
B23/M3/V17  
H24/ AA2/ AB20  
cam_shutter  
Mechanical shutter control signal  
O
B23 / AF3 / T21  
A23 / T19/ L3  
F18/ Y2/ AA18  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
NOTE  
For more information, see Display Subsystem / Display Subsystem Environment section of  
the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Table 2-8. Video Interfaces – DSS Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
dss_pclk  
LCD Pixel Clock  
O
O
O
O
O
O
O
O
O
O
O
O
O
D28  
D26  
G25  
K24  
G22  
E22  
dss_hsync  
dss_vsync  
dss_acbias  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
dss_data7  
dss_data8  
LCD Horizontal Synchronization  
LCD Vertical Synchronization  
AC bias control (STN) or pixel data enable (TFT) output  
LCD Pixel Data bit 0  
D27  
M25  
F22  
E27  
F26  
J21  
AG22 / H26  
AH22 / H25  
AG23 / E28  
AH23 / J26  
AG24 / AC27  
AH24 / AC28  
E26  
AE21 / M24  
AE22 / M26  
AE23 / F25  
AE24 / N24  
AD23 / AC25  
AD24 / AB25  
G26  
AC19 / G24  
AB19 / H23  
AD20 / D23  
AC20 / K22  
AD21 / V21  
AC21 / W21  
D24  
LCD Pixel Data bit 1  
LCD Pixel Data bit 2  
LCD Pixel Data bit 3  
LCD Pixel Data bit 4  
LCD Pixel Data bit 5  
LCD Pixel Data bit 6  
LCD Pixel Data bit 7  
F28  
H25  
E23  
LCD Pixel Data bit 8  
F27  
H26  
E24  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
TERMINAL DESCRIPTION  
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Table 2-8. Video Interfaces – DSS Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
dss_data9  
LCD Pixel Data bit 9  
LCD Pixel Data bit 10  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
G26  
AD28  
J26  
AC26  
F23  
AC22  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
dss_data14  
dss_data15  
dss_data16  
dss_data17  
dss_data18  
dss_data19  
dss_data20  
dss_data21  
dss_data22  
dss_data23  
LCD Pixel Data bit 11  
LCD Pixel Data bit 12  
LCD Pixel Data bit 13  
LCD Pixel Data bit 14  
LCD Pixel Data bit 15  
LCD Pixel Data bit 16  
LCD Pixel Data bit 17  
LCD Pixel Data bit 18  
LCD Pixel Data bit 19  
LCD Pixel Data bit 20  
LCD Pixel Data bit 21  
LCD Pixel Data bit 22  
LCD Pixel Data bit 23  
AD27  
AD26  
AC23  
AB28  
AA25  
AB22  
AB27  
Y25  
Y22  
AA28  
AA26  
W22  
AA27  
AB26  
V22  
G25  
L25  
J22  
H27  
L26  
G23  
H26 / AH26  
H25 / AG26  
E28 / AF18  
J26 / AF19  
AC27 / AE21  
AC28 / AF21  
M24 / F3  
M26 / D3  
F25 / E3  
N24 / E4  
AC25 / G23  
AB25 / D4  
G24 / AB12  
H23 / AC16  
D23 / AD18  
K22 / AC17  
V21 / AB16  
W21 / AA15  
Table 2-9. Video Interfaces – RFBI Signals Description  
SIGNAL  
NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
SUBSYSTEM PIN  
MULTIPLEXING(2)  
rfbi_a0  
RFBI command/data control  
1st LCD chip select  
RFBI data bus 0  
O
O
E27  
D26  
F26  
K24  
J21  
E22  
dss_acbias  
dss_hsync  
dss_data0  
dss_data1  
dss_data2  
dss_data3  
dss_data4  
dss_data5  
dss_data6  
dss_data7  
dss_data8  
dss_data9  
dss_data10  
dss_data11  
dss_data12  
dss_data13  
dss_data14  
dss_data15  
dss_pclk  
rfbi_cs0  
rfbi_da0  
rfbi_da1  
rfbi_da2  
rfbi_da3  
rfbi_da4  
rfbi_da5  
rfbi_da6  
rfbi_da7  
rfbi_da8  
rfbi_da9  
rfbi_da10  
rfbi_da11  
rfbi_da12  
rfbi_da13  
rfbi_da14  
rfbi_da15  
rfbi_rd  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
AG22 / H26  
AH22 / H25  
AG23 / E28  
AH23 / J26  
AG24 / AC27  
AH24 / AC28  
E26  
AE21 / M24  
AE22 / M26  
AE23 / F25  
AE24 / N24  
AD23 / AC25  
AD24 / AB25  
G26  
AC19 / G24  
AB19 / H23  
AD20 / D23  
AC20 / K22  
AD21 / V21  
AC21 / W21  
D24  
RFBI data bus 1  
RFBI data bus 2  
RFBI data bus 3  
RFBI data bus 4  
RFBI data bus 5  
RFBI data bus 6  
RFBI data bus 7  
F28  
H25  
E23  
RFBI data bus 8  
F27  
H26  
E24  
RFBI data bus 9  
G26  
J26  
F23  
RFBI data bus 10  
RFBI data bus 11  
RFBI data bus 12  
RFBI data bus 13  
RFBI data bus 14  
RFBI data bus 15  
Read enable for RFBI  
Write Enable for RFBI  
AD28  
AC26  
AC22  
AD27  
AD26  
AC23  
AB28  
AA25  
AB22  
AB27  
Y25  
Y22  
AA28  
AA26  
W22  
AA27  
AB26  
V22  
D28  
G25  
G22  
rfbi_wr  
O
D27  
M25  
F22  
dss_vsync  
dss_data16  
rfbi_te_vsync tearing effect removal and Vsync input  
I
G25  
L25  
J22  
0
from 1st LCD  
rfbi_hsync0  
Hsync for 1st LCD  
I
I
H27  
L26  
G23  
dss_data17  
dss_data18  
rfbi_te_vsync tearing effect removal and Vsync input  
H26 / AH26  
M24 / F3  
G24 / AB12  
1
from 2nd LCD  
rfbi_hsync1  
rfbi_cs1  
Hsync for 2nd LCD  
2nd LCD chip select  
I
H25 / AG26  
E28 / AF18  
M26 / D3  
F25 / E3  
H23 / AC16  
D23 / AD18  
dss_data19  
dss_data20  
O
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-4.  
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Table 2-10. Video Interfaces – TV Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
cvideo1_out  
TV analog output Composite:  
cvideo1_out  
AO  
Y28  
W26  
AB24  
cvideo2_out  
cvideo1_vfb  
TV analog output S-VIDEO: cvideo2_out  
AO  
AO  
W28  
Y27  
V26  
AA23  
AB23  
cvideo1_vfb: Feedback through external  
resistor to composite  
W25  
cvideo2_vfb  
cvideo1_rset  
cvideo2_vfb: Feedback through external  
resistor to S-VIDEO  
AO  
W27  
W26  
U24  
V23  
Y23  
Y24  
cvideo1 input reference current resistor  
setting  
AIO  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
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2.5.3 Serial Communication Interfaces  
For more information, see HDQ/1-Wire / HDQ/1-Wire Environment section of the AM/DM37x Multimedia  
Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-11. Serial Communication Interfaces – HDQ/1-Wire Signals Description  
SIGNAL  
NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
hdq_sio  
Bidirectional HDQ 1-Wire control and data  
Interface. Output is open drain.  
IOD  
J25  
J23  
A24  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
For more information, see Multimaster High-Speed I2C Controller / HS I2C Environment section of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-12. Serial Communication Interfaces – I2C Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)  
I2C Master Serial clock. Output is open  
i2c1_scl  
OD  
K21  
J21  
J25  
J24  
K20  
K21  
drain.  
I2C Serial Bidirectional Data. Output is  
i2c1_sda  
IOD  
open drain.  
INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)  
I2C Master Serial clock. Output is open  
i2c3_scl  
OD  
IOD  
OD  
AF14  
AG14  
J25  
AB4  
AC4  
J23  
AC13  
AC12  
A24  
drain.  
I2C Serial Bidirectional Data. Output is  
i2c3_sda  
open drain.  
i2c3_sccbe  
Serial Camera Control Bus Enable  
INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)  
I2C Master Serial clock. Output is open  
i2c2_scl  
OD  
IOD  
OD  
AF15  
AE15  
J25  
C2  
C1  
AC15  
AC14  
A24  
drain.  
I2C Serial Bidirectional Data. Output is  
i2c2_sda  
open drain.  
i2c2_sccbe  
Serial Camera Control Bus Enable  
J23  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
For more information, see Power Reset and Clock Management / PRCM Introduction to Power  
Management / SmartReflex Voltage-Control Overview section of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
Table 2-13. Serial Communication Interfaces – SmartReflex Signals Description(1)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
INTER-INTEGRATED CIRCUIT INTERFACE (I2C4)  
I2C Master Serial clock. Output is open  
i2c4_scl  
OD  
AD26  
AE26  
AD15  
W16  
Y16  
Y15  
drain.  
I2C Serial Bidirectional Data. Output is  
i2c4_sda  
IOD  
open drain.  
(1) For more information on SmartReflex voltage control, see the PRCM chapter of the AM/DM37x Multimedia Device Technical Reference  
Manual (literature number SPRUGN4).  
(2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).  
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For more information, see Multi-Channel Buffered Serial Port / McBSP Environment section of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
MULTICHANNEL SERIAL (McBSP LP 1)  
mcbsp1_dr  
mcbsp1_clkr  
mcbsp1_fsr  
mcbsp1_dx  
mcbsp1_clkx  
mcbsp1_fsx  
mcbsp_clks  
Received serial data  
Receive Clock  
I
U21  
Y8 / Y21  
AA21  
V21  
T20  
U19 / H3  
V17  
Y18  
V7 / W19  
AB20  
W18  
IO  
IO  
O
IO  
IO  
I
Receive frame synchronization  
Transmitted serial data  
Transmit clock  
U17  
W21  
T17  
V18  
Transmit frame synchronization  
K26  
P20  
AA19  
AA18  
External clock input (shared by McBSP1, 2,  
3, 4, and 5)  
T21  
T19  
MULTICHANNEL SERIAL (McBSP LP 2)  
mcbsp2_dr  
mcbsp2_dx  
mcbsp2_clkx  
mcbsp2_fsx  
Received serial data  
I
R21  
M21  
N21  
P21  
T18  
R19  
R18  
U18  
V19  
R20  
T21  
V20  
Transmitted serial data  
Combined serial clock  
O
IO  
IO  
Combined frame synchronization  
MULTICHANNEL SERIAL (McBSP LP 3)  
mcbsp3_dr  
mcbsp3_dx  
mcbsp3_clkx  
mcbsp3_fsx  
Received serial data  
I
AE6 / AB25 / U21  
AF6 / AB26 / V21  
AF5 / AA25 / W21  
AE5 / AD25 / K26  
T20 / AA24 / N3  
U17 / Y24 / P3  
T17 / AD22 / U3  
P20 / AD21 / W3  
V5 / Y18  
V6 / W18  
W4 / V18  
V4 / AA19  
Transmitted serial data  
Combined serial clock  
O
IO  
IO  
Combined frame synchronization  
MULTICHANNEL SERIAL (McBSP LP 4)  
mcbsp4_dr  
mcbsp4_dx  
mcbsp4_clkx  
mcbsp4_fsx  
Received serial data  
I
R8 / AD1  
P8 / AD2  
T8 / AE1  
N8 / AC1  
C4 / U4  
B5 / R3  
B4 / V3  
C5 / T3  
G5  
F3  
F4  
G4  
Transmitted serial data  
Combined serial clock  
O
IO  
IO  
Combined frame synchronization  
MULTICHANNEL SERIAL (McBSP LP 5)  
mcbsp5_dr  
mcbsp5_dx  
mcbsp5_clkx  
mcbsp5_fsx  
Received serial data  
I
AE11  
AF13  
AF10  
AH9  
Y3  
AC5  
AC8  
AC1  
AD2  
Transmitted serial data  
Combined serial clock  
O
AE3  
AB2  
AB1  
IO  
IO  
Combined frame synchronization  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
For more information, see Multichannel SPI / McSPI Environment section of the AM/DM37x Multimedia  
Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-15. Serial Communication Interfaces – McSPI Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)  
mcspi1_clk  
SPI Clock  
IO  
IO  
IO  
IO  
AB3  
AB4  
AA4  
AC2  
P9  
P8  
P7  
R7  
T5  
R4  
T4  
T6  
mcspi1_simo  
mcspi1_somi  
mcspi1_cs0  
Slave data in, master data out  
Slave data out, master data in  
SPI Enable 0, polarity configured by  
software  
mcspi1_cs1  
mcspi1_cs2  
SPI Enable 1, polarity configured by  
software  
O
O
AC3  
AB1  
R8  
R9  
NA  
NA  
SPI Enable 2, polarity configured by  
software  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
mcspi1_cs3  
SPI Enable 3, polarity configured by  
software  
O
AB2  
T8  
R5  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)  
mcspi2_clk  
SPI Clock  
IO  
IO  
IO  
IO  
AA3  
Y2  
W7  
W8  
U8  
V8  
N5  
N4  
N3  
M5  
mcspi2_simo  
mcspi2_somi  
mcspi2_cs0  
Slave data in, master data out  
Slave data out, master data in  
Y3  
SPI Enable 0, polarity configured by  
software  
Y4  
mcspi2_cs1  
SPI Enable 1, polarity configured by  
software  
O
V3  
V9  
M4  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)  
mcspi3_clk  
SPI Clock  
IO  
IO  
IO  
IO  
H26 / AE2 / AE13  
H25 / AG5 / AF11  
E28 / AH5 / AG12  
J26 / AF4 / AH12  
W10 / M24 / AA3  
R10 / M26 / AC3  
F25 / T10 / AD4  
U9 / N24 / AD3  
G24 / Y1 / AD8  
H23 / AB5 / AD6  
D23 / AB3 / AC6  
K22 / V3 / AC7  
mcspi3_simo  
mcspi3_somi  
mcspi3_cs0  
Slave data in, master data out  
Slave data out, master data in  
SPI Enable 0, polarity configured by  
software  
mcspi3_cs1  
SPI Enable 1, polarity configured by  
software  
O
AC27 / AG4 / AH14  
AC25 / U10 / AD2  
V21 / W3 / AD9  
MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)  
mcspi4_clk  
SPI Clock  
IO  
IO  
IO  
IO  
Y8 / Y21  
V21  
U19 / H3  
U17  
V7 / W19  
W18  
mcspi4_simo  
mcspi4_somi  
mcspi4_cs0  
Slave data in, master data out  
Slave data out, master data in  
U21  
T20  
Y18  
SPI Enable 0, polarity configured by  
software  
K26  
P20  
AA19  
For more information, see UART/IrDA/CIR / UART/IrDA/CIR Environment section of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-16. Serial Communication Interfaces – UARTs Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)  
uart1_cts  
uart1_rts  
uart1_rx  
uart1_tx  
UART1 Clear To Send  
UART1 Request To Send  
UART1 Receive data  
UART1 Transmit data  
I
AG22 / W8 / T21  
AH22 / AA9  
AE21 / T19 / W2  
AE22 / R2  
AC19 / AC2 / AA18  
W6 / AB19  
O
I
F28 / Y8 / AE7  
E26 / AA8  
H3 / H25 / AE4  
L4 / G26  
E23 / V7 / AC3  
D24 / W7  
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)  
uart2_cts  
uart2_rts  
uart2_rx  
uart2_tx  
UART2 Clear To Send  
UART2 Request To Send  
UART2 Receive data  
UART2 Transmit data  
I
AF6 / AB26 / U26  
AE6 / AB25 / U27  
AE5 / AD25/ U28  
AF5 / AA25/ T27  
Y24/ P3/ W20  
AA24/ N3/ V18  
W3/ AD21/ Y20  
U3/AD22/V20  
V6/ U23  
V5/ U24  
T23/ V4  
T24/ W4  
O
I
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA  
uart3_cts_rctx  
UART3 Clear To Send (input),  
Remote TX (output)  
IO  
H18 / U26  
W20 / F23  
A23 / U23  
uart3_rts_sd  
uart3_rx_irrx  
UART3 Request To Send, IR enable  
O
I
H19 / U27  
V18 / F24  
B23 / U24  
UART3 Receive data, IR and  
Remote RX  
AG24 / H20 / U28 / F27  
AD23 / Y20 / H24/ H26  
AD21 / B24 / T23 / E24  
uart3_tx_irtx  
UART3 Transmit data, IR TX  
O
AH24 / H21 / T27/ G26  
AD24 / V20 / J29 / G24  
AC21 / C23 / T24/ F23  
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4) / IrDA  
uart4_rx  
uart4_tx  
UART4 Receive data  
UART4 Transmit data  
I
J8  
C6  
B3  
NA  
NA  
O
K8  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
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For more information, see High-Speed USB Host Subsystem and High-Speed USB OTG Controller /  
High-Speed USB Host Subsystem / High-Speed USB Host Subsystem Environment section of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-17. Serial Communication Interfaces – USB Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
)
HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0)  
hsusb0_clk  
hsusb0_stp  
hsusb0_dir  
Dedicated for external transceiver 60-MHz clock input to PHY  
I
O
I
T28  
T25  
R28  
W19  
U20  
V19  
R21  
R23  
P23  
Dedicated for external transceiver Stop signal  
Dedicated for external transceiver Data direction control from  
PHY  
hsusb0_nxt  
Dedicated for external transceiver Next signal from PHY  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
I
T26  
T27  
U28  
U27  
U26  
U25  
W18  
V20  
Y20  
V18  
W20  
W17  
R22  
T24  
T23  
U24  
U23  
W24  
hsusb0_data0  
hsusb0_data1  
hsusb0_data2  
hsusb0_data3  
hsusb0_data4  
IO  
IO  
IO  
IO  
IO  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
hsusb0_data5  
hsusb0_data6  
hsusb0_data7  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
IO  
IO  
IO  
V28  
V27  
V26  
Y18  
Y19  
Y17  
V23  
W23  
T22  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
MM_FSUSB3  
mm3_rxdm  
mm3_rxdp  
mm3_rxrcv  
mm3_txse0  
mm3_txdat  
mm3_txen_n  
MM_FSUSB2  
mm2_rxdm  
mm2_rxdp  
mm2_rxrcv  
mm2_txse0  
mm2_txdat  
mm2_txen_n  
MM_FSUSB1  
mm1_rxdm  
mm1_rxdp  
mm1_rxrcv  
mm1_txse0  
mm1_txdat  
mm1_txen_n  
HSUSB2  
Vminus receive data (not used in 3- or 4-pin configurations)  
Vplus receive data (not used in 3- or 4-pin configurations)  
Differential receiver signal input (not used in 3-pin mode)  
Single-ended zero. Used as VM in 4-pin VP_VM mode.  
USB data. Used as VP in 4-pin VP_VM mode.  
Transmit enable  
IO  
IO  
IO  
IO  
IO  
IO  
AE3  
AH3  
AD1  
AE1  
AD2  
AC1  
K3  
M3  
U4  
V3  
R3  
T3  
NA(2)  
NA(2)  
NA  
NA  
NA  
NA  
Vminus receive data (not used in 3- or 4-pin configurations)  
Vplus receive data (not used in 3- or 4-pin configurations)  
Differential receiver signal input (not used in 3-pin mode)  
Single-ended zero. Used as VM in 4-pin VP_VM mode.  
USB data. Used as VP in 4-pin VP_VM mode.  
Transmit enable  
IO  
IO  
IO  
IO  
IO  
IO  
AH7  
AF7  
AG8  
AH8  
AB2  
V3  
AF7  
AF6  
AF9  
AE9  
T8  
AD11  
AC9  
AC11  
AD12  
R5  
V9  
M4  
Vminus receive data (not used in 3- or 4-pin configurations)  
Vplus receive data (not used in 3- or 4-pin configurations)  
Differential receiver signal input (not used in 3-pin mode)  
Single-ended zero. Used as VM in 4-pin VP_VM mode.  
USB data. Used as VP in 4-pin VP_VM mode.  
Transmit enable  
IO  
IO  
IO  
IO  
IO  
IO  
AG9  
AF10  
AF11  
AG12  
AH12  
AH14  
V2  
AD5  
AC1  
AD6  
AC6  
AC7  
AD9  
AB2  
AC3  
AD4  
AD3  
AD2  
hsusb2_clk  
hsusb2_stp  
hsusb2_dir  
Dedicated for external transceiver 60-MHz clock input to PHY  
Dedicated for external transceiver Stop signal  
O
O
I
AE7  
AF7  
AG7  
AE4  
AF6  
AE6  
AC3  
AC9  
Dedicated for external transceiver Data direction control from  
PHY  
AC10  
hsusb2_nxt  
Dedicated for external transceiver Next signal from PHY  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
I
AH7  
AG8  
AH8  
AF7  
AF9  
AE9  
AD11  
AC11  
AD12  
hsusb2_data0  
hsusb2_data1  
IO  
IO  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
(2) This pin is not supported on the CUS package.  
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Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(1  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
)
hsusb2_data2  
hsusb2_data3  
hsusb2_data4  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
IO  
IO  
IO  
AB2  
V3  
T8  
V9  
R5  
M4  
N4  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
Y2  
W8  
hsusb2_data5  
hsusb2_data6  
hsusb2_data7  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
IO  
IO  
IO  
Y3  
Y4  
U8  
V8  
N3  
M5  
N5  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
AA3  
W7  
HSUSB1  
hsusb1_clk  
hsusb1_stp  
hsusb1_dir  
Dedicated for external transceiver 60-MHz clock input to PHY  
Dedicated for external transceiver Stop signal  
O
O
I
AE10  
AF10  
AF9  
AB3  
AB2  
AA4  
AD3  
AC1  
AC4  
Dedicated for external transceiver data direction control from  
PHY  
hsusb1_nxt  
Dedicated for external transceiver Next signal from PHY  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
Dedicated for external transceiver Bidirectional data bus  
I
AG9  
AF11  
AG12  
AH12  
AH14  
AE11  
V2  
AD5  
AD6  
AC6  
AC7  
AD9  
AC5  
hsusb1_data0  
hsusb1_data1  
hsusb1_data2  
hsusb1_data3  
hsusb1_data4  
IO  
IO  
IO  
IO  
IO  
AC3  
AD4  
AD3  
AD2  
Y3  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
hsusb1_data5  
hsusb1_data6  
hsusb1_data7  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
IO  
IO  
IO  
AH9  
AF13  
AE13  
AB1  
AE3  
AA3  
AD2  
AC8  
AD8  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
Dedicated for external transceiver Bidirectional data bus  
additional signals for 12-pin ULPI operation  
102  
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2.5.4 Removable Media Interfaces  
For more information, see MMC/SDIO Card Interface / MMC/SDIO Environment section of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-18. Removable Media Interfaces – MMC/SDIO Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOMa  
(CUS Pkg.)  
)
MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)  
mmc1_clk  
MMC/SD Output Clock  
IO  
O
N28  
M27  
N27  
N26  
N25  
P28  
N19  
L18  
M23  
L23  
mmc1_cmd  
mmc1_dat0  
mmc1_dat1  
mmc1_dat2  
mmc1_dat3  
MMC/SD command signal  
MMC/SD Card Data bit 0 / SPI Serial Input  
MMC/SD Card Data bit 1  
IO  
IO  
IO  
IO  
M19  
M18  
K18  
N20  
M22  
M21  
M20  
N23  
MMC/SD Card Data bit 2  
MMC/SD Card Data bit 3  
MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)  
mmc2_clk  
MMC/SD Output Clock  
IO  
O
AE2  
AE4  
W10  
V10  
Y1  
mmc2_dir_dat0  
Direction control for DAT0 signal case an external  
transceiver used  
AB2  
mmc2_dir_dat1  
mmc2_dir_dat2  
mmc2_dir_dat3  
Direction control for DAT1 and DAT3 signals case an  
external transceiver used  
O
O
O
AH3  
AF19  
AE21  
M3  
E4  
G3  
AA2  
AC17  
AB16  
Direction control for DAT2 signal case an external  
transceiver used  
Direction control for DAT4, DAT5, DAT6, and DAT7  
signals case an external transceiver used  
mmc2_clkin  
mmc2_dat0  
mmc2_dat1  
mmc2_dat2  
mmc2_dat3  
mmc2_dat4  
mmc2_dat5  
mmc2_dat6  
mmc2_dat7  
mmc2_dir_cmd  
MMC/SD input Clock  
I
AE3  
AH5  
K3  
T10  
AA1  
AB3  
MMC/SD Card Data bit 0  
MMC/SD Card Data bit 1  
MMC/SD Card Data bit 2  
MMC/SD Card Data bit 3  
MMC/SD Card Data bit 4  
MMC/SD Card Data bit 5  
MMC/SD Card Data bit 6  
MMC/SD Card Data bit 7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
AH4  
T9  
Y3  
AG4  
U10  
W3  
AF4  
U9  
V3  
AE4 / AB3  
AH3 / AB4  
AF3 / AA4  
AE3 / AC2  
AF3  
P9 / V10  
M3/P8  
L3/P7  
K3/R7  
L3  
AB2 / T5  
AA2 / R4  
Y2 / T4  
AA1 / T6  
Y2  
Direction control for CMD signal case an external  
transceiver is used  
mmc2_cmd  
MMC/SD command signal  
O
AG5  
R10  
AB5  
MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)  
mmc3_clk  
MMC/SD Output Clock  
IO  
O
AB1 / AF10  
AC3 / AE10  
AE4 / AE11  
AH3 / AH9  
AF3 / AF13  
AE3 / AE13  
AF11  
R9 / AB2  
R8 / AB3  
V10 / Y3  
M3/AB1  
L3/AE3  
K3/AA3  
AC3  
AC1  
AD3  
mmc3_cmd  
mmc3_dat0  
mmc3_dat1  
mmc3_dat2  
mmc3_dat3  
mmc3_dat4  
mmc3_dat5  
mmc3_dat6  
mmc3_dat7  
MMC/SD command signal  
MMC/SD Card Data bit 0 / SPI Serial Input  
MMC/SD Card Data bit 1  
MMC/SD Card Data bit 2  
MMC/SD Card Data bit 3  
MMC/SD Card Data bit 4  
MMC/SD Card Data bit 5  
MMC/SD Card Data bit 6  
MMC/SD Card Data bit 7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AB2 / AC5  
AA2 / AD2  
Y2 / AC8  
AA1 / AD8  
AD6  
AG9  
V2  
AD5  
AF9  
AA4  
AC4  
AH14  
AD2  
AD9  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
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2.5.5 Test Interfaces  
Table 2-19. Test Interfaces – ETK Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
etk_ctl  
etk_clk  
etk_d0  
etk_d1  
etk_d2  
etk_d3  
etk_d4  
etk_d5  
etk_d6  
etk_d7  
etk_d8  
etk_d9  
etk_d10  
etk_d11  
etk_d12  
etk_d13  
etk_d14  
etk_d15  
ETK trace ctl  
ETK trace clock  
ETK data 0  
ETK data 1  
ETK data 2  
ETK data 3  
ETK data 4  
ETK data 5  
ETK data 6  
ETK data 7  
ETK data 8  
ETK data 9  
ETK data 10  
ETK data 11  
ETK data 12  
ETK data 13  
ETK data 14  
ETK data 15  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AE10  
AF10  
AF11  
AG12  
AH12  
AE13  
AE11  
AH9  
AB3  
AB2  
AC3  
AD4  
AD3  
AA3  
Y3  
AD3  
AC1  
AD6  
AC6  
AC7  
AD8  
AC5  
AB1  
AE3  
AD2  
AA4  
V2  
AD2  
AF13  
AH14  
AF9  
AC8  
AD9  
AC4  
AG9  
AE7  
AD5  
AE4  
AF6  
AE6  
AF7  
AF9  
AE9  
AC3  
AF7  
AC9  
AG7  
AH7  
AC10  
AD11  
AC11  
AD12  
AG8  
AH8  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
Table 2-20. Test Interfaces – JTAG Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
jtag_ntrst  
jtag_tck  
jtag_rtck  
Test Reset  
Test Clock  
I
I
AA17  
AA13  
AA12  
U15  
V14  
W13  
AB7  
AB6  
AA7  
ARM Clock  
Emulation  
O
jtag_tms_tmsc  
jtag_tdi  
Test Mode Select  
Test Data Input  
Test Data Output  
Test emulation 0  
Test emulation 1  
IO  
I
AA18  
AA20  
AA19  
AA11  
AA10  
V15  
U16  
Y13  
Y15  
Y14  
AA9  
AB10  
AB9  
jtag_tdo  
O
IO  
IO  
jtag_emu0  
jtag_emu1  
AC24  
AD24  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
104  
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Table 2-21. Test Interfaces – SDTI Signals Description  
SIGNAL  
NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
SUBSYSTEM  
SIGNAL  
MULTIPLEXING(2)  
sdti_clk  
sdti_txd0  
sdti_txd1  
sdti_txd2  
sdti_txd3  
Serial clock dual edge  
O
O
O
O
O
AF7 / AA11 / AG8  
AG7 / AA10 / AA11  
AH7 / AA10  
AG8  
AF6 / Y15 / AF9  
AE6 / Y14 / Y15  
AF7 / Y14  
AF9  
AC9 / AC24 / AC11  
etk_d11 / jtag_emu0 /  
etk_d14  
Serial data out (System Trace  
messages)  
AC10 / AD24 /  
AC24  
etk_d12 / jtag_emu1 /  
jtag_emu0  
Serial data out (System Trace  
messages)  
AD11 / AD24  
etk_d13 / jtag_emu1  
Serial data out (System Trace  
messages)  
AC11  
etk_d14  
Serial data out (System Trace  
messages)  
AH8  
AE9  
AD12  
etk_d15  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-4  
Table 2-22. Test Interfaces – HWDBG Signals Description  
SIGNAL NAME  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
hw_dbg0  
hw_dbg1  
hw_dbg2  
hw_dbg3  
hw_dbg4  
hw_dbg5  
hw_dbg6  
hw_dbg7  
hw_dbg8  
hw_dbg9  
hw_dbg10  
hw_dbg11  
hw_dbg12  
hw_dbg13  
hw_dbg14  
hw_dbg15  
hw_dbg16  
hw_dbg17  
Debug signal 0  
Debug signal 1  
Debug signal 2  
Debug signal 3  
Debug signal 4  
Debug signal 5  
Debug signal 6  
Debug signal 7  
Debug signal 8  
Debug signal 9  
Debug signal 10  
Debug signal 11  
Debug signal 12  
Debug signal 13  
Debug signal 14  
Debug signal 15  
Debug signal 16  
Debug signal 17  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A24 / AF10  
A23 / AE10  
C27/ AF11  
C23 / AG12  
B24 / AH12  
C24 / AE13  
D24 / AE11  
A25 / AH9  
B25 / AF13  
C26 / AH14  
B23 / AF9  
D25 / AG9  
D28 / AE7  
D26 / AF7  
E26 / AG7  
F28 / AH7  
F27 / AG8  
G26 / AH8  
C23/AB2  
D23/AB3  
C26/AC3  
B23/AD4  
A24/AD3  
B24/AA3  
D24/Y3  
AC1/A22  
AD3/E18  
AD6/J19  
AC6/H24  
AC7/G19  
AD8/F19  
AC5/G20  
AD2/B21  
AC8/F21  
AD9/G21  
AC4/F18  
AD5/J20  
AC3/G22  
AC9/E22  
AC10/D24  
AD11/E23  
AC11/E24  
AD12/F23  
C24/AB1  
D25/AE3  
E26/AD2  
A23/AA4  
D26/V2  
G25/AE4  
K24/AF6  
G26/AE6  
H25/AF7  
H26/AF9  
J26/AE9  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
2.5.6 Miscellaneous  
For more information, see Timers / GP Timers / GP Timers Environment section of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-23. Miscellaneous – GP Timer Signals Description  
SIGNAL NAME  
gpt_8_pwm_evt  
gpt_9_pwm_evt  
gpt_10_pwm_evt  
gpt_11_pwm_evt  
DESCRIPTION  
TYPE(1)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
PWM or event for GP  
timer 8  
IO  
N8 / AD25 / V3  
T8 / AB26 / Y2  
R8 / AB25 / Y3  
P8 / AA25 / Y4  
C5 / AD21/ V9  
B4 / W8 / Y24  
C4 / U8 / AA24  
B5 / V8 / AD22  
G4/ M4  
F4 / N4  
G5 / N3  
F3 / M5  
PWM or event for GP  
timer 9  
IO  
PWM or event for GP  
timer 10  
IO  
PWM or event for GP  
timer 11  
IO  
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
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2.5.7 General-Purpose IOs  
For more information, see General-Purpose Interface / General-Purpose Interface Environment section of  
the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-24. General-Purpose IOs Signals Description(1)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
gpio_0  
gpio_1  
General-purpose IO 0  
General-purpose IO 1  
General-purpose IO 2  
General-purpose IO 3  
General-purpose IO 4  
General-purpose IO 5  
General-purpose IO 6  
General-purpose IO 7  
General-purpose IO 8  
General-purpose IO 9  
General-purpose IO 10  
General-purpose IO 11  
General-purpose IO 12  
General-purpose IO 13  
General-purpose IO 14  
General-purpose IO 15  
General-purpose IO 16  
General-purpose IO 17  
General-purpose IO 18  
General-purpose IO 19  
General-purpose IO 20  
General-purpose IO 21  
General-purpose IO 22  
General-purpose IO 23  
General-purpose IO 24  
General-purpose IO 25  
General-purpose IO 26  
General-purpose IO 27  
General-purpose IO 28  
General-purpose IO 29  
General-purpose IO 30  
General-purpose IO 31  
General-purpose IO 34  
General-purpose IO 35  
General-purpose IO 36  
General-purpose IO 37  
General-purpose IO 38  
General-purpose IO 39  
General-purpose IO 40  
General-purpose IO 41  
General-purpose IO 42  
General-purpose IO 43  
General-purpose IO 44  
General-purpose IO 45  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AF26  
AF25  
AH26  
AG26  
AE14  
AF18  
AF19  
AE21  
AF21  
AF22  
AG25  
AA11  
AF10  
AE10  
AF11  
AG12  
AH12  
AE13  
AE11  
AH9  
AF13  
AH14  
AF9  
AG9  
AE7  
AF7  
AG7  
AH7  
AG8  
AH8  
AF24  
AA10  
N4  
V16  
W15  
F3  
W16  
Y13  
AB12  
AC16  
AD17  
AD18  
AC17  
AB16  
AA15  
AD23  
Y7  
gpio_2  
gpio_3  
D3  
gpio_4  
C3  
gpio_5  
E3  
gpio_6  
E4  
gpio_7  
G3  
gpio_8  
D4  
gpio_9  
V12  
AE14  
Y15  
AB2  
AB3  
AC3  
AD4  
AD3  
AA3  
Y3  
gpio_10  
gpio_11  
gpio_12  
gpio_13  
gpio_14  
gpio_15  
gpio_16  
gpio_17  
gpio_18  
gpio_19  
gpio_20  
gpio_21  
gpio_22  
gpio_23  
gpio_24  
gpio_25  
gpio_26  
gpio_27  
gpio_28  
gpio_29  
gpio_30  
gpio_31  
gpio_34  
gpio_35  
gpio_36  
gpio_37  
gpio_38  
gpio_39  
gpio_40  
gpio_41  
gpio_42  
gpio_43  
gpio_44  
gpio_45  
AC24  
AC1  
AD3  
AD6  
AC6  
AC7  
AD8  
AC5  
AD2  
AC8  
AD9  
AC4  
AD5  
AC3  
AC9  
AC10  
AD11  
AC11  
AD12  
Y10  
AD24  
K4  
AB1  
AE3  
AD2  
AA4  
V2  
AE4  
AF6  
AE6  
AF7  
AF9  
AE9  
AD7  
Y14  
J2  
M4  
H1  
K3  
L4  
H2  
K2  
K4  
G2  
J4  
T3  
F1  
J3  
R3  
F2  
J2  
N3  
E1  
J1  
M3  
E2  
H1  
L3  
D1  
H2  
K3  
D2  
G2  
H2  
V1  
R2  
K2  
Y1  
T2  
(1) NA in table stands for "Not Applicable".  
(2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
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Table 2-24. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
gpio_46  
gpio_47  
gpio_48  
gpio_49  
gpio_50  
gpio_51  
gpio_52  
gpio_53  
gpio_54  
gpio_55  
gpio_56  
gpio_57  
gpio_58  
gpio_59  
gpio_60  
gpio_61  
gpio_62  
gpio_63  
gpio_64  
gpio_65  
gpio_66  
gpio_67  
gpio_68  
gpio_69  
gpio_70  
gpio_71  
gpio_72  
gpio_73  
gpio_74  
gpio_75  
gpio_76  
gpio_77  
gpio_78  
gpio_79  
gpio_80  
gpio_81  
gpio_82  
gpio_83  
gpio_84  
gpio_85  
gpio_86  
gpio_87  
gpio_88  
gpio_89  
gpio_90  
gpio_91  
gpio_92  
gpio_93  
gpio_94  
gpio_95  
gpio_96  
General-purpose IO 46  
General-purpose IO 47  
General-purpose IO 48  
General-purpose IO 49  
General-purpose IO 50  
General-purpose IO 51  
General-purpose IO 52  
General-purpose IO 53  
General-purpose IO 54  
General-purpose IO 55  
General-purpose IO 56  
General-purpose IO 57  
General-purpose IO 58  
General-purpose IO 59  
General-purpose IO 60  
General-purpose IO 61  
General-purpose IO 62  
General-purpose IO 63  
General-purpose IO 64  
General-purpose IO 65  
General-purpose IO 66  
General-purpose IO 67  
General-purpose IO 68  
General-purpose IO 69  
General-purpose IO 70  
General-purpose IO 71  
General-purpose IO 72  
General-purpose IO 73  
General-purpose IO 74  
General-purpose IO 75  
General-purpose IO 76  
General-purpose IO 77  
General-purpose IO 78  
General-purpose IO 79  
General-purpose IO 80  
General-purpose IO 81  
General-purpose IO 82  
General-purpose IO 83  
General-purpose IO 84  
General-purpose IO 85  
General-purpose IO 86  
General-purpose IO 87  
General-purpose IO 88  
General-purpose IO 89  
General-purpose IO 90  
General-purpose IO 91  
General-purpose IO 92  
General-purpose IO 93  
General-purpose IO 94  
General-purpose IO 95  
General-purpose IO 96  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
P1  
R1  
T1  
U2  
U1  
R3  
R2  
U1  
T3  
T2  
P1  
U2  
W1  
L2  
V1  
Y1  
M2  
V2  
H3  
AD1  
A3  
NA  
V8  
NA  
U8  
B6  
D2  
T8  
B4  
F4  
R8  
C4  
G5  
P8  
B5  
F3  
N8  
C5  
G4  
T4  
N1  
W2  
G3  
K2  
K5  
U3  
J1  
L1  
H1  
AC6  
AC8  
B3  
E1  
L8  
NA  
K8  
NA  
J8  
C6  
C2  
D28  
D26  
D27  
E27  
AG22  
AH22  
AG23  
AH23  
AG24  
AH24  
E26  
F28  
F27  
G26  
AD28  
AD27  
AB28  
AB27  
AA28  
AA27  
G25  
H27  
H26  
H25  
E28  
J26  
G25  
K24  
M25  
F26  
AE21  
AE22  
AE23  
AE24  
AD23  
AD24  
G26  
H25  
H26  
J26  
G22  
E22  
F22  
J21  
AC19  
AB19  
AD20  
AC20  
AD21  
AC21  
D24  
E23  
E24  
F23  
AC22  
AC23  
AB22  
Y22  
W22  
V22  
J22  
G23  
G24  
H23  
D23  
K22  
V21  
W21  
A22  
E18  
B22  
AC26  
AD26  
AA25  
Y25  
AA26  
AB26  
L25  
L26  
M24  
M26  
F25  
N24  
AC25  
AB25  
C23  
D23  
C25  
AC27  
AC28  
A24  
A23  
C25  
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Table 2-24. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
gpio_97  
gpio_98  
General-purpose IO 97  
General-purpose IO 98  
General-purpose IO 99  
General-purpose IO 100  
General-purpose IO 101  
General-purpose IO 102  
General-purpose IO 103  
General-purpose IO 104  
General-purpose IO 105  
General-purpose IO 106  
General-purpose IO 107  
General-purpose IO 108  
General-purpose IO 109  
General-purpose IO 110  
General-purpose IO 111  
General-purpose IO 112  
General-purpose IO 113  
General-purpose IO 114  
General-purpose IO 115  
General-purpose IO 116  
General-purpose IO 117  
General-purpose IO 118  
General-purpose IO 119  
General-purpose IO 120  
General-purpose IO 121  
General-purpose IO 122  
General-purpose IO 123  
General-purpose IO 124  
General-purpose IO 125  
General-purpose IO 126  
General-purpose IO 127  
General-purpose IO 128  
General-purpose IO 129  
General-purpose IO 130  
General-purpose IO 131  
General-purpose IO 132  
General-purpose IO 133  
General-purpose IO 134  
General-purpose IO 135  
General-purpose IO 136  
General-purpose IO 137  
General-purpose IO 138  
General-purpose IO 139  
General-purpose IO 140  
General-purpose IO 141  
General-purpose IO 142  
General-purpose IO 143  
General-purpose IO 144  
General-purpose IO 145  
General-purpose IO 146  
IO  
IO  
I
C27  
C23  
C26  
B23  
J19  
H24  
gpio_99  
AG17  
AH17  
B24  
AE16  
AE15  
A24  
AB18  
AC18  
G19  
gpio_100  
gpio_101  
gpio_102  
gpio_103  
gpio_104  
gpio_105  
gpio_106  
gpio_107  
gpio_108  
gpio_109  
gpio_110  
gpio_111  
gpio_112  
gpio_113  
gpio_114  
gpio_115  
gpio_116  
gpio_117  
gpio_118  
gpio_119  
gpio_120  
gpio_121  
gpio_122  
gpio_123  
gpio_124  
gpio_125  
gpio_126  
gpio_127  
gpio_128  
gpio_129  
gpio_130  
gpio_131  
gpio_132  
gpio_133  
gpio_134  
gpio_135  
gpio_136  
gpio_137  
gpio_138  
gpio_139  
gpio_140  
gpio_141  
gpio_142  
gpio_143  
gpio_144  
gpio_145  
gpio_146  
I
IO  
IO  
IO  
IO  
I
C24  
B24  
F19  
D24  
D24  
G20  
A25  
C24  
B21  
K28  
P25  
L24  
I
L28  
P26  
K24  
I
K27  
N25  
J23  
I
L27  
N26  
K23  
IO  
IO  
IO  
I
B25  
D25  
F21  
C26  
E26  
G21  
B26  
E25  
C22  
AG19  
AH19  
AG18  
AH18  
P21  
AD17  
AD16  
AE18  
AE17  
U18  
NA  
I
NA  
I
NA  
I
NA  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
V20  
N21  
R18  
T21  
R21  
T18  
V19  
M21  
R19  
R20  
N28(3) / T28  
M27(3) / T25  
N27(3) / R28  
N26(3)  
N25(3) / T26  
P28(3) / T27  
D25 / P27(3)  
P26(3)  
R27(3)  
R25(3)  
AE2 / U28  
AG5 / U27  
AH5  
W19 / N19(3)  
U20 / L18(3)  
V19 / M19(3)  
M18(3)  
W18 / K18(3)  
V20 / N20(3)  
M20(3) / D26  
P17(3)  
P18(3)  
P19(3)  
Y20 / W10  
V18 / R10  
T10  
M23(3) / R21  
L23(3) / R23  
M22(3) / P23  
M21(3)  
M20(3)/R22  
N23(3)/T24  
J20 / N22(3)  
NA  
NA  
P24(3)  
Y1 / T23  
AB5 / U24  
AB3  
AH4  
T9  
Y3  
AG4  
U10  
W3  
AF4  
U9  
V3  
AE4  
V10  
AB2  
AH3  
M3  
AA2  
AF3  
L3  
Y2  
AE3  
K3  
AA1  
AF6  
P3  
V6  
AE6  
N3  
V5  
AF5  
U3  
W4  
AE5  
W3  
V4  
AB26  
AB25  
AA25  
Y24  
NA  
AA24  
AD22  
NA  
NA  
(3) The usage of this GPIO is strongly restricted.  
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SPRS685–AUGUST 2010  
Table 2-24. General-Purpose IOs Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL BOTTOM  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
gpio_147  
gpio_148  
gpio_149  
gpio_150  
gpio_151  
gpio_152  
gpio_153  
gpio_154  
gpio_155  
gpio_156  
gpio_157  
gpio_158  
gpio_159  
gpio_160  
gpio_161  
gpio_162  
gpio_163  
gpio_164  
gpio_165  
gpio_166  
gpio_167  
gpio_168  
gpio_169  
gpio_170  
gpio_171  
gpio_172  
gpio_173  
gpio_174  
gpio_175  
gpio_176  
gpio_177  
gpio_178  
gpio_179  
gpio_180  
gpio_181  
gpio_182  
gpio_183  
gpio_184  
gpio_185  
gpio_186  
gpio_188  
gpio_189  
gpio_190  
gpio_191  
General-purpose IO 147  
General-purpose IO 148  
General-purpose IO 149  
General-purpose IO 150  
General-purpose IO 151  
General-purpose IO 152  
General-purpose IO 153  
General-purpose IO 154  
General-purpose IO 155  
General-purpose IO 156  
General-purpose IO 157  
General-purpose IO 158  
General-purpose IO 159  
General-purpose IO 160  
General-purpose IO 161  
General-purpose IO 162  
General-purpose IO 163  
General-purpose IO 164  
General-purpose IO 165  
General-purpose IO 166  
General-purpose IO 167  
General-purpose IO 168  
General-purpose IO 169  
General-purpose IO 170  
General-purpose IO 171  
General-purpose IO 172  
General-purpose IO 173  
General-purpose IO 174  
General-purpose IO 175  
General-purpose IO 176  
General-purpose IO 177  
General-purpose IO 178  
General-purpose IO 179  
General-purpose IO 180  
General-purpose IO 181  
General-purpose IO 182  
General-purpose IO 183  
General-purpose IO 184  
General-purpose IO 185  
General-purpose IO 186  
General-purpose IO 188  
General-purpose IO 189  
General-purpose IO 190  
General-purpose IO 191  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AD25  
AA8  
AA9  
W8  
AD21  
L4  
NA  
W7  
R2  
W6  
W2  
H3  
AC2  
V7  
Y8  
AE1  
AD1  
AD2  
AC1  
Y21  
AA21  
V21  
U21  
T21  
K26  
W21  
H18  
H19  
H20  
H21  
B23  
AF15  
U26  
J25  
V3  
NA  
U4  
NA  
R3  
NA  
T3  
NA  
U19  
V17  
U17  
T20  
T19  
P20  
T17  
F23  
F24  
H24  
G24  
A23  
C2  
W19  
AB20  
W18  
Y18  
AA18  
AA19  
V18  
A23  
B23  
B24  
C23  
F18  
AC15  
U23  
A24  
T5  
W20  
J23  
P9  
AB3  
AB4  
AA4  
AC2  
AC3  
AB1  
AB2  
AA3  
Y2  
P8  
R4  
P7  
T4  
R7  
T6  
R8  
NA  
R9  
NA  
T8  
R5  
W7  
W8  
U8  
N5  
N4  
Y3  
N3  
Y4  
V8  
M5  
V3  
V9  
M4  
AE15  
AF14  
AG14  
AE22  
U25  
V28  
V27  
V26  
C1  
AC14  
AC13  
AC12  
AA6  
W24  
V23  
W23  
T22  
AB4  
AC4  
W11  
W17  
Y18  
Y19  
Y17  
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2.5.8 Power Supplies  
Note: For more information, see Power Reset and Clock Management / PRCM Environment and the  
Power, Reset, and Clock Management / PRCM Functional Description / PRCM Voltage Management  
Functional Description sections of the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
Table 2-25. Power Supplies Signals Description(1)  
SIGNAL NAME  
DESCRIPTION  
BALL BOTTOM  
(CBP Pkg.)  
BALL TOP  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL TOP  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
vdd_mpu_iva  
MPU/IVA power  
supply  
Y9 / W9 / T9 /  
R9 / M9 / L9 / J9  
/ Y10 / U10 / T10  
/ R10 / N10 /  
M10 / L10 / J10 /  
Y11 / W11 / K11  
/ J11 / W12 / K13  
/ Y14 / K14 / J14  
/ Y15 / W15 / J15  
NA  
H7/ N7/ U7/ V7/ N8/  
G9/ L9/ M9/ W9/ Y9/  
M10/ P10/ K11/ U11/  
V11/ Y11/ G12/ D13/  
U13  
NA  
W13/ W12/ V13/  
V12/ U13/ U12/ T8/  
T7/ R8/ R7/ R6/ N8/  
N7/ N6/ M12/ M8/  
M7/ M6/ L12/ L11/  
J10/ J9/ H10/ H9/  
G10/ G9/F10  
vdd_core  
Core power domain  
AC4 / J4 / H4 /  
D8 / AE9 / D9 /  
D15 / Y16 /  
NA  
M7/ T7/ Y8/ G11/  
Y12/ D15/ M17/ G18/  
H20/ R20/ AC21  
NA  
T20/ T19/ T18/ T17/  
R19/ R18/ R17/  
M15/ M14/ L15/  
AE18 / Y18 /  
W18 / K18 / J18 /  
AE19 / Y19 /  
L14/ K19/ K18/ K17/  
J18/ J17/ H13/ H12/  
G13/ G12/ F13/ F12  
U19 / T19 / N19 /  
M19 / J19 / Y20 /  
W20 / V20 / U20  
/ P20 / N20 / K20  
/ J20 / D22 / D23  
/ AE24 / M25 /  
L25 / E25  
cap_vddu_wkup_  
logic  
Decoupling  
AA15  
NA  
NA  
K14  
K13  
NA  
NA  
Y12  
G18  
capacitor for  
WKUP/EMU  
domains (logic)  
vdda_dplls_dll  
Input power for the  
analog part of the  
MPU, CORE  
K15  
DPLLs, IVA, and the  
DLL  
vdda_dac  
vssa_dac  
vdds  
Video DAC power  
plane  
V25  
Y26  
NA  
NA  
NA  
V25  
V24  
NA  
NA  
AB13  
AB15  
Video DAC ground  
plane  
1.8-V power for  
standard IOs  
AD3 / AD4 / W4 /  
AF8 / AE8 /  
AF16 / AE16 /  
AF23 / AE23 /  
F25 / F26 / AG27  
G4/ M4/ T4/ Y4/ L7/  
AC7/ D9/ AE10/ C11/  
J15/ AC15/ A18/ J18/  
AC18/ AD20/ E24/  
L24/ T24/ W24/ AC24  
/ AB24  
A3 / A15 / B5 / F2 /  
F21/ L20 / W21  
Y9 / W10 / W9 / V10  
/ V9 / U10 / N19 /  
N18 / N17 / M19 /  
M18 / M17  
vdds_mem  
Memory IO power  
plane  
U1 / J1 / F1 / J2 / AC5 / P1 / H1 / F23  
F2 / R4 / B5 / A5 / E1 / C23 / A4 / A7  
NA  
NA  
K8 / K7 / K6 / J8 /  
J7 / J6 / H15 / G16 /  
G15 / F16 / F15 /  
E16  
/ AH6 / B8 / A8 /  
B12 / A12 / D16 /  
C16 / B18 / A18 /  
B22 / A22 / G28 /  
C28  
/ A10 / A15 / A18  
vdda_dpll_per  
Input power for the  
analog part of the  
Peripheral DPLLs  
AA16  
NA  
NA  
U14  
NA  
NA  
U17  
vdda_wkup_bg_bb  
For wakeup LDO  
and VDDA (2 LDOs  
SRAM and BG)  
AA14  
W14  
AA13  
(1) NA in this table stands for "Not applicable".  
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Table 2-25. Power Supplies Signals Description (continued)  
SIGNAL NAME  
DESCRIPTION  
BALL BOTTOM  
(CBP Pkg.)  
BALL TOP  
(CBP Pkg.)  
BALL BOTTOM  
(CBC Pkg.)  
BALL TOP  
(CBC Pkg.)  
BALL BOTTOM  
(CUS Pkg.)  
vss  
Ground  
AG2 / U2 / B2 /  
AG3 / W3 / P3 /  
J3 / E3 / A3 / P4 F22 / E2 / C22 / B4 / A6/ D7/ Y7/AE7/ A8/  
/ E4 / AG6 / D7 /  
C7 / V9 / U9 / P9  
/ N9 / K9 / W10 /  
V10 / P10 / K10 /  
D10 / C10 /  
H2 / B18 / AB5 /  
AB14 / AB20 / P2 / H4/ N4/ R4/ W4/ AB5/  
G1/ K1/ R1/ W1/ B2/  
C1/ F1/ H2/ M2/ R2/  
Y6/AA7/ Y11/ AA16/  
W20/P20/ L21/ H20/  
F20/ B14/A13/ A7  
V16/ V15/ U16/  
U15/ U14/ U11/  
U9/T16/ T15/ T14/  
T13/ T12/ T11/ T10/  
T9/ R15/ R14/ R11/  
R10/ P17/ P15/ P14/  
P13/P12/ P11/ P10/  
P8/ N16/ N15/ N14/  
N13/ N12/ N11/  
N10/ N9/ M16/ M13/  
M11/ M10/ M9/ L17/  
L13/ L10/ L8/ K15/  
K14/ K11/ K10/ J16/  
J15/ J14/ J13/ J12/  
J11/H16/ H14/ H11  
B7 / B10 / B15  
G8/ D10/ G10/ L10/  
N10/ Y10/ AC10/  
C12/ D12/A13/ D14/  
AD14/ K15/ Y16/ L17/  
N17/ R17/ D18/  
D20/G20/ E22/ AB22/  
G23/ L23/ T23/ W23/  
B25/ K25/U25/ AD25 /  
Y26  
AF12 / AE12 /  
Y12 / K12 / J12 /  
Y13 / W13 / J13 /  
D13 / C13 / W14  
/ K16 / J16 / W17  
/ K17 / J17 / W19  
/ V19 / R19 / P19  
/ L19 / K19 / D19  
/ C19 / AF20 /  
AE20 / T20 / R20  
/ M20 / L20 / D21  
/ C22 / AC25 /  
Y25 / W25 /  
AC26 / R26 / L26  
/ A26 / G27 / B27  
vdds_sram  
SRAM LDOs  
W16  
K25  
NA  
NA  
U12  
N23  
NA  
NA  
AA12  
N24  
vdds_mmc1  
Input power for  
MMC1 dual voltage  
buffers  
vdds_x  
Power supply for  
P25  
NA  
P23  
NA  
H8  
dual voltage GPIOs  
vss  
Ground  
M28  
AG20  
AG16  
H28  
NA  
NA  
NA  
NA  
NA  
L19  
AD18  
AC16  
L20  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
U8  
vdds  
vss  
IO power plane  
Ground  
vdds  
IO power plane  
cap_vdd_sram_mpu_i Decoupling  
V4  
N9  
va  
capacitor for SRAM  
in processor  
domains  
cap_vdd_sram_core  
Decoupling  
L21  
NA  
K20  
NA  
H17  
capacitor for CORE  
domain (SRAM)  
vdds  
IO power plane  
AG21  
AH20  
NA  
NA  
AD19  
AE19  
NA  
NA  
NA  
cap_vddu_array  
Decoupling  
N20  
capacitor for  
WKUP/EMU  
domains (array)  
vss  
Ground  
AH21  
U4  
NA  
NA  
AC19  
D6  
NA  
NA  
NA  
cap_vdd_bb_mpu_iva Decoupling  
capacitor for  
N21  
processor domains  
(bb)  
sys_xtalgnd  
Kelvin ground  
Y17  
NA  
AF23  
NA  
W15  
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2.5.9 System and Miscellaneous Terminals  
Note: For more information, see the Power, Reset, and Clock Management / PRCM Environment section  
of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 2-26. System and Miscellaneous Signals Description(1)  
SIGNAL NAME  
DESCRIPTION  
TYPE(2)  
BALL  
BOTTOM  
(CBP Pkg.)  
BALL TOP  
(CBP Pkg.)  
BALL  
BOTTOM  
(CBC Pkg.)  
BALL TOP  
(CBC Pkg.)  
BALL  
BOTTOM  
(CUS Pkg.)  
sys_32k  
32-kHz clock input  
I
AE25  
AE17  
NA  
NA  
AE20  
AF19  
NA  
NA  
AA16  
AD15  
sys_xtalin  
Main input clock. Oscillator input or LVCMOS at  
19.2, 13, or 12 MHz.  
AI-I  
sys_xtalout  
sys_altclk  
Output of oscillator  
AO  
I
AF17  
J25  
NA  
NA  
AF20  
J23  
NA  
NA  
AD14  
A24  
Alternate clock source selectable for GPTIMERs  
(maximum 54 MHz), USB (48 MHz), or  
NTSC/PAL (54 MHz)  
sys_clkreq  
Request from device for system clock (open  
source type)  
IO  
AF25  
NA  
W15  
NA  
Y13  
sys_clkout1  
sys_clkout2  
sys_boot0  
sys_boot1  
sys_boot2  
sys_boot3  
sys_boot4  
sys_boot5  
sys_boot6  
Configurable output clock1  
Configurable output clock2  
Boot configuration mode bit 0  
Boot configuration mode bit 1  
Boot configuration mode bit 2  
Boot configuration mode bit 3  
Boot configuration mode bit 4  
Boot configuration mode bit 5  
Boot configuration mode bit 6  
O
AG25  
AE22  
AH26  
AG26  
AE14  
AF18  
AF19  
AE21  
AF21  
AH25  
AF24  
AF26  
AD26  
AE26  
AF22  
U8  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AE14  
W11  
F3  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
AA5  
NA  
NA  
NA  
NA  
NA  
Y7  
O
AA6  
I
AB12  
AC16  
AD17  
AD18  
AC17  
AB16  
AA15  
AA10  
Y10  
I
D3  
I
C3  
I
E3  
I
E4  
I
G3  
I
I
D4  
sys_nrespwron Power On Reset  
V13  
AD7  
V16  
AD15  
W16  
V12  
B6  
sys_nreswarm Warm Boot Reset (open drain output)  
IOD  
I
sys_nirq  
External FIQ input  
W16  
Y16  
sys_nvmode1  
sys_nvmode2  
sys_off_mode  
Indicates the voltage mode  
Indicates the voltage mode  
Indicates the voltage mode  
O
O
O
I
Y15  
AD23  
D2  
sys_ndmareq0 External A request 0 (system expansion). Level  
(active low) or edge (falling) selectable.  
sys_ndmareq1 External A request 1 (system expansion). Level  
(active low) or edge (falling) selectable.  
I
I
I
T8 / J8  
L3 / R8  
K3 / P8  
NA  
NA  
NA  
B4 / C6  
D1 / C4  
D2 / B5  
NA  
NA  
NA  
F4 / C2  
H2 / G5  
G2 / F3  
sys_ndmareq2 External A request 2 (system expansion). Level  
(active low) or edge (falling) selectable.  
sys_ndmareq3 External A request 3 (system expansion). Level  
(active low) or edge (falling) selectable.  
(1) NA in this table stands for "Not applicable".  
(2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog)  
Table 2-27. CBC Package Feed-Through Balls  
(1)  
JEDEC 14x14mm, 0.65mm,  
152ball  
JEDEC DESCRIPTION  
BALL TOP  
BALL BOTTOM  
FEED-THROUGH BALL  
NAME  
NC  
No Connect  
DDR Supply  
No Connect  
Flash Supply  
Flash Supply  
No Connect  
No Connect  
Flash Supply  
Flash Supply  
A1  
A1  
pop_a1_a1  
pop_j1_l1  
NC  
d-vdd  
NC  
J1  
L1  
AA1  
N2  
T2  
AF1  
T2  
f-vdd  
f-vdd  
NC  
pop_n2_t2  
pop_t2_y2  
pop_w2_ae2  
pop_y2_af4  
pop_aa6_af5  
pop_y7_af8  
Y2  
W2  
Y2  
AE2  
AF4  
AF5  
AF8  
NC  
f-vdd  
f-vdd  
AA6  
Y7  
(1) For more details on the feedthrough pin connections, please refer to the PoP memory datasheet.  
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Table 2-27. CBC Package Feed-Through Balls (continued)  
NC, Int  
No Connect; Interrupt when  
using OneNAND POP  
Y9  
AF10  
pop_y9_af10  
f-nbe0, cle0  
d-vdd  
No Connect/CLE  
AA10  
AA11  
AF12  
AF13  
pop_aa10_af12  
pop_aa11_af13  
DDR Supply/ POP FLASH  
vpp supply  
d-tq  
No Connect/ DDR die  
temperature sensor  
AA12  
AF14  
pop_aa12_af14  
vss  
Shared Ground  
DDR Supply  
DDR Supply  
DDR Supply  
Shared Ground  
DDR Supply  
Shared Ground  
DDR Supply  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
DDR Supply  
DDR Supply  
No Connect  
No Connect  
AA13  
Y14  
AF15  
AF17  
AF16  
A20  
pop_aa13_af15  
pop_y14_af17  
pop_aa14_af16  
pop_b16_a20  
pop_y17_af21  
pop_aa17_af18  
pop_y19_af24  
pop_aa19_af22  
pop_a20_a25  
pop_y20_ae25  
pop_aa20_af25  
pop_a21_a26  
pop_b21_b26  
pop_h21_k26  
pop_p21_u26  
pop_y21_ae26  
pop_aa21_af26  
d-vdd  
d-vddq  
d-vdd  
vss  
AA14  
B16  
Y17  
AF21  
AF18  
AF24  
AF22  
A25  
d-vdd  
vss  
AA17  
Y19  
d-vddq  
NC  
AA19  
A20  
NC  
Y20  
AE25  
AF25  
A26  
NC  
AA20  
A21  
NC  
NC  
B21  
B26  
d-vdd  
d-vdd  
NC  
H21  
K26  
P21  
U26  
Y21  
AE26  
AF26  
NC  
AA21  
Table 2-28. CBP Package Feed-Through Balls  
(1)  
JEDEC 12x12, 0.5mm,  
168ball  
JEDEC DESCRIPTION  
BALL TOP  
BALL BOTTOM  
FEED-THROUGH BALL  
NAME  
d-vdd  
d-vdd  
d-vdd  
d-vdd  
d-vdd  
f-vdd  
DDR Supply  
DDR Supply  
DDR Supply  
DDR Supply  
DDR Supply  
Flash Supply  
Flash Supply  
Flash Supply  
Flash Supply  
Flash Supply  
Flash vpp supply  
A12  
AA23  
H23  
K1  
A15  
pop_a12_a15  
pop_aa23_ae28  
pop_h23_af28  
pop_k1_j28  
AE28  
AF28  
J28  
Y23  
AA1  
AC8  
AC13  
L1  
M1  
pop_y23_m1  
pop_aa1_aa1  
pop_ac8_af1  
pop_ac13_ah10  
pop_l1_ah15  
pop_u1_n1  
AA1  
AF1  
f-vdd  
f-vdd  
AH10  
AH15  
N1  
f-vdd  
f-vdd  
U1  
f-vpp  
AC11  
AB9  
AH13  
AG11  
pop_ac11_ah13  
pop_ab9_ag11  
NC, int0  
No Connect/PoP OneNAND  
interrupt  
NC, int1  
No Connect/PoP OneNAND  
interrupt  
AC9  
AH11  
pop_ac9_ah11  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
A1  
A1  
NC  
A2  
A2  
NC  
A22  
A23  
AB1  
AB23  
AC1  
AC2  
AC22  
AC23  
A27  
A28  
AG1  
AG28  
AH1  
AH2  
AH27  
AH28  
pop_a22_a27  
pop_a23_a28  
pop_ab1_ag1  
pop_ab23_ag28  
pop_ac1_ah1  
pop_ac2_ah2  
pop_ac22_ah27  
pop_ac23_ah28  
(1) For more details on the feedthrough pin connections, please refer to the PoP memory datasheet.  
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Table 2-28. CBP Package Feed-Through Balls (continued)  
NC  
No Connect  
B1  
B1  
NC  
NC  
No Connect  
B23  
AB11  
AC14  
AA2  
U2  
B28  
AG13  
AH16  
AA2  
AF2  
AF27  
AG10  
AG15  
B15  
J27  
pop_b23_b28  
pop_ab11_ag13  
pop_ac14_ah16  
pop_aa2_aa2  
pop_u2_af2  
f-rst#, rp#  
d-tq  
vss  
Flash reset  
DDR temperature alert  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
Shared Ground  
vss  
vss  
AA22  
AB8  
AB13  
B12  
H22  
K2  
pop_aa22_af27  
pop_ab8_ag10  
pop_ab13_ag15  
pop_b12_b15  
pop_h22_j27  
pop_k2_m2  
vss  
vss  
vss  
vss  
vss  
M2  
vss  
K22  
L2  
M26  
N2  
pop_k22_m26  
pop_l2_n2  
vss  
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3 Electrical Characteristics  
NOTE  
For more information, see the Power Reset and Clock Management / PRCM Environment  
section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
3.1 Absolute Maximum Ratings  
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.  
These are stress ratings only, and functional operation of the device at these or any other conditions  
beyond those listed under "Recommended Operating Conditions" is not implied. Exposure to absolute  
maximum rated conditions for extended periods may affect device reliability.  
Table 3-1. Absolute Maximum Rating over Junction Temperature Range  
PARAMETER  
MIN  
–0.5  
–0.5  
–0.5  
MAX  
1.5  
UNIT  
vdd_mpu_iva  
vdd_core  
Supply voltage range for MPU / IVA domain  
Supply voltage range for core domain  
V
V
V
1.5  
vdda_wkup_bg_bb  
Supply voltage range for wake-up domain (internal  
LDO)  
2.6  
vdda_dplls_dll  
vdda_dpll_per  
vdds_sram  
vdda_dac  
Supply voltage for MPU, IVA, Core DPLLs, and DLL  
Supply voltage for DPLLs (peripherals)  
Supply voltage for SRAM LDOs  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
-0.5  
–0.5  
-0.5  
-0.5  
-0.5  
–0.5  
–0.5  
TBD  
>250  
–20  
2.1  
V
V
V
V
V
V
V
2.1  
2.6  
Supply voltage for video buffers and DAC  
Supply voltage for 1.8-V I/O macros  
Supply voltage for memory buffers  
2.10  
2.45  
2.45  
2.45  
3.80  
3.80  
3.80  
2.45  
3.80  
2.10  
2.45  
vdds  
vdds_mem  
vdds_mmc1  
Supply voltage range for mmc1  
dual voltage IOs  
1.8-V mode  
3.0-V mode  
1.8-V mode  
3.0-V mode  
1.8-V mode  
3.0-V mode  
vdds_x  
VPAD  
Supply voltage range for dual  
voltage GPIOs  
V
V
mmc1  
Video DAC  
V
V
V
The other balls  
VESD  
ESD stress  
voltage(1)  
HBM (Human Body Model)(2)  
CDM (Charged Device Model)(3)  
Iclamp  
Clamp current for an input or output  
Storage temperature range  
20  
mA  
°C  
(4)  
TSTG  
–65  
150  
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.  
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows  
safe manufacturing with a standard ESD control process. Pins listed as 1000V may actually have higher performance.  
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe  
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.  
(4) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. It is recommended  
returning to ambient room temperature before usage.  
Table 3-2 summarizes the power consumption at the ball level.  
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(3)  
Table 3-2. Maximum Current Ratings at Ball Level  
PARAMETER  
DESCRIPTION  
DM3730  
MAX  
UNIT  
mA  
SIGNAL  
vdd_mpu_iva(1)  
Maximum current rating for MPU / IVA Processors  
domain  
1400(4)  
1400(4)  
300  
230  
60  
DM3725  
vdd_core(1)  
Maximum current rating for core  
domain  
Core  
DM3730  
DM3725  
mA  
vdds  
Maximum current rating for 1.8-V I/O macros  
Maximum current rating for memory buffers  
mA  
mA  
mA  
mA  
mA  
vdds_mem  
vdds_mmc1(2)  
vdds_x  
35  
Maximum current rating for mmc1 dual voltage buffers  
Maximum current rating for GPIO dual voltage buffers  
20  
2
vdda_wkup_bg_b Maximum current rating for wake-up, bandgap and VBB LDOs  
b
5
vdda_dac  
Maximum current rating for video buffers and DAC  
Maximum current rating for MPU, IVA, core DPLLs and DLL  
Maximum current rating for DPLLs (peripherals)  
Maximum current rating for SRAM LDOs (common)  
60  
30  
10  
41  
mA  
mA  
mA  
mA  
vdda_dplls_dll  
vdda_dpll_per  
vdds_sram  
(1) With SmartReflexTM enabled.  
(2) MMC card and I/O card are not included.  
(3) The maximum current ratings documented in this table are preliminary data which are subject to change.  
(4) Conditions used for maximum current ratings:  
–
–
–
TJ is picked up at 90C  
Cold process is used  
VDD1 (vdd_mpu_iva) supplies 1.38 V  
In these conditions, the current listed as 1400mV is the addition of the:  
–
–
Current when running Dhrystone on ARM@1GHz multiplied by a factor x1.5 (to take care of NEON activity)  
Current when running H.264 on IVA@800MHz with a x1.1 factor (to take care of more aggressive SW than H.264)  
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3.2 Recommended Operating Conditions  
The device is used under the recommended operating conditions described in Table 3-4. The POH  
information in Table 3-3 is provided solely for your convenience and does not extend or modify the  
warranty provided under TI’s standard terms and conditions for TI semiconductor products.  
Table 3-3. Reliability Data  
JUNCTION TEMP  
@105C  
TOTAL DEVICE LIFETIME  
89K POH  
>OPP130 MAX TIME  
Not available  
45K  
OPP1G MAX TIME  
Not available  
25K(1)  
@90C  
100K POH  
@75C  
>100K POH  
100K POH  
75K  
(1) If device is only operated at OPP1G, then POH can be extended to 35K POH.  
NOTE  
Logic functions and parameter values are not assured out of the range specified in the  
recommended operating conditions.  
Table 3-4. Recommended Operating Conditions  
PARAMETER  
DESCRIPTION  
Supply voltage range for ARM / IVA domain  
Maximum Noise (peak-peak)  
MIN  
NOM  
See(1)  
40  
MAX  
UNIT  
vdd_mpu_iva  
V
mVPP  
V
vdd_core  
vdds  
Supply voltage range for core domain  
Maximum Noise (peak-peak)  
See(1)  
40  
mVPP  
V
Supply voltage for 1.8-V I/O macros  
1.71  
1.71  
1.80  
40  
1.91  
1.91  
Maximum Noise (peak-peak)  
Oscillator IO (Crystal or  
mVPP  
Square modes)  
Others  
90  
1.80  
90  
vdds_mem  
Supply voltage for memory buffers  
Maximum Noise (peak-peak)  
V
mVPP  
V
vdds_mmc1  
Supply voltage range for mmc1  
dual voltage IOs  
1.8-V mode  
3.0-V mode  
1.8-V mode  
3.0-V mode  
1.8-V mode  
3.0-V mode  
1.8-V mode  
3.0-V mode  
1.71  
2.70  
1.80  
3.00 to 3.30  
90  
1.91  
3.60  
Noise (peak-peak)  
mVPP  
V
150  
vdds_x  
Supply voltage range for x dual  
voltage IOs  
1.71  
2.70  
1.80  
3.00  
90  
1.91  
3.60  
Maximum Noise (peak-peak)  
mVPP  
150  
vdda_wkup_bg_ Supply voltage range for wake-up LDO  
1.71  
1.71  
1.80  
50  
1.91  
1.91  
V
bb  
Maximum Noise (peak-peak)  
mVPP  
V
vdda_dac  
Analog supply voltage for Video DAC  
1.80  
30  
Maximum Noise (peak-peak) for a frequency from 0 to 100  
kHz  
mVPP  
(For a frequency > 100 kHz, decreases 20 dB/dec)  
vdds_sram  
Supply voltage for SRAM LDOs  
1.71  
1.71  
1.80  
50  
1.91  
1.91  
V
Maximum Noise (peak-peak)  
mVPP  
V
vdda_dplls_dll  
Supply voltage for MPU, IVA, core DPLLs and DLL  
1.80  
30  
Maximum Noise (peak-peak)  
For any frequency  
mVPP  
vdda_dpll_per  
vssa_dac  
Supply voltage for DPLLs (peripherals)  
1.71  
1.80  
50  
1.91  
V
Maximum Noise (peak-peak)  
For any frequency  
mVPP  
Ground for video buffers and DAC  
0
V
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Table 3-4. Recommended Operating Conditions (continued)  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
V
vss  
TJ  
Main ground  
Operating junction temperature  
range  
0
Commercial  
Temperature  
0
90  
°C  
Extended Temperature  
-40  
105  
(1) See Section 4.3.4, Processor Clocks. OPP voltage values may change following the silicon characterization result.  
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3.3 DC Electrical Characteristics  
Table 3-5 summarizes the dc electrical characteristics.  
Note: The interfaces or signals described in Table 3-5 correspond to the interfaces or signals available in  
multiplexing mode 0. All interfaces or signals multiplexed on the balls / pins described in Table 3-5 have  
the same DC electrical characteristics.  
Table 3-5. DC Electrical Characteristics  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
SDRC Mode (CBP Balls(15): C14 / B14 / C15 / B16 / D17 / C17 / B17 / D18 / H9 / H10 / H11 / H12 / A13 / A14 / H16 / H17 / H14 / H13 /  
H15 / A16 / A17)(4)  
VIH  
High-level input voltage  
Low-level input voltage  
0.7 * vdds_mem  
V
V
V
V
VIL  
0.3 * vdds_mem  
(1)  
VHYS  
VOH  
Hysteresis voltage at an input  
0.07  
High-level output voltage, driver enabled,  
pullup or pulldown disabled  
IOH = –4 mA  
IOL = 4 mA  
0.8 * vdds_mem  
vdds_mem  
VOL  
CIN  
Low-level output voltage, driver enabled,  
pullup or pulldown disabled  
0
0.2 * vdds_mem  
V
Input capacitance  
1.15  
10  
pF  
ns  
(2)  
tTIN  
Input recommended rise, tRIN, and fall time, tFIN (measured  
between 20% and 80% at PAD)  
(2)  
tROUT  
Output maximum rise time (rise time, tROUT, evaluated  
between 20% and 80% at PAD) @ maximum load  
1.15  
1.10  
ns  
ns  
pF  
(2)  
tFOUT  
Output maximum fall time (fall time, tFOUT, evaluated  
between 20% and 80% at PAD) @ maximum load  
COUT  
Load capacitance  
DS0 = 0(3)  
DS0 = 1(3)  
2
4
4
12  
MMC Interface 1 Mode (CBP Balls(15): N28 / M27 / N27 / N26 / N25 / P28)  
1.8-V Mode  
VIH  
VIL  
High-level input voltage  
0.70 * vdds_mmc1  
–0.3  
vdds_mmc1 + 0.3  
0.30 * vdds_mmc1  
V
V
V
V
Low-level input voltage  
VOH  
VOL  
High-level output voltage with 100-mA sink current IOH  
vdds_mmc1 – 0.2  
Low-level output voltage with 100-mA sink current at  
0.2  
vdds_mmc1 minimum  
(1)  
VHYS  
Hysteresis voltage at an input  
0.1  
V
(2)  
tTIN  
Input transition time (tRIN or tFIN evaluated  
between 10% and 90% at PAD)  
Normal Mode  
3
8
ns  
(SPEEDCTRL  
= 1)(4)  
High-Speed  
(SPEEDCTRL  
= 0)(4)  
COUT  
LOUT  
Load capacitance  
10  
30  
16  
pF  
nH  
Line inductance (except vdds_mmc1)  
3.0-V Mode  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
0.625 * vdds_mmc1  
–0.3  
vdds_mmc1 + 0.3  
0.25 * vdds_mmc1  
V
V
V
V
VOH  
VOL  
High-level output voltage with 100-mA sink current IOH  
0.75 * vdds_mmc1  
Low-level output voltage with 100-mA source current at  
0.125 * vdds_mmc1  
vdds_mmc1 minimum  
(1)  
VHYS  
Hysteresis voltage at an input  
0.05  
V
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Table 3-5. DC Electrical Characteristics (continued)  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
(2)  
tTIN  
Input transition time (tRIN or tFIN evaluated  
between 10% and 90% at PAD)  
Normal Mode  
(SPEEDCTRL  
= 1)(4)  
3
ns  
High-Speed  
(SPEEDCTRL  
= 0)(4)  
8
COUT  
LOUT  
Load capacitance  
10  
30  
16  
pF  
nH  
Line inductance (except vdds_mmc1)  
GPIO Mode (CBP Balls(15): P27 / P26 / R27 / R25)  
1.8-V Mode  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
0.70 * vdds_x  
–0.3  
vdds_x + 0.3  
0.20 * vdds_x  
vdds_x + 0.3  
0.4  
V
V
V
V
VOH  
VOL  
High-level output voltage with 20-mA sink current IOH  
0.8 * vdds_x  
–0.3  
Low-level output voltage with 1-mA source current at vdds_x  
minimum  
(1)  
VHYS  
Hysteresis voltage at an input  
0.1  
V
(2)  
tTIN  
Input transition time (tRIN or tFIN evaluated  
between 10% and 90% at PAD)  
Normal Mode  
(SPEEDCTRL  
= 1)(4)  
35  
ns  
CIN  
Input capacitance  
2.5  
30  
16  
pF  
pF  
nH  
COUT  
LOUT  
Load capacitance  
Line inductance (except vdds_x)  
3.0-V Mode  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
0.70 * vdds_x  
–0.3  
vdds_x + 0.3  
0.20 * vdds_x  
vdds_x + 0.3  
0.4  
V
V
V
V
VOH  
VOL  
High-level output voltage with 20-mA sink current IOH  
0.7 * vdds_x  
–0.3  
Low-level output voltage with 1-mA source current at  
vdds_sim minimum  
(1)  
VHYS  
Hysteresis voltage at an input  
0.05  
V
(2)  
tTIN  
Input transition time (tRIN or tFIN evaluated  
between 10% and 90% at PAD)  
Normal Mode  
35  
ns  
(SPEEDCTRL  
= 1)(4)  
CIN  
Input capacitance  
2.5  
30  
16  
pF  
pF  
nH  
COUT  
LOUT  
Load capacitance  
Line inductance (except vdds_x)  
I2C Mode (CBP Balls(15): K21 / J21 / AF15 / AE15 / AF14 / AG14 / AD26 / AE26) (6)  
Standard Mode  
VIH  
VIL  
VHYS  
VOL  
II  
High-level input voltage  
0.7 * vdds  
–0.5  
vdds + 0.5  
0.3 * vdds  
V
V
Low-level input voltage  
(1)  
Hysteresis voltage at an input  
0.15  
NA(14)  
V
Low-level output voltage open-drain at 3-mA sink current  
NA(14)  
10  
V
Input current at each I/O pin with an input voltage between  
0.1 * vdds to 0.9 * vdds  
–10  
mA  
CI  
Capacitance for each I/O pin  
10  
pF  
ns  
(5)  
(5)  
tFOUT  
Output fall time from VIHmin to VILmax with a bus capacitance  
CB from 10 pF to 400 pF  
250  
tROUT  
Output rise time with a capacitive load from 10 pF to 150 pF  
with internal pullup  
20 + 0.1CB  
250  
ns  
Fast Mode  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
0.7 * vdds  
–0.5  
vdds + 0.5  
0.3 * vdds  
V
V
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Table 3-5. DC Electrical Characteristics (continued)  
PARAMETER  
MIN  
0.15  
0
NOM  
MAX  
UNIT  
V
(1)  
VHYS  
Hysteresis voltage at an input  
VOL  
II  
Low-level output voltage open-drain at 3-mA sink current  
0.2 * vdds  
10  
V
Input current at each I/O pin with an input voltage between  
0.1 * vdds to 0.9 * vdds  
–10  
mA  
CI  
Capacitance for each I/O pin  
10  
pF  
ns  
(5)  
tFOUT  
Output fall time from VIHmin to VILmax with a bus capacitance  
CB from 10 pF to 400 pF  
20 + 0.1CB  
20 + 0.1CB  
250  
(5)  
tROUT  
Output rise time with a capacitive load from 10 pF to 150 pF  
with internal pullup  
250  
ns  
High-Speed Mode  
VIH  
VIL  
VHYS  
VOL  
II  
High-level input voltage  
0.7 * vdds  
–0.5  
0.15  
0
vdds + 0.5  
0.3 * vdds  
V
V
Low-level input voltage  
(1)  
Hysteresis voltage at an input  
V
Low-level output voltage open-drain at 3-mA sink current  
0.2 * vdds  
10  
V
Input current at each I/O pin with an input voltage between  
0.1 * vdds to 0.9 * vdds  
–10  
mA  
CI  
Capacitance for each I/O pin  
10  
40  
pF  
ns  
(5)(6)  
tFOUT  
Output fall time with a capacitive load from 10 pF to 100 pF  
at 3-mA sink current  
10  
20  
10  
Output fall time with a capacitive load of 400 pF at 3-mA  
sink current  
80  
40  
ns  
ns  
(5)  
tROUT  
Output rise time with a capacitive load from 10 pF to 80 pF  
with internal pullup  
Standard LVCMOS Mode  
VIH  
VIL  
High-level input voltage  
0.7 * vdds  
–0.5  
vdds  
V
V
Low-level input voltage  
0.3 * vdds  
VOH  
VOL  
CIN  
tTIN  
High-level output voltage at 4-mA sink current  
Low-level output voltage at 4-mA sink current  
Input capacitance  
vdds – 0.45  
V
0.45  
1.15  
10  
V
pF  
ns  
(2)  
Input transition time (tRIN or tFIN evaluated between 10% and  
90% at PAD)  
tTOUT  
Output transition time at 40-pF load (tROUT or tFOUT  
evaluated between 10% and 90% at PAD)  
10  
ns  
MIPI D-PHY Interface  
MIPI D-PHY Interface - GPI Mode (CBP Balls(15): AG19 / AH19 / AG18 / AH18 / K28 / L28 / K27 / AG17 / AH17)  
(7)  
VIH  
High-level input voltage  
Low-level input voltage  
Hysteresis voltage at an input  
Input capacitance  
0.65 * vdds_x  
–0.3  
vdds_x + 0.3  
0.35 * vdds_x  
V
V
(8)  
VIL  
(1)  
VHYS  
CIN  
0.15  
V
1.3  
10  
pF  
ns  
(2)  
tTIN  
Input transition time (tRIN or tFIN evaluated between 10% and  
90% at PAD)  
Other Balls  
Common to "Other Balls"  
VIH  
High-level input voltage  
0.65 * vdds  
–0.3  
vdds + 0.3  
0.35 * vdds  
V
V
V
V
VIL  
Low-level input voltage  
(1)  
VHYS  
VOH  
Hysteresis voltage at an input  
0.15  
High-level output voltage, driver enabled,  
pullup or pulldown disabled  
IOH = – X mA  
IOL = X mA  
vdds – 0.45  
VOL  
Low-level output voltage, driver enabled,  
pullup or pulldown disabled  
0.45  
V
Differences Between "Other Balls"  
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UNIT  
Table 3-5. DC Electrical Characteristics (continued)  
PARAMETER  
MIN  
NOM  
MAX  
Input Capacitance and Input Transition Time  
sys_xtalin pin (CBP Ball(15): AE17)  
CIN  
tTIN  
Input capacitance  
1.00  
1.15  
1.35  
5
pF  
ns  
(2)  
Input transition time (rise time, tRIN or fall time, tFIN  
evaluated between 10% and 90% at PAD)  
JTAG interface (CBP Balls(15): AA17 / AA13 / AA12 / AA18 / AA20 / AA19 / AA11 / AA10)  
CIN  
tTIN  
Input capacitance  
2.20  
10  
pF  
ns  
(2)  
Input transition time (rise time, tRIN or fall time, tFIN  
evaluated between 10% and 90% at PAD)  
Otherwise  
CIN  
Input capacitance  
1.15  
10  
pF  
ns  
(2)  
tTIN  
Input transition time (rise time, tRIN or fall time, tFIN  
evaluated between 10% and 90% at PAD)  
Output Capacitance Load and Output Transition Time  
sys_32k, sys_clkreq, sys_off_mode, sys_clkout1, sys_nirq, uart3_cts_rctx, uart3_rts_sd, uart3_rx_irrx, uart3_tx_irtx, hdq_sio  
(CBP Balls(15): R27 / AE25 / AF25 / AF22 / AG25 / AF26 / H18 / H19 / H20 / H21 / J25)  
tTOUT  
Output transition time (rise time, tROUT or  
fall time, tFOUT evaluated between 10% and  
90% at PAD)  
DS[1:0] = 00(3)  
DS[1:0] = 10(3)  
DS[1:0] = 01(3)  
1
15  
ns  
CTOUT  
tTOUT  
Output load  
4
60  
5
pF  
ns  
Output transition time (rise time, tROUT or  
fall time, tFOUT evaluated between 10% and  
90% at PAD)  
0.4  
CTOUT  
tTOUT  
Output load  
2
21  
7
pF  
ns  
Output transition time (rise time, tROUT or  
fall time, tFOUT evaluated between 10% and  
90% at PAD)  
0.6  
CTOUT  
Output load  
7
33  
pF  
CAM, HSUSB0, SDMMC2, UART1, UART2, McBSP, McSPI, ETK Interfaces, sys_clkout2 (CBP Ball(15): AE22)  
tTOUT  
Output transition time (rise time, tROUT or fall time, tFOUT  
evaluated between 10% and 90% at PAD)  
1.5  
5
ns  
CTOUT  
Output load  
2
22  
pF  
Otherwise  
tTOUT  
Output transition time (rise time, tROUT or fall time, tFOUT  
evaluated between 10% and 90% at PAD)  
0.6  
2
2.4  
22  
ns  
CTOUT  
Output load  
pF  
Hysteresis  
sys_xtalin pin (CBP Ball(15): AE17)  
(1)  
VHYS  
Hysteresis voltage at an input  
0.25  
0.07  
0.15  
V
V
V
hsusb0_clk (CBP Ball(15): T28)  
(1)  
VHYS  
Hysteresis voltage at an input  
Otherwise  
(1)  
VHYS  
Hysteresis voltage at an input  
(1) Vhys is the magnitude of the difference between the positive-going threshold voltage VT+ and the negative-going threshold voltage VT–  
Some receivers, but not all, are designed for hysteresis. Vhys applies only to those that are.  
.
(2) The tIN (tRIN and tFIN also) value is the recommended condition. The tIN (tRIN and tFIN also) mismatch causes additional delay time inside  
the device then leads to ac timing invalidation in this DM.  
The tIN (tRIN and tFIN also) mismatch does not necessarily mean functional failure. This global value may be overridden on a per interface  
basis if another value is explicitly defined for that interface in the Timing Requirements and Switching Characteristics chapter of the data  
manual.  
(3) For a full description of the DS0 load compensation register configuration, see the description of the CONTROL_PROG_IO1  
configuration registers in System Control Module / Programming Model / Feature Settings / SDRC I/O Drive Strength Selection section  
of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
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(4) For a full description of the SPEEDCTRL speed register configuration, see the description of the CONTROL_PROG_IO1 configuration  
registers in System Control Module / Programming Model / Feature Settings section of the AM/DM37x Multimedia Device Technical  
Reference Manual (literature number SPRUGN4).  
(5) Rise and fall times are specified for (0.3 * vdds) to (0.7 * vdds).  
(6) For capacitive load from 100 pF to 400 pF, fall time should be linearly interpolated:  
tFmin = (1 + (Load – 100 pF) / 300 pF) * 10 ns  
tFmax = (1 + (Load – 100 pF) / 300 pF) * 40 ns  
(7) VIH is the voltage at which the receiver is required to detect a high state in the input signal.  
(8) VIL is the voltage at which the receiver is required to detect a low state in the input signal. VIL is larger than the maximum single-ended  
line voltage during HS transmission. Therefore, both LP receivers will detect low during HS signaling.  
(9) This value includes a ground difference of 50 mV between the transmitter and the receiver, the status common-mode level tolerance  
and variations below 450 MHz.  
(10) Common mode is defined as the average voltage level of DX and DY: VCM = (V(DX) + V(DY))/2. Common mode ripple may be due to  
rise-fall time and transmission line impairments in the PCB.  
(11) Value when driving into differential load impedance anywhere in the range 80 to 125 Ω.  
(12) ULPM stands for Ultra Low Power Mode.  
(13) UI = 1 / (2 * fh), where fh is the fundamental frequency of HS data transmission. For example, for 800 Mbps fh is 400 MHz.  
(14) No VOL specifications are applicable in Standard mode.  
(15) For associated CBC and CUS balls, please refer to the Section 2.4, Multiplexing Characteristics table.  
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3.4 External Capacitors  
To improve module performance, decoupling capacitors are required to suppress the switching noise  
generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective  
when it is close to the device, because this minimizes the inductance of the circuit board wiring and  
interconnects.  
3.4.1 Voltage Decoupling Capacitors  
Table 3-6 summarizes the Core voltage decoupling characteristics.  
3.4.1.1 Core Voltage Decoupling Capacitors  
To improve module performance, decoupling capacitors are required to suppress the switching noise  
generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective  
when it is close to the device, because this minimizes the inductance of the circuit board wiring and  
interconnects.  
Table 3-6. Core Voltage Decoupling Characteristics(1)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
mF  
(1)(2)  
Cvdd_core  
Cvdd_mpu_iva  
(1) In power plan configuration  
0.6  
1.2  
1.8  
(1)  
(2)  
See  
mF  
(2) The typical value corresponds to 2 capacitors of 470 nF, plus 3 capacitors of 100 nF.  
3.4.1.2 IO and Analog Voltage Decoupling Capacitors  
Table 3-7 summarizes the power supply decoupling capacitor characteristics.  
Table 3-7. Power Supply Decoupling Capacitor Characteristics  
PARAMETER  
MIN  
200  
350  
50  
TYP  
400  
700  
100  
100  
100  
100  
220  
470  
100  
MAX  
600  
1050  
150  
150  
150  
150  
330  
700  
150  
UNIT  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
nF  
(1)(2)  
Cvdds  
Cvdds_mem  
Cvdds_mmc1  
(1) (3)  
(4)  
(4)  
Cvdds_x  
50  
(4)  
Cvdda_dplls_dll  
50  
(4)  
Cvdda_dpll_per  
50  
(4)  
Cvdds_sram  
110  
240  
50  
(4)  
Cvdda_wkup_bg_bb  
(4)  
Cvdda_dac  
(1) In power plan configuration  
(2) The typical value corresponds to 4 capacitors of 100 nF.  
(3) The typical value corresponds to 7 capacitors of 100 nF.  
(4) In power rail configuration  
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3.4.2 Output Capacitors  
The capacitors at the outputs are required to stabilize the internal LDO supply voltages. The capacitors  
must be placed as close as possible to the balls.  
Table 3-8 summarizes the power supply decoupling characteristics.  
Table 3-8. Output Capacitor Characteristics  
PARAMETER  
MIN  
0.7  
0.7  
0.7  
0.7  
0.7  
TYP  
MAX  
1.3  
1.3  
1.3  
1.3  
1.3  
UNIT  
mF  
Ccap_vdd_sram_mpu_iva  
Ccap_vdd_sram_core  
Ccap_vddu_wkup_logic  
Ccap_vddu_array  
1
1
1
1
1
mF  
mF  
mF  
Ccap_vdd_bb_mpu_iva  
mF  
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Figure 3-1 illustrates an example of the external capacitors.  
Device  
vdda_dac  
Cvdda_dac  
vdds_sram  
Cvdds_sram  
vdda_dac  
vssa_dac  
vdds_sram  
Video DAC  
SRAM_LDO1  
SRAM_LDO2  
DPLL_MPU  
cap_vdd_sram_mpu_iva  
cap_vdd_sram_core  
Ccap_vdd_sram_mpu_iva  
Ccap_vdd_sram_core  
DPLL_IVA  
DPLL_CORE  
DLL  
vdda_dplls_dll  
vdda_dplls_dll  
vdds_mmc1  
Cvdds_mmc1  
Cvdda_dplls_dll  
vdds_mmc1  
MMC I/Os  
vdda_dpll_per  
Cvdda_dpll_per  
vdds_mem  
Cvdds_mem  
vdda_dpll_per  
vdds_mem  
DPLL5  
DPLL4  
VDDS_MEM  
BG  
vdda_wkup_bg_bb  
vdda_wkup_bg_bb  
Cvdda_wkup_bg_bb  
BBLDO  
cap_vdd_bb_mpu_iva  
Ccap_vdd_bb_mpu_iva  
vdd_mpu_iva  
Cvdd_mpu_iva  
vdd_mpu_iva  
vdd_core  
WKUP_LOGIC  
MPU  
cap_vddu_wkup_logic  
cap_vddu_array  
vdd_core  
Ccap_vddu_wkup_logic  
Ccap_vddu_array  
CORE  
Cvdd_core  
vdds  
Cvdds  
vdds  
vss  
VDDS I/O  
OSC I/O  
sys_xtalgnd  
Figure 3-1. External Capacitors  
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NOTE  
•
•
Decoupling capacitors must be placed as closed as possible of the power ball. Choose  
the ground located closest to the power pin for each decoupling capacitor. In case of  
interconnecting powers, first insert the decoupling capacitor and then interconnect the  
powers.  
The decoupling capacitor value depends on the board characteristics.  
3.5 Power-Up and Power-Down Sequences  
This section provides the timing requirements for the device hardware signals.  
NOTE  
•
•
If the MMC dual voltages interfaces are used with 1.8-V or 3.0-V, then the power-up and  
power-down sequences specified in the Figure 3-2 and Figure 3-3 must be followed  
carefully to avoid any significant current consumption.  
If the MMC dual voltages interfaces are used with 1.8-V only (3.0-V is never used), then  
vdds_mmc1, vdds_x may be connected to the main power supply vdds so that they ramp  
up together before vdd_core.  
3.5.1 Power-Up Sequence  
NOTE  
For more information, see the Power, Reset, and Clock Management / PRCM Functional  
Description / PRCM Reset Manager Functional Description / Reset Sequences of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Figure 3-2 shows the power-up sequence.  
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1.8 V  
vdds, vdds_mem,  
vdds_sram,  
vdda_wkup_bg_bb  
1.8 V  
vdda_dplls_dll,  
vdda_dpll_per  
1.1 V(1)  
vdd_core  
1.1 V(1)  
vdd_mpu_iva  
sys_32k  
sys_xtalin  
sys_nrespwron  
sys_nreswarm  
vdds_mmc1, vdds_x,  
vdda_dac, vpp  
(1) 1.2 V supported.  
(2) If an external square clock is provided, it could be started after sys_nrespwron release, provided it is clean, i.e. no glitch, stable  
frequency and duty cycle.  
(3) sys_32k can be turned on any time between the vdds ramp-up and the sys_nrespwron release.  
Figure 3-2. Power-Up Sequence  
3.5.2 Power-Down Sequence  
The following steps give two examples of power-down sequence supported by the DM37x device.  
1. Put the DM37x device under reset (sys_nrespwron)  
2. Stop all signals driven to its balls (sys_32k, sys_xtalin)  
3. Either:  
(a) Shutdown all power domains at once. This sequence is described in black color in Figure 3-3.  
(b) Or, if the shutdown is sequenced, you must follow these steps (described in dash style blue color  
in Figure 3-3):  
–
–
–
–
–
–
Turn off all complex IO domains (vdds_mmc1, vdds_x)  
Turn off all the core and MPU domains (vdd_core, vdd_mpu_iva)  
Turn off all DPLL domains (vdda_dplls_dll, vdda_dpll_per)  
Turn off all sram LDOs (vdds_sram)  
Turn off all reference domains (vdda_wkup_bg_bb)  
Turn off all standard IO domains (vdds, vdds_mem)  
Figure 3-3 shows both power-down sequences: one of them is described in black color, and the other one  
in dash style blue.  
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sys_nrespwron  
vdds_mmc1, vdds_x,  
vdda_dac  
vdd_core  
vdd_mpu_iva  
vdda_dplls_dll,  
vdda_dpll_per  
vdds_sram  
vdda_wkup_bg_bb  
vdds, vdds_mem  
sys_32k  
sys_xtalin  
A. sys_32k can be turned off any time between the sys_nrespwron assertion and the vdds shut down.  
Figure 3-3. Power-Down Sequence  
Alternate power-down sequence:  
•
•
•
vdd_mpu_iva shuts down before vdd_core.  
vdda_sram, vdda_wkup_bg_bb, vdds and vdds_mem shut down simultaneously.  
vdda_dplls_dll and vdda_dpll_per shut down anytime between all complex IO domains shut down and  
vdda_sram shuts down.  
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4 Clock Specifications  
NOTE  
For more information, see the Power, Reset, and Clock Management / PRCM Environment /  
External Clock Signal and Power, Reset and Clock Management / PRCM Functional  
Description / PRCM Clock Manager Functional Description sections of the AM/DM37x  
Multimedia Device Technical Reference Manual (SPRUGN4).  
Figure 4-1 shows external input clock sources and output clocks.  
Device  
From power IC: 32 768-Hz  
sys_32k  
sys_altclk  
Alternate clock source selectable (48-MHz, 54-MHz)  
To peripherals (from oscillator clock [sys_xtalin]): 12-,13-,  
16.8-, 19.2-, 26-, or 38.4-MHz (no divider)  
sys_clkout1  
sys_clkout2  
To peripherals (from oscillator clock [sys_xtalin]): 12-,13-,  
16.8-, 19.2-, 26-, or 38.4-MHz or Core_clk: up to 332 MHz  
(possible divider: 4, 8, 16) or DPLL 54-MHz, DPLL 96-MHz  
(possible divider: 1, 2, 4, 8, or 16)  
sys_xtalout  
sys_xtalin  
To quartz (oscillator output) or unconnected  
From quartz (oscillator input) or square clock  
sys_clkreq  
Clock request. To square clock source or from peripherals  
sys_xtalout  
sys_xtalout  
Unconnected  
Oscillator  
is bypassed  
Oscillator  
is used  
sys_xtalin  
sys_clkreq  
sys_xtalin  
sys_clkreq  
Square  
clock  
source  
GPin  
SWPS038-006  
Figure 4-1. Clock Interface  
130  
Clock Specifications  
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The device operation requires the following three input clocks:  
•
•
•
The sys_32k 32-kHz clock is used for low frequency operation. It supplies the wake-up domain for  
operation in lowest power mode (off mode). This clock is provided through the sys_32k pin.  
The sys_altclk system alternative clock can be used (through the sys_altclk pin) to provide alternative  
48 MHz or 54 MHz.  
The sys_xtalin / sys_xtalout system input clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to  
generate the main source clock of the device. It supplies the DPLLs as well as several other modules.  
The system input clock can be connected to either:  
–
A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is  
used as an input (GPIN).  
–
A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to  
request the external system clock.  
The device outputs externally two clocks:  
•
sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be  
controlled by software or externally using sys_clkreq control. When the device is in the off state, the  
sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the  
device. The off state polarity of sys_clkout1 is programmable.  
•
sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL  
output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is  
programmable. This output is active only when the core power domain is active.  
4.1 Input Clock Specifications  
4.1.1 Input Clock Requirements  
Table 4-1 illustrates the requirements to supply a clock to the device.  
Table 4-1. Input Clock Requirements  
PAD  
sys_32k  
CLOCK FREQUENCY  
STABILITY  
DUTY CYCLE  
JITTER  
TRANSITION  
32.768 kHz  
+/- 200 ppm  
-
-
-
-
<10 ns  
-
sys_xtalout  
sys_xtalin  
12, 13, 16.8, or 19.2 MHz  
Crystal  
Square  
±50 ppm (±5  
ppm)(1)  
12, 13, 16.8, 19.2, 26, or 38.4 MHz  
±50 ppm (±5  
ppm)(1)  
45% to 55%  
49% to 51%  
X%(2) *  
tc(xtalin)(3) -  
200ps  
5 ns  
sys_altclk  
48 or 54 MHz  
+/-50 ppm  
<1%  
10 ns  
(1) ± 50 ppm is the clock frequency stability/accuracy and ± 5 ppm takes into account the aging effects.  
(2) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin  
input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies.  
For more information, see the Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference  
Manual (SPRUGN4). In X%, X represents then the internal system clock divider with following possible values: X = 1 or 2.  
(3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball.  
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4.1.2 sys_xtalin / sys_xtalout External Crystal  
An external crystal is connected to the device pins. Figure 4-2 describes the crystal implementation.  
Device  
sys_xtalin  
sys_xtalout  
Optional Rbias  
Optional Rd  
Cf1  
Cf2  
Crystal  
SWPS038-007  
Figure 4-2. Crystal Implementation  
The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes  
the required electrical constraints.  
Table 4-2. Crystal Electrical Characteristics(1)  
NAME  
DESCRIPTION  
Parallel resonance crystal frequency(1)  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
fp  
12, 13, 16.8, or 19.2  
Cf1  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
12  
12  
24  
24  
Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
pF  
ESR(Cf1,Cf2)(2) Frequency 10 MHz , Negative resistor at nominal 500 Ω, Negative  
resistor at worst case 300 Ω  
100  
Ω
Frequency 15 MHz, Negative resistor at nominal 300 Ω, Negative  
resistor at worst case 180 Ω  
60  
50  
Ω
Ω
Frequency 30 MHz, Negative resistor at nominal 250 Ω, Negative  
resistor at worst case 150 Ω  
Co  
Crystal shunt capacitance  
4.5  
pF  
(1) Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If  
CL = 20 pF, then both foot capacitors will be Cf1 = Cf2 = 40 pF. Parasitic capacitance from package and board must also be taken in  
account.  
(2) The crystal motional resistance Rm is related to the equivalent series resistance (ESR) by the following formula:  
ESR = Rm * (1 + (CO * Cf1 * Cf2 / (Cf1 + Cf2)))2.  
When selecting a crystal, the system design must take into account the temperature and aging  
characteristics of a crystal versus the user environment and expected lifetime of the system.  
132  
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Table 4-3 details the switching characteristics of the oscillator and the requirements of the input clock.  
Table 4-3. Oscillator Switching Characteristics—Crystal Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
ms  
fp  
Oscillation frequency  
Start-up time(1) (2)  
12, 13, 16.8, or 19.2  
tsX  
3
(1) Start-up time is defined as the time the oscillator takes to gain sys_xtalin amplitude enough to have 45% to 55% duty cycle at the core  
input from the time power down (PWRDN) is released. Start-up time is a strong function of crystal parameters. At power-on reset, the  
time is adjustable using the pin itself. The reset must be released when the oscillator or clock source is stable. To switch from bypass  
mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 ms; however, if the chip comes from bypass  
mode to crystal mode then the crystal will start-up after time mentioned in the tsX parameter.  
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in  
application mode and receives a square wave. The switching time in this case is about 100 ms.  
4.1.3 sys_xtalin Squarer Input Clock  
Table 4-4 summarizes the base oscillator electrical characteristics.  
Table 4-4. Oscillator Electrical Characteristics—Bypass Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
f
Frequency  
12, 13, 16.8, 19.2, 26, or 38.4  
Ci  
Ri  
tsX  
Input Capacitance  
Input Resistance  
Start-up time(1)  
1.00  
160  
1.15  
216  
See(2)  
1.35  
280  
Ω
ms  
(1) To switch from bypass mode to crystal mode or from crystal mode to bypass mode, there is a waiting time about 100 ms; however, if the  
chip comes from bypass mode to crystal mode then the crystal will start-up after time mentioned in Table 4-3, tsX parameter above.  
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in  
application mode and receives a square wave. The switching time in this case is about 100 ms.  
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Table 4-5 details the squarer input clock timing requirements.  
Table 4-5. sys_xtalin Squarer Input Clock Timing Requirements—Bypass Mode  
NAME  
OCS0  
DESCRIPTION  
1 / tc(xtalin)  
tw(xtalin)  
MIN  
12, 13, 16.8, 19.2, 26, or 38.4  
0.45 * tc(xtalin) 0.55 * tc(xtalin)  
TYP  
MAX  
UNIT  
MHz  
ns  
Frequency, sys_xtalin  
OCS1  
Pulse duration, sys_xtalin low or high  
Peak-to-peak jitter(1), sys_xtalin  
tJ(xtalin)  
X%(2)  
*
ps  
tc(xtalin) (3)  
200  
-
tR(xtalin)  
tF(xtalin)  
tJ(xtalin)  
Rise time, sys_xtalin  
5
5
ns  
ns  
Fall time, sys_xtalin  
Frequency stability, sys_xtalin  
+/-50  
ppm  
(+/-5ppm)(4)  
(1)  
–
Peak-to-peak jitter is meant here as follows:  
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period  
The minimum value is the difference between the shortest measured clock period and the expected clock period Maximum and  
minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period  
(2) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin  
input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies. For more information, see the Power,  
Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). In X%, X  
represents then the internal system clock divider with following possible values: X = 1 or 2.  
(3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball.  
(4) ±50 ppm is the clock frequency stability/accuracy and ±5 ppm takes into account the aging effects.  
OSC0  
OSC1  
OSC1  
sys_xtalin  
SWPS038-008  
Figure 4-3. sys_xtalin Squarer Input Clock  
4.1.4 sys_32k CMOS Input Clock  
Table 4-6 summarizes the electrical characteristics of the sys_32k input clock.  
Table 4-6. sys_32k Input Clock Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
kHz  
pF  
f
Frequency, sys_32k  
Input capacitance  
Input resistance  
32.768  
Ci  
Ri  
1.6  
106  
3
MΩ  
Table 4-7 details the input requirements of the sys_32k input clock.  
Table 4-7. sys_32k Input Clock Timing Requirements  
NAME  
DESCRIPTION  
Frequency, sys_32k  
Rise time, sys_32k  
MIN  
TYP  
MAX  
UNIT  
kHz  
ns  
CK0  
1 / tc(32k)  
tR(32k)  
tF(32k)  
32.768  
10  
10  
Fall time, sys_32k  
ns  
tJ(32k)  
Frequency stability, sys_32k  
200  
ppm  
CK0  
CK1  
CK1  
sys_32k  
SWPS038-009  
Figure 4-4. sys_32k Input Clock  
134  
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4.1.5 sys_altclk CMOS Input Clock  
Table 4-8 summarizes the electrical characteristics of the sys_altclk input clock.  
Table 4-8. sys_altclk Input Clock Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
f
Frequency, sys_altclk  
Input capacitance  
Input resistance  
48 or 54  
Ci  
Ri  
1.6  
106  
3
MΩ  
Table 4-9 details the input requirements of the sys_altclk input clock.  
Table 4-9. sys_altclk Input Clock Timing Requirements  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
ns  
ALT0  
ALT1  
1 / tc(altclk)  
tw(altclk)  
tJ(altclk)  
Frequency, sys_altclk  
48 or 54  
Pulse duration, sys_altclk low or high  
Peak-to-peak jitter(1), sys_altclk  
Rise time, sys_altclk  
0.49 * tc(altclk)  
-1%  
0.51 * tc(altclk)  
1%  
10  
10  
50  
tR(altclk)  
tF(altclk)  
tJ(altclk)  
ns  
ns  
Fall time, sys_altclk  
Frequency stability, sys_altclk  
ppm  
(1) Peak-to-peak jitter is meant here as follows:  
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period  
The minimum value is the difference between the shortest measured clock period and the expected clock period Maximum and  
minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period  
ALT0  
ALT1  
ALT1  
sys_altclk  
SWPS038-010  
Figure 4-5. sys_altclk Input Clock  
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4.2 Output Clocks Specifications  
4.2.1 sys_clkout1 Output Clock  
Table 4-10 summarizes the sys_clkout1 ouput clock electrical characteristics.  
Table 4-10. sys_clkout1 Output Clock Electrical Characteristics  
NAME  
DESCRIPTION  
Frequency, sys_clkout1  
MIN  
TYP  
MAX  
UNIT  
f
sys_xtalin / sys_xtalout clock frequency  
MHz  
SC[0:1] = 00(1)  
CL  
Load capacitance (transmission line load + far end load)  
Transmission line impedance  
4
30  
2
60  
70  
20  
pF  
Ω
ZT  
LT  
Transmission line length  
cm  
SC[0:1] = 01(1)  
CL  
Load capacitance (transmission line load + far end load)  
Transmission line impedance  
7
30  
2
33  
70  
8
pF  
Ω
ZT  
LT  
Transmission line length  
cm  
SC[0:1] = 10(1)  
CL  
ZT  
LT  
Load capacitance (transmission line load + far end load)  
Transmission line impedance  
2
30  
1
21  
70  
6
pF  
Ω
Transmission line length  
cm  
(1) The mode is configured by bits SC0 and SC1 of the IO cell. For more details, see the AM/DM37x Multimedia Device Technical  
Reference Manual (SPRUGN4).  
Table 4-11 details the sys_clkout1 ouput clock switching characteristics.  
Table 4-11. sys_clkout1 Output Clock Switching Characteristics  
NAME  
CO0  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
1 / tc(CLKOUT1) Frequency, sys_clkout1  
sys_xtalin/sys_xtalout clock frequency  
MHz  
SC[0:1] = 00(1)  
SC[0:1] = 01(1)  
SC[0:1] = 10(1)  
CL  
Load capacitance  
4
60  
pF  
ps  
ps  
tJ  
Peak-to-peak jitter  
X(5) + 693  
X(5) + 705  
tJC2C  
Cycle-to-cycle jitter  
tW(CLKOUT1)  
Pulse duration, sys_clkout1 low or high  
0.45*tc(CLKOUT  
0.55*tc(CLKOUT  
1)  
1)  
15(3)  
15(3)  
tR(CLKOUT1)  
tF(CLKOUT1)  
Rise time, sys_clkout1  
Fall time, sys_clkout1  
1(2) (4)  
1(2) (4)  
ns  
ns  
CL  
Load capacitance  
7
33  
pF  
ps  
ps  
tJ  
Peak-to-peak jitter  
X(5) + 543  
X(5) + 555  
tJC2C  
Cycle-to-cycle jitter  
tW(CLKOUT1)  
Pulse duration, sys_clkout1 low or high  
0.45*tc(CLKOUT  
0.55*tc(CLKOUT  
1)  
1)  
7(3)  
7(3)  
tR(CLKOUT1)  
tF(CLKOUT1)  
Rise time, sys_clkout1  
Fall time, sys_clkout1  
0.6(2) (4)  
0.6(2) (4)  
ns  
ns  
CL  
Load capacitance  
2
21  
pF  
ps  
ps  
tJ  
Peak-to-peak jitter  
X(5) + 603  
X(5) + 615  
tJC2C  
Cycle-to-cycle jitter  
tW(CLKOUT1)  
Pulse duration, sys_clkout1 low or high  
0.47*tc(CLKOUT  
0.53*tc(CLKOUT  
1)  
1)  
tR(CLKOUT1)  
Rise time, sys_clkout1  
0.4(2) (4)  
5(3)  
ns  
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SPRS685–AUGUST 2010  
Table 4-11. sys_clkout1 Output Clock Switching Characteristics (continued)  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
tF(CLKOUT1)  
Fall time, sys_clkout1  
0.4(2) (4)  
5(3)  
ns  
(1) The mode is configured by bits SC0 and SC1 of the IO cell. For more details, see the AM/DM37x Multimedia Device Technical  
Reference Manual (SPRUGN4).  
(2) At minimum load  
(3) At maximum load (Maximum frequency 20 MHz)  
(4) Caution: this creates EMI parasitics up to 1.2 ns  
(5) X parameter corresponds to the input jitter contribution added at sys_xtalin input pin. For more information regarding the sys_xtalin input  
jitter requirement, see Section 4.1.1.  
CO0  
CO1  
CO1  
sys_clkout1  
SWPS038-011  
Figure 4-6. sys_clkout1 Output Clock  
4.2.2 sys_clkout2 Output Clock  
Table 4-12 summarizes the sys_clkout2 ouput clock electrical characteristics.  
Table 4-12. sys_clkout2 Output Clock Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
f
Frequency, sys_clkout2  
sys_xtalin clock or core_dpll clock(1) or 54  
MHz  
MHz, 96 MHz(2)  
CL  
ZT  
LT  
Load capacitance  
2
30  
1
22  
70  
6
pF  
Ω
Transmission line impedance  
Transmission line length  
cm  
(1) Possible divider: 4, 8, or 16.  
(2) Possible divider: 1, 2, 4, 8, or 16.  
Table 4-13 details the sys_clkout2 ouput clock switching characteristics.  
Table 4-13. sys_clkout2 Output Clock Switching Characteristics  
NAME  
CO0  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
1 / tc(CLKOUT2) Frequency, sys_clkout2  
sys_xtalin clock or core_dpll clock(3) or 54  
MHz  
MHz, 96 MHz(4)  
tc(xtalin)  
Cycle time, sys_xtalin  
1 / sys_xtalin  
(MHz)  
ns  
ns  
tc(coredpll)  
Cycle time, core_dpll (DPLL3) (7)  
1 / core_dpll  
(MHz)  
tc(54mhz)  
Cycle time, 54MHz clock (DPLL4) (7)  
Cycle time, 96MHz clock (DPLL4) (7)  
Pulse duration, sys_clkout2 low or high  
18.52  
10.42  
ns  
ns  
ns  
tc(96mhz)  
CO1  
tw(CLKOUT2)  
0.49*tc(clkout  
2)  
0.51*tc(clkout  
2)  
(5)  
tJ  
Peak-to-peak jitter  
Source clock:  
sys_xtalin  
X%(6)  
tc(xtalin) + 200  
*
ps  
ps  
Source clock:  
core_dpll  
4% *  
tc(coredpll)  
200  
+
Source clock: 54MHz  
Source clock: 96MHz  
4% * tc(54mhz)  
+ 200  
ps  
ps  
ns  
4% * tc(96mhz)  
+ 200  
tR(CLKOUT2)  
Rise time, sys_clkout2  
1.5(1)  
5(2)  
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Table 4-13. sys_clkout2 Output Clock Switching Characteristics (continued)  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
tF(CLKOUT2)  
(1) At minimum load  
Fall time, sys_clkout2  
1.5(1)  
5(2)  
ns  
(2) At maximum load (maximum frequency 104 MHz)  
(3) Possible divider: 4, 8, 16  
(4) Possible divider: 1, 2, 4, 8, or 16  
(5) Peak-to-peak jitter is meant here as follows:  
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period  
The minimum value is the difference between the shortest measured clock period and the expected clock period  
Maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock  
period.  
(6) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin  
input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies. For more information, see the Power,  
Reset, and Clock Management / PRCM Functional Description / PRCM Clock Manager Functional Description / External Clock I/Os /  
External Clock Inputs / High-Frequency System Clock section of AM/DM37x Multimedia Device Technical Reference Manual (literature  
number SPRUGN4).  
In X%, X represents then the internal system clock divider with following possible values: X = 1 or 2.  
(7) This cycle time specified here is the clock period of the clock going out of sys_clkout2.  
CO0  
CO1  
CO1  
sys_clkout2  
SWPS038-012  
Figure 4-7. sys_clkout2 Output Clock  
4.3 DPLL and DLL Specifications  
NOTE  
For more information, see Power, Reset, and Clock Management / PRCM Functional  
Description / PRCM Clock Manager Functional Description / Internal Clock Generation /  
DPLLs section of the AM/DM37x Multimedia Device Technical Reference Manual  
(SPRUGN4).  
The applicative subsystem integrates five DPLLs and a DLL. The PRM and CM drive all of them.  
The five main DPLLs are:  
•
•
•
•
•
DPLL1 (MPU)  
DPLL2 (IVA)  
DPLL3 (Core)  
DPLL4 (Peripherals)  
DPLL5 (Second peripherals DPLL)  
4.3.1 DPLL Characteristics  
Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating  
conditions.  
Table 4-14. DPLL Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
COMMENTS  
vdda_dplls_dll  
Supply voltage for DPLLs (MPU, IVA,  
and Core) and DLL  
1.71  
1.8  
1.91  
V
vdda_dpll_per  
Supply voltage for DPLL  
(Peripherals)  
1.71  
1.8  
1.91  
V
138  
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Table 4-14. DPLL Characteristics (continued)  
NAME  
finput  
DESCRIPTION  
CLKINP Input frequency  
MIN  
0.032  
0.032  
10  
TYP  
MAX  
52  
UNIT  
MHz  
MHz  
MHz  
MHz  
MHz  
COMMENTS  
FINP  
finternal  
Internal reference frequency  
CLKINPHIF Input frequency  
CLKINPULOW Input frequency  
CLKOUT output frequency  
52  
REFCLK  
FINPHIF  
fCLKINPHIF  
fCLKINPULOW  
fCLKOUT  
1000  
800  
1000(2)  
0.001  
10(1)  
[M / (N + 1)] * FINP * [1 /  
M2]  
fCLKOUTx2  
CLKOUTx2 output frequency  
CLKOUTHIF output frequency  
20(1)  
2000(2)  
MHz  
MHz  
2 * [M / (N + 1)] * FINP * [1  
/ M2]  
fCLKOUTHIF  
10(3)  
20(3)  
1000(4)  
2000(4)  
FINPHIF / M3  
2 * [M / (N + 1)] * FINP * [1  
/ M3]  
fDCOCLKLDO  
tlock  
DCOCLKLDO output frequency  
Frequency lock time  
20  
2000  
MHz  
2 * [M / (N + 1)] * FINP  
1.9 +  
ms  
350*REFCLK  
plock  
Phase lock time  
1.9 +  
500*REFCLK  
ms  
ms  
ms  
ms  
ms  
trelock-L  
prelock-L  
trelock-F  
prelock-F  
Relock time—Frequency lock(5) (Low  
power bypass)  
Relock time—Phase lock(5) (Low  
power bypass)  
Relock time—Frequency lock(5) (Fast  
relock bypass)  
Relock time—Phase lock(5) (Fast  
relock bypass)  
1.9 + 70*REFCLK  
DPLL in low-power mode:  
lowcurrstdby = 1  
1.9 +  
120*REFCLK  
DPLL in low-power mode:  
lowcurrstdby = 1  
0.05 +  
70*REFCLK  
DPLL in normal mode:  
lowcurrstdby = 0  
0.05 +  
120*REFCLK  
DPLL in normal mode:  
lowcurrstdby = 0  
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. For M2 > 1, the minimum frequency on these clocks will  
further scale down by factor of M2.  
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.  
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down  
by factor of M3.  
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.  
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.  
Table 4-15. DPLL4 Characteristics  
NAME  
vdda_dpll_per  
finput  
DESCRIPTION  
MIN  
1.71  
0.5  
TYP  
MAX  
1.91  
60  
UNIT  
V
COMMENTS  
Supply voltage for DPLL (peripherals)  
CLKINP input clock frequency  
REFCLK internal reference frequency  
1.8  
MHz  
MHz  
MHz  
FINP  
finternal  
0.5  
2.5  
REFCLK  
fCLKINPULOW  
CLKINPULOW bypass input  
frequency  
0.001  
800  
fCLKOUT  
CLKOUT output clock frequency  
10(1)  
500  
2000(2)  
2000  
MHz  
MHz  
[M / (N + 1)] * FINP * [1 /  
M2]  
fDCOCLKLDO  
Internal oscillator (DCO) output clock  
frequency  
[M / (N + 1)] * FINP  
tlock  
Frequency lock time  
350*REFCLK  
500*REFCLK  
ms  
ms  
ms  
plock  
Phase lock time  
Relock time—Frequency lock(3) (Low  
power bypass)  
trelock-L  
7.5 +  
30*REFCLKs  
DPLL in low-power mode:  
lowcurrstdby = 1  
prelock-L  
trelock-F  
prelock-F  
Relock time—Phase lock(3) (Low  
power bypass)  
Relock time—Frequency lock(3) (Fast  
relock bypass)  
Relock time—Phase lock(3) (Fast  
relock bypass)  
7.5 +  
125*REFCLKs  
ms  
ms  
ms  
DPLL in low-power mode:  
lowcurrstdby = 1  
NA  
NA  
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(1) The minimum frequency on CLKOUT is assuming M2 = 1. For M2 > 1, the minimum frequency on this clock will further scale down by  
factor of M2.  
(2) The maximum frequency on CLKOUT is assuming M2 = 1.  
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.  
4.3.2 DLL Characteristics  
Table 4-16 summarizes the DLL characteristics and assumes testing over recommended operating  
conditions.  
Table 4-16. DLL Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
COMMENTS  
vdda_dplls_dll  
Supply voltage for DPLLs (MPU, IVA, and  
Core) and DLL  
1.71  
1.8  
1.91  
V
(1)  
finput  
tlock  
Input clock frequency  
66  
120  
200  
500  
500  
450  
MHz  
Clocks  
ns  
Either application mode 0 and 1  
IDLE to MODEMAXDELAY  
Lock time  
trelock  
Relock time (Mode transitions through idle  
mode)  
250  
1.88  
1.50  
1.25  
Clocks  
IDLE to APPLICATION MODE 1  
or 0  
3.38  
2.71  
2.25  
ms  
ms  
ms  
IDLE to APPLICATION MODE  
@133 MHz  
IDLE to APPLICATION MODE  
@166 MHz  
IDLE to APPLICATION MODE  
@200 MHz  
(1) Maximum frequency for nominal conditions.  
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4.3.3 DPLL and DLL Noise Isolation  
The noise filters (decoupling capacitors) are required to suppress the switching noise generated by high  
frequency and to stabilize the supply voltage.  
A noise filter is most effective when it is close to the device, because this minimizes the inductance of the  
circuit board wiring and interconnects.  
Figure 4-8 illustrates an example of a noise filter.  
Noise Filter  
vdda_dplls_dll  
C
DPLL_MPU  
DLL  
DPLL_IVA  
DPLL_CORE  
Noise Filter  
vdda_dpll_per  
C
DPLL5  
DPLL4  
030-017  
A. This circuit is provided only as an example.  
B. The filter must be located as close as possible to the device.  
Figure 4-8. DPLL Noise Filter  
Table 4-17 specifies the noise filter requirements.  
Table 4-17. DPLL Noise Filter Requirements(1)  
NAME  
MIN  
TYP  
MAX  
UNIT  
Filtering capacitor  
50  
100  
150  
nF  
(1) For more information, see IO and Analog Voltage Decoupling Characteristics.  
4.3.4 Processor Clocks  
Table 4-18 through Table 4-20 show the clocks AC performance values.  
Table 4-18. Processor Voltages Without SmartReflexTM  
RETENTIO  
N
OPP50  
OPP100  
OPP130(4)  
MIN  
0.8  
MIN  
0.92  
TYP  
0.97  
MAX  
1.02  
MIN  
1.08  
TYP  
1.14  
MAX  
1.2  
MIN  
1.21  
TYP  
1.27  
MAX  
1.33  
VDD1(1) (2)  
(3) (V)  
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(1) At ball level.  
(2) These values are defined when the SmartReflexTM feature is deactivated. They can be lower when SmartReflex is activated.  
(3) Minimum OPP voltage values defined in this table include any voltage transient.  
(4) OPP130 is not available above TJ of 90C.  
Table 4-19. Processor Voltages With SmartReflexTM  
RETENTIO  
N
OPP50  
OPP100  
OPP130(5)  
OPP1G (5) (6)  
MIN  
0.8  
MIN  
0.92  
TYP  
0.97  
MAX  
1.02  
MIN  
1.08  
TYP  
1.14  
MAX  
1.2  
MIN  
1.21  
TYP  
1.27  
MAX  
1.33  
MIN  
1.28  
TYP  
1.33  
MAX  
1.38  
VDD1(1) (2)  
(3) (4) (V)  
(1) At ball level.  
(2) This table defines the safe VDD1 (vdd_mpu_iva) voltage ranges to be used before using the SmartReflex AVS feature for OPPs  
calibration.  
(3) These VDD1 (vdd_mpu_iva) values are the required voltage ranges prior to enabling the SmartReflex AVS feature. After calibration, the  
minimum voltage may be lower than this specification.  
(4) Minimum OPP voltage values defined in this table include any voltage transient.  
(5) OPP130 and OPP1G are not available above TJ of 90C.  
(6) OPP1G is a high performance operating point which has following requirements:  
–
ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1mF capacitor connected  
to cap_vdd_bb_mpu_iva.  
–
AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage.  
Table 4-20. Processor Clocks  
OPP50  
Ratio  
OPP100  
Ratio  
OPP130  
Ratio  
OPP1G (2)  
Description  
Source Clock Max  
Freq.(MHz)  
Max  
Max  
Max  
Ratio  
Freq.(MHz)  
Freq.(MHz)  
Freq.(MHz)  
DPLL1  
-
1200  
-
1200  
-
1600  
-
2000  
-
Locked  
Frequency  
DPLL1CLKO DPLL1  
300  
2 *(M2 = 2)(1) 600  
2 *(M2 = 1)(1) 800  
2 *(M2 = 1)(1) 1000  
2 *(M2 = 1)(1)  
UT_M2  
Locked  
Frequency  
DPLL2  
Locked  
Frequency  
-
1040  
260  
-
1040  
-
1320  
-
1600  
-
DPLL2CLKO DPLL2  
2 *(M2 = 2)(1) 520  
2 *(M2 = 2)(1) 660  
2 *(M2 = 2)(1) 800  
2 *(M2 = 2)(1)  
UT_M2  
Locked  
Frequency  
ARM_FCLK  
IVA_CLK  
DPLL1CLKO 300  
UT_M2  
1
1
600  
520  
1
1
800  
660  
1
1
1000  
800  
1
1
DPLL2CLKO 260  
UT_M2  
(1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference  
Manual (SPRUGN4).  
(2) OPP1G is a high performance operating point which has following requirements:  
–
ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1mF capacitor connected  
to cap_vdd_bb_mpu_iva.  
–
AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage.  
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4.3.5 Device Core Clocks  
Table 4-21 and Table 4-22 show the device core clocks AC performance values.  
Table 4-21. Device Core Voltages  
RETENTION  
OPP50  
OPP100  
MIN  
0.8  
MIN  
0.90  
TYP  
0.95  
MAX  
1.00  
MIN  
1.08  
TYP  
1.14  
MAX  
1.20  
VDD2 (2)(1) (V)  
(1) At ball level.  
(2) Values are defined when SmartReflexTM feature is deactivated. They can be lower when SmartReflexTM is activated.  
Table 4-22. Device Core Clocks  
OPP50  
OPP100  
Descripti Source  
on  
Max  
Freq.(MH  
z)  
Ratio  
-
Max  
Freq.(MH  
z)  
Ratio  
Max  
Freq.(MH  
z)  
Ratio  
-
Max  
Freq.(MH  
z)  
Ratio  
-
Max  
Freq.(MH  
z)  
Ratio  
Max  
Freq.(MH  
z)  
Ratio  
-
DPLL3  
Locked  
Frequenc  
y
-
800  
664  
-
400  
800  
664  
-
532  
DPLL3C DPLL3  
LKOUT_ Locked  
200  
2 *(M2 = 166  
2)(1)  
2 *(M2 = 200  
1)(1)  
2 *(M2 = 400  
1)(1)  
2 *(M2 = 332  
1)(1)  
2 *(M2 = 266  
1)(1)  
2 *(M2 =  
1)(1)  
M2  
Frequenc  
y
CORE_C DPLL3C 200  
1
166  
83  
1
200  
100  
1
400  
200  
1
332  
166  
1
266  
133  
1
LK  
LKOUT_  
M2  
L3_ICLK CORE_C 100  
LK  
2(1)  
2(1)  
2(1)  
2(1)  
2(1)  
2(1)  
L4_ICLK L3_ICLK 50  
2(1)  
1
41.5  
83  
2(1)  
1
50  
2(1)  
1
100  
200  
2(1)  
1
83  
2(1)  
1
66.5  
133  
2(1)  
1
SDRC_C L3_ICLK 100  
LK  
100  
166  
GPMC_C L3_ICLK 50  
LK  
2(1)  
41.5  
2(1)  
50  
2(1)  
100  
2(1)  
83  
2(1)  
66.5  
2(1)  
(1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference  
Manual (SPRUGN4).  
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5 Video DAC Specifications  
NOTE  
For more information regarding the VideoDAC architecture, see the Display Subsystem /  
Display Subsystem Functional Description / Video Encoder Functionalities / Video DAC  
Stage—Architecture and Control section of AM/DM37x Technical Reference Manual  
(literature number SPRUGN4).  
5.1 TVOUT Buffer Mode (DAC + Buffer)  
NOTE  
AVDAC normal mode (DAC + Buffer), higher values of the DAC input code provided by the  
Video Encoder will result in lower output voltage due to the inverting configuration of the  
TVOUT Buffer. See Figure 5-4 for more details on the relation between the composite video  
signal levels and the DAC code values for normal mode of operation.  
In AVDAC bypass mode (DAC only), higher values of the DAC input code will result in higher  
output voltage, as the TVOUT Buffer path is bypassed.  
The connection for this TVOUT buffer mode (DAC + Buffer) normal mode of operation is shown in  
Figure 5-1. The default mode of operation is dc coupling. For more information regarding the  
recommended values of the external components, see Section 5.4, Electrical Specifications Over  
Recommended Operating Conditions.  
AVDAC  
vssa_dac  
vdda_dac  
cvideo1_out  
I DAC  
+
TVBUF  
RLOAD  
–
ROUT  
cvideo1_vfb  
TVDET  
VREF  
cvideo1_rset  
RSET  
= External pin  
swps038-125  
Figure 5-1. Recommended Loading Conditions for TVOUT Buffer Mode(1)  
(1) In single-channel configuration only channel-1 is used.  
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5.2 TVOUT Bypass Mode (DAC Only)  
In this case, TVOUT bypass input is high and the TVOUT buffer is bypassed (for more information, see  
Section 5.5, TVOUT Bypass Mode Specifications (DAC-Only) Electrical Specifications Over  
Recommended Operating Conditions). Figure 5-2 shows the connection. For more information regarding  
the recommended values of the external components, see Section 5.4, Electrical Specifications Over  
Recommended Operating Conditions.  
AVDAC  
vssa_dac  
vdda_dac  
I DAC  
+
TVBUF  
cvideo1_out  
–
OFF  
cvideo1_vfb  
RLOAD  
TVDET  
OFF  
VREF  
cvideo1_rset  
RSET  
= External pin  
swps038-131  
Figure 5-2. Recommended Loading Conditions for TVOUT Bypass Mode(1)  
(1) In single-channel configuration only channel-1 is used.  
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5.3 TVOUT Bypass Mode in Dual-Channel Configuration  
In this case, TVOUT bypass input is high and the TVOUT buffer is bypassed (for more information, see  
Section 5.5, TVOUT Bypass Mode Specifications (DAC-Only) Electrical Specifications Over  
Recommended Operating Conditions). Figure 5-3 shows the connection. For more information regarding  
the recommended values of the external components, see Section 5.4, Electrical Specifications Over  
Recommended Operating Conditions.  
Figure 5-3. Recommended Loading Conditions for TVOUT Bypass Mode in Dual-Channel Configuration(1)  
(1) Here are some connections recommendations:  
–
–
–
An external resistor RSET = 10 kΩ (±1%) is recommended to be connected to the cvideo1_rset signal of Channel 1.  
The cvideo1_rset signal of Channel 2 is left unconnected.  
External resistors RLOAD1LOAD2 = 1.5 kΩ (±1%) is recommended to be connected to cvideo1_vfb or cvideo2_vfb each channel.  
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5.4 Electrical Specifications Over Recommended Operating Conditions  
NOTE  
High-swing mode is the default mode. The low-swing mode is not compliant with the NTSC  
and PAL video-standards. It shall be used only for backwards compatibility to AM/DM37x.  
•
•
•
TVOUT DC High Swing Mode:  
–
–
–
–
ROUT1/2 = 2.7 kΩ (±1%)  
RSET = 4.7 kΩ (±1%)  
RLOAD = 75 Ω (±5%)  
ZCABLE = 75 Ω (±5%)  
TVOUT DC Low Swing Mode:  
–
–
–
–
ROUT1/2 = 2.7 kΩ (±1%)  
RSET = 6.8 kΩ (±1%)  
RLOAD = 75 Ω (±5%)  
ZCABLE = 75 Ω (±5%)  
TVOUT AC High Swing Mode:  
–
–
–
–
–
ROUT1/2 = 2.7 kΩ (±1%)  
RSET = 4.7 kΩ (±1%)  
RLOAD = 75 Ω (±5%)  
ZCABLE = 75 Ω (±5%)  
CAC = 220 µF (±5%)  
•
TVOUT AC Low Swing Mode:  
–
–
–
–
–
ROUT1/2 = 2.7 kΩ (±1%)  
RSET = 6.8 kΩ (±1%)  
RLOAD = 75 Ω (±5%)  
ZCABLE = 75 Ω (±5%)  
CAC = 220 µF (±5%)  
Table 5-1. DAC – Static Electrical Specifications(8)  
PARAMETER  
Resolution  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
R
10  
Bits  
DC ACCURACY  
INL(1)  
Integral Non-Linearity (INL)  
50 to 111 input code range  
111 to 895 input code range  
–6  
–4  
6
4
LSB  
Integral Non-Linearity (INL)  
Signal video range  
Integral Non-Linearity (INL)  
Synchronization pulse  
783 to 1007 input code range  
111 to 895 input code range  
–5  
5
DNL(2)  
Differential nonlinearity  
–2.5  
2.5  
LSB  
V
ANALOG OUTPUT  
-
Output voltage  
0 to 1023 input Low-swing mode  
0.70  
1.2  
0.88  
1.3  
1.00  
1.5  
code range,  
High-swing mode  
RLOAD = 75 Ω  
-
Gain error  
-
Low-swing mode  
High-swing mode  
–20  
–10  
67.5  
20  
10  
% FS  
Ω
RVOUT  
Output impedance  
75.0  
0.55  
82.5  
REFERENCE  
VREF  
Internal Band Gap Voltage Reference  
V
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Table 5-1. DAC – Static Electrical Specifications(8) (continued)  
PARAMETER  
POWER CONSUMPTION  
Ivdda-up Analog Supply  
Current(4)  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
DC mode No  
load  
Average current on vdda_dac, no  
load, 2 channels  
Input code 50 (maximum output  
voltage)  
4.5  
19  
19  
6.5  
28  
28  
60  
8.5  
37  
37  
mA  
AC mode No  
load  
Full load 75-Ω  
load  
Ivdda-up (peak) Peak analog supply current  
Lasts less than 1 ns  
mA  
mA  
Ivdd-up  
Digital supply current(5)  
Average current, measured at fCLK  
2
= 54 MHz,  
fOUT = 2 MHz sine wave, vdd = 1.1  
V
Ivdd-up (peak)  
Peak digital supply current(6)  
Peak current, full-scale transition  
lasting less than 1 ns  
8
mA  
mA  
mA  
(9)  
Ivdda-down  
Analog supply current, total power  
down(9)  
Analog supply current, standby mode(9)  
T = 30ºC, vdda_dac = 1.8 V, no  
load  
12  
(9)  
Ivdda-stdby  
Bandgap and internal LDO are ON,  
all other analog blocks are OFF, no  
load, T = 30 Cº  
90  
180  
270  
(9)  
Ivdd-down(pm)  
Digital supply current, total power  
down(9)  
T = 30ºC, Full  
or Partial Power  
Management  
Low-swing mode  
High-swing mode  
2
6
mA  
mA  
Ivdd-down(nopm) Digital supply current, total power down  
(no power management)  
T = 30ºC, VDD = 1.1 V, no Power  
Management  
60  
(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.  
(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.  
(3) Reference PSR measures the effect of a supply disturbance at cvideo1_out and cvideo2_out.  
(4) The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK  
.
(5) The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.  
(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.  
(7) See Section 5.6, Analog Supply (vdda_dac) Noise Requirements, for actual maximum ripple allowed on vdda_dac.  
(8) For more information on code range definition, see Figure 5-4.  
(9) For more information on AVDAC power-up, power-down, and standby mode configurations, see Display Subsystem / Display  
Subsystem Functional Description / Video Encoder Functionalities / Video DAC Stage Power Management section of AM/DM37x  
Technical Reference Manual (literature number SPRUGN4).  
NOTE  
High-swing mode is the default mode. The low-swing mode is not compliant with the NTSC  
and PAL video-standards. It is used only for backwards compatibility to AM/DM37x.  
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Table 5-2. Video DAC – Dynamic Electrical Specifications(6)  
PARAMET  
ER  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
(1)  
fCLK  
Output update rate  
Clock jitter  
Equal to input clock frequency  
54  
40  
60  
70  
MHz  
ps  
RMS clock jitter required in order to  
assure 10-bit accuracy  
Attenuation at 5.1 MHz  
Signal bandwidth  
Corner frequency for  
signal  
DC mode  
AC mode  
DC mode  
AC mode  
DC mode  
AC mode  
DC mode  
AC mode  
DC mode  
AC mode  
1.5  
dB  
BW  
3 dB  
6
MHz  
Differential gain(2)  
Differential phase(2)  
111 to 895 input code  
range  
–5%  
–5%  
–3º  
–3º  
40  
5%  
5%  
3º  
111 to 895 input code  
range  
3º  
SFDR  
SNR  
Within bandwidth 1 kHz to fCLK = 54 MHz, fOUT = 1  
6 MHz  
50  
54  
70  
dB  
dB  
MHz, sine wane input,  
111 to 895 input code  
range  
Within bandwidth 1 kHz to fCLK = 54 MHz, fOUT = 1  
6 MHz  
DC mode  
AC mode  
50  
75  
MHz, sine wane input,  
256 to 768 input code  
range  
PSR(4)  
Crosstalk  
CLoad  
Power supply rejection (up 100 mVpp at 6 MHz, input code 895  
to 6 MHz)  
6(4)  
dB  
dB  
pF  
Between the two video  
channels  
–50  
–40  
300  
TVOUT (cvideo_out1 and Total decoupling capacity from  
cvideo_out2) stability,  
TVOUT decoupling  
capacity  
cvideo_out1 or cvideo_out2 to ground,  
CLoad1  
CTOT  
TVOUT stability, total  
TVOUT decoupling  
capacity  
Total decoupling capacity: CTOT = CLoad1  
+ CLoad2  
600  
pF  
(1) For internal input clock information, see the DSS chapter of AM/DM37x Technical Reference Manual (literature number SPRUGN4).  
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling. The Differential Gain and  
Phase are measured with respect to the gain and phase of the burst signal (–20 to 20 IRE)  
(3) The SNR value is for dc coupling.  
(4) PSR measures the effect of a supply disturbance at cvideo1_out and cvideo2_out.  
(5) The flat band measurement is done at 500 kHz for characterizing the attenuation at 5.1 MHz.  
(6) For more information on code range definition, see Figure 5-4.  
Figure 5-4 describes the composite video signal levels.  
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10-bit  
DAC code  
IRE  
units  
TVOUT  
Normal  
mode  
0
140  
131  
120  
50  
Peak level  
White level  
111  
223  
100  
1.3 Vpp  
*
ANDARD  
ST  
VIDEO  
20  
741  
783  
Black level  
Blanking level  
7.5  
0
RANGE  
895  
-20  
1007  
1023  
Sync level  
-40  
SWPS038-130  
Figure 5-4. Composite Video Signal Levels(1)(2)  
(1) The 1.3 VPP (peak-to-peak) is referring to the output signal at cvideo1_out in the DAC + Buffer composite-video mode.  
Note that the 1.3 VPP must apply to both cvideo1_out and cvideo2_out in DAC + Buffer s-video mode (dual-DAC mode configured for ac  
or dc coupling).  
(2) In AVDAC normal mode (DAC + Buffer), higher values of the DAC input code provided by the Video Encoder will result in lower output  
voltage due to the inverting configuration of the TVOUT Buffer. See Figure 5-4 for more details on the relation between the composite  
video signal levels and the DAC code values for normal mode of operation.  
In AVDAC bypass mode (DAC only), higher values of the DAC input code will result in higher output voltage, as the TVOUTBuffer path  
is bypassed.  
5.5 TVOUT Bypass Mode Specifications (DAC-Only) Electrical Specifications Over  
Recommended Operating Conditions  
NOTE  
The electrical characteristics for single- and dual-channel bypass modes are the same  
except that the active current will double in the dual-channel configuration.  
•
Bypass Mode  
–
–
RLOAD = 1.5 kΩ (±1%)  
RSET = 10 kΩ (±1%)  
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Table 5-3. DAC—Static Electrical Specifications—Bypass Mode(2)  
PARAMETER  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
MAX  
UNIT  
R
Resolution  
10  
Bits  
DC ACCURACY  
INL(1)  
DNL(1)  
Integral nonlinearity (INL)  
Differential nonlinearity  
37 to 954 input code range, RLOAD = 1.5 kΩ  
37 to 954 input code range, RLOAD = 1.5 kΩ  
–1  
–1  
1
1
LSB  
LSB  
ANALOG OUTPUT  
-
-
-
Output voltage  
RLOAD = 1.5 kΩ  
0.6  
0.6  
0.7  
0.7  
0.77  
0.77  
10  
V
V
Output current  
Gain error  
RLOAD = 1.5 kΩ  
-
–10  
% FS  
POWER CONSUMPTION  
Ivdda-up  
Analog supply current  
Average current on vdda_dac, RLOAD = 1.5 kΩ  
Input code 1023  
0.7  
1.0  
1.4  
12  
mA  
mA  
mA  
Ivdda-down  
Ivdda-stdby  
Analog supply current, total  
power down  
T = 30Cº, vdda_dac = 1.8 V, no load  
Analog supply current,  
standby mode  
Bandgap and internal LDO are ON, all other  
analog blocks are OFF, no load, T = 30Cº  
90  
180  
270  
(1) In bypass mode, output node is cvideo1_out and cvideo2_out nodes. For more information, see Section 5.2, TVOUT Bypass Mode  
(DAC Only) or Section 5.3, TVOUT Bypass Mode in Dual-Channel Configuration.  
(2) For more information on code range definition, see Figure 5-4.  
Table 5-4. Video DAC—Dynamic Electrical Specifications—Bypass Mode  
PARAMETER  
Output update rate  
Clock jitter  
CONDITIONS/ASSUMPTIONS  
MIN  
TYP  
54  
MAX  
60  
UNIT  
MHz  
ps  
fCLK  
Equal to input clock frequency  
RMS clock jitter required in order to  
assure 10-bit accuracy  
40  
70  
BW  
Signal bandwidth  
3dB  
6
MHz  
dB  
SFDR  
Within bandwidth 1 kHz to 6 MHz  
fCLK = 54 MHz, fOUT = 1 MHz, sine  
wave input, 111 to 895 input code  
range  
40  
50  
50  
70  
75  
SNR  
PSR  
Within bandwidth 1 kHz to 6 MHz  
fCLK = 54 MHz, fOUT = 1 MHz, sine  
wave input, 256 to 768 input code  
range  
54  
dB  
dB  
Power supply rejection (up to 6 MHz)  
100 mVpp at 6 MHz, input code 895  
6(1)  
(1) For more information on code range definition, see Figure 5-4.  
5.6 Analog Supply (vdda_dac) Noise Requirements  
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the  
noise requirements stated in this section.  
The DAC Power Supply Rejection Ratio (PSRR) is defined as the relative variation of the full-scale output  
current divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per  
volt  
of  
supply  
variation  
as  
shown  
in  
the  
following  
equation:  
Depending on frequency, the PSRR is defined in Table 5-5.  
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Table 5-5. Video DAC – Power Supply Rejection Ratio  
Supply Noise  
Frequency  
PSRR % FSR/V  
0 to 100 kHz  
> 100 kHz  
1
The rejection decreases 20 dB/dec.  
Example: at 1 MHz the PSRR is 10% of FSR/V.  
A graphic representation is shown in Figure 5-5.  
Figure 5-5. Video DAC – Power Supply Rejection Ratio  
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements  
translate to the following limits on vdda_dac (for the Video DAC).  
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-6.  
Table 5-6. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac  
Tone Frequency  
0 to 100 kHz  
> 100 kHz  
Maximum Peak-to-Peak Noise on vdda_dac  
< 30 mVPP  
Decreases 20 dB/dec.  
Example: at 1 MHz the maximum is 3 mVPP  
The maximum noise spectral density (white noise) is defined in Table 5-7.  
Table 5-7. Video DAC – Maximum Noise Spectral Density  
Supply Noise Bandwidth  
0 to 100 kHz  
Maximum Supply Noise Density  
< 20 µV / √Hz  
> 100 kHz  
Decreases 20 dB/dec.  
Example: at 1 MHz the maximum noise density is 2 µV / √Hz  
Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to  
have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.7, External  
Component Value Choice).  
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5.7 External Component Value Choice  
The output current IDACOUT appearing at the output of the 10-bit DAC is a function of both the input code  
DAC_CODE (ranging from 0 to 1023) and IDACMAX and can be expressed as:  
IDACOUT = IREF * (DAC_CODE / 120) (1)  
The maximum output current IDACMAX from the DAC is given by:  
IDACMAX = IREF * 1023 / 120 (2)  
The reference current, IREF, is set by a combination of internal and external resistors in series, RREF, and  
an internal reference voltage, VREF, and is given by:  
IREF = VREF / RREF (3)  
Typically, VREF = 0.55 V and RREF = 9.4 kΩ (RREF includes both internal and external resistor, 4.7 kΩ each,  
typically)  
The video signal voltage at cvideo_out1 and cvideo_out2 nodes can be written as (excluding the offset  
voltage):  
VTVOUT = 35 * RLOAD * IDACMAX * (1 – DAC_CODE / 1023) (4)  
Figure 5-6 shows the cvideo_out1 and cvideo_out2 transfer function. Regarding the typical composite  
video signal levels versus the DAC input code, for more information on code range definition, see  
Figure 5-4.  
Regarding the typical values of the typical values for Rout1/2 and Rset resistors, as well for Cout capacitor,  
for different modes of the TV display interface, see the Display Subsystem / Display Subsystem  
Environment / TV Display Support section of AM/DM37x Technical Reference Manual (literature number  
SPRUGN4).  
Figure 5-6. cvideo_out1 and cvideo_ou2 Transfer Function  
NOTE  
The dc levels (Voffset) will be shifted due to process variations.  
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6 Timing Requirements and Switching Characteristics  
6.1 Timing Test Conditions  
All timing requirements and switching characteristics are valid over the recommended operating conditions  
unless otherwise specified.  
6.2 Interface Clock Specifications  
6.2.1 Interface Clock Terminology  
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly  
with the interface protocol.  
6.2.2 Interface Clock Frequency  
The two interface clock characteristics are:  
•
•
The maximum clock frequency  
The maximum operating frequency  
The interface clock frequency documented in this document is the maximum clock frequency, which  
corresponds to the maximum frequency programmable on this output clock. This frequency defines the  
maximum limit supported by the device IC and doesn’t take into account any system consideration (PCB,  
Peripherals).  
The system designer will have to consider these system considerations and the device IC timing  
characteristics as well, to define properly the maximum operating frequency, which corresponds to the  
maximum frequency supported to transfer the data on this interface.  
6.2.3 Clock Jitter Specifications  
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this  
document is the time difference between the typical cycle period and the actual cycle period affected by  
noise sources on the clock. The cycle (or period) jitter terminology will be used to identify this type of jitter.  
Tn–1  
Tn  
Tn+1  
SWPS038-013  
Figure 6-1. Cycle (or Period) Jitter  
NOTE  
Max. Cycle Jitter = Max (Ti)  
Min. Cycle Jitter = Min (Ti)  
Jitter Standard Deviation (or RMS Jitter) = Standard Deviation (Ti)  
6.2.4 Clock Duty Cycle Error  
The maximum duty cycle error is the difference between the absolute value of the maximum high-level  
pulse duration or the maximum low-level pulse duration and the typical pulse duration value.  
•
•
Maximum pulse duration = Typical pulse duration + maximum duty cycle error  
Minimum pulse duration = Typical pulse duration - maximum duty cycle error  
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6.3 Timing Parameters  
The timing parameter symbols used in the timing requirements and switching characteristics tables are  
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other  
related terminologies have been abbreviated as follows:  
Table 6-1. Timing Parameters  
SUBSCRIPTS  
SYMBOL  
PARAMETER  
c
d
Cycle time (period)  
Delay time  
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
X
Unknown, changing, or don’t care level  
F
Fall time  
High  
H
L
Low  
R
Rise time  
Valid  
V
IV  
AE  
FE  
LE  
Z
Invalid  
Active edge  
First edge  
Last edge  
High impedance  
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6.4 External Memory Interfaces  
The device includes the following external memory interfaces:  
•
•
General-purpose memory controller (GPMC)  
SDRAM controller (SDRC)  
6.4.1 General-Purpose Memory Controller (GPMC)  
NOTE  
For more information, see Memory Subsystem / General-Purpose Memory Controller section  
of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
The GPMC is the unified memory controller used to interface external memory devices such as:  
•
•
•
Asynchronous SRAM-like memories and ASIC devices  
Asynchronous page mode and synchronous burst NOR flash  
NAND flash  
6.4.1.1 GPMC/NOR Flash—Synchronous Mode  
Table 6-3 and Table 6-4 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-2 through Figure 6-6).  
Table 6-2. GPMC/NOR Flash Timing Conditions—Synchronous Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
1.8  
1.8  
ns  
ns  
Output Conditions  
CLOAD  
Output load capacitance(1)  
12  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
Table 6-3. GPMC/NOR Flash Timing Requirements—Synchronous Mode(1)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
F12  
F13  
F21  
F22  
tsu(dV-clkH)  
th(clkH-dV)  
tsu(waitV-clkH)  
th(clkH-waitV)  
Setup time, input data gpmc_d[15:0] valid before  
output clock gpmc_clk high  
2.3  
1.5  
2.3  
1.9  
2.3  
ns  
ns  
ns  
ns  
Hold time, input data gpmc_d[15:0] valid after output  
clock gpmc_clk high  
Setup time, input wait gpmc_waitx(2) valid before  
output clock gpmc_clk high  
Hold time, input wait gpmc_waitx(2) valid after output  
clock gpmc_clk high  
1.5  
2.3  
1.9  
(1) See Section 4.3.4, Processor Clocks.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Table 6-4. GPMC/NOR Flash Switching Characteristics—Synchronous Mode(2) (18)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
100  
0.5P(12)  
0.5P(12)  
OPP50  
MIN MAX  
100  
0.5P(12)  
0.5P(12)  
UNIT  
F0  
F1  
F1  
1 / tc(clk)  
tw(clkH)  
tw(clkL)  
Frequency(15), output clock gpmc_clk  
MHz  
ns  
Typical pulse duration, output clock gpmc_clk high  
Typical pulse duration, output clock gpmc_clk low  
ns  
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Table 6-4. GPMC/NOR Flash Switching Characteristics—Synchronous Mode(2) (18) (continued)  
NO.  
PARAMETER  
OPP100  
MIN  
–500  
OPP50  
MIN  
–500  
UNIT  
MAX  
500  
33.33  
1.6  
1.6  
2
MAX  
500  
33.33  
1.6  
1.6  
2
tdc(clk)  
tJ(clk)  
Duty cycle error, output clock gpmc_clk  
Jitter standard deviation(16), output clock gpmc_clk  
Rise time, output clock gpmc_clk  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
tR(clk)  
tF(clk)  
Fall time, output clock gpmc_clk  
tR(do)  
Rise time, output data gpmc_d[15:0]  
Fall time, output data gpmc_d[15:0]  
tF(do)  
2
2
F2  
F3  
F4  
F5  
F6  
td(clkH-ncsV)  
Delay time, output clock gpmc_clk rising edge to  
output chip select gpmc_ncsx(11) transition  
F(6) – 1.9 F(6) + 3.3 F(6) – 1.9 F(6) + 3.3  
E(5) – 1.9 E(5) + 3.3 E(5) – 1.9 E(5) + 3.3  
B(2) – 4.1 B(2) + 2.1 B(2) – 4.1 B(2) + 2.1  
td(clkH-ncsIV)  
td(aV-clk)  
td(clkH-aIV)  
td(nbeV-clk)  
Delay time, output clock gpmc_clk rising edge to  
output chip select gpmc_ncsx(11) invalid  
ns  
ns  
ns  
ns  
Delay time, output address gpmc_a[27:1] valid to  
output clock gpmc_clk first edge  
Delay time, output clock gpmc_clk rising edge to  
output address gpmc_a[27:1] invalid  
–2.1  
–2.1  
Delay time, output lower byte enable/command latch  
enable gpmc_nbe0_cle, output upper byte enable  
gpmc_nbe1 valid to output clock gpmc_clk first edge  
B(2) – 1.2 B(2) + 2.2 B(2) – 1.2 B(2) + 2.2  
D(4) – 2.2 D(4) + 1.2 D(4) – 2.2 D(4) + 1.2  
F7  
td(clkH-nbeIV)  
Delay time, output clock gpmc_clk rising edge to  
output lower byte enable/command latch enable  
gpmc_nbe0_cle, output upper byte enable gpmc_nbe1  
invalid  
ns  
F8  
F9  
td(clkH-nadv)  
Delay time, output clock gpmc_clk rising edge to  
output address valid/address latch enable  
gpmc_nadv_ale transition  
G(7) + 0.8 G(7) + 2.2 G(7) + 0.8 G(7) + 2.2  
D(4) – 1.9 D(4) + 4.1 D(4) – 1.9 D(4) + 4.1  
ns  
ns  
td(clkH-nadvIV)  
Delay time, output clock gpmc_clk rising edge to  
output address valid/address latch enable  
gpmc_nadv_ale invalid  
F10  
F11  
F14  
F15  
F17  
td(clkH-noe)  
td(clkH-noeIV)  
td(clkH-nwe)  
td(clkH-do)  
Delay time, output clock gpmc_clk rising edge to  
output enable gpmc_noe transition  
H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1  
E(5) – 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1  
I(9) – 1.9 I(9) + 4.1 I(9) – 1.9 I(9) + 4.1  
ns  
ns  
ns  
ns  
ns  
Delay time, output clock gpmc_clk rising edge to  
output enable gpmc_noe invalid  
Delay time, output clock gpmc_clk rising edge to  
output write enable gpmc_nwe transition  
Delay time, output clock gpmc_clk rising edge to  
output data gpmc_d[15:0] transition  
J(10)  
1.7  
–
–
J(10)  
1.2  
+
+
J(10)  
1.7  
–
–
J(10)  
1.2  
+
+
td(clkH-nbe)  
Delay time, output clock gpmc_clk rising edge to  
output lower byte enable/command latch enable  
gpmc_nbe0_cle transition  
J(10)  
2.2  
J(10)  
1.2  
J(10)  
2.2  
J(10)  
1.2  
F18  
F19  
tw(ncsV)  
Pulse duration, output chip select  
gpmc_ncsx(11) low  
Read  
Write  
Read  
Write  
A(1)  
A(1)  
C(3)  
C(3)  
A(1)  
A(1)  
C(3)  
C(3)  
ns  
ns  
ns  
ns  
tw(nbeV)  
Pulse duration, output lower byte  
enable/command latch enable  
gpmc_nbe0_cle, output upper byte enable  
gpmc_nbe1 low  
F20  
F23  
F24  
tw(nadvV)  
Pulse duration, output address  
valid/address latch enable gpmc_nadv_ale  
low  
Read  
Write  
K(13)  
K(13)  
K(13)  
K(13)  
ns  
ns  
td(clkH-iodir)  
Delay time, output clock gpmc_clk rising edge to  
output IO direction control gpmc_io_dir high (IN  
direction)  
H(8) – 2.1 H(8) + 4.1 H(8) – 2.1 H(8) + 4.1  
ns  
td(clkH-iodirIV)  
Delay time, output clock gpmc_clk rising edge to  
output IO direction control gpmc_io_dir low (OUT  
direction)  
M(17)  
2.1  
–
M(17)  
4.1  
+
M(17)  
2.1  
–
M(17)  
4.1  
+
ns  
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(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
With n being the page burst access number.  
(2) B = ClkActivationTime * GPMC_FCLK(14)  
(14)  
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK  
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
With n being the page burst access number.  
(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
(6) For nCS falling edge (CS activated):  
–
Case GpmcFCLKDivider = 0:  
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime  
are even)  
–
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime) is a multiple of 3)  
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)  
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)  
(7) For ADV falling edge (ADV activated):  
–
Case GpmcFCLKDivider = 0:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and  
ADVOnTime are even)  
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
–
Case GpmcFCLKDivider = 0:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Writing mode:  
–
Case GpmcFCLKDivider = 0:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)  
(8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):  
–
–
Case GpmcFCLKDivider = 0: o H = 0.5 * OEExtraDelay * GPMC_FCLK(14)  
Case GpmcFCLKDivider = 1:  
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime  
are even)  
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime) is a multiple of 3)  
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–
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)  
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
–
Case GpmcFCLKDivider = 0:  
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime  
are even)  
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime) is a multiple of 3)  
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)  
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)  
(9) For WE falling edge (WE activated):  
–
Case GpmcFCLKDivider = 0:  
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14)  
–
Case GpmcFCLKDivider = 1:  
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime  
are even)  
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime) is a multiple of 3)  
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)  
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
–
Case GpmcFCLKDivider = 0:  
I = 0.5 * WEExtraDelay * GPMC_FCLK  
(14)  
–
–
Case GpmcFCLKDivider = 1:  
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime  
are even)  
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise  
–
Case GpmcFCLKDivider = 2:  
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime) is a multiple of 3)  
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)  
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)  
(10) J = GPMC_FCLK(14)  
(11) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(12) P = gpmc_clk period in ns  
(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the  
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.  
(16) The jitter probability density can be approximated by a Gaussian function.  
(17) M = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both  
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses  
performed to Memory and multiplexed or nonmultiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR  
behaviour is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the AM/DM37x Multimedia  
Device Technical Reference Manual (literature number SPRUGN4).  
(18) See Section 4.3.4, Processor Clocks.  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
F18  
gpmc_ncsx  
F4  
F6  
gpmc_a[10:1]  
Valid Address  
F19  
F7  
gpmc_nbe0_cle  
gpmc_nbe1  
F19  
F6  
F8  
F8  
F20  
F9  
gpmc_nadv_ale  
gpmc_noe  
F10  
F11  
F13  
F12  
D 0  
gpmc_d[15:0]  
gpmc_waitx  
F23  
F24  
OUT  
gpmc_io_dir  
OUT  
IN  
SWPS038-014  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-2. GPMC/NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
gpmc_ncsx  
gpmc_a[10:1]  
gpmc_nbe0_cle  
gpmc_nbe1  
F4  
F6  
Valid Address  
F7  
F7  
F6  
F8  
F8  
F9  
gpmc_nadv_ale  
gpmc_noe  
F10  
F11  
F13  
F13  
F12  
F12  
D 0  
F22  
gpmc_d[15:0]  
gpmc_waitx  
D 1  
D 2  
D 3  
F21  
F23  
F24  
gpmc_io_dir  
OUT  
IN  
OUT  
SWPS038-015  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-3. GPMC/NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)  
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F1  
F1  
F0  
gpmc_clk  
gpmc_ncsx  
F2  
F3  
F4  
F6  
gpmc_a[10:1]  
Valid Address  
F17  
F17  
F17  
F17  
F17  
F17  
gpmc_nbe0_cle  
gpmc_nbe1  
gpmc_nadv_ale  
gpmc_nwe  
F6  
F8  
F8  
F9  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
gpmc_d[15:0]  
gpmc_waitx  
D 0  
D 3  
gpmc_io_dir  
OUT  
SWPS038-016  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-4. GPMC/NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
F7  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nbe1  
F6  
F6  
F4  
Valid  
F7  
Valid  
gpmc_a[27:17]  
(gpmc_a[11:1])  
Address (MSB)  
F5  
F12  
F13  
F4  
F12  
gpmc_a[16:1]  
(gpmc_d[15:0])  
Address (LSB)  
D0  
D1  
D2  
D3  
F9  
F8  
F8  
gpmc_nadv_ale  
gpmc_noe  
F10  
F11  
gpmc_waitx  
F23  
F24  
gpmc_io_dir  
OUT  
IN  
OUT  
SWPS038-017  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-5. GPMC/Multiplexed NOR Flash—Synchronous Burst Read  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
F18  
gpmc_ncsx  
F4  
F6  
F6  
gpmc_a[27:17]  
(gpmc_a[11:1])  
Address (MSB)  
F17  
F17  
F17  
F17  
F17  
F17  
gpmc_nbe1  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_nwe  
F8  
F8  
F20  
F9  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
gpmc_a[16:1]  
(gpmc_d[15:0])  
Address (LSB)  
D 0  
D 3  
F22  
F21  
gpmc_waitx  
gpmc_io_dir  
OUT  
SWPS038-018  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-6. GPMC/Multiplexed NOR Flash—Synchronous Burst Write  
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6.4.1.2 GPMC/NOR Flash—Asynchronous Mode  
Table 6-6 and Table 6-7 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-7 through Figure 6-12).  
Table 6-5. GPMC/NOR Flash Timing Conditions—Asynchronous Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
1.8  
1.8  
ns  
ns  
Output Conditions  
CLOAD  
Output load capacitance(1)  
16  
pF  
(1) The load setting of the IO buffer: LB0 = 0.  
Table 6-6. GPMC/NOR Flash Internal Timing Parameters—Asynchronous Mode(1) (2) (4)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
FI1  
FI2  
FI3  
FI4  
FI5  
FI6  
Delay time, output data gpmc_d[15:0] generation from internal  
functional clock GPMC_FCLK(3)  
6.6  
4.4  
6.5  
7.6  
7.6  
6.5  
7.0  
7.0  
7.0  
7.0  
7.0  
7.0  
ns  
ns  
ns  
ns  
ns  
ns  
Delay time, input data gpmc_d[15:0] capture from internal functional  
clock GPMC_FCLK(3)  
Delay time, output chip select gpmc_ncsx generation from internal  
functional clock GPMC_FCLK(3)  
Delay time, output address gpmc_a[27:1] generation from internal  
functional clock GPMC_FCLK(3)  
Delay time, output address gpmc_a[27:1] valid from internal functional  
clock GPMC_FCLK(3)  
Delay time, output lower-byte enable/command latch enable  
gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 generation  
from internal functional clock GPMC_FCLK(3)  
FI7  
FI8  
Delay time, output enable gpmc_noe generation from internal  
functional clock GPMC_FCLK(3)  
5.8  
7.0  
7.0  
7.0  
ns  
ns  
Delay time, output write enable gpmc_nwe generation from internal  
functional clock GPMC_FCLK(3)  
FI9  
Skew, internal functional clock GPMC_FCLK(3)  
100  
6.3  
170  
7.0  
ps  
ps  
FI10  
Delay time, IO direction generation from internal functional clock  
GPMC_FCLK(3)  
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.  
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.  
(4) See Section 4.3.4, Processor Clocks.  
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UNIT  
Table 6-7. GPMC/NOR Flash Timing Requirements—Asynchronous Mode(7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
FA5(1)  
FA20(3)  
FA21(2)  
tacc(d)  
Data access time  
H(5)  
P(4)  
H(5)  
H(5)  
P(4)  
H(5)  
ns  
ns  
ns  
tacc1-pgmode(d)  
tacc2-pgmode(d)  
Page mode successive data access time  
Page mode first data access time  
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock  
edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by  
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.  
(3) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock  
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)  
(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)  
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(7) See Section 4.3.4, Processor Clocks.  
Table 6-8. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode(16)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
tR(d)  
Rise time, output data gpmc_d[15:0]  
Fall time, output data gpmc_d[15:0]  
Pulse duration, output lower-byte Read  
2
2
2
2
ns  
ns  
ns  
tF(d)  
FA0  
tw(nbeV)  
N(12)  
N(12)  
N(12)  
N(12)  
enable/command latch enable  
Write  
gpmc_nbe0_cle, output  
upper-byte enable gpmc_nbe1  
valid time  
FA1  
FA3  
tw(ncsV)  
Pulse duration, output chip select Read  
A(1)  
A(1)  
A(1)  
A(1)  
ns  
ns  
gpmc_ncsx(13) low  
Write  
td(ncsV-nadvIV)  
Delay time, output chip select  
gpmc_ncsx(13) valid to output  
address valid/address latch  
enable gpmc_nadv_ale invalid  
Read  
Write  
B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6  
B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6  
FA4  
td(ncsV-noeIV)  
Delay time, output chip select gpmc_ncsx(13)  
valid to output enable gpmc_noe invalid  
(Single read)  
C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6  
ns  
FA9  
td(aV-ncsV)  
Delay time, output address gpmc_a[27:1] valid J(9) – 0.2  
J(9) + 2.0  
J(9) + 2.0  
J(9) – 0.2  
J(9) – 0.2  
J(9) + 2.6  
J(9) + 2.6  
ns  
ns  
to output chip select gpmc_ncsx(13) valid  
FA10  
td(nbeV-ncsV)  
Delay time, output lower-byte  
enable/command latch enable  
gpmc_nbe0_cle, output upper-byte enable  
gpmc_nbe1 valid to output chip select  
gpmc_ncsx(13) valid  
J(9) – 0.2  
FA12  
td(ncsV-nadvV)  
Delay time, output chip select gpmc_ncsx(13)  
valid to output address valid/address latch  
enable gpmc_nadv_ale valid  
K(10) – 0.2 K(10) + 2.0 K(10) – 0.2 K(10) + 2.6  
ns  
FA13  
FA14  
td(ncsV-noeV)  
td(ncsV-iodir)  
Delay time, output chip select gpmc_ncsx(13)  
valid to output enable gpmc_noe valid  
Delay time, output chip select gpmc_ncsx(13)  
valid to output IO direction control gpmc_io_dir  
high  
Delay time, output chip select gpmc_ncsx(13)  
valid to output IO direction control gpmc_io_dir  
low  
L(11) – 0.2 L(11) + 2.0  
L
(11) – 0.2 L(11) + 2.6  
ns  
ns  
L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6  
M(14) – 0.2 M(14) + 2.0 M(14) – 0.2 M(14) + 2.6  
FA15  
td(ncsV-iodir)  
ns  
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Table 6-8. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode(16) (continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
MAX  
MIN  
MAX  
FA16  
FA18  
tw(aIV)  
Pulse durationm output address gpmc_a[26:1]  
invalid between 2 successive R/W accesses  
Delay time, output chip select gpmc_ncsx(13)  
valid to output enable gpmc_noe invalid (Burst  
read)  
G(7)  
G(7)  
ns  
ns  
td(ncsV-noeIV)  
I(8) – 0.2  
I(8) + 2.0  
I(8) – 0.2  
I(8) + 2.6  
FA20  
FA25  
FA27  
FA28  
FA29  
FA37  
tw(aV)  
Pulse duration, output address gpmc_a[27:1]  
valid – 2nd, 3rd, and 4th accesses  
Delay time, output chip select gpmc_ncsx(13)  
valid to output write enable gpmc_nwe valid  
Delay time, output chip select gpmc_ncsx(13)  
valid to output write enable gpmc_nwe invalid  
D(4)  
D(4)  
ns  
ns  
ns  
ns  
ns  
ns  
td(ncsV-nweV)  
td(ncsV-nweIV)  
td(nweV-dV)  
td(dV-ncsV)  
td(noeV-aIV)  
E(5) – 0.2 E(5) + 2.0 E(5) – 0.2 E(5) + 2.6  
F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6  
Delay time, output write enable gpmc_ nwe  
valid to output data gpmc_d[15:0] valid  
2.0  
J(9) + 2.0  
2.0  
2.6  
J(9) + 2.6  
2.6  
Delay time, output data gpmc_d[15:0] valid to  
output chip select gpmc_ncsx(13) valid  
J(9) – 0.2  
J(9) – 0.2  
Delay time, output enable gpmc_noe valid to  
output address gpmc_a[16:1]_d[15:0] phase  
end  
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
with n being the page burst access number  
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *  
GPMC_FCLK(15)  
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *  
GPMC_FCLK(15)  
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)  
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)  
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)  
(7) G = Cycle2CycleDelay * GPMC_FCLK(15)  
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *  
GPMC_FCLK(15)  
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK(15)  
(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)  
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(15)  
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(15)  
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(14) M = ((RdCycleTime – CSOnTime) * (TimeParaGranularity + 1) – 0.5 * CSExtraDelay) * GPMC_FCLK(15)  
Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both  
RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses  
performed to Memory and multiplexed or nonmultiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR  
behaviour is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the AM/DM37x Multimedia  
Device Technical Reference Manual (literature number SPRUGN4).  
(15) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(16) See Section 4.3.4, Processor Clocks.  
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GPMC_FCLK  
gpmc_clk  
FA5  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[10:1]  
Valid Address  
FA0  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA10  
FA3  
FA12  
gpmc_nadv_ale  
FA4  
FA13  
gpmc_noe  
Data IN 0  
Data IN 0  
gpmc_d[15:0]  
gpmc_waitx  
FA15  
FA14  
gpmc_io_dir  
OUT  
IN  
OUT  
SWPS038-019  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 6-7. GPMC / NOR Flash—Asynchronous Read—Single Word  
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GPMC_FCLK  
gpmc_clk  
gpmc_ncsx  
FA5  
FA5  
FA1  
FA1  
FA16  
FA9  
FA9  
gpmc_a[10:1]  
Address 0  
FA0  
Address 1  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA0  
Valid  
Valid  
FA10  
FA10  
FA3  
FA3  
FA12  
FA12  
gpmc_nadv_ale  
FA4  
FA4  
FA13  
FA13  
gpmc_noe  
Data Upper  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
FA15  
FA15  
FA14  
FA14  
OUT  
IN  
OUT  
IN  
SWPS038-020  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 6-8. GPMC / NOR Flash—Asynchronous Read—32-bit  
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GPMC_FCLK  
gpmc_clk  
FA20  
Add3  
FA20  
Add1  
FA21  
FA20  
Add2  
FA1  
gpmc_ncsx  
FA9  
Add0  
Add4  
gpmc_a[10:1]  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
FA0  
gpmc_nbe1  
FA12  
gpmc_nadv_ale  
FA18  
FA13  
gpmc_noe  
D3  
D0  
D1  
D2  
D3  
gpmc_d[15:0]  
gpmc_waitx  
FA15  
FA14  
OUT  
gpmc_io_dir  
OUT  
IN  
SWPS038-021  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled  
by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.  
(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active  
functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data  
(excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field.  
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 6-9. GPMC / NOR Flash—Asynchronous Read—Page Mode 4x16-bit  
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gpmc_fclk  
gpmc_clk  
gpmc_ncsx  
FA1  
FA9  
gpmc_a[10:1]  
Valid Address  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
FA0  
FA3  
FA12  
gpmc_nadv_ale  
FA27  
FA25  
gpmc_nwe  
gpmc_d[15:0]  
gpmc_waitx  
gpmc_io_dir  
FA29  
Data OUT  
OUT  
SWPS038-022  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-10. GPMC / NOR Flash—Asynchronous Write—Single Word  
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GPMC_FCLK  
gpmc_clk  
FA1  
FA5  
gpmc_ncsx  
FA9  
gpmc_a[27:17]  
(gpmc_a[11:1])  
Address (MSB)  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
Valid  
FA0  
Valid  
FA3  
FA12  
gpmc_nadv_ale  
gpmc_noe  
FA4  
FA13  
FA29  
FA37  
gpmc_a[16:1]  
(gpmc_d[15:0])  
Data IN  
Data IN  
Address (LSB)  
FA15  
FA14  
gpmc_io_dir  
gpmc_waitx  
OUT  
OUT  
IN  
SWPS038-023  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 6-11. GPMC / Multiplexed NOR Flash—Asynchronous Read—Single Word  
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gpmc_fclk  
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gpmc_clk  
FA1  
gpmc_ncsx  
FA9  
gpmc_a[27:17]  
(gpmc_a[11:1])  
Address (MSB)  
FA0  
FA10  
FA10  
gpmc_nbe0_cle  
gpmc_nbe1  
FA0  
FA3  
FA12  
gpmc_nadv_ale  
gpmc_nwe  
FA27  
FA25  
FA29  
FA28  
gpmc_a[16:1]  
(gpmc_d[15:0])  
Valid Address (LSB)  
Data OUT  
gpmc_waitx  
gpmc_io_dir  
OUT  
SWPS038-024  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-12. GPMC / Multiplexed NOR Flash—Asynchronous Write—Single Word  
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6.4.1.3 GPMC/NAND Flash—Asynchronous Mode  
Table 6-10 and Table 6-11 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-13 through Figure 6-16).  
Table 6-9. GPMC/NAND Flash Timing Conditions—Asynchronous Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
1.8  
1.8  
ns  
ns  
Output Conditions  
CLOAD  
Output load capacitance(1)  
16  
pF  
(1) The load setting of the IO buffer: LB0 = 0.  
Table 6-10. GPMC/NAND Flash Internal Timing Parameters—Asynchronous Mode(1) (2) (4)  
NO.  
PARAMETER  
OPP100  
MAX  
OPP50  
UNIT  
MIN  
MIN  
MAX  
GNFI1  
GNFI2  
GNFI3  
GNFI4  
Delay time, output data gpmc_d[15:0] generation from internal  
functional clock GPMC_FCLK(3)  
6.5  
4.0  
6.5  
6.5  
9.1  
ns  
ns  
ns  
ns  
Delay time, input data gpmc_d[15:0] capture from internal  
functional clock GPMC_FCLK(3)  
5.6  
9.1  
9.1  
Delay time, output chip select gpmc_ncsx generation from  
internal functional clock GPMC_FCLK(3)  
Delay time, output address valid/address latch enable  
gpmc_nadv_ale generation from internal functional clock  
GPMC_FCLK(3)  
GNFI5  
Delay time, output lower-byte enable/command latch enable  
gpmc_nbe0_cle generation from internal functional clock  
GPMC_FCLK(3)  
6.5  
9.1  
ns  
GNFI6  
GNFI7  
GNFI8  
Delay time, output enable gpmc_noe generation from internal  
functional clock GPMC_FCLK(3)  
6.5  
6.5  
100  
9.1  
9.1  
170  
ns  
ns  
ps  
Delay time, output write enable gpmc_nwe generation from  
internal functional clock GPMC_FCLK(3)  
Skew, functional clock GPMC_FCLK(3)  
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.  
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.  
(4) See Section 4.3.4, Processor Clocks.  
Table 6-11. GPMC/NAND Flash Timing Requirements—Asynchronous Mode(4)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
MAX  
MIN  
MAX  
GNF12(1) tacc(d)  
Access time, input data gpmc_d[15:0]  
J(2)  
J(2)  
ns  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(3)  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) See Section 4.3.4, Processor Clocks.  
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Table 6-12. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode(15)  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
tR(d)  
Rise time, output data gpmc_d[15:0]  
Fall time, output data gpmc_d[15:0]  
2
2
2
2
ns  
ns  
ns  
tF(d)  
GNF0  
GNF1  
GNF2  
tw(nweV)  
Pulse duration, output write enable gpmc_nwe  
valid  
A(1)  
A(1)  
td(ncsV-nweV)  
tw(cleH-nweV)  
Delay time, output chip select gpmc_ncsx(13)  
valid to output write enable gpmc_nwe valid  
B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6  
C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6  
ns  
ns  
Delay time, output lower-byte  
enable/command latch enable gpmc_nbe0_cle  
high to output write enable gpmc_nwe valid  
GNF3  
GNF4  
GNF5  
tw(nweV-dV)  
Delay time, output data gpmc_d[15:0] valid to  
output write enable gpmc_nwe valid  
D(4) – 0.2 D(4) + 2.0 D(4) – 0.2 D(4) + 2.6  
E(5) – 0.2 E(5) + 2.0 E(5) – 0.2 E(5) + 2.6  
F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6  
ns  
ns  
ns  
tw(nweIV-dIV)  
tw(nweIV-cleIV)  
Delay time, output write enable gpmc_nwe  
invalid to output data gpmc_d[15:0] invalid  
Delay time, output write enable gpmc_nwe  
invalid to output lower-byte enable/command  
latch enable gpmc_nbe0_cle invalid  
GNF6  
GNF7  
GNF8  
tw(nweIV-ncsIV)  
tw(aleH-nweV)  
tw(nweIV-aleIV)  
Delay time, output write enable gpmc_nwe  
invalid to output chip select gpmc_ncsx(13)  
invalid  
Delay time, output address valid/address latch C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6  
enable gpmc_nadv_ale high to output write  
G(7) – 0.2 G(7) + 2.0 G(7) – 0.2 G(7) + 2.6  
ns  
ns  
ns  
enable gpmc_nwe valid  
Delay time, output write enable gpmc_nwe  
invalid to output address valid/address latch  
enable gpmc_nadv_ale invalid  
F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6  
GNF9  
tc(nwe)  
Cycle time, write  
Delay time, output chip select gpmc_ncsx(13)  
valid to output enable gpmc_noe valid  
H(8)  
H(8)  
ns  
ns  
GNF10  
td(ncsV-noeV)  
I(9) – 0.2  
I(9) + 2.0  
I(9) – 0.2  
I(9) + 2.6  
GNF13  
GNF14  
GNF15  
tw(noeV)  
Pulse duration, output enable gpmc_noe valid  
Cycle time, read  
K(10)  
L(11)  
K(10)  
L(11)  
ns  
ns  
ns  
tc(noe)  
tw(noeIV-ncsIV)  
Delay time, output enable gpmc_noe invalid to M(12) – 0.2 M(12) + 2.0 M(12) – 0.2 M(12) + 2.6  
output chip select gpmc_ncsx(13) invalid  
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)  
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)  
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK(14)  
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK(14)  
(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK(14)  
(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)  
(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)  
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)  
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)  
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK(14)  
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)  
(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK(14)  
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) See Section 4.3.4, Processor Clocks.  
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GPMC_FCLK  
GNF1  
GNF2  
GNF6  
GNF5  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]  
(gpmc_d[15:0])  
Command  
SWPS038-025  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
Figure 6-13. GPMC / NAND Flash—Command Latch Cycle  
GPMC_FCLK  
gpmc_ncsx  
GNF1  
GNF7  
GNF6  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF8  
GNF9  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]  
Address  
(gpmc_d[15:0])  
SWPS038-026  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
Figure 6-14. GPMC / NAND Flash—Address Latch Cycle  
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GPMC_FCLK  
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GNF12  
GNF10  
GNF15  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
GNF14  
GNF13  
gpmc_noe  
gpmc_a[16:1]  
(gpmc_d[15:0])  
DATA  
gpmc_waitx  
SWPS038-027  
(1) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active  
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.  
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.  
Figure 6-15. GPMC / NAND Flash—Data Read Cycle  
GPMC_FCLK  
GNF1  
GNF6  
gpmc_ncsx  
gpmc_nbe0_cle  
gpmc_nadv_ale  
gpmc_noe  
GNF9  
GNF0  
gpmc_nwe  
GNF3  
GNF4  
gpmc_a[16:1]  
(gpmc_d[15:0])  
DATA  
SWPS038-028  
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.  
Figure 6-16. GPMC / NAND Flash—Data Write Cycle  
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6.4.2 SDRAM Memory Controller (SDRC)  
NOTE  
For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem  
section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
The SDRAM controller subsystem module provides connectivity between the processor and external  
DRAM memory components. The module includes support for double-data-rate SDRAM (mobile DDR).  
6.4.2.1 LPDDR Interface  
The LPDDR interface is balled out on the bottom side of the CUS package and on the top side of the POP  
packages. The LPDDR interface on the top of the POP package has been designed for compatibility any  
POP LPDDR device with a matching footprint and compliance with the JEDEC LPDDR-266 specification.  
This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and  
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal  
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory  
system without the need for a complex timing closure process. For more information regarding guidelines  
for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing  
Specification Application Report (literature number SPRAAV0).  
6.4.2.1.1 LPDDR Interface Schematic  
Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1  
x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is  
deleted.  
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LPDDR  
DQ0  
T
sdrc_d0  
T
T
T
T
sdrc_d7  
sdrc_dm0  
sdrc_dqs0  
sdrc_d8  
DQ7  
LDM  
LDQS  
DQ8  
T
T
T
sdrc_d15  
sdrc_dm1  
sdrc_dqs1  
DQ15  
UDM  
UDQS  
LPDDR  
DQ0  
T
sdrc_d16  
T
T
T
T
sdrc_d23  
sdrc_dm2  
sdrc_dqs2  
sdrc_d24  
DQ7  
LDM  
LDQS  
DQ8  
T
T
T
sdrc_d31  
sdrc_dm3  
sdrc_dqs3  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
DQ15  
UDM  
UDQS  
BA0  
BA1  
A0  
T
T
T
BA0  
BA1  
A0  
T
T
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_ncas  
sdrc_nras  
sdrc_nwe  
sdrc_cke0  
sdrc_cke1  
sdrc_clk  
A14  
CS  
A14  
CS  
N/C  
T
T
T
T
CAS  
RAS  
WE  
CAS  
RAS  
WE  
CKE  
CKE  
N/C  
T
CK  
CK  
CK  
CK  
T
sdrc_nclk  
Figure 6-17. DM37x LPDDR High Level Schematic (x16 memories)  
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LPDDR  
DQ0  
T
sdrc_d0  
T
T
T
T
sdrc_d7  
sdrc_dm0  
sdrc_dqs0  
sdrc_d8  
DQ7  
DM0  
DQS0  
DQ8  
T
T
T
sdrc_d15  
sdrc_dm1  
sdrc_dqs1  
DQ15  
DM1  
DQS1  
T
sdrc_d16  
DQ16  
T
T
T
T
sdrc_d23  
sdrc_dm2  
sdrc_dqs2  
sdrc_d24  
DQ23  
DM2  
DQS2  
DQ24  
T
T
T
sdrc_d31  
sdrc_dm3  
sdrc_dqs3  
sdrc_ba0  
sdrc_ba1  
sdrc_a0  
DQ31  
DM3  
DQS3  
BA0  
BA1  
A0  
T
T
T
T
T
sdrc_a14  
sdrc_ncs0  
sdrc_ncs1  
sdrc_ncas  
sdrc_nras  
sdrc_nwe  
sdrc_cke0  
sdrc_cke1  
sdrc_clk  
A14  
CS  
N/C  
N/C  
T
T
T
T
CAS  
RAS  
WE  
CKE  
T
T
CK  
CK  
sdrc_nclk  
Figure 6-18. DM37x LPDDR High Level Schematic (x32 memory)  
6.4.2.1.2 Compatible JEDEC LPDDR Devices  
Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.  
Generally, the LPDDR interface is compatible with x16 and x32 LPDDR266 and LPDDR333 speed grade  
LPDDR devices.  
Table 6-13. Compatible JEDEC LPDDR Devices  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
NOTES  
JEDEC LPDDR Device Speed  
Grade  
(1)  
(2)  
1
LPDDR-266  
See Note  
2
3
JEDEC LPDDR Device Bit Width  
JEDEC LPDDR Device Count  
16  
1
32  
2
Bits  
Devices  
See Note  
JEDEC LPDDR Device Ball  
Count  
4
60  
90  
Balls  
(1) Higher LPDDR speed grades are supported due to inherent JEDEC LPDDR backwards compatibility.  
(2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory  
system.  
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6.4.2.1.3 PCB Stackup  
The minimum stackup required for routing the DM37x is a six layer stack as shown in Table 6-14.  
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size  
of the PCB footprint.  
Table 6-14. DM37x Minimum PCB Stack Up  
LAYER  
TYPE  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
DESCRIPTION  
Top Routing Mostly Horizontal  
Ground  
1
2
3
4
5
6
Power  
Internal Routing  
Ground  
Bottom Routing Mostly Vertical  
Table 6-15. PCB Stack Up Specifications  
NO.  
1
PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
NOTES  
PCB Routing/Plane Layers  
Signal Routing Layers  
2
3
3
Full ground layers under LPDDR routing region  
2
4
Number of ground plane cuts allowed within LPDDR routing region  
0
0
Number of ground reference planes required for each LPDDR routing 1  
layer  
5
6
1
Number of layers between LPDDR routing layer and reference ground 0  
plane  
7
PCB Routing Feature Size  
PCB Trace Width w  
4
4
Mils  
Mils  
Mils  
Mils  
8
9
PCB BGA escape via pad size  
PCB BGA escape via hole size  
Device BGA Pad Size  
18  
8
10  
11  
12  
13  
14  
See Note(1)  
See Note(2)  
LPDDR Device BGA Pad Size  
Single Ended Impedance, ZO  
Impedance Control  
50  
75  
Ω
Ω
Z-5  
Z
Z + 5  
See Note(3)  
(1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.  
(2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.  
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.  
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6.5 Multimedia Interfaces  
6.5.1 Camera ISP2P Interface  
NOTE  
For more information, see Camera ISP chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV  
or JPEG image sensor modules to the device for video-preview, video-record and still-image-capture  
applications.  
The camera ISP2P subsystem supports up to two simultaneous pixel flows but only one of them can use  
the video processing hardware:  
•
Parallel camera interface + Serial camera interface: one interface data goes through the video  
processing hardware. The other interface data goes directly to memory  
•
Serial camera interface + Serial camera interface: one serial interface data goes through the video  
processing hardware. The other serial interface data goes directly to memory.  
The camera ISP2P subsystem supports different camera configurations:  
•
•
•
10-bit Parallel interface  
12-bit Parallel interface  
12-bit Parallel interface  
Note: For more information, see the Camera ISP / Camera ISP Environment / Camera ISP Connectivity  
Schemes section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
6.5.1.1 Camera Output Clocks (cam_xclka and cam_xclkb)  
Table 6-16. ISP2P cam_xclka and cam_xclkb Output Clocks Switching Characteristics  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
ISP15  
ISP16  
ISP16  
1 / tc(xclk) Frequency(1), output clock cam_xclkn(4)  
216  
216  
MHz  
ns  
tw(xclkH)  
tw(xclkL)  
tdc(xclk)  
tJ(xclk)  
Typical pulse duration, output clock cam_xclkn(4) high  
Typical pulse duration, output clock cam_xclkn(4) low  
Duty cycle error, output clock cam_xclkn(4)  
Jitter standard deviation(3), output clock cam_xclkn(4)  
Rise time, output clock cam_xclkn(4)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
ns  
231  
33  
231  
33  
ps  
ps  
tR(xclk)  
tF(xclk)  
0.93  
0.93  
0.93  
0.93  
ns  
Fall time, output clock cam_xclkn(4)  
ns  
(1) Related with the cam_xclkn(4) maximum and minimum frequencies programmable in the ISP module.  
NOTE: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(2) P = cam_xclkn(4) period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) In cam_xclkn, n is equal to a or b.  
6.5.1.2 Parallel Camera Interface (CPI)  
6.5.1.2.1 CPI—Video and Graphics Digitizer 1.8V Mode  
The imaging subsystem deals with the processing of the pixel data coming from an external image sensor  
or from video and graphics digitizer. It is a key component for the following multimedia applications: video  
preview, camera viewfinder, video record and still image capture. It supports RAW, RGB, and YUV data  
processing.  
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Table 6-18 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-19 and Figure 6-20).  
Table 6-17. CPI Timing Conditions—Video and Graphics Digitizer 1.8-V Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
80  
80  
1800  
1800  
ps  
ps  
Table 6-18. CPI Timing Requirements—Video and Graphics Digitizer 1.8-V Mode(4) (6)  
NO.  
PARAMETER  
OPP100  
MAX  
148.5  
0.5P(2)  
0.5P(2)  
UNIT  
MIN  
ISP1  
ISP2  
ISP3  
1 / tc(pclk)  
tw(pclkL)  
tw(pclkH)  
tdc(pclk)  
Frequency(1), input pixel clock cam_pclk  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk low  
Typical pulse duration, input pixel clock cam_pclk high  
Duty cycle error, input pixel clock cam_pclk  
ns  
0.5*P(2)  
3.247  
-
ns  
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.06P(2)  
ns  
ns  
ISP4  
ISP5  
tsu(vsV-pclkH)  
Setup time, input vertical synchronization cam_vs valid before input  
pixel clock cam_pclk rising/falling edge  
0.75  
0.96  
0.75  
0.96  
0.75  
0.96  
0.75  
0.96  
0.75  
0.96  
th(pclkH-vsV)  
tsu(hsV-pclkH)  
th(pclkH-hsV)  
tsu(dV-pclkH)  
th(pclkH-dV)  
Hold time, input vertical synchronization cam_vs valid after input pixel  
clock cam_pclk rising/falling edge  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ISP6  
Setup time, input horizontal synchronization cam_hs valid before input  
pixel clock cam_pclk rising/falling edge  
ISP7  
Hold time, input horizontal synchronization cam_hs valid after input  
pixel clock cam_pclk rising/falling edge  
Setup time, input data cam_d[n:0](5) valid before input pixel clock  
cam_pclk rising/falling edge  
Hold time, input data cam_d[n:0](5) valid after input pixel clock  
cam_pclk rising/falling edge  
ISP8  
ISP9  
ISP10  
ISP11  
ISP12  
ISP13  
tsu(wenV-pclkH)  
th(pclkH-wenV)  
tsu(fldV-pclkH)  
th(pclkH-fldV)  
Setup time, input write enable cam_wen valid before input pixel clock  
cam_pclk rising/falling edge  
Hold time, input write enable cam_wen valid after input pixel clock  
cam_pclk rising/falling edge  
Setup time, input field identification cam_fld valid before input pixel  
clock cam_pclk rising/falling edge  
Hold time, input field identification cam_fld valid after input pixel clock  
cam_pclk rising/falling edge  
(1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) n = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). Lines not connected must be  
tied low.  
(6) See Section 4.3.4, Processor Clocks.  
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ISP3  
ISP1  
ISP2  
cam_pclk  
cam_vs  
cam_hs  
ISP4  
ISP6  
ISP5  
ISP7  
ISP8  
ISP9  
D(0)  
D(n-2)  
D(n-1)  
D(0)  
D(n-2)  
D(n-1)  
cam_d[N:0]  
ISP10  
ISP11  
cam_wen  
cam_fld  
SWPS038-048  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as  
an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(2) N = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). When the number of data  
lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. Lines not connected must be  
tied low. For more information about video port mapping, see the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
Figure 6-19. CPI—Video and Graphics Digitizer—1.8-V Progressive Mode  
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ISP3  
ISP1  
ISP2  
cam_pclk  
cam_vs  
cam_hs  
ISP4  
ISP5  
ISP7  
ISP6  
ISP8  
ISP9  
D(n–1)  
D(0)  
D(n–1)  
D(0)  
D(0)  
D(n–1)  
D(0)  
D(n–1)  
cam_d[N:0]  
cam_wen  
cam_fld  
ISP10  
ISP11  
ISP12  
ISP13  
ODD  
EVEN  
SWPS038-049  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as  
an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(2) N = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). When the number of data  
lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. Lines not connected must be  
tied low. For more information about video port mapping, see the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
Figure 6-20. CPI—Video and Graphics Digitizer—1.8-V Interlaced Mode  
6.5.1.2.2 CPI—12-Bit SYNC Normal Progressive Mode  
Table 6-20 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-21).  
Table 6-19. CPI Timing Conditions—12-Bit SYNC Normal Progressive Mode(1)  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2.7  
2.7  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance  
8.6  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
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UNIT  
Table 6-20. CPI Timing Requirements—12-Bit SYNC Normal Progressive Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
45  
0.5P(2)  
0.5P(2)  
MIN  
MAX  
75  
MIN  
ISP17  
ISP18  
ISP18  
1 / tc(pclk)  
tw(pclkH)  
tw(pclkL)  
tdc(pclk)  
Frequency(1), input pixel clock cam_pclk  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk high  
Typical pulse duration, input pixel clock cam_pclk low  
Duty cycle error, input pixel clock cam_pclk  
0.5P(2)  
0.5P(2)  
ns  
0.5P(2)  
3.465  
-
0.5P(2)  
6.93  
-
ns  
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.0649*P  
0.0649*P  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(2)  
(2)  
ISP19  
ISP20  
ISP21  
ISP22  
ISP23  
ISP24  
ISP25  
ISP26  
tsu(dV-pclkH)  
th(pclkH-dV)  
tsu(dV-vsH)  
th(pclkH-vsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
Setup time, input data cam_d[11:0] valid before input  
pixel clock cam_pclk rising edge  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
Hold time, input data cam_d[11:0] valid after input  
pixel clock cam_pclk rising edge  
Setup time, input vertical synchronization cam_vs valid  
before input pixel clock cam_pclk rising edge  
Hold time, input vertical synchronization cam_vs valid  
after input pixel clock cam_pclk rising edge  
Setup time, input horizontal synchronization cam_hs  
valid before input pixel clock cam_pclk rising edge  
Hold time, input horizontal synchronization cam_hs  
valid after input pixel clock cam_pclk rising edge  
Setup time, input write enable cam_wen valid before  
input pixel clock cam_pclk rising edge  
Hold time, input write enable cam_wen valid after input  
pixel clock cam_pclk rising edge  
(1) Related with the input maximum frequency supported by the ISP module.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock.  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
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ISP16  
ISP15  
ISP16  
cam_xclki  
cam_pclk  
cam_vs  
ISP17  
ISP18  
ISP18  
ISP19  
ISP20  
ISP22  
ISP21  
cam_hs  
ISP23  
D(n–1)  
ISP24  
D(1)  
D(n–1)  
D(n–3)  
cam_d[11:0]  
D(0)  
D(n–2)  
D(0)  
ISP25  
ISP26  
cam_wen  
cam_fld  
SWPS038-050  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output,  
the signal length can be set.  
(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.  
(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be  
grounded.  
(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.  
(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit  
mode and cam_d[11:0] in 12-bit mode.  
(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.  
(7) The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs,  
and cam_wen signals are asserted.  
(8) In cam_xclki, i can be equal to a or b. See Table 6-16 for ISP15 and ISP16 parameters.  
Figure 6-21. CPI—12-Bit SYNC Normal Progressive Mode  
6.5.1.2.3 CPI—8-Bit SYNC Packed Progressive Mode  
Table 6-22 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-22).  
Table 6-21. CPI Timing Conditions—8-Bit SYNC Packed Progressive Mode(1)  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2.5  
2.5  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance  
8.6  
pF  
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(1) The load setting of the IO buffer: LB0 = 1.  
Table 6-22. CPI Timing Requirements—8-Bit SYNC Packed Progressive Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
MAX  
130  
OPP50  
UNIT  
MIN  
MIN  
MAX  
ISP3  
ISP4  
1 / tc(pclk)  
tw(pclkH)  
Frequency (1), input pixel clock cam_pclk  
65  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk  
high  
0.5*P(2)  
0.5*P(2)  
0.5*P(2)  
ISP4  
tw(pclkL)  
Typical pulse duration, input pixel clock cam_pclk  
low  
0.5*P(2)  
ns  
ns  
ns  
ns  
ns  
ns  
tdc(pclk)  
Duty cycle error, input pixel clock cam_pclk  
0.5*P(2)  
3.465  
-
0.5*P(2)  
6.93  
0.0649*P(2  
-
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.0649*P(2  
)
)
ISP5  
ISP6  
ISP7  
tsu(dV-pclkH)  
th(pclkH-dV)  
tsu(dV-vsH)  
Setup time, input data cam_d[7:0] valid before  
input pixel clock cam_pclk rising edge  
1.08  
1.08  
1.08  
2.27  
2.27  
2.27  
Hold time, input data cam_d[7:0] valid after input  
pixel clock cam_pclk rising edge  
Setup time, input vertical synchronization cam_vs  
valid before input pixel clock cam_pclk rising  
edge  
ISP8  
ISP9  
th(pclkH-vsV)  
tsu(dV-hsH)  
Hold time, input vertical synchronization cam_vs  
valid after input pixel clock cam_pclk rising edge  
1.08  
1.08  
2.27  
2.27  
ns  
ns  
Setup time, input horizontal synchronization  
cam_hs valid before input pixel clock cam_pclk  
rising edge  
ISP10  
th(pclkH-hsV)  
Hold time, input horizontal synchronization  
cam_hs valid after input pixel clock cam_pclk  
rising edge  
1.08  
2.27  
ns  
ISP11  
ISP12  
tsu(dV-hsH)  
Setup time, input write enable cam_wen valid  
before input pixel clock cam_pclk rising edge  
1.08  
1.08  
2.27  
2.27  
ns  
ns  
th(pclkH-hsV)  
Hold time, input write enable cam_wen valid after  
input pixel clock cam_pclk rising edge  
(1) Related with the input maximum frequency supported by the ISP module.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock.  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
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ISP16  
ISP15  
ISP16  
cam_xclki  
ISP4  
ISP3  
ISP4  
cam_pclk  
cam_vs  
ISP5  
ISP6  
ISP8  
ISP7  
cam_hs  
ISP9  
ISP10  
D(1)  
D(0)  
D(n-3)  
D(n-2)  
D(n-1)  
D(0)  
D(n-1)  
cam_d[7:0]  
ISP11  
ISP12  
cam_wen  
cam_fld  
SWPS038-051  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.  
(2) The image sensor is connected to the lower data lines and the unused lines are grounded. However, it is possible to shift the data to  
0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.  
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a  
external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The  
polarity of cam_fld is programmable.  
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to  
transfer an YCbCr data stream or compressed stream to memory at very high speed.  
(5) In cam_xclki, i can be equal to a or b. See Table 6-16 for ISP15 and ISP16 parameters.  
Figure 6-22. CPI—8-Bit SYNC Packed Progressive Mode  
6.5.1.2.4 CPI—12-Bit SYNC Normal Interlaced Mode  
Table 6-24 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-23).  
Table 6-23. CPI Timing Conditions—12-Bit SYNC Normal Interlaced Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2.7  
2.7  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
8.6  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
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UNIT  
Table 6-24. CPI Timing Requirements—12-Bit SYNC Normal Interlaced Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
45  
0.5P(2)  
0.5P(2)  
MIN  
MAX  
75  
MIN  
ISP17  
ISP18  
ISP18  
1 / tc(pclk)  
tw(pclkH)  
tw(pclkL)  
tdc(pclk)  
Frequency(1), input pixel clock cam_pclk  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk high  
Typical pulse duration, input pixel clock cam_pclk low  
Duty cycle error, input pixel clock cam_pclk  
0.5P(2)  
0.5P(2)  
ns  
0.5*P(2)  
3.465  
-
0.5*P(2)  
6.93  
-
ns  
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.0649*P  
0.0649*P  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(2)  
(2)  
ISP19  
ISP20  
ISP21  
ISP22  
ISP23  
ISP24  
ISP25  
ISP26  
ISP27  
ISP28  
tsu(dV-pclkH)  
th(pclkH-dV)  
tsu(dV-vsH)  
th(pclkH-vsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
tsu(dV-fldH)  
th(pclkH-fldV)  
Setup time, input data cam_d[11:0] valid before input  
pixel clock cam_pclk rising edge  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
1.82  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
3.25  
Hold time, input data cam_d[11:0] valid after input  
pixel clock cam_pclk rising edge  
Setup time, input vertical synchronization cam_vs valid  
before input pixel clock cam_pclk rising edge  
Hold time, input vertical synchronization cam_vs valid  
after input pixel clock cam_pclk rising edge  
Setup time, input horizontal synchronization cam_hs  
valid before input pixel clock cam_pclk rising edge  
Hold time, input horizontal synchronization cam_hs  
valid after input pixel clock cam_pclk rising edge  
Setup time, input write enable cam_wen valid before  
input pixel clock cam_pclk rising edge  
Hold time, input write enable cam_wen valid after input  
pixel clock cam_pclk rising edge  
Setup time, input field identification cam_fld valid  
before input pixel clock cam_pclk rising edge  
Hold time, input field identification cam_fld valid after  
input pixel clock cam_pclk rising edge  
(1) Related with the input maximum frequency supported by the ISP module.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock.  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
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ISP16  
ISP15  
ISP16  
cam_xclki  
ISP18  
ISP18  
ISP17  
cam_pclk  
ISP20  
ISP19  
cam_vs  
cam_hs  
FRAME(0)  
FRAME(0)  
ISP21  
ISP22  
L(n-1)  
L(0)  
L(0)  
ISP23  
ISP24  
D(0)  
D(n-3)  
D(n-2)  
D(n-1)  
D(0)  
D(1)  
D(2)  
D(n-1)  
cam_d[11:0]  
cam_wen  
ISP25  
ISP26  
ISP28  
ISP27  
IMPAIR  
cam_fld  
PAIR  
SWPS038-052  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output,  
the signal length can be set.  
(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.  
(3) When the image sensor has fewer than 12 data lines, it is connected to the lower data lines and the unused lines are grounded.  
(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.  
(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit  
mode and cam_d[11:0] in 12-bit mode.  
(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.  
(7) The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs,  
and cam_wen signals are asserted.  
(8) In cam_xclki, i can be equal to a or b. See Table 6-16 for ISP15 and ISP16 parameters.  
Figure 6-23. CPI—12-bit SYNC Normal Interlaced ModeSection 5.3  
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6.5.1.2.5 CPI—8-Bit SYNC Packed Interlaced Mode  
Table 6-26 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-24).  
Table 6-25. CPI Timing Conditions—8-Bit SYNC Packed Interlaced Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2.5  
2.5  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
8.6  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
Table 6-26. CPI Timing Requirements—8-Bit SYNC Packed Interlaced Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
65  
0.5P(2)  
0.5P(2)  
UNIT  
MIN  
MAX  
130  
MIN  
ISP3  
ISP4  
ISP4  
1 / tc(pclk)  
tw(pclkH)  
tw(pclkL)  
tdc(pclk)  
Frequency(1), input pixel clock cam_pclk  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk high  
Typical pulse duration, input pixel clock cam_pclk low  
Duty cycle error, input pixel clock cam_pclk  
0.5P(2)  
0.5P(2)  
ns  
0.5*P(2)  
3.465  
-
0.5*P(2)  
6.93  
-
ns  
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.0649*P  
0.0649*P  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(2)  
(2)  
ISP5  
ISP6  
tsu(dV-pclkH)  
th(pclkH-dV)  
tsu(dV-vsH)  
th(pclkH-vsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
tsu(dV-hsH)  
th(pclkH-hsV)  
tsu(dV-fldH)  
th(pclkH-fldV)  
Setup time, input data cam_d[8:0] valid before input  
pixel clock cam_pclk rising edge  
1.08  
1.08  
1.08  
1.08  
1.08  
1.08  
1.08  
1.08  
1.08  
1.08  
2.27  
2.27  
2.27  
2.27  
2.27  
2.27  
2.27  
2.27  
2.27  
2.27  
Hold time, input data cam_d[8:0] valid after input pixel  
clock cam_pclk rising edge  
ISP7  
Setup time, input vertical synchronization cam_vs valid  
before input pixel clock cam_pclk rising edge  
ISP8  
Hold time, input vertical synchronization cam_vs valid  
after input pixel clock cam_pclk rising edge  
ISP9  
Setup time, input horizontal synchronization cam_hs  
valid before input pixel clock cam_pclk rising edge  
ISP10  
ISP11  
ISP12  
ISP13  
ISP14  
Hold time, input horizontal synchronization cam_hs  
valid after input pixel clock cam_pclk rising edge  
Setup time, input write enable cam_wen valid before  
input pixel clock cam_pclk rising edge  
Hold time, input write enable cam_wen valid after input  
pixel clock cam_pclk rising edge  
Setup time, input field identification cam_fld valid  
before input pixel clock cam_pclk rising edge  
Hold time, input field identification cam_fld valid after  
input pixel clock cam_pclk rising edge  
(1) Related with the input maximum frequency supported by the ISP module.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock.  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
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ISP15  
ISP16  
ISP16  
cam_xclki  
ISP4  
ISP3  
ISP4  
cam_pclk  
cam_vs  
ISP6  
ISP5  
ISP7  
FRAME(0)  
FRAME(0)  
ISP8  
cam_hs  
L(0)  
L(0)  
L(n-1)  
ISP9  
D(1)  
ISP10  
D(n-1)  
D(0)  
D(n-3)  
D(n-2)  
D(n-1)  
D(0)  
D(2)  
cam_d[7:0]  
cam_wen  
ISP11  
ISP12  
ISP14  
ISP13  
cam_fld  
PAIR  
IMPAIR  
SWPS038-053  
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.  
(2) The image sensor is connected to the lower data lines and the unused lines are grounded. However, it is possible to shift the data to  
0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode .  
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as an  
external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.  
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to  
transfer a YCbCr data stream or compressed stream to memory at very high speed.  
(5) In cam_xclki, i can be equal to a or b. See Table 6-16 for ISP15 and ISP16 parameters.  
Figure 6-24. CPI—8-Bit SYNC Packed Interlaced Mode  
6.5.1.2.6 CPI—ITU Mode  
Table 6-28 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-25).  
Table 6-27. CPI Timing Conditions—ITU Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2.7  
2.7  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
8.6  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
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UNIT  
Table 6-28. CPI Timing Requirements—ITU Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
45  
0.5P(2)  
0.5P(2)  
MIN  
MAX  
75  
MIN  
ISP17  
ISP18  
ISP18  
1 / tc(pclk)  
tw(pclkH)  
tw(pclkL)  
tdc(pclk)  
Frequency(1), input pixel clock cam_pclk  
MHz  
ns  
Typical pulse duration, input pixel clock cam_pclk high  
Typical pulse duration, input pixel clock cam_pclk low  
Duty cycle error, input pixel clock cam_pclk  
0.5P(2)  
0.5P(2)  
ns  
0.5*P(2)  
3.465  
-
0.5*P(2)  
6.93  
-
ns  
tJ(pclk)  
Cycle jitter(3), input pixel clock cam_pclk  
0.0649*P  
0.0649*P  
ns  
ns  
ns  
(2)  
(2)  
ISP23  
ISP24  
tsu(dV-pclkH)  
th(pclkH-dV)  
Setup time, input data cam_d[9:0] valid before input  
pixel clock cam_pclk rising edge  
1.82  
1.82  
3.25  
3.25  
Hold time, input data cam_d[9:0] valid after input pixel  
clock cam_pclk rising edge  
(1) Related with the input maximum frequency supported by the ISP module.  
(2) P = cam_pclk period in ns  
(3) Maximum cycle jitter supported by cam_pclk input clock.  
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
ISP16  
ISP15  
ISP16  
cam_xclki  
cam_pclk  
ISP17  
ISP18  
ISP18  
ISP23  
D(0)  
ISP24  
D(0)  
D(n-1)  
D(n-1)  
SOF  
EOF  
EOF  
cam_d[9:0]  
SOF  
SWPS038-054  
(1) The unused lines are grounded and the data bus is connected to the lower data lines. However, it is possible to shift the data to 0, 2,  
or 4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in  
10-bit mode.  
(2) The parallel camera in ITU mode supports progressive camera modules.  
(3) In cam_xclki, i can be equal to a or b. See Table 6-16 for ISP15 and ISP16 parameters.  
Figure 6-25. CPI—ITU Mode  
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6.5.2 Display Subsystem (DSS)  
NOTE  
For more information, see Display Subsystem chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or  
internal (SRAM) memory on an LCD panel or a TV set. The display subsystem integrates the following  
elements:  
•
•
•
•
Display controller (DISPC) module  
Remote frame buffer interface (RFBI) module  
NTSC/PAL video encoder  
LCD display with:  
–
Parallel Interface  
The two display supports can be active at the same time.  
6.5.2.1 DSS—Parallel Interface  
In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI.  
The display controller has two I/O pad modes and could be in the following configuration:  
•
•
Bypass mode (RFBI disabled), which implements the MIPI DPI protocol  
RFBI mode (RFBI enabled), which implements MIPI DBI 2.0 type B protocol  
For more information about MIPI DPI and MIPI DBI protocols, see the DSS chapter in the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
6.5.2.1.1 DSS—Parallel Interface—Bypass Mode  
Two types of LCD panel are supported:  
•
•
Thin film transistor (TFT) or active matrix technology  
Supertwisted nematic (STN) or passive matrix technology  
Both configurations are discussed in the following paragraphs.  
6.5.2.1.2 DSS—Parallel Interface—Bypass Mode—TFT Mode  
Table 6-30 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-26).  
Table 6-29. DSS Timing Conditions—TFT Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Output Condition  
CLOAD  
Output load capacitance(1)  
10  
pF  
(1) Buffer strength configuration: LB0 = 1  
Table 6-30. DSS Switching Characteristics—TFT Mode(4)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
MAX  
MIN  
MAX  
DL0  
DL1  
td(pclkA-hsync)  
td(pclkA-vsync)  
Delay time, output pixel clock dss_pclk active edge to  
output horizontal synchronization dss_hsync transition  
–4.215  
4.215  
–4.658  
4.658  
ns  
ns  
Delay time, output pixel clock dss_pclk active edge to  
output vertical synchronization dss_vsync transition  
–4.215  
4.215  
–4.658  
4.658  
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Table 6-30. DSS Switching Characteristics—TFT Mode(4) (continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
MIN  
MAX  
MIN  
MAX  
DL2  
DL3  
td(pclkA-acbiasA)  
td(pclkA-dV)  
Delay time, output pixel clock dss_pclk active edge to  
output data enable dss_acbias active level  
–4.215  
4.215  
–4.658  
4.658  
ns  
ns  
Delay time, output pixel clock dss_pclk active edge to  
output data dss_data[23:0] valid  
Frequency(2), output pixel clock dss_pclk  
–4.215  
4.215  
–4.658  
4.658  
66(3)  
DL4  
DL5  
1 / tc(pclk)  
tw(pclk)  
74.3(3)  
MHz  
ns  
Pulse duration, output pixel clock dss_pclk low or high 0.45P(1)  
0.55P(1)  
0.45P(1)  
0.55P(1)  
(5)  
(5)  
(1) P = dss_pclk period in ns  
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the  
DISPC_DIVISOR register.  
(3) For the DSS (TFT mode) in HD-TV application, to run at full speed (74.3 MHz) it is recommended to use the dss_data[5:0] signals on  
the dss_data[23:18] balls (H26, H25, E28, J26, AC27, AC28). In that case, the dss_data[23:18] signals are available on the sys_boot0,  
sys_boot1, sys_boot3, sys_boot4, sys_boot5, and sys_boot6 balls (AH26, AG26, AF18, AF19, AE21, AF21) to run at full speed (74.3  
MHz).  
If the dss_data[5:0] signals are used on the dss_data[5:0] balls (AG22, AH22, AG23, AH23, AG24, AH24), OPP100 DSS (TFT mode)  
are limited at 66 MHz. The values may change following the silicon characterization result.  
(4) See Section 4.3.4, Processor Clocks.  
(5) tW(pclk) = 0.66.P when DISPC_DIVISOR[6:0] PCD = 3.  
DL5  
DL4  
dss_pclk  
DL1  
dss_vsync  
DL0  
dss_hsync  
DL2  
dss_acbias  
DL3  
dss_data[23:0]  
SWPS038-055  
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.  
(2) The pixel clock frequency is programmable.  
(3) All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too.  
(4) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Figure 6-26. DSS—TFT Mode  
6.5.2.1.3 DSS—Parallel Interface—Bypass Mode—STN Mode  
Table 6-32 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-27).  
Table 6-31. DSS Timing Conditions—STN Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Output Condition  
CLOAD  
Output load capacitance(1)  
40  
pF  
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(1) Buffer strength configuration: LB0 = 1  
Table 6-32. DSS Switching Characteristics—STN Mode(3) (4)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
–6.868  
MAX  
MIN  
MAX  
DL3  
td(pclkA-dV)  
Delay time, output pixel clock dss_pclk active edge to  
output data dss_data[7:0] valid  
6.868  
–6.868  
6.868  
ns  
DL4  
DL5  
1 / tc(pclk)  
tw(pclk)  
Frequency(2), output pixel clock dss_pclk  
Pulse duration, output pixel clock dss_pclk low or high 0.45P(1)  
44  
44  
MHz  
ns  
0.55P(1)  
0.45P(1) 0.55P(1)(5  
(5)  
)
(1) P = dss_pclk period in ns  
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the  
DISPC_DIVISOR register.  
(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.  
(4) See Section 4.3.4, Processor Clocks.  
(5) tW(pclk) = 0.66P when DISPC_DIVISOR[6:0] PCD = 3.  
DL5  
DL4  
dss_pclk  
dss_vsync  
dss_hsync  
dss_acbias  
DL3  
dss_data[23:0]  
SWPS038-056  
(1) The pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.  
(2) All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too.  
(3) dss_vsync width must be programmed to be as small as possible.  
(4) The pixel clock frequency is programmable.  
(5) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Figure 6-27. DSS—STN Mode  
6.5.2.2 DSS—Parallel Interface— RFBI Mode — Applications  
6.5.2.2.1 DSS—Parallel Interface—RFBI Mode— MIPI DBI-B 2.0 —LCD Panel  
The Remote Frame Buffer Interface (RFBI) module provides the necessary control signals and data  
(MIPI® DBI 2.0 type B protocol) to interface to the LCD driver of the LCD panel.  
Table 6-34 and Table 6-35 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-28 through Figure 6-30).  
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Table 6-33. DSS Timing Conditions—RFBI Mode—MIPI DBI 2.0 - LCD Panel(2)  
TIMING CONDITION PARAMETER  
VALUE  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
Input signal fall time  
15  
15  
ns  
ns  
tF  
Output Condition  
CLOAD  
Output load capacitance(1)  
30  
pF  
(1) Buffer strength configuration: LB0 = 1.  
(2) For any information regarding the RFBI registers configuration, see Display Subsystem / the Display Subsystem Environment / LCD  
Support / Parallel Interface / Parallel Interface in RFBI Mode (MIPI DBI Protocol) / Transaction Timing Diagrams section of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
Table 6-34. DSS Timing Requirements—RFBI Mode—MIPI DBI 2.0 - LCD Panel  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
DR0  
DR1  
tsu(dV-rdH)  
Setup time, input data rfbi_da[15:0] valid to output  
read enable rfbi_rd high  
7.3  
6.3  
ns  
ns  
ns  
th(rdH-dIV)  
Hold time, output read enable rfbi_rd high to input data  
rfbi_da[15:0] invalid  
10.6  
9.6  
td(Data sampled)  
Input data rfbi_da[15:0] sampled at the end of the  
access time  
N(1)  
N(1)  
(1) N = (AccessTime) * (TimeParaGranularity + 1) * L4CLK  
Table 6-35. DSS Switching Characteristics— RFBI Mode— MIPI DBI 2.0 - LCD Panel  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
tw(wrH)  
tw(wrL)  
Pulse duration, output write enable rfbi_wr high  
Pulse duration, output write enable rfbi_wr low  
A(1)  
B(2)  
C(3)  
A(1)  
B(2)  
C(3)  
ns  
ns  
ns  
td(a0-wrL)  
Delay time, output command/data control rfbi_a0 transition to  
output write enable rfbi_wr low  
td(wrH-a0)  
td(csx-wrL)  
td(wrH-csxH)  
Delay time, output write enable rfbi_wr high to output  
command/data control rfbi_a0 transition  
Delay time, output chip select rfbi_csx(14) low to output write  
enable rfbi_wr low  
D(4)  
E(5)  
F(6)  
D(4)  
E(5)  
F(6)  
ns  
ns  
ns  
Delay time, output write enable rfbi_wr high to output chip select  
rfbi_csx(14) high  
td(dV)  
Output data rfbi_da[15:0] valid  
G(7)  
H(8)  
G(7)  
H(8)  
ns  
ns  
td(a0H-rdL)  
Delay time, output command/data control rfbi_a0 high to output  
read enable rfbi_rd low  
td(rdlH-a0)  
Delay time, output read enable rfbi_rd high to output  
command/data control rfbi_a0 transition  
I(9)  
I(9)  
ns  
tw(rdH)  
Pulse duration, output read enable rfbi_rd high  
Pulse duration, output read enable rfbi_rd low  
J(10)  
K(11)  
L(12)  
J(10)  
K(11)  
L(12)  
ns  
ns  
ns  
tw(rdL)  
td(rdL-csxL)  
Delay time, output read enable rfbi_rd low to output chip select  
rfbi_csx(14) low  
td(rdH-csxH)  
Delay time, output read enable rfbi_rd high to output chip select  
rfbi_csx(14) high  
M(13)  
M(13)  
ns  
tR(wr)  
tF(wr)  
tR(a0)  
tF(a0)  
tR(csx)  
Rise time, output write enable rfbi_wr  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
Fall time, output write enable rfbi_wr  
Rise time, output command/data control rfbi_a0  
Fall time, output command/data control rfbi_a0  
Rise time, output chip select rfbi_csx(14)  
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Table 6-35. DSS Switching Characteristics— RFBI Mode— MIPI DBI 2.0 - LCD Panel (continued)  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
tF(csx)  
tR(d)  
Fall time, output chip select rfbi_csx(14)  
Rise time, output data rfbi_da[15:0]  
Fall time, output data rfbi_da[15:0]  
Rise time, output read enable rfbi_rd  
Fall time, output read enable rfbi_rd  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
tF(d)  
tR(rd)  
tF(rd)  
(1) A = (WECycleTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK  
(2) B = (WEOffTime – WEOntime) * (TimeParaGranularity + 1) * L4CLK  
(3) C = WEOnTime * (TimeParaGranularity + 1) * L4CLK  
(4) D = (WECycleTime + CSPulseWidth – WEOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is  
enabled  
(5) E = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK  
(6) F = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK  
(7) G = WECycleTime * (TimeParaGranularity + 1) * L4CLK  
(8) H = REOnTime * (TimeParaGranularity + 1) * L4CLK  
(9) I = (RECycleTime + CSPulseWidth – REOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is  
enabled  
(10) J = (RECycleTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK  
(11) K = (REOffTime – REOntime) * (TimeParaGranularity + 1) * L4CLK  
(12) L = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK  
(13) M = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK  
(14) In rfbi_csx, x is equal to 0 or 1.  
CsPulseWidth  
WeCycleTime  
CsOffTime  
WeCycleTime  
rfbi_a0  
CsOffTime  
CsOnTime  
CsOnTime  
rfbi_csx  
WeOffTime  
WeOnTime  
WeOffTime  
WeOnTime  
rfbi_wr  
rfbi_da[n:0]  
DATA0  
DATA1  
rfbi_rd  
rfbi_te_vsync[1:0]  
rfbi_hsync[1:0]  
SWPS038-057  
(1) In rfbi_csx, x is equal to 0 or 1.  
(2) rfbi_data[n:0], n up to 15  
(3) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Figure 6-28. DSS—RFBI Mode—MIPI DBI 2.0 —LCD Panel—Command / Data Write  
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AccessTime  
ReCycleTime  
AccessTime  
ReCycleTime  
CsPulseWidth  
rfbi_a0  
rfbi_csx  
rfbi_rd  
CsOffTime  
CsOnTime  
CsOffTime  
CsOnTime  
ReOffTime  
ReOnTime  
ReOffTime  
ReOnTime  
DR0  
DATA0  
DR1  
rfbi_da[n:0]  
rfbi_wr  
DATA1  
rfbi_te_vsync[1:0]  
rfbi_hsync[1:0]  
SWPS038-058  
(1) In rfbi_csx, x is equal to 0 or 1.  
(2) rfbi_data[n:0], n up to 15  
(3) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Figure 6-29. DSS—RFBI Mode—MIPI DBI 2.0 —LCD Panel—Command / Data Read  
WECycleTime  
ReCycleTime  
AccessTime  
WECycleTime  
rfbi_a0  
rfbi_csx  
rfbi_wr  
rfbi_rd  
CsOffTime  
CsOnTime  
CsOffTime  
CsOnTime  
CsOffTime  
CsOnTime  
WEOffTime  
WEOnTime  
WEOffTime  
WEOnTime  
ReOffTime  
ReOnTime  
CsPulseWidth  
CsPulseWidth  
WRITE  
rfbi_da[n:0]  
rfbi_te_vsync[1:0]  
rfbi_hsync[1:0]  
READ  
WRITE  
SWPS038-059  
(1) In rfbi_csx, x is equal to 0 or 1.  
(2) rfbi_data[n:0], n up to 15  
(3) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Figure 6-30. DSS—RFBI Mode—MIPI DBI 2.0 — LCD Panel—Command / Data Write to Read and Read to  
Write Modes  
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6.5.2.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP  
The Remote Frame Buffer Interface (RFBI) module can provide also the necessary control signals and  
data to interface to the Pico DLP driver of the Pico DLP panel. Table 6-36 assumes testing over the  
recommended operating conditions and electrical characteristic conditions below (see Figure 6-31).  
Table 6-36. DSS Timing Conditions—RFBI Mode—Pico DLP  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Output Condition  
CLOAD  
Output load capacitance(1)  
5
pF  
(1) Buffer strength configuration: LB0 = 0  
To use Pico DLP application, RFBI register must be configured as shown in Table 6-37:  
Table 6-37. DSS Register Configuration—RFBI Mode—Pico DLP  
DESCRIPTION  
Selection parallel mode  
REGISTER AND BIT FIELD(1)  
BIT  
VALUES  
RFBI_CONFIGi and  
ParallelMode  
[1:0]  
0b11: 16-bit parallel output interface  
selected  
Time Granularity (multiplies signal timing  
latencies by 2).  
RFBI_CONFIGi  
andTimeGranularity  
[4]  
0b0: x2 latency disable  
CS signal assertion time from Start Access  
Time  
RFBI_ONOFF_TIMEi and  
CSOnTime  
[3:0]  
0b0000  
CS signal de-assertion time from Start Access  
Time  
RFBI_ONOFF_TIMEi and  
CSOffTime  
[9:4]  
0b000100: 4 cycles  
0b0000  
WE signal assertion time from Start Access  
Time  
RFBI_ONOFF_TIMEi and  
WEOnTime  
[13:10]  
[19:14]  
[23:20]  
[29:24]  
[5:0]  
WE signal de-assertion time from Start Access RFBI_ONOFF_TIMEi and  
Time  
0b000010: 2 cycles  
0b0000  
WEOffTime  
RE signal assertion time from Start Access  
Time  
RFBI_ONOFF_TIMEi and  
REOnTime  
RE signal de-assertion time from Start Access  
Time  
RFBI_ONOFF_TIMEi and  
REOffTime  
0b0000  
Write cycle time  
RFBI_CYCLE_TIMEi and  
WECycleTime  
0b000100: 4 cycles  
0b000000  
0b000000  
0b0  
Read cycle time  
RFBI_CYCLE_TIMEi and  
ReCycleTime  
[11:6]  
[17:12]  
[18]  
CS pulse width  
RFBI_CYCLE_TIMEi and  
CSPulseWidth  
Read to Write CS pulse width enable  
Read to Read CS pulse width enable  
Write to Write CS pulse width enable  
Write to Read CS pulse width enable  
RFBI_CYCLE_TIMEi and  
RWEnable  
RFBI_CYCLE_TIMEi and  
RREnable  
[19]  
0b0  
RFBI_CYCLE_TIMEi and  
WWEnable  
[20]  
0b0  
RFBI_CYCLE_TIMEi and  
WREnable  
[21]  
0b0  
From Start Access Time to CLK rising edge  
used for the first data capture  
RFBI_CYCLE_TIMEi and  
AccessTime  
[27:22]  
0b000000  
(1) i is equal to 0 or 1. For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
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Table 6-38. DSS Switching Characteristics—RFBI Mode—Pico DLP(15)(17)(18)  
PARAMETER  
OPP100  
MAX  
OPP50  
MIN  
MIN  
MAX  
tw(wrH)  
tw(wrL)  
Pulse duration, output write enable rfbi_wr high  
Pulse duration, output write enable rfbi_wr low  
A(1)  
B(2)  
C(3)  
A(1)  
B(2)  
C(3)  
ns  
ns  
ns  
td(a0-wrL)  
Delay time, output command/data control rfbi_a0  
transition to output write enable rfbi_wr low  
td(wrH-a0)  
td(csx-wrL)  
td(wrH-csxH)  
Delay time, output write enable rfbi_wr high to output  
command/data control rfbi_a0 transition  
Delay time, output chip select rfbi_csx(14) low to output  
write enable rfbi_wr low  
D(4)  
E(5)  
F(6)  
D(4)  
E(5)  
F(6)  
ns  
ns  
ns  
Delay time, output write enable rfbi_wr high to output  
chip select rfbi_csx(14) high  
td(dataV)  
td(Skew)  
Output data rfbi_da[15:0](16) valid  
G(7)  
G(7)  
ns  
ns  
Skew between output write enable falling rfbi_wr and  
output data rfbi_da[15:0](16) high or low  
15.5  
15.5  
td(a0H-rdL)  
td(rdlH-a0)  
Delay time, output command/data control rfbi_a0 high to  
output read enable rfbi_rd low  
H(8)  
I(9)  
H(8)  
I(9)  
ns  
ns  
Delay time, output read enable rfbi_rd high to output  
command/data control rfbi_a0 transition  
tw(rdH)  
Pulse duration, output read enable rfbi_rd high  
Pulse duration, output read enable rfbi_rd low  
J(10)  
K(11)  
L(12)  
J(10)  
K(11)  
L(12)  
ns  
ns  
ns  
tw(rdL)  
td(rdL-csxL)  
Delay time, output read enable rfbi_rd low to output chip  
select rfbi_csx(14) low  
td(rdL-csxH)  
Delay time, output read enable rfbi_rd low to output chip  
select rfbi_csx(14) high  
M(13)  
M(13)  
ns  
tR(wr)  
tF(wr)  
tR(a0)  
tF(a0)  
Rise time, output write enable rfbi_wr  
Fall time, output write enable rfbi_wr  
Rise time, output command/data control rfbi_a0  
Fall time, output command/data control rfbi_a0  
Rise time, output chip select rfbi_csx(14)  
Fall time, output chip select rfbi_csx(14)  
Rise time, output data rfbi_da[15:0](16)  
Fall time, output data rfbi_da[15:0](16)  
Rise time, output read enable rfbi_rd  
Fall time, output read enable rfbi_rd  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tR(csx)  
tF(csx)  
tR(d)  
tF(d)  
tR(rd)  
tF(rd)  
CsOnTime  
CS signal assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
0(19)  
40(19)  
0(19)  
20(19)  
-
CsOffTime  
WeOnTime  
WeOffTime  
ReOnTime  
ReOffTime  
CS signal de-assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
ns  
ns  
ns  
ns  
ns  
WE signal assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
WE signal de-assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
RE signal assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
RE signal de-assertion time from Start Access Time -  
RFBI_ONOFF_TIMEi Register  
-
WeCycleTime  
ReCycleTime  
CsPulseWidth  
Write cycle time - RFBI_CYCLE_TIMEi Register  
Read cycle time - RFBI_CYCLE_TIMEi Register  
CS pulse width - RFBI_CYCLE_TIMEi Register  
40(19)  
-
0(19)  
ns  
ns  
ns  
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(1) A = (WECycleTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK  
(2) B = (WEOffTime – WEOntime) * (TimeParaGranularity + 1) * L4CLK  
(3) C = WEOnTime * (TimeParaGranularity + 1) * L4CLK  
(4) D = (WECycleTime + CSPulseWidth – WEOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is  
enabled.  
(5) E = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK  
(6) F = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK  
(7) G = WECycleTime * (TimeParaGranularity + 1) * L4CLK  
(8) H = REOnTime * (TimeParaGranularity + 1) * L4CLK  
(9) I = (RECycleTime + CSPulseWidth – REOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is  
enabled.  
(10) J = (RECycleTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK  
(11) K = (REOffTime – REOntime) * (TimeParaGranularity + 1) * L4CLK  
(12) L = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK  
(13) M = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK  
(14) In rfbi_csx, x is equal to 0 or 1.  
(15) See Section 4.3.4, Processor Clocks.  
(16) 16-bit parallel output interface is selected in DSS register.  
(17) At OPP100, L4 clock is 100 MHz and at OPP50, L4 clock is 50 MHz.  
(18) rfbi_wr must be at 25 MHz.  
(19) These values are calculated by the following formula: RFBI Register (Value) * L4 Clock (ns).  
CsPulseWidth  
WeCycleTime  
WeCycleTime  
rfbi_a0  
rfbi_csx  
rfbi_wr  
CsOffTime  
CsOnTime  
CsOffTime  
CsOnTime  
WeOffTime  
WeOnTime  
WeOffTime  
WeOnTime  
DATA0  
DATA1  
rfbi_da[n:0]  
rfbi_rd  
rfbi_te_vsync[1:0]  
rfbi_hsync[1:0]  
swps038-118  
Figure 6-31. DSS—RFBI Mode—Pico DLP—Command / Data Write(1)(2)  
(1) In rfbi_csx, x is equal to 0 or 1.  
(2) rfbi_da[n:0], n up to 15  
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6.6 Serial Communications Interfaces  
6.6.1 Multichannel Buffered Serial Port (McBSP)  
NOTE  
For more information, see Multi-Channel Buffered Serial Port chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
The Multichannel Buffered Serial Port (McBSP) provides a full duplex direct serial interface between the  
chip and other devices in a system such as other application chips, codecs. It can accommodate a wide  
range of peripherals and clocked frame oriented protocols (I2S, PCM, T ) due to its high level of versatility.  
McBSP may support two types of data transfer at the system level:  
•
The full cycle mode, for which one clock period is used to transfer the data, generated on one edge  
and captured on the same edge (one clock period later).  
•
The half cycle mode, for which one half clock period is used to transfer the data, generated on one  
edge and captured on the opposite edge (one half clock period later). Note that a new data is  
generated only every clock period, which secures the required hold time.  
The interface clock (clkx/clkr) activation edge (data/frame sync capture and generation) has to be  
configured accordingly with the external peripheral (activation edge capability) and the type of data  
transfer required at the system level.  
Depending on the number of pins, McBSP supports either:  
•
•
6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins  
4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are  
internally looped back, via software configuration, respectively to the clkr and fsr internal signals for  
data receive.  
McBSP1 supports the 6-pin mode. McBSP2, 3, 4, and 5 support only the 4-pin mode.  
The following sections describe the timing characteristics for applications in normal mode (that is, McBSPx  
connected to one peripheral) and T applications in multipoint mode.  
6.6.1.1 McBSP Timing Conditions—Normal Mode  
Table 6-40 through Table 6-64 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-32 through Figure 6-39).  
Table 6-39. McBSP Timing Conditions—Normal Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2
2
ps  
ps  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
10  
pF  
(1) Buffer strength configuration:  
–
–
McBSP4 - Set #1: LB0 = 1.  
Otherwise: LB0 = 0.  
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Table 6-40. McBSP Output Clock Characteristics—Normal Mode(4)  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
McBSP1  
tc(CLK)  
Cycle time, mcbsp1_clkx (multiplexing mode 0) /  
mcbsp1_clkr (multiplexing mode 0 & 2)  
48  
24  
MHz  
McBSP2  
McBSP3  
tc(CLK)  
tc(CLK)  
Cycle time, mcbsp2_clkx (multiplexing mode 0)  
48  
32  
24  
16  
MHz  
MHz  
Cycle time, mcbsp3_clkx  
IO set 1  
(multiplexing  
mode 0)  
IO set 2  
(multiplexing  
mode 1)  
48  
48  
48  
32  
32  
24  
24  
16  
16  
16  
IO set 3  
(multiplexing  
mode 2)  
McBSP4  
McBSP5  
tc(CLK)  
tc(CLK)  
Cycle time, mcbsp4_clkx  
Cycle time, mcbsp5_clkx  
IO set 1  
(multiplexing  
mode 0)  
MHz  
MHz  
IO set 3  
(multiplexing  
mode 2)  
IO set 2  
(multiplexing  
mode 1)  
tW(CLKH)  
tW(CLKL)  
tdc(CLK)  
Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high(2)  
Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low(2)  
Duty cycle error, mcbsp1_clkr / mcbspx_clkx(2)  
0.5*P(1)  
0.5*P(1)  
0.5*P(1)  
0.5*P(1)  
ns  
ns  
ns  
ns  
–0.75  
-0.40  
0.75  
0.40  
–0.75  
-0.40  
0.75  
0.40  
Jitter, mcbsp1_clkr / mcbspx_clkx(3) / mcbsp_clks  
(1) P = mcbspy_clkx(2) or mcbsp1_clkr output clock period in ns  
(2) In mcbspy, y is equal to 1, 2, 3, 4, or 5.  
(3) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
(4) See Section 4.3.4, Processor Clocks.  
6.6.1.1.1 Rising Edge as Activation Mode  
6.6.1.1.1.1 Timing with Rising Edge as Activation Edge—Receive Mode  
Table 6-41. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Receive Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
8.63  
7.94  
1.01  
0.4  
B3  
tsu(DRV-CLKAE)  
Setup time, mcbspx_dr valid before  
mcbsp1_clkr / mcbspx_clkx active edge  
Master  
Slave  
4.36  
3.67  
1.01  
0.4  
ns  
ns  
ns  
ns  
ns  
B4  
th(CLKAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbsp1_clkr / mcbspx_clkx active edge  
Master  
Slave  
B5  
B6  
tsu(FSV-CLKAE)  
th(CLKAE-FSV)  
Setup time, mcbsp1_fsr / mcbspx_fsx valid before  
mcbsp1_clkr / mcbspx_clkx active edge  
3.67  
7.94  
Hold time, mcbsp1_fsr / mcbspx_fsx valid after  
mcbsp1_clkr / mcbspx_clkx active edge  
0.5  
0.5  
ns  
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(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-42. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Receive  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
29.58  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKAE-FSV)  
Delay time, mcbsp1_clkr / mcbspx_clkx active edge to  
mcbsp1_fsr / mcbspx_fsx valid  
14.79  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-43. McBSP4 (Set #1) Timing Requirements—Rising Edge and Receive Mode(1) (2)  
NO.  
B3  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
8.63  
7.94  
1.01  
0.4  
tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before  
mcbspx_clkx active edge  
Master  
Slave  
2.87  
3.67  
1.01  
0.4  
ns  
ns  
ns  
ns  
ns  
B4  
th(CLKXAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbspx_clkx active edge  
Master  
Slave  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-45 and Table 6-46.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-44. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Receive Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
33.12  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
16.56  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-45 and Table 6-46.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-45. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Receive Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
B3  
tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before  
mcbspx_clkx active edge  
Master  
Slave  
6.49  
5.80  
1.01  
0.4  
12.90  
12.21  
1.01  
ns  
ns  
ns  
ns  
ns  
B4  
th(CLKXAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbspx_clkx active edge  
Master  
Slave  
0.4  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
5.81  
12.21  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
ns  
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(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-41 and Table 6-42.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-46. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Receive  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
44.37  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
22.18  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-41 and Table 6-42.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins)  
(2) See Section 4.3.4, Processor Clocks.  
mcbspx_clkr  
B2  
B2  
mcbspx_fsr  
mcbspx_dr  
B3  
B4  
D7  
D6  
D5  
SWPS038-062  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-32. McBSP Rising Edge Receive Timing in Master Mode  
mcbspx_clkr  
mcbspx_fsr  
mcbspx_dr  
B5  
B6  
B3  
B4  
D7  
D6  
D5  
SWPS038-063  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-33. McBSP Rising Edge Receive Timing in Slave Mode  
6.6.1.1.1.2 Timing with Rising Edge as Activation Edge—Transmit Mode  
Table 6-47. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements—Rising Edge and Transmit Mode(1)  
(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
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(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-48. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics—Rising Edge and Transmit  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
14.79  
0.7  
29.58  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
14.79  
13.89  
0.6  
0.6  
29.58  
28.68  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-49. McBSP4 (Set #1) Timing Requirements—Rising Edge and Transmit Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-51 and Table 6-52.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-50. McBSP4 (Set #1) Switching Characteristics—Rising Edge and Transmit Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
16.56  
0.7  
33.12  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
16.56  
17.15  
0.6  
0.6  
33.12  
32.22  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-51 and Table 6-52.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-51. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements—Rising Edge and Transmit Mode(1)  
(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
5.81  
12.21  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-47 and Table 6-48.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-52. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Transmit  
208  
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Table 6-52. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Rising Edge and Transmit  
Mode(1) (2) (continued)  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
22.18  
0.7  
44.37  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
21.28  
21.28  
0.6  
0.6  
43.47  
43.47  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-47 and Table 6-48.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
mcbspx_clkx  
B2  
B2  
B8  
mcbspx_fsx  
mcbspx_dx  
D7  
D6  
D5  
SWPS038-064  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-34. McBSP Rising Edge Transmit Timing in Master Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B5  
B6  
B8  
D7  
D6  
D5  
SWPS038-065  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-35. McBSP Rising Edge Transmit Timing in Slave Mode  
6.6.1.1.2 Falling Edge as Activation Edge  
6.6.1.1.2.1 Timing with Falling Edge as Activation Edge Mode—Receive Mode  
Table 6-53. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements—Falling Edge and Receive Mode(1)  
(2)  
NO.  
B3  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
8.63  
7.94  
1.01  
0.4  
tsu(DRV-CLKAE)  
Setup time, mcbspx_dr valid before  
mcbsp1_clkr / mcbspx_clkx active edge  
Master  
Slave  
4.36  
3.67  
1.01  
0.4  
ns  
ns  
ns  
ns  
ns  
B4  
th(CLKAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbsp1_clkr / mcbspx_clkx active edge  
Master  
Slave  
B5  
B6  
tsu(FSV-CLKAE)  
th(CLKAE-FSV)  
Setup time, mcbsp1_fsr / mcbspx_fsx valid before  
mcbsp1_clkr / mcbspx_clkx active edge  
3.7  
7.94  
Hold time, mcbsp1_fsr / mcbspx_fsx valid after  
mcbsp1_clkr / mcbspx_clkx active edge  
0.5  
0.5  
ns  
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(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-54. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics—Falling Edge and Receive  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
29.58  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKAE-FSV)  
Delay time, mcbsp1_clkr / mcbspx_clkx active edge to  
mcbsp1_fsr / mcbspx_fsx valid  
14.79  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-55. McBSP4 (Set #1) Timing Requirements—Falling Edge and Receive Mode(1) (2)  
NO.  
B3  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
8.63  
7.94  
1.01  
0.4  
tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before  
mcbspx_clkx active edge  
Master  
Slave  
2.87  
3.67  
1.01  
0.4  
ns  
ns  
ns  
ns  
ns  
B4  
th(CLKXAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbspx_clkx active edge  
Master  
Slave  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-57 and Table 6-58.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-56. McBSP4 (Set #1) Switching Characteristics—Falling Edge and Receive Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
33.12  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
16.56  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-57 and Table 6-58.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-57. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements—Falling Edge and Receive Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
B3  
tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before  
mcbspx_clkx active edge  
Master  
Slave  
6.5  
5.81  
1.01  
0.4  
12.9  
ns  
ns  
ns  
ns  
ns  
12.21  
1.01  
0.4  
B4  
th(CLKXAE-DRV)  
Hold time, mcbspx_dr valid after  
mcbspx_clkx active edge  
Master  
Slave  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
5.81  
12.21  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
ns  
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(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-53 and Table 6-54.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-58. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Falling Edge and Receive  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
44.37  
UNIT  
MIN  
0.7  
MAX  
MIN  
B2  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
22.19  
0.7  
ns  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-53 and Table 6-54.  
(2) See Section 4.3.4, Processor Clocks.  
mcbspx_clkr  
B2  
B2  
mcbspx_fsr  
mcbspx_dr  
B3  
B4  
D7  
D6  
D5  
SWPS038-066  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-36. McBSP Falling Edge Receive Timing in Master Mode  
mcbspx_clkr  
mcbspx_fsr  
mcbspx_dr  
B5  
B6  
B3  
B4  
D7  
D6  
D5  
SWPS038-067  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-37. McBSP Falling Edge Receive Timing in Slave Mode  
6.6.1.1.2.2 Timing with Falling Edge as Activation Edge—Transmit Mode  
Table 6-59. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements—Falling Edge and Transmit Mode(1)  
(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
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(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-60. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics—Falling Edge and Transmit  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
14.79  
0.7  
29.58  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
14.79  
13.89  
0.6  
0.6  
29.58  
28.68  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode  
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-61. McBSP4 (Set #1) Timing Requirements—Falling Edge and Transmit Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
3.67  
7.94  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-63 and Table 6-64.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-62. McBSP4 (Set #1) Switching Characteristics—Falling Edge and Transmit Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
16.56  
0.7  
33.12  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
16.56  
17.15  
0.6  
0.6  
33.12  
32.22  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by  
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-63 and Table 6-64.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-63. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements—Falling Edge and Transmit Mode(1)  
(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
B5  
B6  
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx  
active edge  
5.81  
12.21  
ns  
ns  
th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active  
edge  
0.5  
0.5  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-60 and Table 6-61.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-64. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Falling Edge and Transmit  
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Table 6-64. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics—Falling Edge and Transmit  
Mode(1) (2) (continued)  
Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
B2  
B8  
td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx  
valid  
0.7  
22.18  
0.7  
44.37  
ns  
td(CLKXAE-DXV)  
Delay time, mcbspx_clkx active edge to  
mcbspx_dx valid  
Master  
Slave  
0.6  
0.6  
21.28  
21.28  
0.6  
0.6  
43.47  
43.47  
ns  
ns  
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode  
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are  
specified in Table 6-60 and Table 6-61.  
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).  
(2) See Section 4.3.4, Processor Clocks.  
mcbspx_clkx  
B2  
B2  
mcbspx_fsx  
mcbspx_dx  
B8  
D7  
D6  
D5  
SWPS038-068  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-38. McBSP Falling Edge Transmit Timing in Master Mode  
mcbspx_clkx  
mcbspx_fsx  
mcbspx_dx  
B5  
B6  
B8  
D7  
D6  
D5  
SWPS038-069  
(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.  
Figure 6-39. McBSP Falling Edge Transmit Timing in Slave Mode  
6.6.1.2 McBSP in TDM —Multipoint Mode (McBSP3)  
For T application in multipoint mode, the processor is considered as a slave. Table 6-66 and Table 6-67  
assume testing over the operating conditions and electrical characteristic conditions described below.  
Table 6-65. McBSP3 (Set #3) Timing Conditions—T Multipoint Mode(1)  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
1.0  
1.0  
8.5  
8.5  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(2)  
40  
pF  
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(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins)  
(2) The load setting of the IO buffer: LB0 = 0.  
Table 6-66. McBSP3 (Set #3) Timing Requirements—T Multipoint Mode(4)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
1 / tc(clkxH)  
tw(clkxH)  
Frequency, input clock mcbsp3_clkx  
6
6
MHz  
ns  
Pulse duration, input clock mcbsp3_clkx high  
Pulse duration, input clock mcbsp3_clkx low  
Duty cycle error, input clock mcbsp3_clkx  
0.5P(1)  
0.5P(1)  
0.5P(1)  
0.5P(1)  
tw(clkxL)  
ns  
tdc(clkx)  
–8.14  
9
8.14  
–8.14  
9
8.14  
ns  
B3(3)  
B4(3)  
B5(3)  
B6(3)  
tsu(drV-clkxAE)  
Setup time, input data mcbsp3_dr valid before input  
clock mcbsp3_clkx active edge  
ns  
th(clkxAE-drV)  
tsu(fsxV-clkxAE)  
th(clkxAE-fsxV)  
Hold time, input data mcbsp3_dr valid after input clock  
mcbsp3_clkx active edge  
2.4  
9
2.4  
9
ns  
ns  
ns  
Setup time, input frame synchronization mcbsp3_fsx  
valid before input clock mcbsp3_clkx active edge  
Hold time, input frame synchronization mcbsp3_fsx  
valid after input clock mcbsp3_clkx active edge  
2.4  
2.4  
(1) P = input clock mcbsp3_clkx period in ns  
(2) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).  
(3) See Section 6.6.1.1 for corresponding figures.  
(4) See Section 4.3.4, Processor Clocks.  
Table 6-67. McBSP3 (Set #3) Switching Characteristics—T Multipoint Mode(1)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
0.6  
MAX  
MIN  
MAX  
B8(2)  
td(clkxAE-dxV)  
Delay time, mcbsp3_clkx active edge to output data  
mcbsp3_dx valid  
15.89  
0.6  
28.68  
ns  
(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).  
(2) See Section 6.6.1.1 for corresponding figures.  
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6.6.2 Multichannel Serial Port Interface (McSPI)  
NOTE  
For more information, see Multichannel SPI chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
McSPI allows a duplex, synchronous, serial communication between a local host and SPI compliant  
external devices. The following timings are applicable to the different configurations of McSPI in  
master/slave mode for any McSPI and any channel (n).  
6.6.2.1 McSPI—Slave Mode  
In slave mode, McSPI initiates data transfer on the data lines (mcspix_somi, mcspix_simo) when it  
receives an SPI clock (mcspix_clk) from the external SPI master device.  
Table 6-69 and Table 6-70 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-40 and Figure 6-41).  
Table 6-68. McSPI Timing Conditions—Slave Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
4
4
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
20  
pF  
(1) The load setting of the IO buffer: LB0 = 1.  
Table 6-69. McSPI Timing Requirements—Slave Mode(1) (3)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
24  
0.45*P(2) 0.55*P(2) 0.45*P(2) 0.55*P(2)  
OPP50  
MAX  
12  
UNIT  
MIN  
SS0  
SS1  
SS2  
1/tc(CLK)  
tw(CLK)  
Frequency, mcspix_clk  
MHz  
ns  
Pulse duration, mcspix_clk high or low  
tsu(SIMOV-CLKAE) Setup time, mcspix_simo valid before mcspix_clk  
active edge  
4.2  
9.5  
ns  
SS3  
SS4  
SS5  
th(SIMOV-CLKAE) Hold time, mcspix_simo valid after mcspix_clk active  
edge  
4.6  
9.9  
ns  
ns  
ns  
tsu(CS0V-CLKFE) Setup time, mcspix_cs0 valid before mcspix_clk first  
edge  
13.8  
13.8  
28.6  
28.6  
th(CS0I-CLKLE)  
Hold time, mcspix_cs0 invalid after mcspix_clk last  
edge  
(1) In mcspix, x is equal to 1, 2, 3, or 4.  
(2) P = mcspix_clk clock period  
(3) See Section 4.3.4, Processor Clocks.  
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UNIT  
Table 6-70. McSPI Switching Characteristics—Slave Mode(1) (3) (4)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
MIN  
1.8  
MAX  
MIN  
SS6  
SS7  
td(CLKAE-SOMIV) Delay time, mcspix_clk active edge to mcspix_somi  
shifted  
15.9  
3.2  
31.7  
ns  
ns  
td(CS0AE-SOMIV) Delay time, mcspix_cs0 active edge to  
mcspix_somi shifted  
Modes 0  
and 2(2)  
15.9  
31.7  
(1) In mcspix, x is equal to 1, 2, 3, or 4.  
(2) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all  
software configurable:  
–
mcspix_clk(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2)  
For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.  
(3) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and  
capture input data.  
(4) See Section 4.3.4, Processor Clocks.  
PHA=0  
EPOL=1  
mcspi_cs(IN)  
SS1  
SS0  
SS4  
SS1  
SS1  
SS5  
POL=0  
POL=1  
mcspi_clk(IN)  
SS1  
SS0  
mcspi_clk(IN)  
SS7  
Bit n–1  
SS6  
Bit n–2  
SS6  
Bit n–3  
Bit n–4  
Bit 0  
mcspi_somi(OUT)  
PHA=1  
EPOL=1  
mcspi_cs(IN)  
mcspi_clk(IN)  
SS1  
SS0  
SS4  
SS1  
SS1  
SS5  
POL=0  
POL=1  
SS1  
SS0  
mcspi_clk(IN)  
SS6  
Bit n–1  
SS6  
Bit n–2  
SS6  
Bit n–3  
SS6  
mcspi_somi(OUT)  
Bit 1  
Bit 0  
SWPS038-070  
(1) The active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is  
software configurable with the bit MCSPI_CH(i)CONF[1] = POL and the bit MCSPI_CH(i)CONF[0] = PHA.  
(2) The polarity of mcspi_cs is software configurable with the bit MCSPI_CH(i)CONF[6] = EPOL.  
Figure 6-40. McSPI—Slave Mode—Transmit  
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PHA=0  
EPOL=1  
mcspi_cs(IN)  
SS1  
SS1  
SS0  
SS0  
SS4  
SS1  
SS1  
SS5  
POL=0  
POL=1  
mcspi_clk(IN)  
mcspi_clk(IN)  
mcspi_simo(IN)  
mcspi_cs(IN)  
mcspi_clk(IN)  
mcspi_clk(IN)  
SS3  
SS2  
SS3  
SS2  
Bit n–1  
Bit n–3  
Bit n–2  
Bit n–4  
Bit 0  
PHA=1  
EPOL=1  
SS1  
SS0  
SS4  
SS1  
SS1  
SS5  
POL=0  
POL=1  
SS1  
SS0  
SS2  
SS3  
SS2  
Bit n–1  
SS3  
Bit n–2  
Bit n–3  
Bit 0  
mcspi_simo(IN)  
Bit 1  
SWPS038-071  
(1) The active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is  
software configurable with the bit MCSPI_CH(i)CONF[1] = POL and the bit MCSPI_CH(i)CONF[0] = PHA.  
(2) The polarity of mcspi_cs is software configuable with the bit MCSPI_CH(i)CONF[6] = EPOL.  
Figure 6-41. McSPI—Slave Mode—Receive  
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6.6.2.2 McSPI—Master Mode  
In master mode, McSPI supports multichannel communication. McSPI initiates a data transfer on the data  
lines (SPIDAT [1:0]) and generates clock (SPICLK) and control signals (SPIEN) to a single SPI slave  
device at a time.  
Table 6-72 and Table 6-75 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-42 and Figure 6-43).  
Table 6-71. McSPI Timing Conditions—Master Mode(1)  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
4
4
ns  
ns  
Output Conditions  
McSPI1, McSPI2, McSPI3, and McSPI4  
CLOAD  
Output load capacitance for spix_csn signals  
20  
30  
20  
pF  
pF  
pF  
McSPI2 and McSPI3  
CLOAD  
Output load capacitance for spix_clk and spix_simo  
McSPI1 and McSPI4  
CLOAD  
Output load capacitance for spix_clk and spix_simo  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-72. McSPI1, 2, and 4 Timing Requirements—Master Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
SM2  
SM3  
tsu(SOMIV-CLKAE) Setup time, mcspix_somi valid before mcspix_clk  
active edge  
1.1  
1.5  
ns  
ns  
th(SOMIV-CLKAE) Hold time, mcspix_somi valid after mcspix_clk active  
edge  
1.9  
2.8  
(1) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-73. McSPI1, 2, and 4 Switching Characteristics—Master Mode(1) (6)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
48  
0.45*P(3) 0.55*P(3) 0.45*P(3) 0.55*P(3)  
OPP50  
MIN MAX  
24  
UNIT  
SM0  
SM1  
1/tc(CLK)  
tw(CLK)  
tR(clk)  
Frequency, mcspix_clk  
MHz  
ns  
Pulse duration, mcspix_clk high or low  
Rise time, output clock mcspi1_clk and mcspi4_clk  
Rise time, output clock mcspi2_clk  
5.72  
7.33  
5.22  
6.77  
5.0  
5.68  
7.31  
5.21  
6.71  
11.3  
ns  
tF(clk)  
Fall time, output clock mcspi1_clk and mcspi4_clk  
Fall time, output clock mcspi2_clk  
ns  
ns  
SM4  
SM5  
td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo  
shifted  
–2.1  
–2.1  
td(CSnA-CLKFE)  
Delay time, mcspix_csi active to Modes 1 and 3(2)  
mcspix_clk first edge  
A(4) – 3.2  
B(5) – 3.2  
B(5) – 3.2  
A(4) – 3.2  
A(4) – 4.4  
B(5) – 4.4  
B(5) – 4.4  
A(4) – 4.4  
ns  
ns  
ns  
ns  
ns  
Modes 0 and 2(2)  
Modes 1 and 3(2)  
Modes 0 and 2(2)  
SM6  
SM7  
td(CLKLE-CSnI)  
Delay time, mcspix_clk last  
edge to mcspix_csi inactive  
td(CSnAE-SIMOV) Delay time, mcspix_csi active edge to mcspix_simo  
shifted  
5.0  
11.3  
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(1) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.  
(2) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all  
software configurable:  
–
–
mcspix_clk(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).  
mcspix_clk(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).  
For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.  
(3) P = mcspix_clk clock period  
(4) Case P = 20.8 ns, A = (TCS+0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register).  
Case P > 20.8 ns, A = TCS*P(3) (TCS is a bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of  
the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(5) B = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(6) See Section 4.3.4, Processor Clocks.  
Table 6-74. McSPI3 Timing Requirements—Master Mode(1)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
SM2  
SM3  
tsu(SOMIV-CLKAE) Setup time, mcspi3_somi valid before mcspi3_clk  
active edge  
1.5  
4.3  
ns  
ns  
th(SOMIV-CLKAE) Hold time, mcspi3_somi valid after mcspi3_clk active  
edge  
2.8  
5.9  
(1) See Section 4.3.4, Processor Clocks.  
Table 6-75. McSPI3 Switching Characteristics—Master Mode(1) (2) (6)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
24  
0.45*P(3) 0.55*P(3) 0.45*P(3) 0.55*P(3)  
OPP50  
MIN MAX  
12  
UNIT  
SM0  
SM1  
1/tc(CLK)  
tw(CLKH)  
tR(clk)  
Frequency, mcspi3_clk  
MHz  
ns  
Pulse duration, mcspi3_clk high or low  
Rise time, output clock mcspi3_clk  
CBP  
7.33  
7.31  
ns  
Balls:  
AE2 /  
AE13  
CBP  
Ball: H26  
4.31  
6.77  
4.30  
6.71  
tF(clk)  
Fall time, output clock mcspi3_clk  
CBP  
ns  
Balls:  
AE2 /  
AE13  
CBP  
4.0  
4.0  
Ball: H26  
SM4  
SM5  
td(CLK-SIMO)  
td(CSn-CLK)  
Delay time, mcspi3_clk active edge to mcspi3_simo  
shifted  
–2.1  
11.3  
–5.3  
23.6  
ns  
ns  
ns  
ns  
ns  
ns  
Delay time, mcspi3_csi active to  
mcspi3_clk first edge  
Modes 1 A(4) – 4.4  
and 3  
A(4)  
–
10.1  
B(5)  
–
10.1  
B(5)  
–
10.1  
A(4)  
–
10.1  
Modes 0 B(5) – 4.4  
and 2  
SM6  
SM7  
td(CLK-CSn)  
Delay time, mcspi3_clk last edge to  
mcspi3_csi inactive  
Modes 1 B(5) – 4.4  
and 3  
Modes 0 A(4) – 4.4  
and 2  
td(csn-simo)  
Delay time, mcspi3_csi active edge to  
mcspi3_simo shifted  
Modes 0  
and 2  
11.3  
23.6  
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(1) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and  
mcspi3_somi is latched is all software configurable.  
–
–
mcspi3_clk phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).  
mcspi3_clk phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).  
For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.  
(2) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and  
capture input data.  
(3) P = mcspi3_clk clock period  
(4) Case P = 20.8 ns, A = (TCS + 0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register).  
Case P > 20.8 ns, A = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(5) B = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
(6) See Section 4.3.4, Processor Clocks.  
PHA=0  
EPOL=1  
mcspi_cs(OUT)  
SM0  
SM1  
SM5  
SM1  
SM1  
SM6  
POL=0  
POL=1  
mcspi_clk(OUT)  
SM0  
SM1  
mcspi_clk(OUT)  
SM7  
Bit n–1  
SM4  
Bit n–2  
SM4  
Bit n–3  
Bit n–4  
Bit 0  
mcspi_simo(OUT)  
PHA=1  
EPOL=1  
mcspi_cs(OUT)  
mcspi_clk(OUT)  
SM1  
SM0  
SM5  
SM1  
SM1  
SM6  
POL=0  
POL=1  
SM0  
SM1  
mcspi_clk(OUT)  
SM4  
Bit n–1  
SM4  
SM4  
Bit n–3  
SM4  
Bit n–2  
Bit 1  
Bit 0  
mcspi_simo(OUT)  
SWPS038-072  
(1) The active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is  
software configurable with the bit MCSPI_CH(i)CONF[1] = POL and the bit MCSPI_CH(i)CONF[0] = PHA.  
(2) The polarity of mcspi_ncs is software configuable with the bit MCSPI_CH(i)CONF[6] = EPOL.  
Figure 6-42. McSPI—Master Mode—Transmit  
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PHA=0  
EPOL=1  
mcspi_cs(OUT)  
SM0  
SM1  
SM5  
SM1  
SM6  
POL=0  
POL=1  
mcspi_clk(OUT)  
SM1  
SM0  
SM1  
mcspi_clk(OUT)  
mcspi_somi(IN)  
SM2  
SM3  
SM2  
SM3  
Bit n–1  
Bit n–2  
Bit n–3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
mcspi_cs(OUT)  
mcspi_clk(OUT)  
SM1  
SM0  
SM5  
SM1  
SM1  
SM6  
POL=0  
POL=1  
SM0  
SM1  
mcspi_clk(OUT)  
mcspi_somi(IN)  
SM2  
SM3  
SM2  
SM3  
Bit n–1  
Bit n–2  
Bit n–3  
Bit 1  
Bit 0  
SWPS038-073  
(1) The active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is  
software configurable with the bit MCSPI_CH(i)CONF[1] = POL and the bit MCSPI_CH(i)CONF[0] = PHA.  
(2) The polarity of mcspi_ncs is software configuable with the bit MCSPI_CH(i)CONF[6] = EPOL.  
Figure 6-43. McSPI—Master Mode—Receive  
6.6.3 Multiport Full-Speed Universal Serial Bus (FS-USB)  
NOTE  
For more information, see High-Speed USB Host Subsystem and High-Speed USB OTG  
Controller / High-Speed USB Host Subsystem section of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
The processor provides three USB ports working in full- and low-speed data transactions (up to 12Mbit/s).  
When connected to either a serial link controller or a serial PHY (PHY interface modes) it supports:  
•
•
•
6-pin (Tx: Dat/Se0 or Tx: Dp/ ) unidirectional mode  
4-pin bidirectional mode  
3-pin bidirectional  
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6.6.3.1 FS-USB—Unidirectional Standard 6-pin Mode  
Table 6-77 and Table 6-78 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-44).  
Table 6-76. LS- / FS-USB Timing Conditions—Unidirectional Standard 6-Pin Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2
2
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
15  
pF  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-77. LS- / FS-USB Timing Requirements—Unidirectional Standard 6-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
FSU1  
FSU2  
FSU3  
FSU4  
td(vp,vm)  
td(vp,vm)  
td(rcvU0)  
td(rcvU1)  
Time duration, mmx_rxdp and mmx_rx low together  
during transition  
14  
14  
ns  
ns  
ns  
ns  
Time duration, mmx_rxdp and mmx_rx high together  
during transition  
8
8
Time duration, mmx_rrxcv undefine during a single  
end 0 (mmx_rxdp and mmx_rx low together)  
14  
8
14  
8
Time duration, mmx_rxrcv undefine during a single  
end 1 (mmx_rxdp and mmx_rx high together)  
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-78. LS- / FS-USB Switching Characteristics—Unidirectional Standard 6-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN  
OPP50  
MAX  
UNIT  
MAX  
84.8  
84.8  
1.5  
MIN  
81.8  
81.8  
FSU5  
FSU6  
FSU7  
FSU8  
FSU9  
td(txenL-dV)  
td(txenL-se0V)  
ts(d-se0)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
Delay time, mmx_txdat invalid to mmx_txen_n high  
Delay time, mmx_txse0 invalid to mmx_txen_n high  
81.8  
81.8  
84.8  
84.8  
1.5  
ns  
ns  
ns  
ns  
ns  
td(dI-txenH)  
td(se0I-txenH)  
81.8  
81.8  
81.8  
81.8  
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
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mmx_txen_n  
mmx_txdat  
mmx_txse0  
mmx_rxdp  
mmx_rxdm  
mmx_rxrcv  
Receive  
FSU5  
FSU6  
FSU8  
FSU9  
FSU7  
FSU1  
FSU1  
FSU3  
FSU2  
FSU2  
FSU4  
SWPS038-074  
(1) In mmx, x is equal to 0, 1, or 2.  
Figure 6-44. LS- / FS-USB—Unidirectional Standard 6-Pin Mode  
6.6.3.2 FS-USB—Bidirectional Standard 4-pin Mode  
Table 6-80 and Table 6-81 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-45).  
Table 6-79. LS- / FS-USB Timing Conditions—Bidirectional Standard 4-Pin Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2
2
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
15  
pF  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-80. LS- / FS-USB Timing Requirements—Bidirectional Standard 4-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
FSU10 td(d,se0)  
FSU11 td(d,se0)  
FSU12 td(rcvU0)  
FSU13 td(rcvU1)  
Time duration, mmx_txdat and mmx_txse0 low  
together during transition  
14  
14  
ns  
ns  
ns  
ns  
Time duration, mmx_txdat and mmx_txse0 high  
together during transition  
8
8
Time duration, mmx_rrxcv undefine during a single  
end 0 (mmx_txdat and mmx_txse0 low together)  
14  
8
14  
8
Time duration, mmx_rxrcv undefine during a single  
end 1 (mmx_txdat and mmx_txse0 high together)  
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-81. LS- / FS-USB Switching Characteristics—Bidirectional Standard 4-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN  
OPP50  
MAX  
UNIT  
MAX  
84.8  
84.8  
1.5  
MIN  
81.8  
81.8  
FSU14 td(txenL-dV)  
FSU15 td(txenL-se0V)  
FSU16 ts(d-se0)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
81.8  
81.8  
84.8  
84.8  
1.5  
ns  
ns  
ns  
ns  
FSU17 td(dV-txenH)  
Delay time, mmx_txdat invalid before mmx_txen_n  
high  
81.8  
81.8  
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Table 6-81. LS- / FS-USB Switching Characteristics—Bidirectional Standard 4-Pin Mode(1) (2) (continued)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
81.8  
OPP50  
MAX  
UNIT  
MIN  
FSU18 td(se0V-txenH)  
Delay time, mmx_txse0 invalid before mmx_txen_n  
high  
81.8  
ns  
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
Transmit  
FSU16  
mmx_txen_n  
Receive  
FSU10  
FSU14  
FSU17  
FSU11  
mmx_txdat  
FSU15  
FSU18  
FSU10  
FSU12  
FSU11  
FSU13  
mmx_txse0  
mmx_rxrcv  
SWPS038-075  
(1) In mmx, x is equal to 0, 1, or 2.  
Figure 6-45. LS- / FS-USB—Bidirectional Standard 4-Pin Mode  
6.6.3.3 FS-USB—Bidirectional Standard 3-pin Mode  
Table 6-83 and Table 6-84 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-46).  
Table 6-82. LS- / FS-USB Timing Conditions—Bidirectional Standard 3-Pin Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2
2
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
15  
pF  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-83. LS- / FS-USB Timing Requirements—Bidirectional Standard 3-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
FSU19 td(d,se0)  
FSU20 td(d,se0)  
Time duration, mmx_txdat and mmx_txse0 low  
together during transition  
14  
14  
ns  
ns  
Time duration, mmx_tsdat and mmx_txse0 high  
together during transition  
8
8
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
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Table 6-84. LS- / FS-USB Switching Characteristics—Bidirectional Standard 3-Pin Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN  
OPP50  
MAX  
UNIT  
MAX  
84.8  
84.8  
1.5  
MIN  
81.8  
81.8  
FSU21 td(txenL-dV)  
FSU22 td(txenL-se0V)  
FSU23 ts(d-se0)  
Delay time, mmx_txen_n low to mmx_txdat valid  
Delay time, mmx_txen_n low to mmx_txse0 valid  
Skew between mmx_txdat and mmx_txse0 transition  
Delay time, mmx_txdat invalid to mmx_txen_n high  
Delay time, mmx_txse0 invalid to mmx_txen_n high  
81.8  
81.8  
84.8  
84.8  
1.5  
ns  
ns  
ns  
ns  
ns  
FSU24 td(dI-txenH)  
FSU25 td(se0I-txenH)  
81.8  
81.8  
81.8  
81.8  
(1) In mmx, x is equal to 0, 1, or 2.  
(2) See Section 4.3.4, Processor Clocks.  
Transmit  
mmx_txen_n  
Receive  
FSU21  
FSU24  
FSU25  
FSU19  
FSU20  
mmx_txdat  
FSU22  
FSU23  
FSU19  
FSU20  
mmx_txse0  
SWPS038-076  
Figure 6-46. LS- / FS-USB—Bidirectional Standard 3-Pin Mode(1)  
(1) In mmx, x is equal to 0, 1, or 2.  
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6.6.4 Multiport High-Speed Universal Serial Bus (HS-USB)  
NOTE  
For more information, see High-Speed USB Host Subsystem and High-Speed USB OTG  
Controller / High-Speed USB OTG Controller and High-Speed USB Host Subsystem and  
High-Speed USB OTG Controller / High-Speed USB Host Subsystem sections of the  
AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
In addition to the full-speed (FS) USB controller, a high-speed (HS) USB OTG controller is incorporated in  
the device. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3 described  
below:  
•
•
•
Port 0:  
–
12-bit slave mode (SDR)  
Ports 1 and 2:  
–
12-bit master mode (SDR)  
Port 3:  
6.6.4.1 HSUSB0—Port 0—12-bit Slave Mode  
Table 6-86 and Table 6-87 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-47).  
Table 6-85. HSUSB0 Timing Conditions—12-bit Slave Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
2
2
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
3.5  
pF  
(1) Buffer strength configuration: LB0 = 0.  
Table 6-86. HSUSB0 Timing Requirements—12-bit Slave Mode(3) (4)  
NO.  
PARAMETER  
OPP100  
UNIT  
MIN  
MAX  
60.03  
500  
HSU0  
HSU3  
HSU4  
fp(CLK)  
hsusb0_clk clock frequency(1)  
Cycle jitter(2), hsusb0_clk  
MHz  
ps  
tJ(CLK)  
ts(DIRV-CLKH)  
ts(NXTV-CLKH)  
th(CLKH-DIRIV)  
th(CLKH-NXT/IV)  
ts(DATAV-CLKH)  
th(CLKH-DATIV)  
Setup time, hsusb0_dir valid before hsusb0_clk rising edge  
Setup time, hsusb0_nxt valid before hsusb0_clk rising edge  
Hold time, hsusb0_dir valid after hsusb0_clk rising edge  
Hold time, hsusb0_nxt valid after hsusb0_clk rising edge  
Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge  
Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge  
6.68  
6.68  
0
ns  
ns  
ns  
0
ns  
HSU5  
HSU6  
6.68  
0
ns  
ns  
(1) Related with the input maximum frequency supported by the USB module.  
(2) Maximum cycle jitter supported by hsusb0_clk input clock  
(3) The timing requirements are assured up to the cycle jitter error condition specified.  
(4) See Section 4.3.4, Processor Clocks.  
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Table 6-87. HSUSB0 Switching Characteristics—12-bit Slave Mode(1)  
NO.  
PARAMETER  
OPP100  
UNIT  
MIN  
MAX  
HSU1  
HSU2  
td(clkL-STPV)  
td(clkL-STPIV)  
td(clkL-DV)  
Delay time, hsusb0_clk high to output usb0_stp valid  
8.6  
ns  
ns  
ns  
ns  
Delay time, hsusb0_clk high to output usb0_stp invalid  
Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid  
Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid  
0
0
8.6  
td(clkL-DIV)  
(1) See Section 4.3.4, Processor Clocks.  
HSU0  
hsusb0_clk  
hsusb0_stp  
HSU1  
HSU1  
HSU3  
HSU4  
hsusb0_dir  
and  
hsusb0_nxt  
HSU5  
HSU2  
HSU2  
HSU6  
Data_OUT  
Data_IN  
hsusb0_data[7:0]  
SWPS038-080  
Figure 6-47. HSUSB0—12-bit Slave Mode  
6.6.4.2 HSUSB1 and HSUSB2—Ports 1 and 2—12-bit Slave Mode  
Table 6-89 and Table 6-90 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-48).  
Table 6-88. HSUSB1 and HSUSB2 Timing Conditions—12-bit Master Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
3
2
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
5
pF  
(1) Buffer strength configuration: LB0 = 0.  
Table 6-89. HSUSB1 and HSUSB2 Timing Requirements—12-bit Master Mode(1) (2)  
NO.  
PARAMETER  
OPP100  
MAX  
UNIT  
MIN  
HSU3  
tsu(dirV-clkH)  
tsu(nxtV-clkH)  
th(clkH-dirIV)  
th(clkH-nxtIV)  
tsu(dV-clkH)  
Setup time, input direction control hsusbx_dir valid before output clock  
hsusbx_clk rising edge  
9.3  
ns  
ns  
ns  
ns  
ns  
Setup time, input next signal hsusbx_nxt valid before output clock  
hsusbx_clk rising edge  
9.3  
HSU4  
HSU5  
Hold time, input direction control hsusbx_dir valid after output clock  
hsusbx_clk rising edge  
–0.52  
–0.52  
9.3  
Hold time, input next signal hsusbx_nxt valid after output clock  
hsusbx_clk rising edge  
Setup time, input data hsusbx_data[7:0] valid before output clock  
hsusbx_clk rising edge  
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Table 6-89. HSUSB1 and HSUSB2 Timing Requirements—12-bit Master Mode(1) (2) (continued)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
–0.52  
UNIT  
HSU6  
th(clkH-dV)  
Hold time, input data hsusbx_data[7:0] valid after output clock  
hsusbx_clk rising edge  
ns  
(1) In hsusbx, x is equal to 1 or 2.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-90. HSUSB1 and HSUSB2 Switching Characteristics—12-bit Master Mode(1) (3)  
NO.  
PARAMETER  
OPP100  
MAX  
UNIT  
MIN  
HSU0  
HSU1  
fp(clk)  
Frequency, output clock hsusbx_clk  
Jitter standard deviation(2), output clock hsusbx_clk  
60  
MHz  
ps  
tJ(clk)  
400  
td(clkH-stpV)  
Delay time, output clock hsusbx_clk rising edge to output stop signal  
hsusbx_stp valid  
12.81  
ns  
td(clkH-stpIV)  
td(clkH-dV)  
td(clkH-dIV)  
Delay time, output clock hsusbx_clk rising edge to output stop signal  
hsusbx_stp invalid  
1.95  
1.95  
ns  
ns  
ns  
HSU2  
Delay time, output clock hsusbx_clk rising edge to output data  
hsusbx_data[7:0] valid  
12.81  
Delay time, output clock hsusbx_clk rising edge to output data  
hsusbx_data[7:0] invalid  
tR(d)  
tF(d)  
Rise time, output data hsusbx_data[7:0]  
Fall time, output data hsusbx_data[7:0]  
0
0
ns  
ns  
(1) In hsusbx, x is equal to 1 or 2.  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) See Section 4.3.4, Processor Clocks.  
HSU0  
hsusbx_clk  
HSU1  
HSU1  
hsusbx_stp  
HSU3  
HSU4  
hsusbx_dir  
and  
hsusbx_nxt  
HSU5  
HSU2  
HSU2  
HSU6  
Data_OUT  
Data_IN  
hsusbx_data[7:0]  
SWPS038-081  
(1) In hsusbx, x is equal to 1 or 2.  
Figure 6-48. HSUSB1 and HSUSB2—12-bit Master Mode  
6.6.5 Inter-Integrated Circuit Interface (I2C)  
NOTE  
For more information, see Multimaster High-Speed I2C Controller chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
The multi-master I2C peripheral provides an interface between two or more devices via an I2C serial bus.  
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The I2C controller supports the multi-master mode which allows more than one device capable of  
controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can  
operates as either transmitter or receiver, according to the function of the device. In addition to being a  
transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when  
performing data transfers. This data transfer is carried out via two serial bidirectional wires:  
•
•
An SDA data line  
An SCL clock line  
In Figure 6-49 the data transfer is in master or slave configuration with 7-bit addressing format.  
The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode (up to  
100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s).  
6.6.5.1 I2C—Standard and Fast Modes  
Table 6-91. I2C—Standard and Fast Modes  
NO.  
PARAMETER  
STANDARD MODE  
FAST MODE  
UNIT  
MIN  
MAX  
MIN  
MAX  
fscl  
Frequency, clock i2cx_scl(4)  
Pulse duration, clock i2cx_scl(4) high  
Pulse duration, clock i2cx_scl(4) low  
100  
400  
kHz  
ms  
I1  
I2  
I3  
tw(sclH)  
tw(sclL)  
tsu(sdaV-sclH)  
4.0  
4.7  
250  
0.6  
1.3  
100(1)  
ms  
Setup time, data i2cx_sda(4) valid before clock  
ns  
i2cx_scl(4) active level  
I4  
I5  
th(sclH-sdaV)  
tsu(sdaL-sclH)  
Hold time, data i2cx_sda(4) valid after clock  
i2cx_scl(4) active level  
Setup time, clock i2cx_scl(4) high after data  
i2cx_sda(4) low (for a START(5) condition or a  
repeated START condition)  
0(2)  
4.7  
3.45(3)  
0(2)  
0.6  
0.9(3)  
ms  
ms  
I6  
I7  
th(sclH-sdaH)  
Hold time, data i2cx_sda low level after clock  
i2cx_scl(4) high level (STOP condition)  
Hold time, data i2cx_sda(4) low level after  
clock i2cx_scl(4) high level (for a repeated  
START condition)  
4.0  
4.0  
0.6  
0.6  
ms  
ms  
th(sclH-RSTART)  
I8  
tw(sdaH)  
tR(scl)  
tF(scl)  
tR(sda)  
tF(sda)  
CB  
Pulse duration, data i2cx_sda(4) high between  
STOP and START conditions  
4.7(4)  
1.3  
ms  
ns  
ns  
ns  
ns  
pF  
Rise time, clock i2cx_scl(4)  
Fall time, clock i2cx_scl(4)  
Rise time, data i2cx_sda(4)  
Fall time, data i2cx_sda(4)  
Capacitive load for each bus line  
1000  
300  
20 +  
0.1CB  
300  
300  
300  
300  
400  
20 +  
0.1CB  
1000  
300  
20 +  
0.1CB  
20 +  
0.1CB  
400  
(1) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) ≥ 250 ns must then be  
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl(4). If such a device does stretch the low  
period of the i2cx_scl(4), it must output the next data bit to the i2cx_sda(4) line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns  
(according to the standard-mode I2C-bus specification) before the i2cx_scl(4) line is released.  
(2) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda(4) signal (see the fall and rise times of i2cx_scl(4)) to  
bridge the undefined region of the falling edge of i2cx_scl(4)  
.
(3) The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl(4) signal.  
(4) In i2cx, x is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.  
(5) After this time, the first clock is generated.  
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START  
START REPEAT  
START  
STOP  
i2cX_sda  
i2cX_scl  
I5  
I6  
I8  
I7  
I6  
I1  
I2  
I3  
I4  
SWPS038-084  
(1) In i2cX, X is equal to 1, 2, 3, or 4.  
6.6.5.2 I2C—High-Speed Mode  
NO.  
Figure 6-49. I2C—Standard and Fast Modes  
Table 6-92. I2C—High-Speed Mode  
PARAMETER  
MIN  
MAX  
3.4(5)  
UNIT  
MHz  
ns  
fscl  
Frequency, clock i2cx_scl(3)  
Pulse duration, clock i2cx_scl(3) high  
I1  
I2  
I3  
I4  
I5  
tw(sclH)  
60(1)  
160(1)  
10  
tw(sclL)  
Pulse duration, clock i2cx_scl(3) low  
Setup time, data i2cx_sda(3) valid before clock i2cx_scl(3) active level  
Hold time, data i2cx_sda(3) valid after clock i2cx_scl(3) active level  
ns  
tsu(sdaV-sclH)  
th(sclH-sdaV)  
tsu(sdaL-sclH)  
ns  
0(4)  
70  
ns  
Setup time, clock i2cx_scl(3) high after data i2cx_sda(3) low (for a  
160  
ns  
START(2) condition or a repeated START condition)  
I6  
I7  
th(sclH-sdaH)  
Hold time, data i2cx_sda(3) low level after clock i2cx_scl(3) high level  
(STOP condition)  
Hold time, data i2cx_sda(3) low level after clock i2cx_scl(3) high level  
(for a repeated START condition)  
160  
160  
ns  
ns  
th(sclH-RSTART)  
tR(scl)  
tR(scl)  
Rise time, clock i2cx_scl(3)  
Rise time, clock i2cx_scl(3) after a repeated START condition and after  
a bit acknowledge  
10  
10  
40  
80  
ns  
ns  
tF(scl)  
tR(sda)  
tF(sda)  
CB  
Fall time, clock i2cx_scl(3)  
Rise time, data i2cx_sda(3)  
Fall time, data i2cx_sda(3)  
Capacitive load for each bus line  
10  
10  
10  
40  
80  
ns  
ns  
ns  
pF  
80  
100  
(1) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(sclL) > 2 * tw(sclH)  
.
(2) After this time, the first clock is generated.  
(3) In i2cx, x is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.  
(4) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda(3) signal (see the fall and rise times of i2cx_scl(3)) to  
bridge the undefined region of the falling edge of i2cx_scl(3)  
.
(5) The I2C4 clock frequency in high-speed mode is equal to the sys_xtalin input clock frequency divided by 15.  
START REPEAT  
STOP  
IH7  
i2cX_sda  
IH5  
IH6  
IH1  
IH2  
IH3  
IH4  
i2cX_scl  
SWPS038-085  
(1) In i2cX, X is equal to 1, 2, 3, or 4.  
Figure 6-50. I2C—High-Speed Mode  
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Table 6-93. I2C Correspondence Standard vs Data Manual Timing References  
TI  
STANDARD-I2C  
Standard/Fast Modes  
FSCL  
High-Speed Mode  
FSCLH  
THIGH  
fscl  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
I8  
tw(sclH)  
THIGH  
tw(sclL)  
TLOW  
TLOW  
tsu(sdaV-sclH)  
th(sclH-sdaV)  
tsu(sdaL-sclH)  
th(sclH-sdaH)  
th(sclH-RSTART)  
tw(sdaH)  
TSU;DAT  
TSU;DAT  
TSU;STA  
THD;STA  
TSU;STO  
TBUF  
TSU;DAT  
TSU;DAT  
TSU;STA  
THD;STA  
TSU;STO  
6.6.6 HDQ / 1-Wire Interface (HDQ/1-Wire)  
NOTE  
For more information, see HDQ/1-Wire / HDQ/1-Wire chapter of the AM/DM37x Multimedia  
Device Technical Reference Manual (literature number SPRUGN4).  
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to  
communicate between the master and the slave. The protocols employ an asynchronous return to one  
mechanism where, after any command, the line is pulled high.  
6.6.6.1 HDQ/1-Wire—HDQ Mode  
Table 6-94 and Table 6-96 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-51 through Figure 6-55).  
Table 6-94. HDQ Interface Read Timing  
PARAMETER  
DESCRIPTION  
Read bit window timing  
MIN  
190  
TYP  
MAX  
250  
UNIT  
ms  
tCYCH  
tHW1  
Read one data valid after HDQ low  
Read zero data hold after HDQ low  
Response time from HDQ slave device(1)  
32(2)  
70(2)  
190  
66(2)  
145(2)  
320  
ms  
tHW0  
tRSPS  
ms  
ms  
(1) Defined by software  
(2) If the HDQ slave device drives a logic-low state after tHW0 max, it can be interpreted as a break pulse. For more information see  
Table 6-95 and the HDQ/1-Wire chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number  
SPRUGN4).  
Table 6-95. HDQ Sampling Cases(1)  
CASES  
FIRST SAMPLING (at 68 µs)  
L (logic-low state)  
SECOND SAMPLING (at 180 µs)  
L (logic-low state)  
1
2
3
4
L (logic-low state)  
H (logic-high state)  
H (logic-high state)  
H (logic-high state)  
L (logic-low state)  
H (logic-high state)  
(1) The different cases can be interpreted as follows:  
–
Case 1: If a logic-low state is present at the first sampling time and also at the second sampling time, the receive data can be  
interpreted as a break pulse.  
–
Case 2: If a logic-low state is present at the first sampling time and a logic-high state is present at the second sampling time, the  
receive data on the line is a zero (data).  
–
–
Case 3: Undefined.  
Case 4: If a logic-high state is present at the first sampling time and also at the second sampling time, the receive data on the line is  
a one (data).  
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Table 6-96. HDQ Write Switching Characteristics  
PARAMETER  
DESCRIPTION  
MIN  
190  
40  
TYP  
MAX  
UNIT  
ms  
tB  
Break timing  
tBR  
Break recovery time  
ms  
tCYCD  
tDW1  
tDW0  
Write bit windows timing  
190  
0.5  
86  
ms  
Write one data valid after HDQ low  
Write zero data hold after HDQ low  
50  
ms  
145  
ms  
tB  
tBR  
HDQ  
SWPS038-086  
Figure 6-51. HDQ Break and Break Recovery Timing— HDQ Interface Writing to Slave  
tB  
tBR  
HDQ  
First sampling time  
Second sampling time  
tHW1  
tHW0  
SWPS038-122  
Figure 6-52. HDQ Break Detection— HDQ Interface Reading Slave  
tCYCH  
tHW0  
tHW1  
HDQ  
SWPS038-087  
Figure 6-53. HDQ Interface Bit Read Timing (Data)  
tCYCD  
tDW0  
tDW1  
HDQ  
SWPS038-088  
Figure 6-54. HDQ Interface Bit Write Timing (Command/Address or Data)  
Command_byte_written  
0_(LSB)  
Data_byte_received  
1
tRSPS  
Break  
1
6
7_(MSB)  
0_(LSB)  
6
HDQ  
SWPS038-089  
Figure 6-55. HDQ—Communication  
6.6.6.2 HDQ/1-Wire—1-Wire Mode  
Table 6-97 and Table 6-98 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-56 through Figure 6-59).  
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Table 6-97. HDQ/1-Wire Timing Requirements—1-Wire Mode  
PARAMETER  
DESCRIPTION  
Presence pulse delay high  
MIN  
15  
TYP  
MAX  
UNIT  
ms  
tPDH  
tPDL  
tRDV  
tREL  
60  
240  
15  
Presence pulse delay low  
Read data valid time  
60  
ms  
tLOWR  
0
ms  
Read data release time  
45  
ms  
Table 6-98. HDQ/1-Wire Switching Characteristics—1-Wire Mode  
PARAMETER  
tRSTL  
DESCRIPTION  
MIN  
480  
480  
60  
1
TYP  
MAX  
UNIT  
ms  
Reset time low  
Reset time high  
Bit cycle time  
960  
tRSTH  
ms  
tSLOT  
120  
15  
ms  
tLOW1  
Write bit-one time  
Write bit-zero time(2)  
Recovery time  
ms  
tLOW0  
60  
1
120  
ms  
tREC  
ms  
tLOWR  
Read bit strobe time(1)  
1
15  
ms  
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.  
(2) tLOW0 must be less than tSLOT  
.
tRSTH  
tPDL  
tRTSL  
tPDH  
1-WIRE  
SWPS038-090  
Figure 6-56. 1-Wire Reset Timing  
tSLOT  
tREC  
tRDV  
tREL  
tLOWR  
1-WIRE  
SWPS038-091  
Figure 6-57. 1-Wire Read Bit Timing (Data)  
tSLOT  
tREC  
1-WIRE  
tLOW1  
SWPS038-123  
Figure 6-58. 1-Wire Write Bit-One Timing (Command / Address or Data)  
tSLOT  
tLOW0  
tREC  
1-WIRE  
SWPS038-124  
Figure 6-59. 1-Wire Write Bit-Zero Timing (Command/Address or Data)  
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6.6.7 Universal Asynchronous Receiver Transmitter (UART)  
NOTE  
For more information, see UART/IrDA/CIR chapter of the AM/DM37x Multimedia Device  
Technical Reference Manual (literature number SPRUGN4).  
6.6.7.1 UART3 IrDA  
The IrDA module can operate in three different modes:  
•
•
•
Slow infrared (SIR) (≤ 115.2 Kbits/s)  
Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)  
Fast infrared (FIR) (4 Mbits/s)  
Pulse Duration  
90%  
90%  
50%  
50%  
10%  
10%  
t
r
t
f
SWPS038-093  
Figure 6-60. UART IrDA Pulse Parameters  
6.6.7.1.1 UART3 IrDA—Receive Mode  
Table 6-99. UART3 IrDA Signaling Rate and Pulse Duration—Receive Mode  
SIGNALING RATE  
ELECTRICAL PULSE DURATION  
UNIT  
MIN  
TYP  
MAX  
SIR  
2.4 Kbit/s  
52.17  
13.10  
6.59  
3.34  
2.25  
1.17  
78.13  
19.53  
9.77  
4.88  
3.26  
1.63  
208.33  
52.08  
26.04  
13.02  
8.68  
ms  
ms  
ms  
ms  
ms  
ms  
9.6 Kbit/s  
19.2 Kbit/s  
38.4 Kbit/s  
57.6 Kbit/s  
115.2 Kbit/s  
MIR  
4.34  
0.576 Mbit/s  
1.152 Mbit/s  
FIR  
300.55  
192.04  
416.67  
208.33  
867.86  
433.83  
ns  
ns  
4.0 Mbit/s (Single pulse)  
4.0 Mbit/s (Double pulse)  
62.70  
125.00  
250.00  
170.63  
291.47  
ns  
ns  
208.53  
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Table 6-100. UART3 IrDA Rise and Fall Times—Receive Mode  
PARAMETER  
MIN  
TYP  
MAX  
200  
UNIT  
ns  
tR  
tF  
Rise time, input data uart3_rx_irrx  
Fall time, input data uart3_rx_irrx  
200  
ns  
6.6.7.1.2 UART3 IrDA—Transmit Mode  
Table 6-101. UART3 IrDA Signaling Rate and Pulse Duration—Transmit Mode  
SIGNALING RATE  
ELECTRICAL PULSE DURATION  
UNIT  
MIN  
TYP  
MAX  
SIR  
2.4 Kbit/s  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
78.1  
19.5  
9.75  
4.87  
3.25  
1.62  
ms  
ms  
ms  
ms  
ms  
ms  
9.6 Kbit/s  
19.2 Kbit/s  
38.4 Kbit/s  
57.6 Kbit/s  
115.2 Kbit/s  
MIR  
0.576 Mbit/s  
1.152 Mbit/s  
FIR  
414  
206  
416  
208  
419  
211  
ns  
ns  
4.0 Mbit/s (Single pulse)  
4.0 Mbit/s (Double pulse)  
123  
248  
125  
250  
128  
253  
ns  
ns  
6.6.8 Removable Media Interfaces  
6.6.8.1 Multimedia Memory Card and Secure Digital IO Card (MMC)  
NOTE  
For more information, see MMC/SD/SDIO Card Interface chapter of the AM/DM37x  
Multimedia Device Technical Reference Manual (literature number SPRUGN4).  
The MMC host controller provides an interface to high-speed and standard MMC, SD memory cards, or  
SDIO cards. The application interface is responsible for managing transaction semantics. The MMC/SDIO  
host controller deals with MMC/SDIO protocol at transmission level, packing data, adding CRC, start/end  
bit, and checking for syntactical correctness.  
There are three MMC interfaces on the device:  
•
MMC1:  
–
–
1.8-V / 3-V support  
4-bit in Standard MMC, High-Speed MMC, Standard SD, and High-Speed SD modes  
•
MMC2:  
–
–
–
1.8-V support  
8-bit without external transceiver  
4-bit with external transceiver allowing supporting 3-V peripherals. Transceiver direction control  
signals are multiplexed with the upper four data bits.  
•
MMC3:  
–
–
1.8-V support  
8-bit without external transceiver  
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6.6.8.1.1 MMC1 Interface—SD Identification Modes  
Table 6-103 and Table 6-104 assume testing over the recommended operating conditions and electrical  
characteristic conditions below.  
Table 6-102. MMC1 Interface Timing Conditions—SD Identification Modes  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
10  
10  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
40  
pF  
(1) Buffer strength configuration: LB0 = 0.  
Table 6-103. MMC1 Interface Timing Requirements—SD Identification Modes(1) (2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
MMC1 Interface (1.8-V IO)  
SD3  
tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
1198.4  
1249.2  
1198.4  
1249.2  
ns  
ns  
SD4  
th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC1 Interface (3.0-V IO)  
SD3  
tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
1198.4  
1249.2  
1198.4  
1249.2  
ns  
ns  
clock edge  
SD4  
th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
(1) Corresponding figures showing timing parameters are common with other interface modes. (See SD , HS SD modes).  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-104. MMC1 Interface Switching Characteristics—SD Identification Modes(4) (7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
SD Identification Mode  
SD1  
SD2  
SD2  
tc(clk)  
Frequency(1), output clock period  
0.4  
X(5)*PO(2)  
Y(6)*PO(2)  
125  
0.4  
X(5)*PO(2)  
Y(6)*PO(2)  
125  
MHz  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tJ(clk)  
Typical pulse duration, output clock high  
Typical pulse duration, output clock low  
Duty cycle error, output clock  
ns  
ns  
Jitter standard deviation(3), output clock  
200  
200  
ps  
MMC1 Interface (1.8-V IO)  
tR(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
tF(clk)  
tR(data)  
tF(data)  
td(CLKOH-CMD)  
10  
10  
10  
10  
SD5  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
6.3  
2492.7  
6.3  
2492.7  
MMC1 Interface (3.0-V IO)  
tR(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
tF(clk)  
tR(data)  
tF(data)  
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Table 6-104. MMC1 Interface Switching Characteristics—SD Identification Modes(4) (7) (continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
2492.7  
UNIT  
MIN  
6.3  
MAX  
MIN  
SD5  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
2492.7  
6.3  
ns  
(1) Related with the output clock maximum and minimum frequencies programmable in mmc module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) Corresponding figures showing timing parameters are common with other interface modes. (See SD, HS SD modes).  
(5) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(7) See Section 4.3.4, Processor Clocks.  
6.6.8.1.2 MMC1 Interface—High-Speed SD Mode  
Table 6-106 and Table 6-107 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-61 and Figure 6-62).  
Table 6-105. MMC1 Interface Timing Conditions—High-Speed SD Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
3
3
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
40  
pF  
(1) Buffer strength configuration: SPEEDCTRL = 1.  
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UNIT  
Table 6-106. MMC1 Interface Timing Requirements—High-Speed SD Mode(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
MIN  
MMC1 Interface (1.8-V IO)  
HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
5.6  
2.3  
5.6  
2.3  
26  
1.9  
26  
ns  
ns  
ns  
ns  
HSSD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
HSSD8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
1.9  
MMC1 Interface (3.0-V IO)  
HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
5.6  
2.3  
5.6  
2.3  
26  
1.9  
26  
ns  
ns  
ns  
ns  
HSSD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
HSSD8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
1.9  
(1) In mmc1_dat[n:0], n is equal to 3.  
(2) See Section 4.3.4, Processor Clocks.  
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Table 6-107. MMC1 Interface Switching Characteristics—High-Speed SD Mode(7)  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
High-Speed SD Mode  
HSSD1 tc(clk)  
HSSD2 tW(clkH)  
HSSD2 tW(clkL)  
tdc(clk)  
Frequency(1), output clock period  
48  
X(4)*PO(2)  
Y(5)*PO(2)  
1041.67  
24  
X(4)*PO(2)  
Y(5)*PO(2)  
2083.33  
MHz  
ns  
Typical pulse duration, output clock high  
Typical pulse duration, output clock low  
Duty cycle error, output clock  
ns  
ps  
tJ(clk)  
Jitter standard deviation(3), output clock  
200  
200  
ps  
MMC1 Interface (1.8-V IO)  
tR(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
3
3
ns  
ns  
ns  
ns  
ns  
tF(clk)  
3
3
3
3
tR(data)  
tF(data)  
3
3
HSSD5 td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.72  
3.72  
14.11  
4.13  
4.13  
34.53  
HSSD6 td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](6) transition  
14.11  
34.53  
ns  
MMC1 Interface (3.0-V IO)  
tR(clk)  
tF(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
3
3
ns  
ns  
ns  
ns  
ns  
3
3
3
3
tR(data)  
tF(data)  
3
3
HSSD5 td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.72  
3.72  
14.11  
4.13  
4.13  
34.53  
HSSD6 td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](6) transition  
14.11  
34.53  
ns  
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(5) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) In mmc1_dat[n:0], n is equal to 3.  
(7) See Section 4.3.4, Processor Clocks.  
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HSSD1  
HSSD2  
mmc1_clk  
mmc1_cmd  
HSSD3  
HSSD4  
HSSD7  
HSSD8  
mmc1_dat[3:0]  
SWPS038-094  
Figure 6-61. MMC1 Interface—High-Speed SD Mode—Data/Command Receive  
HSSD1  
HSSD2  
mmc1_clk  
mmc1_cmd  
HSSD5  
HSSD5  
HSSD6  
HSSD6  
mmc1_dat[3:0]  
SWPS038-095  
Figure 6-62. MMC1 Interface—High-Speed SD Mode—Data/Command Transmit  
6.6.8.1.3 MMC1 Interface—Standard SD Mode  
Table 6-109 and Table 6-110 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-63 and Figure 6-64).  
Table 6-108. MMC1 Interface Timing Conditions—Standard SD Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
10  
10  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
40  
pF  
(1) Buffer strength configuration: SPEEDCTRL = 1.  
Table 6-109. MMC1 Interface Timing Requirements—Standard SD Mode(1) (2) (4)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
MMC1 Interface (1.8-V IO)  
SD3  
SD4  
SD7  
SD8  
tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
3.3  
18.1  
3.3  
21.9  
36.7  
21.9  
36.7  
ns  
ns  
ns  
ns  
th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](3) valid before mmc1_clk  
rising clock edge  
th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](3) valid after mmc1_clk  
rising clock edge  
18.1  
MMC1 Interface (3.0-V IO)  
SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
3.3  
21.9  
ns  
clock edge  
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Table 6-109. MMC1 Interface Timing Requirements—Standard SD Mode(1) (2) (4) (continued)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
SD4  
SD7  
SD8  
th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](3) valid before mmc1_clk  
rising clock edge  
th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](3) valid after mmc1_clk  
rising clock edge  
18.1  
36.7  
ns  
ns  
ns  
3.3  
21.9  
36.7  
18.1  
(1) Timing parameters are referred to output clock specified in Table 6-110.  
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-110.  
(3) In mmc1_dat[n:0], n is equal to 3.  
(4) See Section 4.3.4, Processor Clocks.  
Table 6-110. MMC1 Interface Switching Characteristics—Standard SD Mode(7)  
NO.  
PARAMETER  
OPP100  
OPP50  
MIN  
UNIT  
MIN  
MAX  
MAX  
Standard SD Mode  
SD1  
SD2  
SD2  
tc(clk)  
Frequency(1), output clock period  
24  
12  
MHz  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tJ(clk)  
Typical pulse duration, output clock high  
Typical pulse duration, output clock low  
Duty cycle error, output clock  
X(4)*PO(2)  
Y(5)*PO(2)  
X(4)*PO(2)  
Y(5)*PO(2)  
ns  
2083.33  
200  
4166.67  
200  
ps  
Jitter standard deviation(3), output clock  
ps  
MMC1 Interface (1.8-V)  
tR(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
tF(clk)  
tR(data)  
tF(data)  
td(CLKOH-CMD)  
10  
10  
10  
10  
SD5  
SD6  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
6.13  
6.13  
35.53  
6.3  
6.3  
77.03  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](6) transition  
35.53  
77.03  
ns  
MMC1 Interface (3.0-V)  
tR(clk)  
Rise time, output clock  
Fall time, output clock  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
tF(clk)  
tR(data)  
tF(data)  
td(CLKOH-CMD)  
10  
10  
10  
10  
SD5  
SD6  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
6.13  
6.13  
35.53  
6.3  
6.3  
77.03  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](6) transition  
35.53  
77.03  
ns  
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
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All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(5) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) In mmc1_dat[n:0], n is equal to 3.  
(7) See Section 4.3.4, Processor Clocks.  
SD1  
SD2  
mmc1_clk  
mmc1_cmd  
SD3  
SD4  
SD7  
SD8  
mmc1_dat[n:0]  
SWPS038-098  
Figure 6-63. MMC1 Interface—Standard SD Mode—Data/Command Receive  
SD1  
SD2  
mmc1_clk  
mmc1_cmd  
SD5  
SD6  
SD5  
SD6  
mmc1_dat[n:0]  
SWPS038-099  
Figure 6-64. MMC1 Interface—Standard SD Mode—Data/Command Transmit  
6.6.8.1.4 MMC1 Interface—Standard MMC and MMC Identification Modes  
Table 6-112 and Table 6-113 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-65 and Figure 6-66).  
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Table 6-111. MMC1 Interface Timing Conditions—Standard MMC and MMC Identification Modes  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
3
3
ns  
ns  
Output Conditions  
CLOAD  
Output load capacitance(1)  
30  
pF  
(1) Buffer strength configuration: SPEEDCTRL = 1.  
Table 6-112. MMC1 Interface Timing Requirements—Standard MMC and MMC Identification Modes(2) (3) (4)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
MMC1 Interface (1.8-V IO)  
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
13.6  
7.7  
55.1  
7.5  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
13.6  
7.7  
55.1  
7.5  
MMC1 Interface (3.0-V IO)  
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
13.6  
7.7  
55.1  
7.5  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
13.6  
7.7  
55.1  
7.5  
(1) In mmc1_dat[n:0], n is equal to 3.  
(2) Timing parameters are referred to output clock specified in Table 6-113.  
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-113.  
(4) See Section 4.3.4, Processor Clocks.  
Table 6-113. MMC1 Interface Switching Characteristics—Standard MMC and MMC Identification Modes(7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
MMC Identification Mode  
MMC1 1/tc(clk)  
MMC2 tW(clkH)  
MMC2 tW(clkL)  
tdc(clk)  
Frequency(1), output clk period  
0.4  
X(5)*PO(2)  
Y(6)*PO(2)  
125  
0.4  
X(5)*PO(2)  
Y(6)*PO(2)  
125  
MHz  
ns  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
ns  
ns  
tJ(clk)  
Jitter standard deviation(3), output clk  
200  
200  
ps  
Standard MMC Identification Mode  
MMC1 tc(clk)  
MMC2 tW(clkH)  
MMC2 tW(clkL)  
tdc(clk)  
Frequency(1), output clk period  
24  
12  
MHz  
ns  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
X(5)*PO(2)  
Y(6)*PO(2)  
2083.3  
X(5)*PO(2)  
Y(6)*PO(2)  
4166.7  
ns  
ps  
tJ(clk)  
Jitter standard deviation(3), output clk  
200  
200  
ps  
MMC1 Interface (1.8-V IO)  
tR(clk)  
Rise time, output clk  
10  
10  
ns  
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Table 6-113. MMC1 Interface Switching Characteristics—Standard MMC and MMC Identification Modes(7)  
(continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
tF(clk)  
Fall time, output clk  
10  
10  
10  
10  
10  
79  
ns  
ns  
ns  
ns  
tR(data)  
tF(data)  
MMC5 td(CLKOH-CMD)  
Rise time, output data  
Fall time, output data  
10  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
4.1  
4.1  
37.6  
4.3  
4.3  
MMC6 td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](4) transition  
37.6  
79  
ns  
MMC1 Interface (3.0-V IO)  
tR(clk)  
tF(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
10  
10  
10  
10  
10  
10  
79  
ns  
ns  
ns  
ns  
ns  
tR(data)  
10  
tF(data)  
10  
MMC5 td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
4.1  
4.1  
37.6  
4.3  
4.3  
MMC6 td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](4) transition  
37.6  
79  
ns  
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) In mmc1_dat[n:0], n is equal to 3.  
(5) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(7) See Section 4.3.4, Processor Clocks.  
MMC1  
MMC2  
mmc1_clk  
mmc1_cmd  
MMC3  
MMC4  
MMC7  
MMC8  
mmc1_dat[3:0]  
SWPS038-102  
Figure 6-65. MMC1 Interface—Standard MMC and MMC Identification Modes—Data/Command Receive  
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MMC1  
MMC2  
sdmmc1_clk  
MMC5  
MMC5  
sdmmc1_cmd  
MMC6  
MMC6  
sdmmc1_dat[3:0]  
SWPS038-103  
Figure 6-66. MMC1 Interface—Standard MMC and MMC Identification Modes—Data/Command Transmit  
6.6.8.1.5 MMC1 Interface—High-Speed MMC Mode  
Table 6-115 and Table 6-116 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-67 and Figure 6-68).  
Table 6-114. MMC1 Interface Timing Conditions—High-Speed MMC Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
tF  
Input signal rise time  
Input signal fall time  
3
3
ns  
ns  
Output Conditions  
CLOAD  
Output load capacitance(1)  
30  
pF  
(1) The load setting of the IO buffer: SPEEDCTRL = 1.  
Table 6-115. MMC1 Interface Timing Requirements—High-Speed MMC Mode(2) (3) (4) (5)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
MMC1 Interface (1.8-V IO)  
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
5.6  
2.3  
5.6  
2.3  
26.0  
1.9  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
26.0  
1.9  
MMC1 Interface (3.0-V IO)  
MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising  
clock edge  
5.6  
2.3  
5.6  
2.3  
26.0  
1.9  
ns  
ns  
ns  
ns  
MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising  
clock edge  
MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk  
rising clock edge  
MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk  
rising clock edge  
26.0  
1.9  
(1) In mmc1_dat[n:0], n is equal to 3.  
(2) Timing parameters are referred to output clock specified in Table 6-116.  
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-116.  
(4) Corresponding figures showing timing parameters are common with the Standard MMC mode figures.  
(5) See Section 4.3.4, Processor Clocks.  
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UNIT  
Table 6-116. MMC1 Interface Switching Characteristics—High-Speed MMC Mode(4) (8)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
48  
X(6)*PO(2)  
Y(7)*PO(2)  
1041.7  
OPP50  
MIN MAX  
24  
X(6)*PO(2)  
Y(7)*PO(2)  
2083.3  
MMC1  
MMC2  
MMC2  
tc(clk)  
Frequency(1), output clk period  
MHz  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
tJ(clk)  
Typical pulse duration, output clk high  
Typical pulse duration, output clk low  
Duty cycle error, output clk  
ns  
ps  
Jitter standard deviation(3), output clk  
200  
200  
ps  
MMC1 Interface (1.8-V IO)  
tR(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
3
3
3
ns  
ns  
ns  
ns  
ns  
tF(clk)  
tR(data)  
tF(data)  
td(CLKOH-CMD)  
3
3
3
3
MMC5  
MMC6  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.7  
3.7  
14.1  
4.1  
4.1  
34.5  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](5) transition  
14.1  
34.5  
ns  
MMC1 Interface (3.0-V IO)  
tR(clk)  
tF(clk)  
tR(data)  
tF(clk)  
Rise time, output clk  
Fall time, output clk  
Rise time, output data  
Fall time, output data  
3
3
3
3
ns  
ns  
ns  
ns  
ns  
3
3
3
3
MMC5  
MMC6  
td(CLKOH-CMD)  
Delay time, mmc1_clk rising clock edge to mmc1_cmd  
transition  
3.7  
3.7  
14.1  
4.1  
4.1  
34.5  
td(CLKOH-DATx)  
Delay time, mmc1_clk rising clock edge to  
mmc1_dat[n:0](5) transition  
14.1  
34.5  
ns  
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) Corresponding figures showing timing parameters are common with the Standard MMC mode figures.  
(5) In MMC1_dat[n:0], n is equal to 3.  
(6) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(7) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(8) See Section 4.3.4, Processor Clocks.  
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MMC1  
MMC2  
mmc1_clk  
MMC3  
MMC4  
mmc1_cmd  
MMC7  
MMC8  
mmc1_dat[3:0]  
SWPS038-100  
Figure 6-67. MMC1 Interface—High-Speed MMC Mode—Data/Command Receive  
MMC1  
MMC2  
mmc1_clk  
mmc1_cmd  
MMC5  
MMC5  
MMC6  
MMC6  
mmc1_dat[3:0]  
SWPS038-101  
Figure 6-68. MMC1 Interface—High-Speed MMC Mode—Data/Command Transmit  
6.6.8.1.6 MMC2 and MMC3 Interfaces—SDIO Identification Mode  
Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-69 and Figure 6-70).  
Table 6-117. MMC2 and MMC3 Interfaces Timing Conditions—SDIO Identification Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
10  
10  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
5
pF  
(1) Buffer strength configuration: LB0 = 0  
Table 6-118. MMC2 and MMC3 Interfaces Timing Requirements—SDIO Identification Mode(1)(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
MMC2 and MMC3 Interface (1.8-V IO)  
SD3 tsu(CMDV-CLKIH) Setup time, mmcx_cmd valid before  
1198.4  
1249.2  
1198.4  
1249.2  
ns  
ns  
mmcx_clk rising clock edge  
SD4 th(CLKIH-CMDIV)  
Hold time, mmcx_cmd valid after mmcx_clk  
rising clock edge  
(1) See Section 4.3.4, Processor Clocks.  
(2) In mmcx, x is equal to 2 or 3.  
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Table 6-119. MMC2 and MMC3 Interfaces Switching Characteristics—SDIO Identification Mode(4)(7)(7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
Standard SDIO Mode  
SD1 tc(clk)  
Frequency(1), output clock period  
0.4  
0.4  
MHz  
ns  
SD2 tW(clkH)  
Typical pulse duration, output clock high  
X(5)  
*
X(5)  
*
PO(2)  
PO(2)  
SD2 tW(clkL)  
Typical pulse duration, output clock low  
Y(6)  
*
Y(6)  
*
ns  
PO(2)  
PO(2)  
tdc(clk)  
tJ(clk)  
Duty cycle error, output clock  
Jitter standard deviation(3), output clock  
Rise time, output clock  
125  
200  
10  
125  
200  
10  
ns  
ps  
ns  
ns  
ns  
ns  
ns  
tR(clk)  
tF(clk)  
Fall time, output clock  
10  
10  
tR(data)  
Rise time, output data  
10  
10  
tF(data)  
Fall time, output data  
10  
10  
SD5 td(CLKOH-CMD)  
Delay time, mmcx_clk rising clock edge to  
mmcx_cmd transition  
6.3  
2492.7  
6.3  
77.03  
(1) Related to the output mmcx_clk maximum and minimum frequency.  
(2) P = output mmcx_clk period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) Corresponding figures showing timing parameters are common with other interface modes (see SDIO, HS SDIO modes).  
(5) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(7) In mmcx, x is equal to 2 or 3.  
6.6.8.1.7 MMC2 and MMC3 Interfaces—High-Speed SDIO Mode  
Table 6-121 and Table 6-122 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-69 and Figure 6-70).  
Table 6-120. MMC2 and MMC3 Interfaces Timing Conditions—High-Speed SDIO Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
0.18  
0.19  
5.69  
5.70  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
5
pF  
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(1) Buffer strength configuration for MMC2 and MMC3: LB0 = 0.  
Table 6-121. MMC2 and MMC3 Interfaces Timing Requirements—High-Speed SDIO Mode(2)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
HSSD3  
HSSD4  
HSSD7  
HSSD8  
tsu(dV-clkH)  
th(clkH-dV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, mmcx_cmd valid before mmcx_clk rising  
clock edge  
3.4  
1.7  
3.4  
1.7  
23.8  
ns  
ns  
ns  
ns  
Hold time, mmcx_cmd valid after mmcx_clk rising  
clock edge  
Setup time, mmcx_dat[n:0](1) valid before mmcx_clk  
rising clock edge  
Hold time, mmcx_dat[n:0](1) valid after mmcx_clk rising  
clock edge  
1.3  
23.8  
1.3  
(1) In mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3.  
(2) See Section 4.3.4, Processor Clocks.  
Table 6-122. MMC2 and MMC3 Interfaces Switching Characteristics—High-Speed SDIO Mode(2) (5)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
HSSD1  
HSSD2  
HSSD2  
tc(clk)  
Frequency(1), output mmcx_clk period  
Typical pulse duration, output mmcx_clk high  
Typical pulse duration, output mmcx_clk low  
Duty cycle error, output mmcx_clk  
48  
24  
MHz  
ns  
tW(clkH)  
tW(clkL)  
tdc(clk)  
0.5*P(3)  
0.5*P(3)  
0.5*P(3)  
0.5*P(3)  
ns  
–1042  
–65  
1042  
65  
–2083  
–65  
3
2083  
65  
ps  
tJ(clk)  
Jitter standard deviation(4), output mmcx_clk  
ps  
HSSD5  
HSSD6  
td(clkL-doV)  
Delay time, mmcx_clk rising clock edge to mmcx_cmd  
transition  
2.6  
13.8  
34.3  
ns  
td(clkL-doV)  
Delay time, mmcx_clk rising clock edge to  
mmcx_dat[n:0](2) transition  
2.6  
13.8  
3
34.3  
ns  
(1) Related with the output mmcx_clk maximum and minimum frequency.  
(2) In mmcx, x = 2 or 3. In mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3.  
(3) P = output mmcx_clk period in ns.  
(4) The jitter probability density can be approximated by a Gaussian function.  
(5) See Section 4.3.4, Processor Clocks.  
HSSD1  
HSSD2  
HSSD2  
mmcx_clk  
HSSD3  
HSSD4  
mmcx_cmd  
HSSD7  
HSSD8  
mmcx_dat[n:0]  
SWPS038-096  
Figure 6-69. MMC2 and MMC3 Interfaces—High-Speed SDIO Mode—Data/Command Receive(1)  
(1) In mmcx, x = 2 or 3. In mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3.  
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HSSD1  
HSSD2  
HSSD2  
mmcx_clk  
mmcx_cmd  
HSSD5  
HSSD6  
HSSD5  
HSSD6  
mmcx_dat[n:0]  
SWPS038-097  
Figure 6-70. MMC2 and MMC3 Interfaces—High-Speed SDIO Mode—Data/Command Transmit(1)  
(1) In mmcx, x = 2 or 3. In mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3.  
6.6.8.1.8 MMC2 and MMC3 Interfaces—Standard SDIO Mode  
Table 6-124 and Table 6-125 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 5-89 and Figure 5-90).  
Table 6-123. MMC2 and MMC3 Interfaces Timing Conditions—Standard SDIO Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
10  
10  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
5
pF  
(1) Buffer strength configuration: SPEEDCTRL = 1  
Table 6-124. MMC2 and MMC3 Interfaces Timing Requirements—Standard SDIO Mode(2)(3)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
MMC2 and MMC3 Interface (1.8-V IO)  
SD3  
SD4  
SD7  
SD8  
tsu(CMDV-CLKIH)  
th(CLKIH-CMDIV)  
tsu(DATxV-CLKIH)  
th(CLKIH-DATxIV)  
Setup time, mmcx_cmd valid before  
mmcx_clk rising clock edge  
3.3  
18.1  
3.3  
21.9  
36.7  
21.9  
36.7  
ns  
ns  
ns  
ns  
Hold time, mmcx_cmd valid after mmcx_clk  
rising clock edge  
Setup time, mmcx_dat[n:0](1) valid before  
mmcx_clk rising clock edge  
Hold time, mmcx_dat[n:0](1) valid after  
mmcx_clk rising clock edge  
18.1  
(1) In mmcx_dat[n:0], n is equal to 3 for MMC2 and 7 for MMC3.  
(2) See Section 4.3.4, Processor Clocks.  
(3) In mmcx, x is equal to 2 or 3.  
Table 6-125. MMC2 and MMC3 Interfaces Switching Characteristics—Standard SDIO Mode(6)(7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
Standard SDIO Mode  
SD1  
SD2  
tc(clk)  
Frequency(1), output clock period  
24  
12  
MHz  
ns  
tW(clkH)  
Typical pulse duration, output clock high  
X(4)  
*
X(4)  
*
PO(2)  
PO(2)  
SD2  
tW(clkL)  
tdc(clk)  
Typical pulse duration, output clock low  
Duty cycle error, output clock  
Y(5)  
*
Y(5)  
*
ns  
ps  
PO(2)  
PO(2)  
2083.33  
4166.67  
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Table 6-125. MMC2 and MMC3 Interfaces Switching Characteristics—Standard SDIO Mode(6)(7) (continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
tJ(clk)  
Jitter standard deviation(3), output clock  
Rise time, output clock  
200  
10  
200  
10  
ps  
ns  
ns  
ns  
ns  
ns  
tR(clk)  
tF(clk)  
Fall time, output clock  
10  
10  
tR(data)  
tF(data)  
td(CLKOH-CMD)  
Rise time, output data  
10  
10  
Fall time, output data  
10  
10  
SD5  
SD6  
Delay time, mmcx_clk rising clock edge to  
mmcx_cmd transition  
6.13  
6.13  
35.53  
6.3  
6.3  
77.03  
td(CLKOH-DATx)  
Delay time, mmcx_clk rising clock edge to  
mmcx_dat[n:0](6) transition  
35.53  
77.03  
ns  
(1) Related to the output mmcx_clk maximum and minimum frequency.  
(2) P = output mmcx_clk period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) The X parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
X
0.5  
(trunk[CLKD/2]+1)/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(5) The Y parameter is defined as follows:  
CLKD  
1 or Even  
Odd  
Y
0.5  
(trunk[CLKD/2])/CLKD  
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual  
(literature number SPRUGN4).  
(6) In mmcx, x is equal to 2 or 3. In mmcx_dat[n :0] is equal to 3 for mmc2 and 7 for mmc3.  
(7) See Section 4.3.4, Processor Clocks.  
SD1  
SD2  
mmc1_clk  
mmc1_cmd  
SD3  
SD4  
SD7  
SD8  
mmc1_dat[n:0]  
SWPS038-098  
Figure 6-71. MMC2 and MMC3 Interfaces—Standard SDIO Mode—Data/Command Receive(1)  
(1) In mmcx, x is equal to 2 or 3. In mmcx_dat[n:0] is equal to 3 for MMC2 and 7 for MMC3.  
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SD1  
SD2  
mmc1_clk  
mmc1_cmd  
SD5  
SD6  
SD5  
SD6  
mmc1_dat[n:0]  
SWPS038-099  
Figure 6-72. MMC2 and MMC3 Interfaces—Standard SDIO Mode—Data/Command Transmit(1)  
(1) In mmcx, x is equal to 2 or 3. In mmcx_dat[n:0] is equal to 3 for MMC2 and 7 for MMC3.  
6.6.8.1.9 MMC2 and MMC3 Interfaces—Embedded Media Interface (eMMC)—High-Speed JC64 Mode  
Table 6-127 and Table 6-128 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-73 through Figure 6-74).  
Table 6-126. MMC2 and MMC3 Interfaces Timing Conditions—High-Speed JC64 Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Input Conditions  
tR  
Input signal rise time  
0.38  
0.39  
3.82  
3.68  
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance(1)  
14  
pF  
(1) Buffer strength configuration for MMC3: LB0 = 1.  
Table 6-127. MMC2 and MMC3 Interfaces Timing Requirements—High-Speed JC64 Mode(1)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
UNIT  
MIN  
MMC3 tsu(cmdV-clkH)  
MMC4 th(clkH-cmdIV)  
MMC7 tsu(dV-clkH)  
MMC8 th(clkH-dIV)  
Setup time, input command mmcx_cmd valid before  
output clock mmcx_clk rising edge  
5.1  
1.3  
5.1  
1.3  
25.5  
ns  
ns  
ns  
ns  
Hold time, input command mmcx_cmd valid after  
output clock mmcx_clk rising edge  
0.9  
25.5  
0.9  
Setup time, input data mmcx_dat[n:0] valid before  
output clock mmcx_clk rising edge  
Hold time, input data mmcx_dat[n:0] valid after output  
clock mmcx_clk rising edge  
(1) In mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7.  
(2) In mmx_cmd, x is equal to 2 or 3.  
(3) In mmx_clk, x is equal to 2 or 3.  
Table 6-128. MMC2 and MMC3 Interfaces Switching Characteristics—High-Speed JC64 Mode(5) (6)(7)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
MMC1 1/tc(clk)  
MMC2 tW(clkH)  
MMC2 tW(clkL)  
tdc(clk)  
Frequency(1), output mmcx_clk period  
Typical pulse duration, output mmcx_clk high  
Typical pulse duration, output mmcx_clk low  
Duty cycle error, output mmcx_clk  
48  
24  
MHz  
ns  
0.5*P(2)  
0.5*P(2)  
0.5*P(2)  
0.5*P(2)  
ns  
–1042  
–65  
1042  
65  
–2083  
–65  
2083  
65  
ps  
tJ(clk)  
Jitter standard deviation(3), output mmcx_clk  
ps  
tR(clk)  
Rising time, output mmcx_clk  
2263  
2136  
2263  
2136  
ps  
tF(clk)  
Falling time, output mmcx_clk  
ps  
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Table 6-128. MMC2 and MMC3 Interfaces Switching Characteristics—High-Speed JC64 Mode(5)  
(6)(7)  
(continued)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
MMC5 td(clkL-doV)  
Delay time, mmcx_clk rising clock edge to mmcx_cmd  
transition  
3.6  
16.8  
4
37.2  
ns  
tR(do)  
tF(do)  
Rising time, output mmcx_cmd  
Falling time, output mmcx_cmd  
2263  
2136  
16.8  
2263  
2136  
37.2  
ps  
ps  
ns  
MMC6 td(clkL-doV)  
Delay time, mmcx_clk rising clock edge to mmcx_daty  
transition  
3.6  
4
tR(do)  
tF(do)  
Rising time, output mmcx_dat[n:0](4)  
Falling time, output mmcx_dat[n:0](4)  
2263  
2136  
2263  
2136  
ps  
ps  
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.  
(2) PO = output clock period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) In mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7.  
(5) See Section 4.3.4, Processor Clocks.  
(6) In mmx_cmd, x is equal to 2 or 3.  
(7) In mmx_clk, x is equal to 2 or 3.  
MMC1  
MMC2  
MMC2  
mmcx_clk  
MMC5  
MMC5  
mmcx_cmd  
MMC6  
MMC6  
mmcx_dat[n:0]  
SWPS038-104  
Figure 6-73. MMC2 and MMC3 Interfaces—High-Speed JC64 Transmiter Mode(1)(2)(3)  
(1) In mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7.  
(2) In mmx_cmd, x is equal to 2 or 3.  
(3) In mmx_clk, x is equal to 2 or 3.  
MMC1  
MMC2  
MMC2  
mmcx_clk  
mmcx_cmd  
MMC3  
MMC4  
MMC7  
MMC8  
mmcx_dat[n:0]  
SWPS038-105  
Figure 6-74. MMC2 and MMC3 Interfaces—High-Speed JC64 Receiver Mode(1)(2)(3)  
(1) In mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7.  
(2) In mmx_cmd, x is equal to 2 or 3.  
(3) In mmx_clk, x is equal to 2 or 3.  
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6.6.9 Test Interfaces  
6.6.9.1 Embedded Trace Macro Interface (ETM)  
Table 6-130 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-75).  
Table 6-129. ETM Timing Conditions—Transmit Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
MIN  
MAX  
Output Condition  
CLOAD  
Output load capacitance(1)  
10  
pF  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-130. ETM Switching Characteristics—Transmit Mode(4)  
NO.  
PARAMETER  
OPP100  
OPP50  
MAX  
UNIT  
MIN  
MAX  
MIN  
TPIU1 1 / tc(clk)  
TPIU2 tw(clkH)  
TPIU3 tw(clkL)  
tdc(clk)  
Frequency(3), output clock etk_clk  
Pulse duration, output clock etk_clk high  
Pulse duration, output clock etk_clk low  
Duty cycle error, output clock etk_clk  
Jitter standard deviation(2), output clock etk_clk  
Rise time, output clock etk_clk  
166  
166  
MHz  
ns  
0.5P(1)  
0.5P(1)  
0.5P(1)  
0.5P(1)  
ns  
–301  
301  
65  
–301  
301  
65  
ps  
tJ(clk)  
ps  
tR(clk)  
1.2  
1.2  
1.2  
1.2  
ns  
tF(clk)  
Fall time, output clock etk_clk  
ns  
TPIU4 td(clk-ctl)  
Delay time, output clock etk_clk low/high to output  
control etk_ctl transition  
0.839  
0.839  
1.2  
0.839  
0.839  
1.2  
ns  
TPIU5 td(clkH-d)  
tR(d/ctl)  
Delay time, output clock etk_clk low/high to output  
data etk_d[15:0] transition  
ns  
ns  
ns  
Rise time, output data etk_d[15:0] and output control  
etk_ctl  
tF(d/ctl)  
Fall time, output data etk_d[15:0] and output control  
etk_ctl  
1.2  
1.2  
(1) P = etk_clk period in ns  
(2) The jitter probability density can be approximated by a Gaussian function.  
(3) Related with the etm_clk maximum frequency.  
(4) See Section 4.3.4, Processor Clocks.  
TPIU1  
TPIU2  
TPIU3  
etk_clk  
TPIU4  
TPIU4  
etk_ctl  
TPIU5  
TPIU5  
etk_d[15:0]  
SWPS038-106  
Figure 6-75. ETM—Transmit Mode  
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6.6.9.2 System Debug Trace Interface (SDTI)  
The System Debug Trace Interface (SDTI) module provides real-time software tracing functionality to the  
device. The trace interface has four trace data pins and a trace clock pin.  
This interface is a dual-edge interface:  
•
•
The data are available on rising and falling edge of sdti_clk.  
But can be also configured in single-edge mode where data are available on the falling edge of  
sdti_clk.  
Serial interface operates in clock stop regime: serial clock is not free-running; when there is no trace data,  
there is no trace clock.  
6.6.9.2.1 SDTI—Dual-Edge Mode  
Table 6-132 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-76).  
Table 6-131. SDTI Timing Conditions—Dual-Edge Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Output Condition  
CLOAD  
Output load capacitance(1)  
25  
pF  
(1) Buffer strength configuration: LB0 = 1.  
Table 6-132. SDTI Switching Characteristics—Dual-Edge Mode(2)  
NO.  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
MAX  
MIN  
MAX  
SD1  
SD2  
1 / tc(clk)  
tw(clk)  
Frequency, output clock sdti_clk  
34.5  
0.5P(1)  
1.2  
34.5  
0.5P(1)  
1.2  
MHz  
ns  
Pulse duration, output clock sdti_clk high or low  
0.5P(1)  
1.2  
–
+
0.5P(1)  
1.2  
–
+
SD3  
td(clk-txd)  
Delay time, output clock sdti_clk  
transition to output data  
sdti_txd[3:0] transition  
Multiplexing mode on  
etk pins  
2.3  
10.9  
2.3  
10.9  
ns  
Multiplexing mode on  
jtag_emu pins  
2.3  
13.9  
2.3  
13.9  
(1) P = sdti_clk clock period in ns  
(2) See Section 4.3.4, Processor Clocks.  
SD1  
SD2  
sdti_clk  
SD3  
Header  
SD3  
Ad[7:4]  
sdti_txd[3:0]  
Header  
Ad[3:0] Da[15:12] Da[11:8]  
Da[7:4]  
Da[3:0]  
SWPS038-107  
Figure 6-76. SDTI—Dual-Edge Mode  
6.6.9.2.2 SDTI—Single-Edge Mode  
Table 6-134 assumes testing over the recommended operating conditions and electrical characteristic  
conditions below (see Figure 6-77).  
Table 6-133. SDTI Timing Conditions—Single-Edge Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Output Condition  
CLOAD  
Output load capacitance(1)  
25  
pF  
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(1) Buffer strength configuration: LB0 = 1.  
256  
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Table 6-134. SDTI Switching Characteristics—Single-Edge Mode(2)  
PARAMETER  
OPP100  
OPP50  
UNIT  
MIN  
MAX  
MIN  
MAX  
SD1  
SD2  
1 / tc(clk)  
tw(clk)  
Frequency, output clock sdti_clk  
34.5  
0.5P(1)  
1.2  
34.5  
0.5P(1)  
1.2  
MHz  
ns  
Pulse duration, output clock sdti_clk high or low  
0.5P(1)  
1.2  
–
+
0.5P(1)  
1.2  
–
+
SD3  
td(clk-txd)  
Delay time, output clock sdti_clk  
transition to output data  
sdti_txd[3:0] transition  
Multiplexing mode on  
etk pins  
2.3  
26.5  
2.3  
26.5  
ns  
Multiplexing mode on  
jtag_emu pins  
2.3  
33.2  
2.3  
33.2  
(1) P = sdti_clk clock period in ns  
(2) See Section 4.3.4, Processor Clocks.  
SD1  
SD2  
sdti_clk  
SD3  
Header  
SD3  
Ad[7:4]  
sdti_txd[3:0]  
Header  
Ad[3:0]  
Da[15:12]  
Da[11:8]  
Da[7:4]  
Da[3:0]  
SWPS038-108  
Figure 6-77. SDTI—Single-Edge Mode  
6.6.9.3 JTAG Interface (JTAG)  
The JTAG TAP controller handles standard IEEE JTAG interfaces. The following section defines the  
timing requirements for several tools used to test the device as:  
•
•
Free-running clock tool, like XDS560 and XDS510 tools  
Adaptive clock tool, like RealView® ICE tool and LauterbachTM tool  
6.6.9.3.1 JTAG—Free-Running Clock Mode  
Table 6-136 and Table 6-137 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-78).  
Table 6-135. JTAG Timing Conditions—Free-Running Clock Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
5
5
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-136. JTAG Timing Requirements—Free-Running Clock Mode(5) (6)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
JT4  
JT5  
JT6  
1 / tc(tck)  
tw(tckL)  
tw(tckH)  
tdc(tck)  
Frequency(1), input clock jtag_tck  
Pulse duration, input clock jtag_tck low  
Pulse duration, input clock jtag_tck high  
Duty cycle error, input clock jtag_tck  
Cycle jitter(3), input clock jtag_tck  
50  
50  
MHz  
ns  
0.5P(2)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
ns  
–1250  
–1250  
1.6  
1250  
1250  
–1667  
–1667  
1.6  
1667  
1667  
ps  
tJ(tck)  
ps  
JT7  
tsu(tdiV-rtckH)  
Setup time, input data jtag_tdi valid before output  
clock jtag_rtck high  
ns  
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UNIT  
Table 6-136. JTAG Timing Requirements—Free-Running Clock Mode(5) (6) (continued)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MAX  
MIN  
JT8  
JT9  
th(tdiV-rtckH)  
Hold time, input data jtag_tdi valid after output clock  
jtag_rtck high  
0.7  
1.0  
ns  
ns  
ns  
ns  
ns  
tsu(tmsV-rtckH)  
th(tmsV-rtckH)  
tsu(emuxV-rtckH)  
th(emuxV-rtckH)  
Setup time, input mode select jtag_tms_tmsc valid  
before output clock jtag_rtck high  
1.6  
1.6  
1.0  
JT10  
JT12  
JT13  
Hold time, input mode select jtag_tms_tmsc valid after  
output clock jtag_rtck high  
Setup time, input emulation jtag_emux(4) valid before  
output clock jtag_rtck high  
Hold time, input emulation jtag_emux(4) valid after  
output clock jtag_rtck high  
0.7  
14.4  
2.0  
19.6  
2.7  
(1) Related with the input maximum frequency supported by the JTAG module.  
(2) P = input clock jtag _tck period in ns  
(3) Maximum cycle jitter supported by input clock jtag _tck.  
(4) In jtag_emux, x is equal to 0 or 1.  
(5) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.  
(6) See Section 4.3.4, Processor Clocks.  
Table 6-137. JTAG Switching Characteristics—Free-Running Clock Mode(5)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
UNIT  
MIN  
MAX  
JT1  
JT2  
JT3  
1 / tc(rtck)  
tw(rtckL)  
tw(rtckH)  
tdc(rtck)  
Frequency(1), output clock jtag_rtck  
Pulse duration, output clock jtag_rtck low  
Pulse duration, output clock jtag_rtck high  
Duty cycle error, output clock jtag_rtck  
Jitter standard deviation(3), output clock jtag_rtck  
Rise time, output clock jtag_rtck  
50  
50  
MHz  
ns  
0.5P(2)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
ns  
–1250  
1250  
33.3  
0
–1667  
1667  
33.3  
0
ps  
tJ(rtck)  
ps  
tR(rtck)  
ns  
tF(rtck)  
Fall time, output clock jtag_rtck  
0
0
ns  
JT11  
JT14  
td(rtckL-tdoV)  
Delay time, output clock jtag_rtck low to output data  
jtag_tdo valid  
–5.8  
2.7  
5.8  
–7.9  
2.7  
7.9  
ns  
tR(tdo)  
Rise time, output data jtag_tdo  
Fall time, output data jtag_tdo  
0
0
0
0
ns  
ns  
ns  
tF(tdo)  
td(rtckH-emuxV)  
Delay time, output clock jtag_rtck high to output  
emulation ,jtag_emux(4) valid  
15.1  
20.4  
(1) Related with the jtag_rtck maximum frequency.  
(2) P = output clock jtag _rtck period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) In jtag_emux, x is equal to 0 or 1.  
(5) See Section 4.3.4, Processor Clocks.  
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JT4  
JT1  
JT5  
JT2  
JT6  
JT3  
jtag_tck  
jtag_rtck  
jtag_tdi  
JT7  
JT9  
JT8  
JT10  
JT13  
jtag_tms_tmsc  
JT12  
jtag_emux(IN)  
JT11  
jtag_tdo  
JT14  
jtag_emux(OUT)  
(1) In jtag_emux, x is equal to 0 or 1.  
SWPS038-109  
Figure 6-78. JTAG—Free-Running Clock Mode  
6.6.9.3.2 JTAG—Adaptative Clock Mode  
Table 6-139 and Table 6-140 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 6-79).  
Table 6-138. JTAG Timing Conditions—Adaptative Clock Mode  
TIMING CONDITION PARAMETER  
VALUE  
UNIT  
Input Conditions  
tR  
Input signal rise time  
5
5
ns  
ns  
tF  
Input signal fall time  
Output Condition  
CLOAD  
Output load capacitance  
30  
pF  
Table 6-139. JTAG Timing Requirements—Adaptative Clock Mode(4) (5)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
JA4  
JA5  
JA6  
1 / tc(tck)  
tw(tckL)  
tw(tckH)  
tdc(lclk)  
Frequency(1), input clock jtag_tck  
Pulse duration, input clock jtag_tck low  
Pulse duration, input clock jtag_tck high  
Duty cycle error, input clock jtag_tck  
Cycle jitter(3), input clock jtag_tck  
50  
50  
MHz  
ns  
0.5P(2)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
ns  
–2500  
–1500  
13.8  
2500  
1500  
–2500  
–1500  
13.8  
2500  
1500  
ps  
tJ(lclk)  
ps  
JA7  
JA8  
tsu(tdiV-tckH)  
Setup time, input data jtag_tdi valid before input clock  
jtag_tck high  
ns  
th(tdiV-tckH)  
tsu(tmsV-tckH)  
th(tmsV-tckH)  
Hold time, input data jtag_tdi valid after input clock  
jtag_tck high  
13.8  
13.8  
13.8  
13.8  
13.8  
13.8  
ns  
ns  
ns  
JA9  
Setup time, input mode select jtag_tms_tmsc valid  
before input clock jtag_tck high  
JA10  
Hold time, input mode select jtag_tms_tmsc valid after  
input clock jtag_tck high  
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(1) Related with the input maximum frequency supported by the JTAG module  
(2) P = input clock jtag _tck period in ns  
(3) Maximum cycle jitter supported by input clock jtag _tck.  
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.  
(5) See Section 4.3.4, Processor Clocks.  
Table 6-140. JTAG Switching Characteristics—Adaptative Clock Mode(4)  
NO.  
PARAMETER  
OPP100  
MIN MAX  
OPP50  
MIN MAX  
UNIT  
JA1  
JA2  
JA3  
1 / tc(rtck)  
tw(rtckL)  
tw(rtckH)  
tdc(rtck)  
Frequency(1), output clock jtag_rtck  
Pulse duration, output clock jtag_rtck low  
Pulse duration, output clock jtag_rtck high  
Duty cycle error, output clock jtag_rtck  
Jitter standard deviation(3), output clock jtag_rtck  
Rise time, output clock jtag_rtck  
50  
50  
MHz  
ns  
0.5P(2)  
0.5P(2)  
0.5P(2)  
0.5P(2)  
ns  
–2500  
2500  
33.3  
0
–2500  
2500  
33.3  
0
ps  
tJ(rtck)  
ps  
tR(rtck)  
ns  
tF(rtck)  
Fall time, output clock jtag_rtck  
0
0
ns  
JA11  
td(rtckL-tdoV)  
Delay time, output clock jtag_rtck low to output data  
jtag_tdo valid  
–14.6  
14.6  
–14.6  
14.6  
ns  
(1) Related with the jtag _rtck maximum frequency programmable.  
(2) P = output clock jtag _rtck period in ns  
(3) The jitter probability density can be approximated by a Gaussian function.  
(4) See Section 4.3.4, Processor Clocks.  
JA4  
JA5  
JA6  
jtag_tck  
jtag_tdi  
JA7  
JA9  
JA8  
JA10  
JA1  
jtag_tms  
JA2  
JA3  
jtag_rtck  
jtag_tdo  
JA11  
SWPS038-110  
Figure 6-79. JTAG—Adaptative Clock Mode  
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7 Package Characteristics  
7.1 Package Thermal Characteristics  
Table 7-1 and Table 7-2 provide the thermal resistance characteristics for the packages used on this  
device.  
Note: This table provides simulation data and may not represent actual use-case values.  
Table 7-1. Thermal Resistance Characteristics 800MHz ARM Operation-4Gb DDR + Flash  
PACKAGE  
CBP Package  
CBC Package  
CUS Package  
Power (W)(5)  
1.42  
qJA(°C/W)(2)  
20.06  
qJB(°C/W)(3)  
6.44  
qJC(°C/W)(4)  
BOARD TYPE  
2S2P(1)  
(6)  
(6)  
1.42  
19.97  
7.76  
2S2P(1)  
2S2P(1)  
1.05  
24.75  
11.06  
7.06  
(1) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Array Surface Mount Package Thermal  
Measurements).  
(2) qJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W  
(3) qJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W  
(4) qJC (Theta-JC) = Thermal Resistance Junction-to-Board, °C/W  
(5) These power numbers are based on simulation results for DM37x. Power numbers for CBP and CBC packages include the DM37x  
device and POP memory. CUS package is DM37x only.  
(6) Not applicable since these packages have memory package mounted on top.  
Table 7-2. Thermal Resistance Characteristics 1GHz ARM Operation-8Gb DDR  
PACKAGE  
CBP Package  
CBC Package  
CUS Package  
Power (W)(5)  
2.06  
qJA(°C/W)(2)  
19.51  
qJB(°C/W)(3)  
6.19  
qJC(°C/W)(4)  
BOARD TYPE  
2S2P(1)  
(6)  
(6)  
2.06  
20.11  
8.01  
2S2P(1)  
2S2P(1)  
1.4  
24.75  
11.06  
7.06  
(1) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Array Surface Mount Package Thermal  
Measurements).  
(2) qJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W  
(3) qJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W  
(4) qJC (Theta-JC) = Thermal Resistance Junction-to-Board, °C/W  
(5) These power numbers are based on simulation results for DM37x. Power numbers for CBP and CBC packages include the DM37x  
device and POP memory. CUS package is DM37x only.  
(6) Not applicable since these packages have memory package mounted on top.  
7.2 Device Support  
7.2.1 Device and Development-Support Tool Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
DM37x processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix).  
Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and  
TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes  
(TMDX) through fully qualified production devices/tools (TMDS).  
Device development evolutionary flow:  
X
Experimental device that is not necessarily representative of the final devices electrical  
specifications and may not use production assembly flow. (TMX definition)  
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet  
final electrical specifications. (TMP definition)  
null  
Production version of the silicon die that is fully qualified. (TMS definition)  
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Support tool development evolutionary flow:  
TMDX  
TMDS  
Development support product that has not yet completed Texas Instruments internal  
qualification testing.  
Fully qualified development support product.  
TMX and TMP devices and TMDX development-support tools are shipped against the following  
disclaimer:  
Developmental product is intended for internal evaluation purposes.  
Production devices and TMDS development-support tools have been characterized fully, and the quality  
and reliability of the device have been demonstrated fully. TIs standard warranty applies.  
Predictions show that prototype devices (X or P), have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system  
because their expected end-use failure rate still is undefined. Only qualified production devices are to be  
used.  
For additional description of the device nomenclature markings, see the Processor Silicon Errata.  
X
DM3730 ( ) CBP  
(
)
blank = 800 MHz Cortex-A8  
100 = 1GHz Cortex-A8  
(
)
( )  
PREFIX  
blank = tray  
= tape and reel  
X
P
= Experimental Device  
= Prototype Device  
R
blank = Production Device  
blank = commercial temperature  
= extended temperature  
A
PACKAGE TYPE  
DEVICE  
CBP = 515-pin sPBGA  
CBC = 515-pin sPBGA  
CUS = 423-pin sPBGA  
SILICON REVISION  
Figure 7-1. Device Nomenclature  
262  
Package Characteristics  
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7.3 Mechanical Data  
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PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
Samples Not Available  
Samples Not Available  
Purchase Samples  
Purchase Samples  
Purchase Samples  
DM3725CBC100  
DM3725CBP100  
XDM3730ACUS  
XDM3730CBC  
XDM3730CUS  
PREVIEW POP-FCBGA  
PREVIEW POP-FCBGA  
CBC  
515  
515  
423  
515  
423  
119  
168  
1
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
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Call TI  
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CBP  
CUS  
CBC  
CUS  
ACTIVE  
ACTIVE  
ACTIVE  
FCBGA  
POP-FCBGA  
FCBGA  
1
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
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DM383AAAR11

 DM383 DaVinc Digital Media Processor
TI

DM383AAAR21

 DaVinci 数字媒体处理器 | AAR | 609
TI

DM383AAAR21F

 DaVinci 数字媒体处理器 | AAR | 609
TI

DM383_13

 DM383 DaVinc Digital Media Processor
TI

DM385

 DM385 and DM388 DaVinci™ Digital Media Processor
TI

DM385AAAR01

 DM385 and DM388 DaVinci™ Digital Media Processor
TI

DM385AAAR01F

 DM385 and DM388 DaVinci™ Digital Media Processor
TI

DM385AAAR11

 DM385 and DM388 DaVinci™ Digital Media Processor
TI

DM385AAAR11F

 DM385 and DM388 DaVinci™ Digital Media Processor
TI
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