DP83848CVV/NOPB_技术文档

May 2008

DP83848C PHYTER^®- Commercial Temperature

Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

General Description

Features

The DP83848C is a robust fully featured 10/100 single

port Physical Layer device offering low power con-

sumption, including several intelligent power down

states. These low power modes increase overall prod-

uct reliability due to decreased power dissipation. Sup-

porting multiple intelligent power modes allows the

application to use the absolute minimum amount of

power needed for operation.

•

Low-power 3.3V, 0.18µm CMOS technology

Low power consumption < 270mW Typical

3.3V MAC Interface

Auto-MDIX for 10/100 Mb/s

Energy Detection Mode

25 MHz clock out

SNI Interface (configurable)

The DP83848C includes a 25MHz clock out. This

means that the application can be designed with a

minimum of external parts, which in turn results in the

lowest possible total cost of the solution.

RMII Rev. 1.2 Interface (configurable)

MII Serial Management Interface (MDC and MDIO)

IEEE 802.3u MII

The DP83848C easily interfaces to twisted pair media

via an external transformer. Both MII and RMII are

supported ensuring ease and flexibility of design.

IEEE 802.3u Auto-Negotiation and Parallel Detection

IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

IEEE 802.3u PCS, 100BASE-TX transceivers and filters

The DP83848C features integrated sublayers to sup-

port both 10BASE-T and 100BASE-TX Ethernet proto-

cols, which ensures compatibility and interoperability

with all other standards based Ethernet solutions.

Integrated ANSI X3.263 compliant TP-PMD physical sub-

layer with adaptive equalization and Baseline Wander com-

pensation

•

Error-free Operation up to 137 meters

The DP83848C is offered in a small form factor (48 pin

LQFP) so that a minimum of board space is needed.

Programmable LED support Link, 10 /100 Mb/s Mode, Activ-

ity, and Collision Detect

Applications

•

Single register access for complete PHY status

10/100 Mb/s packet BIST (Built in Self Test)

48-pin LQFP package (7mm) x (7mm)

•

High End Peripheral Devices

Industrial Controls and Factory Automation

General Embedded Applications

System Diagram

10BASE-T

or

DP83848C

MPU/CPU

MII/RMII/SNI

100BASE-TX

10/100 Mb/s

25 MHz

Clock

Source

Status

LEDs

Typical Application

®

PHYTER is a registered trademark of National Semiconductor.

www.national.com

1

MII/RMII/SNI

SERIAL

MANAGEMENT

MII/RMII/SNI INTERFACES

RX_CLK

TX_DATA

TX_CLK

RX_DATA

MII

Registers

10BASE-T &

100BASE-TX

Auto-Negotiation

State Machine

Transmit

Block

Receive

Block

Clock

Generation

ADC

DAC

Auto-MDIX

LED

Drivers

TD± RD±

LEDS

REFERENCE CLOCK

Figure 1. DP83848C Functional Block Diagram

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2

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.5 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.6 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.7 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.8 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.9 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.10 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.6 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Reduced MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.3 10 Mb Serial Network Interface (SNI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.4 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.4.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3

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4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

5.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.3 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.4 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.5 Power Down/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.5.1 Power Down Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.2 Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.6 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 47

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 48

7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

7.2.1 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2.2 MII Interrupt Control Register (MICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.2.3 MII Interrupt Status and Misc. Control Register (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.2.4 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.2.5 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.2.6 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.2.7 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.2.8 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.2.9 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.2.10 10Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2.11 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.2.12 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.6 100BASE-TX Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2.7 100BASE-TX Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2.9 100BASE-TX Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.2.10 100BASE-TX Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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4

8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.2.28 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.2.29 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.2.30 100 Mb/s X1 to TX_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5

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List of Figures

Figure 1. DP83848C Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 28

Figure 9. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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6

List of Tables

Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 5. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 5. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 6. 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 7. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 8. 50 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 9. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 10. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 12. Basic Mode Control Register (BMCR), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 13. Basic Mode Status Register (BMSR), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 16. Negotiation Advertisement Register (ANAR), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 . . . . . . . .46

Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 . . . . . . . . .48

Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 20. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 . . . . . . . . . . . . . . . . . . .49

Table 21. PHY Status Register (PHYSTS), address 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 22. MII Interrupt Control Register (MICR), address 0x11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 23. MII Interrupt Status and Misc. Control Register (MISR), address 0x12 . . . . . . . . . . . . . . . . . . . . . .53

Table 24. False Carrier Sense Counter Register (FCSCR), address 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 25. Receiver Error Counter Register (RECR), address 0x15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 . . . . . . . . . . . . . . . . . . . .55

Table 27. RMII and Bypass Register (RBR), addresses 0x17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 28. LED Direct Control Register (LEDCR), address 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 29. PHY Control Register (PHYCR), address 0x19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 32. Energy Detect Control (EDCR), address 0x1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7

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Pin Layout

37

24

23

RBIAS

PFBIN2

PFBOUT

AVDD33

RESERVED

AGND

RX_CLK

38

39

40

41

RX_DV/MII_MODE

CRS/CRS_DV/LED_CFG

RX_ER/MDIX_EN

COL/PHYAD0

22

21

20

19

42

43

44

45

46

47

48

DP83848C

PFBIN1

TD +

RXD_0/PHYAD1

RXD_1/PHYAD2

RXD_2/PHYAD3

RXD_3/PHYAD4

IOGND

18

17

16

15

14

13

TD -

AGND

RD +

RD -

IOVDD33

o

Top View

NS Package Number VBH48A

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8

1.0 Pin Descriptions

The DP83848C pins are classified into the following inter- All DP83848C signal pins are I/O cells regardless of the

face categories (each interface is described in the sections particular use. The definitions below define the functionality

that follow):

of the I/O cells for each pin.

— Serial Management Interface

— MAC Data Interface

— Clock Interface

Type: I

Input

Type: O

Type: I/O

Type OD

Output

Input/Output

Open Drain

— LED Interface

— Reset and Power Down

— Strap Options

Type: PD,PU Internal Pulldown/Pullup

Type: S Strapping Pin (All strap pins have weak in-

ternal pull-ups or pull-downs. If the default

strap value is needed to be changed then an

external 2.2 kΩ resistor should be used.

Please see Section 1.6 for details.)

— 10/100 Mb/s PMD Interface

— Special Connect Pins

— Power and Ground pins

Note: Strapping pin option. Please see Section 1.6 for strap

definitions.

1.1 Serial Management Interface

Signal Name

Type

Pin #

Description

MDC

I

31

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be

asynchronous to transmit and receive clocks. The maximum clock

rate is 25 MHz with no minimum clock rate.

MDIO

I/O

30

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management

entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

1.2 MAC Data Interface

Signal Name

Type

Pin #

Description

TX_CLK

O

1

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100

Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz

reference clock.

Unused in RMII mode. The device uses the X1 reference clock in-

put as the 50 MHz reference for both transmit and receive.

SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb

SNI mode. The MAC should source TX_EN and TXD_0 using this

clock.

TX_EN

I, PD

2

MII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data on TXD_0.

TXD_0

TXD_1

TXD_2

TXD_3

I

3

4

5

6

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],

that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s

mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],

that accept data synchronous to the 50 MHz reference clock.

S, I, PD

SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that

accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI

mode).

9

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Signal Name

RX_CLK

Type

Pin #

Description

O

38

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive

clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

Unused in RMII mode. The device uses the X1 reference clock in-

put as the 50 MHz reference for both transmit and receive.

SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive

clocks for 10 Mb/s SNI mode.

RX_DV

RX_ER

S, O, PD

S, O, PU

39

41

MII RECEIVE DATA VALID: Asserted high to indicate that valid

data is present on the corresponding RXD[3:0]. MII mode by de-

fault with internal pulldown.

RMII Synchronous Receive Data Valid: This signal provides the

RMII Receive Data Valid indication independent of Carrier Sense.

This pin is not used in SNI mode.

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK

to indicate that an invalid symbol has been detected within a re-

ceived packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Assert high synchronously to X1 when-

ever it detects a media error and RXDV is asserted in 100 Mb/s

mode.

This pin is not required to be used by a MAC, in either MII or RMII

mode, since the Phy is required to corrupt data on a receive error.

This pin is not used in SNI mode.

RXD_0

RXD_1

RXD_2

RXD_3

S, O, PD

S, O, PU

43

44

45

46

MII RECEIVE DATA: Nibble wide receive data signals driven syn-

chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz

for 10 Mb/s mode). RXD[3:0] signals contain valid data when

RX_DV is asserted.

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driv-

en synchronously to the X1 clock, 50 MHz.

SNI RECEIVE DATA: Receive data signal, RXD_0, driven syn-

chronously to the RX_CLK. RXD_0 contains valid data when CRS

is asserted. RXD[3:1] are not used in this mode.

CRS/CRS_DV

40

MII CARRIER SENSE: Asserted high to indicate the receive me-

dium is non-idle.

RMII CARRIER SENSE/RECEIVE DATA VALID: This signal

combines the RMII Carrier and Receive Data Valid indications.

For a detailed description of this signal, see the RMII Specifica-

tion.

SNI CARRIER SENSE: Asserted high to indicate the receive me-

dium is non-idle. It is used to frame valid receive data on the

RXD_0 signal.

COL

42

MII COLLISION DETECT: Asserted high to indicate detection of

a collision condition (simultaneous transmit and receive activity)

in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this

pin is also asserted for a duration of approximately 1µs at the end

of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-

nal is always logic 0. There is no heartbeat function during 10

Mb/s full duplex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL

signal is required. The MAC will recover CRS from the CRS_DV

signal and use that along with its TX_EN signal to determine col-

lision.

SNI COLLISION DETECT: Asserted high to indicate detection of

a collision condition (simultaneous transmit and receive activity)

in 10 Mb/s SNI mode.

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10

1.3 Clock Interface

Signal Name

Type

Pin #

Description

X1

I

34

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock

reference input for the DP83848C and must be connected to a 25

MHz 0.005% (+50 ppm) clock source. The DP83848C supports

either an external crystal resonator connected across pins X1 and

X2, or an external CMOS-level oscillator source connected to pin

X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock refer-

ence input for the RMII mode and must be connected to a 50 MHz

0.005% (+50 ppm) CMOS-level oscillator source.

X2

O

33

25

CRYSTAL OUTPUT: This pin is the primary clock reference out-

put to connect to an external 25 MHz crystal resonator device.

This pin must be left unconnected if an external CMOS oscillator

clock source is used.

25MHz_OUT

25 MHz CLOCK OUTPUT:

In MII mode, this pin provides a 25 MHz clock output to the sys-

tem.

In RMII mode, this pin provides a 50 MHz clock output to the sys-

tem.

This allows other devices to use the reference clock from the

DP83848C without requiring additional clock sources.

1.4 LED Interface

See Table 3 for LED Mode Selection.

Signal Name

LED_LINK

Type

Pin #

Description

S, O, PU

28

LINK LED: In Mode 1, this pin indicates the status of the LINK.

The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit

and receive activity in addition to the status of the Link. The LED

will be ON when Link is good. It will blink when the transmitter or

receiver is active.

LED_SPEED

S, O, PU

27

26

SPEED LED: The LED is ON when device is in 100 Mb/s and OFF

when in 10 Mb/s. Functionality of this LED is independent of mode

selected.

LED_ACT/COL

ACTIVITY LED: In Mode 1, this pin is the Activity LED which is

ON when activity is present on either Transmit or Receive.

COLLISION/DUPLEX LED: In Mode 2, this pin by default indi-

cates Collision detection. For Mode 3, this LED output may be

programmed to indicate Full-duplex status instead of Collision.

11

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1.5 Reset and Power Down

Signal Name

Type

Pin #

Description

RESET_N

I, PU

29

RESET: Active Low input that initializes or re-initializes the

DP83848C. Asserting this pin low for at least 1 µs will force a reset

process to occur. All internal registers will re-initialize to their de-

fault states as specified for each bit in the Register Block section.

All strap options are re-initialized as well.

PWR_DOWN/INT

I, OD, PU

7

See Section 5.5 for detailed description.

The default function of this pin is POWER DOWN.

POWER DOWN: The pin is an active low input in this mode and

should be asserted low to put the device in a Power Down mode.

INTERRUPT: The pin is an open drain output in this mode and will

be asserted low when an interrupt condition occurs. Although the

pin has a weak internal pull-up, some applications may require an

external pull-up resister. Register access is required for the pin to

be used as an interrupt mechanism. See Section 5.5.2 Interrupt

Mechanism for more details on the interrupt mechanisms.

1.6 Strap Options

The DP83848C uses many of the functional pins as strap options. The values of these pins are sampled during reset and

used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The func-

tional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default option is

required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate functions

after reset is deasserted, they should not be connected directly to VCC or GND.

Signal Name

PHYAD0 (COL)

Type

Pin #

42

Description

S, O, PU

S, O, PD

PHY ADDRESS [4:0]: The DP83848C provides five PHY ad-

dress pins, the state of which are latched into the PHYCTRL reg-

ister at system Hardware-Reset.

PHYAD1 (RXD_0)

PHYAD2 (RXD_1)

PHYAD3 (RXD_2)

PHYAD4 (RXD_3)

43

44

The DP83848C supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). A PHY Address of 0 puts the

part into the MII Isolate Mode. The MII isolate mode must be se-

lected by strapping Phy Address 0; changing to Address 0 by reg-

ister write will not put the Phy in the MII isolate mode. Please refer

to section 2.3 for additional information.

45

46

PHYAD0 pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

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12

Signal Name

AN_EN (LED_ACT/COL)

AN_1 (LED_SPEED)

AN_0 (LED_LINK)

Type

Pin #

26

Description

S, O, PU

Auto-Negotiation Enable: When high, this enables Auto-Negoti-

ation with the capability set by ANO and AN1 pins. When low, this

puts the part into Forced Mode with the capability set by AN0 and

AN1 pins.

27

28

AN0 / AN1: These input pins control the forced or advertised op-

erating mode of the DP83848C according to the following table.

The value on these pins is set by connecting the input pins to

GND (0) or V_CC(1) through 2.2 kΩ resistors. These pins should

NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83848C at Hard-

ware-Reset.

The float/pull-down status of these pins are latched into the Basic

Mode Control Register and the Auto_Negotiation Advertisement

Register during Hardware-Reset.

The default is 111 since these pins have internal pull-ups.

AN_EN AN1 AN0

Forced Mode

0

1

0

1

0

1

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

Advertised Mode

AN_EN AN1 AN0

1

0

1

0

1

0

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX,Half/Full-Duplex

1

MII_MODE (RX_DV)

SNI_MODE (TXD_3)

S, O, PD

39

6

MII MODE SELECT: This strapping option pair determines the

operating mode of the MAC Data Interface. Default operation (No

pull-ups) will enable normal MII Mode of operation. Strapping

MII_MODE high will cause the device to be in RMII or SNI mode

of operation, determined by the status of the SNI_MODE strap.

Since the pins include internal pull-downs, the default values are

0.

The following table details the configurations:

MII_MODE SNI_MODE

MAC Interface

Mode

0

1

X

0

1

MII Mode

RMII Mode

10 Mb SNI Mode

LED_CFG (CRS)

S, O, PU

40

41

LED CONFIGURATION: This strapping option determines the

mode of operation of the LED pins. Default is Mode 1. Mode 1 and

Mode 2 can be controlled via the strap option. All modes are con-

figurable via register access.

SeeTable 3 for LED Mode Selection.

MDIX_EN (RX_ER)

MDIX ENABLE: Default is to enable MDIX. This strapping option

disables Auto-MDIX. An external pull-down will disable Auto-

MDIX mode.

13

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1.7 10 Mb/s and 100 Mb/s PMD Interface

Signal Name

TD-, TD+

Type

Pin #

Description

I/O

16, 17

Differential common driver transmit output (PMD Output Pair).

These differential outputs are automatically configured to either

10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Re-

ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+

I/O

13, 14

Differential receive input (PMD Input Pair). These differential in-

puts are automatically configured to accept either 100BASE-TX

or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the

Transmit Output pair.

These pins require 3.3V bias for operation.

1.8 Special Connections

Signal Name

Type

Pin #

Description

RBIAS

I

24

Bias Resistor Connection. A 4.87 kΩ 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT

O

I

23

Power Feedback Output. Parallel caps, 10µ F (Tantalum pre-

ferred) and 0.1µF, should be placed close to the PFBOUT. Con-

nect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See

Section 5.4 for proper placement pin.

PFBIN1

PFBIN2

18

37

Power Feedback Input. These pins are fed with power from

PFBOUT pin. A small capacitor of 0.1µF should be connected

close to each pin.

Note: Do not supply power to these pins other than from

PFBOUT.

RESERVED

I/O

8, 9, 10, 11, RESERVED: These pins must be left unconnected.

12

20, 21

RESERVED: These pins must be pulled-up through 2.2 kΩ resis-

tors to AVDD33 supply.

1.9 Power Supply Pins

Signal Name

IOVDD33

IOGND

Pin #

Description

I/O 3.3V Supply

32, 48

35, 47

36

I/O Ground

DGND

Digital Ground

AVDD33

22

Analog 3.3V Supply

Analog Ground

AGND

15, 19

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1.10 Package Pin Assignments

VBH48A Pin # Pin Name

41

42

43

44

45

46

47

48

RX_ER/MDIX_EN

COL/PHYAD0

RXD_0/PHYAD1

RXD_1/PHYAD2

RXD_2/PHYAD3

RXD_3/PHYAD4

IOGND

1

TX_CLK

2

TX_EN

3

TXD_0

4

TXD_1

5

TXD_2

6

TXD_3/SNI_MODE

PWR_DOWN/INT

RESERVED

RD -

IOVDD33

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

RD +

AGND

TD -

TD +

PFBIN1

AGND

RESERVED

AVDD33

PFBOUT

RBIAS

25MHz_OUT

LED_ACT/COL/AN_EN

LED_SPEED/AN1

LED_LINK/AN0

RESET_N

MDIO

MDC

IOVDD33

X2

X1

IOGND

DGND

PFBIN2

RX_CLK

RX_DV/MII_MODE

CRS/CRS_DV/LED_CFG

15

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2.0 Configuration

This section includes information on the various configura-

tion options available with the DP83848C. The configura-

tion options described below include:

Table 1. Auto-Negotiation Modes

AN_EN AN1

AN0

Forced Mode

0

1

0

1

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

Advertised Mode

— Auto-Negotiation

— PHY Address and LEDs

— Half Duplex vs. Full Duplex

— Isolate mode

0

1

— Loopback mode

— BIST

AN_EN AN1

AN0

0

1

0

1

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

1

2.1 Auto-Negotiation

0

The Auto-Negotiation function provides a mechanism for

exchanging configuration information between two ends of

a link segment and automatically selecting the highest per-

formance mode of operation supported by both devices.

Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83848C supports four differ-

ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high-

est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83848C can be controlled either by

internal register access or by the use of the AN_EN, AN1

and AN0 pins.

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

1

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848C trans-

mits the abilities programmed into the Auto-Negotiation

Advertisement register (ANAR) at address 04h via FLP

Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-

Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:

— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex

— (3) 10BASE-T Full Duplex

2.1.1 Auto-Negotiation Pin Control

— (4) 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the

Auto-Negotiation process. When Auto-Negotiation is dis-

abled, the Speed Selection bit in the BMCR controls

switching between 10 Mb/s or 100 Mb/s operation, and the

Duplex Mode bit controls switching between full duplex

operation and half duplex operation. The Speed Selection

and Duplex Mode bits have no effect on the mode of oper-

The state of AN_EN, AN0 and AN1 determines whether the

DP83848C is forced into a specific mode or Auto-Negotia-

tion will advertise a specific ability (or set of abilities) as

given in Table 1. These pins allow configuration options to

be selected without requiring internal register access.

The state of AN_EN, AN0 and AN1, upon power-up/reset,

determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or ation when the Auto-Negotiation Enable bit is set.

reset can be changed at any time by writing to the Basic

Mode Control Register (BMCR) at address 0x00h.

The Link Speed can be examined through the PHY Status

Register (PHYSTS) at address 10h after a Link is

achieved.

The Basic Mode Status Register (BMSR) indicates the set

of available abilities for technology types, Auto-Negotiation

ability, and Extended Register Capability. These bits are

permanently set to indicate the full functionality of the

DP83848C (only the 100BASE-T4 bit is not set since the

DP83848C does not support that function).

The BMSR also provides status on:

— Whether or not Auto-Negotiation is complete

— Whether or not the Link Partner is advertising that a re-

mote fault has occurred

— Whether or not valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR)

indicates the Auto-Negotiation abilities to be advertised by

the DP83848C. All available abilities are transmitted by

default, but any ability can be suppressed by writing to the

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16

ANAR. Updating the ANAR to suppress an ability is one 2.1.4 Auto-Negotiation Restart

way for a management agent to change (restrict) the tech-

nology that is used.

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu-

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

The Auto-Negotiation Link Partner Ability Register

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83848C to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83848C will resume Auto-Negotiation after the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

— Whether or not a Parallel Detect Fault has occurred

— Whether or not the Link Partner supports the Next Page

function

— Whether or not the DP83848C supports the Next Page

function

2.1.5 Enabling Auto-Negotiation via Software

— Whether or not the current page being exchanged by

Auto-Negotiation has been received

It is important to note that if the DP83848C has been initial-

ized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit 12 (Auto-Negotiation Enable) of the Basic Mode Control

Register (BMCR) must first be cleared and then set for any

Auto-Negotiation function to take effect.

— Whether or not the Link Partner supports Auto-Negotia-

tion

2.1.3 Auto-Negotiation Parallel Detection

The DP83848C supports the Parallel Detection function as

defined in the IEEE 802.3u specification. Parallel Detection

requires both the 10 Mb/s and 100 Mb/s receivers to moni-

tor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this informa-

tion to configure the correct technology in the event that the

Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com-

plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

If the DP83848C completes Auto-Negotiation as a result of

Parallel Detection, bits 5 and 7 within the ANLPAR register

will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter-

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able bit

once the Auto-Negotiation Complete bit is set. If configured

for parallel detect mode and any condition other than a sin-

gle good link occurs then the parallel detect fault bit will be

set.

2.2 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to

determine the proper configuration for transmission and

reception of data and subsequently selects the appropriate

MDI pair for MDI/MDIX operation. The function uses a ran-

dom seed to control switching of the crossover circuitry.

This implementation complies with the corresponding IEEE

802.3 Auto-Negotiation and Crossover Specifications.

Auto-MDIX is enabled by default and can be configured via

strap or via PHYCR (0x19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced

crossover can be achieved through the FORCE_MDIX bit,

bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera-

tion.

17

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Since the PHYAD[0] pin has weak internal pull-up resistor

and PHYAD[4:1] pins have weak internal pull-down resis-

tors, the default setting for the PHY address is 00001

(01h).

2.3 PHY Address

The 5 PHY address inputs pins are shared with the

RXD[3:0] pins and COL pin as shown below.

Refer to Figure 2 for an example of a PHYAD connection to

external components. In this example, the PHYAD strap-

ping results in address 00011 (03h).

Table 2. PHY Address Mapping

Pin #

42

PHYAD Function

PHYAD0

RXD Function

COL

43

PHYAD1

RXD_0

2.3.1 MII Isolate Mode

44

PHYAD2

RXD_1

The DP83848C can be put into MII Isolate mode by writing

to bit 10 of the BMCR register or by strapping in Physical

Address 0. It should be noted that selecting Physical

Address 0 via an MDIO write to PHYCR will not put the

device in the MII isolate mode.

45

PHYAD3

RXD_2

46

PHYAD4

RXD_3

The DP83848C can be set to respond to any of 32 possible

PHY addresses via strap pins. The information is latched

into the PHYCR register (address 19h, bits [4:0]) at device

power-up and hardware reset. The PHY Address pins are

shared with the RXD and COL pins. Each DP83848C or

port sharing an MDIO bus in a system must have a unique

physical address.

When in the MII isolate mode, the DP83848C does not

respond to packet data present at TXD[3:0], TX_EN inputs

and presents a high impedance on the TX_CLK, RX_CLK,

RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When

in Isolate mode, the DP83848C will continue to respond to

all management transactions.

While in Isolate mode, the PMD output pair will not transmit

packet data but will continue to source 100BASE-TX

scrambled idles or 10BASE-T normal link pulses.

The DP83848C supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). Strapping PHY Address

0 puts the part into Isolate Mode. It should also be noted

that selecting PHY Address 0 via an MDIO write to PHYCR

will not put the device in Isolate Mode. See Section 2.3.1for

more information.

The DP83848C can Auto-Negotiate or parallel detect to a

specific technology depending on the receive signal at the

PMD input pair. A valid link can be established for the

receiver even when the DP83848C is in Isolate mode.

For further detail relating to the latch-in timing requirements

of the PHY Address pins, as well as the other hardware

configuration pins, refer to the Reset summary in

Section 6.0.

PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1

PHYAD4= 0

VCC

Figure 2. PHYAD Strapping Example

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2.4 LED Interface

multiplexed among the LEDs. The PHY Control Register

(PHYCR) for the LEDs can also be selected through

address 19h, bits [6:5].

The DP83848C supports three configurable Light Emitting

Diode (LED) pins. The device supports three LED configu-

rations: Link, Speed, Activity and Collision. Function are

See Table 3 for LED Mode selection.

Table 3. LED Mode Select

Mode

LED_CFG[1]

(bit 6)

LED_CFG[0]

(bit 5)

LED_LINK

LED_SPEED

LED_ACT/COL

or (pin40)

1

2

3

don’t care

1

ON for Good Link

OFF for No Link

ON for Good Link

BLINK for Activity

ON for Good Link

BLINK for Activity

ON in 100 Mb/s

OFF in 10 Mb/s

ON in 100 Mb/s

OFF in 10 Mb/s

ON in 100 Mb/s

OFF in 10 Mb/s

ON for Activity

OFF for No Activity

ON for Collision

0

1

0

OFF for No Collision

ON for Full Duplex

OFF for Half Duplex

The LED_LINK pin in Mode 1 indicates the link status of Specifically, when the LED outputs are used to drive LEDs

the port. In 100BASE-T mode, link is established as a directly, the active state of each output driver is dependent

result of input receive amplitude compliant with the TP- on the logic level sampled by the corresponding AN input

PMD specifications which will result in internal generation upon power-up/reset. For example, if a given AN input is

of signal detect. A 10 Mb/s Link is established as a result of resistively pulled low then the corresponding output will be

the reception of at least seven consecutive normal Link configured as an active high driver. Conversely, if a given

Pulses or the reception of a valid 10BASE-T packet. This AN input is resistively pulled high, then the corresponding

will cause the assertion of LED_LINK. LED_LINK will deas- output will be configured as an active low driver.

sert in accordance with the Link Loss Timer as specified in

the IEEE 802.3 specification.

Refer to Figure 3 for an example of AN connections to

external components. In this example, the AN strapping

The LED_LINK pin in Mode 1 will be OFF when no LINK is results in Auto-Negotiation with 10/100 Half/Full-Duplex

present.

advertised.

The LED_LINK pin in Mode 2 and Mode 3 will be ON to The adaptive nature of the LED outputs helps to simplify

indicate Link is good and BLINK to indicate activity is potential implementation issues of these dual purpose pins.

present on either transmit or receive activity.

The LED_SPEED pin indicates 10 or 100 Mb/s data rate of

the port. The standard CMOS driver goes high when oper-

ating in 100 Mb/s operation. The functionality of this LED is

independent of mode selected.

The LED_ACT/COL pin in Mode 1 indicates the presence

of either transmit or receive activity. The LED will be ON for

Activity and OFF for No Activity. In Mode 2, this pin indi-

cates the Collision status of the port. The LED will be ON

for Collision and OFF for No Collision.

AN_EN = 1 AN1 = 1

AN0 = 1

The LED_ACT/COL pin in Mode 3 indicates the presence

of Duplex status for 10 Mb/s or 100 Mb/s operation. The

LED will be ON for Full Duplex and OFF for Half Duplex.

In 10 Mb/s half duplex mode, the collision LED is based on

the COL signal.

Since these LED pins are also used as strap options, the

polarity of the LED is dependent on whether the pin is

pulled up or down.

VCC

2.4.1 LEDs

Since the Auto-Negotiation (AN) strap options share the

LED output pins, the external components required for

strapping and LED usage must be considered in order to

avoid contention.

Figure 3. AN Strapping and LED Loading Example

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2.4.2 LED Direct Control

2.6 Internal Loopback

The DP83848C provides another option to directly control

any or all LED outputs through the LED Direct Control Reg-

ister (LEDCR), address 18h. The register does not provide

read access to LEDs.

The DP83848C includes a Loopback Test mode for facili-

tating system diagnostics. The Loopback mode is selected

through bit 14 (Loopback) of the Basic Mode Control Reg-

ister (BMCR). Writing 1 to this bit enables MII transmit data

to be routed to the MII receive outputs. Loopback status

may be checked in bit 3 of the PHY Status Register

(PHYSTS). While in Loopback mode the data will not be

transmitted onto the media. To ensure that the desired

operating mode is maintained, Auto-Negotiation should be

disabled before selecting the Loopback mode.

2.5 Half Duplex vs. Full Duplex

The DP83848C supports both half and full duplex opera-

tion at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the CSMA/CD protocol to handle colli-

sions and network access. In Half-Duplex mode, CRS

responds to both transmit and receive activity in order to

maintain compliance with the IEEE 802.3 specification.

2.7 BIST

The DP83848C incorporates an internal Built-in Self Test

(BIST) circuit to accommodate in-circuit testing or diagnos-

tics. The BIST circuit can be utilized to test the integrity of

the transmit and receive data paths. BIST testing can be

performed with the part in the internal loopback mode or

externally looped back using a loopback cable fixture.

Since the DP83848C is designed to support simultaneous

transmit and receive activity it is capable of supporting full-

duplex switched applications with a throughput of up to 200

Mb/s per port when operating in 100BASE-TX mode.

Because the CSMA/CD protocol does not apply to full-

duplex operation, the DP83848C disables its own internal

collision sensing and reporting functions and modifies the

behavior of Carrier Sense (CRS) such that it indicates only

receive activity. This allows a full-duplex capable MAC to

operate properly.

The BIST is implemented with independent transmit and

receive paths, with the transmit block generating a continu-

ous stream of a pseudo random sequence. The user can

select a 9 bit or 15 bit pseudo random sequence from the

PSR_15 bit in the PHY Control Register (PHYCR). The

received data is compared to the generated pseudo-ran-

dom data by the BIST Linear Feedback Shift Register

(LFSR) to determine the BIST pass/fail status.

All modes of operation (100BASE-TX and 10BASE-T) can

run either half-duplex or full-duplex. Additionally, other than

CRS and Collision reporting, all remaining MII signaling

remains the same regardless of the selected duplex mode.

The pass/fail status of the BIST is stored in the BIST status

bit in the PHYCR register. The status bit defaults to 0 (BIST

fail) and will transition on a successful comparison. If an

error (mis-compare) occurs, the status bit is latched and is

cleared upon a subsequent write to the Start/Stop bit.

It is important to understand that while Auto-Negotiation

with the use of Fast Link Pulse code words can interpret

and configure to full-duplex operation, parallel detection

can not recognize the difference between full and half-

duplex from a fixed 10 Mb/s or 100 Mb/s link partner over

twisted pair. As specified in the 802.3u specification, if a

far-end link partner is configured to a forced full duplex

100BASE-TX ability, the parallel detection state machine in

the partner would be unable to detect the full duplex capa-

bility of the far-end link partner. This link segment would

negotiate to a half duplex 100BASE-TX configuration

(same scenario for 10 Mb/s).

For transmit VOD testing, the Packet BIST Continuous

Mode can be used to allow continuous data transmission,

setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the

BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].

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If the DP83848C is transmitting in 10 Mb/s mode when a

collision is detected, the collision is not reported until seven

bits have been received while in the collision state. This

prevents a collision being reported incorrectly due to noise

on the network. The COL signal remains set for the dura-

tion of the collision.

3.0 Functional Description

The DP83848C supports several modes of operation using

the MII interface pins. The options are defined in the follow-

ing sections and include:

— MII Mode

If a collision occurs during a receive operation, it is immedi-

ately reported by the COL signal.

— RMII Mode

— 10 Mb Serial Network Interface (SNI)

When heartbeat is enabled (only applicable to 10 Mb/s

operation), approximately 1µs after the transmission of

each packet, a Signal Quality Error (SQE) signal of approx-

imately 10 bit times is generated (internally) to indicate

successful transmission. SQE is reported as a pulse on the

COL signal of the MII.

The modes of operation can be selected by strap options

or register control. For RMII mode, it is required to use the

strap option, since it requires a 50 MHz clock instead of the

normal 25 MHz.

In each of these modes, the IEEE 802.3 serial manage-

ment interface is operational for device configuration and

status. The serial management interface of the MII allows

for the configuration and control of multiple PHY devices,

gathering of status, error information, and the determina-

tion of the type and capabilities of the attached PHY(s).

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,

once valid data is detected via the squelch function during

10 Mb/s operation. During 100 Mb/s operation CRS is

asserted when a valid link (SD) and two non-contiguous

zeros are detected on the line.

3.1 MII Interface

The DP83848C incorporates the Media Independent Inter-

face (MII) as specified in Clause 22 of the IEEE 802.3u

standard. This interface may be used to connect PHY

devices to a MAC in 10/100 Mb/s systems. This section

describes the nibble wide MII data interface.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted

during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted

only due to receive activity.

The nibble wide MII data interface consists of a receive bus

and a transmit bus each with control signals to facilitate

data transfer between the PHY and the upper layer (MAC).

CRS is deasserted following an end of packet.

3.2 Reduced MII Interface

The DP83848C incorporates the Reduced Media Indepen-

dent Interface (RMII) as specified in the RMII specification

(rev1.2) from the RMII Consortium. This interface may be

used to connect PHY devices to a MAC in 10/100 Mb/s

systems using a reduced number of pins. In this mode,

data is transferred 2-bits at a time using the 50 MHz

RMII_REF clock for both transmit and receive. The follow-

ing pins are used in RMII mode:

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the

Media Independent Interface. This interface includes a

dedicated receive bus and a dedicated transmit bus. These

two data buses, along with various control and status sig-

nals, allow for the simultaneous exchange of data between

the DP83848C and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus

RXD[3:0], a receive error signal RX_ER, a receive data

valid flag RX_DV, and a receive clock RX_CLK for syn-

chronous transfer of the data. The receive clock operates

— TX_EN

— TXD[1:0]

— RX_ER (optional for Mac)

at either 2.5 MHz to support 10 Mb/s operation modes or at — CRS_DV

25 MHz to support 100 Mb/s operational modes.

— RXD[1:0]

The transmit interface consists of a nibble wide data bus

TXD[3:0], a transmit enable control signal TX_EN, and a

transmit clock TX_CLK which runs at either 2.5 MHz or 25

MHz.

— X1 (RMII Reference clock is 50 MHz)

In addition, the RMII mode supplies an RX_DV signal

which allows for a simpler method of recovering receive

data without having to separate RX_DV from the CRS_DV

indication. This is especially useful for systems which do

not require CRS, such as systems that only support full-

duplex operation. This signal is also useful for diagnostic

testing where it may be desirable to loop Receive RMII

data directly to the transmitter.

Additionally, the MII includes the carrier sense signal CRS,

as well as a collision detect signal COL. The CRS signal

asserts to indicate the reception of data from the network

or as a function of transmit data in Half Duplex mode. The

COL signal asserts as an indication of a collision which can

occur during half-duplex operation when both a transmit

and receive operation occur simultaneously.

Since the reference clock operates at 10 times the data

rate for 10 Mb/s operation, transmit data is sampled every

10 clocks. Likewise, receive data will be generated every

10th clock so that an attached device can sample the data

every 10 clocks.

3.1.2 Collision Detect

RMII mode requires a 50 MHz oscillator be connected to

the device X1 pin. A 50 MHz crystal is not supported.

For Half Duplex, a 10BASE-T or 100BASE-TX collision is

detected when the receive and transmit channels are

active simultaneously. Collisions are reported by the COL

signal on the MII.

21

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To tolerate potential frequency differences between the 50 The elasticity buffer will force Frame Check Sequence

MHz reference clock and the recovered receive clock, the errors for packets which overrun or underrun the FIFO.

receive RMII function includes a programmable elasticity Underrun and Overrun conditions can be reported in the

buffer. The elasticity buffer is programmable to minimize RMII and Bypass Register (RBR). The following table indi-

propagation delay based on expected packet size and cates how to program the elasticity buffer fifo (in 4-bit incre-

clock accuracy. This allows for supporting a range of ments) based on expected max packet size and clock

packet sizes including jumbo frames.

accuracy. It assumes both clocks (RMII Reference clock

and far-end Transmitter clock) have the same accuracy.

Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock

Start Threshold

RBR[1:0]

Latency Tolerance

Recommended Packet Size Recommended Packet Size

at +/- 50ppm

2400 bytes

7200 bytes

12000 bytes

16800 bytes

at +/- 100ppm

1200 bytes

3600 bytes

6000 bytes

8400 bytes

1 (4-bits)

2 (8-bits)

3 (12-bits)

0 (16-bits)

2 bits

6 bits

10 bits

14 bits

The MDIO pin requires a pull-up resistor (1.5 kΩ) which,

during IDLE and turnaround, will pull MDIO high. In order to

initialize the MDIO interface, the station management entity

sends a sequence of 32 contiguous logic ones on MDIO to

provide the DP83848C with a sequence that can be used

to establish synchronization. This preamble may be gener-

ated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pull-up resis-

tor to pull the MDIO pin high during which time 32 MDC

clock cycles are provided. In addition 32 MDC clock cycles

should be used to re-sync the device if an invalid start,

opcode, or turnaround bit is detected.

3.3 10 Mb Serial Network Interface (SNI)

The DP83848C incorporates a 10 Mb Serial Network Inter-

face (SNI) which allows a simple serial data interface for 10

Mb only devices. This is also referred to as a 7-wire inter-

face. While there is no defined standard for this interface, it

is based on early 10 Mb physical layer devices. Data is

clocked serially at 10 MHz using separate transmit and

receive paths. The following pins are used in SNI mode:

— TX_CLK

— TX_EN

— TXD[0]

— RX_CLK

— RXD[0]

— CRS

The DP83848C waits until it has received this preamble

sequence before responding to any other transaction.

Once the DP83848C serial management port has been ini-

tialized no further preamble sequencing is required until

after a power-on/reset, invalid Start, invalid Opcode, or

invalid turnaround bit has occurred.

— COL

The Start code is indicated by a <01> pattern. This assures

the MDIO line transitions from the default idle line state.

3.4 802.3u MII Serial Management Interface

Turnaround is defined as an idle bit time inserted between

the Register Address field and the Data field. To avoid con-

tention during a read transaction, no device shall actively

drive the MDIO signal during the first bit of Turnaround.

The addressed DP83848C drives the MDIO with a zero for

the second bit of turnaround and follows this with the

required data. Figure 4 shows the timing relationship

between MDC and the MDIO as driven/received by the Sta-

tion (STA) and the DP83848C (PHY) for a typical register

read access.

3.4.1 Serial Management Register Access

The serial management MII specification defines a set of

thirty-two 16-bit status and control registers that are acces-

sible through the management interface pins MDC and

MDIO. The DP83848C implements all the required MII reg-

isters as well as several optional registers. These registers

are fully described in Section 7.0. A description of the serial

management access protocol follows.

For write transactions, the station management entity

writes data to the addressed DP83848C thus eliminating

the requirement for MDIO Turnaround. The Turnaround

time is filled by the management entity by inserting <10>.

Figure 5 shows the timing relationship for a typical MII reg-

ister write access.

3.4.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage-

ment Data Clock (MDC) and Management Data Input/Out-

put (MDIO). MDC has a maximum clock rate of 25 MHz

and no minimum rate. The MDIO line is bi-directional and

may be shared by up to 32 devices. The MDIO frame for-

mat is shown below in Table 5.

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22

Table 5. Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation

Write Operation

MDC

Z

MDIO

(STA)

Z

MDIO

(PHY)

Z

0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0

Opcode

(Read)

Register Address

(00h = BMCR)

PHY Address

Register Data

Idle

TA

Idle

Start

(PHYAD = 0Ch)

Figure 4. Typical MDC/MDIO Read Operation

MDC

Z

MDIO

(STA)

Z

0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PHY Address

Register Address

(00h = BMCR)

Opcode

(Write)

Register Data

Idle

Start

TA

(PHYAD = 0Ch)

Figure 5. Typical MDC/MDIO Write Operation

3.4.3 Serial Management Preamble Suppression

requirement is generally met by the mandatory pull-up

resistor on MDIO in conjunction with a continuous MDC, or

the management access made to determine whether Pre-

amble Suppression is supported.

The DP83848C supports a Preamble Suppression mode

as indicated by a one in bit 6 of the Basic Mode Status

Register (BMSR, address 01h.) If the station management

entity (i.e. MAC or other management controller) deter-

mines that all PHYs in the system support Preamble Sup-

pression by returning a one in this bit, then the station

management entity need not generate preamble for each

management transaction.

While the DP83848C requires an initial preamble

sequence of 32 bits for management initialization, it does

not require a full 32-bit sequence between each subse-

quent transaction. A minimum of one idle bit between man-

agement transactions is required as specified in the IEEE

802.3u specification.

The DP83848C requires a single initialization sequence of

32 bits of preamble following hardware/software reset. This

23

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The block diagram in Figure 6. provides an overview of

each functional block within the 100BASE-TX transmit sec-

tion.

4.0 Architecture

This section describes the operations within each trans-

ceiver module, 100BASE-TX and 10BASE-T. Each opera-

tion consists of several functional blocks and described in

the following:

The Transmitter section consists of the following functional

blocks:

— Code-group Encoder and Injection block

— Scrambler block (bypass option)

— 100BASE-TX Transmitter

— 100BASE-TX Receiver

— NRZ to NRZI encoder block

— 10BASE-T Transceiver Module

— Binary to MLT-3 converter / Common Driver

The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications

where data conversion is not always required. The

DP83848C implements the 100BASE-TX transmit state

machine diagram as specified in the IEEE 802.3u Stan-

dard, Clause 24.

4.1 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional

blocks which convert synchronous 4-bit nibble data, as pro-

vided by the MII, to a scrambled MLT-3 125 Mb/s serial

data stream. Because the 100BASE-TX TP-PMD is inte-

grated, the differential output pins, PMD Output Pair, can

be directly routed to the magnetics.

TX_CLK

TXD[3:0] /

TX_EN

DIVIDE

BY 5

4B5B CODE-

GROUP

ENCODER &

5B PARALLEL

TO SERIAL

125MHZ CLOCK

SCRAMBLER

MUX

BP_SCR

MLT[1:0]

100BASE-TX

LOOPBACK

NRZ TO NRZI

ENCODER

BINARY

TO MLT-3 /

COMMON

DRIVER

PMD OUTPUT PAIR

Figure 6. 100BASE-TX Transmit Block Diagram

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24

Table 65. 4B5B Code-Group Encoding/Decoding

DATA CODES

0

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

IDLE AND CONTROL CODES

H

00100

11111

11000

10001

01101

00111

HALT code-group - Error code

I

Inter-Packet IDLE - 0000 (Note 1)

First Start of Packet - 0101 (Note 1)

Second Start of Packet - 0101 (Note 1)

First End of Packet - 0000 (Note 1)

Second End of Packet - 0000 (Note 1)

J

K

T

R

INVALID CODES

V

00000

00001

00010

00011

00101

00110

01000

01100

Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER as-

serted.

25

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4.1.1 Code-group Encoding and Injection

transmit transformer primary winding, resulting in a MLT-3

signal.

The code-group encoder converts 4-bit (4B) nibble data

generated by the MAC into 5-bit (5B) code-groups for

transmission. This conversion is required to allow control

data to be combined with packet data code-groups. Refer

to Table 5 for 4B to 5B code-group mapping details.

The 100BASE-TX MLT-3 signal sourced by the PMD Out-

put Pair common driver is slew rate controlled. This should

be considered when selecting AC coupling magnetics to

ensure TP-PMD Standard compliant transition times (3 ns

< Tr < 5 ns).

The code-group encoder substitutes the first 8-bits of the

MAC preamble with a J/K code-group pair (11000 10001)

upon transmission. The code-group encoder continues to

replace subsequent 4B preamble and data nibbles with

corresponding 5B code-groups. At the end of the transmit

packet, upon the deassertion of Transmit Enable signal

from the MAC, the code-group encoder injects the T/R

code-group pair (01101 00111) indicating the end of the

frame.

The 100BASE-TX transmit TP-PMD function within the

DP83848C is capable of sourcing only MLT-3 encoded

data. Binary output from the PMD Output Pair is not possi-

ble in 100 Mb/s mode.

4.2 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional

blocks which convert the scrambled MLT-3 125 Mb/s serial

data stream to synchronous 4-bit nibble data that is pro-

vided to the MII. Because the 100BASE-TX TP-PMD is

integrated, the differential input pins, RD±, can be directly

routed from the AC coupling magnetics.

After the T/R code-group pair, the code-group encoder

continuously injects IDLEs into the transmit data stream

until the next transmit packet is detected (reassertion of

Transmit Enable).

See Figure 7 for a block diagram of the 100BASE-TX

receive function. This provides an overview of each func-

tional block within the 100BASE-TX receive section.

4.1.2 Scrambler

The scrambler is required to control the radiated emissions

at the media connector and on the twisted pair cable (for

100BASE-TX applications). By scrambling the data, the

total energy launched onto the cable is randomly distrib-

uted over a wide frequency range. Without the scrambler,

The Receive section consists of the following functional

blocks:

— Analog Front End

energy levels at the PMD and on the cable could peak — Digital Signal Processor

beyond FCC limitations at frequencies related to repeating

5B sequences (i.e., continuous transmission of IDLEs).

— MLT-3 to Binary Decoder

The scrambler is configured as a closed loop linear feed-

— Signal Detect

— NRZI to NRZ Decoder

back shift register (LFSR) with an 11-bit polynomial. The

— Serial to Parallel

— Descrambler

output of the closed loop LFSR is X-ORd with the serial

NRZ data from the code-group encoder. The result is a

scrambled data stream with sufficient randomization to

decrease radiated emissions at certain frequencies by as

much as 20 dB. The DP83848C uses the PHY_ID (pins

PHYAD [4:0]) to set a unique seed value.

— Code Group Alignment

— 4B/5B Decoder

— Link Integrity Monitor

— Bad SSD Detection

4.1.3 NRZ to NRZI Encoder

4.2.1 Analog Front End

After the transmit data stream has been serialized and

scrambled, the data must be NRZI encoded in order to

comply with the TP-PMD standard for 100BASE-TX trans-

mission over Category-5 Unshielded twisted pair cable.

In addition to the Digital Equalization and Gain Control, the

DP83848C includes Analog Equalization and Gain Control

in the Analog Front End. The Analog Equalization reduces

the amount of Digital Equalization required in the DSP.

4.1.4 Binary to MLT-3 Convertor

4.2.2 Digital Signal Processor

The Binary to MLT-3 conversion is accomplished by con-

verting the serial binary data stream output from the NRZI

encoder into two binary data streams with alternately

phased logic one events. These two binary streams are

then fed to the twisted pair output driver which converts the

voltage to current and alternately drives either side of the

The Digital Signal Processor includes Adaptive Equaliza-

tion with Gain Control and Base Line Wander Compensa-

tion.

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26

RX_DV/CRS

RX_CLK

RXD[3:0] / RX_ER

4B/5B DECODER

SERIAL TO

PARALLEL

CODE GROUP

ALIGNMENT

LINK

INTEGRITY

MONITOR

RX_DATA

VALID SSD

DETECT

DESCRAMBLER

NRZI TO NRZ

DECODER

MLT-3 TO BINARY

DECODER

SIGNAL

DETECT

DIGITAL

SIGNAL

PROCESSOR

ANALOG

FRONT

END

RD +/−

Figure 7. 100BASE-TX Receive Block Diagram

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4.2.2.1 Digital Adaptive Equalization and Gain Control tive to ensure proper conditioning of the received signal

independent of the cable length.

When transmitting data at high speeds over copper twisted

The DP83848C utilizes an extremely robust equalization

scheme referred as ‘Digital Adaptive Equalization.’

pair cable, frequency dependent attenuation becomes a

concern. In high-speed twisted pair signalling, the fre-

quency content of the transmitted signal can vary greatly

during normal operation based primarily on the random-

ness of the scrambled data stream. This variation in signal

attenuation caused by frequency variations must be com-

pensated to ensure the integrity of the transmission.

The Digital Equalizer removes ISI (inter symbol interfer-

ence) from the receive data stream by continuously adapt-

ing to provide a filter with the inverse frequency response

of the channel. Equalization is combined with an adaptive

gain control stage. This enables the receive 'eye pattern' to

be opened sufficiently to allow very reliable data recovery.

In order to ensure quality transmission when employing

MLT-3 encoding, the compensation must be able to adapt

to various cable lengths and cable types depending on the

installed environment. The selection of long cable lengths

for a given implementation, requires significant compensa-

tion which will over-compensate for shorter, less attenuat-

ing lengths. Conversely, the selection of short or

intermediate cable lengths requiring less compensation will

cause serious under-compensation for longer length

cables. The compensation or equalization must be adap-

The curves given in Figure 8 illustrate attenuation at certain

frequencies for given cable lengths. This is derived from

the worst case frequency vs. attenuation figures as speci-

fied in the EIA/TIA Bulletin TSB-36. These curves indicate

the significant variations in signal attenuation that must be

compensated for by the receive adaptive equalization cir-

cuit.

Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50,

100, 130 & 150 meters of CAT 5 cable

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4.2.2.2 Base Line Wander Compensation

Figure 9. 100BASE-TX BLW Event

The DP83848C is completely ANSI TP-PMD compliant and PMD Standard as well as the IEEE 802.3 100BASE-TX

includes Base Line Wander (BLW) compensation. The Standard for both voltage thresholds and timing parame-

BLW compensation block can successfully recover the TP- ters.

PMD defined “killer” pattern.

Note that the reception of normal 10BASE-T link pulses

BLW can generally be defined as the change in the aver- and fast link pulses per IEEE 802.3u Auto-Negotiation by

age DC content, relatively short period over time, of an AC the 100BASE-TX receiver do not cause the DP83848C to

coupled digital transmission over a given transmission assert signal detect.

medium. (i.e., copper wire).

BLW results from the interaction between the low fre-

quency components of a transmitted bit stream and the fre- 4.2.4 MLT-3 to NRZI Decoder

quency response of the AC coupling component(s) within

The DP83848C decodes the MLT-3 information from the

the transmission system. If the low frequency content of

Digital Adaptive Equalizer block to binary NRZI data.

the digital bit stream goes below the low frequency pole of

the AC coupling transformers then the droop characteris-

tics of the transformers will dominate resulting in potentially

serious BLW.

4.2.5 NRZI to NRZ

The digital oscilloscope plot provided in Figure 9 illustrates

the severity of the BLW event that can theoretically be gen-

erated during 100BASE-TX packet transmission. This

event consists of approximately 800 mV of DC offset for a

period of 120 µs. Left uncompensated, events such as this

can cause packet loss.

In a typical application, the NRZI to NRZ decoder is

required in order to present NRZ formatted data to the

descrambler.

4.2.6 Serial to Parallel

4.2.3 Signal Detect

The 100BASE-TX receiver includes a Serial to Parallel

converter which supplies 5-bit wide data symbols to the

PCS Rx state machine.

The signal detect function of the DP83848C is incorporated

to meet the specifications mandated by the ANSI FDDI TP-

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4.2.7 Descrambler

4.2.10 100BASE-TX Link Integrity Monitor

A serial descrambler is used to de-scramble the received The 100 Base TX Link monitor ensures that a valid and sta-

NRZ data. The descrambler has to generate an identical ble link is established before enabling both the Transmit

data scrambling sequence (N) in order to recover the origi- and Receive PCS layer.

nal unscrambled data (UD) from the scrambled data (SD)

as represented in the equations:

Signal detect must be valid for 395us to allow the link mon-

itor to enter the 'Link Up' state, and enable the transmit and

receive functions.

SD= (UD N)

UD= (SD N)

Synchronization of the descrambler to the original scram-

bling sequence (N) is achieved based on the knowledge

that the incoming scrambled data stream consists of

scrambled IDLE data. After the descrambler has recog-

nized 12 consecutive IDLE code-groups, where an

unscrambled IDLE code-group in 5B NRZ is equal to five

consecutive ones (11111), it will synchronize to the receive

data stream and generate unscrambled data in the form of

unaligned 5B code-groups.

4.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition

from consecutive idle code-groups to non-idle code-groups

which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83848C will assert

RX_ER and present RXD[3:0] = 1110 to the MII for the

cycles that correspond to received 5B code-groups until at

least two IDLE code groups are detected. In addition, the

False Carrier Sense Counter register (FCSCR) will be

incremented by one.

In order to maintain synchronization, the descrambler must

continuously monitor the validity of the unscrambled data

that it generates. To ensure this, a line state monitor and a

hold timer are used to constantly monitor the synchroniza-

tion status. Upon synchronization of the descrambler the

hold timer starts a 722 µs countdown. Upon detection of

sufficient IDLE code-groups (58 bit times) within the 722 µs

period, the hold timer will reset and begin a new count-

down. This monitoring operation will continue indefinitely

given a properly operating network connection with good

signal integrity. If the line state monitor does not recognize

sufficient unscrambled IDLE code-groups within the 722 µs

period, the entire descrambler will be forced out of the cur-

rent state of synchronization and reset in order to re-

acquire synchronization.

Once at least two IDLE code groups are detected, RX_ER

and CRS become de-asserted.

4.3 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compli-

ant. It includes the receiver, transmitter, collision, heart-

beat, loopback, jabber, and link integrity functions, as

defined in the standard. An external filter is not required on

the 10BASE-T interface since this is integrated inside the

DP83848C. This section focuses on the general 10BASE-T

system level operation.

4.2.8 Code-group Alignment

4.3.1 Operational Modes

The code-group alignment module operates on unaligned

5-bit data from the descrambler (or, if the descrambler is

bypassed, directly from the NRZI/NRZ decoder) and con-

verts it into 5B code-group data (5 bits). Code-group align-

ment occurs after the J/K code-group pair is detected.

Once the J/K code-group pair (11000 10001) is detected,

subsequent data is aligned on a fixed boundary.

The DP83848C has two basic 10BASE-T operational

modes:

— Half Duplex mode

— Full Duplex mode

Half Duplex Mode

In Half Duplex mode the DP83848C functions as a stan-

dard IEEE 802.3 10BASE-T transceiver supporting the

CSMA/CD protocol.

4.2.9 4B/5B Decoder

The code-group decoder functions as a look up table that

translates incoming 5B code-groups into 4B nibbles. The

code-group decoder first detects the J/K code-group pair

preceded by IDLE code-groups and replaces the J/K with

MAC preamble. Specifically, the J/K 10-bit code-group pair

is replaced by the nibble pair (0101 0101). All subsequent

Full Duplex Mode

In Full Duplex mode the DP83848C is capable of simulta-

5B code-groups are converted to the corresponding 4B neously transmitting and receiving without asserting the

nibbles for the duration of the entire packet. This conver- collision signal. The DP83848C's 10 Mb/s ENDEC is

sion ceases upon the detection of the T/R code-group pair

denoting the End of Stream Delimiter (ESD) or with the

reception of a minimum of two IDLE code-groups.

designed to encode and decode simultaneously.

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30

4.3.2 Smart Squelch

within 150 ns. Finally the signal must again exceed the

original squelch level within a 150 ns to ensure that the

input waveform will not be rejected. This checking proce-

dure results in the loss of typically three preamble bits at

the beginning of each packet.

The smart squelch is responsible for determining when

valid data is present on the differential receive inputs. The

DP83848C implements an intelligent receive squelch to

ensure that impulse noise on the receive inputs will not be

mistaken for a valid signal. Smart squelch operation is

independent of the 10BASE-T operational mode.

Only after all these conditions have been satisfied will a

control signal be generated to indicate to the remainder of

the circuitry that valid data is present. At this time, the

smart squelch circuitry is reset.

The squelch circuitry employs a combination of amplitude

and timing measurements (as specified in the IEEE 802.3

10BSE-T standard) to determine the validity of data on the

twisted pair inputs (refer to Figure 10).

Valid data is considered to be present until the squelch

level has not been generated for a time longer than 150 ns,

indicating the End of Packet. Once good data has been

detected, the squelch levels are reduced to minimize the

effect of noise causing premature End of Packet detection.

The signal at the start of a packet is checked by the smart

squelch and any pulses not exceeding the squelch level

(either positive or negative, depending upon polarity) will

be rejected. Once this first squelch level is overcome cor-

rectly, the opposite squelch level must then be exceeded

<150 ns

>150 ns

<150 ns

V

SQ+

V

SQ+(reduced)

V

SQ-(reduced)

V

SQ-

end of packet

start of packet

Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation

4.3.3 Collision Detection and SQE

4.3.4 Carrier Sense

When in Half Duplex, a 10BASE-T collision is detected Carrier Sense (CRS) may be asserted due to receive activ-

when the receive and transmit channels are active simulta- ity once valid data is detected via the squelch function.

neously. Collisions are reported by the COL signal on the

For 10 Mb/s Half Duplex operation, CRS is asserted during

MII. Collisions are also reported when a jabber condition is

either packet transmission or reception.

detected.

For 10 Mb/s Full Duplex operation, CRS is asserted only

The COL signal remains set for the duration of the collision.

during receive activity.

If the PHY is receiving when a collision is detected it is

CRS is deasserted following an end of packet.

reported immediately (through the COL pin).

When heartbeat is enabled, approximately 1 µs after the

transmission of each packet, a Signal Quality Error (SQE)

signal of approximately 10-bit times is generated to indi-

cate successful transmission. SQE is reported as a pulse

on the COL signal of the MII.

4.3.5 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as defined in the

IEEE 802.3 10BASE-T standard. Each link pulse is nomi-

nally 100 ns in duration and transmitted every 16 ms in the

absence of transmit data.

The SQE test is inhibited when the PHY is set in full duplex

mode. SQE can also be inhibited by setting the

HEARTBEAT_DIS bit in the 10BTSCR register.

Link pulses are used to check the integrity of the connec-

tion with the remote end. If valid link pulses are not

received, the link detector disables the 10BASE-T twisted

pair transmitter, receiver and collision detection functions.

When

the

link

integrity

function

is

disabled

(FORCE_LINK_10 of the 10BTSCR register), a good link is

forced and the 10BASE-T transceiver will operate regard-

less of the presence of link pulses.

31

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4.3.6 Jabber Function

4.3.8 Transmit and Receive Filtering

The jabber function monitors the DP83848C's output and External 10BASE-T filters are not required when using the

disables the transmitter if it attempts to transmit a packet of DP83848C, as the required signal conditioning is inte-

longer than legal size. A jabber timer monitors the transmit- grated into the device.

ter and disables the transmission if the transmitter is active

for approximately 85 ms.

Only isolation transformers and impedance matching resis-

tors are required for the 10BASE-T transmit and receive

Once disabled by the Jabber function, the transmitter stays interface. The internal transmit filtering ensures that all the

disabled for the entire time that the ENDEC module's inter- harmonics in the transmit signal are attenuated by at least

nal transmit enable is asserted. This signal has to be de- 30 dB.

asserted for approximately 500 ms (the “unjab” time)

before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

4.3.9 Transmitter

The encoder begins operation when the Transmit Enable

input (TX_EN) goes high and converts NRZ data to pre-

emphasized Manchester data for the transceiver. For the

duration of TX_EN, the serialized Transmit Data (TXD) is

encoded for the transmit-driver pair (PMD Output Pair).

TXD must be valid on the rising edge of Transmit Clock

(TX_CLK). Transmission ends when TX_EN deasserts.

The last transition is always positive; it occurs at the center

of the bit cell if the last bit is a one, or at the end of the bit

cell if the last bit is a zero.

4.3.7 Automatic Link Polarity Detection and Correction

The DP83848C's 10BASE-T transceiver module incorpo-

rates an automatic link polarity detection circuit. When

three consecutive inverted link pulses are received, bad

polarity is reported.

A polarity reversal can be caused by a wiring error at either

end of the cable, usually at the Main Distribution Frame

(MDF) or patch panel in the wiring closet.

The bad polarity condition is latched in the 10BTSCR regis-

ter. The DP83848C's 10BASE-T transceiver module cor-

rects for this error internally and will continue to decode

received data correctly. This eliminates the need to correct

the wiring error immediately.

4.3.10 Receiver

The decoder detects the end of a frame when no additional

mid-bit transitions are detected. Within one and a half bit

times after the last bit, carrier sense is de-asserted.

Receive clock stays active for five more bit times after CRS

goes low, to guarantee the receive timings of the controller.

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32

5.0 Design Guidelines

5.1 TPI Network Circuit

Pulse H1102

Pulse H2019

Pulse J0011D21

Pulse J0011D21B

Figure 11 shows the recommended circuit for a 10/100

Mb/s twisted pair interface. To the right is a partial list of

recommended transformers. It is important that the user

realize that variations with PCB and component character-

istics requires that the application be tested to ensure that

the circuit meets the requirements of the intended applica-

tion.

Vdd

RD-

Vdd

COMMON MODE CHOKES

MAY BE REQUIRED.

49.9Ω

0.1µF

1:1

49.9

Ω

RD+

TD-

RD-

0.1µF*

RD+

TD-

TD+

Vdd

RJ45

T1

49.9Ω

1:1

0.1µF

NOTE: CENTER TAP IS PULLED TO VDD

49.9

Ω

*PLACE CAPACITORS CLOSE TO THE

TRANSFORMER CENTER TAPS

TD+

All values are typical and are +/- 1%

PLACE RESISTORS AND

CAPACITORS CLOSE TO

THE DEVICE.

Figure 11. 10/100 Mb/s Twisted Pair Interface

33

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capacitor values will vary with the crystal vendors; check

with the vendor for the recommended loads.

5.2 ESD Protection

Typically, ESD precautions are predominantly in effect

when handling the devices or board before being installed

in a system. In those cases, strict handling procedures

need be implemented during the manufacturing process to

greatly reduce the occurrences of catastrophic ESD

events. After the system is assembled, internal compo-

nents are less sensitive from ESD events.

The oscillator circuit is designed to drive a parallel reso-

nance AT cut crystal with a minimum drive level of 100µW

and a maximum of 500µW. If a crystal is specified for a

lower drive level, a current limiting resistor should be

placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the

requirements for the crystal are not known, C_L1and C_L2

should be set at 33 pF, and R₁should be set at 0Ω.

See Section 8.0 for ESD rating.

Specification for 25 MHz crystal are listed in Table 9.

5.3 Clock In (X1) Requirements

The DP83848C supports an external CMOS level oscillator

source or a crystal resonator device.

X2

X1

Oscillator

If an external clock source is used, X1 should be tied to the

clock source and X2 should be left floating.

R₁

Specifications for CMOS oscillators: 25 MHz in MII Mode

and 50 MHz in RMII Mode are listed in Table 6 and Table 8.

C_L1

C_L2

Crystal

A 25 MHz, parallel, 20 pF load crystal resonator should be

used if a crystal source is desired. Figure 12 shows a typi-

cal connection for a crystal resonator circuit. The load

Figure 12. Crystal Oscillator Circuit

Table 6. 25

Table 7. 25 MHz Oscillator Specification

Parameter

Frequency

Tolerance

Frequency

Stability

Min

Typ

Max

+50

Units

MHz

ppm

Condition

Operational Temperature

1 year aging

25

ppm

Rise / Fall Time

Jitter

6

nsec

psec

20% - 80%

Short term

800¹

Jitter

psec

Long term

Symmetry

40%

60%

Duty Cycle

¹This limit is provided as a guideline for component selection and to guaranteed by production testing.

Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.

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34

Table 8. 50 MHz Oscillator Specification

Parameter

Frequency

Tolerance

Frequency

Stability

Min

Typ

Max

+50

Units

MHz

ppm

Condition

50

Operational

Temperature

ppm

Operational

Temperature

Rise / Fall Time

Jitter

6

nsec

psec

20% - 80%

Short term

800¹

Jitter

psec

Long term

Duty Cycle

Symmetry

40%

60%

¹This limit is provided as a guideline for component selection and to guaranteed by production testing.

Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.

Table 9. 25 MHz Crystal Specification

Parameter

Frequency

Min

Typ

Max

+50

40

Units

MHz

ppm

Condition

25

Frequency

Operational Tem-

perature

Tolerance

Frequency

ppm

pF

1 year aging

Stability

Load Capacitance

25

5.4 Power Feedback Circuit

To ensure correct operation for the DP83848C, parallel

caps with values of 10 µF (Tantalum) and 0.1 µF should be

placed close to pin 23 (PFBOUT) of the device.

5.5 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed

on pin 7 of the device. By default, this pin functions as a

power down input and the interrupt function is disabled.

Setting bit 0 (INT_OE) of MICR (0x11h) will configure the

pin as an active low interrupt output.

Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected

to pin 23 (PFBOUT), each pin requires a small capacitor

(.1 µF). See Figure 13 below for proper connections.

5.5.1 Power Down Control Mode

Pin 23 (PFBOUT

)

The PWR_DOWN/INT pin can be asserted low to put the

device in a Power Down mode. This is equivalent to setting

bit 11 (Power Down) in the Basic Mode Control Register,

BMCR (0x00h). An external control signal can be used to

drive the pin low, overcoming the weak internal pull-up

resistor. Alternatively, the device can be configured to ini-

tialize into a Power Down state by use of an external pull-

down resistor on the PWR_DOWN/INT pin. Since the

device will still respond to management register accesses,

setting the INT_OE bit in the MICR register will disable the

PWR_DOWN/INT input, allowing the device to exit the

Power Down state.

.1 µF

10 µF

+

-

Pin 18 (PFBIN1)

Pin 37 (PFBIN2)

.1 µF

Figure 13. Power Feeback Connection

35

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5.5.2 Interrupt Mechanisms

When PWR_DOWN/INT pin asserts low, user would read

the MISR register to see if the ED_INT or LINK_INT bits

are set, i.e. which source caused the interrupt. After read-

ing the MISR, the interrupt bits should clear and the

PWR_DOWN/INT pin will deassert.

The interrupt function is controlled via register access. All

interrupt sources are disabled by default. Setting bit 1

(INTEN) of MICR (0x11h) will enable interrupts to be out-

put, dependent on the interrupt mask set in the lower byte

of the MISR (0x12h). The PWR_DOWN/INT pin is asyn-

chronously asserted low when an interrupt condition

occurs. The source of the interrupt can be determined by

reading the upper byte of the MISR. One or more bits in the

MISR will be set, denoting all currently pending interrupts.

Reading of the MISR clears ALL pending interrupts.

5.6 Energy Detect Mode

When Energy Detect is enabled and there is no activity on

the cable, the DP83848C will remain in a low power mode

while monitoring the transmission line. Activity on the line

will cause the DP83848C to go through a normal power up

sequence. Regardless of cable activity, the DP83848C will

occasionally wake up the transmitter to put ED pulses on

the line, but will otherwise draw as little power as possible.

Energy detect functionality is controlled via register Energy

Detect Control (EDCR), address 0x1Dh.

Example: To generate an interrupt on a change of link sta-

tus or on a change of energy detect power state, the steps

would be:

— Write 0003h to MICR to set INTEN and INT_OE

— Write 0060h to MISR to set ED_INT_EN and

LINK_INT_EN

— Monitor PWR_DOWN/INT pin

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36

figuration values will be re-latched into the device (similar

to the power-up/reset operation).

6.0 Reset Operation

The DP83848C includes an internal power-on reset (POR)

function and does not need to be explicitly reset for normal

operation after power up. If required during normal opera-

tion, the device can be reset by a hardware or software

reset.

6.2 Software Reset

A software reset is accomplished by setting the reset bit

(bit 15) of the Basic Mode Control Register (BMCR). The

period from the point in time when the reset bit is set to the

point in time when software reset has concluded is approx-

imately 1 µs.

6.1 Hardware Reset

The software reset will reset the device such that all regis-

ters will be reset to default values and the hardware config-

uration values will be maintained. Software driver code

must wait 3 µs following a software reset before allowing

further serial MII operations with the DP83848C.

A hardware reset is accomplished by applying a low pulse

(TTL level), with a duration of at least 1 µs, to the

RESET_N. This will reset the device such that all registers

will be reinitialized to default values and the hardware con-

37

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7.0 Register Block

Table 10. Register Map

Tag

Offset

Access

Description

Hex

00h

Decimal

0

1

RW

RO

RW

BMCR

Basic Mode Control Register

01h

BMSR

Basic Mode Status Register

02h

2

PHYIDR1

PHYIDR2

ANAR

PHY Identifier Register #1

03h

3

PHY Identifier Register #2

04h

4

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register (Base Page)

Auto-Negotiation Link Partner Ability Register (Next Page)

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page TX

05h

5

ANLPAR

ANLPARNP

ANER

05h

5

06h

6

07h

7

ANNPTR

RESERVED

08h-Fh

8-15

RESERVED

Extended Registers

10h

11h

16

17

RO

RW

RO

RW

RO

RW

PHYSTS

MICR

PHY Status Register

MII Interrupt Control Register

MII Interrupt Status Register

RESERVED

12h

18

MISR

13h

19

RESERVED

FCSCR

RECR

14h

20

False Carrier Sense Counter Register

Receive Error Counter Register

PCS Sub-Layer Configuration and Status Register

RMII and Bypass Register

LED Direct Control Register

PHY Control Register

15h

21

16h

22

PCSR

17h

23

RBR

18h

24

LEDCR

PHYCR

10BTSCR

CDCTRL1

RESERVED

EDCR

19h

25

1Ah

1Bh

1Ch

1Dh

1Eh-1Fh

26

10Base-T Status/Control Register

CD Test Control Register and BIST Extensions Register

RESERVED

27

28

29

Energy Detect Control Register

RESERVED

30-31

RESERVED

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38

7.1 Register Definition

In the register definitions under the ‘Default’ heading, the following definitions hold true:

— RW=Read Write access

— SC=Register sets on event occurrence and Self-Clears when event ends

— RW/SC =Read Write access/Self Clearing bit

— RO=Read Only access

— COR = Clear on Read

— RO/COR=Read Only, Clear on Read

— RO/P=Read Only, Permanently set to a default value

— LL=Latched Low and held until read, based upon the occurrence of the corresponding event

— LH=Latched High and held until read, based upon the occurrence of the corresponding event

41

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7.1.1 Basic Mode Control Register (BMCR)

Table 12. Basic Mode Control Register (BMCR), address 0x00

Bit

Bit Name

Default

Description

15

Reset

0, RW/SC

Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

14

Loopback

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MII transmit data to be routed to the MII

receive data path.

Setting this bit may cause the descrambler to lose synchronization and

produce a 500 µs “dead time” before any valid data will appear at the

MII receive outputs.

13

12

Speed Selection

Strap, RW

Speed Select:

When auto-negotiation is disabled writing to this bit allows the port

speed to be selected.

1 = 100 Mb/s.

0 = 10 Mb/s.

Auto-Negotiation

Enable

Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ig-

nored when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed

and duplex mode.

11

Power Down

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is en-

abled during a power down condition. This bit is OR’d with the input

from the PWR_DOWN/INT pin. When the active low

PWR_DOWN/INT pin is asserted, this bit will be set.

10

9

Isolate

0, RW

Isolate:

1 = Isolates the Port from the MII with the exception of the serial man-

agement.

0 = Normal operation.

Restart Auto-

Negotiation

0, RW/SC

Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation pro-

cess. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This

bit is self-clearing and will return a value of 1 until Auto-Negotiation is

initiated, whereupon it will self-clear. Operation of the Auto-Negotiation

process is not affected by the management entity clearing this bit.

0 = Normal operation.

8

Duplex Mode

Strap, RW

Duplex Mode:

When auto-negotiation is disabled writing to this bit allows the port Du-

plex capability to be selected.

1 = Full Duplex operation.

0 = Half Duplex operation.

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42

Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued)

Bit

Bit Name

Default

Description

7

Collision Test

0, RW

Collision Test:

1 = Collision test enabled.

0 = Normal operation.

When set, this bit will cause the COL signal to be asserted in response

to the assertion of TX_EN within 512-bit times. The COL signal will be

de-asserted within 4-bit times in response to the de-assertion of

TX_EN.

6:0

RESERVED

0, RO

RESERVED: Write ignored, read as 0.

43

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7.1.2 Basic Mode Status Register (BMSR)

Table 13. Basic Mode Status Register (BMSR), address 0x01

Bit

Bit Name

Default

Description

15

100BASE-T4

0, RO/P

100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

100BASE-TX Full Duplex Capable:

14

13

12

11

100BASE-TX

Full Duplex

100BASE-TX

Half Duplex

10BASE-T

1, RO/P

1 = Device able to perform 100BASE-TX in full duplex mode.

100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

10BASE-T Full Duplex Capable:

Full Duplex

10BASE-T

1 = Device able to perform 10BASE-T in full duplex mode.

10BASE-T Half Duplex Capable:

Half Duplex

RESERVED

MF Preamble

Suppression

1 = Device able to perform 10BASE-T in half duplex mode.

RESERVED: Write as 0, read as 0.

10:7

6

0, RO

1, RO/P

Preamble suppression Capable:

1 = Device able to perform management transaction with preamble

suppressed, 32-bits of preamble needed only once after reset, invalid

opcode or invalid turnaround.

0 = Normal management operation.

Auto-Negotiation Complete:

5

4

Auto-Negotiation Com-

plete

0, RO

1 = Auto-Negotiation process complete.

0 = Auto-Negotiation process not complete.

Remote Fault

0, RO/LH Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset).

Fault criteria: Far End Fault Indication or notification from Link Part-

ner of Remote Fault.

0 = No remote fault condition detected.

Auto Negotiation Ability:

3

2

Auto-Negotiation Abili-

ty

1, RO/P

1 = Device is able to perform Auto-Negotiation.

0 = Device is not able to perform Auto-Negotiation.

Link Status

0, RO/LL Link Status:

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

The criteria for link validity is implementation specific. The occurrence

of a link failure condition will causes the Link Status bit to clear. Once

cleared, this bit may only be set by establishing a good link condition

and a read via the management interface.

1

0

Jabber Detect

0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the occur-

rence of a jabber condition causes it to set until it is cleared by a read

to this register by the management interface or by a reset.

Extended Capability

1, RO/P

Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

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44

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848C. The Identifier consists of a

concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-

ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended

to support network management. National's IEEE assigned OUI is 080017h.

7.1.3 PHY Identifier Register #1 (PHYIDR1)

Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02

Bit

Bit Name

Default

Description

15:0

OUI_MSB

<0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are

0000>, RO/P

stored in bits 15 to 0 of this register. The most significant two bits

of the OUI are ignored (the IEEE standard refers to these as bits 1

and 2).

7.1.4 PHY Identifier Register #2 (PHYIDR2)

Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03

Bit

Bit Name

Default

<0101 11>, RO/P OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10

Description

15:10

OUI_LSB

of this register respectively.

9:4

3:0

VNDR_MDL

MDL_REV

<00 1001>, RO/P Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4

(most significant bit to bit 9).

<0000>, RO/P

Model Revision Number:

Four bits of the vendor model revision number are mapped from

bits 3 to 0 (most significant bit to bit 3). This field will be incremented

for all major device changes.

7.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-

tiation.

Table 16. Negotiation Advertisement Register (ANAR), address 0x04

Bit

Bit Name

Default

Description

15

NP

0, RW

Next Page Indication:

0 = Next Page Transfer not desired.

1 = Next Page Transfer desired.

14

13

RESERVED

RF

0, RO/P

0, RW

RESERVED by IEEE: Writes ignored, Read as 0.

Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.

12

RESERVED

0, RW

RESERVED for Future IEEE use: Write as 0, Read as 0

45

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Table 16. Negotiation Advertisement Register (ANAR), address 0x04 (Continued)

Bit

Bit Name

Default

Description

11

ASM_DIR

0, RW

Asymmetric PAUSE Support for Full Duplex Links:

The ASM_DIR bit indicates that asymmetric PAUSE is supported.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu-

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control sublayer and the pause function as specified in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.

10

PAUSE

0, RW

PAUSE Support for Full Duplex Links:

The PAUSE bit indicates that the device is capable of providing the

symmetric PAUSE functions as defined in Annex 31B.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu-

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control sublayer and the pause function as specified in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.

100BASE-T4 Support:

9

8

T4

TX_FD

TX

0, RO/P

1= 100BASE-T4 is supported by the local device.

0 = 100BASE-T4 not supported.

Strap, RW

100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

100BASE-TX Support:

7

1 = 100BASE-TX is supported by the local device.

0 = 100BASE-TX not supported.

6

10_FD

10

10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device.

0 = 10BASE-T Full Duplex not supported.

10BASE-T Support:

5

1 = 10BASE-T is supported by the local device.

0 = 10BASE-T not supported.

4:0

Selector

<00001>, RW Protocol Selection Bits:

These bits contain the binary encoded protocol selector supported

by this port. <00001> indicates that this device supports IEEE

802.3u.

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46

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content

changes after the successful auto-negotiation if Next-pages are supported.

Table 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05

Bit

Bit Name

Default

Description

15

NP

0, RO

Next Page Indication:

0 = Link Partner does not desire Next Page Transfer.

1 = Link Partner desires Next Page Transfer.

Acknowledge:

14

13

ACK

RF

0, RO

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts.

Remote Fault:

1 = Remote Fault indicated by Link Partner.

0 = No Remote Fault indicated by Link Partner.

RESERVED for Future IEEE use:

12

11

RESERVED

ASM_DIR

0, RO

Write as 0, read as 0.

ASYMMETRIC PAUSE:

1 = Asymmetric pause is supported by the Link Partner.

0 = Asymmetric pause is not supported by the Link Partner.

PAUSE:

10

9

PAUSE

T4

0, RO

1 = Pause function is supported by the Link Partner.

0 = Pause function is not supported by the Link Partner.

100BASE-T4 Support:

1 = 100BASE-T4 is supported by the Link Partner.

0 = 100BASE-T4 not supported by the Link Partner.

100BASE-TX Full Duplex Support:

8

TX_FD

TX

1 = 100BASE-TX Full Duplex is supported by the Link Partner.

0 = 100BASE-TX Full Duplex not supported by the Link Partner.

100BASE-TX Support:

7

1 = 100BASE-TX is supported by the Link Partner.

0 = 100BASE-TX not supported by the Link Partner.

10BASE-T Full Duplex Support:

6

10_FD

10

1 = 10BASE-T Full Duplex is supported by the Link Partner.

0 = 10BASE-T Full Duplex not supported by the Link Partner.

10BASE-T Support:

5

1 = 10BASE-T is supported by the Link Partner.

0 = 10BASE-T not supported by the Link Partner.

4:0

Selector

<0 0000>, RO Protocol Selection Bits:

Link Partner’s binary encoded protocol selector.

47

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7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)

Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05

Bit

Bit Name

Default

Description

15

NP

0, RO

Next Page Indication:

1 = Link Partner desires Next Page Transfer.

0 = Link Partner does not desire Next Page Transfer.

Acknowledge:

14

ACK

0, RO

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts. Software should not at-

tempt to write to this bit.

13

12

MP

0, RO

Message Page:

1 = Message Page.

0 = Unformatted Page.

Acknowledge 2:

ACK2

1 = Link Partner does have the ability to comply to next page mes-

sage.

0 = Link Partner does not have the ability to comply to next page

message.

11

Toggle

CODE

0, RO

Toggle:

1 = Previous value of the transmitted Link Code word equalled 0.

0 = Previous value of the transmitted Link Code word equalled 1.

10:0

<00000000000>, Code:

RO

This field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a “Message Page,” as defined in annex 28C of

Clause 28. Otherwise, the code shall be interpreted as an “Unfor-

matted Page,” and the interpretation is application specific.

7.1.8 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06

Bit

15:5

4

Bit Name

RESERVED

PDF

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0.

Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function.

0 = A fault has not been detected.

3

LP_NP_ABLE

0, RO

Link Partner Next Page Able:

1 = Link Partner does support Next Page.

0 = Link Partner does not support Next Page.

Next Page Able:

2

1

NP_ABLE

PAGE_RX

1, RO/P

1 = Indicates local device is able to send additional “Next Pages”.

Link Code Word Page Received:

0, RO/COR

1 = Link Code Word has been received, cleared on a read.

0 = Link Code Word has not been received.

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48

Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06 (Continued)

Bit

Bit Name

Default

Description

0

LP_AN_ABLE

0, RO

Link Partner Auto-Negotiation Able:

1 = indicates that the Link Partner supports Auto-Negotiation.

0 = indicates that the Link Partner does not support Auto-Negotia-

tion.

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 20. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07

Bit

Bit Name

Default

Description

15

NP

0, RW

Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired.

RESERVED: Writes ignored, read as 0.

Message Page:

14

13

RESERVED

MP

0, RO

1, RW

1 = Message Page.

0 = Unformatted Page.

12

11

ACK2

0, RW

0, RO

Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by the next page function to indicate that Lo-

cal Device has the ability to comply with the message received.

TOG_TX

Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word

was 0.

0 = Value of toggle bit in previously transmitted Link Code Word

was 1.

Toggle is used by the Arbitration function within Auto-Negotiation

to ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Tog-

gle bit in the previously exchanged Link Code Word.

10:0

CODE

<00000000001>, This field represents the code field of the next page transmission.

RW

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformat-

ted Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined

in Annex 28C of IEEE 802.3u.

49

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7.2 Extended Registers

7.2.1 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed information.

Table 21. PHY Status Register (PHYSTS), address 0x10

Bit

15

14

Bit Name

RESERVED

MDI-X mode

Default

0, RO

Description

RESERVED: Write ignored, read as 0.

MDI-X mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and

FORCE_MDIX bits in the PHYCR register. When MDIX is en-

abled, but not forced, this bit will update dynamically as the

Auto-MDIX algorithm swaps between MDI and MDI-X configu-

rations.

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

Receive Error Latch:

13

12

Receive Error Latch

Polarity Status

0, RO/LH

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 0x15, Page 0).

0 = No receive error event has occurred.

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

11

False Carrier Sense

Latch

0, RO/LH

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (ad-

dress 0x14).

0 = No False Carrier event has occurred.

100Base-TX unconditional Signal Detect from PMD.

100Base-TX Descrambler Lock from PMD.

Link Code Word Page Received:

10

9

Signal Detect

Descrambler Lock

Page Received

0, RO/LL

0, RO

8

This is a duplicate of the Page Received bit in the ANER register,

but this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on

read of the ANER (address 0x06, bit 1).

0 = Link Code Word Page has not been received.

7

6

MII Interrupt

0, RO

MII Interrupt Pending:

1 = Indicates that an internal interrupt is pending. Interrupt source

can be determined by reading the MISR Register (0x12h). Reading

the MISR will clear the Interrupt.

0= No interrupt pending.

Remote Fault

Remote Fault:

1 = Remote Fault condition detected (cleared on read of BMSR (ad-

dress 01h) register or by reset). Fault criteria: notification from Link

Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected.

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50

Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued)

Bit

Bit Name

Default

Description

5

Jabber Detect

0, RO

Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a duplicate of the Jabber Detect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

4

3

2

Auto-Neg Complete

Loopback Status

Duplex Status

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.

Loopback:

1 = Loopback enabled.

0 = Normal operation.

Duplex:

This bit indicates duplex status and is determined from Auto-Nego-

tiation or Forced Modes.

1 = Full duplex mode.

0 = Half duplex mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

1

Speed Status

0, RO

Speed10:

This bit indicates the status of the speed and is determined from

Auto-Negotiation or Forced Modes.

1 = 10 Mb/s mode.

0 = 100 Mb/s mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

0

Link Status

0, RO

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will not be cleared upon a read of the PHYSTS regis-

ter.

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established.

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7.2.2 MII Interrupt Control Register (MICR)

This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy

Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or

any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Inter-

rupt Status and Event Control Register (MISR).

Table 22. MII Interrupt Control Register (MICR), address 0x11

Bit

15:3

2

Bit Name

Reserved

TINT

Default

0, RO

Description

Reserved: Write ignored, Read as 0

Test Interrupt:

0, RW

Forces the PHY to generate an interrupt to facilitate interrupt test-

ing. Interrupts will continue to be generated as long as this bit re-

mains set.

1 = Generate an interrupt

0 = Do not generate interrupt

Interrupt Enable:

1

0

INTEN

0, RW

Enable interrupt dependent on the event enables in the MISR reg-

ister.

1 = Enable event based interrupts

0 = Disable event based interrupts

Interrupt Output Enable:

INT_OE

Enable interrupt events to signal via the PWR_DOWN/INT pin by

configuring the PWR_DOWN/INT pin as an output.

1 = PWR_DOWN/INT is an Interrupt Output

0 = PWR_DOWN/INT is a Power Down Input

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52

7.2.3 MII Interrupt Status and Misc. Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since the last read of

this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt

will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indi-

cations in this register will be set even if the interrupt is not enabled

Table 23. MII Interrupt Status and Misc. Control Register (MISR), address 0x12

15

14

Reserved

ED_INT

0, RO

RESERVED: Writes ignored, Read as 0

0, RO/COR

Energy Detect interrupt:

1 = Energy detect interrupt is pending and is cleared by the current

read.

0 = No energy detect interrupt pending.

13

12

11

10

9

LINK_INT

SPD_INT

DUP_INT

ANC_INT

FHF_INT

RHF_INT

0, RO/COR

Change of Link Status interrupt:

1 = Change of link status interrupt is pending and is cleared by the

current read.

0 = No change of link status interrupt pending.

Change of speed status interrupt:

1 = Speed status change interrupt is pending and is cleared by the

current read.

0 = No speed status change interrupt pending.

Change of duplex status interrupt:

1 = Duplex status change interrupt is pending and is cleared by

the current read.

0 = No duplex status change interrupt pending.

Auto-Negotiation Complete interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared

by the current read.

0 = No Auto-negotiation complete interrupt pending.

False Carrier Counter half-full interrupt:

1 = False carrier counter half-full interrupt is pending and is

cleared by the current read.

0 = No false carrier counter half-full interrupt pending.

8

Receive Error Counter half-full interrupt:

1 = Receive error counter half-full interrupt is pending and is

cleared by the current read.

0 = No receive error carrier counter half-full interrupt pending.

RESERVED: Writes ignored, Read as 0

7

6

5

4

3

2

1

0

RESERVED

ED_INT_EN

0, RO

0, RW

Enable Interrupt on energy detect event

LINK_INT_EN

SPD_INT_EN

DUP_INT_EN

ANC_INT_EN

FHF_INT_EN

RHF_INT_EN

Enable Interrupt on change of link status

Enable Interrupt on change of speed status

Enable Interrupt on change of duplex status

Enable Interrupt on Auto-negotiation complete event

Enable Interrupt on False Carrier Counter Register half-full event

Enable Interrupt on Receive Error Counter Register half-full event

53

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7.2.4 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU managed object

class of Clause 30 of the IEEE 802.3u specification.

Table 24. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit

15:8

7:0

Bit Name

RESERVED

FCSCNT[7:0]

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0

False Carrier Event Counter:

0, RO / COR

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

7.2.5 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY man-

aged object class of Clause 30 of the IEEE 802.3u specification.

Table 25. Receiver Error Counter Register (RECR), address 0x15

Bit

15:8

7:0

Bit Name

RESERVED

RXERCNT[7:0]

Default

0, RO

Description

RESERVED: Writes ignored, Read as 0

RX_ER Counter:

0, RO / COR

When a valid carrier is present and there is at least one occurrence

of an invalid data symbol, this 8-bit counter increments for each re-

ceive error detected. This event can increment only once per valid

carrier event. If a collision is present, the attribute will not incre-

ment. The counter sticks when it reaches its max count.

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54

7.2.6 100 Mb/s PCS Configuration and Status Register (PCSR)

Table 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16

Bit

15:13

12

Bit Name

RESERVED

Default

<00>, RO

0

Description

RESERVED: Writes ignored, Read as 0.

RESERVED:

Must be zero.

11

10

RESERVED

TQ_EN

0

RESERVED:

Must be zero.

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.

0 = Normal Transmit Mode.

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.

0 = Normal SD operation.

Signal Detect Option:

0, RW

9

8

7

SD FORCE PMA

SD_OPTION

0, RW

1, RW

0, RW

1 = Enhanced signal detect algorithm.

0 = Reduced signal detect algorithm.

Descrambler Timeout:

DESC_TIME

Increase the descrambler timeout. When set this should allow the

device to receive larger packets (>9k bytes) without loss of syn-

chronization.

1 = 2ms

0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)

RESERVED:

6

5

RESERVED

0

Must be zero.

FORCE_100_OK

0, RW

Force 100Mb/s Good Link:

1 = Forces 100Mb/s Good Link.

0 = Normal 100Mb/s operation.

RESERVED:

4

3

2

RESERVED

0

Must be zero.

RESERVED:

Must be zero.

NRZI_BYPASS

0, RW

NRZI Bypass Enable:

1 = NRZI Bypass Enabled.

0 = NRZI Bypass Disabled.

RESERVED:

1

0

RESERVED

0

Must be zero.

RESERVED:

Must be zero.

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7.2.7 RMII and Bypass Register (RBR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.

Table 27. RMII and Bypass Register (RBR), addresses 0x17

Bit

15:6

5

Bit Name

RESERVED

RMII_MODE

Default

0, RO

Description

RESERVED: Writes ignored, read as 0.

Reduced MII Mode:

Strap, RW

0 = Standard MII Mode

1 = Reduced MII Mode

4

RMII_REV1_0

0, RW

Reduce MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet

to indicate deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data

is transferred. CRS_DV will not toggle at the end of a packet.

3

2

RX_OVF_STS

RX_UNF_STS

ELAST_BUF[1:0]

0, RO

RX FIFO Over Flow Status:

0 = Normal

1 = Overflow detected

RX FIFO Under Flow Status:

0 = Normal

1 = Underflow detected

1:0

01, RW

Receive Elasticity Buffer. This field controls the Receive Elastic-

ity Buffer which allows for frequency variation tolerance between

the 50MHz RMII clock and the recovered data. The following val-

ues indicate the tolerance in bits for a single packet. The minimum

setting allows for standard Ethernet frame sizes at +/-50ppm accu-

racy for both RMII and Receive clocks. For greater frequency tol-

erance the packet lengths may be scaled (i.e. for +/-100ppm, the

packet lengths need to be divided by 2).

00 = 14 bit tolerance (up to 16800 byte packets)

01 = 2 bit tolerance (up to 2400 byte packets)

10 = 6 bit tolerance (up to 7200 byte packets)

11 = 10 bit tolerance (up to 12000 byte packets)

7.2.8 LED Direct Control Register (LEDCR)

This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.

Table 28. LED Direct Control Register (LEDCR), address 0x18

Bit

15:6

5

Bit Name

RESERVED

DRV_SPDLED

Default

0, RO

Description

RESERVED: Writes ignored, read as 0.

1 = Drive value of SPDLED bit onto LED_SPD output

0 = Normal operation

0, RW

4

3

DRV_LNKLED

DRV_ACTLED

0, RW

1 = Drive value of LNKLED bit onto LED_LNK output

0 = Normal operation

1 = Drive value of ACTLED bit onto LED_ACT/COL output

0 = Normal operation

2

1

0

SPDLED

LNKLED

ACTLED

0, RW

Value to force on LED_SPD output

Value to force on LED_LNK output

Value to force on LED_ACT/COL output

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56

7.2.9 PHY Control Register (PHYCR)

Table 29. PHY Control Register (PHYCR), address 0x19

Bit

Bit Name

Default

Description

15

MDIX_EN

Strap, RW

Auto-MDIX Enable:

1 = Enable Auto-neg Auto-MDIX capability.

0 = Disable Auto-neg Auto-MDIX capability.

The Auto-MDIX algorithm requires that the Auto-Negotiation En-

able bit in the BMCR register to be set. If Auto-Negotiation is not

enabled, Auto-MDIX should be disabled as well.

14

13

FORCE_MDIX

PAUSE_RX

0, RW

0, RO

Force MDIX:

1 = Force MDI pairs to cross.

(Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation.

Pause Receive Negotiated:

Indicates that pause receive should be enabled in the MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B

Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-

est Common Denominator is a full duplex technology.

12

11

PAUSE_TX

BIST_FE

0, RO

Pause Transmit Negotiated:

Indicates that pause transmit should be enabled in the MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B

Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-

est Common Denominator is a full duplex technology.

0, RW/SC

BIST Force Error:

1 = Force BIST Error.

0 = Normal operation.

This bit forces a single error, and is self clearing.

BIST Sequence select:

1 = PSR15 selected.

10

9

PSR_15

0, RW

0 = PSR9 selected.

BIST_STATUS

0, LL/RO

BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared when BIST is stopped.

For a count number of BIST errors, see the BIST Error Count in the

CDCTRL1 register.

8

7

BIST_START

BP_STRETCH

0, RW

BIST Start:

1 = BIST start.

0 = BIST stop.

Bypass LED Stretching:

This will bypass the LED stretching and the LEDs will reflect the in-

ternal value.

1 = Bypass LED stretching.

0 = Normal operation.

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Table 29. PHY Control Register (PHYCR), address 0x19 (Continued)

Bit

6

Bit Name

Default

0, RW

Description

LED_CNFG[1]

LED_CNFG[0]

LEDs Configuration

5

LED_CNFG[1]

LED_ CNFG[0]

Mode Description

Mode 1

Strap, RW

Don’t care

1

0

1

Mode 2

Mode 3

In Mode 1, LEDs are configured as follows:

LED_LINK = ON for Good Link, OFF for No Link

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Activity, OFF for No Activity

In Mode 2, LEDs are configured as follows:

LED_LINK = ON for good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Collision, OFF for No Collision

Full Duplex, OFF for Half Duplex

In Mode 3, LEDs are configured as follows:

LED_LINK = ON for Good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex

PHY Address: PHY address for port.

4:0

PHYADDR[4:0]

Strap, RW

7.2.10 10Base-T Status/Control Register (10BTSCR)

Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A

Bit

Bit Name

Default

Description

10Base-T Serial Mode (SNI)

15

10BT_SERIAL

Strap, RW

1 = Enables 10Base-T Serial Mode

0 = Normal Operation

Places 10 Mb/s transmit and receive functions in Serial Network

Interface (SNI) Mode of operation. Has no effect on 100 Mb/s

operation.

14:12

11:9

RESERVED

SQUELCH

0, RW

RESERVED:

Must be zero.

100, RW

Squelch Configuration:

Used to set the Squelch ‘ON’ threshold for the receiver.

Default Squelch ON is 330mV peak.

8

LOOPBACK_10_D

IS

0, RW

In half-duplex mode, default 10BASE-T operation loops Transmit

data to the Receive data in addition to transmitting the data on the

physical medium. This is for consistency with earlier 10BASE2 and

10BASE5 implementations which used a shared medium. Setting

this bit disables the loopback function.

This bit does not affect loopback due to setting BMCR[14].

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58

Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A

Bit

Bit Name

Default

Description

Normal Link Pulse Disable:

7

LP_DIS

0, RW

1 = Transmission of NLPs is disabled.

0 = Transmission of NLPs is enabled.

Force 10Mb Good Link:

1 = Forced Good 10Mb Link.

0 = Normal Link Status.

RESERVED:

6

FORCE_LINK_10

0, RW

5

4

RESERVED

POLARITY

0, RW

RO/LH

Must be zero.

10Mb Polarity Status:

This bit is a duplication of bit 12 in the PHYSTS register. Both bits

will be cleared upon a read of 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

RESERVED:

3

2

1

RESERVED

0, RW

1, RW

0, RW

Must be zero.

RESERVED:

Must be set to one.

HEARTBEAT_DIS

Heartbeat Disable: This bit only has influence in half-duplex 10Mb

mode.

1 = Heartbeat function disabled.

0 = Heartbeat function enabled.

When the device is operating at 100Mb or configured for full

duplex operation, this bit will be ignored - the heartbeat func-

tion is disabled.

0

JABBER_DIS

0, RW

Jabber Disable:

Applicable only in 10BASE-T.

1 = Jabber function disabled.

0 = Jabber function enabled.

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7.2.11 CD Test and BIST Extensions Register (CDCTRL1)

Table 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B

Bit

Bit Name

Default

Description

15:8

BIST_ERROR_CO

UNT

0, RO

BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This

value will reset when Packet BIST is restarted. The counter sticks

when it reaches its max count.

7:6

5

RESERVED

0, RW

RESERVED:

Must be zero.

BIST_CONT_MOD

E

Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing.

This is used in conjunction with the BIST controls in the PHYCR

Register (0x19h). For 10Mb operation, jabber function must be dis-

abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1.

4

CDPATTEN_10

RESERVED

0, RW

CD Pattern Enable for 10Mb:

1 = Enabled.

0 = Disabled.

3

2

0, RW

RESERVED:

Must be zero.

10MEG_PATT_GA

P

Defines gap between data or NLP test sequences:

1 = 15 µs.

0 = 10 µs.

1:0

CDPATTSEL[1:0]

00, RW

CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10MHz sine wave) for harmonic dis-

tortion testing.

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60

7.2.12 Energy Detect Control (EDCR)

Table 32. Energy Detect Control (EDCR), address 0x1D

Bit

Bit Name

Default

Description

15

ED_EN

0, RW

Energy Detect Enable:

Allow Energy Detect Mode.

When Energy Detect is enabled and Auto-Negotiation is disabled

via the BMCR register, Auto-MDIX should be disabled via the PHY-

CR register.

14

13

12

ED_AUTO_UP

ED_AUTO_DOWN

ED_MAN

1, RW

Energy Detect Automatic Power Up:

Automatically begin power up sequence when Energy Detect Data

Threshold value (EDCR[3:0]) is reached. Alternatively, device

could be powered up manually using the ED_MAN bit (ECDR[12]).

Energy Detect Automatic Power Down:

Automatically begin power down sequence when no energy is de-

tected. Alternatively, device could be powered down using the

ED_MAN bit (EDCR[12]).

0, RW/SC

Energy Detect Manual Power Up/Down:

Begin power up/down sequence when this bit is asserted. When

set, the Energy Detect algorithm will initiate a change of Energy De-

tect state regardless of threshold (error or data) and timer values.

In managed applications, this bit can be set after clearing the Ener-

gy Detect interrupt to control the timing of changing the power

state.

11

10

ED_BURST_DIS

ED_PWR_STATE

0, RW

0, RO

Energy Detect Bust Disable:

Disable bursting of energy detect data pulses. By default, Energy

Detect (ED) transmits a burst of 4 ED data pulses each time the CD

is powered up. When bursting is disabled, only a single ED data

pulse will be send each time the CD is powered up.

Energy Detect Power State:

Indicates current Energy Detect Power state. When set, Energy

Detect is in the powered up state. When cleared, Energy Detect is

in the powered down state. This bit is invalid when Energy Detect

is not enabled.

9

8

ED_ERR_MET

ED_DATA_MET

ED_ERR_COUNT

0, RO/COR

0001, RW

Energy Detect Error Threshold Met:

No action is automatically taken upon receipt of error events. This

bit is informational only and would be cleared on a read.

Energy Detect Data Threshold Met:

The number of data events that occurred met or surpassed the En-

ergy Detect Data Threshold. This bit is cleared on a read.

7:4

Energy Detect Error Threshold:

Threshold to determine the number of energy detect error events

that should cause the device to take action. Intended to allow aver-

aging of noise that may be on the line. Counter will reset after ap-

proximately 2 seconds without any energy detect data events.

3:0

ED_DATA_COUNT

0001, RW

Energy Detect Data Threshold:

Threshold to determine the number of energy detect events that

should cause the device to take actions. Intended to allow averag-

ing of noise that may be on the line. Counter will reset after approx-

imately 2 seconds without any energy detect data events.

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8.0 Electrical Specifications

Note: All parameters are guaranteed by test, statistical analysis or design.

Recommended Operating Conditions

Supply voltage (V_CC

Absolute Maximum Ratings

Supply Voltage (V_CC

)

3.3 Volts + .3V

)

-0.5 V to 4.2 V

-0.5V to V_CC+ 0.5V

Commercial - Ambient Temperature (T_A)

Power Dissipation (P_D)

DC Input Voltage (V_IN)

0 to 70 °C

267 mW

DC Output Voltage (V_OUT

)

-65^oC to 150°C

92 °C

Absolute maximum ratings are those values beyond which

the safety of the device cannot be guaranteed. They are

not meant to imply that the device should be operated at

these limits.

Storage Temperature (T_STG

)

Max case temp for T_A= 70°C

Max. die temperature (Tj)

150 °C

260 °C

Lead Temp. (TL)

(Soldering, 10 sec.)

ESD Rating

4.0 kV

(R_ZAP= 1.5k, C_ZAP= 100 pF)

Max

Units

Thermal Characteristic

Theta Junction to Case (T_jc)

28.7

°C / W

Theta Junction to Ambient (T_ja) degrees Celsius/Watt - No Airflow @ 1.0W

Note: This is done with a JEDEC (2 layer 2 oz CU.) thermal test board

83.6

°C / W

8.1 DC Specs

Symbol

I_IH

Pin Types

Parameter

Conditions

Min

Typ

Max

Units

I

Input High Current V_IN= V_CC

10

µA

I/O

I_IL

I

Input Low Current V_IN= GND

10

µA

I/O

V_OL

V_OH

I_OZ

O,

I/O

Output Low

Voltage

I_OL= 4 mA

I_OH= -4 mA

V_OUT= V_CC

0.4

V

O,

I/O

Output High

Voltage

Vcc - 0.5

0.95

V

I/O,

O

TRI-STATE

Leakage

+ 10

1.05

+ 2

µA

V_{TPTD_100}PMD Output 100M Transmit

Pair Voltage

1

V

V_TPTDsymPMD Output 100M Transmit

Pair Voltage Symmetry

%

V_{TPTD_10}

C_IN1

C_OUT1

SD_THon

PMD Output 10M Transmit

2.2

2.5

5

2.8

V

Pair

Voltage

I

CMOS Input

Capacitance

pF

O

CMOS Output

Capacitance

5

PMD Input

Pair

100BASE-TX

Signal detect turn-

on threshold

1000

mV diff pk-pk

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62

Symbol

Pin Types

Parameter

Conditions

Min

Typ

Max

Units

SD_THoff

PMD Input

Pair

100BASE-TX

Signal detect turn-

off threshold

200

mV diff pk-pk

V_TH1

I_dd100

I_dd10

I_dd

PMD Input

Pair

10BASE-T Re-

ceive Threshold

585

mV

mA

Supply

100BASE-TX

(Full Duplex)

81

92

14

10BASE-T

(Full Duplex)

Power Down

Mode

63

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8.2 AC Specs

8.2.1 Power Up Timing

Vcc

X1 clock

T2.1.1

Hardware

RESET_N

32 clocks

MDC

T2.1.2

Latch-In of Hardware

Configuration Pins

T2.1.3

input

output

Dual Function Pins

Become Enabled As Outputs

Parameter

Description

Post Power Up Stabilization

Notes

Min

Typ Max Units

T2.1.1

MDIO is pulled high for 32-bit serial man- 167

ms

time prior to MDC preamble for agement initialization

register accesses

X1 Clock must be stable for a min. of

167ms at power up.

T2.1.2

T2.1.3

Hardware Configuration Latch- Hardware Configuration Pins are de-

167

ms

in Time from power up

scribed in the Pin Description section

X1 Clock must be stable for a min. of

167ms at power up.

Hardware Configuration pins

transition to output drivers

50

ns

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64

8.2.2 Reset Timing

Vcc

X1 clock

T2.2.1

T2.2.4

Hardware

RESET_N

32 clocks

MDC

T2.2.2

Latch-In of Hardware

Configuration Pins

T2.2.3

input

output

Dual Function Pins

Become Enabled As Outputs

Parameter

Description

Notes

Min

Typ Max Units

T2.2.1

Post RESET Stabilization time MDIO is pulled high for 32-bit serial man-

prior to MDC preamble for reg- agement initialization

ister accesses

3

µs

T2.2.2

Hardware Configuration Latch- Hardware Configuration Pins are de-

in Time from the Deassertion scribed in the Pin Description section

of RESET (either soft or hard)

3

µs

T2.2.3

T2.2.4

Hardware Configuration pins

transition to output drivers

50

ns

RESET pulse width

X1 Clock must be stable for at min. of 1us

during RESET pulse low time.

1

µs

Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide

fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

65

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8.2.3 MII Serial Management Timing

MDC

T2.3.1

T2.3.4

MDIO (output)

MDC

T2.3.2

T2.3.3

Valid Data

MDIO (input)

Parameter

T2.3.1

Description

Notes

Min

0

Typ

Max

Units

ns

MDC to MDIO (Output) Delay Time

MDIO (Input) to MDC Setup Time

MDIO (Input) to MDC Hold Time

MDC Frequency

30

T2.3.2

10

ns

T2.3.3

ns

T2.3.4

2.5

25

MHz

8.2.4 100 Mb/s MII Transmit Timing

T2.4.1

TX_CLK

T2.4.3

T2.4.2

TXD[3:0]

TX_EN

Valid Data

Parameter

T2.4.1

Description

Notes

Min Typ Max Units

TX_CLK High/Low Time

100 Mb/s Normal mode

16

10

20

24

ns

T2.4.2

TXD[3:0], TX_EN Data Setup to TX_CLK

T2.4.3

TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode

0

ns

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66

8.2.5 100 Mb/s MII Receive Timing

T2.5.1

RX_CLK

T2.5.2

RXD[3:0]

RX_DV

RX_ER

Valid Data

Parameter

T2.5.1

Description

RX_CLK High/Low Time

RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode

Notes

Min Typ Max Units

100 Mb/s Normal mode

16

10

20

24

30

ns

T2.5.2

Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered

clocks. Minimum high and low times will not be violated.

8.2.6 100BASE-TX Transmit Packet Latency Timing

TX_CLK

TX_EN

TXD

T2.6.1

IDLE

(J/K)

DATA

PMD Output Pair

Parameter

Description

Notes

Min

Typ Max

Units

T2.6.1

TX_CLK to PMD Output Pair 100 Mb/s Normal mode

Latency

6

bits

Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after

the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100

Mb/s mode.

67

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8.2.7 100BASE-TX Transmit Packet Deassertion Timing

TX_CLK

TX_EN

TXD

T2.7.1

PMD Output Pair

DATA

(T/R)

IDLE

Parameter

Description

Notes

Min

Typ Max Units

bits

T2.7.1

TX_CLK to PMD Output Pair 100 Mb/s Normal mode

Deassertion

6

Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser-

tion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

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68

8.2.8 100BASE-TX Transmit Timing (t_R/F& Jitter)

T2.8.1

+1 rise

90%

10%

PMD Output Pair

10%

90%

+1 fall

T2.8.1

-1 fall

-1 rise

T2.8.1

T2.8.2

PMD Output Pair

eye pattern

T2.8.2

Parameter

Description

Notes

Min

Typ Max Units

T2.8.1

100 Mb/s PMD Output Pair t_R

and t_F

3

4

5

ns

100 Mb/s t_Rand t_FMismatch

500

1.4

ps

ns

T2.8.2

100 Mb/s PMD Output Pair

Transmit Jitter

Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times

Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude

69

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8.2.9 100BASE-TX Receive Packet Latency Timing

PMD Input Pair

IDLE

(J/K)

Data

T2.9.1

CRS

T2.9.2

RXD[3:0]

RX_DV

RX_ER

Parameter

T2.9.1

Description

Carrier Sense ON Delay

Receive Data Latency

Notes

Min

Typ Max

Units

bits

100 Mb/s Normal mode

20

24

T2.9.2

bits

Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion

of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode

Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

8.2.10 100BASE-TX Receive Packet Deassertion Timing

PMD Input Pair

CRS

IDLE

DATA

(T/R)

T2.10.1

Parameter

T2.10.1

Description

Carrier Sense OFF Delay

Notes

100 Mb/s Normal mode

Min

Typ Max

Units

24

bits

Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deasser-

tion of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode

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70

8.2.11 10 Mb/s MII Transmit Timing

T2.11.1

TX_CLK

T2.11.2

T2.11.3

TXD[3:0]

TX_EN

Valid Data

Parameter

T2.11.1

Description

TX_CLK High/Low Time

Notes

Min Typ Max Units

10 Mb/s MII mode

190 200 210

ns

T2.11.2

TXD[3:0], TX_EN Data Setup to TX_CLK fall

TXD[3:0], TX_EN Data Hold from TX_CLK rise

25

0

T2.11.3

Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII

signals are sampled on the falling edge of TX_CLK.

8.2.12 10 Mb/s MII Receive Timing

T2.12.1

RX_CLK

T2.12.3

T2.12.2

RXD[3:0]

RX_DV

Valid Data

Parameter

T2.12.1

Description

Notes

Min Typ Max Units

RX_CLK High/Low Time

160 200

100

240

ns

T2.12.2

RX_CLK to RXD[3:0], RX_DV Delay

10 Mb/s MII mode

T2.12.3

RX_CLK rising edge delay from RXD[3:0],

RX_DV Valid

100

Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks.

Minimum high and low times will not be violated.

71

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8.2.13 10 Mb/s Serial Mode Transmit Timing

T2.13.2

T2.13.1

TX_CLK

T2.13.4

T2.13.3

TXD[0]

TX_EN

Valid Data

Parameter

T2.13.1

Description

TX_CLK High Time

Notes

Min Typ Max Units

10 Mb/s Serial mode

20

70

25

0

25

75

30

80

ns

T2.13.2

TX_CLK Low Time

T2.13.3

TXD_0, TX_EN Data Setup to TX_CLK rise

TXD_0, TX_EN Data Hold from TX_CLK rise

T2.13.4

8.2.14 10 Mb/s Serial Mode Receive Timing

T2.14.1

RX_CLK

T2.14.2

RXD[0]

RX_DV

Valid Data

Parameter

T2.14.1

Description

RX_CLK High/Low Time

RX_CLK fall to RXD_0, RX_DV Delay

Notes

Min Typ Max Units

35

50

65

10

ns

T2.14.2

10 Mb/s Serial mode

-10

Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks.

Minimum high and low times will not be violated.

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72

8.2.15 10BASE-T Transmit Timing (Start of Packet)

TX_CLK

TX_EN

TXD

T2.15.2

PMD Output Pair

T2.15.1

Parameter

Description

Notes

Min

Typ

Max

Units

T2.15.1

Transmit Output Delay from the

Falling Edge of TX_CLK

10 Mb/s MII mode

3.5

bits

T2.15.2

Transmit Output Delay from the

Rising Edge of TX_CLK

10 Mb/s Serial mode

3.5

bits

Note: 1 bit time = 100 ns in 10Mb/s.

8.2.16 10BASE-T Transmit Timing (End of Packet)

TX_CLK

TX_EN

T2.16.1

0

PMD Output Pair

T2.16.2

PMD Output Pair

1

Parameter

Description

Notes

Min

Typ Max Units

T2.16.1

End of Packet High Time

(with ‘0’ ending bit)

250

300

ns

T2.16.2

End of Packet High Time

(with ‘1’ ending bit)

250

300

ns

73

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8.2.17 10BASE-T Receive Timing (Start of Packet)

1st SFD bit decoded

1

0

1

0

1

0

1

0

1

0

1

TPRD±

T2.17.1

CRS

RX_CLK

T2.17.2

RX_DV

T2.17.3

0000

Preamble

SFD

Data

RXD[3:0]

Parameter

Description

Notes

Min

Typ Max Units

T2.17.1

Carrier Sense Turn On Delay (PMD

Input Pair to CRS)

630 1000

ns

T2.17.2

T2.17.3

RX_DV Latency

10

8

bits

Receive Data Latency

Measurement shown from SFD

Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV

Note: 1 bit time = 100 ns in 10 Mb/s mode.

8.2.18 10BASE-T Receive Timing (End of Packet)

1

IDLE

0

1

PMD Input Pair

RX_CLK

T2.18.1

CRS

Parameter

Description

Carrier Sense Turn Off Delay

Notes

Min

Typ Max Units

T2.18.1

1.0

µs

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74

8.2.19 10 Mb/s Heartbeat Timing

TX_EN

TX_CLK

COL

T2.19.2

T2.19.1

Parameter

T2.19.1

Description

Notes

Min

Typ Max Units

CD Heartbeat Delay

All 10 Mb/s modes

1200

1000

ns

T2.19.2

CD Heartbeat Duration

8.2.20 10 Mb/s Jabber Timing

TXE

T2.20.1

T2.20.2

PMD Output Pair

COL

Parameter

T2.20.1

Description

Jabber Activation Time

Jabber Deactivation Time

Notes

Min

Typ Max Units

85

ms

T2.20.2

500

75

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8.2.21 10BASE-T Normal Link Pulse Timing

T2.21.2

T2.21.1

Normal Link Pulse(s)

Parameter

Description

Notes

Min

Typ Max Units

T2.21.1

T2.21.2

Pulse Width

Pulse Period

100

16

ns

ms

Note: These specifications represent transmit timings.

8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing

T2.22.2

T2.22.3

T2.22.1

Fast Link Pulse(s)

clock

pulse

data

pulse

clock

pulse

T2.22.5

T2.22.4

FLP Burst

Parameter

T2.22.1

Description

Notes

Min

Typ Max Units

Clock, Data Pulse Width

100

125

ns

T2.22.2

Clock Pulse to Clock Pulse

Period

µs

T2.22.3

Clock Pulse to Data Pulse

Period

Data = 1

62

µs

T2.22.4

T2.22.5

Burst Width

2

ms

FLP Burst to FLP Burst Period

16

Note: These specifications represent transmit timings.

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76

8.2.23 100BASE-TX Signal Detect Timing

PMD Input Pair

T2.23.1

T2.23.2

SD+ internal

Parameter

T2.23.1

Description

Notes

Min

Typ Max Units

SD Internal Turn-on Time

SD Internal Turn-off Time

1

ms

T2.23.2

350

µs

Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.

8.2.24 100 Mb/s Internal Loopback Timing

TX_CLK

TX_EN

TXD[3:0]

CRS

T2.24.1

RX_CLK

RX_DV

RXD[3:0]

Parameter

Description

Notes

Min

Typ Max Units

240 ns

T2.24.1

TX_EN to RX_DV Loopback

100 Mb/s internal loopback mode

Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”

of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is

based on device delays after the initial 550µs “dead-time”.

Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

77

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8.2.25 10 Mb/s Internal Loopback Timing

TX_CLK

TX_EN

TXD[3:0]

CRS

T2.25.1

RX_CLK

RX_DV

RXD[3:0]

Parameter

Description

Notes

Min

Typ Max Units

µs

T2.25.1

TX_EN to RX_DV Loopback 10 Mb/s internal loopback mode

2

Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

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78

8.2.26 RMII Transmit Timing

T2.26.1

X1

T2.26.2

T2.26.3

TXD[1:0]

TX_EN

Valid Data

T2.26.4

Symbol

PMD Output Pair

Parameter

T2.26.1

Description

X1 Clock Period

Notes

50 MHz Reference Clock

Min Typ Max Units

20

ns

T2.26.2

TXD[1:0], TX_EN, DataSetup

to X1 rising

4

2

T2.26.3

T2.26.4

TXD[1:0], TX_EN, Data Hold

from X1 rising

ns

X1 Clock to PMD Output Pair From X1 Rising edge to first bit of symbol

Latency

17

bits

79

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8.2.27 RMII Receive Timing

Data

IDLE

(J/K)

(TR)

PMD Input Pair

T2.27.4

T2.27.5

X1

T2.27.1

T2.27.2

T2.27.3

T2.27.2

RX_DV

CRS_DV

T2.27.2

RXD[1:0]

RX_ER

Parameter

Description

X1 Clock Period

Notes

Min Typ Max Units

T2.27.1

T2.27.2

50 MHz Reference Clock

20

ns

RXD[1:0], CRS_DV, RX_DV,

and RX_ER output delay from

X1 rising

2

14

T2.27.3

T2.27.4

T2.27.5

CRS ON delay

From JK symbol on PMD Receive Pair to

initial assertion of CRS_DV

18.5

27

bits

CRS OFF delay

From TR symbol on PMD Receive Pair to

initial deassertion of CRS_DV

RXD[1:0] and RX_ER latency From symbol on Receive Pair. Elasticity

buffer set to default value (01)

38

Note: Per the RMII Specification, output delays assume a 25pF load.

Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may

toggle synchronously at the end of the packet to indicate CRS deassertion.

Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of

receive data.

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80

8.2.28 Isolation Timing

Clear bit 10 of BMCR

(return to normal operation

from Isolate mode)

T2.28.1

T2.28.2

H/W or S/W Reset

(with PHYAD = 00000)

MODE

NORMAL

ISOLATE

Parameter

Description

Notes

Min

Typ Max Units

T2.28.1

From software clear of bit 10 in

the BMCR register to the transi-

tion from Isolate to Normal Mode

100

µs

T2.28.2

From Deassertion of S/W or H/W

Reset to transition from Isolate to

Normal mode

500

µs

8.2.29 25 MHz_OUT Timing

X1

T2.29.2

T2.29.1

25 MHz_OUT

Parameter

Description

Notes

Min Typ Max Units

T2.29.1

25 MHz_OUT High/Low Time

MII mode

20

10

ns

RMII mode

T2.29.2

25 MHz_OUT propagation delay

Relative to X1

8

Note: 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.

81

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8.2.30 100 Mb/s X1 to TX_CLK Timing

X1

T2.30.1

TX_CLK

Parameter

Description

X1 to TX_CLK delay

Notes

Min Typ Max Units

ns

T2.30.1

100 Mb/s Normal mode

0

5

Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit

Mll data.

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82

Notes:

83

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inches (millimeters) unless otherwise noted

9.0 Physical Dimensions

Lead Quad Frame Package (LQFP)

NS Package Number VBH48A

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Applications

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amplifier.ti.com

dataconverter.ti.com

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logic.ti.com

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power.ti.com

microcontroller.ti.com

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Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

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型号：	DP83848CVV/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	支持 SNI 接口和 JTAG、具有商业级温度范围的 10/100Mbps 以太网 PHY 收发器 \| PT \| 48 \| 0 to 70 以太网局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路电信电路网络接口
文件：	总86页 (文件大小：711K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83848CVV/NOPB [TI]

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