DP83867ISRGZT_技术文档

DP83867CS, DP83867IS, DP83867E

ZHCSEC3D –OCTOBER 2015 –REVISED NOVEMBER 2022

DP83867E/IS/CS 稳健型高抗扰性小型10/100/1000 以太网物理层收发器

1 特性

3 说明

• 超低延迟，TX < 90ns，RX < 290ns

• 符合时间敏感网络(TSN) 标准

• 低功耗：457mW

• 超过8000V IEC 61000-4-2 ESD 保护等级

• 符合EN55011 B 类发射标准

• 在RX/TX 上提供16 种可编程RGMII 延迟模式

• 集成MDI 终端电阻器

• 可编程MAC 接口端接阻抗

• WoL（局域网唤醒）数据包检测

• 25MHz 或125MHz 同步时钟输出

• IEEE 1588 时间戳帧起始检测

• RJ45 镜像模式

• 完全符合IEEE 802.3 10BASE-Te、100BASE-TX

和1000BASE-T 规范

• 电缆诊断

DP83867 器件是一款稳健型低功耗全功能物理层收发

器，它集成了 PMD 子层以支持 10BASE-Te 、

100BASE-TX 和 1000BASE-T 以太网协议。DP83867

经优化可提供 ESD 保护，超过了 8kV IEC 61000-4-2

标准（直接接触）。

DP83867 可轻松实现 10/100/1000Mbps 以太网

LAN。它通过外部变压器直接连接双绞线介质。此器件

通过 RGMII 或嵌入式时钟 SGMII 直接与 MAC 层相

连。

DP83867 提供精确时钟同步，其中包括同步以太网时

钟输出。该器件具有低延迟，并提供 IEEE 1588 帧起

始检测。

DP83867 采用低功耗设计，满功率运行时仅消耗

457mW。局域网唤醒可用于降低系统功耗。

• RGMII 和SGMII MAC 接口选项

• 可配置I/O 电压（3.3V、2.5V、1.8V）

• 快速链路断开模式

器件信息

封装尺寸（标称

封装⁽¹⁾

器件型号

温度

值）

7mm x 7mm

• JTAG 支持

DP83867CSRGZ

DP83867ISRGZ

DP83867ERGZ

VQFN (48)

0°C 至+70°C

–40°C 至+85°C

-40°C 至+105°C

2 应用

• 电机驱动器

• 工厂自动化

• 现场总线支持

• 工业嵌入式计算

• 有线和无线通信基础设施

• 测试和测量

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 消费类电子产品

10BASE-Te

100BASE-TX

1000BASE-T

RGMII

SGMII

DP83867

10/100/1000 Mbps

Ethernet Physical Layer

Ethernet MAC

Magnetics

RJ-45

25 MHz

Crystal or Oscillator

Status

LEDs

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS504

DP83867CS, DP83867IS, DP83867E

ZHCSEC3D –OCTOBER 2015 –REVISED NOVEMBER 2022

www.ti.com.cn

Table of Contents

8 Detailed Description......................................................20

8.1 Overview...................................................................20

8.2 Functional Block Diagram.........................................21

8.3 Feature Description...................................................22

8.4 Device Functional Modes..........................................25

8.5 Programming............................................................ 38

8.6 Register Maps...........................................................45

9 Application and Implementation................................103

9.1 Application Information........................................... 103

9.2 Typical Application.................................................. 103

10 Power Supply Recommendations............................110

11 Layout......................................................................... 113

11.1 Layout Guidelines..................................................113

11.2 Layout Example.....................................................115

12 Device and Documentation Support........................116

12.1 Documentation Support........................................ 116

12.2 Related Links........................................................ 116

12.3 接收文档更新通知................................................. 116

12.4 支持资源................................................................116

12.5 Electrostatic Discharge Caution............................116

12.6 术语表................................................................... 116

12.7 Trademarks........................................................... 116

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................5

6 Pin Configuration and Functions...................................5

6.1 Pin Functions.............................................................. 6

6.2 Unused Pins................................................................9

7 Specifications................................................................ 10

7.1 Absolute Maximum Ratings...................................... 10

7.2 ESD Ratings............................................................. 10

7.3 Recommended Operating Conditions.......................11

7.4 Thermal Information..................................................11

7.5 Electrical Characteristics...........................................11

7.6 Power-Up Timing...................................................... 13

7.7 Reset Timing.............................................................14

7.8 MII Serial Management Timing................................. 14

7.9 SGMII Timing............................................................ 14

7.10 RGMII Timing..........................................................14

7.11 DP83867E Start of Frame Detection Timing...........15

7.12 DP83867IS/CS Start of Frame Detection Timing....15

7.13 Timing Diagrams ....................................................16

7.14 Typical Characteristics............................................19

4 Revision History

Changes from Revision C (October 2019) to Revision D (November 2022)

Page

• 更新了IEEE 1588 时间戳的帧起始检测............................................................................................................. 1

• Updated Electrical Characteristics....................................................................................................................11

• Added Phy has internal 100 Ohm differential termination in 节8.4.1.1 ...........................................................25

• Added following wording to the end of first paragraph in 节8.4.3.9 "DP83867 devices manufactured after

August, 2022, have an increased random seed value that now includes 255 different seed values to expedite

Auto-MDIX resolution with a link partner."........................................................................................................ 33

• Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in ........................................................65

• Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated 节8.6.31 ............................................76

• Added Register 0x008A....................................................................................................................................82

• Added Register 0x00B3....................................................................................................................................83

• Added Register 0x00C0....................................................................................................................................83

• Added Register 0x0100.................................................................................................................................... 85

Changes from Revision B (March 2017) to Revision C (October 2019)

Page

• 向节1 添加了“符合时间敏感网络(TSN) 标准”..............................................................................................1

• 将节1 中的“快速链路建立/链路断开模式”更改为“快速链路断开模式”...................................................... 1

• 向节2 添加了“现场总线支持”......................................................................................................................... 1

• Deleted "NOTE: Internal pullup and pulldown resistors on the IO pins are disabled when the device enters

functional mode after power up." from Pin Functions......................................................................................... 6

• Added XI pin voltage ratings to 节7.1 ............................................................................................................. 10

• Added XI Input Voltage section to 节7.5 ......................................................................................................... 11

• Added SGMII Latency nominal values to 节7.9 ..............................................................................................14

• Changed links to RGMII timing diagrams in 节7.10 ........................................................................................14

• Changed T_holdRparameter description in 节7.10 ............................................................................................14

2

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• Added table note explaining how Duty Cycle % must be interpreted in 节7.10 ..............................................14

• Added RGMII TX and RX Latency values in 节7.10 .......................................................................................14

• Changed suggestion to program '10M_SGMII_RATE_ADAPT' bit in 节8.4.1.1 ............................................. 25

• Changed statement about PHY address in 节8.4.2 ........................................................................................28

• Deleted mentions of pin strapping to configure Auto-MDIX in 节8.4.3.9 ........................................................ 33

• Added 图8-9 ....................................................................................................................................................33

• Deleted "The BIST allows full control of the packet lengths and of the IPG." from 节8.4.5 ............................35

• Deleted mention of ALCD from 节8.4.6 .......................................................................................................... 35

• Deleted subsection describing ALCD from 节8.4.6 ........................................................................................ 35

• Added sentence about the polarity of MDI signals in 节8.4.6.5 ......................................................................37

• Changed note after 表8-5 to be a table note referenced within the table. ...................................................... 38

• Changed 'MMD3_PCS_CTRL' address to 'MMD3' register 0x0000 in 节8.5.5.5 ........................................... 44

• Deleted mention of MMD7 in 节8.5.5.5 ...........................................................................................................44

• Added definition for register Bit Name type 'Strap' in 节8.6 ............................................................................45

• Deleted Advanced Link Cable Diagnostics Control Register (ALCD_CTRL) .................................................. 45

• Added PAP package default for '1000BASE-T FULL DUPLEX' in 节8.6.10 ...................................................55

• Changed 'SGMII_EN' default in 节8.6.14 ....................................................................................................... 58

• Changed 'MDI_CROSSOVER' default in 节8.6.14 .........................................................................................58

• Added PAP package default for 'SPEED_OPT_EN' in 节8.6.18 .....................................................................65

• Added 节8.6.28 ...............................................................................................................................................74

• Changed descriptions of bits 'FORCE_DROP' and 'FLD_EN' in 节8.6.29 ..................................................... 75

• Added 节8.6.30 ...............................................................................................................................................76

• Added 'INT_TST_MODE_1' to 节8.6.31 .........................................................................................................76

• Changed 'PORT_MIRROR_EN' default in 节8.6.31 ....................................................................................... 76

• Added PAP package default for 'RGMII_EN' in 节8.6.32 ................................................................................76

• Added 节8.6.36 ...............................................................................................................................................79

• Changed description of 'STRAP_FLD' from "Fast Link Detect" to "Fast Link Drop" in 节8.6.39 .....................81

• Added 节8.6.42 ...............................................................................................................................................82

• Added 节8.6.43 ...............................................................................................................................................82

• Changed 'RGMII_TX_DELAY_CTRL' default value in 节8.6.45 ..................................................................... 83

• Changed 'RGMII_RX_DELAY_CTRL' default value in 节8.6.45 .....................................................................83

• Added 节8.6.48 ...............................................................................................................................................83

• Added 节8.6.53 ...............................................................................................................................................85

• Changed description of '10M_SGMIII_RATE_ADAPT' in 节8.6.99 .................................................................93

• Added GPIO_MUX_CTRL register for RGZ devices........................................................................................95

• Added TDR registers 0x0190 to 0x01A4.......................................................................................................... 96

• Added TDR registers........................................................................................................................................ 96

• Added 节8.6.124 ...........................................................................................................................................101

• Changed 'PCS_RESET' description in 节8.6.125 .........................................................................................101

• Changed capacitor value in 图9-2 and added footnotes................................................................................104

• Added requirements for 2.5-V clock source capacitors in 节9.2.1.2 .............................................................106

• Added 图9-4 ..................................................................................................................................................106

• Added "RMS Jitter" to 表9-2 ......................................................................................................................... 106

• Added 节9.2.1.4 ............................................................................................................................................108

• Changed capacitor placement in 图10-1 and footnote about decoupling capacitor placement.....................110

• Changed capacitor placement in 图10-2 and footnote about decoupling capacitor placement.....................110

Changes from Revision A (February 2017) to Revision B (March 2017)

Page

• Changed pin 6 name in the pinout diagram from: VDDA1P0 to: VDD1P0......................................................... 5

• Changed INT / PWDN Interrupt description........................................................................................................6

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• Changed RESERVED bit number from: 15:8 to: 15:9 ..................................................................................... 76

• Changed RESERVED bit number from: 7 to: 8:7 ............................................................................................ 76

• Changed the default and description of the CLK_O_DISABLE bit (bit 6).........................................................93

• Clarified 图9-2 ...............................................................................................................................................104

• Changed text in MDI traces bullet from: or to: and......................................................................................... 109

Changes from Revision * (October 2015) to Revision A (February 2017)

Page

• 根据最新文档和翻译标准更新了数据表文本....................................................................................................... 1

• Added storage temperature to 节7.1 .............................................................................................................. 10

• Updated parameter symbol from VIH to V_IH.................................................................................................... 11

• Added MDC toggling clarification to 节7.7 ......................................................................................................14

• Added 节7.11 ..................................................................................................................................................15

• Added DP83867IS/CS Start of Frame Detection Timing.................................................................................. 15

• Added section 节8.3.2.1 ................................................................................................................................. 24

• Changed target strap voltage thresholds 表8-4 ..............................................................................................38

• Changed values for RX_CTRL pin for modes 1 and 2 to N/A in 表8-5 ...........................................................38

• Changed strap name SPEED_SEL to ANEG_SEL in 表8-5 ...........................................................................38

• Changed table name Speed Select Strap Details to Auto-Negotiation Select Strap Details in 表8-6 ............ 38

• Changed strap option SPEED_SEL to ANEG_SEL in 表8-6 ..........................................................................38

• Changed mode 5 RGMII Clock Skew value from 4.0 ns to 0 ns in 表8-7 .......................................................38

• Changed strap control of Speed Select bit 13 in 表8-9 ...................................................................................45

• Changed strap control of Speed Select bit 6 in 表8-9 .....................................................................................45

• Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in 表8-18 ............... 55

• Changed bit 9 descriptions from half duplex to full duplex in 表8-18 ..............................................................55

• Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in 节

8.6.16 ...............................................................................................................................................................61

• Changed Register definition to move a statement from 节8.6.17 to 节8.6.16 ............................................... 61

• Changed default of bit 9 from '1' to '0' in 表8-27 .............................................................................................65

• Changed default of bits 5:0 from '0' to '0 0111' in 表8-27 ................................................................................65

• Added 节8.6.29 register...................................................................................................................................75

• Added 节8.6.37 register...................................................................................................................................79

• Changed SPEED_SEL strap bit name to ANEG_SEL in Strap Configuration Status Register 1

(STRAP_STS1), Address 0x006E....................................................................................................................80

• Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_TX' to 'STRAP_RGMII_CLK_SKEW_TX' in 表

8-48 ..................................................................................................................................................................81

• Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_RX' to 'STRAP_RGMII_CLK_SKEW_RX' in 表

8-48 ..................................................................................................................................................................81

• Added 节8.6.50 register...................................................................................................................................85

• Changed default of bits 12:8 to 0 1100 in 表8-109 ......................................................................................... 93

• Changed description for IO_IMPEDANCE_CTRL bits in 节8.6.100 ...............................................................93

• Changed 节10 section....................................................................................................................................110

• Added power down supply sequence sentence in 节10 ............................................................................... 110

• Added 图10-3 ................................................................................................................................................110

• Added 表10-1 ................................................................................................................................................110

• Added note regarding 1.8-V supply sequence if no load exists on 2.5-V supply in Layout ........................... 110

4

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5 Device Comparison

表5-1. Device Features Comparison

DEVICE

MAC

TEMPERATURE RANGE

TEMPERATURE GRADE

Commercial

DP83867CSRGZ

DP83867ISRGZ

DP83867ERGZ

SGMII/RGMII

0°C

70°C

85°C

Industrial

–40°C

105°C

Extended

6 Pin Configuration and Functions

48 47 46 45 44 43 42 41 40 39 38 37

RX_D3/SGMII_SON

RX_D2/SGMII_SOP

RX_D1/SGMII_CON

RX_D0/SGMII_COP

RX_CLK

1

2

36

35

34

33

32

31

30

29

28

27

26

25

TD_P_A

TD_M_A

VDDA2P5

TD_P_B

TD_M_B

3

4

DP83867

5

TOP VIEW

(not to scale)

VDD1P0

6

VDD1P0

TD_P_C

48-pin QFN Package

VDDIO

7

TD_M_C

VDDA2P5

TD_P_D

DAP = GND

GTX_CLK

8

TX_D0/SGMII_SIN

TX_D1/SGMII_SIP

TX_D2

9

10

11

TD_M_D

TX_D3

RBIAS 12

13 14 15 16 17 18 19 20 21 22 23 24

图6-1. RGZ Package 48-Pin VQFN Top View

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6.1 Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

MAC INTERFACES (SGMII, RGMII)

TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in

RGMII mode. It is synchronous to the transmit clock GTX_CLK.

TX_D3

TX_D2

25

26

I, PD

TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in

RGMII mode. It is synchronous to the transmit clock GTX_CLK.

Differential SGMII Data Input: This signal carries data from the MAC to the

PHY in SGMII mode. It is synchronous to the differential SGMII clock input.

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

SGMII_SIP

TX_D1

27

28

I, PD

TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in

RGMII mode. It is synchronous to the transmit clock GTX_CLK.

Differential SGMII Data Input: This signal carries data from the MAC to the

PHY in SGMII mode. It is synchronous to the differential SGMII clock input.

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

SGMII_SIN

TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in

RGMII mode. It is synchronous to the transmit clock GTX_CLK.

TX_D0

28

29

I, PD

RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the

MAC layer to the PHY. Nominal frequency is 125 MHz.

GTX_CLK

RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different

modes of operation:

RX_CLK

32

O

2.5 MHz in 10-Mbps mode.

25 MHz in 100-Mbps mode.

125 MHz in 1000-Mbps mode.

Differential SGMII Clock Output: This signal is a continuous 625-MHz clock

signal driven by the PHY in SGMII mode.

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

SGMII_COP

RX_D0

33

34

S, O

RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in

RGMII mode. It is synchronous to the receive clock RX_CLK.

S, O, PD

O, PD

Differential SGMII Clock Output: This signal is a continuous 625-MHz clock

signal driven by the MAC in SGMII mode.

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

SGMII_CON

RX_D1

RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in

RGMII mode. It is synchronous to the receive clock RX_CLK.

Differential SGMII Data Output: This signal carries data from the PHY to the

MAC in SGMII mode. It is synchronous to the differential SGMII clock output.

SGMII_SOP

35

S, O, PD

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in

RGMII mode. It is synchronous to the receive clock RX_CLK.

RX_D2

35

36

S, O, PD

Differential SGMII Data Output: This signal carries data from the PHY to the

MAC in SGMII mode. It is synchronous to the differential SGMII clock output.

This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when

operating in SGMII mode.

SGMII_SON

RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in

RGMII mode. It is synchronous to the receive clock RX_CLK.

RX_D3

36

37

O, PD

I, PD

TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and

the transmit error signals of GMII mode using both clock edges.

TX_CTRL

RECEIVE CONTROL: In RGMII mode, the receive data available and receive

error are combined (RXDV_ER) using both rising and falling edges of the

receive clock (RX_CLK).

RX_CTRL

38

S, O, PD

GENERAL-PURPOSE I/O

6

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TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

General-Purpose I/O: This signal provides a multi-function configurable I/O.

Refer to the GPIO_MUX_CTRL register for details.

GPIO_0

39

S, O, PD

General-Purpose I/O: This signal provides a multi-function configurable I/O.

Refer to the GPIO_MUX_CTRL register for details.

GPIO_1

40

MANAGEMENT INTERFACE

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial

management input and output data. This clock may be asynchronous to the

MAC transmit and receive clocks. The maximum clock rate is 25 MHz and no

minimum.

MDC

16

I, PD

I/O

MANAGEMENT DATA I/O: Bidirectional management instruction and data

signal that may be sourced by the management station or the PHY. This pin

requires pullup resistor. The IEEE specified resistor value is 1.5 kΩ, but a 2.2

kΩis acceptable.

MDIO

17

44

INTERRUPT / POWER DOWN:

The default function of this pin is POWER DOWN.

POWER DOWN: This is an Active Low Input. Asserting this signal low enables

the power-down mode of operation. In this mode, the device powers down and

consume minimum power. Register access is available through the

Management Interface to configure and power up the device.

INTERRUPT: When operating this pin as an interrupt, it is an open-drain

architecture. TI recommends using an external 2.2-kΩresistor connected to

the VDDIO supply.

INT / PWDN

I/O, PU

RESET

RESET: The active low RESET initializes or reinitializes the DP83867. All

internal registers re-initialize to their default state upon assertion of RESET.

The RESET input must be held low for a minimum of 1 µs.

RESET_N

43

I, PU

CLOCK INTERFACE

XI

15

14

18

I

CRYSTAL/OSCILLATOR INPUT: 25-MHz oscillator or crystal input (50 ppm)

CRYSTAL OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if

a clock oscillator is used.

XO

O

CLK_OUT

CLOCK OUTPUT: Output clock

JTAG INTERFACE

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all

test logic input and output controlled by the testing entity.

JTAG_CLK

JTAG_TDO

20

21

I, PU

O

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most

recent test results are scanned out of the device through TDO.

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin

sequences the Tap Controller (16-state FSM) to select the desired test

instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to

reset the JTAG.

JTAG_TMS

22

23

I, PU

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

scanned into the device through TDI.

JTAG_TDI

LED INTERFACE

LED_2

LED_2: By default, this pin indicates receive or transmit activity. Additional

functionality is configurable through LEDCR1[11:8] register bits.

45

46

47

S, I/O, PD

LED_1: By default, this pin indicates that 1000BASE-T link is established.

Additional functionality is configurable through LEDCR1[7:4] register bits.

LED_1

LED_0

LED_0: By default, this pin indicates that link is established. Additional

functionality is configurable through LEDCR1[3:0] register bits.

MEDIA DEPENDENT INTERFACE

TD_P_A

TD_M_A

TD_P_B

TD_M_B

1

2

4

5

A

Differential Transmit and Receive Signals

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TYPE⁽¹⁾

DESCRIPTION

Differential Transmit and Receive Signals

NAME

TD_P_C

NO.

7

A

TD_M_C

8

Differential Transmit and Receive Signals

TD_P_D

10

11

TD_M_D

OTHER PINS

Bias Resistor Connection. A 11-kΩ±1% resistor should be connected from

RBIAS to GND.

RBIAS

12

A

POWER AND GROUND PINS

2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to

GND.

VDDA2P5

VDD1P0

3, 9

P

1-V Analog Supply (+15.5%, –5%). Each pin requires a 1-µF and 0.1-µF

capacitor to GND.

6, 24, 31, 42

1.8-V Analog Supply (±5%).

No external supply is required for this pin. When unused, no connections

should be made to this pin.

For additional power savings, an external 1.8-V supply can be connected to

these pins. When using an external supply, each pin requires a 1-µF and 0.1-

µF capacitor to GND.

VDDA1P8

13, 48

P

I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF

and 0.1-µF capacitor to GND

VDDIO

GND

19, 30, 41

P

Die Attach Pad

Ground

(1) The definitions below define the functionality of each pin.

•

Type: I Input

Type: O Output

Type: I/O Input/Output

Type: PD, PU Internal Pulldown/Pullup

Type: S Configuration Pin

Type: P Power or GND

Type: A Analog pins

8

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6.2 Unused Pins

DP83867 has internal pullups or pulldowns on most pins. The data sheet details which pins have internal pullups

or pulldowns and which pins require external pull resistors.

Even though a device may have internal pullup or pulldown resistors, a good practice is to terminate unused

inputs rather than allowing them to float. Floating inputs could result in unstable conditions. Except for VDDA1P8

pins, if they are not used then they should be left floating. It is considered a safer practice to pull an unused input

pin high or low with a pullup or pulldown resistor. It is also possible to group together adjacent unused input pins,

and as a group pull them up or down using a single resistor.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

VDDA2P5

VDDA1P8

3

–0.3

–60

2.1

VDD1P0

Supply voltage

1.3

V

3.3-V option

3.8

2.5-V option

1.8-V option

3

VDDIO

2.1

6.5

MDI

VDDIO + 0.3

2.1

MAC interface, MDIO, MDC, GPIO

INT/PWDN, RESET

JTAG

V

Pins

XI (Oscillator Clock Input)

V

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

DP83867ERGZ and DP83867ISRGZ in the RGZ Package

All pins except 1, 2, 4, 5,

7, 8, 10, and 11

±2500

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Pins 1, 2, 4, 5, 7, 8, 10,

and 11⁽³⁾

V

±8000

±1500

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

DP83867CSRGZ in the RGZ Package

All pins except 1, 2, 4, 5,

7, 8, 10, and 11

±2500

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Pins 1, 2, 4, 5, 7, 8, 10,

and 11⁽³⁾

V

±6000

±1500

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8 V and/or ± 2 V may actually have higher

performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

(3) MDI Pins tested as per IEC 61000-4-2 standards.

10

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

1.71

0.95

3.15

2.375

1.71

0

TYP

2.5

1.8

1

MAX

2.625

1.89

1.155

3.45

2.625

1.89

90

UNIT

VDDA2P5

VDDA1P8

VDD1P0

Supply voltage

V

3.3-V option

3.3

2.5

1.8

VDDIO

2.5-V option

1.8-V option

Commercial (DP83867CSRGZ)

Industrial (DP83867ISRGZ)

Extended (DP83867ERGZ)

Commercial (DP83867CSRGZ)

Industrial (DP83867ISRGZ)

Extended (DP83867ERGZ)

105

Operating junction temperature

–40

0

°C

125

25

70

85

Operating free air temperature

–40

105

7.4 Thermal Information

DP83867xS, DP83867E

THERMAL METRIC⁽¹⁾

RGZ (VQFN)

48 PINS

30.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJC(bot)

R_θJB

18.7

1.4

7.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.3

ψ_JT

7.5

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life

of the product containing it.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.3-V V_DDIO

V_OH

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

2

V

I_OH= –4 mA

V_OL

I_OL= 4 mA

0.6

0.7

V_IH

1.7

V_IL

2.5-V V_VDDIO

V_OH

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

V_DDIO× 0.8

V

I_OH= –4 mA

V_OL

I_OL= 4 mA

0.6

0.7

V_IH

1.7

V_IL

1.8-V V_DDIO

V_OH

High level output voltage

V

I_OH= –1 mA

V_DDIO–0.2

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7.5 Electrical Characteristics (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life

of the product containing it.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OL

V_IH

V_IL

Low level output voltage

High level input voltage

Low level input voltage

I_OL= 1 mA

0.2

V

0.7 × V_DDIO

0.2 × VDDIO

1.9

XI INPUT VOLTAGE

V_OSC

Input voltage for 25 MHz

Oscillator

1.5

1.4

Vpp

V_IH

V_IL

High level input voltage

Low level input voltage

V

0.45

DC CHARACTERISTICS

VIN = VDD, T_A= –40°C to

+85°C

-10

-20

-10

-20

-10

-20

10

20

10

20

10

µA

I_IH

Input high current

VIN = VDD, T_A= 85°C to

+105°C

VIN = GND, T_A= –40°C to

+85°C

I_IL

Input low current

VIN = GND, T_A= 85°C to

+105°C

VOUT = VDD, VOUT = GND,

T_A= –40°C to +85°C

I_OZ

TRI-STATE output current

Input capacitance

VOUT = VDD, VOUT = GND,

T_A= 85°C to +105°C

20

5

µA

pF

C_IN

See ⁽³⁾

PMD OUTPUTS

ERGZ/ISRGZ

CSRGZ

1.54

0.95

0.67

1.75

1

1.96

1.05

0.82

V Peak

Differential

V_OD-10

MDI

ERGZ/ISRGZ

CSRGZ

V Peak

Differential

V_OD-100

MDI

1

ERGZ/ISRGZ

CSRGZ

0.745

V Peak

Differential

V_OD-1000

POWER CONSUMPTION

RGMII power consumption⁽¹⁾

2 supplies

495

457

137

108

24

P1000

mW

(2) (4)

Optional 3rd supply

2 supplies

IDD25

Supply current

mA

IDD10

IDDIO (1.8 V)

IDD25

Supply current

Optional 3rd supply

86

IDD10

108

50

IDD18

IDDIO (1.8 V)

24

(1) Power consumption represents total operational power for 1000BASE-T.

(2) See 节10 for details on 2-supply and 3-supply configuration.

(3) Ensured by production test, characterization, or design.

(4) For detailed information about DP83867 power consumption for specific supplies under a wide set of conditions, see the

DP83867E/IS/CS/IR/CR RGZ Power Consumption Data application report (SNLA241).

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7.6 Power-Up Timing

See 图7-1.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

NOM

MAX UNIT

Post power-up stabilization time prior to MDC MDIO is pulled high for 32-bit serial

T1

T2

T3

200

ms

preamble for register accesses

management initialization.

Hardware Configuration Pins are

described in 节8.5.1.

Hardware configuration latch-in time from

power up

200

64

ms

ns

Hardware configuration pins transition to

output drivers

(1) Ensured by production test, characterization, or design.

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7.7 Reset Timing

See 图7-2.

PARAMETER

TEST CONDITIONS ⁽¹⁾

MIN

NOM

MAX UNIT

MDIO is pulled high for 32-bit serial

management initialization.

MDC may toggle during this period when

MDIO remains high.

Post RESET stabilization time prior to MDC

preamble for register accesses

T1

195

µs

T2

T3

T4

Hardware Configuration Pins are

described in 节8.5.1.

Hardware configuration latch-in time from the

deassertion of RESET (either soft or hard)

120

64

ns

µs

Hardware configuration pins transition to

output drivers

X1 Clock must be stable for a minimum of

1 μs during RESET pulse low time

RESET pulse width

1

(1) Ensured by production test, characterization, or design.

7.8 MII Serial Management Timing

See 图7-3.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

0

NOM MAX UNIT

T1

T2

T3

T4

MDC to MDIO (output) delay time

MDIO (input) to MDC setup time

MDIO (input) to MDC hold time

MDC frequency

10

ns

10

2.5

25 MHz

(1) Ensured by production test, characterization, or design.

7.9 SGMII Timing

See 图7-4.

PARAMETER

TEST CONDITIONS ⁽³⁾

MIN

48%

100

NOM

MAX UNIT

T1

T2

SGMII Clock Output Duty Cycle

Setup time

52%

ps

See ⁽¹⁾

Clock to Data relationship from

T3

either edges of the clock to valid See ⁽²⁾

data

250

550

ps

T_R

VOD fall time

20% - 80%

100

200

ps

ns

T_F

VOD rise time

20% - 80%

See ⁽¹⁾

T_hold

T_TXLAT

T_RXLAT

Hold time

SGMII to MDI Latency

MDI to SGMII Latency

See ⁽⁴⁾

201

289

See ⁽⁴⁾

(1) Setup and hold time are measured at 50% of the transition.

(2) T3 is measured at 0 V differential.

(3) Ensured by production test, characterization, or design.

(4) Operating in 1000Base-T

7.10 RGMII Timing

See 图7-5 and .图7-6

PARAMETER

TEST CONDITIONS⁽⁵⁾

MIN

NOM

MAX UNIT

Data to Clock output Skew

(at Transmitter)

T_skewT

T_skewR

T_setupT

See ⁽¹⁾

See ⁽⁴⁾

0

500

2.6

ps

ns

–500

1

Data to Clock input Skew

(at Receiver)

1.8

2

Data to Clock output Setup

(at Transmitter –internal delay)

1.2

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7.10 RGMII Timing (continued)

See 图7-5 and .图7-6

PARAMETER

TEST CONDITIONS⁽⁵⁾

See ⁽⁴⁾

MIN

NOM

MAX UNIT

Clock to Data output Hold

T_holdT

1.2

2

ns

(at Transmitter –internal delay)

Data to Clock input Setup

T_setupR

See ⁽⁴⁾

1

2

ns

(at Reciever –internal delay)

Clock to Data input Hold

T_holdR

(at Receiver –internal delay)

T_cyc

Clock Cycle Duration

Duty Cycle for Gigabit

Duty Cycle for 10/100T

Rise Time (20% to 80%)

Fall Time (20% to 80%)

RGMII to MDI Latency

MDI to RGMII Latency

See ⁽²⁾

7.2

45

40

8

50

8.8

55%

60%

0.75

ns

Duty_G

Duty_T

T_R

See ^{(3) (7)}

ns

T_F

T_TXLAT

T_RXLAT

See ⁽⁶⁾

88

288

(1) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of

greater than 1.5 ns is added to the associated clock signal.

(2) For 10-Mbps and 100-Mbps, Tcyc will scale to 400 ns ± 40 ns and 40 ns ± 4 ns.

(3) Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as

minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.

(4) Device may operate with or without internal delay.

(5) Ensured by production test, characterization, or design.

(6) Operating in 1000Base-T .

(7) Duty cycle values are defined in percentages of the nominal clock speed. For example, the minimum Gigabit RGMII clock pulse

duration is 45 % of 8 ns.

7.11 DP83867E Start of Frame Detection Timing

图7-7

PARAMETER

TEST CONDITIONS

1000-Mb Master

MIN

0

NOM

MAX UNIT

0

8

4

0

ns

T1

T2

Transmit SFD variation^{(1) (2)}

1000-Mb Slave

100-Mb

0

1000-Mb Master

1000-Mb Slave

100-Mb

–4

0

Receive SFD variation^{(1) (2)}

0

(1) A larger variation may be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see

the 节8.3.2.1 section for a method to compensate for variation in the SFD pulses.

(2) Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in 节8.3.2.1.

7.12 DP83867IS/CS Start of Frame Detection Timing

图7-8

PARAMETER

TEST CONDITIONS

1000-Mb Master

MIN

0

NOM

MAX UNIT

0

ns

T1

T2

Transmit SFD variation^{(1) (2)}

1000-Mb Slave

100-Mb

0

16

8

1000-Mb Master

1000-Mb Slave

100-Mb

–8

0

Receive SFD variation^{(1) (2)}

8

0

(1) A larger variation may be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see

the 节8.3.2.1 section for a method to compensate for variation in the SFD pulses.

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(2) Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in 节8.3.2.1.

7.13 Timing Diagrams

VDD

XI clock

T1

Hardware

RESET_N

32

CLOCKS

MDC

T2

Latch-In of Hardware

Configuration Pins

T3

Dual Function Pins

Become Enabled As Outputs

INPUT

OUTPUT

图7-1. Power-Up Timing

VDD

XI clock

T1

T4

Hardware

RESET_N

32

CLOCKS

MDC

T2

Latch-In of Hardware

Configuration Pins

T3

Dual Function Pins

Become Enabled As Outputs

Input

Output

图7-2. Reset Timing

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MDC

T4

T1

MDIO

(output)

MDC

T2

T3

MDIO

(input)

Valid Data

图7-3. MII Serial Management Timing

SG_RXCK

(single ended)

SG_RXCK

(differential)

tT2t

tT1t

SG_RXDA

(single ended)

SG_RXDA

(differential)

T3 (min)

T3 (max)

图7-4. SGMII Timing

GTX

(at Transmitter)

TskewT

TXD [8:5][3:0]

TXD [7:4][3:0]

TXD [8:5]

TXD [7:4]

TXD [3:0]

TXD [4]

TXEN

TXD [9]

TXERR

TX_CTL

TskewR

GTX

(at Receiver)

图7-5. RGMII Transmit Multiplexing and Timing Diagram

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RXC

(Source of Data)

RXC with Internal

Delay Added

TsetupT

RXD [8:5][3:0]

RXD [7:4][3:0]

RXD [8:5]

RXD [7:4]

RXD [3:0]

TholdT

RXD [4]

RXDV

RXD [9]

RXERR

RX_CTL

RXC

(at Receiver)

TholdR

TsetupR

图7-6. RGMII Receive Multiplexing and Timing Diagram

T1

TX SFD

Packet

Transmitted

on Wire

Packet

Received

from Wire

T2

RX SFD

图7-7. DP83867E Start of Frame Delimiter Timing

T1

TX SFD

Packet

Transmitted

on Wire

Packet

Received

from Wire

T2

RX SFD

图7-8. DP83867IS/CS Start of Frame Delimiter Timing

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7.14 Typical Characteristics

Time (4 ns/DIV)

Time (32 ns/DIV)

1000Base-T Signaling

100Base-TX Signaling

(Scrambled Idles)

(Test Mode TM2 Output)

图7-9. 1000Base-T Signaling

图7-10. 100Base-TX Signaling

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8 Detailed Description

8.1 Overview

The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sub-layers to support 10BASE-

Te, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83867 is designed for easy implementation of 10-,100-, and 1000-Mbps Ethernet LANs. It interfaces

directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer

through the Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII).

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has

low jitter, low latency and provides IEEE 1588 Start of Frame Detection for time sensitive protocols.

The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction

during normal operation. It can support up to 130-m cable length.

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8.2 Functional Block Diagram

MGMT INTERFACE

COMBINED RGMII / SGMII INTERFACE

MGNT

& PHY CNTRL

MUX / DMUX

1000BASE-T

Block

100BASE-TX

Block

10BASE-Te

Block

100BASE-TX

PCS

1000BASE-T

PCS

Echo cancellation

Crosstalk cancellation

ADC

10BASE-Te PLS

Decode / Descramble

Equalization

Timing

Skew compensation

BLW

Wake on

LAN

100BASE-TX

PMA

10BASE-Te

PMA

10000BASE-T

PMA

Auto-

Negotiation

Manchester

10 Mbps

100BASE-TX

PMD

PAM-5

17 Level PR Shaped

125 Msymbols/s

MLT-3

100 Mbps

DAC / ADC

SUBSYSTEM

TIMING

DRIVERS /

RECEIVERS

DAC / ADC

TIMING BLOCK

MAGNETICS

4-pair CAT-5 Cable

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8.3 Feature Description

8.3.1 WoL (Wake-on-LAN) Packet Detection

Wake-on-LAN provides a mechanism for bringing the DP83867 out of a low-power state using a special Ethernet

packet called a Magic Packet. The DP83867 can be configured to generate an interrupt to wake up the MAC

when a qualifying packet is received. An option is also available to generate a signal on a GPIO when a

qualifying signal is received.

备注

Please ensure that BMCR (register address 0x0000) bit[10] is disabled, when using the WoL feature.

This bit enables the MII ISOLATE function used to disable the MAC interface of the PHY, also

disabling the WoL interrupt on this PHY. If the WoL feature is needed while MII ISOLATE is enabled

please use TI's DP83869HM PHY instead.

The Wake-on-LAN feature includes the following functionality:

• Identification of magic packets in all supported speeds (1000BASE-T, 100BASE-TX, 10BASE-Te)

• Wakeup interrupt generation upon receiving a valid magic packet

• CRC checking of magic packets to prevent interrupt generation for invalid packets

In addition to the basic magic packet support, the DP83867 also supports:

• Magic packets that include secure-on password

• Pattern match –one configurable 64 byte pattern of that can wake up the MAC similar to magic packet

• Independent configuration for Wake on Broadcast and Unicast packet types.

8.3.1.1 Magic Packet Structure

When configured for Magic Packet mode, the DP83867 scans all incoming frames addressed to the node for a

specific data sequence. This sequence identifies the frame as a Magic Packet frame.

备注

The Magic Packet should be byte aligned.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE

ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST

address), and CRC.

The specific Magic Packet sequence consists of 16 duplications of the IEEE address of this node, with no breaks

or interruptions, followed by secure-on password if security is enabled. This sequence can be located anywhere

within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as

6 bytes of FFh.

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DEST (6 bytes)

SRC (6 bytes)

MISC (X bytes, X >= 0)

FF… FF (6 bytes)

MAGIC pattern

DEST * 16

SecureOn Password (6 bytes)

MISC (Y bytes, Y >= 0)

CRC (4 bytes)

Only if Secure-On is enabled

图8-1. Magic Packet Structure

8.3.1.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a

SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:

DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44

55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

8.3.1.3 Wake-on-LAN Configuration and Status

Wake-on-LAN functionality is configured through the RXFCFG register (address 0x0134). Wake-on-LAN status

is reported in the RXFSTS register (address 0x0135).

8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp

The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and

transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is

presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can

be adjusted through register. Each increment of phase value is an 8-ns step.

图8-2. IEEE 1588 Message Timestamp Point

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The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register

address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The ENHANCED_MAC_SUPPORT bit in

RXCFG (register address 0x0134) must also be set to allow output of the SFD.

For more information about configuring the DP83867's SFD feature, see the How to Configure DP83867 Start of

Frame application report (SNLA242).

8.3.2.1 SFD Latency Variation and Determinism

Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not

accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the

accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits

latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine

when an SFD latency variation has occurred and how to compensate for the variation in system software to

improve timestamp accuracy.

In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time

measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet

cable with all 4 pairs perfectly matched in propagation time. In the scenario where all 4 pairs being perfectly

matched, a 1000BASE-T PHY will not have to align the 4 received symbols on the wire and will not introduce

extra latency due to alignment.

TX SFD

Baseline Latency

RX SFD

SFD Variation

图8-3. Baseline Latency and SFD Variation in Latency Measurement

SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must

introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is

established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects.

During a single, uninterrupted link, the SFD variation will remain constant.

The DP83867 can limit and report the variation applied to the SFD pulse while in the 1000-Mb operating mode.

Before a link is established in 1000-Mb mode, the Sync FIFO Control Register (register address 0x00E9) must

be set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync FIFO

Control Register has been initialized and a new link has been established. It is acceptable to set the Sync FIFO

Control register value and then perform a software restart by setting the SW_RESTART bit[14] in the Control

Register (register address 0x001F) if a link is already present.

8.3.2.1.1 1000-Mb SFD Variation in Master Mode

When the DP83867 is operating in 1000-Mb master mode, variation of the RX_SFD pulse can be estimated

using the Skew FIFO Status register (register address 0x0055) bit[7:4]. The value read from the Skew FIFO

Status register bit[7:4] must be multiplied by 8 ns to estimate the RX_SFD variation added to the baseline

latency.

Example: While operating in master 1000-Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4].

2 × 8 ns = 16 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

8.3.2.1.2 1000-Mb SFD Variation in Slave Mode

When the DP83867 is operating in 1000-Mb slave mode, the variation of the RX_SFD pulse can be determined

using the Skew FIFO Status register (register address 0x0055) bit[3:0].The value read from the Skew FIFO

Status register bit[3:0] should be multiplied by 8ns to estimate the RX_SFD variation added to the baseline

latency.

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Example: While operating in slave 1000-Mb mode, a value of 0x1 is read from the Skew FIFO register bit[3:0].

1 × 8 ns = 8 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

8.3.2.1.3 100-Mb SFD Variation

The latency variation in 100-Mb mode of operation is determined by random process and does not require any

register readout or system level compensation of SFD pulses.

8.3.3 Clock Output

The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and

the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock.

The local reference clock acts as the central source for all clocking in the device.

The local reference clock is embedded into the transmit network packet traffic and is recovered from the network

packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream

and is locked to the transmit clock in the partner.

Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal

clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input.

The default output clock is suitable for use as the reference clock of another DP83867 device. Through registers,

the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the

divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in

1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.

The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register.

8.4 Device Functional Modes

8.4.1 MAC Interfaces

The DP83867 supports connection to an Ethernet MAC through the following interfaces: SGMII and RGMII.

The SGMII Enable (LED_0) strap allows the user to turn the SGMII MAC interface on or off. The SGMII Enable

strap corresponds to the SGMII Enable (bit 11) in the PHYCR register (address 0x0010).

The SGMII enable has higher priority than the RGMII enable. 表 8-1 is the configuration table for the MAC

interfaces:

表8-1. Configuration Table for the MAC Interfaces

SGMII ENABLE (REGISTER 0x0010, BIT

RGMII ENABLE (REGISTER 0x0032, BIT 7)

DEVICE FUNCTIONAL MODE

11)

0x1

0x0

0x1

0x0

0x1

SGMII

RGMII

The initial strap values for the SGMII enable and the RGMII disable are also available in the Strap Configuration

Status Register 1 (STRAP_STS1).

8.4.1.1 Serial GMII (SGMII)

The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port

speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for

GMII (24 pins) or RGMII (12 pins). The SGMII interface uses 1.25-Gbps LVDS differential signaling which has

the added benefit of reducing EMI emissions relative to GMII or RGMII.

Because the internal clock and data recovery circuitry (CDR) of DP83867 can detect the transmit timing of the

SGMII data, TX_CLK is not required. SGMII interface is capable of working as a 4-wire or 6-wire SGMII

interface. The default SGMII connection is through four wires. Two differential pairs are used for the transmit and

receive connections. Clock and data recovery are performed in the MAC and in the PHY, so no additional

differential pair is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the

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SGMII receive data, the DP83867 can be configured to provide the SGMII receive clock through a differential

pair.

The 1.25-Gbps rate of SGMII is excessive for 100-Mbps operation. When operating in 100-Mbps mode, the PHY

elongates the frame by replicating each frame byte 10 times. This frame elongation takes place above the IEEE

802.3 PCS layer, thus the start of frame delimiter only appears once per frame.

The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control

information to be exchanged between the PHY and the MAC. This allows the interface to be automatically

configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII

speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced

speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation.

The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI

resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual

speed mode. SGMII Auto-Negotiation can be disabled through the SGMII_AUTONEG_EN register bit in the

CFG2 register (address 0x0014).

The 10M_SGMII_RATE_ADAPT bit (bit 7) does not need to be changed for 10M speed as the PHY will

automatically adapt the rate of SGMII.

SGMII is enabled through a resistor strap option. See 节8.5.1 for details.

All SGMII connections must be AC-coupled through an 0.1-µF capacitor. PHY has inbuilt 100 Ω differential

termination at receive and transmit pins of SGMII.

The connection diagrams for 4-wire SGMII and 6-wire SGMII are shown in 图8-4 and 图8-5.

PHY

MAC

0.1 µF

SGMII_SIP

SGMII_SIN

0.1 µF

SGMII_SOP

SGMII_SON

图8-4. SGMII 4-Wire Connections

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PHY

MAC

0.1 µF

SGMII_SIP

SGMII_SIN

0.1 µF

SGMII_SOP

SGMII_SON

SGMII_COP

SGMII_CON

0.1 µF

图8-5. SGMII 6-Wire Connections

8.4.1.2 Reduced GMII (RGMII)

The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to

interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data

paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the

clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-

Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.

For more information about RGMII timing, see the RGMII Interface Timing Budgets application report

(SNLA243).

8.4.1.2.1 1000-Mbps Mode Operation

All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The

lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The

control signals are multiplexed into a single clock cycle using the same technique.

To reduce power consumption of RGMII interface, TXEN_ER and RXDV_ER are encoded in a manner that

minimizes transitions during normal network operation. This is done by following encoding method. Note that the

value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock. In RGMII mode, GMII_TX_ER

is presented on TX_CTRL at the falling edge of the GTX_CLK clock. RX_CTRL coding is implemented the same

fashion.

When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of

RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is

being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL =

False is generated as a logic low on the falling edge of RX_CLK.

TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for

both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low

for both edges.

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8.4.1.2.2 1000-Mbps Mode Timing

The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the

interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path

support 16 programmable RGMII delay modes through register configuration. Strap configuration can also be

used to configure 8 programmable RGMII modes for both the transmit and receive paths. See 节 8.5.1 for

details.

The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is

introduced. In Shift mode, the clock skew can be introduced in 0.5-ns increments (through strap configuration) or

in 0.25-ns increments (through register configuration). Configuration of the Aligned mode or Shift mode is

accomplished through the RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew

can be adjusted using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086.

8.4.1.2.3 10- and 100-Mbps Mode

When the RGMII interface is operating in the 100-Mbps mode, the Ethernet Media Independent Interface (MII) is

implemented by reducing the clock rate to 25 MHz. For 10-Mbps operation, the clock is further reduced to 2.5

MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive

clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may

be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock to

a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or

negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.

This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the

exception that the data may be duplicated on the falling edge of the appropriate clock.

The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY.

PHY

MAC

TX_CTRL

GTX_CLK

TX_D [3:0]

RX_CTRL

RX_CLK

RX_D [3:0]

图8-6. RGMII Connections

8.4.2 Serial Management Interface

The Serial Management Interface (SMI), provides access to the DP83867 internal register space for status

information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register

set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and

controllability of the DP83867 device.

The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is

sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of

25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when

the bus is idle.

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The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched

on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2 kΩ) which, during IDLE and

turnaround, pulls MDIO high.

Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used. During

power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address. The

DP83867IRPAP 64-pin variant can support up to 32 PHYs and uses a 5-bit address.

The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid

operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal

MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus

allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The

data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes

sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time

inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no

device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83867 drives the

MDIO with a zero for the second bit of turnaround and follows this with the required data. 图 8-7 shows the

timing relationship between MDC and the MDIO as driven and received by the Station (STA) and the DP83867

(PHY) for a typical register read access.

For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating

the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting <10>.

图 8-7 shows the timing relationship for a typical MII register write access. The frame structure and general read

and write transactions are shown in 表8-2, 图8-7, and 图8-8.

表8-2. Typical MDIO Frame Format

TYPICAL MDIO FRAME FORMAT

Read Operation

Write Operation

图8-7. Typical MDC/MDIO Read Operation

图8-8. Typical MDC/MDIO Write Operation

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8.4.2.1 Extended Address Space Access

The DP83867 SMI function supports read or write access to the extended register set using registers REGCR

(0x000Dh) and ADDAR (0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE

802.3ah Draft for clause 22 for accessing the clause 45 extended register set.

The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the

indirect method, except for register REGCR (0x000Dh) and ADDAR (0x000Eh) which is accessed only using the

normal MDIO transaction. The SMI function ignores indirect accesses to these registers.

REGCR (0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the

device address DEVAD that directs any accesses of ADDAR (0x000Eh) register to the appropriate MMD.

The DP83867 supports one MMD device address. The vendor-specific device address DEVAD[4:0] = 11111 is

used for general MMD register accesses.

All accesses through registers REGCR and ADDAR must use the correct DEVAD. Transactions with other

DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),

data with post increment on read and writes (10) and data with post increment on writes only (11).

• ADDAR is the address and data MMD register. ADDAR is used in conjunction with REGCR to provide the

access to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the

extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its

address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended

register set address register. This address register must always be initialized to access any of the registers

within the extended register set.

• When REGCR[15:14] is set to 01, accesses to register ADDAR access the register within the extended

register set selected by the value in the address register.

• When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register

set selected by the value in the address register. After that access is complete, for both reads and writes, the

value in the address register is incremented.

• When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register

set selected by the value in the address register. After that access is complete, for write accesses only, the

value in the address register is incremented. For read accesses, the value of the address register remains

unchanged.

The following sections describe how to perform operations on the extended register set using register REGCR

and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] = 11111).

8.4.2.1.1 Write Address Operation

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

Subsequent writes to register ADDAR (step 2) continue to write the address register.

8.4.2.1.2 Read Address Operation

To read the address register:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Read the register address from register ADDAR.

8.4.2.1.3 Write (No Post Increment) Operation

To write a register in the extended register set:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the

address register.

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Note: steps (1) and (2) can be skipped if the address register was previously configured.

8.4.2.1.4 Read (No Post Increment) Operation

To read a register in the extended register set:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Read the content of the desired extended register set register to register ADDAR.

Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the

address register.

Note: steps (1) and (2) can be skipped if the address register was previously configured.

8.4.2.1.5 Write (Post Increment) Operation

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the register address from register ADDAR.

3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) or the

value 0xC01F (data, post increment on writes function field = 11. DEVAD = 31) to register REGCR.

4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the

value of the address register; the address register is incremented after each access.

8.4.2.1.6 Read (Post Increment) Operation

To read a register in the extended register set and automatically increment the address register to the next

higher value following the write operation:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) to

register REGCR.

4. Read the content of the desired extended register set register to register ADDAR.

Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the

value of the address register; the address register is incremented after each access.

8.4.2.1.7 Example of Read Operation Using Indirect Register Access

Read register 0x0170.

1. Write register 0x0D to value 0x001F.

2. Write register 0x0E to value 0x0170

3. Write register 0x0D to value 0x401F.

4. Read register 0x0E.

The expected default value is 0x0C10.

8.4.2.1.8 Example of Write Operation Using Indirect Register Access

Write register 0x0170 to value 0x0C50.

1. Write register 0x0D to value 0x001F.

2. Write register 0x0E to value 0x0170

3. Write register 0x0D to value 0x401F.

4. Write register 0x0E to value 0x0C50.

This write disables the output clock on the CLK_OUT pin.

8.4.3 Auto-Negotiation

All 1000BASE-T PHYs are required to support Auto-Negotiation. The Auto-Negotiation function in 1000BASE-T

has three primary purposes:

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• Auto-Negotiation of Speed and Duplex Selection

• Auto-Negotiation of Master or Slave Resolution

• Auto-Negotiation of Pause or Asymetrical Pause Resolution

8.4.3.1 Speed and Duplex Selection - Priority Resolution

The Auto-Negotiation function provides a mechanism for exchanging configuration information between the two

ends of a link segment. This mechanism is implemented by exchanging Fast Link Pulses (FLP). FLPs are burst

pulses that provide the signalling used to communicate the abilities between two devices at each end of a link

segment. For further details regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3 specification. The

DP83867 supports 1000BASE-T, 100BASE-TX, and 1000BASE-T modes of operation. The process of Auto-

Negotiation ensures that the highest performance protocol is selected (that is, priority resolution) based on the

advertised abilities of the Link Partner and the local device.

8.4.3.2 Master and Slave Resolution

If 1000BASE-T mode is selected during the priority resolution, the second goal of Auto-Negotiation is to resolve

Master or Slave configuration. The Master mode priority is given to the device that supports multiport nodes,

such as switches and repeaters. Single node devices such as DTE or NIC card takes lower Master mode priority.

8.4.3.3 Pause and Asymmetrical Pause Resolution

When Full-Duplex operation is selected during priority resolution, the Auto-Negotiation also determines the Flow

Control capabilities of the two link partners. Flow control was originally introduced to force a busy station’s Link

Partner to stop transmitting data in Full-Duplex operation. Unlike Half-Duplex mode of operation where a link

partner could be forced to back off by simply generating collisions, the Full-Duplex operation needed a

mechanism to slow down transmission from a link partner in the event that the receiving station’s buffers are

becoming full. A new MAC control layer was added to handle the generation and reception of Pause Frames.

Each MAC Controller has to advertise whether it is capable of processing Pause Frames. In addition, the MAC

Controller advertises if Pause frames can be handled in both directions, that is, receive and transmit. If the MAC

Controller only generates Pause frames but does not respond to Pause frames generated by a link partner, it is

called Asymmetrical Pause. The advertisement of Pause and Asymmetrical Pause capabilities is enabled by

writing 1 to bits 10 and 11 of ANAR (register address 0x0004). The link partner’s Pause capabilities is stored in

ANLPAR (register address 0x0005) bits 10 and 11. The MAC Controller has to read from ANLPAR to determine

which Pause mode to operate. The PHY layer is not involved in Pause resolution other than simply advertising

and reporting of Pause capabilities.

8.4.3.4 Next Page Support

The DP83867 supports the Auto-Negotiation Next Page protocol as required by IEEE 802.3 clause 28.2.4.1.7.

The ANNPTR 0x07 allows for the configuration and transmission of the Next Page. Refer to clause 28 of the

IEEE 802.3 standard for detailed information regarding the Auto-Negotiation Next Page function.

8.4.3.5 Parallel Detection

The DP83867 supports the Parallel Detection function as defined in the IEEE 802.3 specification. Parallel

Detection requires the 10/100-Mbps receivers to monitor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that

the Link Partner does not support Auto-Negotiation, yet is transmitting link signals that the 10BASE-Te or

100BASE-X PMA recognize as valid link signals.

If the DP83867 completes Auto-Negotiation as a result of Parallel Detection, without Next Page operation, bits 5

and 7 of ANLPAR (register address 0x0005) are set to reflect the mode of operation present in the Link Partner.

Note that bits 4:0 of the ANLPAR are also set to 00001 based on a successful parallel detection to indicate a

valid 802.3 selector field. Software may determine that the negotiation is completed through Parallel Detection

by reading 0 in bit 0 of ANER (register address 0x006) after Auto-Negotiation Complete, bit 5 of BMSR (register

address 0x0001), is set. If the PHY is configured for parallel detect mode and any condition other than a good

link occurs, the parallel detect fault, bit 4 of ANER (register address 0x06), sets.

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8.4.3.6 Restart Auto-Negotiation

If a link is established by successful Auto-Negotiation and then lost, the Auto-Negotiation process resumes to

determine the configuration for the link. This function ensures that a link can be re-established if the cable

becomes disconnected and reconnected. After Auto-Negotiation is completed, it may be restarted at any time by

writing 1 to bit 9 of the BMCR (register address 0x0000). A restart Auto-Negotiation request from any entity, such

as a management agent, causes DP83867 to halt data transmission or link pulse activity until the

break_link_timer expires. Consequently, the Link Partner goes into link fail mode and the resume Auto-

Negotiation. The DP83867 resumes Auto-Negotiation after the break_link_timer has expired by transmitting FLP

(Fast Link Pulse) bursts.

8.4.3.7 Enabling Auto-Negotiation Through Software

If Auto-Negotiation is disabled by MDIO access, and the user desires to restart Auto-Negotiation, this could be

accomplished by software access. Bit 12 of BMCR (register address 0x00) should be cleared and then set for

Auto-Negotiation operation to take place.

If Auto-Negotiation is disabled by strap option, Auto-Negotiation can not be reenabled.

8.4.3.8 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation typically take 2-3 seconds to complete. In addition, Auto-Negotiation with

next page exchange takes approximately 2-3 seconds to complete, depending on the number of next pages

exchanged. Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to

Auto-Negotiation

8.4.3.9 Auto-MDIX Resolution

The DP83867 can determine if a straight or crossover cable is used to connect to the link partner. It can

automatically re-assign channel A and B to establish link with the link partner, (and channel C and D in

1000BASE-T mode). Auto-MDIX resolution precedes the actual Auto-Negotiation process that involves

exchange of FLPs to advertise capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section

40.8.2. It is not a required implementation for 10BASE-Te and 100BASE-TX. DP83867 devices manufactured

after August, 2022, have an increased random seed value that now includes 255 different seed values to

expedite Auto-MDIX resolution with a link partner.

Auto-MDIX can be enabled or disabled by register configuration, using bit 6 of the PHYCR register (address

0x0010). When Auto-MDIX is disabled, the PMA is forced to either MDI (straight) or MDIX (crossed). Manual

configuration of MDI or MDIX can also be accomplished by register configuration, using bit 5 of the PHYCR

register.

For 10/100, Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX works in both Auto-Negotiation mode

and manual forced speed mode.

8.4.4 Loopback Mode

There are several options for Loopback that test and verify various functional blocks within the PHY. Enabling

loopback mode allows in-circuit testing of the digital and analog data paths. Generally, the DP83867 may be

configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. MII Loopback is

configured using the BMCR (register address 0x0000). All other loopback modes are enabled using the BISCR

(register address 0x16). Except where otherwise noted, loopback modes are supported for all speeds

(10/100/1000) and all MAC interfaces (SGMII and RGMII).

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Reverse

Loopback

PCS

Loopback

Analog

Loopback

MAC

MII

Loopback

Digital

Loopback

External

Loopback

图8-9. Loopbacks

The availability of Loopback depends on the operational mode of the PHY. The Link Status in these loopback

modes is also affected by the operational mode. 表 8-3 lists out the availability of Loopback Modes and their

corresponding Link Status indication.

表8-3. Loopback Availability

1000M

100M

10M

LOOPBACK

MODE

MAC INTERFACE

AVAILABILIT

LINK

STATUS

AVAILABILIT

LINK

STATUS

AVAILABILIT

Y

LINK STATUS

Y

MII

PCS

RGMII

SGMII

Yes

No

Yes

No

Yes

No

Yes

No

Digital

Analog

External

MII

Yes

No

Yes

No

Yes

No

Yes

No

Digital

IO

Yes

No

8.4.4.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver through the digital or

analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several

options being provided.

When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address 0x00FE, should

be set to 0xE720.

To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting the Near-End

Loopback mode. This constraint does not apply for external-loopback mode.

Auto-MDIX should be disabled before selecting the Near-End Loopback mode. MDI or MDIX configuration

should be manually configured.

8.4.4.1.1 MII Loopback

MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications

between the MAC and the PHY. While in MII Loopback mode the data is looped back, and can also be

configured through register to transmit onto the media.

8.4.4.1.2 PCS Loopback

PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS

Loopback.

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8.4.4.1.3 Digital Loopback

Digital Loopback includes the entire digital transmit – receive path. Data is looped back prior to the analog

circuitry.

8.4.4.1.4 Analog Loopback

Analog Loopback includes the entire analog transmit-receive path.

8.4.4.2 External Loopback

When operating in 10BASE-Te or 100Base-T mode, signals can be looped back at the RJ-45 connector by

wiring the transmit pins to the receive pins. Due to the nature of the signaling in 1000Base-T mode, this type of

external loopback is not supported. Analog loopback provides a way to loop data back in the analog circuitry

when operating in 1000Base-T mode. For proper operation in Analog Loopback mode, attach 100-Ω

terminations to the RJ45 connector.

8.4.4.3 Far-End (Reverse) Loopback

Far-end (Reverse) Loopback is a special test mode to allow testing the PHY from the link-partner side. In this

mode, data that is received from the link partner passes through the PHY's receiver, is looped back at the MAC

interface and is transmitted back to the link partner. While in Reverse Loopback mode, all data signals that come

from the MAC are ignored. Through register configuration, data can also be transmitted onto the MAC Interface.

8.4.5 BIST Configuration

The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST

can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The

BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on

the lines.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating a

continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for

the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback

Shift Register (LFSR) to determine the BIST pass or fail status. The number of error bytes that the PRBS

checker received is stored in the BICSR2 register (0x0072). The status of whether the PRBS checker is locked

to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy,

can be read from the STS2 register (0x0017h). While the lock and sync indications are required to identify the

beginning of proper data reception, for any link failures or data corruption, the best indication is the contents of

the error counter in the BICSR2 register (0x0072). The number of received bytes are stored in BICSR1 (0x0071).

The PRBS test can be put in a continuous mode by using bit 14 of the BISCR register (0x0016h). In continuous

mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero

again. Packet transmission can be configured for one of two types, 64 and 1518 bytes, through register bit 13 of

the BISCR register (0x0016).

8.4.6 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable

diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed

results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides

extensive information about cable integrity. The DP83867 offers, Time Domain Reflectometry (TDR) capability in

its Cable Diagnostic tools kit.

8.4.6.1 TDR

The DP83867 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and

terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed

include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross

shorts, and any other discontinuities along the cable.

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The DP83867 transmits a test pulse of known amplitude (1 V or 2.5 V) down each of the two pairs of an attached

cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad

connector, and from the end of the cable itself. After the pulse transmission, the DP83867 measures the return

time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude

(impedance) of non-terminated cables (open or short), discontinuities (bad connectors), improperly-terminated

cables, and crossed pairs wires with ±1-m accuracy.

The DP83867 also uses data averaging to reduce noise and improve accuracy. The DP83867 can record up to

five reflections within the tested pair. If more than 5 reflections are recorded, the DP83867 saves the first 5 of

them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the

tested channel. The DP83867 TDR can measure cables beyond 100 m in length.

For all TDR measurements, the transformation between time of arrival and physical distance is done by the

external host using minor computations (such as multiplication, addition, and lookup tables). The host must know

the expected propagation delay of the cable, which depends, among other things, on the cable category (for

example, CAT5, CAT5e, or CAT6).

TDR measurement is allowed in the DP83867 in the following scenarios:

• While Link partner is disconnected –cable is unplugged at the other side

• Link partner is connected but remains quiet (for example, in power-down mode)

• TDR could be automatically activated when the link fails or is dropped by setting bit 7 of register 0x0009

(CFG1). The results of the TDR run after the link fails are saved in the TDR registers.

Software could read these registers at any time to apply post processing on the TDR results. This mode is

designed for cases when the link dropped due to cable disconnections; after link failure, for instance, the line is

quiet to allow a proper function of the TDR.

8.4.6.2 Energy Detect

The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an

IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to

predefined thresholds to decide the presence or absence of an incoming signal. The energy detector also

implements hysteresis to avoid jittering in signal-detect indication. Additionally, it has fully-programmable

thresholds and listening-time periods, enabling shortening of the reaction time if required.

8.4.6.3 Fast Link Detect

Several advanced modes are available for fast link establishment. Unlike the Auto-Negotiation and Auto-MDIX

mechanisms defined by the IEEE 802.3 specification, these modes are specific to the DP83867. Take care when

implementing these modes. For best operation, TI recommends implementing these modes with a DP83867 on

both ends of the link.

These advanced link and crossover modes depend on the speed selected for the link. Some modes are

intended for use in 1000Base-T operation. Others are intended for use in 100Base-TX operation.

Fast Link Detect functionality can be configured using the Configuration Register 3 (CFG3), address 0x001E.

8.4.6.4 Speed Optimization

Speed optimization, also known as link downshift, enables fallback to 100-M operation after multiple consecutive

failed attempts at Gigabit link establishment. Such a case could occur if cabling with only four wires (two twisted

pairs) were connected instead of the standard cabling with eight wires (four twisted pairs).

The number of failed link attempts before falling back to 100-M operation is configurable. By default, four failed

link attempts are required before falling back to 100 M.

In enhanced mode, fallback to 100 M can occur after one failed link attempt if energy is not detected on the C

and D channels. Speed optimization also supports fallback to 10 M if link establishment fails in Gigabit and in

100-M mode.

Speed optimization can be enabled through register configuration.

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8.4.6.5 Mirror Mode

In some multiport applications, RJ-45 ports may be mirrored relative to one another. This mirroring can require

crossing board traces. The DP83867 can resolve this issue by implementing mirroring of the ports inside the

device.

In 10/100 operation, the mapping of the port mirroring is:

MDI MODE

MIRROR PORT CONFIGURATION

MDI

A →D

B →C

A →D

B →C

MDIX

In Gigabit operation, the mapping of the port mirroring is:

MDI MODE

MIRROR PORT CONFIGURATION

MDI or MDIX

A →D

B →C

C →B

D →A

Mirror mode can be enabled through strap or through register configuration using the Port Mirror Enable bit in

the CFG4 register (address 0x0031). In Mirror mode, the polarity of the signals is also reversed.

8.4.6.6 Interrupt

The DP83867 can be configured to generate an interrupt when changes of internal status occur. The interrupt

allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be

selected through the interrupt registers, MICR (register address 0x0012) and ISR (register address 0x0013).

8.4.6.7 IEEE 802.3 Test Modes

IEEE 802.3 specification for 1000BASE-T requires that the PHY layer be able to generate certain well defined

test patterns on TX outputs. Clause 40 section 40.6.1.1.2 Test Modes describes these tests in detail. There are

four test modes as well as the normal operation mode. These modes can be selected by writing to the CFG1

register (address 0x0009).

See IEEE 802.3 section 40.6.1.1.2 Test modes for more information on the nature of the test modes. The

DP83867 provides a test clock synchronous to the IEEE test patterns. The test patterns are output on the MDI

pins of the device and the transmit clock is output on the CLK_OUT pin.

For more information about configuring the DP83867 for IEEE 802.3 compliance testing, see the How to

Configure DP838XX for Ethernet Compliance Testing application report (SNLS239).

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8.5 Programming

8.5.1 Strap Configuration

The DP83867 uses many of the functional pins as strap options to place the device into specific modes of

operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap

options are internally reloaded from the values sampled at power up or hard reset. The strap option pin

assignments are defined below. The functional pin name is indicated in parentheses.

The strap pins supported are 4-level straps, which are described in greater detail below.

备注

Because strap pins may have alternate functions after reset is deasserted, they should not be

connected directly to VDD or GND.

Configuration of the device may be done through the 4-level strap pins or through the management register

interface. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of

the 4-level strap pin input and the supply to select one of the possible selected modes.

The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs are implemented

on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies.

For more information about configuring 4-level straps, see the Configuring Ethernet Devices with 4-Level Straps

application report (SNLA258).

VDDIO

DP83867

Rhi

V

STRAP

9kꢀ

25%

Rlo

图8-10. Strap Circuit

表8-4. 4-Level Strap Resistor Ratios

TARGET VOLTAGE

MODE

IDEAL Rhi (kΩ)

IDEAL Rlo (kΩ)

Vmin (V)

0

Vtyp (V)

0

Vmax (V)

1

2

3

4

0.098 × VDDIO

0.191 × VDDIO

0.284 × VDDIO

0.888 × VDDIO

OPEN

10

OPEN

2.49

0.140 × VDDIO

0.225 × VDDIO

0.694 × VDDIO

0.165 × VDDIO

0.255 × VDDIO

0.783 × VDDIO

5.76

2.49

OPEN

For SGMII Mode 4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2

and RX_D3.

All straps have a 9 kΩ ±25% internal pulldown resistor. The voltage at strap pins should be between the Vmin

and Vmax mentioned in the Target Voltage column in 表 8-4. Strap resistors with 1% tolerance are

recommended.

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The following tables describes the DP83867 configuration straps:

表8-5. 4-Level Strap Pins

PIN NAME

48 VQFN PIN #

DEFAULT

STRAP FUNCTION

MODE

PHY_ADD1

PHY_ADD0

1

0

RX_D0

33

[00]

2

0

1

3

1

0

4

1

MODE

PHY_ADD3

PHY_ADD2

1

0

1

0

RX_D2

35

38

[00]

2

1

3

0

4

1

MODE

Autoneg Disable

1

2

3

4

N/A

0

RX_CTRL ⁽¹⁾

1

RGMII Clock Skew

RX[0]

MODE

1

2

3

4

0

GPIO_0 ⁽²⁾

GPIO_1

LED_2

39

40

45

[00]

Not Applicable

1

Not Applicable

RGMII Clock Skew

RX[2]

RGMII Clock Skew

RX[1]

MODE

1

2

3

4

0

1

0

1

0

1

RGMII Clock Skew

TX[1]

RGMII Clock Skew

TX[0]

MODE

1

2

3

4

0

1

0

1

0

1

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表8-5. 4-Level Strap Pins (continued)

PIN NAME

48 VQFN PIN #

DEFAULT

STRAP FUNCTION

RGMII Clock Skew

TX[2]

MODE

ANEG_SEL

1

0

LED_1

46

[00]

2

0

1

3

1

0

4

1

MODE

Mirror Enable

SGMII Enable

1

2

3

4

0

1

0

1

0

1

LED_0

47

[00]

(1) Strap modes 1 and 2 are not applicable for RX_CTRL. The RX_CTRL strap must be configured for strap mode 3 or strap mode 4. If

the RX_CTRL pin cannot be strapped to mode 3 or mode 4, bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0.

Autoneg Disable should always be set to 0 when using gigabit Ethernet.

(2) Only Mode 1 and 3 are valid for GPIO_0. Mode 2 and 4 are not applicable and should not be used.

备注

RX_D1 is not a strap input, but this pin must be populated with the same strap resistors chosen for

RX_D0. RX_D0 and RX_D1 form an SGMII differential pair. The dummy straps on RX_D1 are

required to provide a balanced load for this SGMII differential pair.

备注

RX_D3 is not a strap input, but this pin must be populated with the same strap resistors chosen for

RX_D2. RX_D2 and RX_D3 form an SGMII differential pair. The dummy straps on RX_D3 are

required to provide a balanced load for this SGMII differential pair.

表8-6. Auto-Negotiation Select Strap Details

MODE

ANEG_SEL

REMARKS

advertise ability of 10/100/1000

advertise ability of 100/1000 only

10/100/1000

100/1000

0

1

表8-7. RGMII Transmit Clock Skew Details

RGMII CLOCK SKEW

TX[1]

RGMII CLOCK SKEW

MODE

RGMII TX CLOCK SKEW

TX[2]

TX[0]

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.0 ns

1.5 ns

1.0 ns

0.5 ns

0 ns

3.5 ns

3.0 ns

2.5 ns

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表8-8. RGMII Receive Clock Skew Details

RGMII CLOCK SKEW

RX[2]

RGMII CLOCK SKEW

RX[1]

RGMII CLOCK SKEW

RX[0]

MODE

RGMII RX CLOCK SKEW

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.0 ns

1.5 ns

1.0 ns

0.5 ns

0 ns

3.5 ns

3.0 ns

2.5 ns

8.5.2 LED Configuration

The DP83867 supports four configurable Light Emitting Diode (LED) pins: LED_0, LED_1, and LED_2. A GPIO

pin can also be configured to operate as LED_3. Several functions can be multiplexed onto the LEDs for

different modes of operation. The LED operation mode can be selected using the LEDCR1 register (address

0x0018).

Because the LED output pins are also used as straps, the external components required for strapping and LED

usage must be considered to avoid contention. Specifically, when the LED outputs are used to drive LEDs

directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN

input upon power up or reset.

If a given strap input is resistively pulled low then the corresponding output is configured as an active high driver.

In the context of the 4-level straps, this occurs for modes 1, 2, and 3. Conversely, if a given strap input is

resistively pulled high, then the corresponding output is configured as an active low driver. In the context of the

4-level straps, this occurs only for mode 4.

Refer to 图 8-11 for an example of strap connections to external components. In this example, the strapping

results in Mode 1 for LED_0 and Mode 4 for LED_1.

The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose

pins.

Mode 1

Mode 4

470Ω

VDD

GND

图8-11. Example Strap Connections

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8.5.3 LED Operation From 1.8-V I/O VDD Supply

Operation of LEDs from a 1.8-V supply results in dim LED lighting. For best results, the recommendation is to

operate from a higher supply (2.5 V or 3.3 V). Refer to 图8-12 for a possible implementation of this functionality.

2.5V or 3.3V

Mode 2

200 Ω

1.8V

10 kΩ

2.49 kΩ

GND

图8-12. LED Operation From 1.8-V I/O VDD Supply

8.5.4 PHY Address Configuration

The DP83867 can be set to respond to any of 16 possible PHY addresses through strap pins. The information is

latched into the device at a device power up or hardware reset. Each DP83867 or port sharing an MDIO bus in a

system must have a unique physical address. The DP83867 supports PHY address strapping values 0 (<0000>)

through 15 (<1111>).

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to 节8.5.5.

Based on the default strap configuration of PHY_ADD[3:0], the DP83867 PHY address initializes to 0x00 without

any external strap configuration.

Refer to 图 8-13 for an example of a PHY address connection to external components. In this example, the pins

are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address

strapping results in address 1001 (09h).

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VDDIO

10 kΩ

RX_D0

VDDIO

2.49 kΩ

5.76 kΩ

RX_D2

2.49 kΩ

图8-13. PHY Address Strapping Example

When operating in SGMII mode, dummy straps must be added to provide a balanced load for the SGMII

differential pairs. Therefore, for SGMII applications with the straps shown in 图 8-13, the corresponding

connections for RX_D1 and RX_D3 are shown in 图8-14.

VDDIO

10 kΩ

RX_D1

2.49 kΩ

VDDIO

5.76 kΩ

RX_D3

2.49 kΩ

图8-14. PHY Address Strapping Example for SGMII

8.5.5 Reset Operation

The DP83867 includes an internal power-on-reset (POR) function and therefore does not need to be explicitly

reset for normal operation after power up. If required during normal operation, the device can be reset by a

hardware or software reset.

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8.5.5.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse, with a duration of at least 1 μs, to the RESET_N pin.

This resets the device such that all registers are reinitialized to default values and the hardware configuration

values are re-latched into the device (similar to the power up or reset operation).

8.5.5.2 IEEE Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (address

0x0000). This bit resets the IEEE-defined standard registers.

8.5.5.3 Global Software Reset

A global software reset is accomplished by setting bit 15 of register CTRL (address 0x001F) to 1. This bit resets

all the internal circuits in the PHY including IEEE-defined registers and all the extended registers. The global

software reset resets the device such that all registers are reset to default values and the hardware configuration

values are maintained.

8.5.5.4 Global Software Restart

A global software restart is accomplished by setting bit 14 of register CTRL (0x001F) to 1. This action resets all

the PHY circuits except the registers in the Register File.

8.5.5.5 PCS Restart

A PCS reset is accomplished by setting bit 15 of register MMD3_PCS_CTRL (MMD3 register 0x0000). Setting

this bit resets the MMD3 register. This bit subsequently cause a soft reset through the BMCR RESET bit (bit 15

of register address 0x0000).

8.5.6 Power-Saving Modes

DP83867 supports 4 power saving modes. The details are provided below.

8.5.6.1 IEEE Power Down

The PHY is powered down but access to the PHY through MDIO-MDC pins is retained. This mode can be

activated by asserting external PWDN pin or by setting bit 11 of BMCR (Register 0x00).

The PHY can be taken out of this mode by a power cycle, software reset, or by clearing the bit 11 in BMCR

register. However, the external PWDN pin should be deasserted. If the PWDN pin is kept asserted then the PHY

remains in power down.

8.5.6.2 Deep Power-Down Mode

This same as IEEE power down but the XI pad is also turned off. This mode can be activated by asserting the

external PWDN pin or by setting bit 11 of BMCR (Register 0x00). Before activating this mode, it is required to set

bit 7 for PHYCR (Register 0x10).

The PHY can be taken out of this mode by a power cycle, software reset or by clearing the bit 11 in BMCR

register. However, the external PWDN pin should be de-asserted. If the PWDN pin is kept asserted then the PHY

remains in power down.

8.5.6.3 Active Sleep

In this mode, all the digital and analog blocks are powered down. The PHY is automatically powered up when a

link partner is detected. This mode is useful for saving power when the link partner is down or inactive, but PHY

cannot be powered down. In Active Sleep mode, the PHY still routinely sends NLP to the link partner. This mode

can be active by writing binary 10 to bits [9:8] for PHYCR (Register 0x10).

8.5.6.4 Passive Sleep

This is just like Active sleep except the PHY does not send NLP. This mode can be activated by writing binary 11

to bits [9:8] PHYCR (Register 0x10).

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8.6 Register Maps

In the register definitions under the ‘Default’heading, the following definitions hold true:

RW

Read Write access

SC

Register sets on event occurrence and Self-Clears when event ends

ReadWrite access/Self Clearing bit

Read Only access

RW/SC

RO

COR

COR = Clear On Read

RO/COR Read Only, Clear On Read

RO/P

LL

Read Only, Permanently set to a default value

Latched Low and held until read, based upon the occurrence of the corresponding event

Latched High and held until read, based upon the occurrence of the corresponding event

Default value loaded from bootstrap pin after reset

LH

Strap

8.6.1 Basic Mode Control Register (BMCR)

表8-9. Basic Mode Control Register (BMCR), Address 0x0000

BIT

BIT NAME

DEFAULT

0, RW/SC

DESCRIPTION

15

14

RESET

Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is restrapped.

LOOPBACK

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MAC transmit data to be routed to

the MAC receive data path.

Setting this bit may cause the descrambler to lose synchronization

and produce a 500-µs dead time before any valid data will appear at

the MII receive outputs.

13

SPEED SELECTION LSB

0, RW

Speed Select (Bits 6, 13):

When auto-negotiation is disabled writing to this bit allows the port

speed to be selected.

11 = Reserved

10 = 1000 Mbps

1 = 100 Mbps

0 = 10 Mbps

12

11

AUTO-NEGOTIATION ENABLE Strap, RW

Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are

ignored when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port

speed and duplex mode.

POWER DOWN

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is

enabled during a power down condition. This bit is ORd with the

input from the PWRDOWN_INT pin. When the active low

PWRDOWN_INT pin is asserted, this bit will be set.

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表8-9. Basic Mode Control Register (BMCR), Address 0x0000 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

10

9

ISOLATE

0, RW

Isolate:

1 = Isolates the Port from the MII with the exception of the serial

management.

0 = Normal operation.

RESTART AUTO-NEGOTIATION 0, RW/SC

Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation

process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is

ignored. This bit is self-clearing and will return a value of 1 until

Auto-Negotiation is initiated, whereupon it will self-clear. Operation of

the Auto-Negotiation process is not affected by the management

entity clearing this bit.

0 = Normal operation.

8

7

DUPLEX MODE

Strap, RW

0, RW

Duplex Mode:

When auto-negotiation is disabled writing to this bit allows the port

Duplex capability to be selected.

1 = Full Duplex operation.

0 = Half Duplex operation.

COLLISION TEST

Collision Test:

1 = Collision test enabled.

0 = Normal operation.

When set, this bit will cause the COL signal to be asserted in

response to the assertion of TX_EN within 512-bit times. The COL

signal will be deasserted within 4-bit times in response to the

deassertion of TX_EN.

6

SPEED SELECTION MSB

RESERVED

1, RW

Speed Select: See description for bit 13.

RESERVED: Write ignored, read as 0.

5:0

0 0000, RO

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8.6.2 Basic Mode Status Register (BMSR)

表8-10. Basic Mode Status Register (BMSR), Address 0x0001

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

13

12

11

10

9

100BASE-T4

0, RO/P

100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

100BASE-TX FULL DUPLEX

100BASE-TX HALF DUPLEX

10BASE-Te FULL DUPLEX

10BASE-Te HALF DUPLEX

100BASE-T2 FULL DUPLEX

100BASE-T2 HALF DUPLEX

EXTENDED STATUS

1, RO/P

0, RO/P

1, RO/P

0, RO

100BASE-TX Full Duplex Capable:

1 = Device able to perform 100BASE-TX in full duplex mode.

100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

10BASE-Te Full Duplex Capable:

1 = Device able to perform 10BASE-Te in full duplex mode.

10BASE-Te Half Duplex Capable:

1 = Device able to perform 10BASE-Te in half duplex mode.

100BASE-T2 Full Duplex Capable:

0 = Device not able to perform 100BASE-T2 in full duplex mode.

100BASE-T2 Half Duplex Capable:

0 = Device not able to perform 100BASE-T2 in half duplex mode.

8

1000BASE-T Extended Status Register:

1 = Device supports Extended Status Register 0x0F.

7

6

RESERVED

RESERVED: Write as 0, read as 0.

MF PREAMBLE SUPPRESSION 1, RO/P

Preamble Suppression Capable:

1 = Device able to perform management transaction with preamble

suppressed, 32-bits of preamble needed only once after reset,

invalid opcode or invalid turnaround.

0 = Normal management operation.

5

4

AUTO-NEGOTIATION

COMPLETE

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation process complete.

0 = Auto-Negotiation process not complete.

REMOTE FAULT

0, RO/LH

Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset).

Fault criteria: Far-End Fault Indication or notification from Link

Partner of Remote Fault.

0 = No remote fault condition detected.

3

2

AUTO-NEGOTIATION ABILITY

LINK STATUS

1, RO/P

Auto Negotiation Ability:

1 = Device is able to perform Auto-Negotiation.

0 = Device is not able to perform Auto-Negotiation.

0, RO/LL

Link Status:

1 = Valid link established.

0 = Link not established.

The criteria for link validity is implementation specific. The

occurrence of a link failure condition will causes the Link Status bit to

clear. Once cleared, this bit may only be set by establishing a good

link condition and a read through the management interface.

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表8-10. Basic Mode Status Register (BMSR), Address 0x0001 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1

0

JABBER DETECT

0, RO/LH

Jabber Detect: This bit only has meaning in 10-Mbps mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the

occurrence of a jabber condition causes it to set until it is cleared by

a read to this register by the management interface or by a reset.

EXTENDED CAPABILITY

1, RO/P

Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

8.6.3 PHY Identifier Register #1 (PHYIDR1)

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83867. The Identifier consists

of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model

revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The

PHY Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.

表8-11. PHY Identifier Register #1 (PHYIDR1), Address 0x0002

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

OUI_MSB

0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are

0000, RO/P

stored in bits 15 to 0 of this register. The most significant two bits of

the OUI are ignored (the IEEE standard refers to these as bits 1 and

2).

8.6.4 PHY Identifier Register #2 (PHYIDR2)

表8-12. PHY Identifier Register #2 (PHYIDR2), Address 0x0003

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:10

9:4

OUI_LSB

1010 00, RO/P OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of

this register respectively.

VNDR_MDL

MDL_REV

10 0011, RO/P Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4

(most significant bit to bit 9).

3:0

0001, RO/P

Model Revision Number:

Four bits of the vendor model revision number are mapped from bits

3 to 0 (most significant bit to bit 3). This field will be incremented for

all major device changes.

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8.6.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner during

Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic

Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a

renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.

表8-13. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

NP

0, RW

Next Page Indication:

0 = Next Page Transfer not desired.

1 = Next Page Transfer desired.

14

13

RESERVED

RF

0, RO/P

0, RW

RESERVED by IEEE: Writes ignored, Read as 0.

Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.

12

11

RESERVED

ASM_DIR

0, RW

RESERVED for Future IEEE use: Write as 0, Read as 0

Asymmetric PAUSE Support for Full Duplex Links:

The ASM_DIR bit indicates that asymmetric PAUSE is supported.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution

status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the optional

MAC control sublayer and the pause function as specified in clause

31 and annex 31B of 802.3u.

0 = No MAC based full duplex flow control.

10

PAUSE

0, RW

PAUSE Support for Full Duplex Links:

The PAUSE bit indicates that the device is capable of providing the

symmetric PAUSE functions as defined in Annex 31B.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution

status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the optional

MAC control sublayer and the pause function as specified in clause

31 and annex 31B of 802.3u.

0 = No MAC based full duplex flow control.

9

8

7

6

T4

0, RO/P

100BASE-T4 Support:

1 = 100BASE-T4 is supported by the local device.

0 = 100BASE-T4 not supported.

TX_FD

TX

Strap, RW

100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

100BASE-TX Support:

1 = 100BASE-TX is supported by the local device.

0 = 100BASE-TX not supported.

10_FD

10BASE-Te Full Duplex Support:

1 = 10BASE-Te Full Duplex is supported by the local device.

0 = 10BASE-Te Full Duplex not supported.

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表8-13. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

5

10BASETe_EN

Strap, RW

10BASE-Te Support:

1 = 10BASE-Te is supported by the local device.

0 = 10BASE-Te not supported.

4:0

SELECTOR

0 0001, RW

Protocol Selection Bits:

These bits contain the binary encoded protocol selector supported by

this port. <00001> indicates that this device supports IEEE 802.3u.

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8.6.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The

content changes after the successful Auto-Negotiation if Next pages are supported.

表8-14. Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

NP

0, RO

Next Page Indication:

0 = Link Partner does not desire Next Page Transfer.

1 = Link Partner desires Next Page Transfer.

ACK

0, RO

Acknowledge:

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control this bit

based on the incoming FLP bursts.

13

RF

Remote Fault:

1 = Remote Fault indicated by Link Partner.

0 = No Remote Fault indicated by Link Partner.

12

11

RESERVED

ASM_DIR

0, RO

RESERVED for Future IEEE use: Write as 0, read as 0.

ASYMMETRIC PAUSE:

1 = Asymmetric pause is supported by the Link Partner.

0 = Asymmetric pause is not supported by the Link Partner.

10

9

PAUSE

T4

0, RO

PAUSE:

1 = Pause function is supported by the Link Partner.

0 = Pause function is not supported by the Link Partner.

0, RO

100BASE-T4 Support:

1 = 100BASE-T4 is supported by the Link Partner.

0 = 100BASE-T4 not supported by the Link Partner.

8

TX_FD

TX

0, RO

100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the Link Partner.

0 = 100BASE-TX Full Duplex not supported by the Link Partner.

7

0, RO

100BASE-TX Support:

1 = 100BASE-TX is supported by the Link Partner.

0 = 100BASE-TX not supported by the Link Partner.

6

10_FD

10

0, RO

10BASE-Te Full Duplex Support:

1 = 10BASE-Te Full Duplex is supported by the Link Partner.

0 = 10BASE-Te Full Duplex not supported by the Link Partner.

5

0, RO

10BASE-Te Support:

1 = 10BASE-Te is supported by the Link Partner.

0 = 10BASE-Te not supported by the Link Partner.

4:0

SELECTOR

0 0000, RO

Protocol Selection Bits:

Link Partner's binary encoded protocol selector.

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8.6.7 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

表8-15. Auto-Negotiate Expansion Register (ANER), Address 0x0006

BIT

BIT NAME

RESERVED

DEFAULT

0, RO

DESCRIPTION

RESERVED: Writes ignored, Read as 0.

Receive Next Page Location Able:

1 = Received Next Page storage location is specified by bit 6.5.

0 = Received Next Page storage location is not specified by bit 6.5.

15:7

6

RX_NEXT_PAGE_LOC_ABLE

RX_NEXT_PAGE_STOR_LOC

PDF

1, RO

0, RO

5

4

3

Receive Next Page Storage Location:

1 = Link Partner Next Pages are stored in register 8.

0 = Link Partner Next Pages are stored in register 5.

Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function.

0 = A fault has not been detected.

LP_NP_ABLE

Link Partner Next Page Able:

1 = Link Partner does support Next Page.

0 = Link Partner does not support Next Page.

2

1

NP_ABLE

PAGE_RX

1, RO/P

Next Page Able:

1 = Indicates local device is able to send additional Next Pages.

0, RO/COR

Link Code Word Page Received:

1 = Link Code Word has been received, cleared on a read.

0 = Link Code Word has not been received.

0

LP_AN_ABLE

0, RO

Link Partner Auto-Negotiation Able:

1 = Indicates that the Link Partner supports Auto-Negotiation.

0 = Indicates that the Link Partner does not support Auto-

Negotiation.

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8.6.8 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

表8-16. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0007

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

13

12

NP

0, RW

Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired.

ACK

MP

0, RO

1, RW

0, RW

Acknowledge:

1 = Acknowledge reception of link code word

0 = Do not acknowledge of link code word.

Message Page:

1 = Current page is a Message Page.

0 = Current page is an Unformatted Page.

ACK2

Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by the next page function to indicate that

Local Device has the ability to comply with the message received.

11

TOG_TX

0, RO

Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word was

0.

0 = Value of toggle bit in previously transmitted Link Code Word was

1.

Toggle is used by the Arbitration function within Auto-Negotiation to

ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Toggle

bit in the previously exchanged Link Code Word.

10:0

CODE

000 0000 0001, Code:

RW This field represents the code field of the next page transmission. If

the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in Annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformatted

Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in

Annex 28C of IEEE 802.3u.

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8.6.9 Auto-Negotiation Next Page Receive Register (ANNPRR)

This register contains the next page information sent by the Link Partner during Auto-Negotiation.

表8-17. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0008

BIT

BIT NAME

DEFAULT

0, RW

DESCRIPTION

15

14

13

12

NP

Next Page Indication:

0 = No other Next Page Transfer desired by the link partner.

1 = Another Next Page desired by the link partner.

ACK

MP

0, RO

1, RW

0, RW

Acknowledge:

1 = Acknowledge reception of link code word by the link partner.

0 = Link partner does not acknowledge reception of link code word.

Message Page:

1 = Received page is a Message Page.

0 = Received page is an Unformatted Page.

ACK2

Acknowledge2:

1 = Link partner sets the ACK2 bit.

0 = Link partner coes not set the ACK2 bit.

Acknowledge2 is used by the next page function to indicate that link

partner has the ability to comply with the message received.

11

TOG_TX

0, RO

Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word was

0.

0 = Value of toggle bit in previously transmitted Link Code Word was

1.

Toggle is used by the Arbitration function within Auto-Negotiation to

ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Toggle

bit in the previously exchanged Link Code Word.

10:0

CODE

000 0000 0001, Code:

RW This field represents the code field of the next page transmission. If

the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in Annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformatted

Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in

Annex 28C of IEEE 802.3u.

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8.6.10 1000BASE-T Configuration Register (CFG1)

表8-18. Configuration Register 1 (CFG1), Address 0x0009

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

TEST MODE

000, RW

Test Mode Select:

111 = Test Mode 7 - Repetitive {Pulse, 63 zeros}

110 = Test Mode 6 - Repetitive 0001 sequence

101 = Test Mode 5 - Scrambled MLT3 Idles

100 = Test Mode 4 - Transmit Distortion Test

011 = Test Mode 3 - Transmit Jitter Test (Slave Mode)

010 = Test Mode 2 - Transmit Jitter Test (Master Mode)

001 = Test Mode 1 - Transmit Waveform Test

000 = Normal Mode

12

11

MASTER / SLAVE MANUAL

CONFIGURATION

0, RW

Enable Manual Master / Slave Configuration:

1 = Enable Manual Master/Slave Configuration control.

0 = Disable Manual Master/Slave Configuration control.

Using the manual configuration feature may prevent the PHY from

establishing link in 1000Base-T mode if a conflict with the link

partner’s setting exists.

MASTER / SLAVE

CONFIGURATION VALUE

Manual Master / Slave Configuration Value:

1 = Set PHY as MASTER when register 09h bit 12 = 1.

0 = Set PHY as SLAVE when register 09h bit 12 = 1.

Using the manual configuration feature may prevent the PHY from

establishing link in 1000Base-T mode if a conflict with the link

partner’s setting exists.

10

9

PORT TYPE

Advertise Device Type: Multi or single port:

1 = Multi-port device.

0 = Single-port device.

1000BASE-T FULL DUPLEX

1000BASE-T HALF DUPLEX

TDR AUTO RUN

RGZ: 1, RW

Advertise 1000BASE-T Full Duplex Capable:

1 = Advertise 1000Base-T Full Duplex ability.

0 = Do not advertise 1000Base-T Full Duplex ability.

PAP: Strap, RW

8

1, RW

Advertise 1000BASE-T Half Duplex Capable:

1 = Advertise 1000Base-T Half Duplex ability.

0 = Do not advertise 1000Base-T Half Duplex ability.

7

0, RW

Automatic TDR on Link Down:

1 = Enable execution of TDR procedure after link down event.

0 = Disable automatic execution of TDR.

6:0

RESERVED

000 0000, RO

RESERVED: Write ignored, read as 0.

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8.6.11 Status Register 1 (STS1)

表8-19. Status Register 1 (STS1) Address 0x000A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

13

12

11

10

MASTER / SLAVE

CONFIGURATION FAULT

0, RO, LH, COR Master / Slave Manual Configuration Fault Detected:

1 = Manual Master/Slave Configuration fault detected.

0 = No Manual Master/Slave Configuration fault detected.

MASTER / SLAVE

CONFIGURATION

RESOLUTION

0, RO

00, RO

Master / Slave Configuration Results:

1 = Configuration resolved to MASTER.

0 = Configuration resolved to SLAVE.

LOCAL RECEIVER STATUS

REMOTE RECEIVER STATUS

1000BASE-T FULL DUPLEX

1000BASE-T HALF DUPLEX

Local Receiver Status:

1 = Local receiver is OK.

0 = Local receiver is not OK.

Remote Receiver Status:

1 = Remote receiver is OK.

0 = Remote receiver is not OK.

Link Partner 1000BASE-T Full Duplex Capable:

1 = Link Partner capable of 1000Base-T Full Duplex.

0 = Link partner not capable of 1000Base-T Full Duplex.

Link Partner 1000BASE-T Half Duplex Capable:

1 = Link Partner capable of 1000Base-T Half Duplex.

0 = Link partner not capable of 1000Base-T Half Duplex.

9:8

7:0

RESERVED

RESERVED by IEEE: Writes ignored, read as 0.

IDLE ERROR COUNTER

0000 0000, RO, 1000BASE-T Idle Error Counter

COR

8.6.12 Extended Register Addressing

REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above

0x001F) using indirect addressing.

• REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address

register must be initialized to access any of the registers within the extended register set.

• •REGCR [15:14] = 01: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. The address register contents (pointer) remain

unchanged.

• REGCR [15:14] = 10: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. After that access is complete, for both reads and

writes, the value in the address register is incremented.

• REGCR [15:14] = 11: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. After that access is complete, for write accesses

only, the value in the address register is incremented. For read accesses, the value of the address register

remains unchanged.

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8.6.12.1 Register Control Register (REGCR)

This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device

address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR

also contains selection bits for auto increment of the data register. This register contains the device address to

be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains

selection bits (15:14) for the address auto-increment mode of ADDAR.

表8-20. Register Control Register (REGCR), Address 0x000D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:14

Function

0, RW

00 = Address

01 = Data, no post increment

10 = Data, post increment on read and write

11 = Data, post increment on write only

13:5

4:0

RESERVED

DEVAD

0, RO

0, RW

RESERVED: Writes ignored, read as 0.

Device Address: In general, these bits [4:0] are the device address

DEVAD that directs any accesses of ADDAR register (0x000E) to the

appropriate MMD. Specifically, the DP83867 uses the vendor specific

DEVAD [4:0] = 11111 for accesses. All accesses through registers

REGCR and ADDAR should use this DEVAD. Transactions with

other DEVAD are ignored.

8.6.12.2 Address or Data Register (ADDAR)

This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to

provide the access by indirect read/write mechanism to the extended register set.

表8-21. Address or Data Register (ADDAR) address 0x000E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

Address / Data

0, RW

If REGCR register 15:14 = 00, holds the MMD DEVAD's address

register, otherwise holds the MMD DEVAD's data register

8.6.13 1000BASE-T Status Register (1KSCR)

表8-22. 1000BASE-T Status Register (1KSCR) address 0x000F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

1000BASE-X FULL DUPLEX

0, RO/P

1000BASE-X Full Duplex Support:

1 = 1000BASE-X Full Duplex is supported by the local device.

0 = 1000BASE-X Full Duplex is not supported by the local device.

14

1000BASE-X HALF DUPLEX

1000BASE-T FULL DUPLEX

1000BASE-T HALF DUPLEX

RESERVED

0, RO/P

1, RO/P

00, RO

1000BASE-X Half Duplex Support:

1 = 1000BASE-X Half Duplex is supported by the local device.

0 = 1000BASE-X Half Duplex is not supported by the local device.

13

1000BASE-T Full Duplex Support:

1 = 1000BASE-T Full Duplex is supported by the local device.

0 = 1000BASE-T Full Duplex is not supported by the local device.

12

1000BASE-T Half Duplex Support:

1 = 1000BASE-T Half Duplex is supported by the local device.

0 = 1000BASE-T Half Duplex is not supported by the local device.

11:0

RESERVED by IEEE: Writes ignored, read as 0.

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8.6.14 PHY Control Register (PHYCR)

表8-23. PHY Control Register (PHYCR), Address 0x0010

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:14

TX FIFO Depth

1, RW

TX FIFO Depth:

11 = 8 bytes/nibbles (1000Mbps/Other Speeds)

10 = 6 bytes/nibbles (1000Mbps/Other Speeds)

01 = 4 bytes/nibbles (1000Mbps/Other Speeds)

00 = 3 bytes/nibbles (1000Mbps/Other Speeds)

Note: FIFO is enabled only in the following modes:

1000BaseT + GMII

10BaseT/100BaseTX/1000BaseT + SGMII

13:12

RX FIFO Depth

1, RW

RX FIFO Depth:

11 = 8 bytes/nibbles (1000 Mbps/Other Speeds)

10 = 6 bytes/nibbles (1000 Mbps/Other Speeds)

01 = 4 bytes/nibbles (1000 Mbps/Other Speeds)

00 = 3 bytes/nibbles (1000 Mbps/Other Speeds)

Note: FIFO is enabled only in SGMII

11

SGMII_EN

Strap, RW

0, RW

SGMII Enable:

1 = Enable SGMII

0 = Disable SGMII

10

9:8

FORCE_LINK_GOOD

POWER_SAVE_MODE

Force Link Good:

1 = Force link good according to the selected speed.

0 = Normal operation

0, RW

Power-Saving Modes:

11 = Passive Sleep mode: Power down all digital and analog blocks.

10 =Active Sleep mode: Power down all digital and analog blocks.

Automatic power-up is performed when link partner is detected. Link

pulses are transmitted approximately once per 1.4 Sec in this mode

to wake up any potential link partner.

01 = IEEE mode: power down all digital and analog blocks.

Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the

PLL is also powered down.

00 = Normal mode

7

DEEP_POWER_DOWN_EN

0, RW

Deep power-down mode enable

1 = When power down is initiated through assertion of the external

power-down pin or through the POWER_DOWN bit in the BMCR, the

device enters a deep power-down mode.

0 = Normal operation.

6:5

4

MDI_CROSSOVER

DISABLE_CLK_125

RGZ: 10, RW

MDI Crosssover Mode:

1x = Enable automatic crossover

01 = Manual MDI-X configuration

00 = Manual MDI configuration

PAP: Strap, RW

0, RW

Disable 125MHz Clock:

This bit may be used in conjunction with POWER_SAVE_MODE (bits

9:8 of this register).

1 = Disable CLK125.

0 = Enable CLK125.

3

2

RESERVED

1, RO

0, RW

RESERVED: Writes ignored, read as 1.

STANDBY_MODE

Standby Mode:

1 = Enable standby mode. Digital and analog circuitry are powered

up, but no link can be established.

0 = Normal operation.

1

0

LINE_DRIVER_INV_EN

DISABLE_JABBER

0, RW

Line Driver Inversion Enable:

1 = Invert Line Driver Transmission.

0 = Normal operation.

Disable Jabber

1 = Disable Jabber function.

0 = Enable Jabber function.

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8.6.15 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed

information.

表8-24. PHY Status Register (PHYSTS), Address 0x0011

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:14

SPEED SELECTION

0, RO

Speed Select Status:

These two bits indicate the speed of operation as determined by

Auto-Negotiation or as set by manual configuration.

11 = Reserved

10 = 1000 Mbps

01 = 100 Mbps

00 = 10 Mbps

13

12

DUPLEX MODE

0, RO

Duplex Mode Status:

1 = Full Duplex

0 = Half Duplex.

PAGE RECEIVED

0, RO, LH, COR Page Received:

This bit is latched high and will be cleared upon a read.

1 = Page received.

0 = No page received.

11

10

9

SPEED DUPLEX RESOLVED

LINK_STATUS

0, RO

Speed Duplex Resolution Status:

1 = Auto-Negotiation has completed or is disabled.

0 = Auto-Negotiation is enabled and has not completed.

Link Status:

1 = Link is up.

0 = Link is down.

MDI_X_MODE_CD

MDI_X_MODE_AB

MDI/MDIX Resolution Status for C and D Line Driver Pairs:

1 = Resolved as MDIX

0 = Resolved as MDI.

8

MDI/MDIX Resolution Status for A and B Line Driver Pairs:

1 = Resolved as MDIX

0 = Resolved as MDI.

7

SPEED_OPT_STATUS

Speed Optimization Status:

1 = Auto-Negotiation is currently being performed with Speed

Optimization masking 1000BaseT abilities (Valid only during Auto-

Negotiation).

0 = Auto-Negotiation is currently being performed without Speed

Optimization.

6

SLEEP_MODE

WIRE_CROSS

0, RO

Sleep Mode Status:

1 = Device currently in sleep mode.

0 = Device currently in active mode.

5:2

Crossed Wire Indication:

Indicates channel polarity in 1000BASE-T linked status. Bits [5:2]

correspond to channels [D,C,B,A], respectively.

1 = Channel polarity is reversed.

0 = Channel polarity is normal.

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表8-24. PHY Status Register (PHYSTS), Address 0x0011 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1

0

POLARITY STATUS

1, RO

10BASE-Te Polarity Status:

1 = Correct Polarity detected.

0 = Inverted Polarity detected.

JABBER DETECT

0, RO

Jabber Detect: This bit only has meaning in 10 Mbps mode.

This bit is a duplicate of the Jabber Detect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

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8.6.16 MII Interrupt Control Register (MICR)

This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be

enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register

is set, an interrupt is generated if the event occurs.

表8-25. MII Interrupt Control Register (MICR), Address 0x0012

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

13

12

11

10

AUTONEG_ERR_INT_EN

0, RW

Enable Auto-Negotiation Error Interrupt:

1 = Enable Auto-Negotiation Error interrupt.

0 = Disable Auto-Negotiation Error interrupt.

SPEED_CHNG_INT_EN

0, RW

Enable Speed Change Interrupt:

1 = Enable Speed Change interrupt.

0 = Disable Speed Change interrupt.

DUPLEX_MODE_CHNG_INT_E 0, RW

N

Enable Duplex Mode Change Interrupt:

1 = Enable Duplex Mode Change interrupt.

0 = Disable Duplex Mode Change interrupt.

PAGE_RECEIVED_INT_EN

AUTONEG_COMP_INT_EN

0, RW

Enable Page Received Interrupt:

1 = Enable Page Received Interrupt.

0 = Disable Page Received Interrupt.

Enable Auto-Negotiation Complete Interrupt:

1 = Enable Auto-Negotiation Complete Interrupt.

0 = Disable Auto-Negotiation Complete Interrupt.

LINK_STATUS_CHNG_INT_EN 0, RW

Enable Link Status Change Interrupt:

1 = Enable Link Status Change interrupt.

0 = Disable Link Status Change interrupt.

9

8

RESERVED

0, RO

0, RW

RESERVED

FALSE_CARRIER_INT_EN

Enable False Carrier Interrupt:

1 = Enable False Carrier interrupt.

0 = Disable False Carrier interrupt.

7

6

RESERVED

0, RO

RESERVED

MDI_CROSSOVER_CHNG_INT_ 0, RW

EN

Enable MDI Crossover Change Interrupt:

1 = Enable MDI Crossover Change interrupt.

0 = Disable MDI Crossover Change interrupt.

5

4

3

SPEED_OPT_EVENT_INT_EN

0, RW

Enable Speed Optimization Event Interrupt:

1 = Enable Speed Optimization Event Interrupt.

0 = Disable Speed Optimization Event Interrupt.

SLEEP_MODE_CHNG_INT_EN 0, RW

Enable Sleep Mode Change Interrupt:

1 = Enable Sleep Mode Change Interrupt.

0 = Disable Sleep Mode Change Interrupt.

WOL_INT_EN

0, RW

Enable Wake-on-LAN Interrupt:

1 = Enable Wake-on-LAN Interrupt.

0 = Disable Wake-on-LAN Interrupt.

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表8-25. MII Interrupt Control Register (MICR), Address 0x0012 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

2

1

0

XGMII_ERR_INT_EN

0, RW

Enable xGMII Error Interrupt:

1 = Enable xGMII Error Interrupt.

0 = Disable xGMII Error Interrupt.

POLARITY_CHNG_INT_EN

JABBER_INT_EN

0, RW

Enable Polarity Change Interrupt:

1 = Enable Polarity Change interrupt.

0 = Disable Polarity Change interrupt.

Enable Jabber Interrupt:

1 = Enable Jabber interrupt.

0 = Disable Jabber interrupt.

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8.6.17 Interrupt Status Register (ISR)

This register contains event status for the interrupt function. If an event has occurred since the last read of this

register, the corresponding status bit will be set. The status indications in this register will be set even if the

interrupt is not enabled.

表8-26. Interrupt Status Register (ISR), Address 0x0013

BIT

BIT NAME

DEFAULT

0, RO, LH, COR Auto-Negotiation Error Interrupt:

1 = Auto-Negotiation Error interrupt is pending and is cleared by the

DESCRIPTION

15

14

13

12

11

10

AUTONEG_ERR_INT

current read.

0 = No Auto-Negotiation Error interrupt.

SPEED_CHNG_INT

0, RO, LH, COR Speed Change Interrupt:

1 = Speed Change interrupt is pending and is cleared by the current

read.

0 = No Speed Change interrupt.

DUPLEX_MODE_CHNG_INT

PAGE_RECEIVED_INT

AUTONEG_COMP_INT

LINK_STATUS_CHNG_INT

0, RO, LH, COR Duplex Mode Change Interrupt:

1 = Duplex Mode Change interrupt is pending and is cleared by the

current read.

0 = No Duplex Mode Change interrupt.

0, RO, LH, COR Page Received Interrupt:

1 = Page Received Interrupt is pending and is cleared by the current

read.

0 = No Page Received Interrupt is pending.

0, RO, LH, COR Auto-Negotiation Complete Interrupt:

1 = Auto-Negotiation Complete Interrupt is pending and is cleared by

the current read.

0 = No Auto-Negotiation Complete Interrupt is pending.

0, RO, LH, COR Link Status Change Interrupt:

1 = Link Status Change interrupt is pending and is cleared by the

current read.

0 = No Link Status Change interrupt is pending.

9

8

RESERVED

0, RO

RESERVED

FALSE_CARRIER_INT

0, RO, LH, COR False Carrier Interrupt:

1 = False Carrier interrupt is pending and is cleared by the current

read.

0 = No False Carrier interrupt is pending.

7

6

RESERVED

0, RO

RESERVED

MDI_CROSSOVER_CHNG_INT 0, RO, LH, COR MDI Crossover Change Interrupt:

1 = MDI Crossover Change interrupt is pending and is cleared by the

current read.

0 = No MDI Crossover Change interrupt is pending.

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表8-26. Interrupt Status Register (ISR), Address 0x0013 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

5

4

SPEED_OPT_EVENT_INT

0, RO, LH, COR Speed Optimization Event Interrupt:

1 = Speed Optimization Event Interrupt is pending and is cleared by

the current read.

0 = No Speed Optimization Event Interrupt is pending.

SLEEP_MODE_CHNG_INT

0, RO, LH, COR Sleep Mode Change Interrupt:

1 = Sleep Mode Change Interrupt is pending and is cleared by the

current read.

0 = No Sleep Mode Change Interrupt is pending.

3

2

WOL_INT

0, RO, LH, COR Wake-on-LAN Interrupt:

1 = Wake-on-LAN Interrupt is pending.

0 = No Wake-on-LAN Interrupt is pending.

XGMII_ERR_INT ¹

0, RO, LH, COR xGMII Error Interrupt:

1 = xGMII Error Interrupt is pending and is cleared by the current

read.

0 = No xGMII Error Interrupt is pending.

1

0

POLARITY_CHNG_INT

JABBER_INT

0, RO, LH, COR Polarity Change Interrupt:

1 = Polarity Change interrupt is pending and is cleared by the current

read.

0 = No Polarity Change interrupt is pending.

0, RO, LH, COR Jabber Interrupt:

1 = Jabber interrupt is pending and is cleared by the current read.

0 = No Jabber interrupt is pending.

1

xGMII: RGMII or SGMII

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8.6.18 Configuration Register 2 (CFG2)

表8-27. Configuration Register 2 (CFG2), Address 0x0014

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:14

13

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

INTERRUPT_POLARITY

1, RW

Configure Interrupt Polarity:

1 = Interrupt pin is active low.

0 = Interrupt pin is active high.

12

RESERVED

0, RO

RESERVED

11:10

SPEED_OPT_ATTEMPT_CNT

10, RW

Speed Optimization Attempt Count:

Selects the number of 1000BASE-T link establishment attempt

failures prior to performing Speed Optimization.

11 = 8

10 = 4

01 = 2

00 = 1

9

8

SPEED_OPT_EN

RGZ: 0, RW

Speed Optimization Enable:

1 = Enable Speed Optimization.

0 = Disable Speed Optimization.

PAP: Strap, RW

SPEED_OPT_ENHANCED_EN 1, RW

Speed Optimization Enhanced Mode Enable:

In enhanced mode, speed is optimized if energy is not detected in

channels C and D.

1 = Enable Speed Optimization enhanced mode.

0 = Disable Speed Optimization enhanced mode.

7

6

SGMII_AUTONEG_EN

SPEED_OPT_10M_EN

1, RW

SGMII Auto-Negotiation Enable:

1 = Enable SGMII Auto-Negotaition.

0 = Disable SGMII Auto-Negotaition.

Enable Speed Optimization to 10BASE-Te:

1 = Enable speed optimization to 10BASE-Te if link establishment

fails in 1000BASE-T and 100BASE-TX .

0 = Disable speed optimization to 10BASE-Te.

5:0

RESERVED

0 0111, RO

RESERVED

8.6.19 Receiver Error Counter Register (RECR)

表8-28. Receiver Error Counter Register (RECR), Address 0x0015

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

RXERCNT[15:0]

0, RO, WSC

RX_ER Counter:

Receive error counter. This register saturates at the maximum value

of 0xFFFF. It is cleared by dummy write to this register.

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8.6.20 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random

Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact

loopback point in the signal chain is also done in this register.

表8-29. BIST Control Register (BISCR), Address 0x0016

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

PRBS_COUNT_MODE

0, RW

PRBS Continuous Mode:

1 = Continuous mode enabled. When one of the PRBS counters

reaches the maximum value, a pulse is generated and the counter

starts counting from zero again. This bit must be set for proper PRBS

operation.

0 = PRBS continuous mode disabled. PRBS operation is not

supported for this setting.

14

GEN_PRBS_PACKET

0, RW

Generated PRBS Packets:

1 = When the packet generator is enabled, it will generate

continuous packets with PRBS data. When the packet generator is

disabled, the PRBS checker is still enabled.

0 = When the packet generator is enabled, it will generate a single

packet with constant data. PRBS generation and checking is

disabled.

13

12

PACKET_GEN_64BIT_MODE

PACKET_GEN_EN

0, RW

BIST Packet Size:

1 = Transmit 64 byte packets in packet generation mode.

0 = Transmit 1518 byte packets in packet generation mode

Packet BIST Enable:

1 = Enable packet/PRBS generator

0 = Disable packet/PRBS generator

11:8

7

RESERVED

0, RO

0, RW

RESERVED: Writes ignored, read as 0.

REV_LOOP_RX_DATA_CTRL

Reverse Loopback Receive Data Control:

This bit may only be set in Reverse Loopback mode.

1 = Send RX packets to MAC in reverse loop

0 = Suppress RX packets to MAC in reverse loop

6

MII_LOOP_TX_DATA_CTRL

LOOPBACK_MODE

0, RW

MII Loopback Transmit Data Control:

This bit may only be set in MII Loopback mode.

1 = Transmit data to MDI in MII loop

0 = Suppress data to MDI in MII loop

5:2

Loopback Mode Select:

PCS Loopback must be disabled (Bits [1:0] =00) prior to selecting the

loopback mode.

1000: Reverse loop

0100: External loop

0010: Analog loop

0001: Digital loop

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表8-29. BIST Control Register (BISCR), Address 0x0016 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1:0

PCS_LOOPBACK

0, RW

PCS Loopback Select:

When configured for 100Base-TX:

11: Loop after MLT3 encoder (full TX/RX path)

10: Loop after scrambler, before MLT3 encoder

01: Loop before scrambler

When configured for 1000Base-T:

x1: Loop before 1000Base-T signal processing.

8.6.21 Status Register 2 (STS2)

表8-30. Status Register 2 (STS2), Address 0x0017

BIT

BIT NAME

DEFAULT

0, RO

DESCRIPTION

15:12

11

RESERVED

PRBS_LOCK

RESERVED: Writes ignored, read as 0.

PRBS Lock Status:

1 = PRBS checker is locked to the received byte stream.

0 = PRBS checker is not locked.

10

9

PRBS_LOCK_LOST

PKT_GEN_BUSY

0, RO, LH, COR PRBS Lock Lost:

1 = PRBS checker has lost lock.

0 = PRBS checker has not lost lock.

0, RO

Packet Generator Busy:

1 = Packet generation is in process.

0 = Packet generation is not in process.

8

SCR_MODE_MASTER_1G

CORE_PWR_MODE

RESERVED

Gigabit Master Scramble Mode:

1 = 1G PCS (master) is in legacy encoding mode.

0 = 1G PCS (master) is in normal encoding mode..

7

Gigabit Slave Scramble Mode:

1 = 1G PCS (slave) is in legacy encoding mode.

0 = 1G PCS (slave) is in normal encoding mode..

6

Core Power Mode:

1 = Core is in normal power mode.

0 = Core is power-down mode or in sleep mode.

5:0

RESERVED: Writes ignored, read as 0.

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8.6.22 LED Configuration Register 1 (LEDCR1)

This register maps the LED functions to the corresponding pins.

表8-31. LED Configuration Register 1 (LEDCR1), Address 0x0018

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:12

LED_GPIO_SEL

RW, 0110

Source of the GPIO LED_3:

1111: Reserved

1110: Receive Error

1101: Receive Error or Transmit Error

1100: RESERVED

1011: Link established, blink for transmit or receive activity

1010: Full duplex

1001: 100/1000BT link established

1000: 10/100BT link established

0111: 10BT link established

0110: 100 BTX link established

0101: 1000BT link established

0100: Collision detected

0011: Receive activity

0010: Transmit activity

0001: Receive or Transmit activity

0000: Link established

11:8

LED_2_SEL

RW, 0001

Source of LED_2:

1111: Reserved

1110: Receive Error

1101: Receive Error or Transmit Error

1100: RESERVED

1011: Link established, blink for transmit or receive activity

1010: Full duplex

1001: 100/1000BT link established

1000: 10/100BT link established

0111: 10BT link established

0110: 100 BTX link established

0101: 1000BT link established

0100: Collision detected

0011: Receive activity

0010: Transmit activity

0001: Receive or Transmit activity

0000: Link established

68

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表8-31. LED Configuration Register 1 (LEDCR1), Address 0x0018 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

7:4

LED_1_SEL

RW, 0101

Source of LED_1:

1111: Reserved

1110: Receive Error

1101: Receive Error or Transmit Error

1100: RESERVED

1011: Link established, blink for transmit or receive activity

1010: Full duplex

1001: 100/1000BT link established

1000: 10/100BT link established

0111: 10BT link established

0110: 100 BTX link established

0101: 1000BT link established

0100: Collision detected

0011: Receive activity

0010: Transmit activity

0001: Receive or Transmit activity

0000: Link established

3:0

LED_0_SEL

RW, 0000

Source of LED_0:

1111: Reserved

1110: Receive Error

1101: Receive Error or Transmit Error

1100: RESERVED

1011: Link established, blink for transmit or receive activity

1010: Full duplex

1001: 100/1000BT link established

1000: 10/100BT link established

0111: 10BT link established

0110: 100 BTX link established

0101: 1000BT link established

0100: Collision detected

0011: Receive activity

0010: Transmit activity

0001: Receive or Transmit activity

0000: Link established

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8.6.23 LED Configuration Register 2 (LEDCR2)

This register provides the ability to directly control any or all LED outputs.

表8-32. LED Configuration Register 2 (LEDCR2), Address 0x0019

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

LED_GPIO_POLARITY

LED_GPIO_DRV_VAL

LED_GPIO_DRV_EN

1, RW

0, RW

GPIO LED Polarity:

1 = Active high

0 = Active low

13

12

GPIO LED Drive Value:

Value to force on GPIO LED

This bit is only valid if enabled through LED_GPIO_DRV_EN.

GPIO LED Drive Enable:

1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO

LED.

0 = Normal operation

11

10

RESERVED

0, RO

1, RW

RESERVED: Writes ignored, read as 0.

LED_2_POLARITY

LED_2 Polarity:

1 = Active high

0 = Active low

9

8

LED_2_DRV_VAL

LED_2_DRV_EN

0, RW

LED_2 Drive Value:

Value to force on LED_2

This bit is only valid if enabled through LED_2_DRV_EN.

LED_2 Drive Enable:

1 = Force the value of the LED_2_DRV_VAL bit onto LED_2.

0 = Normal operation

7

6

RESERVED

0, RO

1, RW

RESERVED: Writes ignored, read as 0.

LED_1_POLARITY

LED_1 Polarity:

1 = Active high

0 = Active low

5

4

LED_1_DRV_VAL

LED_1_DRV_EN

0, RW

LED_1 Drive Value:

Value to force on LED_1

This bit is only valid if enabled through LED_1_DRV_EN.

LED_1 Drive Enable:

1 = Force the value of the LED_1_DRV_VAL bit onto LED_1.

0 = Normal operation

3

2

RESERVED

0, RO

1, RW

RESERVED: Writes ignored, read as 0.

LED_0_POLARITY

LED_0 Polarity:

1 = Active high

0 = Active low

1

0

LED_0_DRV_VAL

LED_0_DRV_EN

0, RW

LED_0 Drive Value:

Value to force on LED_0

This bit is only valid if enabled through LED_0_DRV_EN.

LED_0 Drive Enable:

1 = Force the value of the LED_0_DRV_VAL bit onto LED_0.

0 = Normal operation

8.6.24 LED Configuration Register (LEDCR3)

This register controls the LED blink rate and stretching.

表8-33. LED Configuration Register 3 (LEDCR3), Address 0x001A

BIT

BIT NAME

RESERVED

LEDS_BYPASS_STRETCHING 0, RW

DEFAULT

DESCRIPTION

15:3

2

0, RO

RESERVED: Writes ignored, read as 0.

Bypass LED Stretching:

1 = Bypass LED Stretching

0 = Normal operation

70

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表8-33. LED Configuration Register 3 (LEDCR3), Address 0x001A (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1:0

LEDS_BLINK_RATE

10, RW

LED Blink Rate:

11: 2 Hz (500 ms)

10: 5 Hz (200 ms)

01: 10 Hz (100 ms)

00 = 20 Hz (50 ms)

8.6.25 Configuration Register 3 (CFG3)

表8-34. Configuration Register 3 (CFG3), Address 0x001E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

Fast Link-Up in Parallel Detect

0, RW

Fast Link-Up in Parallel Detect Mode:

1 = Enable Fast Link-Up time During Parallel Detection

0 = Normal Parallel Detection link establishment

In Fast Auto MDI-X this bit is automatically set.

14

Fast AN Enable

0, RW

Fast Auto-Negotiation Enable:

1 = Enable Fast Auto-Negotiation mode –The PHY auto-negotiates

using Timer setting according to Fast AN Sel bits

0 = Disable Fast Auto-Negotiation mode –The PHY auto-

negotiates using normal Timer setting

Adjusting these bits reduces the time it takes to Auto-negotiate

between two PHYs. Note: When using this option care must be

taken to maintain proper operation of the system. While shortening

these timer intervals may not cause problems in normal operation,

there are certain situations where this may lead to problems.

13:12

Fast AN Sel

0, RW

Fast Auto-Negotiation Select bits:

Fast AN

Select

Break

Link

Link Fall

Inhibit

Auto-Neg

Wait

Timer(ms)

<00>

<01>

<10>

<11>

80

50

35

120

240

NA

75

50

150

NA

100

NA

Adjusting these bits reduces the time it takes to auto-negotiate

between two PHYs. In Fast AN mode, both PHYs should be

configured to the same configuration. These 2 bits define the

duration for each state of the Auto-Negotiation process according to

the table above. The new duration time must be enabled by setting

Fast AN En - bit 4 of this register. Note: Using this mode in cases

where both link partners are not configured to the same Fast Auto-

Negotiation configuration might produce scenarios with unexpected

behavior.

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表8-34. Configuration Register 3 (CFG3), Address 0x001E (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

11

Extended FD Ability

0, RW

Extended Full-Duplex Ability:

1 = Force Full-Duplex while working with link partner in forced 100B-

TX. When the PHY is set to Auto-Negotiation or Force 100B-TX and

the link partner is operated in Force 100B-TX, the link is always Full

Duplex

0 = Disable Extended Full Duplex Ability. Decision to work in Full

Duplex or Half Duplex mode follows IEEE specification.

10

9

RESERVED

0, RO

0, RW

RESERVED

Robust Auto-MDIX

Robust Auto-MDIX:

1 =Enable Robust Auto MDI/MDIX resolution

0 = Normal Auto MDI/MDIX mode

If link partners are configured to operational modes that are not

supported by normal Auto MDI/MDIX mode (like Auto-Neg versus

Force 100Base-TX or Force 100Base-TX versus Force 100Base-

TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution

and prevents deadlock.

8

Fast Auto-MDIX

0, RW

Fast Auto MDI/MDIX:

1 = Enable Fast Auto MDI/MDIX mode

0 = Normal Auto MDI/MDIX mode

If both link partners are configured to work in Force 100Base-TX

mode (Auto-Negotiation is disabled), this mode enables Automatic

MDI/MDIX resolution in a short time.

7

6

INT_OE

0, RW

Interrupt Output Enable:

1 = INTN/PWDNN Pad is an Interrupt Output.

0 = INTN/PWDNN Pad in a Power-Down Input.

FORCE_INTERRUPT

Force Interrupt:

1 = Assert interrupt pin.

0 = Normal interrupt mode.

5:3

2

RESERVED

TDR_FAIL

0, RO

RESERVED: Writes ignored, read as 0.

TDR Failure:

1 = TDR failed.

0 = Normal TDR operation.

1

0

TDR_DONE

TDR_START

1, RO

0, RW

TDR Done:

1 = TDR has completed.

0 = TDR has not completed.

TDR Start:

1 = Start TDR.

0 = Normal operation

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8.6.26 Control Register (CTRL)

表8-35. Control Register (CTRL), Address 0x001F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

SW_RESET

0, RW, SC

Software Reset:

1 = Perform a full reset, including registers.

0 = Normal operation.

14

SW_RESTART

RESERVED

0, RW, SC

0, RO

Software Restart:

1 = Perform a full reset, not including registers. .

0 = Normal operation.

13:0

RESERVED: Writes ignored, read as 0.

8.6.27 Testmode Channel Control (TMCH_CTRL)

表8-36. Testmode Channel Control (TMCH_CTRL), Address 0x0025

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0x04

RESERVED

Test mode Channel Select.

If bit 7 is set then Test mode is driven on all 4 channels. If bit 7 is

cleared then test modes are driven according to bits 6:5 as follows:

00: Channel A

01: Channel B

10: Channel C

11: Channel D

RESERVED

7:5

TM_CH_SEL

RESERVED

0x0

4:0

0x00

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8.6.28 Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)

In order to use this register the Robust AMDIX feature must be enabled.

表8-37. Robust Auto MDIX Timer Configuration Register (RAMDIX_TMR_CFG), Address 0x002C

BIT

BIT NAME

RESERVED

RAMDIX_TMR

DEFAULT

0x141, RW

0xF, RW

DESCRIPTION

15:4

3:0

RESERVED

Robust Auto MDIX Timer

0000: 32 ms

0001: 64 ms

0010: 96 ms

.

1111: 480 ms

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8.6.29 Fast Link Drop Configuration Register (FLD_CFG)

表8-38. Fast Link Drop Configuration Register (FLD_CFG), Address 0x002D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

FORCE_DROP

0, RW

Force Drop Link

Forces the link partner to drop the link when no signal is received.

1 = Drops link

0 = Normal operation

FLD_EN

0, RW

1000BASE-T Fast Link Drop:

This bit must be set to 0 during the link up process. After the link is

established set this bit to 1 to enable FLD.

1 = Enable FLD

0 = Normal operation

13

RESERVED

FLD_STS

0, RO

RESERVED

12:8

0, RO, LH

Fast Link Drop Status:

Status Registers that latch high each time a given Fast Link Down

mode is activated and causes a link drop (assuming this criterion

was enabled):

Bit 12: Descrambler Loss Sync

Bit 11: RX Errors

Bit 10: MLT3 Errors

Bit 9: SNR level

Bit 8: Signal/Energy Lost

7:5

4:0

RESERVED

0, RO

0, RW

RESERVED

FLD_SRC_CFG

Fast Link Drop Source Configuration:

The following FLD sources can be configured independently:

Bit 4: Descrambler Loss Sync

Bit 3: RX Errors

Bit 2: MLT3 Errors

Bit 1: SNR level

Bit 0: Signal/Energy Lost

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8.6.30 Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)

表8-39. Fast Link Drop Threshold Configuration Register (FLD_THR_CFG), Address 0x002E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:11

10:8

7

RESERVED

0, RO

RESERVED

0x2, RW

0, RO

RESERVED

6:4

3

RESERVED

0x2, RW

0, RO

RESERVED

2:0

ENERGY_LOST_FLD_THR

0x1, RW

Energy Lost Threshold for FLD Energy Lost Mode

ENERGY_LOST_FLD_THR will be asserted if energy detector

accumulator falls below this threshold. When using strap to enable

FLD feature, this bit defaults to 0x2. Register write is needed to

change it to 0x1. Changing the field to other value is not advised.

8.6.31 Configuration Register 4 (CFG4)

表8-40. Configuration Register 4 (CFG4), Address 0x0031

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

12

RESERVED

000, RO

RESERVED

1, RO

11:9

8

RESERVED

000, RO

0, RW

RESERVED

7

INT_TST_MODE_1

Strap, RW

Reserved; 0: Normal Operation.

If RX_CTRL is strapped to mode1/mode2 then PHY will go to

internal test mode. Reg x6F[8] = 0 will also indicate the test mode

entry request from RX_CTRL's strap . To overrule this test mode

entry through strap mode, INT_TST_MODE_1bit can be set to 0.

1: Internal Test Mode 1, this bit must be cleared

0: Normal Operation

6:5

SGMII_AUTONEG_TIMER

01, RW

SGMII Auto-Negotiation Timer Duration:

11: 11 ms

10: 800 µs

01: 2 µs

00: 16 ms

4:1

0

RESERVED

1000, RO

Strap, RW

RESERVED: Writes ignored, read as 1000.

PORT_MIRROR_EN

Port Mirror Enable:

1 = Enable port mirroring.

0 = Normal operation

8.6.32 RGMII Control Register (RGMIICTL)

This register provides access to the RGMII controls.

表8-41. RGMII Control Register (RGMIICTL), Address 0x0032

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

RGMII_EN

RGZ: 1, RW

RGMII Enable:

1 = Enable RGMII interface.

0 = Disable RGMII interface.

PAP: Strap, RW

6:5

4:3

2

RGMII_RX_HALF_FULL_THR

RGMII_TX_HALF_FULL_THR

RESERVED

10, RW

0, RO

RGMII Receive FIFO Half Full Threshold:

This field controls the RGMII receive FIFO half full threshold.

RGMII Transmit FIFO Half Full Threshold:

This field controls the RGMII transmit FIFO half full threshold.

RESERVED: Writes ignored, read as 0.

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表8-41. RGMII Control Register (RGMIICTL), Address 0x0032 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1

RGMII_TX_CLK_DELAY

0, RW

RGMII Transmit Clock Delay:

1 = RGMII transmit clock is shifted relative to transmit data.

0 = RGMII transmit clock is aligned to transmit data.

0

RGMII_RX_CLK_DELAY

0, RW

RGMII Receive Clock Delay:

1 = RGMII receive clock is shifted relative to receive data.

0 = RGMII receive clock is aligned to receive data.

8.6.33 RGMII Control Register 2 (RGMIICTL2)

表8-42. RGMII Control Register 2 (RGMIICTL2), Address 0x0033

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:5

4

RESERVED

0, RO

RESERVED

RGMII_AF_BYPASS_EN

0, RW

RGMII Async FIFO Bypass Enable:

1 = Enable RGMII Async FIFO Bypass.

0 = Normal operation.

3

RGMII_AF_BYPASS_DLY_EN

LOW_LATENCY_10_100_EN

RESERVED

0, RW

0, RO

RGMII Async FIFO Bypass Delay Enable:

1 = Delay RX_CLK when operating in 10/100 with RGMII.

0 = Normal operation.

2

Low Latency 10/100 Enable:

1 = Enable low latency in 10/100 operation.

0 = Normal operation.

1:0

RESERVED

8.6.34 SGMII Auto-Negotiation Status (SGMII_ANEG_STS)

表8-43. SGMII Auto-Negotiation Status (SGMII_ANEG_STS)), address 0x0037

BIT

BIT NAME

RESERVED

SGMII_PAGE_RX

DEFAULT

0, RO

DESCRIPTION

15:2

1

RESERVED: Writes ignored, read as 0.

SGMII Page Received:

1 = SGMII page has been received.

0 = SGMII page has not been received.

0

SGMII_AUTONEG_COMPLETE 0, RO

SGMII Auto-Negotiation Complete:

1 = SGMII Auto-Negotiation process complete.

0 = SGMII Auto-Negotiation process not complete.

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8.6.35 100BASE-TX Configuration (100CR)

表8-44. 100BASE-TX Configuration Register (100CR), Address 0x0043

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:12

11

RESERVED

0, RO

RESERVED

Disable 100Base-TX Descrambler Timeout:

DESCRAM_TIMEOUT_DIS

0, RW

1 = Disable packet reception when received packet violates the

descrambler timeout. This occurs when the packet is longer than 1.5

ms.

0 = Stops packet reception when received packet violates the

descrambler timeout. This occurs when the packet is longer than 1.5

ms.

10:7

DESCRAM_TIMEOUT

FORCE_100_OK

1111, RW

0, RW

Descrambler Timeout:

Adjust the descrambler time out value. This value refers to the

recovery time due to descrambler unlock. Timer is in ms units.

6

5

4

Force 100-Mbps Good Link:

1 = Forces 100-Mbps good link.

0 = Normal operation.

ENH_MLT3_DET_EN

ENH_IPG_DET_EN

1, RW

Enhanced MLT-3 Detection Enable:

1 = Enable enhanced MLT-3 Detection.

0 = Normal operation.

0, RW

Enhanced Interpacket Gap Detection Enable:

1 = Enable enhanced interpacket gap detection.

0 = Normal operation.

3

2

RESERVED

SCR_DIS

0, RO

0, RW

RESERVED

Disable Scrambler:

1 = Disable scrambler.

0 = Normal operation.

1

0

ODD_NIBBLE_DETECT

FAST_RX_DV

0, RW

Enable Odd Nibble Detection:

1 = Detect when an odd number of nibbles is received.

0 = Normal operation.

Fast RX_DV Enable:

1 = Enable fast RX_DV.

0 = Normal operation.

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8.6.36 Viterbi Module Configuration (VTM_CFG)

表8-45. Viterbi Module Configuration (VTM_CFG), Address 0x0053

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:4

3:0

RESERVED

0x205, RO

RESERVED

VTM_IDLE_CHECK_CNT_THR 0x5, RW

Viterbi Detector Idle Count Threshold

Threshold for consecutive amount of Idle symbols for Viterbi Idle

detector to assert Idle Mode.

Default value 0x5 is for IPG >= 12. Set this field to 0x4: for IPG < 12.

Please verify new register settings through system level tests if this

field is changed.

8.6.37 Skew FIFO Status (SKEW_FIFO)

表8-46. Skew FIFO Status (SKEW_FIFO), Address 0x0055

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:4

RESERVED

0, RO

RESERVED

CH_B_SKEW

CH_A_SKEW

0, RO

Skew of RX channel B to align symbols in # of clock cycles.

Skew of RX channel A to align symbols in # of clock cycles.

3:0

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8.6.38 Strap Configuration Status Register 1 (STRAP_STS1)

Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E

表8-47. Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E

BIT

BIT NAME

DEFAULT

Strap, RO

DESCRIPTION

15

14

13

12

11

10

9

STRAP_MIRROR_EN

Mirror Enable Strap:

1 = Port mirroring strapped to enable.

0 = Port mirroring strapped to disable.

STRAP_LINK_DOWNSHIFT_EN Strap, RO

Link Downshift Enable Strap:

1 = Link Downshift strapped to enable.

0 = Link Downshift strapped to disable.

STRAP_CLK_OUT_DIS

STRAP_RGMII_DIS

STRAP_SGMII_EN

STRAP_AMDIX_DIS

STRAP_FORCE_MDI_X

STRAP_HD_EN

Strap, RO

Clock Output Disable Strap:

1 = Clock output strapped to disable.

0 = Clock output strapped to enable.

RGMII Disable Strap:

1 = RGMII strapped to disable.

0 = RGMII strapped to enable.

SGMII Enable Strap:

1 = SGMII strapped to enable.

0 = SGMII strapped to disable.

Auto-MDIX Disable Strap:

1 = Auto-MDIX strapped to disable.

0 = Auto-MDIX strapped to enable.

Force MDI/X Strap:

1 = Force MDIX strapped to enable.

0 = Force MDI strapped to enable.

8

Half Duplex Enable Strap:

1 = Half Duplex strapped to enable.

0 = Full Duplex strapped to enable.

7

STRAP_ANEG_DIS

Auto-Negotiation Disable Strap:

1 = Auto-Negotiation strapped to disable.

0 = Auto-Negotiation strapped to enable.

6

5

RESERVED

0, RO

RESERVED

STRAP_ANEG_SEL

Strap, RO

ANEG_SEL value from strap.

See Auto-Negotiation Select Strap Details table.

4

RESERVED

0, RO

RESERVED

3:0

STRAP_PHY_ADD

Strap, RO

PHY Address Strap:

PHY address value from straps.

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8.6.39 Strap Configuration Status Register 2 (STRAP_STS2)

表8-48. Strap Configuration Status Register 2 (STRAP_STS2), Address 0x006F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:11

10

RESERVED

0, RO

RESERVED

STRAP_ FLD

Strap, RO

Fast Link Drop (FLD) Enable Strap:

1 = FLD strapped to enable.

0 = FLD strapped to disable.

10

9

RESERVED

0, RO

RESERVED

8

7

6:4

STRAP_RGMII_CLK_SKEW_TX Strap, RO

(RGZ)

RGMII Transmit Clock Skew Strap:

RGMII_TX_DELAY_CTRL[2:0] values from straps.

See RGMII Transmit Clock Skew Details table for more information.

6:4

STRAP_RGMII_CLK_SKEW_TX Strap, RO

RGMII Transmit Clock Skew Strap:

RGMII_TX_DELAY_CTRL[2:0] values from straps.

See RGMII Transmit Clock Skew Details table for more information.

3

RESERVED

0, RO

RESERVED

2:0

STRAP_RGMII_CLK_SKEW_RX Strap, RO

RGMII Receive Clock Skew Strap:

RGMII_RX_DELAY_CTRL[2:0] values from straps.

See 表8-7 for more information.

8.6.40 BIST Control and Status Register 1 (BICSR1)

表8-49. BIST Control and Status Register 1 (BICSR1), Address 0x0071

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PRBS_BYTE_CNT

0x0000, RO

Holds the number of total bytes received by the PRBS checker.

Value in this register is locked when write is done to register BICSR2

bit[0] or bit[1].

The count stops at 0xFFFF when PRBS_COUNT_MODE in BISCR

register (0x0016) is set to 0.

8.6.41 BIST Control and Status Register 2 (BICSR2)

表8-50. BIST Control and Status Register 2 (BICSR2), Address 0x0072

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:11

10

Reserved

0x00, RO

Ignored on Read

PRBS Checker Packet Count Overflow

If set, PRBS Packet counter has reached overflow. Overflow is

cleared when PRBS counters are cleared by setting bit #1 of this

register.

PRBS_PKT_CNT_OVF

0, RO

PRBS Byte Count Overflow

9

8

PRBS_BYTE_CNT_OVF

Reserved

0, RO

0,RO

If set, PRBS Byte counter has reached overflow. Overflow is cleared

when PRBS counters are cleared by setting bit #1 of this register.

Ignore on Read

Holds number of error bytes that are received by PRBS checker.

Value in this register is locked when write is done to bit[0] or bit[1]

When PRBS Count Mode set to zero, count stops on 0xFF (see

register 0x0016)

7:0

PRBS_ERR_CNT

0x00, RO

Notes: Writing bit 0 generates a lock signal for the PRBS counters.

Writing bit 1 generates a lock and clear signal for the PRBS counters

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8.6.42 BIST Control and Status Register 3 (BICSR3)

表8-51. BIST Control and Status Register 3 (BICSR3), Address 0x007B

BIT

BIT NAME

DEFAULT

DESCRIPTION

Length of the generated BIST packets. The value of this register

defines the size (in bytes) of every packet that is generated by the

BIST. Default value is 0x05DC, which is equal to 1500 bytes.

Each packet is appended with 13 nibbles of 0x5 and then 0xD5

(SFD).

15:0

PKT_LEN_PRBS

0x05DC, RW

8.6.43 BIST Control and Status Register 4 (BICSR4)

表8-52. BIST Control and Status Register 4 (BICSR4), Address 0x007C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

RESERVED

0x00, RO

RESERVED

Inter Packet Gap (IPG) Length defines the size of the gap (in bytes)

between any 2 successive packets generated by the BIST. Default

value is 0x7D (equal to 500 bytes). An increment in this fields value

corresponds to an addition of 4 bytes to the IPG Length.

IPG_LEN

0x7D, RW

8.6.44 Configuration for Receiver's Equalizer (CRE)

表8-53. Configuration for Receiver's Equalizer (CRE), Address 0x008A

BIT

BIT NAME

DEFAULT

DESCRIPTION

Configuration for receiver's equalizer. Value 0x010F may further

improve the immunity margins during EMC testing.

15:0

CONFIG_REC_EQ

0x0000, RW

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8.6.45 RGMII Delay Control Register (RGMIIDCTL)

This register provides access to the RGMII delay controls.

表8-54. RGMII Delay Control Register (RGMIIDCTL), Address 0x0086

BIT

BIT NAME

RESERVED

RGMII_TX_DELAY_CTRL

DEFAULT

0, RO

Strap, RW

DESCRIPTION

15:8

7:4

RESERVED: Writes ignored, read as 0.

RGMII Transmit Clock Delay:

1111: 4.00 ns

1110: 3.75 ns

1101: 3.50 ns

1100: 3.25 ns

1011: 3.00 ns

1010: 2.75 ns

1001: 2.50 ns

1000: 2.25 ns

0111: 2.00 ns

0110: 1.75 ns

0101: 1.50 ns

0100: 1.25 ns

0011: 1.00 ns

0010: 0.75 ns

0001: 0.50 ns

0000: 0.25 ns

3:0

RGMII_RX_DELAY_CTRL

Strap, RW

RGMII Receive Clock Delay:

1111: 4.00 ns

1110: 3.75 ns

1101: 3.50 ns

1100: 3.25 ns

1011: 3.00 ns

1010: 2.75 ns

1001: 2.50 ns

1000: 2.25 ns

0111: 2.00 ns

0110: 1.75 ns

0101: 1.50 ns

0100: 1.25 ns

0011: 1.00 ns

0010: 0.75 ns

0001: 0.50 ns

0000: 0.25 ns

8.6.46 Configuration of Receiver's LPF (CRLPF)

表8-55. Configuration of Receiver's LPF (CRLPF), Address 0x00B3

BIT

BIT NAME

DEFAULT

DESCRIPTION

Configuration of receiver's LPF. Value 0x000C may further improve

the immunity margins during EMC testing.

15:0

CONFIG_REC_LPF

0x0088, RW

8.6.47 Enable Control of Receiver's Equalizer (ECRE)

表8-56. Enable Control of Receiver's Equalizer (ECRE), Address 0x00C0

BIT

BIT NAME

DEFAULT

DESCRIPTION

Enable control of receiver's equalizer. Value 0x0000 may further

improve the immunity margins during EMC testing.

15:0

EN_CTRL_REC_EQ

0x0000, RW

8.6.48 PLL Clock-out Control Register (PLLCTL)

表8-57. PLL Clock-out Control Register (PLLCTL), Address 0x00C6

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:5

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

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表8-57. PLL Clock-out Control Register (PLLCTL), Address 0x00C6 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

4

CLK_MUX

0, RW

Internal Clock MUX Control:

1 = Configures analog CLK_OUT to be TX_TCLK for compliance

testing.

0 = Normal operation.

3:0

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

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8.6.49 SGMII Control Register 1 (SGMIICTL1)

表8-58. SGMII Control Register 1 (SGMIICTL1), Address 0x00D3

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

14

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

SGMII_TYPE

RESERVED

0, RW

0, RO

SGMII Configuration:

1 = 6-wire mode. Enable differential SGMII clock to MAC.

0 = 4-wire mode

13:0

RESERVED: Writes ignored, read as 0.

8.6.50 Sync FIFO Control (SYNC_FIFO_CTRL)

表8-59. Sync FIFO Control (SYNC_FIFO_CTRL), Address 0x00E9

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

RESERVED

0x9F22, RW

RESERVED

8.6.51 Loopback Configuration Register (LOOPCR)

表8-60. Loopback Configuration Register (LOOPCR), Address 0x00FE

BIT

BIT NAME

DEFAULT

1110 0111 0010 Loopback Configuration Value:

0001, RW 1110 0111 0010 000: Configuration for loopback modes.

DESCRIPTION

15:0

LOOP_CFG_VAL

A software reset through bit 14 of the Control Register (CTRL),

address 0x001F, is required after changes to this register value.

Other values for this register are not recommended.

8.6.52 DSP Configuration (DSP_CONFIG)

表8-61. DSP Configuration (DSP_CONFIG), Address 0x0100

BIT

BIT NAME

DEFAULT

DESCRIPTION

DSP Configuration. Value 0x1027 may further improve the immunity

margins during EMC testing.

15:0

DSP_CONFIG

0x051C, RW

8.6.53 DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)

Certain applications may need this register to be configured to 0x0E81 to improve Short Cable performance.

Changing this register to 0x0E81, will not effect Long Cable performance.

表8-62. DSP Feedforward Equalizer Configuration (DSP_FFE_CFG), Address 0x012C

BIT

BIT NAME

RESERVED

FFE_EQ

DEFAULT

DESCRIPTION

15:10

9:0

0000 11, RO

RESERVED

00 0010 1101, FFE Equalizer Configuration

RW

Set this field to 10 1000 0001 when using cables of length <= 1 m.

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8.6.54 Receive Configuration Register (RXFCFG)

This register provides receive configuration for Wake-on-LAN (WoL).

表8-63. Receive Configuration Register (RXFCFG), Address 0x0134

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:12

11

RESERVED

0, RO

RESERVED

Clear Wake-on-LAN Output:

This bit is only applicable when configured for level mode.

1 = Clear Wake-on-LAN output

WOL_OUT_CLEAR

0, RW, SC

00, RW

10:9

WOL_OUT_STRETCH

Wake-on-LAN Output Stretch:

If WoL out is configured for pulse mode, the pulse length is defined

as the following number of 125-MHz clock cycles:

11 = 64 clock cycles

10 = 32 clock cycles

01 = 16 clock cycles

00 = 8 clock cycles

8

7

WOL_OUT_MODE

0, RW

Wake-on-LAN Output Mode:

1 = Level Mode. WoL is cleared by a write to WOL_OUT_CLEAR (bit

11).

0 = Pulse Mode. Pulse width is configured via

WOL_OUT_STRETCH (bits 10:9).

ENHANCED_MAC_SUPPORT

Enable Enhanced Receive Features:

1 = Enable for Wake-on-LAN, CRC check, and Receive 1588

indication.

0 = Normal operation.

6

5

RESERVED

SCRON_EN

0, RO

0, RW

RESERVED

Enable SecureOn Password:

1 = SecureOn Password enabled.

0 = SecureOn Password disabled.

4

WAKE_ON_UCAST

0, RW

Wake on Unicast Packet:

1 = Issue an interrupt upon reception of Unicast packet.

0 = Do not issue an interrupt upon reception of Unicast packet.

3

2

RESERVED

0, RO

1, RW

RESERVED

WAKE_ON_BCAST

Wake on Broadcast Packet:

1 = Issue an interrupt upon reception of Broadcast packet.

0 = Do not issue an interrupt upon reception of Broadcast packet.

1

0

WAKE_ON_PATTERN

WAKE_ON_MAGIC

0, RW

Wake on Pattern Match:

1 = Issue an interrupt upon pattern match.

0 = Do not issue an interrupt upon pattern match.

Wake on Magic Packet:

1 = Issue an interrupt upon reception of Magic packet.

0 = Do not issue an interrupt upon reception of Magic packet.

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8.6.55 Receive Status Register (RXFSTS)

This register provides status for receive functionality.

表8-64. Receive Status Register (RXFSTS), Address 0x0135

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7

RESERVED

0, RO

RESERVED

SFD Error:

SFD_ERR

0, R0, LH, SC

1 = Packet with SFD error (without an 0x5D SFD byte) received.

0 = No SFD error seen.

6

5

4

BAD_CRC

Bad CRC:

1 = A packet with a bad CRC was received.

0 = No bad CRC seen.

SCRON_HACK

UCAST_RCVD

SecureOn Hack Attempt Flag:

1 = SecureOn Hack attempt seen.

0 = No SecureOn Hack attempt seen.

Unicast Packet Received:

1 = A valid Unicast packet was received.

0 = No valid Unicast packet was received.

3

2

RESERVED

0, RO

RESERVED

BCAST_RCVD

0, R0, LH, SC

Broadcast Packet Received:

1 = A valid Broadcast packet was received.

0 = No valid Broadcast packet was received.

1

0

PATTERN_RCVD

MAGIC_RCVD

0, R0, LH, SC

Pattern Match Received:

1 = A valid packet with the configured pattern was received.

0 = No valid packet with the configured pattern was received.

Magic Packet Received:

1 = A valid Magic packet was received.

0 = No valid Magic packet was received.

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8.6.56 Pattern Match Data Register 1 (RXFPMD1)

表8-65. Pattern Match Data Register 1 (RXFPMD1), Address 0x0136

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PMATCH_DATA_15_0

0, RW

Bits 15:0 of Perfect Match Data - used for DA (destination address)

match

8.6.57 Pattern Match Data Register 2 (RXFPMD2)

表8-66. Pattern Match Data Register 2 (RXFPMD2), address 0x0137

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PMATCH_DATA_31_16

0, RW

Bits 31:16 of Perfect Match Data - used for DA (destination address)

match

8.6.58 Pattern Match Data Register 3 (RXFPMD3)

表8-67. Pattern Match Data Register 3 (RXFPMD3), address 0x0138

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PMATCH_DATA_ 47_32

0, RW

Bits 47:32 of Perfect Match Data - used for DA (destination address)

match

8.6.59 SecureOn Pass Register 2 (RXFSOP1)

表8-68. SecureOn Pass Register 1 (RXFSOP1), Address 0x0139

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

SCRON_PASSWORD _15_0

0, RW

Bits 15:0 of secure-on password for magic packet)

8.6.60 SecureOn Pass Register 2 (RXFSOP2)

表8-69. SecureOn Pass Register 2 (RXFSOP2), Address 0x013A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

SCRON_PASSWORD _31_16

0, RW

Bits 31:16 of secure-on password for magic packet

8.6.61 SecureOn Pass Register 3 (RXFSOP3)

表8-70. SecureOn Pass Register 3 (RXFSOP3), Address 0x013B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

SCRON_PASSWORD _ 47_32

0, RW

Bits 47:32 of secure-on password for magic packet

8.6.62 Receive Pattern Register 1 (RXFPAT1)

表8-71. Receive Pattern Register 1 (RXFPAT1), Address 0x013C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_0_1

0, RW

Bytes 0 (LSbyte) + 1 of the configured pattern. Each byte can be

masked separately through the RXF_PATTERN_BYTE_MASK

registers.

8.6.63 Receive Pattern Register 2 (RXFPAT2)

表8-72. Receive Pattern Register 2 (RXFPAT2), Address 0x013D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_2_3

0, RW

Bytes 2 + 3 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

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8.6.64 Receive Pattern Register 3 (RXFPAT3)

表8-73. Receive Pattern Register 3 (RXFPAT3), Address 0x013E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_4_5

0, RW

Bytes 4 + 5 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.65 Receive Pattern Register 4 (RXFPAT4)

表8-74. Receive Pattern Register 4 (RXFPAT4), Address 0x013F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_6_7

0, RW

Bytes 6 + 7 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.66 Receive Pattern Register 5 (RXFPAT5)

表8-75. Receive Pattern Register 5 (RXFPAT5), Address 0x0140

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_8_9

0, RW

Bytes 8 + 9 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.67 Receive Pattern Register 6 (RXFPAT6)

表8-76. Receive Pattern Register 6 (RXFPAT6), Address 0x0141

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_10_11

0, RW

Bytes 10 + 11 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.68 Receive Pattern Register 7 (RXFPAT7)

表8-77. Receive Pattern Register 7 (RXFPAT7), Address 0x0142

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_12_13

0, RW

Bytes 12 + 13 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.69 Receive Pattern Register 8 (RXFPAT8)

表8-78. Receive Pattern Register 8 (RXFPAT8), Address 0x0143

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_14_15

0, RW

Bytes 0 14 + 15 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.70 Receive Pattern Register 9 (RXFPAT9)

表8-79. Receive Pattern Register 9 (RXFPAT9), Address 0x0144

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_16_17

0, RW.

Bytes 16 + 17 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

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8.6.71 Receive Pattern Register 10 (RXFPAT10)

表8-80. Receive Pattern Register 10 (RXFPAT10), Address 0x0145

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_18_19

0, RW

Bytes 18 + 19 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.72 Receive Pattern Register 11 (RXFPAT11)

表8-81. Receive Pattern Register 11 (RXFPAT11), Address 0x0146

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_20_21

0, RW

Bytes 20 + 21 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.73 Receive Pattern Register 12 (RXFPAT12)

表8-82. Receive Pattern Register 12 (RXFPAT12), Address 0x0147

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_22_23

0, RW

Bytes 22 + 23 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.74 Receive Pattern Register 13 (RXFPAT13)

表8-83. Receive Pattern Register 13 (RXFPAT13), Address 0x0148

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_24_25

0, RW

Bytes 24 + 25 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.75 Receive Pattern Register 14 (RXFPAT14)

表8-84. Receive Pattern Register 14 (RXFPAT14), Address 0x0149

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_26_27

0, RW

Bytes 26 + 27 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.76 Receive Pattern Register 15 (RXFPAT15)

表8-85. Receive Pattern Register 15 (RXFPAT15), address 0x014A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_28_29

0, RW

Bytes 28 + 29 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.77 Receive Pattern Register 16 (RXFPAT16)

表8-86. Receive Pattern Register 16 (RXFPAT16), Address 0x014B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_30_31

0, RW

Bytes 30 + 31 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.78 Receive Pattern Register 17 (RXFPAT17)

表8-87. Receive Pattern Register 17 (RXFPAT17), Address 0x014C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_32_33

0, RW

Bytes 32 + 33 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

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8.6.79 Receive Pattern Register 18 (RXFPAT18)

表8-88. Receive Pattern Register 18 (RXFPAT18), Address 0x014D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_34_35

0, RW

Bytes 34 + 35 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.80 Receive Pattern Register 19 (RXFPAT19)

表8-89. Receive Pattern Register 19 (RXFPAT19), Address 0x014E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_36_37

0, RW

Bytes 36 + 37 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.81 Receive Pattern Register 20 (RXFPAT20)

表8-90. Receive Pattern Register 20 (RXFPAT20), Address 0x014F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_38_39

0, RW

Bytes 38 + 39 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.82 Receive Pattern Register 21 (RXFPAT21)

表8-91. Receive Pattern Register 21 (RXFPAT21), Address 0x0150

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_38_39

0, RW

Bytes 38 + 39 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.83 Receive Pattern Register 22 (RXFPAT22)

表8-92. Receive Pattern Register 22 (RXFPAT22), Address 0x0151

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_42_43

0, RW

Bytes 42 + 43 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.84 Receive Pattern Register 23 (RXFPAT23)

表8-93. Receive Pattern Register 23 (RXFPAT23), Address 0x0152

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_44_45

0, RW

Bytes 44 + 45 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.85 Receive Pattern Register 24 (RXFPAT24)

表8-94. Receive Pattern Register 24 (RXFPAT24), Address 0x0153

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_46_47

0, RW

Bytes 46 + 47 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.86 Receive Pattern Register 25 (RXFPAT25)

表8-95. Receive Pattern Register 25 (RXFPAT25), Address 0x0154

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_48_49

0, RW

Bytes 48 + 49 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

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8.6.87 Receive Pattern Register 26 (RXFPAT26)

表8-96. Receive Pattern Register 26 (RXFPAT26), Address 0x0155

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_50_51

0, RW

Bytes 50 + 51 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.88 Receive Pattern Register 27 (RXFPAT27)

表8-97. Receive Pattern Register 27 (RXFPAT27), Address 0x0156

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_52_53

0, RW

Bytes 52 + 53 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.89 Receive Pattern Register 28 (RXFPAT28)

表8-98. Receive Pattern Register 28 (RXFPAT28), Address 0x0157

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_54_55

0, RW

Bytes 54 + 55 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.90 Receive Pattern Register 29 (RXFPAT29)

表8-99. Receive Pattern Register 29 (RXFPAT29), Address 0x0158

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_56_57

0, RW

Bytes 56 + 57 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.91 Receive Pattern Register 30 (RXFPAT30)

表8-100. Receive Pattern Register 30 (RXFPAT30), Address 0x0159

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_58_59

0, RW

Bytes 58 + 59 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.92 Receive Pattern Register 31 (RXFPAT31)

表8-101. Receive Pattern Register 31 (RXFPAT31), Address 0x015A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_0_1

0, RW

Bytes 60 + 61 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.93 Receive Pattern Register 32 (RXFPAT32)

表8-102. Receive Pattern Register 32 (RXFPAT32), Address 0x015B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_62_63

0, RW

Bytes 62 + 63 of the configured pattern. Each byte can be masked

separately through the RXF_PATTERN_BYTE_MASK registers.

8.6.94 Receive Pattern Byte Mask Register 1 (RXFPBM1)

表8-103. Receive Pattern Byte Mask Register 1 (RXFPBM1), Address 0x015C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_ MASK_0_15 0, RW

Masks for bytes 0 to 15 of the pattern. A 1 indicates a mask for the

associated byte.

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8.6.95 Receive Pattern Byte Mask Register 2 (RXFPBM2)

表8-104. Receive Pattern Byte Mask Register 2 (RXFPBM2), Address 0x015D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_16_31

0, RW

Masks for bytes 16 to 31 of the pattern. A 1 indicates a mask for the

associated byte.

8.6.96 Receive Pattern Byte Mask Register 3 (RXFPBM3)

表8-105. Receive Pattern Byte Mask Register 3 (RXFPBM3), Address 0x015E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_32_47

0, RW

Masks for bytes 32 to 47 of the pattern. A 1 indicates a mask for the

associated byte.

8.6.97 Receive Pattern Byte Mask Register 4 (RXFPBM4)

表8-106. Receive Pattern Byte Mask Register 4 (RXFPBM4), Address 0x015F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_48_63

0, RW

Masks for bytes 48 to 63 of the pattern. A 1 indicates a mask for the

associated byte.

8.6.98 Receive Pattern Control (RXFPATC)

表8-107. Receive Status Register (RXFSTS), Address 0x0161

BIT

BIT NAME

RESERVED

PATTERN_START_POINT

DEFAULT

0, RO

0, RW

DESCRIPTION

15:6

5:0

RESERVED: Writes ignored, read as 0.

Number of bytes after SFD where comparison of the RX packet to

the configured pattern begins:

111111 - Start compare in the 64th byte after SFD

000000 - Start compare in the 1st byte after SFD

8.6.99 10M SGMII Configuration (10M_SGMII_CFG)

表8-108. 10M SGMII Configuration (10M_SGMII_CFG), Address 0x016F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7

RESERVED

0000 0000, RO RESERVED

10M_SGMII_RATE_ADAPT

RESERVED

1, RW

RESERVED - Do not change this bit. The PHY adapts automatically

to 10M speed.

6:0

001 0101, RO

RESERVED

8.6.100 I/O Configuration (IO_MUX_CFG)

表8-109. I/O Configuration (IO_MUX_CFG), Address 0x0170

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

0, RO

RESERVED

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表8-109. I/O Configuration (IO_MUX_CFG), Address 0x0170 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

12:8

CLK_O_SEL

0 1100, RW

Clock Output Select:

01101 - 11111: RESERVED

01100: Reference clock (synchronous to XI input clock)

01011: Channel D transmit clock

01010: Channel C transmit clock

01001: Channel B transmit clock

01000: Channel A transmit clock

00111: Channel D receive clock divided by 5

00110: Channel C receive clock divided by 5

00101: Channel B receive clock divided by 5

00100: Channel A receive clock divided by 5

00011: Channel D receive clock

00010: Channel C receive clock

00001: Channel B receive clock

00000: Channel A receive clock

7

6

RESERVED

0, RO

RESERVED

CLK_O_DISABLE

0 , RW

Clock Output Disable:

1 = Disable clock output on CLK_OUT pin.

0 = Enable clock output on CLK_OUT pin.

5

RESERVED

0, RO

RESERVED

4:0

IO_IMPEDANCE_CTRL

TRIM, RW

Impedance Control for MAC I/Os:

Output impedance approximate range from 35-70 Ωin 32 steps.

Lowest being 11111 and highest being 00000. Range and Step size

will vary with process.

Default is set to 50 Ωby trim. But the default register value can vary

by process. Non default values of MAC I/O impedance can be used

based on trace impedance. Mismatch between device and trace

impedance can cause voltage overshoot and undershoot.

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8.6.101 GPIO Mux Control Register (GPIO_MUX_CTRL)

表8-110. GPIO Mux Control Register (GPIO_MUX_CTRL), Address 0x0172

BIT

BIT NAME

RESERVED

GPIO_1_CTRL

DEFAULT

0, RO

RW, 0000

DESCRIPTION

15:8

7:4

RESERVED

GPIO_1 Control:

1010 - 1111: RESERVED

1001: Constant 1

1000: Constant 0

0111: PRBS Errors / Loss of Sync

0110: LED_3

0101: RESERVED

0100: Energy Detect (1000Base-T and 100Base-TX only)

0011: WOL

0010: 1588 RX SFD

0001: 1588 TX SFD

0000: COL

3:0

GPIO_0_CTRL

RW, 0000

GPIO_0 Control:

1010 - 1111: RESERVED

1001: Constant 1

1000: Constant 0

0111: PRBS Errors / Loss of Sync

0110: LED_3

0101: RESERVED

0100: Energy Detect (1000Base-T and 100Base-TX only)

0011: WOL

0010: 1588 RX SFD

0001: 1588 TX SFD

0000: RX_ER

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8.6.102 TDR General Configuration Register 1 (TDR_GEN_CFG1)

表8-111. TDR General Configuration Register 1 (TDR_GEN_CFG1), Address 0x0180

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

12

RESERVED

0, RO

RESERVED

TDR_CH_CD_BYPASS

0, RW

TDR Bypass for Channel C and D:

1 = Bypass channel C and D in TDR tests.

0 = Normal operation.

11

TDR_CROSS_MODE_DIS

Disable TDR Cross Mode:

1 = Disable cross mode option. Do not check cross channels. Only

listen to the channel being used for transmit.

0 = Normal operation.

10

TDR_NLP_CHECK

TDR_AVG_NUM

1, RW

TDR NLP Check:

1 = Check for NLPs during silence.

0 = Normal operation.

9:7

110, RW

Number Of TDR Cycles to Average:

111: RESERVED: Writes ignored, read as 0.

110: 64 TDR cycles

101: 32 TDR cycles

100: 16 TDR cycles

011: 8 TDR cycles

010: 4 TDR cycles

001: 2 TDR cycles

000: 1 TDR cycle

6:4

3:0

TDR_SEG_NUM

101, RW

010, RW

Set the number of TDR segments to check.

TDR_CYCLE_TIME

Set the time for each TDR cycle. Value is measured in

microseconds.

8.6.103 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)

表8-112. TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1), Address 0x0190

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_A_1

0, RO

Location of the second peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into distance from the

PHY.

TDR_PEAKS_LOC_A_0

0, RO

Location of the first peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into distance from the

PHY.

8.6.104 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)

表8-113. TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2), Address 0x0191

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_A_3

0, RO

Location of the fourth peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into distance from the

PHY.

TDR_PEAKS_LOC_A_2

0, RO

Location of the third peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into distance from the

PHY.

8.6.105 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)

表8-114. TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3), Address 0x0192

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

TDR_PEAKS_LOC_B_0

0, RO

Location of the first peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into distance from the

PHY.

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表8-114. TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3), Address 0x0192 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

7:0

TDR_PEAKS_LOC_A_4

0, RO

Location of the fifth peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into distance from the

PHY.

8.6.106 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)

表8-115. TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4), Address 0x0193

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_B_2

0, RO

Location of the third peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into distance from the

PHY.

TDR_PEAKS_LOC_B_1

0, RO

Location of the second peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into distance from the

PHY.

8.6.107 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)

表8-116. TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5), Address 0x0194

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_B_4

0, RO

Location of the fifth peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into distance from the

PHY.

TDR_PEAKS_LOC_B_3

0, RO

Location of the fourth peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into distance from the

PHY.

8.6.108 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)

表8-117. TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6), Address 0x0195

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_C_1

0, RO

Location of the second peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into distance from

the PHY.

TDR_PEAKS_LOC_C_0

0, RO

Location of the first peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into distance from

the PHY.

8.6.109 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)

表8-118. TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7), Address 0x0196

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_C_3

0, RO

Location of the fourth peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into distance from

the PHY.

TDR_PEAKS_LOC_C_2

0, RO

Location of the third peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into distance from

the PHY.

8.6.110 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)

表8-119. TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8), Address 0x0197

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

TDR_PEAKS_LOC_D_0

0, RO

Location of the first peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into distance from

the PHY.

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表8-119. TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8), Address 0x0197 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

7:0

TDR_PEAKS_LOC_C_4

0, RO

Location of the fifth peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into distance from

the PHY.

8.6.111 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)

表8-120. TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9), Address 0x0198

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_D_2

0, RO

Location of the third peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into distance from

the PHY.

TDR_PEAKS_LOC_D_1

0, RO

Location of the second peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into distance from

the PHY.

8.6.112 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)

表8-121. TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10), Address 0x0199

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

7:0

TDR_PEAKS_LOC_D_4

0, RO

Location of the fifth peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into distance from

the PHY.

TDR_PEAKS_LOC_D_3

0, RO

Location of the fourth peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into distance from

the PHY.

8.6.113 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)

表8-122. TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1), Address 0x019A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_A_1

0, RO

Amplitude of the second peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_A_0

Amplitude of the first peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into type of cable

fault and-or interference.

8.6.114 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)

表8-123. TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2), Address 0x019B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_A_3

0, RO

Amplitude of the fourth peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_A_2

Amplitude of the third peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into type of cable

fault and-or interference.

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8.6.115 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)

表8-124. TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3), Address 0x019C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_B_0

0, RO

Amplitude of the first peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_A_4

Amplitude of the fifth peak discovered by the TDR mechanism on

channel A. The value of these bits is translated into type of cable

fault and-or interference.

8.6.116 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)

表8-125. TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4), Address 0x019D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_B_2

0, RO

Amplitude of the third peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_B_1

Amplitude of the second peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into type of cable

fault and-or interference.

8.6.117 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)

表8-126. TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5), Address 0x019E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_B_4

0, RO

Amplitude of the fifth peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_B_3

Amplitude of the fourth peak discovered by the TDR mechanism on

channel B. The value of these bits is translated into type of cable

fault and-or interference.

8.6.118 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)

表8-127. TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6), Address 0x019F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_C_1

0, RO

Amplitude of the second peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_C_0

Amplitude of the first peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into type of cable

fault and-or interference.

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8.6.119 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)

表8-128. TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7), Address 0x01A0

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_C_3

0, RO

Amplitude of the fourth peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_C_2

Amplitude of the third peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into type of cable

fault and-or interference.

8.6.120 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)

表8-129. TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8), Address 0x01A1

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_D_0

0, RO

Amplitude of the first peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_C_4

Amplitude of the fifth peak discovered by the TDR mechanism on

channel C. The value of these bits is translated into type of cable

fault and-or interference.

8.6.121 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)

表8-130. TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9), Address 0x01A2

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_D_2

0, RO

Amplitude of the third peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_D_1

Amplitude of the second peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into type of cable

fault and-or interference.

8.6.122 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)

表8-131. TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10), Address 0x01A3

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

RESERVED

0, RO

RESERVED

14:8

TDR_PEAKS_AMP_D_4

0, RO

Amplitude of the fifth peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into type of cable

fault and-or interference.

7

RESERVED

0, RO

RESERVED

6:0

TDR_PEAKS_AMP_D_3

Amplitude of the fourth peak discovered by the TDR mechanism on

channel D. The value of these bits is translated into type of cable

fault and-or interference.

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8.6.123 TDR General Status (TDR_GEN_STATUS)

表8-132. TDR General Status (TDR_GEN_STATUS), Address 0x01A4

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:12

11

RESERVED

0, RO

RESERVED

TDR_P_LOC_CROSS_MODE_D 0, RO

TDR_P_LOC_CROSS_MODE_C 0, RO

TDR_P_LOC_CROSS_MODE_B 0, RO

TDR_P_LOC_CROSS_MODE_A 0, RO

Cross Detect on Channel D:

1 = Cross reflection detected on channel D. Indicates a short

between channels.

0 = No cross reflection detected.

10

9

Cross Detect on Channel C:

1 = Cross reflection detected on channel C. Indicates a short

between channels.

0 = No cross reflection detected.

Cross Detect on Channel B:

1 = Cross reflection detected on channel B. Indicates a short

between channels.

0 = No cross reflection detected.

8

Cross Detect on Channel A:

1 = Cross reflection detected on channel A. Indicates a short

between channels.

0 = No cross reflection detected.

7

TDR_P_LOC_OVERFLOW_D

TDR_P_LOC_OVERFLOW_C

TDR_P_LOC_OVERFLOW_B

TDR_P_LOC_OVERFLOW_A

RESERVED

0, RO

Peak Overflow on Channel D:

1 = More than 5 reflections were detected on channel D.

0 = Normal operation.

6

Peak Overflow on Channel C:

1 = More than 5 reflections were detected on channel C.

0 = Normal operation.

5

Peak Overflow on Channel B:

1 = More than 5 reflections were detected on channel B.

0 = Normal operation.

4

Peak Overflow on Channel A:

1 = More than 5 reflections were detected on channel A.

0 = Normal operation.

3:0

RESERVED

8.6.124 Programmable Gain Register (PROG_GAIN)

表8-133. Programmable Gain (PROG_GAIN), Address 0x01D5

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:4

3

RESERVED

1111 0101

RESERVED

0000, RW

0, RW

UNF_FUNC_MODE

For Force Mode Only

1 = Sets required swing level for compliance testing.

0 = Normal operation.

2

1

RESERVED

0, RW

RESERVED

SGMII_TX_POL_IN

SGMII TX Bus Polarity Invert

1 = Invert Polarity

0 = Normal Polarity

0

SGMII_RX_POL_IN

0, RW

SGMII RX Bus Polarity Invert

1= Invert Polarity

0 = Normal Polarity

8.6.125 MMD3 PCS Control Register (MMD3_PCS_CTRL)

This register is accessed via indirect register access. See 节8.4.2.1 for details

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表8-134. MMD3 PCS Control Register (MMD3_PCS_CTRL), MMD3 Address 0x0000

BIT

BIT NAME

DEFAULT

DESCRIPTION

15

PCS_RESET

0, RW, SC

MMD3 PCS Reset:

1 = Resets the MMD3 register. Note: Setting this bit will subsequently

cause a soft reset via the BMCR RESET bit (bit 15 of register

address 0x0000).

0 = Normal operation.

14:0

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The DP83867 is a single port 10/100/1000 Ethernet PHY. It supports connections to an Ethernet MAC through

SGMII or RGMII. Connections to the Ethernet media are made through the IEEE 802.3 defined Media

Dependent Interface.

When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation

of the device. The following typical application and design requirements can be used for selecting appropriate

component values for DP83867.

9.2 Typical Application

10BASE-Te

100BASE-TX

1000BASE-T

RGMII

SGMII

DP83867

10/100/1000 Mbps

Ethernet Physical Layer

Ethernet MAC

Magnetics

RJ-45

25 MHz

Crystal or Oscillator

Status

LEDs

图9-1. Typical DP83867 Application

9.2.1 Design Requirements

The design requirements for the DP83867 are:

• VDDA2P5 = 2.5 V

• VDD1P0 = 1 V

• VDDIO = 3.3 V, 2.5 V, or 1.8 V

• Clock Input = 25 MHz

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9.2.1.1 Cable Line Driver

The line driver implementation is designed to support simple connections to the transformer and the connector.

The DP83867 includes integrated terminations so no external termination resistors are required.

The connection diagram for the cable line driver is shown in 图9-2.

DP83867

Magnetics

RJ-45 Connector

Pin 1

TD_P_A

TD_M_A

TD_P_B

Pin 2

Pin 3

TD_M_B

TD_P_C

Pin 6

Pin 4

TD_M_C

TD_P_D

Pin 5

Pin 7

TD_M_D

Pin 8

0.1µF

75ꢀ

1nF

2kV

A. Each center tap on the side connected to the PHY, must be isolated from one another and connected to ground via a decoupling

capacitor (0.1 µF recommended).

B. Pulse Electronics part, HX5008FNL is recommended for a discrete magnetics solution.

图9-2. Magnetics Connections

Magnetic isolation used with the DP83867 can either be a discrete solution or integrated with the RJ-45

connector. Refer to 表9-1 for the electrical requirements.

表9-1. Magnetic Isolation Requirements

PARAMETER

Turns Ratio

TEST CONDITIONS

±2% Tolerance

-

TYP

1:1

UNIT

-

Open Circuit Inductance

Insertion Loss

320 to 350

-1

µH

dB

1-100 MHz

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表9-1. Magnetic Isolation Requirements (continued)

PARAMETER

TEST CONDITIONS

TYP

-16

UNIT

dB

1-30 MHz

Return Loss

30-60 MHz

60-100 MHz

1-50 MHz

-12

dB

-10

dB

-30

dB

Differential to Common Mode Rejection Ratio

50-150 MHz

30 MHz

-20

dB

-35

dB

Crosstalk

Isolation

60 MHz

-30

dB

HPOT

1500

Vrms

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9.2.1.2 Clock In (XI) Recommendation

If an external clock source is used, XO should be left floating. For a 1.8-V clock source, XI should be tied to the

clock source. For a 3.3-V or 2.5-V clock source, a capacitor divider is recommended as shown in 图 9-3. For a

3.3-V clock source, the CD1 and CD2 capacitors used are recommended to be 27 pF. If a 2.5-V clock source is

used check with the vendor for recommended capacitor loads. The values of CD1 and CD2 shall be adjusted to

meet XI Input pin specification defined in 节7.5.

XI

XO

3.3V or 2.5V

Clock Source

CD1

CD2

图9-3. Clock Divider

The CMOS 25-MHz oscillator specifications are listed in 表9-2. Additionally, the maximum oscillator phase noise

tolerated by the PHY is shown in 图9-4

表9-2. 25-MHz Oscillator Specifications

PARAMETER

Frequency

TEST CONDITION

MIN

TYP

MAX

UNIT

MHz

ppm

ns

25

Frequency Tolerance

Frequency Stability

Rise / Fall Time

Symmetry

Operational Temperature

1 year aging

±50

5

20% - 80%

Duty Cycle

40%

60%

11

Jitter RMS

Integration Band: 12 kHz to 5 MHz

ps

-85

-90

-95

-100

-105

-110

-115

-120

-125

-130

10

100

1000 10000

Frequency Offset (Hz)

100000

1000000

D001

图9-4. 25-MHz Oscillator Phase Noise

9.2.1.3 Crystal Recommendations

A 25-MHz, parallel, 18-pF load crystal resonator should be used if a crystal source is desired. 图 9-5 shows a

typical connection for a crystal resonator circuit. The load capacitor values vary with the crystal vendors; check

with the vendor for the recommended loads.

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XI

XO

R1

CL1

CL2

图9-5. Crystal Oscillator Circuit

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and

CL2 should be set at 27 pF, and R1 should be set at 0 Ω.

Specification for 25-MHz crystal are listed in 表9-3.

表9-3. 25-MHz Crystal Specifications

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Frequency

25

MHz

Frequency

Tolerance

Operational Temperature

1 year aging

±50

ppm

Frequency Stability

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9.2.1.4 Clock Out (CLK_OUT) Phase Noise

图9-6 provides a phase noise plot for the 25 MHz clock output from the device.

A. This measurement was taken on a DP83867 configured as a slave. The PHY was linked to another DP83867 configured as the master.

Both devices had PRBS enabled (BISCR, register 0x0016, configured to 0xD000).

B. The phase noise on the CLK_OUT pin before linkup and after link up with no packets being generated are expected to be lower than

pictured.

图9-6. 25 MHz Clock Output Phase Noise

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9.2.2 Detailed Design Procedure

9.2.2.1 MAC Interface

The Media Independent Interface (SGMII / RGMII) connects the DP83867 to the Media Access Controller

(MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU, or FPGA.

9.2.2.1.1 SGMII Layout Guidelines

• All SGMII connections must be AC-coupled through an 0.1-µF capacitor. Series capacitors must be 0.1 µF

and the size should be 0402 or smaller.

• SGMII signals are differential signals.

• Traces must be routed with 100-Ωdifferential impedance.

• Skew matching within a pair must be less than 5 pS, which correlates to 30 mil for standard FR4.

• There is no requirement to match the TX pair to the RX pair.

• SGMII signals must be routed on the same layer.

• Pairs must be referenced to parallel ground plane.

• When operating in 6-wire mode, the RX pair must match the Clock pair to within 5 pS, which correlates to 30

mil for standard FR4.

9.2.2.1.2 RGMII Layout Guidelines

• RGMII signals are single-ended signals.

• Traces must be routed with impedance of 50 Ωto ground.

• Skew between TXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

• Skew between RXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

• Keep trace lengths as short as possible; less than 2 inches is recommended with less than 6 inches as

maximum length.

• Configurable clock skew for GTX_CLK and RX_CLK.

– Clock skew for RX and TX paths can be optimized independently.

– Clock skew is adjustable in 0.25-ns increments (through register).

9.2.2.2 Media Dependent Interface (MDI)

The Media Dependent Interface (MDI) connects the DP83867 to the transformer and the Ethernet network.

9.2.2.2.1 MDI Layout Guidelines

• MDI traces must be 50 Ωto ground and 100 Ω-differential controlled impedance.

• Route MDI traces to transformer on the same layer.

• Use a metal shielded RJ-45 connector, and connect the shield to chassis ground.

• Use magnetics with integrated common-mode choking devices.

• Void supplies and ground beneath magnetics.

• Do not overlap the circuit and chassis ground planes, keep them isolated. Instead, make chassis ground an

isolated island and make a void between the chassis and circuit ground. Connecting circuit and chassis

planes using a size 1206 resistor and capacitor on either side of the connector is a good practice.

9.2.3 Application Curves

表9-4 lists the application curves for this application.

表9-4. Table of Graphs

TITLE

FIGURE

图7-9

1000Base-T Signaling

100Base-TX Signaling

图7-10

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10 Power Supply Recommendations

The DP83867 is capable of operating with as few as two or three supplies. The I/O power supply can also be

operated independently of the main device power supplies to provide flexibility for the MAC interface.

For detailed information about DP83867 power consumption for specific supplies under a wide set of conditions,

see the DP83867E/IS/CS/IR/CR RGZ Power Consumption Data application report (SNLA241).

The connection diagrams for the two-supply and three-supply configurations are shown in 图10-1 and 图10-2.

VDD1P0

VDDIO

1.0V

Supply

VDDIO

Supply

0.1 mF

1 mF

VDD1P0

10 mF 10 nF

10 nF 10 mF

1 mF

0.1 mF

VDDIO

VDD1P0

0.1 mF

VDDA2P5

VDDA1P8

2.5V

Supply

0.1 mF

1 mF

10 mF 10 nF

GND

(Die Attach Pad)

For two supply configuration, both VDDA1P8 pins must be left unconnected.

Place 1-µF and 0.1-µF decoupling capacitors as close as possible to component VDD pins, placing the 0.1-µF capacitor closest to the

pin.

VDDIO may be 3.3 V or 2.5 V or 1.8 V.

No Components should be connected to VDDA1P8 pins in Two-Supply Configuration.

图10-1. Two-Supply Configuration

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VDD1P0

VDDIO

1.0V

Supply

VDDIO

Supply

0.1 mF

1 mF

VDD1P0

10 mF 10 nF

10 nF 10 mF

1 mF

0.1 mF

VDDIO

VDD1P0

0.1 mF

VDDA2P5

VDDA1P8

2.5V

Supply

1.8V

Supply

0.1 mF

1 mF

0.1 mF

1 mF

10 mF 10 nF

1 mF 10 nF 10 mF

GND

(Die Attach Pad)

Place 1-µF and 0.1-µF decoupling capacitors as close as possible to component VDD pins, placing the 0.1-µF capacitor closest to the

pin.

Note: VDDIO may be 3.3 V or 2.5 V or 1.8 V.

图10-2. Three-Supply Configuration

There is no requirement for the sequence of the supplies when operating in two-supply mode.

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When operating in three-supply mode, the 1.8-V VDDA1P8 supply must be stable within 25 ms of the 2.5-V

VDDA2P5 supply ramping up. There is no sequencing requirement for other supplies when operating in three-

supply mode.

When powering down the DP83867, the 1.8-V supply should be brought down before the 2.5-V supply.

VDDA2P5

tt₁t

VDDA1P8

图10-3. Three-Supply Mode Power Supply Sequence Diagram

表10-1. Three-Supply Mode Power Supply Sequence

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

25 ms

Beginning of VDDA2P5 ramp up

to VDDA1P8 stable

T1

0

备注

If the 2.5-V power supply provides power to DP83867 devices only, the 1.8-V supply may ramp up any

time before 2.5-V.

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11 Layout

11.1 Layout Guidelines

11.1.1 Signal Traces

PCB traces are lossy and long traces can degrade the signal quality. Traces must be kept short as possible.

Unless mentioned otherwise, all signal traces should be 50-Ω, single-ended impedance. Differential traces

should be 50-Ω, single-ended and 100-Ω differential. Take care that the impedance is constant throughout.

Impedance discontinuities cause reflections leading to EMI & signal integrity problems. Stubs must be avoided

on all signal traces, especially the differential signal pairs. See 图11-1

Within the differential pairs, the trace lengths must run parallel to each other and matched in length. Matched

lengths minimize delay differences, avoiding an increase in common-mode noise and increased EMI.

Length matching is also important on MAC interface. All Transmit signal trace lengths must match to each other

and all Receive signal trace lengths must match to each other.

Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities and

should be minimized. Route an entire trace pair on a single layer if possible.

图11-1. Avoiding Stubs in a Differential Signal Pair

Signals on different layers should not cross each other without at least one return path plane between them.

Coupling between traces is also an important factor. Unwanted coupling can cause cross talk problems.

Differential pairs on the other hand, should have a constant coupling distance between them.

For convenience and efficient layout process, start by routing the critical signals first.

11.1.2 Return Path

A general best practice is to have a solid return path beneath all signal traces. This return path can be a

continuous ground or DC power plane. Reducing the width of the return path width can potentially affect the

impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to

the width of the signal trace. Breaks in return path beneath the signal traces should be avoided at all cost. A

signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality

as well, potentially creating EMI problems. See 图11-2

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图11-2. Differential Signal Pair-Plane Crossing

11.1.3 Transformer Layout

There should be no metal layer running beneath the transformer. Transformers can inject noise in metal beneath

them which can affect the performance of the system.

11.1.4 Metal Pour

All metal pours which are not signals or power should be tied to ground. There should be no floating metal on

the system. There should be no metal between the differential traces.

11.1.5 PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a 4-layer PCB should be used. However a

6-layer board is recommended. See 图 11-3 for the recommended layer stack ups for 4, 6 and 8-layer boards.

These are recommendations not requirements, other configurations can be used as per system requirements.

图11-3. Recommended Layer Stack Up

Within a PCB, it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the

location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated

chassis ground plane is used. 图11-4 illustrates alternative PCB stacking options.

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图11-4. Alternative Layer Stack Up

11.2 Layout Example

Plane

Coupling

Component

Transformer

RJ45

Connector

PHY

Component

(if not

Integrated in

RJ45)

Plane

Coupling

Component

Note: Power/Ground

Planes Voided under

Transformer

Chassis

Ground

Plane

System Power/

Ground Planes

图11-5. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• DP83867 Troubleshooting Guide (SNLA246)

• How to Configure DP838XX for Ethernet Compliance Testing (SNLA239)

• Configuring Ethernet Devices with 4-Level Straps (SNLA258)

• RGMII Interface Timing Budgets (SNLA243)

• DP83867E/IS/CS/IR/CR RGZ Power Consumption Data (SNLA241)

• How to Configure DP83867 Start of Frame (SNLA242)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

表12-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

DP83867CS

DP83867IS

DP83867E

Click here

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12.7 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

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PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

0.18

36

48X

1

0.1

0.05

C B A

48

37

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

METAL

TYP

(

1.17)

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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型号：	DP83867ISRGZT
厂家：	TEXAS INSTRUMENTS
描述：	支持 SGMII 接口、具有工业级温度范围的耐用型千兆位以太网 PHY 收发器 \| RGZ \| 48 \| -40 to 85 以太网
文件：	总125页 (文件大小：3177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83867ISRGZT [TI]

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