DP83TC813SRHFRQ1 [TI]
汽车级低功耗、小型封装 100BASE-T1 以太网 PHY (SGMII) | RHF | 28 | -40 to 125;型号: | DP83TC813SRHFRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 汽车级低功耗、小型封装 100BASE-T1 以太网 PHY (SGMII) | RHF | 28 | -40 to 125 以太网 |
文件: | 总195页 (文件大小:5422K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DP83TC813S-Q1, DP83TC813R-Q1
ZHCSQL1 –MAY 2022
DP83TC813x-Q1 符合TC-10 标准的小尺寸100BASE-T1 汽车以太网PHY
1 特性
3 说明
• 符合Open Alliance 和IEEE 802.3bw 100BASE-T1
标准
DP83TC813-Q1 器件是一款符合IEEE 802.3bw 标准
的汽车PHYTER™ 以太网物理层收发器,可使用非屏
蔽双绞线电缆。PHY 支持TC10 睡眠和唤醒功能。它
提供通过单一屏蔽双绞线电缆发送和接收数据所需的所
有物理层功能。该器件具有xMII 灵活性,支持标准
MII、RMII、RGMII 和SGMII MAC 接口。PHY 还在
MDI 侧集成了低通滤波器,从而减少排放。
– 借助集成式LPF 满足IV 级排放标准
– 符合TC-10 标准且休眠电流< 20μA
• 外形小巧:28 引脚VQFN (5mm x 4mm)
• 符合SAE J2962-3 EMC 标准
• 可配置的I/O 电压:3.3V、2.5V 和1.8V
• MAC 接口:MII、RMII、RGMII 和SGMII
• MAC 接口引脚可选独立电压轨(3.3V、2.5V、
1.8V)
该器件包含诊断工具套件,从而提供广泛的实时监控工
具、调试工具和测试模式。该工具套件中包含首款集成
式静电放电(ESD) 监控工具。它能够对MDI 上的ESD
事件进行计数,并且能够通过使用可编程中断提供实时
监控。此外,DP83TC813-Q1 还包含一个假随机二进
制序列(PRBS) 帧生成工具,该工具与内部环回完全兼
容,能够在不使用 MAC 的情况下发送和接收数据。该
器件采用 5.00mm × 4.00mm、28 引脚 VQFN 可湿侧
面封装。
• 符合面向汽车应用的AEC-Q100 标准:
– 温度等级1: –40°C 至+125 °C 的工作环境温度
范围
– 面向引脚19 和20 的±8kV HBM ESD
– 引脚19 和20 的IEC61000-4-2 ESD 分级等级
为4:±8kV 接触放电
• 支持IEEE 1588 SFD
• 符合TSN 标准,支持802.3br 帧抢占
• 低有功功率运行:< 230mW
• 诊断工具套件
器件信息
封装(1)
VQFN (28)
VQFN (28)
封装尺寸(标称值)
5.00mm × 4.00mm
5.00mm × 4.00mm
零件编号
DP83TC813S-Q1
DP83TC813R-Q1
– 信号质量指示(SQI)
– 时域反射(TDR)
– 静电放电传感器
– 电压传感器
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
– PRBS 内置自检
– 环回
• VQFN,可湿侧面封装
2 应用
• ADAS
• 网关和车身控制
• 远程信息处理
100BASE-T1
IEEE 802.3bw
MII
RMII
RGMII
CMC
DP83TC81xS-Q1
100BASE-T1
Ethernet PHY
SGMII
CPU/MPU
MAC
Automotive
Connector
CM
Termination
25MHz
Clock Source
Status
LEDs
GND
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS676
DP83TC813S-Q1, DP83TC813R-Q1
ZHCSQL1 –MAY 2022
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Table of Contents
8.4 Device Functional Modes..........................................45
8.5 Programming............................................................ 59
8.6 Register Maps...........................................................63
9 Application and Implementation................................174
9.1 Application Information........................................... 174
9.2 Typical Applications................................................ 174
10 Power Supply Recommendations............................181
11 Layout.........................................................................183
11.1 Layout Guidelines................................................. 183
11.2 Layout Example.................................................... 185
12 Device and Documentation Support........................186
12.1 Receiving Notification of Documentation Updates186
12.2 支持资源................................................................186
12.3 Community Resources..........................................186
12.4 Trademarks...........................................................186
12.5 Electrostatic Discharge Caution............................186
12.6 术语表................................................................... 186
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications................................................................ 16
7.1 Absolute Maximum Ratings...................................... 16
7.2 ESD Ratings............................................................. 16
7.3 Recommended Operating Conditions.......................16
7.4 Thermal Information..................................................17
7.5 Electrical Characteristics...........................................17
7.6 Timing Requirements................................................22
7.7 Timing Diagrams.......................................................25
7.8 Typical Characteristics..............................................32
8 Detailed Description......................................................34
8.1 Overview...................................................................34
8.2 Functional Block Diagram.........................................35
8.3 Feature Description...................................................36
Information.................................................................. 186
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
May 2022
*
Initial Release
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5 Device Comparison Table
PART
SGMII
OPERATING
NUMBER
SUPPORT
TEMPERATURE
DP83TC813R-Q1
DP83TC813S-Q1
No
–40°C to 125°C
–40°C to 125°C
Yes
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6 Pin Configuration and Functions
22
21
20
19
18
17
16
15
VDDMAC
23
24
25
26
27
28
14
13
12
11
10
9
CLKOUT/LED_1
RX_D3/RX_M
XI
RX_D2/RX_P
RX_D1
XO
GND
RESET_N
INT_N
MDC
RX_D0
RX_CLK
1
2
3
4
5
6
7
8
图6-1. DP83TC813S-Q1 RHF Package
28-Pin VQFN
Top View
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22
21
20
19
18
17
16
15
VDDMAC
RX_D3
23
24
25
26
27
28
14
13
12
11
10
9
CLKOUT/LED_1
XI
RX_D2
RX_D1
XO
GND
RESET_N
INT_N
MDC
RX_D0
RX_CLK
1
2
3
4
5
6
7
8
图6-2. DP83TC813R-Q1 RHF Package
28-Pin VQFN
Top View
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表6-1. Pin Functions
PIN
STATE1
DESCRIPTION
NAME2
NO.
MAC INTERFACE
RX_D3
Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the
rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted
in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII
mode.
24
RX_M
RX_D2
RX_P
25
S, PD, O
If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted on RX_D3.
This clock must be fed to the MAC.
RX_D1
RX_D0
26
27
RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC.
Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock.
RX_CLK
28
S, PD, O
S, PD, O
Unused in RMII and SGMII modes
Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a
received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode,
RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used
by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error.
Unused in RGMII and SGMII modes
RX_ER
21
Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.
Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When
CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.
RX_DV
CRS_DV
RX_CTRL
22
S, PD, O
PD, I, O
PD, I
RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a
single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of
RX_CLK.
Unused in SGMII mode
Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase referenced to the
reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25-MHz clock must be
provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled).
Unused in RMII and SGMII modes
TX_CLK
1
Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN
indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the
rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].
RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single
signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of
TX_CLK.
TX_EN
TX_CTRL
2
Unused in SGMII mode
TX_D3
TX_D2
3
4
Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the
rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference
clock. TX_D[3:2] are not used in RMII mode.
TX_D1
TX_P
5
6
PD, I
TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.
TX_D0
TX_M
SERIAL MANAGEMENT INTERFACE
Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock
MDC
9
I
may be asynchronous to the MAC transmit and receive clocks.
Management Data Input/Output: Bidirectional management data signal that may be sourced by the management
station or the PHY. This pin requires a pullup resistor. In systems with multiple PHYs using same MDIO-MDC bus, a
single pull-up resistor must be used on MDIO line.
MDIO
8
OD, IO
Recommended to use a resistor between 2.2 kΩand 9 kΩ.
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表6-1. Pin Functions (continued)
PIN
STATE1
DESCRIPTION
NAME2
NO.
CONTROL INTERFACE
Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak
internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set,
register access is required to clear the interrupt event. This pin can be configured as an Active-HIGH output using
register 0x0011.
INT
10
PU, OD, IO
This pin can also operate as Power-Down control where asserting this pin low would put the PHY in power down
mode and asserting high would put the PHY in normal mode. This feature can also be enabled via register 0x0011.
Reset: Active-LOW input, which initializes or reinitializes the PHY. Asserting this pin LOW for at least 1 μs will
force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in
the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.
RESET
WAKE
INH
11
16
17
PU, I
PD, I/O
O, OD
WAKE: Active-HIGH input, which wakes the PHY from TC-10 SLEEP. Asserting this pin HIGH at power-up will
prevent the PHY from going to SLEEP. External 10kΩ pull down resistor can be used when implementing TC-10
circuit to prevent accidental wake-up. This pin can be directly tied to VSLEEP to wake the device.
INH: Active-HIGH output. This pin will be Hi-Z when the PHY is in TC-10 SLEEP. This pin is HIGH for all other PHY
states. External 2kΩ - 10kΩ pull down resistor must be used when implementing TC-10 circuit. If multiple devices
are sharing INH pin, then a single pull down resistor must be used.
CLOCK INTERFACE
Reference Clock Input (RMII): Reference clock 50-MHz CMOS-level oscillator in RMII Slave mode. Reference
clock 25-MHz crystal or oscillator in RMII Master mode.
XI
13
I
Reference Clock Input (Other MAC Interfaces): Reference clock 25-MHz crystal or oscillator input. The device
supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator
connected to pin XI only and XO left floating.
Reference Clock Output: XO pin is used for crystal only. This pin must be left floating when a CMOS-level
XO
12
O
oscillator is connected to XI.
LED/GPIO INTERFACE
CLKOUT /
14
IO
Clock Output: 25-MHz reference clock. This pin can be used as LED or GPIO via register configuration.
LED_1
MEDIUM DEPENDENT INTERFACE
TRD_M
TRD_P
20
19
Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE
IO
802.3bw compliant.
POWER CONNECTIONS
Core Supply: 3.3 V
VDDA
18
7
SUPPLY
SUPPLY
Recommend using 0.47-µF and 0.01-µF ceramic decoupling capacitors; optional ferrite bead can also be used.
IO Supply: 1.8 V, 2.5 V, or 3.3 V
VDDIO
Recommend using ferrite bead 0.47-µF, and 0.01-µF ceramic decoupling capacitors.
Optional MAC Interface Supply: 1.8 V, 2.5 V, or 3.3 V
Optional separate supply for MAC interface pins. This pin supplies power to the MAC interface pins and can be kept
at a different voltage level as compared to other IO pins. Recommend using 0.47-µF, and 0.01-µF ceramic
decoupling capacitors; optional ferrite bead. When separate VDDMAC is not required in the system then it must be
connected to VDDIO. When connecting to VDDIO, 0.47-µF can be removed.
VDDMAC
23
SUPPLY
VSLEEP Supply: 3.3 V
VSLEEP
15
SUPPLY
Recommend using 0.1-µF ceramic decoupling capacitors.
GROUND
DAP
GROUND
Ground: This must always be connected to power ground.
1. Pin Type:
I = Input
O = Output
IO = Input/Output
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OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)
2. When pins are unused, follow the recommended connection requirements provided in the table above. If
pins do not have required termination, they may be left floating.
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表6-2. Pin Domain
PIN NAME
MDC
PIN NO
9
VOLTAGE DOMAIN
VDDIO
10
11
12
13
14
16
17
19
20
21
22
24
25
26
27
28
1
INT_N
VDDIO
RESET_N
XO
VDDIO
VDDIO
XI
VDDIO
LED_1/GPIO_1
WAKE
VDDIO
VSLEEP
VSLEEP
VDDA
INH
TRD_P
TRD_M
VDDA
RX_ER
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDMAC
VDDIO
RX_DV/CRS_DV/RX_CTRL
RX_D3/RX_M
RX_D2/RX_P
RX_D1
RX_D0
RX_CLK
TX_CLK
2
TX_EN/TX_CTRL
TX_D3
3
4
TX_D2
5
TX_D1/TX_P
TX_D0/TX_M
MDIO
6
8
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表6-3. Pin States - POWER-UP / RESET
POWER-UP / RESET
PIN
PIN NO
NAME
PULL VALUE
PIN STATE (1)
PULL TYPE
(kΩ)
none
9
9
MDC
INT
I
none
PU
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
I
RESET
XO
I
PU
9
O
none
none
none
PD
none
none
none
455
none
none
none
none
6
XI
I
VSLEEP
WAKE
INH
SUPPLY
I/O
OD, O
none
none
none
none
PD
VDDA
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
SUPPLY
IO
IO
I
I
PD
6
SUPPLY
none
PD
none
9
I
I
PD
9
I
PD
9
I
PD
9
I
PD
9
I
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
2
I
3
I
4
I
5
I
6
I
7
SUPPLY
OD, IO
8
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PIN NO
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表6-4. Pin States - TC10 SLEEP
TC10 SLEEP (All Supplies On)
PIN
NAME
PULL VALUE
PIN STATE (1)
PULL TYPE
(kΩ)
9
MDC
INT
I
none
PU
none
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
I
RESET
XO
I
PU
9
O
none
none
none
PD
none
none
none
455
none
none
none
none
6
XI
I
VSLEEP
WAKE
INH
SUPPLY
I/O
OD, O
none
none
none
none
PD
VDDA
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
SUPPLY
IO
IO
I
I
PD
6
SUPPLY
none
PD
none
9
I
I
PD
9
I
PD
9
I
PD
9
I
PD
9
I
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
2
I
3
I
4
I
5
I
6
I
7
SUPPLY
OD, IO
8
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表6-5. Pin States - MAC ISOLATE and IEEE PWDN
MAC ISOLATE
IEEE PWDN
PULL TYPE
PIN
NAME
PIN NO
PULL VALUE
PULL VALUE
PIN STATE (1)
PULL TYPE
PIN STATE (1)
(kΩ)
(kΩ)
9
MDC
INT
I
none
PU
none
9
I
none
PU
none
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
OD, O
OD, O
RESET
XO
I
PU
9
I
PU
9
O
none
none
none
PD
none
none
none
455
none
none
none
none
6
O
none
none
none
PD
none
none
none
455
XI
I
I
VSLEEP
WAKE
INH
SUPPLY
SUPPLY
IO
IO
OD, O
none
none
none
none
PD
OD, O
none
none
none
none
PD
none
none
none
none
6
VDDA
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
SUPPLY
SUPPLY
IO
IO
IO
IO
I
I
I
PD
6
O
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
SUPPLY
none
PD
none
9
SUPPLY
I
O
I
PD
9
O
I
PD
9
O
I
PD
9
O
I
PD
9
O
I
PD
9
I
2
I
PD
9
I
3
I
PD
9
I
4
I
PD
9
I
5
I
PD
9
I
6
I
PD
9
I
7
SUPPLY
OD, IO
none
none
none
none
SUPPLY
OD, IO
8
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PIN NO
ZHCSQL1 –MAY 2022
表6-6. Pin States - MII and RGMII
MII
RGMII
PIN
NAME
PULL VALUE
PULL VALUE
PIN STATE (1)
PULL TYPE
PIN STATE (1)
PULL TYPE
(kΩ)
(kΩ)
none
9
9
MDC
INT
I
none
PU
none
9
I
none
PU
10
11
12
13
OD, O
OD, O
RESET
XO
I
PU
9
I
PU
9
O
none
none
none
PD
none
none
none
455
O
none
none
none
PD
none
none
none
455
XI
I
I
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
VSLEEP
WAKE
SUPPLY
SUPPLY
IO
IO
INH
OD, O
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
OD, O
none
none
none
none
PD
none
none
none
none
6
VDDA
SUPPLY
SUPPLY
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
IO
IO
IO
IO
O
I
O
O
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
SUPPLY
SUPPLY
O
O
O
O
O
O
O
O
O
O
O
I
2
I
I
3
I
I
4
I
I
5
I
I
6
I
I
7
SUPPLY
OD, IO
SUPPLY
OD, IO
8
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表6-7. Pin States - RMII MASTER and RMII SLAVE
RMII MASTER
RMII SLAVE
PULL TYPE
PIN
NAME
PIN NO
PULL VALUE
PULL VALUE
PIN STATE (1)
PULL TYPE
PIN STATE (1)
(kΩ)
(kΩ)
9
MDC
INT
I
none
PU
none
9
I
none
PU
none
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
OD, O
OD, O
RESET
XO
I
PU
9
I
PU
9
O
none
none
none
PD
none
none
none
455
O
none
none
none
PD
none
none
none
455
XI
I
I
VSLEEP
WAKE
INH
SUPPLY
SUPPLY
IO
IO
OD, O
none
none
none
none
none
none
none
none
PD
none
none
none
none
none
none
none
none
9
OD, O
none
none
none
none
none
none
none
PD
none
none
none
none
none
none
none
9
VDDA
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
SUPPLY
SUPPLY
IO
IO
IO
IO
O
O
O
O
SUPPLY
SUPPLY
O, 50MHz
I
I
I
PD
9
O
none
none
PD
none
none
9
O
none
none
PD
none
none
9
O
O
I
I
I
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
I
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
2
I
I
3
I
I
4
I
I
5
I
I
6
I
I
7
SUPPLY
OD, IO
SUPPLY
OD, IO
8
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PIN NO
ZHCSQL1 –MAY 2022
表6-8. Pin States - SGMII
SGMII
PIN
NAME
PULL VALUE
PIN STATE (1)
PULL TYPE
(kΩ)
9
MDC
INT
I
none
PU
none
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
OD, O
RESET
XO
I
PU
9
O
none
none
none
PD
none
none
none
455
none
none
none
none
6
XI
I
VSLEEP
WAKE
INH
SUPPLY
IO
OD, O
none
none
none
none
PD
VDDA
TRD_P
TRD_M
RX_ER
RX_DV
VDDMAC
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
TX_CLK
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
VDDIO
MDIO
SUPPLY
IO
IO
I
I
PD
6
SUPPLY
none
none
none
PD
none
none
none
9
O
O
I
I
PD
9
I
PD
9
I
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
2
I
3
I
4
I
5
I
6
I
7
SUPPLY
OD, IO
8
(1) Type: I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
–0.3
-0.3
TYP
MAX
UNIT
V
Input Voltage VDDA
4
4
4
4
4
4
Input Voltage VDDIO/VDDMAC (3.3V)
Input Voltage VDDIO/VDDMAC (2.5V)
Input Voltage VDDIO/VDDMAC (1.8V)
Input Voltage VSLEEP
V
V
V
V
Pins
Pins
Pins
Pins
MDI
V
–0.3
VDDMAC +
0.3
MAC interface
V
V
V
–0.3
–0.3
–0.3
MDIO, MDC, GPIO, XI, XO, INT, RESET, CLKOUT
WAKE, INH
VDDIO + 0.3
VSLEEP +
0.3
DC Output
Voltage
All Pins
4
V
–0.3
TJ
Junction Temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE UNIT
All pins
±2000
±8000
±750
Human body model (HBM), per
AEC Q100-002(1)
TRD_N, TRD_P pins
Corner pins
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per
AEC Q100-011
Other pins
±750
IEC 61000-4-2 contact discharge
TRD_N, TRD_P pins
±8000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
2.25
2.97
2.97
2.97
–40
NOM
1.8
MAX
1.98
2.75
3.63
3.63
3.63
125
UNIT
IO Supply Voltage, 1.8V operation
IO Supply Voltage, 2.5V operation
IO Supply Voltage, 3.3V operation
Core Supply Voltage, 3.3V
VDDIO /
VDDMAC
2.5
V
3.3
VDDA
VSLEEP
TA
3.3
V
V
Sleep Supply Voltage, 3.3V
Ambient temperature
3.3
°C
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7.4 Thermal Information
DP83TC813
THERMAL METRIC(1)
RHF (VQFN)
28 PINS
39.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.6
17.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ΨJT
17.4
ΨJB
RθJC(bot)
5.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100BASE-T1 PMA CONFORMANCE
Output Differential
VOD-MDI
Voltage
2.2
V
RL(diff) = 100Ω
TRD_P and TRD_M
Integrated Differential
RMDI-Diff
100
Ω
Output Termination
BOOTSTRAP DC CHARACTERISTICS (2 Level)
Mode 1 Strap Voltage
Range
VMODE1
VMODE2
VMODE1
VMODE2
VMODE1
VMODE2
VDDIO = 3.3V ±10%, 2-level strap
0
2
0.8
VDDIO
0.7
V
V
V
V
V
V
Mode 2 Strap Voltage
Range
VDDIO = 3.3V ±10%, 2-level strap
VDDIO = 2.5V ±10%, 2-level strap
VDDIO = 2.5V ±10%, 2-level strap
VDDIO = 1.8V ±10%, 2-level strap
VDDIO = 1.8V ±10%, 2-level strap
Mode 1 Strap Voltage
Range
0
Mode 2 Strap Voltage
Range
1.5
0
VDDIO
Mode 1 Strap Voltage
Range
0.35 x
VDDIO
Mode 2 Strap Voltage
Range
0.65 x
VDDIO
VDDIO
BOOTSTRAP DC CHARACTERISTICS (3 Level)
Mode 1 Strap Voltage
Range
0.18 x
VDDIO
VMODE1
VMODE2
VMODE3
VMODE1
VMODE2
VMODE3
VMODE1
VMODE2
VDDIO = 3.3V ±10%, 3-level strap
0
V
V
V
V
V
V
V
V
Mode 2 Strap Voltage
Range
0.22 x
VDDIO
0.42 x
VDDIO
VDDIO = 3.3V ±10%, 3-level strap
VDDIO = 3.3V ±10%, 3-level strap
VDDIO = 2.5V ±10%, 3-level strap
VDDIO = 2.5V ±10%, 3-level strap
VDDIO = 2.5V ±10%, 3-level strap
VDDIO = 1.8V ±10%, 3-level strap
VDDIO = 1.8V ±10%, 3-level strap
Mode 3 Strap Voltage
Range
0.46 x
VDDIO
VDDIO
Mode 1 Strap Voltage
Range
0.19 x
VDDIO
0
Mode 2 Strap Voltage
Range
0.27 x
VDDIO
0.41 x
VDDIO
Mode 3 Strap Voltage
Range
0.58 x
VDDIO
VDDIO
Mode 1 Strap Voltage
Range
0.35 x
VDDIO
0
Mode 2 Strap Voltage
Range
0.40 x
VDDIO
0.75 x
VDDIO
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Mode 3 Strap Voltage
Range
IO CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.84 x
VDDIO
VMODE3
VDDIO = 1.8V ±10%, 3-level strap
VDDIO
V
High Level Input
Voltage
VIH
VIL
VDDIO = 3.3V ±10%
2
2.4
1.7
2
V
V
V
V
V
V
V
V
V
V
V
V
µA
Low Level Input
Voltage
VDDIO = 3.3V ±10%
0.8
0.4
0.7
0.4
High Level Output
Voltage
VOH
VOL
VIH
VIL
IOH = -2mA, VDDIO = 3.3V ±10%
IOL = 2mA, VDDIO = 3.3V ±10%
VDDIO = 2.5V ±10%
Low Level Output
Voltage
High Level Input
Voltage
Low Level Input
Voltage
VDDIO = 2.5V ±10%
High Level Output
Voltage
VOH
VOL
VIH
VIL
IOH = -2mA, VDDIO = 2.5V ±10%
IOL = 2mA, VDDIO = 2.5V ±10%
VDDIO = 1.8V ±10%
Low Level Output
Voltage
High Level Input
Voltage
0.65*VDDI
O
Low Level Input
Voltage
0.35*VDDI
O
VDDIO = 1.8V ±10%
High Level Output
Voltage
VDDIO-0.
45
VOH
VOL
IIH
IOH = -2mA, VDDIO = 1.8V ±10%
IOL = 2mA, VDDIO = 1.8V ±10%
Low Level Output
Voltage
0.45
10
TA = -40℃to 125℃, VIN=VDDIO, All pins
except XI and WAKE
Input High Current(1)
-10
IIH-XI
IIL-XI
Input High Current(1)
Input Low Current(1)
-15
-15
15
15
µA
µA
TA = -40℃to 125℃, VIN=VDDIO, XI pin
TA = -40℃to 125℃, VIN=GND, XI pin
TA = -40℃to 125℃, VIN=GND, All pins except
XI pin
IIL
Input Low Current(1)
-10
-10
10
10
µA
µA
Tri-state Output High
Current(2)
TA = -40℃to 125℃, VIN=VDDIO, All pins
except RX_CTRL and RX_ER
Iozh
Tri-state Output High
Current(2)
TA = -40℃to 125℃, VIN=VDDIO, RX_CTRL
and RX_ER
Iozh
-52
52
µA
µA
kΩ
kΩ
kΩ
kΩ
V
Tri-state Output Low
Current(2)
Iozl
-10
10
TA = -40℃to 125℃, VOUT=GND
RX_D[3:0], RX_CLK, LED_1
RX_CTRL, RX_ER
WAKE
Internal Pull Down
Resistor
Rpulldn
Rpulldn
Rpulldn
Rpullup
XI VIH
XI VIL
6.2
8.4
5.8
455
9
10.7
7.2
Internal Pull Down
Resistor
4.725
Internal Pull Down
Resistor
Internal Pull Up
Resistor
INT, RESET
6.3
1.3
11.2
VDDIO
0.5
High Level Input
Voltage
Low Level Input
Voltage
V
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CIN
CIN
Input Capacitance XI
1
pF
Input Capacitance
INPUT PINS
5
1
pF
pF
pF
Ω
Output Capacitance
XO
COUT
COUT
Rseries
Output Capacitance
OUTPUT PINS
5
Integrated MAC Series
Termination Resistor
RX_D[3:0], RX_ER, RX_DV, RX_CLK
35
50
65
POWER CONSUMPTION
I(3V3)
MII
57
57
57
81
19
18
13
7
63
63
63
95
24
23
21
12
18
17
16
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40℃to 125℃
I(3V3)
RMII
RGMII
SGMII
MII
-40℃to 125℃
I(3V3)
-40℃to 125℃
I(3V3)
-40℃to 125℃
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=2.5V)
I(VDDIO=2.5V)
I(VDDIO=2.5V)
I(VDDIO=2.5V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
-40℃to 125℃, VDDIO = VDDMAC
RMII
RGMII
SGMII
MII
12
12
12
6
RMII
RGMII
SGMII
MII
9
13
13
12
6
RMII
RGMII
SGMII
9
9
4
POWER CONSUMPTION (LOW POWER MODE)
I(VDDA3V3)
I(VDDA3V3)
I(VDDA3V3)
I(VDDA3V3)
I(VDDA3V3)
I(VDDA3V3)
I(VDDA3V3)
IEEE Power Down
TC-10 Sleep
RESET
8
30
9
22
50
23
33
30
30
30
mA
mA
mA
mA
mA
mA
mA
-40℃to 125℃, All interfaces
-40℃to 125℃, All interfaces
-40℃to 125℃, All interfaces
-40℃to 125℃, MII
Standby
15
15
15
15
Standby
-40℃to 125℃, RMII
Standby
-40℃to 125℃, RGMII
-40℃to 125℃, SGMII
Standby
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=3.3V)
IEEE Power Down
TC-10 Sleep
RESET
15
15
15
23
23
23
mA
mA
mA
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=3.3V)
I(VDDIO=3.3V)
Standby
Standby
Standby
Standby
19
16
14
14
25
20
20
16
mA
mA
mA
mA
-40℃to 125℃, MII, VDDIO=VDDMAC
-40℃to 125℃, RMII, VDDIO=VDDMAC
-40℃to 125℃, RGMII, VDDIO=VDDMAC
-40℃to 125℃, SGMII, VDDIO=VDDMAC
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=2.5V)
IEEE Power Down
TC-10 Sleep
RESET
10
16
16
16
mA
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=2.5V)
I(VDDIO=2.5V)
10
10
mA
mA
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=2.5V)
I(VDDIO=2.5V)
I(VDDIO=2.5V)
I(VDDIO=2.5V)
Standby
Standby
Standby
Standby
14
11
9
18
14
14
14
mA
mA
mA
mA
-40℃to 125℃, MII, VDDIO=VDDMAC
-40℃to 125℃, RMII, VDDIO=VDDMAC
-40℃to 125℃, RGMII, VDDIO=VDDMAC
-40℃to 125℃, SGMII, VDDIO=VDDMAC
9
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=1.8V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
IEEE Power Down
TC-10 Sleep
RESET
7
7
7
11
11
11
mA
mA
mA
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
-40℃to 125℃, All interfaces,
VDDIO=VDDMAC
I(VDDIO=1.8V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
I(VDDIO=1.8V)
Standby
Standby
Standby
Standby
10
7
12
11
11
11
mA
mA
mA
mA
-40℃to 125℃, MII, VDDIO=VDDMAC
-40℃to 125℃, RMII, VDDIO=VDDMAC
-40℃to 125℃, RGMII, VDDIO=VDDMAC
-40℃to 125℃, SGMII, VDDIO=VDDMAC
6
6
-40℃to 125℃, All interfaces, All other
supplies are off
I(VSLEEP)
SGMII Input
VIDTH
TC-10 Sleep
7
18
µA
Input differential
voltage threshold
SI_P and SI_N, AC coupled
0.1
80
V
Receiver differential
input impedance (DC)
RIN-DIFF
120
ohm
SGMII Output
SO_P and SO_N, AC coupled, 0101010101
pattern
Clock signal duty cycle
48
52
%
Output Differential
Voltage
SO_P and SO_N, AC coupled
150
400
mV
Voltage Sensor
VDDA Sensor Range
2.7
3.3
8.8
4
V
-40℃to +125℃
-40℃to +125℃
VDDA Sensor
Resolution (LSB)
mV
VDDA Sensor
Accuracy (voltage and
temperature variation
on single part)
VDDA
-120
-50
120
50
mV
mV
-40℃to +125℃
-40℃to +125℃
VDDA Sensor
Accuracy (part-part
variation)
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDIO / VDDMAC
Sensor Range
1.44
3.9
V
-40℃to +125℃
VDDIO / VDDMAC
Sensor Resolution
(LSB)
16
mV
mV
-40℃to +125℃
-40℃to +125℃
VDDIO / VDDMAC
Sensor Accuracy
(voltage and
VDDIO /
VDDMAC
-144
144
temperature variation
on single part)
VDDIO /
VDDMAC Sensor
Accuracy (part-part
variation)
-85
2.7
85
4
mV
-40℃to +125℃
VSLEEP Sensor
Range
3.3
8.8
V
-40℃to +125℃
-40℃to +125℃
VSLEEP Sensor
Resolution (LSB)
mV
VSLEEP Sensor
VSLEEP
Accuracy (voltage and
temperature variation
on single part)
-120
-50
120
50
mV
mV
-40℃to +125℃
-40℃to +125℃
VSLEEP Sensor
Accuracy (part-part
variation)
(1) For pins: MDC, TX_CLK, TX_CTRL, TX_D[3:0], and RESET_N
(2) For pins: RX_D[3:0], RX_CLK, RX_CTRL, MDIO, INT_N, and XO.
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7.6 Timing Requirements
TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
MII TIMING
T1.1
T1.2
T1.3
T2.1
T2.2
TX_CLK High / Low Time
16
10
0
20
24
ns
ns
ns
ns
ns
TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK
TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK
RX_CLK High / Low Time
16
10
20
20
24
30
RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising
RMII MASTER TIMING
T3.1
RMII Master Clock Period
ns
%
RMII Master Clock Duty Cycle
35
4
65
14
65
T3.2
T3.3
TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock
TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock
ns
ns
2
RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock
rising edge
T3.4
4
10
20
ns
RMII SLAVE TIMING
T3.1
Input Reference Clock Period
ns
%
Reference Clock Duty Cycle
35
4
T3.2
T3.3
T3.4
TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising
TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising
RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising
ns
ns
ns
2
4
14
44
RGMII INPUT TIMING
Tcyc
Clock Cycle Duration
TX_CLK
36
1
40
2
ns
ns
ns
Tsetup(alig
TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode)
n)
Thold(align) TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode)
RGMII OUTPUT TIMING
1
2
Tskew(align RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode
On PHY Pins
On PHY Pins
-750
2
750
ps
ns
Enabled)
)
Tsetup(shift RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode
Enabled, default)
)
Tcyc
Clock Cycle Duration
RX_CLK
36
45
40
50
44
55
ns
%
Duty_G Duty Cycle
RX_CLK
Tr/Tf
Rise / Fall Time ( 20% to 80%)
CLOAD = 5pF
1.2
ns
SMI TIMING
25pF load
capacitance
T4.1
MDC to MDIO (Output) Delay Time
0
40
20
ns
T4.2
T4.3
MDIO (Input) to MDC Setup Time
MDIO (Input) to MDC Hold Time
MDC Frequency
10
10
ns
ns
2.5
MHz
POWER-UP TIMING
T5.1
T5.1
T5.2
T5.3
T5.4
Supply ramp time: For all supplies except VSLEEP (1)
0.2
0.4
8
8
ms
ms
ms
ms
ms
ms
Supply ramp time: For VSLEEP(1)
Supply ramp delay offset: For all supplies
XTAL Startup / Settling: Powerup to XI good/stabilized
Oscillator stabilization time from power up
Last Supply power up To Reset Release
10
0.35
10
10
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7.6 Timing Requirements (continued)
TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
Post power-up to SMI ready: Post Power-up wait time required
before MDC preamble can be sent for register access
T5.5
10
ms
T5.6
T5.7
T5.8
Power-up to Strap latch-in
10
10
10
ms
ms
ms
CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized
Power-up to idle stream
RESET TIMING (RESET_N)
Reset Pulse Width: Miminum Reset pulse width to be able to
reset
T6.1
T6.2
720
1
ns
Reset to SMI ready: Post reset wait time required before MDC
preamble can be sent for register access
ms
Reset to Strap latch-in: Hardware configuration pins transition
to output drivers
T6.3
T6.4
40
µs
µs
Reset to idle stream
1800
WAKE REQUEST AND WAKE PULSE TIMING
T7.1
T7.2
T7.3
T7.4
T7.5
Local Wake-Up Pulse Duration
40
µs
µs
Local Wake-Up to INH Transition
40
0.7
0.7
1.4
Energy-detect-based Wake-Up Pulse Duration
Energy-detect-based Wake-Up to INH Transition
Energy-detect-based Wake-Up to WAKE forwarding pulse
ms
ms
ms
TRANSMIT LATENCY TIMING
MII Rising edge TX_CLK with assertion TX_EN to SSD symbol
205
374
382
233
409
408
ns
ns
ns
on MD
Slave RMII Rising edge XI clock with assertion TX_EN to SSD
symbol on MDI
Master RMII Rising edge clock with assertion TX_EN to SSD
symbol on MDI
RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD
symbol on MDI
370
420
390
456
ns
ns
First symbol of SGMII to SSD symbol on MDI
RECEIVE LATENCY TIMING
SSD symbol on MDI to MII Rising edge of RX_CLK with
assertion of RX_DV
467
527
521
491
574
557
ns
ns
ns
SSD symbol on MDI to Slave RMII Rising edge of XI clock with
assertion of CRS_DV
SSD symbol on MDI to Master RMII Rising edge of Master
clock with assertion of CRS_DV
SSD symbol on MDI to Rising edge of RGMII RX_CLK with
assertion of RX_CTRL
484
708
511
788
ns
ns
SSD symbol on MDI to first symbol of SGMII
25 MHz OSCILLATOR REQUIREMENTS
Frequency Tolerance
Rise / Fall Time (10%-90%)
-100
40
+100
8
ppm
ns
Jitter Tolerance (RMS)
25
ps
XI Duty Cycle in external clock mode
50 MHz OSCILLATOR REQUIREMENTS
Frequency
60
%
50
MHz
ppm
ns
Frequency Tolerance and Stability Over temperature and aging
Rise / Fall Time (10% - 90%)
100
4
–100
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7.6 Timing Requirements (continued)
TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
Duty Cycle
35
65
%
25 MHz CRYSTAL REQUIREMENTS
Frequency
25
MHz
ppm
Ω
Frequency Tolerance and Stability Over temperature and aging
100
100
–100
Equivalent Series Resistance
OUTPUT CLOCK TIMING (25 MHz)
Frequency (PPM)
Duty Cycle
-100
40
100
60
-
%
Rise Time
5000
5000
1000
ps
Fall Time
ps
Jitter (Short Term)
Frequency
ps
25
MHz
(1) For supplies with ramp rate longer than 8ms, a RESET pulse will be required after the last supply becomes stable.
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7.7 Timing Diagrams
tT1.1t
tT1.1t
Transmit
Clock
tT1.2t
tT1.3t
Transmit Data
and Control
Valid Data
Transmit
tT2.1t
tT2.1t
Receive
Clock
tT2.2t
Receive Data
and Control
Valid Data
Receive
图7-1. MII Timing
tT3.1t
Clock
tT3.2t
tT3.3t
Transmit
Data and
Control
Valid Data
tT3.4t
Receive
Data and
Control
Valid Data
图7-2. RMII Transmit and Receive Timing
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tTcyc
t
TX_CLK
Thold(shift)
TX_D[3:0]
Valid Data
Valid Data
Valid Data
Tsetup(shift)
TX_CTRL
TX_ER
TX_EN
TX_ER
TX_EN
图7-3. RGMII Transmit Timing (Internal Delay Enabled)
tTcyc
t
TX_CLK
TX_D[3:0]
TX_CTRL
Thold(align)
Valid Data
Valid Data
Valid Data
Tsetup(align)
TX_EN
TX_ER
TX_EN
TX_ER
图7-4. RGMII Transmit Timing (Internal Delay Disabled)
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tTcyc
t
RX_CLK
RX_D[3:0]
RX_CTRL
Tskew(shift)
Valid Data
Valid Data
Valid Data
Tskew(shift)
RX_DV
RX_ER
RX_DV
RX_ER
RX_DV
图7-5. RGMII Receive Timing (Internal Delay Enabled)
tTcyc
t
RX_CLK
RX_D[3:0]
RX_CTRL
Tskew(align)
Valid Data
Valid Data
RX_DV
RX_ER
RX_DV
图7-6. RGMII Receive Timing (Internal Delay Disabled)
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MDC
MDIO
MDIO
tT4.2t
tT4.3t
Valid Data
tT4.1t
Valid Data
图7-7. Serial Management Timing
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tT5.3t
XI(crystal)
tT5.4t
T5.1
XI(oscillator)
VDDA
T5.2
VDDIO/ Vsleep
RESET_N
MDC
tT5.5t
tT5.6t
Bootstrap
Latch-in
CLKOUT
tT5.7t
tT5.8t
+1
PAM3
0
(Master)
-1
图7-8. Power-Up Timing
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VVDD
XI
tT6.1t
Hardware
RESET_N
MDC
tT6.2t
Bootstrap
Latch-in
Active
I/O Pins
tT6.3t
tT6.4t
+1
PAM3
0
(Master)
-1
图7-9. Reset Timing
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VSLEEP
WAKE
INH
tT7.1t
tT7.2t
LOCAL WAKE
VSLEEP
+1
MDI
0
-1
tT7.3t
tT7.4t
INH
tT7.5t
WAKE
图7-10. WAKE Timing
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7.8 Typical Characteristics
VDDIO = 2.5 V
图7-11. LED pins VOL (2.5 V)
VDDIO = 2.5 V
图7-12. LED pins VOH (2.5 V)
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7.8 Typical Characteristics
VDDIO = 3.3 V
图7-13. LED pins VOL (3.3 V)
VDDIO = 3.3 V
图7-14. LED pins VOH (3.3 V)
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8 Detailed Description
8.1 Overview
The DP83TC813S-Q1 is a 100BASE-T1 automotive Ethernet Physical Layer transceiver. It is IEEE 802.3bw
compliant and AEC-Q100 qualified for automotive applications. The DP83TC813S-Q1 is interoperable with both
BroadR-Reach PHYs and 100BASE-T1 PHYs.
The DP83TC813S-Q1 also supports Open Alliance TC-10 low power mode for additional power savings. The
PHY supports WAKE and INH pins for implementing TC-10 functionality in the system.
This device is specifically designed to operate at 100-Mbps speed while meeting stringent automotive EMC
limits. The DP83TC813S-Q1 transmits PAM3 ternary symbols at 66.667 MHz over unshielded single twisted-pair
cable. It is application flexible; supporting MII, RMII, RGMII, and SGMII in a single 28-pin VQFN wettable flank
package.
There is an extensive Diagnostic Tool Kit within the DP83TC813S-Q1 for both in-system use as well as debug,
compliance and system prototyping for bring-up. The DP83TC813S-Q1 can meet IEC61000-4-2 Level 4
electrostatic discharge limits and it also includes an on-chip ESD sensor for detecting ESD events in real-time.
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8.2 Functional Block Diagram
MII / RGMII Option
SGMII Option
RMII Option
Serial
Management
MII / RMII / RGMII / SGMII Interface
TX
Data
RX
Data
TX_CLK
RX_CLK
MII
Registers
100BASE-T1
PCS - TX
100BASE-T1
PCS - RX
PHY Control
100BASE-T1
PMA - TX
100BASE-T1
PMA - RX
Transmit Block
Receive Block
BIST
TC-10
LED
Driver
Cable Diagnostics
Hybrid
TRD±
LEDs
图8-1. DP83TC813S-Q1
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8.3 Feature Description
备注
Refer to SNLA389 Application Note for more information about the register settings used for
compliance testing. It is necessary to use these register settings to achieve the same performance as
observed during compliance testing.
8.3.1 Diagnostic Tool Kit
The DP83TC813 diagnostic tool kit provides mechanisms for monitoring normal operation, device-level
debugging, system-level debugging, fault detection, and compliance testing. This tool kit includes a built-in self-
test with PRBS data, various loopback modes, Signal Quality Indicator (SQI), Time Domain Reflectometry
(TDR), undervoltage monitor, electrostatic discharge monitor, and IEEE 802.3bw test modes.
8.3.1.1 Signal Quality Indicator
When the DP83TC813S-Q1 is active, the Signal Quality Indicator may be used to determine the quality of link
based on SNR readings made by the device. SQI is presented as a 8-level indication. Signal quality indication is
accessible through register 0x871. SQI is continuously monitored by the PHY to allow for real-time link signal
quality status.
Bits[3:1] in register 0x871 provide SQI value while bits [7:5] provide the worst SQI value since the last read. The
SQI value reported in register 0x871[3:1] map directly to the SQI levels required by Open Alliance.
To get the most accurate SQI reporting, use the initialization routine explained in SNLA389 application note.
表8-1. Signal Quality Indicator
REG 0x871[3:1]
OPEN ALLIANCE SQI LEVEL
LINK QUALITY
Poor/ No Link
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0 (Worst)
1
2
3
4
Good / Excellent Link
5
6
7 (Best)
8.3.1.2 Electrostatic Discharge Sensing
Electrostatic discharge is a serious issue for electronic circuits and if not properly mitigated can create short-term
issues (signal integrity, link drops, packet loss) as well as long-term reliability faults. The DP83TC813 has robust
integrated ESD circuitry and offers an ESD sensing architecture. ESD events can be detected on MDI pins
independently for further analysis and debug.
Additionally, the DP83TC813 provides an interrupt status flag; Register 0x12[11] is set when an ESD event is
logged. This interrupt can be routed to the INT_N pin using bit[3] of the same register. Register 0x442[14:9] store
the number of ESD events that have occurred since power-up. Hardware and software resets are ignored by the
ESDS register to prevent unwarranted clearing.
8.3.1.3 Time Domain Reflectometry
Time domain reflectometry helps determine the quality of the cable, connectors and terminations in addition to
estimating OPEN and SHORT faults along a cable. The DP83TC813-Q1 transmits a test pulse down the
attached twisted-pair cable. Transmitted pulses continue down the cable and reflect from each imperfection and
fault, allowing the device to measure the time to return and strength (amplitude) of all reflections. This technique
enables the DP83TC813-Q1 to identify cable OPENs and SHORTs.
TDR is activated by setting bit[15] in register 0x1E. The procedure is as follows.
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• Configure the DP83TC813-Q1 as per the initilization settings from SNLA389 Application Note
• Ensure that the Link Partner connected to the PHY is slient. Link will be down during TDR execution.
• Run the Pre-TDR configuration settings as listed in SNLA389.
• Start TDR by setting register 0x1E[15] to '1'.
• Wait 100ms, read register 0x1E[1:0]
– If it reads 0b10 then TDR has executed successfully.
• If TDR executed successfully then read register 0x310 to get TDR results.
– 0x310[8]: 0 = Half Wire Open not detected or 1 = Half Wire Open detected
– 0x310[7]: 0 = Cable fault not detected or 1 = Cable fault detected
– 0x310[6]: 0 = Cable fault is OPEN or 1 = Cable fault is SHORT
– If valid cable fault is detected then 0x310[5:0] will store the location value in meters.
8.3.1.4 Voltage Sensing
The DP83TC813 offers sensors for monitoringvoltage at the supply pins. Undervoltage monitoring are always
active in the DP83TC813 by default. If an undervoltage condition is detected, interrupt status flag is set in
register 0x0013. These interrupts can also be optionally routed to the INT pin using the same register.
The following method must be used to read each sensor.
• Step 1: Program register 0x0467 = 0x6004 ; Initial configuration of monitors
• Step 2: Program register 0x046A = 0x00A3; Enable Monitors
• Step 3: Configure register 0x0468 with the corresponding setting to select the required sensor.
– VDDA Sensor: Use 0x0468 = 0x0920
– VSLEEP Sensor: Use 0x0468 = 0x1920
– VDDMAC Sensor: Use 0x0468 = 0x2920
– VDDIO Sensor: Use 0x0468 = 0x3920
• Step 4: Read register 0x047B[14:7] and convert this output code to decimal.
• Step 5: Use the output code in the following equations to get the sensor's absolute value. Refer to 表8-2
table for constant values for corresponding sensors.
– vdda_value = 3.3 + (vdda_output_code - vdda_output_mean_code)*slope_vdda_sensor
– vsleep_value = 3.3 + (vsleep_output_code - vsleep_output_mean_code)*slope_vsleep_sensor
– vddmac_value = 3.3 + (vddmac_output_code - vddmac_output_mean_code)*slope_vddmac_sensor
– vddio_value = 3.3 + (vddio_output_code - vddio_output_mean_code)*slope_vddio_sensor
表8-2. Sensors Constant Values
Sensor
Constant
Value
VDDA
VSLEEP
VDDMAC
VDDIO
vdda_output_mean_code
slope_vdda_sensor
126
0.0088
134
vsleep_output_mean_code
slope_vsleep_sensor
0.0088
205
vddmac_output_mean_code
slope_vddmac_sensor
vddio_output_mean_code
slope_vddio_sensor
0.016
205
0.016
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8.3.1.5 BIST and Loopback Modes
DP83TC813 incorporates a data-path’s Built-In-Self-Test (BIST) to check the PHY level and system level data-
paths. BIST has following integrated features which make the system level data transfer tests (through-put etc)
and diagnostics possible without relying on MAC or external data generator hardware/software.
The following features are available in the DP83TC813 which can be used for easy evaluation.
1. Loopback modes
2. Data Generator
a. Customizable MAC packets generator
b. Transmitted packet counter
c. PRBS stream generator
3. Data Checker
a. Received MAC packets error checker
b. Received packet counter: Counts total packets received and packets received with errors
c. PRBS lock and PRBS error checker
8.3.1.5.1 Data Generator and Checker
DP83TC813 supports inbuilt Pseudo-random data generator and checker which can be used in conjuction with
Loopback modes to check the data path. Data generator can be programmed to generate either user defined
MAC packets or PRBS stream.
Following
parameters
of
generated
MAC
packets
can
be
configured
(refer
to
registers<0x061B>,register<0x061A> and register<0x0624> for required configuration):
• Packet Length
• Inter-packet gap
• Defined number of packets to be sent or continuous transmission
• Packet data-type: Incremental/Fixed/PRBS
• Number of valid bytes per packet
8.3.1.5.2 xMII Loopback
Data
Generator
Data
Checker
MAC
图8-2. xMII Loopback Without Data Generator
xMII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications
between the MAC and the PHY. When in xMII Loopback, data transmitted from a connected MAC on the TX path
is internally looped back in the DP83TC813 to the RX pins where it can be checked by the MAC. There is no link
indication when in xMII loopback.
Enable Loopback
Write register 0x0000 = 0x6100
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Enable data generator/checker for MAC side
Data will be generated externally on the MAC TX pins.
Use the following register settings to enable checker depending on the MAC interface mode.
• For RGMII, write register 0x0619 = 0x1004
• For SGMII, write register 0x0619 = 0x1114
• For RMII, write register 0x0619 = 0x1224
• For MII, write register 0x0619 = 0x1334
Check incoming data from MAC side
Data can be verified at MAC interface RX pins.
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
Enable data generator/checker for Cable side
Not applicable as data will be generated externally on the MAC interface TX pins.
Check data for Cable side
Not applicable as PRBS stream checker works with only internal PRBS generator.
Other system requirements
Generated data will be going to cable side.
8.3.1.5.3 PCS Loopback
Data
Generator
Data
Checker
MAC
图8-3. PCS Loopback with data generator
Data
Generator
Data
Checker
MAC
图8-4. PCS Loopback without data generator
PCS Loopback will loop back data prior to it exiting the PCS and entering the PMA. Data received from the MAC
on the transmit path is brought through the digital block within the PHY where it is then routed back to the MAC
through the receive path. The DP83TC813 receive PMA circuitry is configured for isolation to prevent contention.
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Enable Loopback
Write register 0x0016 = 0x0102
Enable data generator/checker for MAC side
Write register 0x0619 = 0x1555
Write register 0x0624 = 0x55BF
Check incoming data from MAC side
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
Enable data generator/checker for Cable side
Write register 0x0619 = 0x0557
Write register 0x0624 = 0x55BF
Check data for Cable side
1. Write register 0x0620[1] = 1'b1
2. Read register 0x620
a. Bit [7:0] = Number of errors bytes received
b. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)
Repeat steps 1 and 2 to continously check error status of incoming data stream.
Other system requirements
Data generate by the internal PRBS will be transmitted over the MDI and the MAC interface.
8.3.1.5.4 Digital Loopback
Data
Generator
Data
Checker
MAC
图8-5. Digital loopback with data generator
Data
Generator
Data
Checker
MAC
图8-6. Digital loopback without data generator
Digital Loopback will loop back data prior to it exiting the Digital and entering the AFE. Data received from the
MAC on the transmit path is brought through the digital block within the PHY where it is then routed back to the
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MAC through the receive path. The DP83TC813 receive Analog circuitry is configured for isolation to prevent
contention.
Enable Loopback
Write register 0x0016 = 0x0104
Enable data generator/checker for MAC side
Write register 0x0619 = 0x1555
Write register 0x0624 = 0x55BF
Check incoming data from MAC side
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
Enable data generator/checker for Cable side
Write register 0x0619 = 0x0557
Write register 0x0624 = 0x55BF
Check data for Cable side
1. Write register 0x0620[1] = 1'b1
2. Read register 0x620
a. Bit [7:0] = Number of errors bytes received
b. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)
Repeat steps 1 and 2 to continously check error status of incoming data stream.
Other system requirements
Data generate by the internal PRBS will be transmitted over the MDI and the MAC interface.
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8.3.1.5.5 Analog Loopback
Data
Generator
Data
Checker
MAC
图8-7. Analog loopback with data generator
Data
Generator
Data
Checker
MAC
图8-8. Analog loopback without data generator
Analog Loopback uses the echoed signals from the unterminated MDI and decodes these signals in the Hybrid
to return the data to the MAC.
Enable Loopback
Write register 0x0016 = 0x0108
Enable data generator/checker for MAC side
Write register 0x0619 = 0x1555
Write register 0x0624 = 0x55BF
Check incoming data from MAC side
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
Enable data generator/checker for Cable side
Write register 0x0619 = 0x0557
Write register 0x0624 = 0x55BF
Check data for Cable side
1. Write register 0x0620[1] = 1'b1
2. Read register 0x620
a. Bit [7:0] = Number of errors bytes received
b. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)
Repeat steps 1 and 2 to continously check error status of incoming data stream.
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Other system requirements
Data generate by the internal PRBS will be transmitted over the MDI and the MAC interface.
8.3.1.5.6 Reverse Loopback
Data
Generator
Data
Checker
MAC
图8-9. Reverse Loopback With Data Generator
Data
Generator
Data
Checker
MAC
图8-10. Reverse Loopback Without Data Generator
Reverse Loopback receives data on the MDI and passes it through the entire receive block where it is then
looped back within the PCS layer to the transmit block. The data is transmitted back out on the MDI to the
attached Link Partner. To avoid contention, MAC transmit path is isolated.
Enable Loopback
Write register 0x0016 = 0x0110
Enable data generator/checker for MAC side
Use the following register settings to enable checker depending on the MAC interface mode.
• For RGMII, write register 0x0619 = 0x1004
• For SGMII, write register 0x0619 = 0x1114
• For RMII, write register 0x0619 = 0x1224
• For MII, write register 0x0619 = 0x1334
Write register 0x0624 = 0x55BF
Check incoming data from MAC side
Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E
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Enable data generator/checker for Cable side
Write register 0x0619 = 0x0557
Write register 0x0624 = 0x55BF
Check data for Cable side
1. Write register 0x0620[1] = 1'b1
2. Read register 0x620
a. Bit [7:0] = Number of errors bytes received
b. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)
Repeat steps 1 and 2 to continously check error status of incoming data stream.
Other system requirements
Data generate by the internal PRBS will be transmitted over the MDI and the MAC interface.
8.3.2 Compliance Test Modes
备注
Refer to SNLA389 Application Note for more information about the register settings used for
compliance testing. It is necessary to use these register settings to achieve the same performance as
observed during compliance testing.
There are four PMA compliance test modes required in IEEE 802.3bw, sub-clause 96.5.2, which are all
supported by the DP83TC813-Q1 . These compliance test modes include: transmitter waveform Power Spectral
Density (PSD) mask, amplitude, distortion, 100BASE-T1 Master jitter, 100BASE-T1 Slave jitter, droop,
transmitter frequency, frequency tolerance, return loss, and mode conversion.
TX_TCLK can be routed to CLKOUT/LED_1 pin for 100BASE-T1 Slave Jitter measurement. This can be
enabled via register 0x45F. The device must be configured in Slave mode.
8.3.2.1 Test Mode 1
Test mode 1 evaluates transmitter droop. In test mode 1, the DP83TC813-Q1 transmits ‘+1’ symbols for a
minimum of 600 ns followed by ‘–1’ symbols for a minimum of 600 ns. This pattern is repeated continuously
until the test mode is disabled.
Test mode 1 is enabled by setting bits[15:13] = 0b001 in the MMD1_PMA_TEST_MODE_CTRL Register
(0x1836).
8.3.2.2 Test Mode 2
Test mode 2 evaluates the transmitter 100BASE-T1 Master mode jitter. In test mode 2, the DP83TC813-Q1
transmits a {+1,-1} data symbol sequence. The transmitter synchronizes the transmitted symbols from the local
reference clock.
Test mode 2 is enabled by setting bits[15:13] = 0b010 in MMD1_PMA_TEST_MODE_CTRL Register (0x1836).
8.3.2.3 Test Mode 4
Test mode 4 evaluates the transmitter distortion. In test mode 4, the DP83TC813-Q1 transmits the sequence of
symbols generated by 方程式1:
g(x) = 1 + x9 + x11
(1)
The bit sequences, x0n and x1n, are generated from combinations of the scrambler in accordance to 方程式 2
and 方程式3:
'x0n = Scrn[0]
(2)
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x1n = Scrn[1] ^ Scrn[4]
(3)
Example streams of the 3-bit nibbles are shown in 表8-3.
表8-3. Transmitter Test Mode 4 Symbol Mapping
x1n
x0n
PAM3 SYMBOL
0
0
0
+1
0
0
1
1
0
1
1
–1
Test mode 4 is enabled by setting bits[15:13] = 0b100 in MMD1_PMA_TEST_MODE_CTRL Register (0x1836).
8.3.2.4 Test Mode 5
Test mode 5 evaluates the transmitter PSD mask. In test mode 5, the DP83TC813-Q1 transmits a pseudo-
random sequence of PAM3 symbols.
Test mode 5 is enabled by setting bits[15:13] = 0b101 in MMD1_PMA_TEST_MODE_CTRL Register (0x1836).
8.4 Device Functional Modes
Stnd_by=1
From any state
Stnd_by=1
RESET = LOW
TC10_en=1 & LPS_rcvd =1
((normal_cmd=1 | | (Auto = 1
& Slp_slnt = 0)) & Stnd_by = 0)
RESET
Stand-by
Normal
Sleep Ack
TC10_SBY=1/0?
TC10_Abrt=1
TC10_en & Sleep_req &
Tx_Send_n = 1
POR incomplete
Sleep_ack_ mer_done ||
Sleep_req
Power Up
Local_Wk ||
WUP
Power
Up
Sleep
Sleep Fail
TC10_SBY = 1 &
MDI_egy_rcv = 0
TC10_SBY=0 &
MDI_egy_rcv = 0
Slp_req_tmr=1
Slp_req_tmr=1
Sleep
Request
Sleep Silent
Tx_LPS_done = 1
&& LPS_rcvd = 1
图8-11. PHY Operation State Diagram
8.4.1 Power Down
When any of the supply rails are below the POR threshold (~0.6V), the PHY is in a power-down state. All digital
IOs will remain in high impedance states and analog blocks are disabled. PMA termination is not present when
powered down.
8.4.2 Reset
Reset is activated upon power-up, when RESET is pulled LOW (for the minimum reset pulse time) or if hardware
reset is initiated by setting bit[15] in register 0x1F. All digital circuitry is cleared along with register settings during
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reset. Once reset completes, device bootstraps are re-sampled and associated bootstrap registers are set
accordingly. PMA termination is not present in reset.
8.4.3 Standby
The device (100BASE-T1 Master mode only) automatically enters into standby post power-up and reset so long
that all supplies including VSLEEP are available and the device is bootstrapped for managed operation.
In standby, all PHY functions are operational except for PCS and PMA blocks. The PMA termination is also not
present. Link establishment is not possible in standby and data cannot be transmitted or received. SMI functions
are operational and register configurations are maintained.
If the device is configured for autonomous operation through bootstrap setting, the PHY automatically switches
to normal operation once POR is complete.
8.4.4 Normal
Normal mode can be entered from either autonomous or managed operation. When in autonomous operation,
the PHY will automatically try to establish a link with a valid Link Partner once POR is complete.
In managed operation, SMI access is required to allow the device to exit standby (100BASE-T1 Master mode
only); commands issued through the SMI allow the device to exit standby and enables both the PCS and PMA
blocks. All device features are operational in normal mode.
Autonomous operation can be enabled through SMI access by setting bit[6] in the register 0x18B.
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8.4.5 Sleep Ack
When the PHY receives low power sleep requests from the link partner, it enter Sleep Ack mode. In this mode,
the PHY allows 8ms for the MAC to decide if TC-10 sleep mode must be enabled or not. If the MAC decides to
allow TC-10, the PHY proceeds to the next step in TC-10 state machine. However, the MAC can decide to abort
TC-10 and the PHY returns to Normal mode. TC10 can be aborted via register setting by disabling TC10 or via
GPIO. If TC10 is aborted by disabling TC10 feature, then it is recommended to re-enable TC10 feature once the
sleep request has been aborted.
8.4.6 Sleep Request
Sleep request is entered when switching from normal mode to sleep mode. This is an intermediate state and is
used to for a smooth transition into sleep mode. In sleep request mode, the PHY transmits LPS code-groups,
informing the Link Partner that sleep is requested.
PHY sleep_rqst_timer (default = 16ms) begins once the PHY enters into sleep request mode. LPS decoding at
the Link Partner will trigger the LPS RECEIVED interrupt. In sleep request state device waits for Link Partner to
send LPS symbols. Once LPS symbols are received by the device, it transitions to SLEEP_SILENT state. If the
sleep_rqst_timer expires before device receives LPS codes, the device enters SLEEP FAIL state. .
8.4.7 Sleep Fail
The PHY enters sleep fail mode if the Sleep_rqst_timer expires when in sleep_request state or sleep_silent
state.. This indicates that the link partner has not entered sleep mode. After entering sleep fail mode, the PHY
transitions to Normal mode.
8.4.8 Sleep
If sleep enable is set, the PHY transitions to sleep mode after the MDI line goes silent when in sleep_silent state;
however, if sleep enable is not set, the device transitions to standby after the MDI line goes silent. By default,
sleep enable is set. Once in sleep mode, all PHY blocks are disabled except for energy detection on the MDI. All
register configurations are lost in sleep mode. No link can be established, data cannot be transmitted or received
and SMI access is not available when in sleep mode.
备注
When the PHY is in Sleep mode, the MAC interface must not be driven by the Ethernet MAC.
8.4.9 Wake-Up
The user can wake up the DP83TC813S-Q1 remotely through energy detection on the MDI or locally using the
WAKE pin. For local wake, the WAKE pin must be pulled HIGH. If the WAKE pin is tied LOW, the PHY will only
exit sleep if energy is detected on the MDI.
8.4.10 TC10 System Example
The following block diagrams explains how TC10 sleep and wake function works in a system.
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VREG
CORE
VBAT
EN
PMIC
(3.3V)
VDDA
VDDIO
VSLEEP
VREG
SLEEP
EN
10k
VDDMAC
GND
INH
(3.3V)
MAC
Voltage
MDI
DP83TC81XX-Q1
100BASE-T1
Ethernet PHY
CPU/MPU
MAC
WAKE
(3.3V)
Remote wake
over MDI
10k
GND
图8-12. TC10 System Example - Remote Wake
VREG
CORE
VBAT
EN
PMIC
(3.3V)
VDDA
VSLEEP
VREG
SLEEP
EN
VDDIO
10k
VDDMAC
GND
INH
(3.3V)
MDI
DP83TC81XX-Q1
100BASE-T1
Ethernet PHY
CPU/MPU
MAC
WAKE
(3.3V)
10k
GND
Local wake
through WAKE
pin
图8-13. TC10 System Example - Local Wake
Remote Wake Up
For remote wake up, the initial state of the system is TC10 sleep. Core voltages to the PHY and MAC are turned
off but the VSLEEP of the PHY is present. At some time, wake-up pulses (WUP) are received on the MDI lines.
The PHY recevies the message and if its a valid sequence then the PHY wakes up and drives INH pin HIGH.
INH pin is used as enable input to voltage regulator (e.g. LDO). Voltage regulators turns on and supplies power
to a power management device. The power management device then supplies power to the PHY, MAC, and any
other devices on the system. The whole system powers up and becomes operational.
Wake Forwarding
DP83TC813-Q1
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support wake forwarding feature. When the device received Wake-Up Requests (WUR) or Wake-Up Pulses
(MDI) on the MDI then the PHY will transmit an 40µs high pulse on the WAKE pin. This can be used to wake-up
any other PHYs on the system that are in TC-10 sleep.
Local Wake Up
For local wake, it is assumed that some portion of the system is already active and the PHY is in TC10 sleep. As
a example, the system might have micro-controller in active mode to control the WAKE pin of the PHY. When the
MCU wants to wake up the PHY from TC10 sleep, it raises the WAKE pin to 3.3V to send a wake pulse (min.
40μs). The PHY wakes up and drives INH pin HIGH. INH pin is used as enable input to voltage regulator (e.g.
LDO). Voltage regulators turns on and supplies power to a power management device. The power management
device then supplies power to the PHY. Any other device on the system that depends on the PHY wake up can
now be powered up and the system becomes operational.
Local Sleep
When the PHY is in normal operational mode and the MAC needs to put it in TC10 sleep, it initiates the TC10
sleep process via SMI on the PHY. DP83TC813-Q1 then sends LPS signals on MDI to the link partner. If the link
partner also agrees to enter TC10 sleep, the host PHY enters TC10 sleep. It then releases the INH pin and it
gets pulled low through the external pull down resistor. Voltage regulator that uses INH pin as enable input will
be turned off. PHY, MAC, and any other devices that are dependent on the voltage regulator will be turned off.
The PHY will still have VSLEEP voltage present and continue to stay in TC10 sleep.
8.4.11 Media Dependent Interface
8.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
100BASE-T1 Master and 100BASE-T1 Slave are configured using either hardware bootstraps or through
register access.
RX_D3 controls the 100BASE-T1 Master and 100BASE-T1 Slave bootstrap configuration. By default, 100BASE-
T1 Slave mode is configured because there is an internal pulldown resistor on LED_0 pin. If 100BASE-T1
Master mode configuration through hardware bootstrap is preferred, an external pullup resistor is required.
Additionally, bit[14] in the MMD1_PMA_CTRL_2 Register (Address 0x1834) controls the 100BASE-T1 Master
and 100BASE-T1 Slave configuration. When this bit is set, 100BASE-T1 Master mode is enabled.
8.4.11.2 Auto-Polarity Detection and Correction
During the link training process, the DP83TC813-Q1 100BASE-T1 Slave device is able to detect polarity reversal
and automatically corrects the error. If polarity reversal is detected, the 100BASE-T1 Slave will invert its own
transmitted signals to account for the error and ensure compatibility with the 100BASE-T1 Master. Polarity at the
100BASE-T1 Master is always observed as correct because polarity detection and correction is handled entirely
by the 100BASE-T1 Slave.
Auto-polarity correction may be disabled in cases where it is not required. Disabling of auto-polarity correction is
achieved via register 0x0553.
8.4.11.3 Jabber Detection
The jabber function prevents the PCS Receive state machine from locking up into a DATA state if the End-of-
Stream Delimiters, ESD1 and ESD2, are never detected or received within the rcv_max_timer. When the
maximum receive DATA state timer expires, the PCS Receive state machine is reset and transitions into IDLE
state. IEEE 802.3bw specifies that jabber timeout be set to 1.08 ms ± 54 μs. By default, jabber timeout in the
DP83TC813 is set to 1.1 ms. This timer is configurable in Register 0x496[10:0].
8.4.11.4 Interleave Detection
The interleave function allows for the DP83TC813-Q1 to detect and de-interleave the serial stream from a
connected link partner. The two possible interleave sequences of ternary symbols include: (TAn, TBn) or (TBn,
TAn).
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8.4.12 MAC Interfaces
8.4.12.1 Media Independent Interface
The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY
to the MAC. The MII is fully compliant with IEEE 802.3-2015 clause 22. The PHY has internal series termination
resistors on MII output pins including TX_CLK output when the PHY is operating in MII mode. In this mode, it is
recommended to not leave the MII-TX pins floating or High-Z.
The MII signals are summarized in 表8-4:
表8-4. MII Signals
FUNCTION
PINS
TX_D[3:0]
Data Signals
RX_D[3:0]
TX_EN, TX_ER
RX_DV, RX_ER
TX_CLK
Control Signals
Clock Signals
RX_CLK
TX_CLK
TX_ER
TX_EN
TX_D[3:0]
RX_CLK
RX_DV
PHY
MAC
RX_ER
RX_D[3:0]
图8-14. MII Signaling
表8-5. MII Transmit Encoding
TX_D[3:0]
TX_EN
TX_ER
DESCRIPTION
0
0
1
1
0
1
0
1
0000 through 1111
Normal Inter-Frame
Reserved
0000 through 1111
0000 through 1111
Normal Data Transmission
Transmit Error Propagation
0000 through 1111
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表8-6. MII Receive Encoding
RX_DV
RX_ER
RX_D[3:0]
0000 through 1111
0000
DESCRIPTION
Normal Inter-Frame
Normal Inter-Frame
Reserved
0
0
0
0
0
1
1
0
1
1
1
1
0
1
0001 through 1101
1110
False Carrier Indication
Reserved
1111
0000 through 1111
0000 through 1111
Normal Data Reception
Data Reception with Errors
8.4.12.2 Reduced Media Independent Interface
The DP83TC813-Q1 incorporates the Reduced Media Independent Interface (RMII) as defined in the RMII
Revision 1.2 and 1.0 from the RMII consortium. The purpose of this interface is to provide a reduced pin count
alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an
additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.
The DP83TC813-Q1 offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave Mode, the
DP83TC813-Q1 operates off a 50-MHz CMOS-level oscillator, which is either provided by the MAC or
synchronous to the MAC's reference clock. In RMII Master operation, the DP83TC813-Q1 operates off of either
a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins.
When bootstrapping to RMII Master Mode, a 50-MHz output clock will automatically be enabled on RX_D3. This
50-MHz output clock must be routed to the MAC.
The RMII specification has the following characteristics:
• Single clock reference shared between MAC and PHY
• Provides independent 2-bit wide transmit and receive data paths
In this mode, data transfers are two bits for every clock cycle using the 50-MHz reference clock for both transmit
and receive paths.
The RMII signals are summarized in 表8-7:
表8-7. RMII Signals
FUNCTION
PINS
TX_D[1:0]
RX_D[1:0]
TX_EN
Data Signals
Control Signals
CRS_DV
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TX_EN
TX_D[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER (optional)
RX_D[1:0]
PHY
MAC
CRS_DV
图8-15. RMII Signaling
表8-8. RMII Transmit Encoding
TX_D[1:0]
TX_EN
DESCRIPTION
Normal Inter-Frame
0
1
00 through 11
00 through 11
Normal Data Transmission
表8-9. RMII Receive Encoding
CRS_DV
RX_ER
RX_D[1:0]
00 through 11
00
DESCRIPTION
0
0
0
1
1
0
1
1
0
1
Normal Inter-Frame
Normal Inter-Frame
Reserved
01 through 11
00 through 11
00 through 11
Normal Data Reception
Data Reception with Errors
RMII Slave: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock at
the XI pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the XI pin.
RMII Master: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock
at the RX_D3 pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the RX_D3
pin.
The DP83TC813-Q1 RMII supplies an RX_DV signal, which provides a simpler method to recover receive data
without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though it is
not required by the RMII specification.
RMII includes a programmable FIFO to adjust for the frequency differences between the reference clock and the
recovered clock. The programmable FIFO, located in the register 0x0011[9:8] and register 0x0648[9:7],
minimizes internal propagation delay based on expected maximum packet size and clock accuracy.
8.4.12.3 Reduced Gigabit Media Independent Interface
The DP83TC813-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by
RGMII version 2.0 with LVCMOS. RGMII is designed to reduce the number of pins required to connect MAC and
PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are
used to sample the control signal pin on transmit and receive paths. Data is samples on just the rising edge of
the clock. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25 MHz.
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The RGMII signals are summarized in 表8-10:
表8-10. RGMII Signals
FUNCTION
PINS
TX_D[3:0]
RX_D[3:0]
TX_CTRL
RX_CTRL
TX_CLK
Data Signals
Control Signals
Clock Signals
RX_CLK
TX_CLK
TX_CTRL
TX_D[3:0]
RX_CLK
PHY
MAC
RX_CTRL
RX_D[3:0]
25-MHz Crystal or
CMOS-level
Oscillator
图8-16. RGMII Connections
表8-11. RGMII Transmit Encoding
TX_CTRL
(POSITIVE EDGE)
TX_CTRL
(NEGATIVE EDGE)
TX_D[3:0]
DESCRIPTION
0
0
1
1
0
1
0
1
0000 through 1111
0000 through 1111
0000 through 1111
0000 through 1111
Normal Inter-Frame
Reserved
Normal Data Transmission
Transmit Error Propagation
表8-12. RGMII Receive Encoding
RX_CTRL
(POSITIVE EDGE)
RX_CTRL
(NEGATIVE EDGE)
RX_D[3:0]
DESCRIPTION
0
0
0
0
1
1
0
1
1
1
0
1
0000 through 1111
0000 through 1101
1110
Normal Inter-Frame
Reserved
False Carrier Indication
Reserved
1111
0000 through 1111
0000 through 1111
Normal Data Reception
Data Reception with Errors
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the
transition from the internal free running clock to a recovered clock (data synchronous). Data may be duplicated
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on the falling edge of the clock because double data rate (DDR) is only required for 1-Gbps operation, which is
not supported by the DP83TC813-Q1.
The DP83TC813-Q1 supports in-band status indication to help simplify link status detection. Inter-frame signals
on RX_D[3:0] pins as specified in 表8-13.
表8-13. RGMII In-Band Status
RX_CTRL
RX_D3
RX_D[2:1]
RX_D0
RX_CLK Clock Speed:
00 = 2.5 MHz
00
Note:
Duplex Status:
0 = Half-Duplex
1 = Full-Duplex
Link Status:
0 = Link not established
1 = Valid link established
01 = 25 MHz
10 = 125 MHz
11 = Reserved
In-band status is only valid when
RX_CTRL is low
8.4.12.4 Serial Gigabit Media Independent Interface
The Serial Gigabit Media Independent Interface (SGMII) provides a means for data transfer between MAC and
PHY with significantly less signal pins (4 pins) compared to MII (14 pins), RMII (7 pins) or RGMII (12 pins).
SGMII uses low-voltage differential signaling (LVDS) to reduce emissions and improve signal quality.
The DP83TC813 SGMII is capable of operating in 4-wire. SGMII is configurable through hardware bootstraps. In
4-wire operation, two differential pairs are used to transmit and receive data. Clock and data recovery are
performed in the MAC and in the PHY.
Because the DP83TC813 operates at 100-Mbps, the 1.25-Gbps rate of the SGMII is excessive. The SGMII
specification allows for 100-Mbps operation by replicating each byte within a frame 10 times. Frame elongation
takes place above the IEEE 802.3 PCS layer, which prevents the start-of-frame delimiter from appearing more
than once.
Because the DP83TC813 only supports 100-Mbps speed, SGMII Auto-Negotitation can be disabled by setting
bit[0] = 0b0 in the Register 0x608.
The SGMII signals are summarized in 表8-14.
表8-14. SGMII Signals
FUNCTION
PINS
TX_M, TX_P
RX_M, RX_P
Data Signals
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TX_M
TX_P
RX_M
RX_P
0.1
0.1
0.1
0.1
F
F
F
F
MAC
PHY
25-MHz Crystal or
CMOS-level
Oscillator
图8-17. SGMII Connections
8.4.13 Serial Management Interface
The Serial Management Interface (SMI) provides access to the DP83TC813S-Q1 internal register space for
status information and configuration. The SMI frames and base registers are compatible with IEEE 802.3 clause
22. The implemented register set consists of the registers required by the IEEE 802.3 plus several others to
provide additional visibility and controllability of the DP83TC813S-Q1 . Additionally, the DP83TC813S-Q1
includes control and status registers added to clause 45 as defined by IEEE 802.3bw. Access to clause 45
register field is achieved using clause 22 access.
The SMI includes the management clock (MDC) and the management input and output data pin (MDIO). MDC is
sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of
24 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when
the bus is idle.
MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the
rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ), which pulls MDIO high during IDLE and
turnaround.
Up to 9 DP83TC813S-Q1 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit
address is used. During power-up-reset, the DP83TC813S-Q1 latches the PHYAD[3:0] configuration pins to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up-reset. To maintain
valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In
normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field,
thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific).
The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern
makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit
time inserted between the Register Address field and the Data field. To avoid contention during a read
transaction, no device may actively drive the MDIO signal during the first bit of turnaround. The addressed
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DP83TC813S-Q1 drives the MDIO with a zero for the second bit of turnaround and follows this with the required
data.
For write transactions, the station-management entity writes data to the addressed DP83TC813S-Q1 , thus
eliminating the requirement for MDIO Turnaround. The turnaround time is filled by the management entity by
inserting <10>.
表8-15. SMI Protocol Structure
SMI PROTOCOL
Read Operation
Write Operation
<idle> <start> <op code> <device address> <reg address> <turnaround> <data> <idle>
<idle><01><10><AAAAA><RRRRR><Z0><XXXX XXXX XXXX XXXX><idle>
<idle><01><01><AAAAA><RRRRR><10><XXXX XXXX XXXX XXXX><idle>
8.4.14 Direct Register Access
Direct register access can be used for the first 31 registers (0x0 through 0x1F).
8.4.15 Extended Register Space Access
The DP83TC813S-Q1 SMI function supports read and write access to the extended register set using registers
REGCR (0xD) and ADDAR (0xE) and the MDIO Manageable Device (MMD) indirect method defined in IEEE
802.3ah Draft for Clause 22 for accessing the Clause 45 extended register set.
REGCR (0xD) is the MDIO Manageable MMD access control. In general, register REGCR[4:0] is the device
address DEVAD that directs any accesses of ADDAR (0xE) register to the appropriate MMD.
The DP83TC813S-Q1 supports 3 MMD device addresses:
1. DEVAD[4:0] = 11111 is used for general MMD register accesses for IEEE defined registers as well as vendor
defined registers.
2. DEVAD[4:0] = 00001 is used for 100BASE-T1 PMA MMD register accesses. Register names for registers
accessible at this device address are preceded by MMD1.
3. DEVAD[4:0] = 00011 is used for vendor specific registers. This registers space is called MMD3.
All accesses through register REGCR and ADDAR must use the correct DEVAD. Transactions with other
DEVADs are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),
data with post increment on read and writes (10) and data with post increment on writes only (11).
• ADDAR is the address and data MMD register. ADDAR is used in conjunction with REGCR to provide the
access to the extended register set. If register REGCR[15:14] is (00), then ADDAR holds the address of the
extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its
address register. When REGCR[15:14] is set to (00), accesses to register ADDAR modify the extended
register set address register. This address register must always be initialized to access any of the registers
within the extended register set.
• When REGCR[15:14] is set to (01), accesses to register ADDAR access the register within the extended
register set selected by the value in the address register.
• When REGCR[15:14] is set to (10), access to register ADDAR access the register within the extended
register set selected by the value in the address register. After that access is complete, for both reads and
writes, the value in the address register is incremented.
• When REGCR[15:14] is set to (11), access to register ADDAR access the register within the extended
register set selected by the value in the address register. After that access is complete, for write access only,
the value in the address register is incremented. For read accesses, the value of the address register
remains unchanged.
The following sections describe how to perform operations on the extended register set using register REGCR
and ADDAR.
8.4.16 Write Address Operation
To set the address register:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Write the register address to register ADDAR.
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Subsequent writes to register ADDAR (step 2) continue to write the address register.
8.4.16.1 MMD1 - Write Address Operation
For writing register addresses within MMD1 field:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Write the register address to register ADDAR.
8.4.17 Read Address Operation
To read the address register:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Read the register address from register ADDAR.
Subsequent reads to register ADDAR (step 2) continue to read the address register.
8.4.17.1 MMD1 - Read Address Operation
For reading register addresses within MMD1 field:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Read the register address from register ADDAR.
8.4.18 Write Operation (No Post Increment)
To write a register in the extended register set:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = '11111') to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the
address register.
备注
Steps (1) and (2) can be skipped if the address register was previously configured.
8.4.18.1 MMD1 - Write Operation (No Post Increment)
To write a register in the MMD1 extended register set:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x4001 (data, no post increment function field = 01, DEVAD = '00001') to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
8.4.19 Read Operation (No Post Increment)
To read a register in the extended register set:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = '11111') to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
Subsequent reads to register ADDAR (step 4) continue to reading the register selected by the value in the
address register.
备注
Steps (1) and (2) can be skipped if the address register was previously configured.
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8.4.19.1 MMD1 - Read Operation (No Post Increment)
To read a register in the MMD1 extended register set:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x4001 (data, no post increment function field = 01, DEVAD = '00001') to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
8.4.20 Write Operation (Post Increment)
To write a register in the extended register set with post increment:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x801F (data, post increment function field = 10, DEVAD = '11111') or the value 0xC01F
(data, post increment on writes function field = 11, DEVAD = '11111') to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the
value of the address register; the address register is incremented after each access.
8.4.20.1 MMD1 - Write Operation (Post Increment)
To write a register in the MMD1 extended register set with post increment:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x8001 (data, post increment function field = 10, DEVAD = '00001') or the value 0xC001
(data, post increment on writes function field = 11, DEVAD = '00001') to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
8.4.21 Read Operation (Post Increment)
To read a register in the extended register set and automatically increment the address register to the next
higher value following the write operation:
1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x801F (data, post increment function field = 10, DEVAD = '11111') to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the
value of the address register; the address register is incremented after each access.
8.4.21.1 MMD1 - Read Operation (Post Increment)
To read a register in the MMD1 extended register set and automatically increment the address register to the
next higher value following the write operation:
1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x8001 (data, post increment function field = 10, DEVAD = '00001') to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
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8.5 Programming
8.5.1 Strap Configuration
The DP83TC813S-Q1 uses functional pins as strap options to place the device into specific modes of operation.
The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register
access). Some strap pins support 3 levels and some strap pins support 2 levels, which are described in greater
detail below. PHY address straps, RX_DV/RX_CTRL and RX_ER, are 3-level straps while all other straps are
two levels. Configuration of the device may be done through strapping or through serial management interface.
备注
Because strap pins are functional pins after reset is deasserted, they must not be connected directly
to VDDIO or VDDMAC or GND. Either pullup resistors, pulldown resistors, or both are required for
proper operation.
备注
When using VDDMAC and VDDIO separately, it is important to connect strap resistors to the correct
voltage rail. Each pin's voltage domain is listed in the 表8-18 table below.
VDDMAC
or
VDDIO
RH
Rpulldn
RL
图8-18. Strap Circuit
Rpulldn value is included in the Electrical Characteristics table of the data sheet.
表8-16. Recommended 3-Level Strap Resistor Ratios for PHY Address
IDEAL RH (kΩ) (VDDIO =
MODE3
IDEAL RH (kΩ) (VDDIO = 3.3V)1
IDEAL RH (kΩ) (VDDIO = 2.5V)2
1.8V)1
1
2
3
OPEN
13
OPEN
12
OPEN
4
4.5
2
0.8
1. Strap resistors with 10% tolerance.
2. Strap resistors with 1% tolerance.
3. RL is optional and can be added if voltage on bootstrap pins needs to be adjusted.
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表8-17. Recommended 2-Level Strap Resistors
IDEAL RH (kΩ) 1, 2
MODE
1
2
OPEN
2.49
1. Strap resistors with up to 10% tolerance can be used.
2. To gain more margin in customer application for 1.8V VDDIO, either 2.1 kΩ +/-10% pull-up can be used or
resistor accuracy of 2.49 kΩ resistor can be limited to 1%.
The following table describes the PHY configuration bootstraps:
表8-18. Bootstraps
PIN
NAME
DEFAULT
MODE
PIN NO.
DOMAIN
STRAP FUNCTION
DESCRIPTION
MODE
PHY_AD[0]
PHY_AD[2]
1
0
0
RX_DV/
RX_CTRL
13
VDDMAC
1
PHY_AD: PHY Address ID
2
0
1
3
1
1
MODE
PHY_AD[1]
PHY_AD[3]
1
0
0
1
1
RX_ER
21
28
VDDMAC
VDDMAC
1
1
PHY_AD: PHY Address ID
AUTO: Autonomous Disable.
2
0
3
1
RX_CLK
MODE
AUTO
1
0
2
1
MODE
MAC[0]
RX_D0
RX_D1
RX_D2
RX_D3
27
26
25
24
VDDMAC
VDDMAC
VDDMAC
VDDMAC
1
1
1
1
1
0
MAC: MAC Interface Selection
MAC: MAC Interface Selection
MAC: MAC Interface Selection
2
1
MODE
MAC[1]
1
0
2
1
MODE
MAC[2]
1
0
1
2
MODE
MS
0
MS: 100BASE-T1 Master and 100BASE-
T1 Slave Selection
1
2
1
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备注
Refer to SNLA389 Application Note for more information about the register settings used for
compliance testing. It is necessary to use these register settings to achieve the same performance as
observed during compliance testing. Managed mode strap option is recommended to prevent the link
up process from initiating while the software configuration from SNLA389 is being executed. Once the
software configuration is completed, the PHY can be removed from Managed mode by setting bit
0x018B[6] to ‘0’
表8-19. 100BASE-T1 Master and 100BASE-T1 Slave Selection Bootstrap
MS
DESCRIPTION
0
100BASE-T1 Slave Configuration
100BASE-T1 Master Configuration
1
表8-20. Autonomous Mode Bootstrap
AUTO
DESCRIPTION
0
1
Autonomous Mode, PHY able to establish link after power-up
Managed Mode, PHY must be allowed to establish link after power-up based on register write
表8-21. MAC Interface Selection Bootstraps
MAC[2]
MAC[1]
MAC[0]
DESCRIPTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SGMII (4-wire)(1)
MII
RMII Slave
RMII Master
RGMII (Align Mode)
RGMII (TX Internal Delay Mode)
RGMII (TX and RX Internal Delay Mode)
RGMII (RX Internal Delay Mode)
(1) SGMII strap mode is only available on 'S' type device variant. For 'R' type device variant, this strap mode is RESERVED
表8-22. PHY Address Bootstraps
PHY_AD[3:0]
0000
0001
0010
0011
RX_CTRL STRAP MODE
RX_ER STRAP MODE
DESCRIPTION 节8.5.1
1
-
1
-
PHY Address: 0b00000 (0x0)
NA
-
-
NA
-
-
NA
0100
0101
0110
2
3
-
1
1
-
PHY Address: 0b00100 (0x4)
PHY Address: 0b00101 (0x5)
NA
0111
-
-
NA
1000
1001
1010
1011
1
-
2
-
PHY Address: 0b01000 (0x8)
NA
1
-
3
-
PHY Address: 0b01010 (0xA)
NA
1100
2
3
2
3
2
2
3
3
PHY Address: 0b01010 (0xC)
PHY Address: 0b01011 (0xD)
PHY Address: 0b01110 (0xE)
PHY Address: 0b01111 (0xF)
1101
1110
1111
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8.5.2 LED Configuration
The DP83TC813S-Q1 supports 1 configurable LED pin (LED_1) which also doubles up as a clock output pin
(CLKOUT). Several functions can be multiplexed onto the LEDs for different modes of operation. LED operations
are selected using registers 0x0450.
Because the LED output pins are also used as strap pins, external components required for strapping and the
user must consider the LED usage to avoid contention. Specifically, when the LED outputs are used to drive
LEDs directly, the active state of each output driver is dependent on the logic level sampled by the
corresponding input upon power up or hardware reset.
图8-19 shows the two proper ways of connecting LEDs directly to the DP83TC813S-Q1 .
Pull-Down
VDDIO
Strap Pin
RCL
D1
RP
RP
D1
RCL
Pull-Up
Strap Pin
图8-19. Example Strap Connections
8.5.3 PHY Address Configuration
The DP83TC813S-Q1 can be set to respond to any of 9 possible PHY addresses through bootstrap pins. The
PHY address is latched into the device upon power-up or hardware reset. Each PHY on the serial management
bus in the system must have a unique PHY address.
By default, DP83TC813S-Q1 will latch to a PHY address of 0 (<0b00000>). This address can be changed by
adding pullup resistors to bootstrap pins found in 节8.5.3.
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8.6 Register Maps
8.6.1 Register Access Summary
There are two different methods for accessing registers within the field. Direct register access method is only
allowed for the first 31 registers (0x0 through 0x1F). Registers beyond 0x1F must be accessed by use of the
Indirect Method (Extended Register Space) described in 节8.4.15.
表8-23. MMD Register Space Division
MMD REGISTER SPACE
REGISTER ADDRESS RANGE
MMD1F
MMD1
MMD3
0x0000 - 0x0EFD
0x1000 - 0x1836
0x3000 - 0x3001
备注
For MMD1 and MMD3, the most significant nibble of the register address is used to denote the
respective MMD space. This nibble must be ignored during actual register access operation. For
example, to access register 0x1836, use 0x1 as the MMD indicator and 0x0836 as the register
address.
表8-24. Register Access Summary
REGISTER FIELD
REGISTER ACCESS METHODS
Direct Access
Indirect Access, MMD1F = '11111'
Example: to read register 0x17 in MMD1F field with no post increment
Step 1) write 0x1F to register 0xD
0x0 through 0x1F
Step 2) write 0x17 to register 0xE
Step 3) write 0x401F to register 0xD
Step 4) read register 0xE
Indirect Access, MMD1F = '11111'
Example: to read register 0x462 in MMD1F field with no post increment
Step 1) write 0x1F to register 0xD
Step 2) write 0x462 to register 0xE
MMD1F Field
0x20 - 0xFFF
Step 3) write 0x401F to register 0xD
Step 4) read register 0xE
Indirect Access, MMD1 = '00001'
Example: to read register 0x7 in MMD1 field (register 0x1007) with no post increment
Step 1) write 0x1 to register 0xD
Step 2) write 0x7 to register 0xE
MMD1 Field
0x0 - 0xFFF
Step 3) write 0x4001 to register 0xD
Step 4) read register 0xE
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8.6.2 DP83TC813 Registers
表 8-25 lists the memory-mapped registers for the DP83TC813 registers. All register offset addresses not listed
in 表8-25 must be considered as reserved locations and the register contents must not be modified.
表8-25. DP83TC813 Registers
Address Acronym
Register Name
Section
0h
BMCR
节8.6.2.1
节8.6.2.2
节8.6.2.3
节8.6.2.4
节8.6.2.5
节8.6.2.6
节8.6.2.7
节8.6.2.8
节8.6.2.9
节8.6.2.10
节8.6.2.11
节8.6.2.12
节8.6.2.13
节8.6.2.14
节8.6.2.15
节8.6.2.16
节8.6.2.17
节8.6.2.18
节8.6.2.19
节8.6.2.20
节8.6.2.21
节8.6.2.22
节8.6.2.23
节8.6.2.24
节8.6.2.25
节8.6.2.26
节8.6.2.27
节8.6.2.28
节8.6.2.29
节8.6.2.30
节8.6.2.31
节8.6.2.32
节8.6.2.33
节8.6.2.34
节8.6.2.35
节8.6.2.36
节8.6.2.37
节8.6.2.38
节8.6.2.39
1h
BMSR
2h
PHYIDR1
3h
PHYIDR2
10h
PHYSTS
11h
PHYSCR
12h
MISR1
13h
MISR2
15h
RECR
16h
BISCR
18h
MISR3
19h
REG_19
1Bh
TC10_ABORT_REG
CDCR
1Eh
1Fh
PHYRCR
41h
Register_41
Register_133
Register_17F
Register_180
Register_181
Register_182
LPS_CFG4
LPS_CFG
LPS_CFG5
LPS_CFG7
LPS_CFG8
LPS_CFG9
LPS_CFG10
LPS_CFG3
LPS_STATUS
TDR_TX_CFG
TAP_PROCESS_CFG
TDR_CFG1
TDR_CFG2
TDR_CFG3
TDR_CFG4
TDR_CFG5
TDR_TC1
133h
17Fh
180h
181h
182h
183h
184h
185h
187h
188h
189h
18Ah
18Ch
18Eh
300h
301h
302h
303h
304h
305h
306h
310h
430h
A2D_REG_48
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表8-25. DP83TC813 Registers (continued)
Address Acronym
Register Name
Section
450h
451h
452h
453h
456h
457h
458h
45Dh
45Fh
485h
486h
489h
496h
497h
4A0h
553h
560h
561h
562h
600h
601h
602h
603h
608h
609h
60Ah
60Bh
60Ch
60Dh
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
620h
622h
623h
624h
625h
626h
627h
LEDS_CFG_1
节8.6.2.40
节8.6.2.41
节8.6.2.42
节8.6.2.43
节8.6.2.44
节8.6.2.45
节8.6.2.46
节8.6.2.47
节8.6.2.48
节8.6.2.49
节8.6.2.50
节8.6.2.51
节8.6.2.52
节8.6.2.53
节8.6.2.54
节8.6.2.55
节8.6.2.56
节8.6.2.57
节8.6.2.58
节8.6.2.59
节8.6.2.60
节8.6.2.61
节8.6.2.62
节8.6.2.63
节8.6.2.64
节8.6.2.65
节8.6.2.66
节8.6.2.67
节8.6.2.68
节8.6.2.69
节8.6.2.70
节8.6.2.71
节8.6.2.72
节8.6.2.73
节8.6.2.74
节8.6.2.75
节8.6.2.76
节8.6.2.77
节8.6.2.78
节8.6.2.79
节8.6.2.80
节8.6.2.81
节8.6.2.82
LEDS_CFG_2
IO_MUX_CFG_1
IO_MUX_CFG_2
IO_MUX_CFG
IO_STATUS_1
IO_STATUS_2
CHIP_SOR_1
LED1_CLKOUT_ANA_CTRL
PCS_CTRL_1
PCS_CTRL_2
TX_INTER_CFG
JABBER_CFG
TEST_MODE_CTRL
RXF_CFG
PG_REG_4
TC1_CFG_RW
TC1_LINK_FAIL_LOSS
TC1_LINK_TRAINING_TIME
RGMII_CTRL
RGMII_FIFO_STATUS
RGMII_CLK_SHIFT_CTRL
RGMII_EEE_CTRL
SGMII_CTRL_1
SGMII_EEE_CTRL_1
SGMII_STATUS
SGMII_EEE_CTRL_2
SGMII_CTRL_2
SGMII_FIFO_STATUS
PRBS_STATUS_1
PRBS_CTRL_1
PRBS_CTRL_2
PRBS_CTRL_3
PRBS_STATUS_2
PRBS_STATUS_3
PRBS_STATUS_4
PRBS_STATUS_5
PRBS_STATUS_6
PRBS_STATUS_7
PRBS_CTRL_4
PATTERN_CTRL_1
PATTERN_CTRL_2
PATTERN_CTRL_3
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表8-25. DP83TC813 Registers (continued)
Address Acronym
Register Name
Section
节8.6.2.83
节8.6.2.84
节8.6.2.85
节8.6.2.86
节8.6.2.87
节8.6.2.88
节8.6.2.89
节8.6.2.90
节8.6.2.91
节8.6.2.92
节8.6.2.93
节8.6.2.94
节8.6.2.95
节8.6.2.96
节8.6.2.97
节8.6.2.98
节8.6.2.99
节8.6.2.100
节8.6.2.101
节8.6.2.102
628h
629h
62Ah
639h
63Ah
63Bh
63Ch
63Dh
63Eh
648h
649h
64Ah
871h
PMATCH_CTRL_1
PMATCH_CTRL_2
PMATCH_CTRL_3
TX_PKT_CNT_1
TX_PKT_CNT_2
TX_PKT_CNT_3
RX_PKT_CNT_1
RX_PKT_CNT_2
RX_PKT_CNT_3
RMII_CTRL_1
RMII_STATUS_1
RMII_OVERRIDE_CTRL
dsp_reg_71
1000h MMD1_PMA_CTRL_1
1001h MMD1_PMA_STATUS_1
1007h MMD1_PMA_STAUS_2
100Bh MMD1_PMA_EXT_ABILITY_1
1012h MMD1_PMA_EXT_ABILITY_2
1834h MMD1_PMA_CTRL_2
1836h MMD1_PMA_TEST_MODE_CTR
L
3000h MMD3_PCS_CTRL_1
3001h MMD3_PCS_Status_1
节8.6.2.103
节8.6.2.104
Complex bit access types are encoded to fit into small table cells. 表 8-26 shows the codes that are used for
access types in this section.
表8-26. DP83TC813 Access Type Codes
Access Type
Code
Description
Read Type
H
H
R
Set or cleared by hardware
Read
R
RH
R
H
Read
Set or cleared by hardware
Write Type
W
W
Write
W0S
W
Write
0S
0 to set
W1S
WSC
W
1S
Write
1 to set
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.6.2.1 BMCR Register (Address = 0h) [Reset = 2100h]
BMCR is shown in 图8-20 and described in 表8-27.
Return to the 表8-25.
图8-20. BMCR Register
15
14
13
12
11
10
9
8
MII_reset
xMII Loopback Manual_speed_
MII
Auto-
Negotiation
Enable
Power Down
Isolate
RESERVED
Duplex Mode
RH/W1S-0b
R/W-0b
6
R-1b
5
R-0b
4
R/W-0b
R/W-0b
2
R-0b
1
R-1b
0
7
3
RESERVED
R/W-0b
RESERVED
R-0b
表8-27. BMCR Register Field Descriptions
Bit
Field
MII_reset
Type
Reset
Description
15
RH/W1S
0b
MII Reset. This bit will reset the Digital blocks of the PHY and return
registers 0x0-0x0F back to default values. Other register will not be
affected.
0b = No reset
1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default
14
xMII Loopback
R/W
0b
xMII Loopback: 1 = xMII Loopback enabled 0 = Normal Operation
When xMII loopback mode is activated, the transmitted data
presented on xMII TXD is looped back to xMII RXD internally. There
is no LINK indication generated when xMII loopback is enabled.
1b = Enable Loopback from G/MII input to G/MII output
13
12
Manual_speed_MII
R
R
1b
0b
Speed Selection: Always 100-Mbps Speed
Auto-Negotiation Enable
Auto-Negotiation: Not supported on this device
0b = Disable Auto-Negotiation
11
Power Down
R/W
0b
Power Down: The PHY is powered down after this bit is set. Only
register access is enabled during this power down condition.
The power down mode can be controlled via this bit or via INT_N pin.
INT_N pin needs to be configured to operate as power down control.
This bit is OR-ed with the input from the INT_N pin. When the active
low INT_N is asserted, this bit is set.
0b = Normal Mode
1b = IEEE Power Down
10
Isolate
R/W
0b
Isolate:Isolates the port from the xMII with the exception of the serial
management interface
0b = Normal Mode
1b = Enable Isolate Mode
9
8
RESERVED
Duplex Mode
R
R
0b
1b
Reserved
1 = Full Duplex 0 = Half duplex
0b = Half duplex
1b = Full Duplex
7
RESERVED
RESERVED
R/W
R
0b
0b
Reserved
Reserved
6-0
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8.6.2.2 BMSR Register (Address = 1h) [Reset = 0061h]
BMSR is shown in 图8-21 and described in 表8-28.
Return to the 表8-25.
图8-21. BMSR Register
15
14
13
12
11
10
9
8
0
100Base-T4
100Base-X Full 100Base-X Half 10 Mbps Full
10 Mbps Half
Duplex
RESERVED
Duplex
R-0b
Duplex
R-0b
Duplex
R-0b
R-0b
R-0b
3
R-0b
7
6
5
4
2
1
RESERVED
MF Preamble
Suppression
Auto-
Negotiation
Complete
Remote fault
Auto-
Negotiation
Ability
Link status
jabber detect
Extended
Capability
R-0b
R-1b
R-1b
H-0b
R-0b
0b
H-0b
R-1b
表8-28. BMSR Register Field Descriptions
Bit
15
14
Field
100Base-T4
Type
Reset
Description
R
0b
Always 0 - PHY not able to perform 100Base-T4
100Base-X Full Duplex
100Base-X Half Duplex
10 Mbps Full Duplex
10 Mbps Half Duplex
RESERVED
R
0b
1 = PHY able to perform full duplex 100Base-X 0 = PHY not able to
perform full duplex 100Base-X
0b = PHY not able to perform full duplex 100Base-X
1b = PHY able to perform full duplex 100Base-X
13
12
11
R
R
R
R
0b
0b
0b
1 = PHY able to perform half duplex 100Base-X 0 = PHY not able to
perform half duplex 100Base-X
0b = PHY not able to perform half duplex 100Base-X
1b = PHY able to perform half duplex 100Base-X
1 = PHY able to operate at 10Mbps in full duplex 0 = PHY not able to
operate at 10Mbps in full duplex
0b = PHY not able to operate at 10Mbps in full duplex
1b = PHY able to operate at 10Mbps in full duplex
1 = PHY able to operate at 10Mbps in half duplex 0 = PHY not able
to operate at 10Mbps in half duplex
0b = PHY not able to operate at 10Mbps in half duplex
1b = PHY able to operate at 10Mbps in half duplex
10-7
6
0b
1b
Reserved
MF Preamble Suppression R
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
0b = PHY will not accept management frames with preamble
suppressed
1b = PHY will accept management frames with preamble suppressed
5
Auto-Negotiation
Complete
R
1b
1 = Auto-Negotiation process completed 0 = Auto Negotiation
process not completed (either still in process, disabled or reset)
0b = Auto Negotiation process not completed (either still in process,
disabled or reset)
1b = Auto-Negotiation process completed
4
3
2
Remote fault
H
R
0b
0b
0b
1 = Remote fault condition detected 0 = No remote fault condition
detected
0b = No remote fault condition detected
1b = Remote fault condition detected
Auto-Negotiation Ability
Link status
1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to
perform Auto-Negotiation
0b = PHY is not able to perform Auto-Negotiation
1b = PHY is able to perform Auto-Negotiation
Link Status bit
0b = Link is down
1b = Link is up
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表8-28. BMSR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
jabber detect
H
0b
1= jabber condition detected 0 = No jabber condition detected
0b = No jabber condition detected
1b = jabber condition detected
0
Extended Capability
R
1b
1 = Extended register capabilities 0 = Basic register set capabilities
only
0b = Basic register set capabilities only
1b = Extended register capabilities
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8.6.2.3 PHYIDR1 Register (Address = 2h) [Reset = 2000h]
PHYIDR1 is shown in 图8-22 and described in 表8-29.
Return to the 表8-25.
图8-22. PHYIDR1 Register
15
14
13
12
11
10
2
9
1
8
0
Organizationally Unique Identifier Bits 21:6
R-10000000000000b
7
6
5
4
3
Organizationally Unique Identifier Bits 21:6
R-10000000000000b
表8-29. PHYIDR1 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
Organizationally Unique
Identifier Bits 21:6
R
1000000000 Organizationally Unique Identification Number
0000b
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8.6.2.4 PHYIDR2 Register (Address = 3h) [Reset = A211h]
PHYIDR2 is shown in 图8-23 and described in 表8-30.
Return to the 表8-25.
图8-23. PHYIDR2 Register
15
14
13
12
11
10
2
9
1
8
0
Organizationally Unique Identifier Bits 5:0
R-101000b
Model Number
R-100001b
7
6
5
4
3
Model Number
R-100001b
Revision Number
R-1b
表8-30. PHYIDR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
Organizationally Unique
Identifier Bits 5:0
R
101000b
Organizationally Unique Identification Number
9-4
Model Number
R
R
100001b
1b
Vendor Model Number: The six bits of vendor model number are
mapped from bits 9 to 4
3-0
Revision Number
Device Revision Number
0b = Silicon Rev 1.0
1b = Silicon Rev 2.0
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8.6.2.5 PHYSTS Register (Address = 10h) [Reset = 0004h]
PHYSTS is shown in 图8-24 and described in 表8-31.
Return to the 表8-25.
图8-24. PHYSTS Register
15
14
13
12
11
10
9
8
RESERVED
RESERVED receive_error_la RESERVED
tch
RESERVED
signal_detect descrambler_lo
ck
RESERVED
R-0b
R-0b
H-0b
H-0b
4
H-0b
3
R/W0S-0b
2
R/W0S-0b
R-0b
7
6
5
1
0
mii_interrupt
H-0b
RESERVED
R-0b
jabber_dtct
R-0b
RESERVED loopback_status duplex_status
H-0b R-0b R-1b
RESERVED
R-0b
link_status
R-0b
表8-31. PHYSTS Register Field Descriptions
Bit
15
14
13
12
11
10
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
R
0b
RESERVED
R
0b
receive_error_latch
RESERVED
H
0b
RxerrCnt0 since last read.clear on read
H
0b
Reserved
Reserved
RESERVED
H
0b
signal_detect
R/W0S
0b
Channel ok latch low
0b = Channel ok had been reset
1b = Channel ok is set
9
descrambler_lock
R/W0S
0b
Descrambler lock latch low
0b = Descrmabler had been locked
1b = Descrambler is locked
8
7
RESERVED
mii_interrupt
R
H
0b
0b
Reserved
Interrupts pin status, cleared on reading 0x12 1b0 = Interrupts pin
not set 1b1 = Interrupt pin had been set
6
5
4
3
RESERVED
jabber_dtct
R
R
H
R
0b
0b
0b
0b
Reserved
duplicate from reg.0x1.1
Reserved
RESERVED
loopback_status
MII loopback status
0b = No MII loopback
1b = MII loopback
2
duplex_status
R
1b
Duplex mode status
0b = Half duplex
1b = Full duplex
1
0
RESERVED
link_status
R
R
0b
0b
Reserved
duplication of reg.0x1.2 - link_status_bit
0b = Link is down
1b = Link is up
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8.6.2.6 PHYSCR Register (Address = 11h) [Reset = 010Bh]
PHYSCR is shown in 图8-25 and described in 表8-32.
Return to the 表8-25.
图8-25. PHYSCR Register
15
14
13
12
11
10
9
1
8
dis_clk_125
pwr_save_mod
e_en
pwr_save_mode
sgmii_soft_rese use_PHYAD0_a
tx_fifo_depth
R/W-1b
t
s_Isolate
R/W-0b
R/W-0b
R/W-0b
6
R/W-0b
R/WSC-0b
7
5
4
3
2
0
RESERVED
R/W-0b
RESERVED
R-0b
int_pol
R/W-1b
force_interrupt
R/W-0b
INTEN
INT_OE
R/W-1b
R/W-1b
表8-32. PHYSCR Register Field Descriptions
Bit
Field
dis_clk_125
Type
Reset
Description
15
R/W
0b
1 = Disable CLK125 (Sourced by the CLK125 port)
1b = Disable CLK125 (Sourced by the CLK125 port)
14
pwr_save_mode_en
pwr_save_mode
R/W
R/W
0b
0b
Enable power save mode config from reg
13-12
Power Save Mode
0b = Normal mode
1b = IEEE mode: power down all digital and analog blocks, if bit [11]
set to zero, PLL is also powered down 10 = Reserved 11 = Reserved
11
10
sgmii_soft_reset
R/WSC
0b
0b
Reset SGMII
use_PHYAD0_as_Isolate R/W
1- when phy_addr == 0, isolate MAC Interface 0- do not Isolate for
PHYAD == 0.
0b = do not Isolate for PHYAD is 0.
1b = when phy_addr is 0, isolate MAC Interface
9-8
tx_fifo_depth
R/W
1b
RMII TX fifo depth
0b = 4 nibbles
1b = 5 nibbles
1010b = 6 nibbles
1011b = 8 nibbles
7
6-4
3
RESERVED
RESERVED
int_pol
R/W
R
0b
0b
1b
Reserved
Reserved
R/W
Interrupt Polarity
0b = Steady state (normal operation) without an interrupt is logical 0;
during interrupt, pin is logical 1
1b = Steady state (normal operation) without an interrupt is logical 1;
during interrupt, pin is logical 0
2
1
0
force_interrupt
INTEN
R/W
R/W
R/W
0b
1b
1b
Force interrupt pin
0b = Do not force interrupt pin
1b = Force interrupt pin
Enable interrupts
0b = Disable interrupts
1b = Enable interrupts
INT_OE
Interrupt/Power down pin configuration
0b = PIN is a power down PIN (input)
1b = PIN is an interrupt pin (output)
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8.6.2.7 MISR1 Register (Address = 12h) [Reset = 0000h]
MISR1 is shown in 图8-26 and described in 表8-33.
Return to the 表8-25.
图8-26. MISR1 Register
15
14
13
12
11
10
9
8
link_qual_int
energy_det_int
link_int
wol_int
esd_int
ms_train_done_
int
fhf_int
rhf_int
H-0b
7
H-0b
6
H-0b
H-0b
H-0b
H-0b
2
H-0b
H-0b
5
4
3
1
0
link_qual_int_en energy_det_int_
en
link_int_en
wol_int_en
esd_int_en
ms_train_done_
int_en
fhf_int_en
rhf_int_en
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-33. MISR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
link_qual_int
H
0b
Link quality(Not good) interrupt
0b = Link qual is Good
1b = Link qual is Not Good when link is ON.
14
energy_det_int
H
0b
This INT can be asserted upon Rising edge only of energy_det
signal using reg0x101 bit [0] : cfg_energy_det_int_le_only. status
output of energy_det_hist signal on reg0x19 bit[10].
0b = No Change of energy detected
1b = Change of energy_detected (both rising and falling edges)
13
12
link_int
wol_int
H
H
0b
0b
Link status change interrupt
0b = No change of link status interrupt pending.
1b = Change of link status interrupt is pending and is cleared by the
current read.
Interrupt bit indicating that WOL packet is received
0b = No WoL interrupt pending.
1b = WoL packet received interrupt is pending and is cleared by the
current read.
11
10
esd_int
H
H
0b
0b
1 = ESD detected interrupt is pending and is cleared by the current
read. 0 = No ESD interrupt pending.
ms_train_done_int
1 = M/S Link Training Completed interrupt is pending and is cleared
by the current read. 0 = No M/S Link Training Completed interrupt
pending.
9
8
fhf_int
rhf_int
H
H
0b
0b
1 = False carrier counter half-full interrupt is pending and is cleared
by the current read. 0 = No false carrier counter half-full interrupt
pending.
1 = Receive error counter half-full interrupt is pending and is cleared
by the current read. 0 = No receive error carrier counter half-full
interrupt pending.
7
6
5
4
3
2
1
0
link_qual_int_en
energy_det_int_en
link_int_en
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0b
Enable Interrupt on Link Quality status.
Enable Interrupt on change of Energy Detect histr. Status
Enable Interrupt on change of link status
wol_int_en
Enable Interrupt on WoL detection
esd_int_en
Enable Interrupt on ESD detect event
ms_train_done_int_en
fhf_int_en
Enable Interrupt on M/S Link Training Completed event
Enable Interrupt on False Carrier Counter Register half-full event
Enable Interrupt on Receive Error Counter Register half-full event
rhf_int_en
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8.6.2.8 MISR2 Register (Address = 13h) [Reset = 0000h]
MISR2 is shown in 图8-27 and described in 表8-34.
Return to the 表8-25.
图8-27. MISR2 Register
15
under_volt_int
H-0b
14
13
12
11
10
9
8
over_volt_int
H-0b
RESERVED
H-0b
RESERVED
H-0b
RESERVED
H-0b
sleep_int
H-0b
pol_int
H-0b
jabber_int
H-0b
7
6
5
4
3
2
1
0
under_volt_int_ over_volt_int_e page_rcvd_int_
Fifo_int_en
RESERVED
sleep_int_en
pol_int_en
jabber_int_en
en
n
en
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-34. MISR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
under_volt_int
H
0b
1 = Under Voltage has been detected 0 =Under Voltage has not
been detected
0b = Under Voltage has not been detected
1b = Under Voltage has been detected
14
over_volt_int
H
0b
1 = Over Voltage has been detected 0 = Over Voltage has not been
detected
0b = Over Voltage has not been detected
1b = Over Voltage has been detected
13
12
11
10
RESERVED
RESERVED
RESERVED
sleep_int
H
H
H
H
0b
0b
0b
0b
Reserved
Reserved
Reserved
1 = Sleep mode has changed 0 = Sleep mode has not changed
0b = Sleep mode has not changed
1b = Sleep mode has changed
9
8
pol_int
H
H
0b
0b
The device has auto-polarity correction when operating in slave
mode. This bit will reflect if polarity was automatically swapped or
not.
0b = Data polarity has not changed
1b = Data polarity has changed
jabber_int
1 = Jabber detected 0 = Jabber not detected
0b = Jabber not detected
1b = Jabber detected
7
6
5
4
under_volt_int_en
over_volt_int_en
page_rcvd_int_en
Fifo_int_en
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0 = Disable interrupt
0b = Disable interrupt
0 = Disable interrupt
0b = Disable interrupt
1 = Enable interrupt
1b = Enable interrupt
1 = Enable interrupt
1b = Enable interrupt
3
2
RESERVED
sleep_int_en
R/W
R/W
0b
0b
Reserved
1 = Enable interrupt
1b = Enable interrupt
1
0
pol_int_en
R/W
R/W
0b
0b
1 = Enable interrupt
1b = Enable interrupt
jabber_int_en
1 = Enable interrupt
1b = Enable interrupt
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8.6.2.9 RECR Register (Address = 15h) [Reset = 0000h]
RECR is shown in 图8-28 and described in 表8-35.
Return to the 表8-25.
图8-28. RECR Register
15
14
13
12
11
10
2
9
1
8
0
rx_err_cnt
0b
7
6
5
4
3
rx_err_cnt
0b
表8-35. RECR Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
rx_err_cnt
0b
RX_ER Counter: When a valid carrier is presented (only while
RX_DV is set), and there is at least one occurrence of an invalid data
symbol, this 16-bit counter increments for each receive error
detected. The RX_ER counter does not count in xMII loopback
mode. The counter stops when it reaches its maximum count
(0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt
is generated. This register is cleared on read.
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8.6.2.10 BISCR Register (Address = 16h) [Reset = 0100h]
BISCR is shown in 图8-29 and described in 表8-36.
Return to the 表8-25.
图8-29. BISCR Register
15
14
13
12
11
10
prbs_sync_loss
H-0b
9
8
RESERVED
R-0b
RESERVED core_pwr_mode
R-0b
R-1b
7
6
5
4
3
2
1
0
RESERVED
R-0b
tx_mii_lpbk
R/W-0b
loopback_mode
R/W-0b
pcs_lpbck
R/W-0b
RESERVED
R/W-0b
表8-36. BISCR Register Field Descriptions
Bit
15-11
10
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
prbs_sync_loss
H
0b
Prbs lock lost latch status
0b = Prbs lock never lost
1b = Prbs lock had been lost
9
8
RESERVED
R
R
0b
1b
Reserved
core_pwr_mode
1b0 = Core is in power down or sleep mode 1b1 = Core is is normal
power mode
0b = Core is in power down or sleep mode
1b = Core is is normal power mode
7
6
RESERVED
tx_mii_lpbk
R
0b
0b
Reserved
R/W
Transmit data control during xMII Loopback
0b = Suppress data during xMII loopback
1b = Transmit data on MDI during xMII loopback
5-2
loopback_mode
R/W
0b
Loopback Modes (Bit [1:0] must be 0)
1b = Digital Loopback
10b = Analog Loopback
100b = Reverse Loopback
1000b = External Loopback
1
0
pcs_lpbck
R/W
R/W
0b
0b
PCS loopback after PAM3
0b = Disable PCS Loopback
1b = Enable PCS Loopback
RESERVED
Reserved
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8.6.2.11 MISR3 Register (Address = 18h) [Reset = X]
MISR3 is shown in 图8-30 and described in 表8-37.
Return to the 表8-25.
图8-30. MISR3 Register
15
14
13
12
POR_done_int
H-0b
11
10
9
8
wup_psv_int
H-0b
no_link_int
H-0b
sleep_fail_int
H-0b
no_frame_int
H-0b
wake_req_int WUP_sleep_int
LPS_int
H-0b
H-0b
2
H-0b
1
7
6
5
4
3
0
wup_psv_int_en no_link_int_en sleep_fail_int_e POR_done_int_ no_frame_int_e wake_req_int_e WUP_sleep_int
LPS_int_en
n
en
n
n
_en
R/W-X
R/W-0b
R/W-1b
R/W-0b
R/W-0b
R/W-1b
R/W-0b
R/W-1b
表8-37. MISR3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
wup_psv_int
H
0b
0b = WUP are not received
1b = WUP received from remote PHY when in passive link
14
no_link_int
H
0b
1= Link has not been observed within time programmed in 0x562
once training has started. 0= Link up is still in progress or Link has
already formed
0b = Link up is still in progress or Link has already formed
1b = Link has not been observed within time programmed in 0x562
once training has started.
13
12
sleep_fail_int
H
H
0b
0b
0b = Sleep negotiation not failed yet
1b = Sleep negotiation failed
POR_done_int
0b = POR not completed yet
1b = POR completed (required for re-initialization of registers when
we come out of sleep)
11
10
9
no_frame_int
H
0b
0b
0b
0b
X
0b = Frame was detected
1b = No Frame detected for transmission or reception in given time
wake_req_int
H
0b = Wake-up request not received
1b = Wake-up request command was received from remote PHY
WUP_sleep_int
LPS_int
H
0b = WUP not received
1b = WUP received from remote PHY when in sleep
8
H
0b = LPS symbols not detected
1b = LPS symbols detetced
7
wup_psv_int_en
no_link_int_en
sleep_fail_int_en
POR_done_int_en
no_frame_int_en
wake_req_int_en
WUP_sleep_int_en
LPS_int_en
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b = Disable interrupt
1b = Enable interrupt
6
0b
1b
0b
0b
1b
0b
1b
0b = Disable interrupt
1b = Enable interrupt
5
0b = Disable interrupt
1b = Enable interrupt
4
0b = Disable interrupt
1b = Enable interrupt
3
0b = Disable interrupt
1b = Enable interrupt
2
0b = Disable interrupt
1b = Enable interrupt
1
0b = Disable interrupt
1b = Enable interrupt
0
0b = Disable interrupt
1b = Enable interrupt
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8.6.2.12 REG_19 Register (Address = 19h) [Reset = 0800h]
REG_19 is shown in 图8-31 and described in 表8-38.
Return to the 表8-25.
图8-31. REG_19 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
RESERVED
RESERVED
RESERVED dsp_energy_det
ect
RESERVED
R-0b
R-0b
5
R-0b
4
R-1b
3
R-0b
7
6
2
RESERVED
R-0b
PHY_ADDR
R-0b
表8-38. REG_19 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
13
RESERVED
RESERVED
RESERVED
RESERVED
dsp_energy_detect
RESERVED
PHY_ADDR
R
0b
Reserved
R
0b
Reserved
12
R
0b
Reserved
11
R
1b
Reserved
10
R
0b
DSP energy detected status
Reserved
9-5
4-0
R
0b
R
0b
PHY address decode from straps
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8.6.2.13 TC10_ABORT_REG Register (Address = 1Bh) [Reset = 0000h]
TC10_ABORT_REG is shown in 图8-32 and described in 表8-39.
Return to the 表8-25.
图8-32. TC10_ABORT_REG Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
R-0b
cfg_tc10_abort_ cfg_sleep_abort
gpio_en
R/W-0b
R/W-0b
表8-39. TC10_ABORT_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-2
1
RESERVED
R
0b
Reserved
cfg_tc10_abort_gpio_en
R/W
0b
enables aborting TC10 via GPIO. one of CLKOUT/LED_1 pins which
is being used as an LED can be used to abort
0b = disable TC10 abort via GPIO
1b = enable TC10 abort via GPIO
0
cfg_sleep_abort
R/W
0b
loc_sleep_abprt as defined by TC10 standard. Aborts sleep
negotiation while in SLEEP_ACK state
0b = allow TC10 sleep negotiation
1b = abort TC10 sleep negotiation
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8.6.2.14 CDCR Register (Address = 1Eh) [Reset = 0000h]
CDCR is shown in 图8-33 and described in 表8-40.
Return to the 表8-25.
图8-33. CDCR Register
15
14
13
12
11
10
2
9
8
tdr_start
cfg_tdr_auto_ru
n
RESERVED
R-0b
RH/W1S-0b
7
R/W-0b
6
5
4
3
1
0
RESERVED
R-0b
tdr_done
R-0b
tdr_fail
R-0b
表8-40. CDCR Register Field Descriptions
Bit
Field
Type
Reset
Description
15
tdr_start
RH/W1S
0b
clr by tdr done Start TDR manually
0b = No TDR
1b = TDR start
14
cfg_tdr_auto_run
R/W
0b
Enable TDR auto run on link down
0b = TDR start manually
1b = TDR start automatically on link down
13-2
1
RESERVED
tdr_done
R
R
0b
0b
Reserved
TDR done status
0b = TDR still not done
1b = TDR done
0
tdr_fail
R
0b
TDR fail status
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8.6.2.15 PHYRCR Register (Address = 1Fh) [Reset = 0000h]
PHYRCR is shown in 图8-34 and described in 表8-41.
Return to the 表8-25.
图8-34. PHYRCR Register
15
14
13
12
11
10
9
1
8
0
Software Global
Reset
Digital reset
RESERVED
RESERVED
RH/W1S-0b
RH/W1S-0b
R/W-0b
R/W-0b
7
6
5
4
3
2
Standby_mode
R/W-0b
RESERVED
R/W-0b
RESERVED
R-0b
RESERVED
R/W-0b
表8-41. PHYRCR Register Field Descriptions
Bit
Field
Type
Reset
Description
15
Software Global Reset
RH/W1S
0b
Hardware Reset(Reset digital + register file)
0b = Normal Operation
1b = Reset PHY. This bit is self cleared and has the same effect as
the RESET pin.
14
Digital reset
RH/W1S
0b
Software Restart
0b = Normal Operation
1b = Restart PHY. This bit is self cleared and resets all PHY circuitry
except registers.
13
12-8
7
RESERVED
RESERVED
Standby_mode
R/W
R/W
R/W
0b
0b
0b
Reserved
Reserved
Standby Mode
0b = Normal operation
1b = Standby mode enabled
6
5
RESERVED
RESERVED
RESERVED
R/W
R
0b
0b
0b
Reserved
Reserved
Reserved
4-0
R/W
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8.6.2.16 Register_41 (Address = 41h) [Reset = 88F7h]
Register_41 is shown in 图8-35 and described in 表8-42.
Return to the 表8-25.
图8-35. Register_41
15
14
13
12
11
10
2
9
1
8
0
cfg_ether_type_pattern
R/W-1000100011110111b
7
6
5
4
3
cfg_ether_type_pattern
R/W-1000100011110111b
表8-42. Register_41 Field Descriptions
Bit
15-0
Field
cfg_ether_type_pattern
Type
Reset
Description
R/W
1000100011 Ethertype pattern to be detected when 0x40[0] is enabled
110111b
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8.6.2.17 Register_133 (Address = 133h) [Reset = 0000h]
Register_133 is shown in 图8-36 and described in 表8-43.
Return to the 表8-25.
图8-36. Register_133
15
14
13
12
11
10
9
1
8
0
RESERVED
link_up_c_and_ link_status_pc
s
link_status
RESERVED
R-0b
R-0b
R-0b
R-0b
R-0b
7
6
5
4
3
2
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
descr_sync
R-0b
loc_rcvr_status rem_rcvr_status
R-0b R-0b
表8-43. Register_133 Field Descriptions
Bit
15
14
13
12
11-8
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
link_up_c_and_s
link_status_pc
link_status
R
0b
link up for C&S
PHY control in SEND_DATA state
link status set by link monitor
Reserved
R
0b
R
0b
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
descr_sync
R
0b
R
0b
Reserved
6
R
0b
Reserved
5
R
0b
Reserved
4
R
0b
Reserved
3
R
0b
Reserved
2
R
0b
Status of descrambler
0b = Scrambler Not Locked
1b = Scrambler Locked
1
0
loc_rcvr_status
rem_rcvr_status
R
R
0b
0b
Local receiver status
0b = Local PHY received link invalid
1b = Local PHY received link valid
Remote receiver status
0b = Remote PHY received link invalid
1b = Remote PHY received link valid
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8.6.2.18 Register_17F (Address = 17Fh) [Reset = 4028h]
Register_17F is shown in 图8-37 and described in 表8-44.
Return to the 表8-25.
图8-37. Register_17F
15
14
13
12
11
10
2
9
1
8
0
cfg_en_wur_via cfg_en_wup_via
RESERVED
R-0b
_wake
_wake
R/W-0b
R/W-1b
7
6
5
4
3
cfg_wake_pin_len_fr_wur_th
R/W-101000b
表8-44. Register_17F Field Descriptions
Bit
Field
Type
Reset
Description
15
cfg_en_wur_via_wake
R/W
0b
enable sending WUR when wake pin is asserted during active link.
Duration of pulse on WAKE pin can be configured in 0x17F[7:0]
0b = disable sending WUR when pulse on wake pin
1b = enable sending WUR when pulse on wake pin
14
cfg_en_wup_via_wake
RESERVED
R/W
R
1b
enable sending WUP when device is woken by WAKE pin
0b = disables WUP
1b = enables WUP
13-8
7-0
0b
Reserved
cfg_wake_pin_len_fr_wur_ R/W
th
101000b
Width of pulse in microseconds required to initiate WUR during an
active link
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8.6.2.19 Register_180 (Address = 180h) [Reset = 0000h]
Register_180 is shown in 图8-38 and described in 表8-45.
Return to the 表8-25.
图8-38. Register_180
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
cfg_sleep_req_timer_sel
R/W-0b
RESERVED
R-0b
cfg_sleep_ack_timer_sel
R/W-0b
表8-45. Register_180 Field Descriptions
Bit
Field
Type
Reset
Description
15-5
4-3
RESERVED
R
0b
Reserved
cfg_sleep_req_timer_sel
R/W
0b
Configure sleep request timer
0b = 16ms
1b = 4ms
10b = 32ms
11b = 40ms
2
RESERVED
R
0b
0b
Reserved
1-0
cfg_sleep_ack_timer_sel R/W
Configure sleep acknowledge timer
0b = 8ms
1b = 6ms
10b = 24ms
11b = 32ms
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8.6.2.20 Register_181 (Address = 181h) [Reset = 0000h]
Register_181 is shown in 图8-39 and described in 表8-46.
Return to the 表8-25.
图8-39. Register_181
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
rx_lps_cnt
R-0b
7
6
5
4
3
rx_lps_cnt
R-0b
表8-46. Register_181 Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-0
RESERVED
rx_lps_cnt
R
0b
Reserved
R
0b
indicates number of LPS codes received
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8.6.2.21 Register_182 (Address = 182h) [Reset = 0000h]
Register_182 is shown in 图8-40 and described in 表8-47.
Return to the 表8-25.
图8-40. Register_182
15
14
13
12
11
10
2
9
1
8
RESERVED
R-0b
tx_lps_cnt
R-0b
7
6
5
4
3
0
tx_lps_cnt
R-0b
表8-47. Register_182 Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-0
RESERVED
tx_lps_cnt
R
0b
Reserved
R
0b
indicates number of WUR codes received
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8.6.2.22 LPS_CFG4 Register (Address = 183h) [Reset = 0000h]
LPS_CFG4 is shown in 图8-41 and described in 表8-48.
Return to the 表8-25.
图8-41. LPS_CFG4 Register
15
14
13
12
11
10
9
8
cfg_send_wup_ cfg_force_lps_sl cfg_force_lps_sl cfg_force_tx_lp cfg_force_tx_lp cfg_force_lps_li cfg_force_lps_li cfg_force_lps_s
dis_tx
eep_en
R/W-0b
eep
s_en
s
nk_control_en
R/W-0b
nk_control
R/W-0b
t_en
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
7
6
5
4
3
2
1
0
RESERVED
R-0b
cfg_force_lps_st
R/W-0b
表8-48. LPS_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
cfg_send_wup_dis_tx
R/W
0b
Write 1 to this bit to send WUP when PHY control is in
DISABLE_TRANSMIT state
14
13
12
11
10
cfg_force_lps_sleep_en
cfg_force_lps_sleep
cfg_force_tx_lps_en
cfg_force_tx_lps
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
force control enable for sleep from LPS SM to PHY control SM
force value for sleep from LPS SM to PHY control SM
force enable for TX_LPS
force value for TX_LPS
cfg_force_lps_link_control R/W
_en
force link control enable to LPS state machine
9
8
cfg_force_lps_link_control R/W
0b
0b
0b
0b
force link control value from LPS state machine
force enable for LPS state machine
Reserved
cfg_force_lps_st_en
RESERVED
R/W
R
7
6-0
cfg_force_lps_st
R/W
force value of LPS state machine
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8.6.2.23 LPS_CFG Register (Address = 184h) [Reset = 0223h]
LPS_CFG is shown in 图8-42 and described in 表8-49.
Return to the 表8-25.
图8-42. LPS_CFG Register
15
14
13
12
11
10
2
9
8
cfg_reset_wur_
cnt_rx_data
RESERVED
R-0b
cfg_reset_lps_c
nt_rx_data
RESERVED
R-0b
cfg_reset_wur_
cnt_tx_data
RESERVED
R/W-0b
R/W-0b
4
R/W-1b
1
R-0b
0
7
6
5
3
RESERVED
cfg_reset_lps_c cfg_wake_fwd_ cfg_wake_fwd_
cfg_wake_fwd_dig_timer
R/W-0b
cfg_wake_fwd_ cfg_wake_fwd_
nt_tx_data
en_wup_psv_lin
k
man_trig
en_wur
R/W-1b
en_wup
R/W-1b
R-0b
R/W-0b
R/W-1b
R/W-0b
表8-49. LPS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
cfg_reset_wur_cnt_rx_dat R/W
a
0b
When set, resets the WUR received symbol counter upon receiving
data
14-13
12
RESERVED
R
0b
0b
Reserved
cfg_reset_lps_cnt_rx_data R/W
When set, resets the LPS received symbol counter upon receiving
data
11-10
9
RESERVED
R
0b
1b
Reserved
cfg_reset_wur_cnt_tx_dat R/W
a
When set, resets the transmitted WUR symbols count when sending
data
8-7
6
RESERVED
R
0b
0b
Reserved
cfg_reset_lps_cnt_tx_data R/W
When set, resets the transmitted LPS symbols count when sending
data
5
cfg_wake_fwd_en_wup_p R/W
sv_link
1b
control to enable/disable Wake forwarding on WAKE pin when WUP
is received when in PASSIVE_LINK mode
0b = disables wake forwarding
1b = enables wake forwarding
4
cfg_wake_fwd_man_trig
R/W
0b
0b
Write 1 to manually generate Wake forwarding signal on WAKE pin.
This bit is self-cleared
3-2
cfg_wake_fwd_dig_timer R/W
when wake up request is received on an active link, the width of
wake forwarding pulses are configurable to : 00: 50us 01: 500us 10:
2ms 11: 20ms
1
0
cfg_wake_fwd_en_wur
cfg_wake_fwd_en_wup
R/W
R/W
1b
1b
If set, enables doing wake forwarding when WUR symbols are
received
0b = Don 't do wake forwarding on WAKE pin
1b = do wake forwarding on WAKE pin
If set, enables doing wake forwarding when WUP symbols are
received
0b = Don 't do wake forwarding on WAKE pin
1b = do wake forwarding on WAKE pin
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8.6.2.24 LPS_CFG5 Register (Address = 185h) [Reset = 0000h]
LPS_CFG5 is shown in 图8-43 and described in 表8-50.
Return to the 表8-25.
图8-43. LPS_CFG5 Register
15
14
13
12
11
10
9
1
8
0
cfg_wup_timer
R/W-0b
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
cfg_rx_wur_sym_gap
R/W-0b
cfg_rx_lps_sym_gap
R/W-0b
表8-50. LPS_CFG5 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
cfg_wup_timer
R/W
0b
Time for which PHY control SM stays in WAKE_TRANSMIT b000:
1ms b001: 0.7ms b010: 1.3ms b011: 0.85ms b100: 1.5ms b101: 2ms
b110: 2.5ms b111: 3ms
12-4
3-2
RESERVED
R
0b
0b
0b
Reserved
cfg_rx_wur_sym_gap
cfg_rx_lps_sym_gap
R/W
R/W
max gap allowed b/w two WUR symbols for ack of WUR
max gap allowed b/w two LPS symbols for ack of LPS
1-0
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8.6.2.25 LPS_CFG7 Register (Address = 187h) [Reset = 0000h]
LPS_CFG7 is shown in 图8-44 and described in 表8-51.
Return to the 表8-25.
图8-44. LPS_CFG7 Register
15
14
13
12
11
10
2
9
1
8
0
cfg_tx_lps_stop
_on_done
RESERVED
R/W-0b
7
R-0b
3
6
5
4
cfg_tx_lps_sel
R/W-0b
表8-51. LPS_CFG7 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
cfg_tx_lps_stop_on_done R/W
0b
configures the device to stop sending LPS codes once it is done
sending the number of codes configures in 0x1879:0
0b = continues even after reaching limit
1b = stops after reaching limit
14-8
9-0
RESERVED
R
0b
0b
Reserved
cfg_tx_lps_sel
R/W
Indicates number of LPS symbols to be transmitted before
tx_lps_done becomes true
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8.6.2.26 LPS_CFG8 Register (Address = 188h) [Reset = 0080h]
LPS_CFG8 is shown in 图8-45 and described in 表8-52.
Return to the 表8-25.
图8-45. LPS_CFG8 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
cfg_tx_wur_sel
R/W-10000000b
7
6
5
4
3
cfg_tx_wur_sel
R/W-10000000b
表8-52. LPS_CFG8 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-0
RESERVED
R
0b
Reserved
cfg_tx_wur_sel
R/W
10000000b Indicates number of WUR symbols to be transmitted
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8.6.2.27 LPS_CFG9 Register (Address = 189h) [Reset = 0040h]
LPS_CFG9 is shown in 图8-46 and described in 表8-53.
Return to the 表8-25.
图8-46. LPS_CFG9 Register
15
14
13
12
11
10
2
9
1
8
RESERVED
R-0b
cfg_rx_lps_sel
R/W-1000000b
7
6
5
4
3
0
cfg_rx_lps_sel
R/W-1000000b
表8-53. LPS_CFG9 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-0
RESERVED
R
0b
Reserved
cfg_rx_lps_sel
R/W
1000000b
Indicates number of LPS symbols to be received to set lps_recv
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8.6.2.28 LPS_CFG10 Register (Address = 18Ah) [Reset = 0040h]
LPS_CFG10 is shown in 图8-47 and described in 表8-54.
Return to the 表8-25.
图8-47. LPS_CFG10 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
cfg_rx_wur_sel
R/W-1000000b
7
6
5
4
3
cfg_rx_wur_sel
R/W-1000000b
表8-54. LPS_CFG10 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-0
RESERVED
R
0b
Reserved
cfg_rx_wur_sel
R/W
1000000b
Indicates number of WUR symbols to be received to acknowlege
WUR and do wake forwarding
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8.6.2.29 LPS_CFG3 Register (Address = 18Ch) [Reset = 0000h]
LPS_CFG3 is shown in 图8-48 and described in 表8-55.
Return to the 表8-25.
图8-48. LPS_CFG3 Register
15
14
13
12
11
10
2
9
1
8
RESERVED
cfg_lps_pwr_m
ode
R-0b
4
RH/W1S-0b
0
7
6
5
3
cfg_lps_pwr_mode
RH/W1S-0b
表8-55. LPS_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-9
8-0
RESERVED
R
0b
Reserved
cfg_lps_pwr_mode
RH/W1S
0b
1b = Normal command
10b = Sleep request
10000b = Standby command
10000000b = WUR command
100000000b = Go to Passive Link command
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8.6.2.30 LPS_STATUS Register (Address = 18Eh) [Reset = 0000h]
LPS_STATUS is shown in 图8-49 and described in 表8-56.
Return to the 表8-25.
图8-49. LPS_STATUS Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
R-0b
status_lps_st
R-0b
表8-56. LPS_STATUS Register Field Descriptions
Bit
15-7
6-0
Field
Type
Reset
Description
RESERVED
status_lps_st
R
0b
Reserved
R
0b
LPS SM state
1b = SLEEP
10b = STANDBY
100b = NORMAL
1000b = SLEEP_ACK
10000b = SLEEP_REQ
100000b = SLEEP_FAIL
1000000b = SLEEP_SILENT
1000001b = PASSIVE_LINK
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8.6.2.31 TDR_TX_CFG Register (Address = 300h) [Reset = 2710h]
TDR_TX_CFG is shown in 图8-50 and described in 表8-57.
Return to the 表8-25.
图8-50. TDR_TX_CFG Register
15
14
13
12
11
10
2
9
1
8
0
cfg_tdr_tx_duration
R/W-10011100010000b
7
6
5
4
3
cfg_tdr_tx_duration
R/W-10011100010000b
表8-57. TDR_TX_CFG Register Field Descriptions
Bit
15-0
Field
cfg_tdr_tx_duration
Type
Reset
Description
R/W
1001110001 TDR transmit duration in usec, Default : 10000usec
0000b
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8.6.2.32 TAP_PROCESS_CFG Register (Address = 301h) [Reset = 1703h]
TAP_PROCESS_CFG is shown in 图8-51 and described in 表8-58.
Return to the 表8-25.
图8-51. TAP_PROCESS_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
cfg_end_tap_index
R/W-10111b
7
6
5
4
3
2
RESERVED
R-0b
cfg_start_tap_index
R/W-11b
表8-58. TAP_PROCESS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-8
7-5
RESERVED
R
0b
Reserved
cfg_end_tap_index
RESERVED
R/W
R
10111b
0b
End echo coefficient index for peak detect sweep during TDR
Reserved
4-0
cfg_start_tap_index
R/W
11b
Starting echo coefficient index for peak detect sweep during TDR
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8.6.2.33 TDR_CFG1 Register (Address = 302h) [Reset = 0045h]
TDR_CFG1 is shown in 图8-52 and described in 表8-59.
Return to the 表8-25.
图8-52. TDR_CFG1 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
cfg_forward_shadow
R/W-100b
cfg_post_silence_time
R/W-1b
cfg_pre_silence_time
R/W-1b
表8-59. TDR_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-4
RESERVED
cfg_forward_shadow
R
0b
Reserved
R/W
100b
Num of neighboring echo coeff taps to be considered for calculating
local maximum
3-2
1-0
cfg_post_silence_time
cfg_pre_silence_time
R/W
R/W
1b
1b
Post-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms
0x11 : 1000ms
Pre-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms
0x11 : 1000ms
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8.6.2.34 TDR_CFG2 Register (Address = 303h) [Reset = 0419h]
TDR_CFG2 is shown in 图8-53 and described in 表8-60.
Return to the 表8-25.
图8-53. TDR_CFG2 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
cfg_tdr_filt_loc_offset
R/W-100b
7
6
5
4
3
2
cfg_tdr_filt_init
R/W-11001b
表8-60. TDR_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-8
7-0
RESERVED
R
0b
Reserved
cfg_tdr_filt_loc_offset
cfg_tdr_filt_init
R/W
R/W
100b
11001b
tap index offset of dyamic peak equation, cfg_start_tap_index + 1'b1
Value of peak_th at x=start_tap_index of dynamic peak threshold
equation
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8.6.2.35 TDR_CFG3 Register (Address = 304h) [Reset = 0030h]
TDR_CFG3 is shown in 图8-54 and described in 表8-61.
Return to the 表8-25.
图8-54. TDR_CFG3 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
cfg_tdr_filt_slope
R/W-110000b
表8-61. TDR_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
RESERVED
R
0b
Reserved
cfg_tdr_filt_slope
R/W
110000b
Slope of dynamic peak threshold equation (0.4)
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8.6.2.36 TDR_CFG4 Register (Address = 305h) [Reset = 0004h]
TDR_CFG4 is shown in 图8-55 and described in 表8-62.
Return to the 表8-25.
图8-55. TDR_CFG4 Register
15
14
13
12
11
10
2
9
8
RESERVED
R-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
7
6
5
4
3
1
0
RESERVED
R/W-0b
RESERVED
R/W-0b
hpf_gain_tdr
R/W-0b
pga_gain_tdr
R/W-100b
表8-62. TDR_CFG4 Register Field Descriptions
Bit
15-10
9
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
RESERVED
RESERVED
RESERVED
hpf_gain_tdr
pga_gain_tdr
R/W
R/W
R/W
R/W
R/W
0b
Reserved
8-7
6
0b
Reserved
0b
Reserved
5-4
3-0
0b
HPF gain code during TDR
PGA gain code during TDR
100b
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8.6.2.37 TDR_CFG5 Register (Address = 306h) [Reset = 000Ah]
TDR_CFG5 is shown in 图8-56 and described in 表8-63.
Return to the 表8-25.
图8-56. TDR_CFG5 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
cfg_half_open_
det_en
cfg_cable_delay_num
R-0b
R/W-0b
R/W-1010b
表8-63. TDR_CFG5 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-5
4
RESERVED
R
0b
Reserved
cfg_half_open_det_en
R/W
0b
enables detection of half cable
0b = Disables half open detection
1b = Enbales half open detection
3-0
cfg_cable_delay_num
R/W
1010b
Configure the propagation delay per meter of the cable in
nanoseconds. This is used for the fault location estimation Valid
values : 4 'd0 to 4 'd11 - [4.5:0.1:5.6]ns Default : 4 'd10 (5.5 ns)
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8.6.2.38 TDR_TC1 Register (Address = 310h) [Reset = 0000h]
TDR_TC1 is shown in 图8-57 and described in 表8-64.
Return to the 表8-25.
图8-57. TDR_TC1 Register
15
14
13
12
11
10
2
9
1
8
RESERVED
half_open_dete
ct
R-0b
4
R-0b
0
7
6
5
3
peak_detect
R-0b
peak_sign
R-0b
peak_loc_in_meters
R-0b
表8-64. TDR_TC1 Register Field Descriptions
Bit
15-9
8
Field
Type
Reset
Description
RESERVED
R
0b
Reserved
half_open_detect
R
0b
Half wire open detect value
0b = Half wire open not detected
1b = Half wire open detected
7
6
peak_detect
R
R
R
0b
0b
0b
Set if fault is detected in cable
0b = Fault not detected in cable
1b = Fault detected in cable
peak_sign
Nature of discontinuity. Valid only if peak_detect is set
0b = Short to GND, supply, or between MDI pins
1b = Open. Applicable to both 1-wire and 2-wire open faults
5-0
peak_loc_in_meters
Fault location in meters (Valid only if peak_detect is set)
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8.6.2.39 A2D_REG_48 Register (Address = 430h) [Reset = 0770h]
A2D_REG_48 is shown in 图8-58 and described in 表8-65.
Return to the 表8-25.
图8-58. A2D_REG_48 Register
15
14
13
12
11
10
9
8
0
RESERVED
R-0b
RESERVED
R/W-0b
dll_tx_delay_ctrl_rgmii_sl
R/W-111b
7
6
5
4
3
2
1
dll_rx_delay_ctrl_rgmii_sl
R/W-111b
RESERVED
R/W-0b
表8-65. A2D_REG_48 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
15-13
12
RESERVED
RESERVED
R
0b
R/W
0b
11-8
dll_tx_delay_ctrl_rgmii_sl R/W
111b
controls TX DLL in RGMII mode inSteps of 312.5ps, affects the
CLK_90 output.
Delay = ((Bit[11:8] in decimal) + 1)*312.5 ps
7-4
3-0
dll_rx_delay_ctrl_rgmii_sl R/W
111b
0b
Controls RX DLL in RGMII mode in Steps of 312.5ps, affects the
CLK_90 output.
Delay = ((Bit[7:4] in decimal) + 1)*312.5 ps
RESERVED
R/W
Reserved
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8.6.2.40 LEDS_CFG_1 Register (Address = 450h) [Reset = 2610h]
LEDS_CFG_1 is shown in 图8-59 and described in 表8-66.
Return to the 表8-25.
图8-59. LEDS_CFG_1 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED leds_bypass_str
etching
leds_blink_rate
R/W-10b
led_2_option
R/W-110b
R-0b
7
R/W-0b
6
5
4
3
led_1_option
R/W-1b
led_0_option
R/W-0b
表8-66. LEDS_CFG_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
14
RESERVED
R
0b
Reserved
leds_bypass_stretching
R/W
0b
0 - Noraml Operation 1 - Bypass LEDs stretching
0b = Noraml Operation
1b = Bypass LEDs stretching
13-12
leds_blink_rate
R/W
10b
0b = 20Hz (50mSec)
1b = 10Hz (100mSec)
1010b = 5Hz (200mSec)
1011b = 2Hz (500mSec)
11-8
7-4
led_2_option
led_1_option
led_0_option
R/W
R/W
R/W
110b
1b
Controlls LED_2 sources
(same as bits 3:0)
Controlls LED_1 sources
(same as bits 3:0)
3-0
0b
Controlls LED_0 source:
0b = link OK
1b = link OK + blink on TX/RX activity
10b = link OK + blink on TX activity
11b = link OK + blink on RX activity
100b = link OK + 100Base-T1 Master
101b = link OK + 100Base-T1 Slave
110b = TX/RX activity with stretch option
111b = Reserved
1000b = Reserved
1001b = Link lost (remains on until register 0x1 is read)
1010b = PRBS error (toggles on error)
1011b = XMII TX/RX Error with stretch option
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8.6.2.41 LEDS_CFG_2 Register (Address = 451h) [Reset = 0049h]
LEDS_CFG_2 is shown in 图8-60 and described in 表8-67.
Return to the 表8-25.
图8-60. LEDS_CFG_2 Register
15
14
13
12
11
10
9
8
clk_o_gpio_ctrl_ led_1_gpio_ctrl led_0_gpio_ctrl
RESERVED
R-0b
led_2_drv_en
3
_3
_3
R/W-0b
R/W-0b
R/W-0b
R/W-0b
7
6
5
4
3
2
1
0
led_2_drv_val
R/W-0b
led_2_polarity
R/W-1b
led_1_drv_en
R/W-0b
led_1_drv_val
R/W-0b
led_1_polarity
R/W-1b
led_0_drv_en
R/W-0b
led_0_drv_val
R/W-0b
led_0_polarity
R/W-1b
表8-67. LEDS_CFG_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
clk_o_gpio_ctrl_3
led_1_gpio_ctrl_3
led_0_gpio_ctrl_3
R/W
0b
MSB of CLKOUT gpio control. This bit provides additional options for
configuring CLKOUT
If set to 1, it changes the effect ofclk_o_gpio_ctrl bits of 0x453
Reg 0x453[2:0] will control CLKOUT as follows
0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
14
R/W
0b
MSB of LED_1 gpio control. This bit provides additional options for
configuring LED_0
If set to 1, it changes the effect of led_1_gpio_ctrl bits of 0x452
Reg 0x452[10:8] will control LED_1 as follows
0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
13
R/W
0b
MSB of LED_0 gpio control. This bit provides additional options for
configuring LED_0
If set to 1, it changes the effect of led_0_gpio_ctrl bits of 0x452
Reg 0x452[2:0] will control LED_0 as follows
0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
12-9
8
RESERVED
R
0b
0b
Reserved
led_2_drv_en
R/W
0 - LED_2 is in normal operation mode 1 - Drive the value of LED_2
(driven value is bit 9)
0b = LED_2 is in normal operation mode
1b = Drive the value of LED_2 (driven value is bit 9)
7
led_2_drv_val
R/W
0b
If bit #8 is set, this is the value of LED_2
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表8-67. LEDS_CFG_2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
led_2_polarity
R/W
1b
LED_2 polarity
0b = Active low
1b = Active high
5
led_1_drv_en
R/W
0b
0 - LED_1 is in normal operation mode 1 - Drive the value of LED_1
(driven value is bit #5)
0b = LED_1 is in normal operation mode
1b = Drive the value of LED_1 (driven value is bit #5)
4
3
led_1_drv_val
led_1_polarity
R/W
R/W
0b
1b
If bit #4 is set, this is the value of LED_1
LED_1 polarity: if(RX_D3_strap == 1) reset_val = ~CLKOUT_strap
else reset_val = ~LED_1_strap
0b = Active low
1b = Active high
2
led_0_drv_en
R/W
0b
0 - LED_0 is in normal operation mode 1 - Drive the value of LED_0
(driven value is bit #1)
1
0
led_0_drv_val
led_0_polarity
R/W
R/W
0b
1b
If bit #1 is set, this is the value of LED_1
LED_0 polarity: reset_val = ~LED_0_strap
0b = Active low
1b = Active high
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8.6.2.42 IO_MUX_CFG_1 Register (Address = 452h) [Reset = 0000h]
IO_MUX_CFG_1 is shown in 图8-61 and described in 表8-68.
Return to the 表8-25.
图8-61. IO_MUX_CFG_1 Register
15
14
13
12
11
10
2
9
8
0
led_1_clk_div_2
_en
led_1_clk_source
led_1_clk_inv_e
n
led_1_gpio_ctrl
R/W-0b
7
R/W-0b
R/W-0b
3
R/W-0b
6
5
4
1
led_0_clk_div_2
_en
led_0_clk_source
led_0_clk_inv_e
n
led_0_gpio_ctrl
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-68. IO_MUX_CFG_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
led_1_clk_div_2_en
R/W
0b
If led_1_gpio is configured to led_1_clk_source, Selects divide by 2
of clock at led_1_clk_source
14-12
led_1_clk_source
R/W
0b
In case clk_out is MUXed to LED_1 IO, this field controls clk_out
source:
000b - XI clock
001b - 200M pll clock
010b - 67 MHz ADC clock (recovered)
011b - Free 200MHz clock
100b - 25M MII clock derived from 200M LD clock
101b - 25MHz clock to PLL (XI or XI/2) or POR clock
110b - Core 100 MHz clock
111b - 67 MHz DSP clock (recovered, 1/3 duty cycle)
11
led_1_clk_inv_en
led_1_gpio_ctrl
R/W
R/W
0b
0b
If led_1_gpio is configured to led_1_clk_source, Selects inversion of
clock at led_1_clk_source
10-8
controls the output of LED_1 IO:
000b - LED_1 (default: LINK + ACT)
001b - LED_1 Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt
if(RX_D3_strap ==1)
reset_val = 3'b001
else
reset_val = 3'b000
7
led_0_clk_div_2_en
led_0_clk_source
R/W
R/W
0b
0b
If led_0_gpio is configured to led_0_clk_source, Selects divide by 2
of clock at led_0_clk_source
6-4
In case clk_out is MUXed to LED_0 IO, this field controls clk_out
source:
0b = XI clock
1b = 200M pll clock
10b = 67 MHz ADC clock (recovered)
11b = Free 200MHz clock
100b = 25M MII clock derived from 200M LD clock
101b = 25MHz clock to PLL (XI or XI/2) or POR clock
110b = Core 100 MHz clock
111b = 67 MHz DSP clock (recovered, 1/3 duty cycle)
3
led_0_clk_inv_en
R/W
0b
If led_0_gpio is configured to led_0_clk_source, Selects inversion of
clock at led_0_clk_source
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表8-68. IO_MUX_CFG_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
led_0_gpio_ctrl
R/W
0b
controls the output of LED_0 IO:
0b = LED_0 (default: LINK) 001b =LED_0 Clock mux out 010b =
WoL 011b = Under-Voltage indication 100b = 1588 TX 101b = 1588
RX 110b = ESD 111b = interrupt
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8.6.2.43 IO_MUX_CFG_2 Register (Address = 453h) [Reset = 0001h]
IO_MUX_CFG_2 is shown in 图8-62 and described in 表8-69.
Return to the 表8-25.
图8-62. IO_MUX_CFG_2 Register
15
14
13
12
11
10
2
9
8
cfg_tx_er_on_le
d1
RESERVED
R-0b
clk_o_clk_div_2
_en
R/W-0b
7
R/W-0b
0
6
5
4
3
1
clk_o_clk_source
R/W-0b
clk_o_clk_inv_e
n
clk_o_gpio_ctrl
R/W-0b
R/W-1b
表8-69. IO_MUX_CFG_2 Register Field Descriptions
Bit
15
Field
Type
R/W
R
Reset
Description
cfg_tx_er_on_led1
RESERVED
0b
configures led_1 pin to tx_er pin and LED_1 pin is made input
Reserved
14-9
8
0b
clk_o_clk_div_2_en
R/W
0b
If clk_out is configured to output clk_o_clk_source, Selects divide by
2 of clock at clk_o_clk_source
7-4
clk_o_clk_source
R/W
0b
In case clk_out is MUXed to CLK_O IO, this field controls clk_out
source: 0000b - XI clock
0001b - 200M pll clock
0010b - 67 MHz ADC clock (recovered)
0011b - Free 200MHz clock
0100b - 25M MII clock derived from 200M LD clock
0101b - 25MHz clock to PLL (XI or XI/2) or POR clock
0110b - Core 100 MHz clock
0111b - 67 MHz DSP clock (recovered, 1/3 duty cycle)
1000b - CLK25_50 (50 MHz in RMII, 25 MHz in others)
1001b - 50M RMII RX clk
1010b - SGMII serlz clk
1011b - SGMII deserlz clk
1100b - 30ns tick
1101b - 40ns tick
1110b - DLL TX CLK
1111b - DLL RX CLK
3
clk_o_clk_inv_en
clk_o_gpio_ctrl
R/W
R/W
0b
1b
If clk_out is configured to output clk_o_clk_source, Selects inversion
of clock at clk_o_clk_source
2-0
controls the output of CLK_O IO:
000b - LED_1
001b - CLKOUT Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt
Automatically gets configured
to 3 'h0 if pin6(LED_1) is strapped
As daisy chain CLKOUT
if(RX_D3_strap ==1)
reset_val = 3'b000
else
reset_val = 3'b001
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8.6.2.44 IO_MUX_CFG Register (Address = 456h) [Reset = 0000h]
IO_MUX_CFG is shown in 图8-63 and described in 表8-70.
Return to the 表8-25.
图8-63. IO_MUX_CFG Register
15
14
13
12
11
10
9
8
rx_pins_pupd_value
rx_pins_pupd_f
orce_control
tx_pins_pupd_value
R/W-0b
tx_pins_pupd_f
orce_control
mac_rx_impedance_ctrl
R/W-0b
R/W-0b
5
R/W-0b
R/W-0b
7
6
4
3
2
1
0
mac_rx_impedance_ctrl
R/W-0b
mac_tx_impedance_ctrl
R/W-0b
表8-70. IO_MUX_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
rx_pins_pupd_value
R/W
0b
when RX pins PUPD force control is enabled, PUPD is contolled by
this register
0b = No pull
1b = Pull up
10b = Pull down
11b = Reserved
13
rx_pins_pupd_force_contr R/W
ol
0b
0b
enables PUPD force control on RX MAC pins
0b = No force control
1b = enables force control
12-11
tx_pins_pupd_value
R/W
when TX pins PUPD force control is enabled, PUPD is contolled by
this register
0b = No pull
1b = Pull up
10b = Pull down
11b = Reserved
10
tx_pins_pupd_force_contr R/W
ol
0b
enables PUPD force control on TX MAC pins
0b = No force control
1b = enables force control
9-5
4-0
mac_rx_impedance_ctrl
mac_tx_impedance_ctrl
R/W
R/W
0b
0b
RX MAC interface PAD impedance control
TX MAC interface PAD impedance control
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8.6.2.45 IO_STATUS_1 Register (Address = 457h) [Reset = 0000h]
IO_STATUS_1 is shown in 图8-64 and described in 表8-71.
Return to the 表8-25.
图8-64. IO_STATUS_1 Register
15
14
13
12
11
10
2
9
1
8
0
io_status_1
R-0b
7
6
5
4
3
io_status_1
R-0b
表8-71. IO_STATUS_1 Register Field Descriptions
Bit
15-0
Field
io_status_1
Type
Reset
Description
R
0b
If IO direction is controlled via register (IO_MUX_CFG) and
(IO_INPUT_MODE_1), and direction is INPUT
(i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current
value of the following IOs:
bit 0 - RX_D3
bit 1 - TX_CLK
bit 2 - TX_EN
bit 3 - TX_D0
bit 4 - TX_D1
bit 5 - TX_D2
bit 6 - TX_D3
bit 7 - INT_N
bit 8 - CLKOUT
bit 9 - LED_0
bit 10 - RX_CLK
bit 11 - RX_DV
bit 12 - 0
bit 13 - RX_ERR
bit 14 - LED_1
bit 15 - RX_D0
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8.6.2.46 IO_STATUS_2 Register (Address = 458h) [Reset = 0000h]
IO_STATUS_2 is shown in 图8-65 and described in 表8-72.
Return to the 表8-25.
图8-65. IO_STATUS_2 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
R-0b
io_status_2
R-0b
表8-72. IO_STATUS_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-2
1-0
RESERVED
io_status_2
R
0b
Reserved
R
0b
"If IO direction is controlled via register (IO_MUX_CFG) and
(IO_INPUT_MODE_2), and direction is INPUT (i.e.
io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value
of the following IOs: bit 0 - RX_D1 bit 1 - RX_D2 "
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8.6.2.47 CHIP_SOR_1 Register (Address = 45Dh) [Reset = 0000h]
CHIP_SOR_1 is shown in 图8-66 and described in 表8-73.
Return to the 表8-25.
图8-66. CHIP_SOR_1 Register
15
14
13
12
RX_D3_POR
R-0b
11
10
9
8
RESERVED
R-0b
RESERVED
R-0b
LED1_POR
R-0b
RESERVED
R-0b
RESERVED
R-0b
LED0_STRAP RXD3_STRAP
R-0b
1
R-0b
0
7
6
5
4
3
2
RXD2_STRAP RXD1_STRAP RXD0_STRAP RXCLK_STRAP
R-0b R-0b R-0b R-0b
RXER_STRAP
R-0b
RXDV_STRAP
R-0b
表8-73. CHIP_SOR_1 Register Field Descriptions
Bit
Field
Type
Reset
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
15
14
13
12
11
10
9
RESERVED
R
RESERVED
R
Reserved
LED1_POR
R
LED_1 strap sampled at power up
RX_D3 strap sampled at power up
Reserved
RX_D3_POR
RESERVED
R
R
RESERVED
R
Reserved
LED0_STRAP
RXD3_STRAP
RXD2_STRAP
RXD1_STRAP
RXD0_STRAP
RXCLK_STRAP
RXER_STRAP
RXDV_STRAP
R
LED_0 strap sampled at power up or reset
RX_D3 strap sampled at reset
RX_D2 strap sampled at power up or reset
RX_D1 strap sampled at power up or reset
RX_D0 strap sampled at power up or reset
RX_CLK strap sampled at power up or reset
RX_ER strap sampled at power up or reset
RX_DV strap sampled at power up or reset
8
R
7
R
6
R
5
R
4
R
3-2
1-0
R
R
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8.6.2.48 LED1_CLKOUT_ANA_CTRL Register (Address = 45Fh) [Reset = 000Ch]
LED1_CLKOUT_ANA_CTRL is shown in 图8-67 and described in 表8-74.
Return to the 表8-25.
图8-67. LED1_CLKOUT_ANA_CTRL Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
clkout_ana_sel_
1p0v_sl
led_1_ana_mux_ctrl
R/W-11b
clkout_ana_mux_ctrl
R-0b
R/W-0b
R/W-0b
表8-74. LED1_CLKOUT_ANA_CTRL Register Field Descriptions
Bit
15
Field
Type
R/W
R/W
R
Reset
Description
Reserved
Reserved
Reserved
RESERVED
0b
14
RESERVED
0b
13-5
4
RESERVED
0b
clkout_ana_sel_1p0v_sl
led_1_ana_mux_ctrl
R/W
R/W
0b
For selecting test line b/w analog test clocks
3-2
11b
Selects the signal to be sent out on LED_1 pin Automatically selects
output from digital if Pin6(LED_1) is strapped As daisy chain
CLKOUT if(RX_D3_strap == 1) reset_val = 2'b00 else reset_val =
2'b11
0b = Daisy chain clock
1b = TX_TCLK for test modes
10b = ANA Test clock
11b = clkout_out_1p0v_sl from digital
1-0
clkout_ana_mux_ctrl
R/W
0b
Selects the signal to be sent out on CLKOUT pin Automatically
selects output from digital if Pin6(LED_1) is strapped As daisy chain
CLKOUT if(RX_D3_strap == 1) reset_val = 2'b11 else reset_val =
2'b00
0b = Daisy chain clock
1b = TX_TCLK for test modes
10b = ANA Test clock
11b = clkout_out_1p0v_sl from digital
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8.6.2.49 PCS_CTRL_1 Register (Address = 485h) [Reset = 1078h]
PCS_CTRL_1 is shown in 图8-68 and described in 表8-75.
Return to the 表8-25.
图8-68. PCS_CTRL_1 Register
15
14
13
12
11
10
9
1
8
RESERVED
cfg_force_slave cfg_dis_ipg_scr cfg_link_control
RESERVED
cfg_desc_first_l
ock_count
_phase1_done
R/W-0b
_lock_check
R/W-0b
R-0b
7
R/W-1b
4
R-0b
2
R/W-1111000b
0
6
5
3
cfg_desc_first_lock_count
R/W-1111000b
表8-75. PCS_CTRL_1 Register Field Descriptions
Bit
15
14
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
cfg_force_slave_phase1_ R/W
done
0b
Force to say phase1 of DSP slave training done
13
cfg_dis_ipg_scr_lock_che R/W
ck
0b
Disable scrambler lock check during IPG
12
11-9
8-0
cfg_link_control
RESERVED
R/W
R
1b
Enable for the entire training/linkup to start
Reserved
0b
cfg_desc_first_lock_count R/W
1111000b
Number of idle symbols to decide on scrambler lock
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8.6.2.50 PCS_CTRL_2 Register (Address = 486h) [Reset = 0A05h]
PCS_CTRL_2 is shown in 图8-69 and described in 表8-76.
Return to the 表8-25.
图8-69. PCS_CTRL_2 Register
15
14
13
12
11
10
9
1
8
0
cfg_desc_error_count
R/W-1010b
7
6
5
4
3
2
RESERVED
R-0b
cfg_rem_rcvr_sts_error_cnt
R/W-101b
表8-76. PCS_CTRL_2 Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
1010b
0b
Description
15-8
7-5
cfg_desc_error_count
RESERVED
Number of non-idle ymbols to look for to say scrambler unlocked
Reserved
4-0
cfg_rem_rcvr_sts_error_c R/W
nt
101b
No of error symbols to rem rcvr status to go low
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8.6.2.51 TX_INTER_CFG Register (Address = 489h) [Reset = 0001h]
TX_INTER_CFG is shown in 图8-70 and described in 表8-77.
Return to the 表8-25.
图8-70. TX_INTER_CFG Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
cfg_force_tx_int cfg_tx_interleav cfg_interleave_
erleave
e_en
det_en
R-0b
R/W-0b
R/W-0b
R/W-1b
表8-77. TX_INTER_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
RESERVED
R
0b
Reserved
2
1
cfg_force_tx_interleave
cfg_tx_interleave_en
R/W
R/W
0b
Force interleave on Tx
0b
Enable interleave on tx, if interleave detected on the Rx
0b = Interleave on Tx disabled
1b = Interleave on Tx enabled if interleave detected on Rx
0
cfg_interleave_det_en
R/W
1b
Enable interleave detection
0b = Disable Interleave Detection
1b = Enable Interleave Detection
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8.6.2.52 JABBER_CFG Register (Address = 496h) [Reset = 044Ch]
JABBER_CFG is shown in 图8-71 and described in 表8-78.
Return to the 表8-25.
图8-71. JABBER_CFG Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R-0b
cfg_rcv_jab_timer_val
R/W-10001001100b
7
6
5
4
3
1
cfg_rcv_jab_timer_val
R/W-10001001100b
表8-78. JABBER_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-11
10-0
RESERVED
R
0b
Reserved
cfg_rcv_jab_timer_val
R/W
1000100110 Jabber timeout count in usec
0b
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8.6.2.53 TEST_MODE_CTRL Register (Address = 497h) [Reset = 01C0h]
TEST_MODE_CTRL is shown in 图8-72 and described in 表8-79.
Return to the 表8-25.
图8-72. TEST_MODE_CTRL Register
15
14
13
12
11
10
2
9
8
RESERVED
R-0b
cfg_test_mode1_symbol_cnt
R/W-11100b
7
6
5
4
3
1
0
cfg_test_mode1_symbol_cnt
R/W-11100b
RESERVED
R-0b
表8-79. TEST_MODE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
9-4
RESERVED
R
0b
Reserved
cfg_test_mode1_symbol_c R/W
nt
11100b
number of +1/-1 symbols to send in test_mode_1 N= 2 + 2*
CFG_TEST_MODE1_SYMBOL_CNT
3-0
RESERVED
R
0b
Reserved
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8.6.2.54 RXF_CFG Register (Address = 4A0h) [Reset = 1000h]
RXF_CFG is shown in 图8-73 and described in 表8-80.
Return to the 表8-25.
图8-73. RXF_CFG Register
15
bits_nibbles_swap
R/W-0b
14
13
12
11
10
2
9
8
sfd_byte
R/W-0b
RESERVED
R/W-1b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
7
6
5
4
3
1
0
enhanced_mac
_support
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R-0b
R/W-0b
表8-80. RXF_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
bits_nibbles_swap
R/W
0b
Option to swap bits / nibbles inside every RX data byte
0b = regular order, no swaps - RXD[3-0]
1b = swap bits order - RXD[0-3]
1010b = swap nibbles order - { RXD[3-0] , RXD[7-4] }
1011b = swap bits order in each nibble - { RXD[4-7] , RXD[0-3] }
13
sfd_byte
R/W
0b
0 - SFD is 0xD5 (i.e. RXF module searchs 0xD5) 1 - SFD is 0x5D
(i.e. RXF module searchs 0x5D)
0b = SFD is 0xD5 (i.e. RXF module searchs 0xD5)
1b = SFD is 0x5D (i.e. RXF module searchs 0x5D)
12
11
10-9
8
RESERVED
R/W
R/W
R/W
R/W
R/W
1b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Reserved
RESERVED
RESERVED
RESERVED
7
enhanced_mac_support
Enables enhanced RX features. This bit shall be set when using
wakeup abilities, CRC check or RX 1588 indication
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
R/W
R
0b
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
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8.6.2.55 PG_REG_4 Register (Address = 553h) [Reset = 0000h]
PG_REG_4 is shown in 图8-74 and described in 表8-81.
Return to the 表8-25.
图8-74. PG_REG_4 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0b
force_pol_en
R/W-0b
force_pol_val
R/W-0b
RESERVED
R/W-0b
7
6
5
4
3
RESERVED
R/W-0b
表8-81. PG_REG_4 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15-14
13
RESERVED
force_pol_en
0b
Reserved
0b
Enable force on polarity
0b = Auto-polarity on MDI
1b = Force polarity on MDI
12
force_pol_val
RESERVED
R/W
R/W
0b
0b
Polarity force value. Only valid if bit [13] is 1.
0b = Forced Normal polarity
1b = Forced Inverted polarity
11-0
Reserved
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8.6.2.56 TC1_CFG_RW Register (Address = 560h) [Reset = 07E4h]
TC1_CFG_RW is shown in 图8-75 and described in 表8-82.
Return to the 表8-25.
图8-75. TC1_CFG_RW Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R-0b
RESERVED
R/W-0b
cfg_link_status_metric
R/W-0b
cfg_link_failure_multihot
R/W-111111b
7
6
5
4
3
1
cfg_link_failure_multihot
R/W-111111b
cfg_comm_timer_thrs
R/W-0b
cfg_bad_sqi_thrs
R/W-100b
表8-82. TC1_CFG_RW Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
15-14
13
RESERVED
RESERVED
cfg_link_status_metric
R
0b
R/W
R/W
0b
12-11
0b
selects following link up signals as defined by C&S
0b = link_up_c_and_s
1b = link_montor_status
10b = (phy_control = SEND_DATA)
11b = comm_ready from TC1 spec
10-5
cfg_link_failure_multihot
R/W
111111b
each bit enables logging of link failure in the given scenario:
bit[5] - SQI greater than configured thershold in register
cfg_bad_sqi_thrs
bit[6] - RCV_JABBER_DET5 - BAD_SSD
bit[7] - LINK_FAILED
bit[8] - RX_ERROR
bit[9] - BAD_END
bit[10] - RESERVED
4-3
2-0
cfg_comm_timer_thrs
cfg_bad_sqi_thrs
R/W
R/W
0b
selects the hysteresis timer value for TC1 comm ready
0b = 2ms
1b = 500us
10b = 1ms
11b = 4ms
100b
SQI threshold used to increment Link Failure Count defined by TC1.
Whenever SQI becomes worse than the threshold, link failure count
(Register 0x0561 bit[9:0]) as defined by TC1 is incremented
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8.6.2.57 TC1_LINK_FAIL_LOSS Register (Address = 561h) [Reset = 0000h]
TC1_LINK_FAIL_LOSS is shown in 图8-76 and described in 表8-83.
Return to the 表8-25.
图8-76. TC1_LINK_FAIL_LOSS Register
15
14
13
12
11
10
9
1
8
link_losses
R-0b
link_failures
R-0b
7
6
5
4
3
2
0
link_failures
R-0b
表8-83. TC1_LINK_FAIL_LOSS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
link_losses
R
0b
Number of Link Losses occurred since last power cycle (as per TC1
specification)
9-0
link_failures
R
0b
Number of Link Failures causing NOT a link loss since last power
cycle (as per TC1 specification)
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8.6.2.58 TC1_LINK_TRAINING_TIME Register (Address = 562h) [Reset = 0000h]
TC1_LINK_TRAINING_TIME is shown in 图8-77 and described in 表8-84.
Return to the 表8-25.
图8-77. TC1_LINK_TRAINING_TIME Register
15
comm_ready
R-0b
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
lq_ltt
R-0b
表8-84. TC1_LINK_TRAINING_TIME Register Field Descriptions
Bit
Field
Type
Reset
Description
15
comm_ready
R
0b
TC1 comm ready signal (Optimized link status indication for higher
Layers to indicate if communication is possible via link)
0b = Communication Not Possible
1b = Communication Possible
14-8
7-0
RESERVED
lq_ltt
R
R
0b
0b
Reserved
Link training time of the last link training (as per TC1 specification)
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8.6.2.59 RGMII_CTRL Register (Address = 600h) [Reset = 0030h]
RGMII_CTRL is shown in 图8-78 and described in 表8-85.
Return to the 表8-25.
图8-78. RGMII_CTRL Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
rgmii_tx_half_full_th
cfg_rgmii_en
R/W-0b
inv_rgmii_txd
inv_rgmii_rxd sup_tx_err_fd_r
gmii
R-0b
R/W-11b
R/W-0b
R/W-0b
R/W-0b
表8-85. RGMII_CTRL Register Field Descriptions
Bit
15-7
6-4
3
Field
Type
Reset
Description
RESERVED
R
0b
Reserved
rgmii_tx_half_full_th
cfg_rgmii_en
R/W
R/W
11b
0b
RGMII TX sync FIFO half full threshold in number if nibbles
RGMII enable bit Default from strap if(RX_D2_strap == 1) reset_val
= 1 else reset_val = 0
0b = RGMII disable
1b = RGMII enable
2
1
0
inv_rgmii_txd
R/W
R/W
R/W
0b
0b
0b
Invert RGMII Tx wire order - full swap [3:0] -- [0:3]
Invert RGMII Rx wire order - full swap [3:0] -- [0:3]
this bit can disable the TX_ERR indication input
inv_rgmii_rxd
sup_tx_err_fd_rgmii
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8.6.2.60 RGMII_FIFO_STATUS Register (Address = 601h) [Reset = 0000h]
RGMII_FIFO_STATUS is shown in 图8-79 and described in 表8-86.
Return to the 表8-25.
图8-79. RGMII_FIFO_STATUS Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
rgmii_tx_af_full rgmii_tx_af_em
_err
pty_err
R-0b
R-0b
表8-86. RGMII_FIFO_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-2
RESERVED
R
0b
Reserved
1
0
rgmii_tx_af_full_err
rgmii_tx_af_empty_err
R
0b
RGMII Tx fifo full error
RGMII Tx fifo empty error
R
0b
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8.6.2.61 RGMII_CLK_SHIFT_CTRL Register (Address = 602h) [Reset = 0000h]
RGMII_CLK_SHIFT_CTRL is shown in 图8-80 and described in 表8-87.
Return to the 表8-25.
图8-80. RGMII_CLK_SHIFT_CTRL Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
cfg_rgmii_rx_clk cfg_rgmii_tx_clk
_shift_sel
_shift_sel
R/W-0b
R/W-0b
表8-87. RGMII_CLK_SHIFT_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15-2
1
R
0b
Reserved
cfg_rgmii_rx_clk_shift_sel R/W
0b
0: clock and data are aligned 1: clock on PIN is delayed by 90
degrees relative to RGMII_RX data if({RX_D2_strap, RX_D1_strap}
== 2'b11) reset_val = 1 else resett_val = 0
0b = clock and data are aligned
1b = clock on PIN is delayed by 90 degrees relative to RGMII_RX
data
0
cfg_rgmii_tx_clk_shift_sel R/W
0b
use this mode when RGMII_TX_CLK and RGMII_TXD are aligned
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b101) reset_val
= 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b110)
reset_val = 1 else reset_val = 0
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8.6.2.62 RGMII_EEE_CTRL Register (Address = 603h) [Reset = 0000h]
RGMII_EEE_CTRL is shown in 图8-81 and described in 表8-88.
Return to the 表8-25.
图8-81. RGMII_EEE_CTRL Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
R-0b
cfg_rgmii_wake_signaling_en
R/W-0b
表8-88. RGMII_EEE_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15-2
1-0
R
0b
Reserved
cfg_rgmii_wake_signaling R/W
_en
0b
RGMII signaling behavior during exit LPI period.
Bit[1] - exhibit rx_err on rx_ctrl for lpi_exit, else rx_ctrl is zero for both
lpi and exit_lpi periods.
Bit[0] - exhibit zeros on rxd for lpi_exit, else rxd=IB_code
Note: option 00b is not supported, non-valid coding.
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8.6.2.63 SGMII_CTRL_1 Register (Address = 608h) [Reset = 007Bh]
SGMII_CTRL_1 is shown in 图8-82 and described in 表8-89.
Return to the 表8-25.
图8-82. SGMII_CTRL_1 Register
15
14
13
12
11
10
2
9
8
sgmii_tx_err_di cfg_align_idx_fo
cfg_align_idx_value
R/W-0b
cfg_sgmii_en cfg_sgmii_rx_p
ol_invert
s
rce_en
R/W-0b
R/W-0b
R/W-0b
1
R/W-0b
0
7
6
5
4
3
cfg_sgmii_tx_po
l_invert
serdes_tx_bits_order
serdes_rx_bits_ cfg_sgmii_align
sgmii_autoneg_timer
sgmii_autoneg_
en
order
_pkt_en
R/W-0b
R/W-11b
R/W-1b
R/W-1b
R/W-1b
R/W-1b
表8-89. SGMII_CTRL_1 Register Field Descriptions
Bit
15
Field
Type
R/W
R/W
R/W
Reset
Description
sgmii_tx_err_dis
0b
SGMII TX err disable bit
Force word boundray index selection
14
cfg_align_idx_force_en
cfg_align_idx_value
0b
13-10
0b
when cfg_align_idx_force is set,This value set the iword boundray
index
9
cfg_sgmii_en
R/W
0b
SGMII enable bit Default from strap if({RX_D2_strap, RX_D1_strap,
RX_D0_strap} == 3'b000) reset_val = 1 else reset_val = 0
0b = SGMII MAC i/f disabled
1b = SGMII MAC i/f enabled
8
7
cfg_sgmii_rx_pol_invert
cfg_sgmii_tx_pol_invert
serdes_tx_bits_order
serdes_rx_bits_order
R/W
R/W
R/W
R/W
0b
SGMII RX bus invert polarity
0b
SGMII TX bus invert polarity
6-5
4
11b
1b
SERDES TX bits order (input to digital core)
SERDES RX bits order (output of digital core) : 0 - MSB-first (default)
1 - LSB-first (reversed order)
3
cfg_sgmii_align_pkt_en
sgmii_autoneg_timer
R/W
R/W
1b
1b
For aligning the start of read out TX packet (towards serializer) w/
tx_even pulse. To sync with the Code_Group/OSET FSM code slots.
Default is '1', when using '0' we go back to Gemini code
2-1
Selects duration of SGMII Auto-Negotiation timer
0b = 1.6ms
1b = 2us
10b = 800us
11b = 11ms
0
sgmii_autoneg_en
R/W
1b
sgmii auto negotiation enable
0b = SGMII autoneg disabled
1b = SGMII autoneg enabled
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8.6.2.64 SGMII_EEE_CTRL_1 Register (Address = 609h) [Reset = 0000h]
SGMII_EEE_CTRL_1 is shown in 图8-83 and described in 表8-90.
Return to the 表8-25.
图8-83. SGMII_EEE_CTRL_1 Register
15
14
13
12
11
10
9
8
0
cfg_sgmii_tx_tr_timer_val
R/W-0b
cfg_sgmii_tx_tq_timer_val
R/W-0b
7
6
5
4
3
2
1
cfg_sgmii_tx_tq_timer_val
R/W-0b
cfg_sgmii_tx_ts_timer_val
cfg_support_no
n_eee_mac_sg
mii_en
R/W-0b
R/W-0b
表8-90. SGMII_EEE_CTRL_1 Register Field Descriptions
Bit
15-11
10-6
5-1
Field
Type
Reset
Description
cfg_sgmii_tx_tr_timer_val R/W
cfg_sgmii_tx_tq_timer_val R/W
cfg_sgmii_tx_ts_timer_val R/W
0b
0b
0b
0
cfg_support_non_eee_ma R/W
c_sgmii_en
0b
special mode to support non sgmii eee mac in eee mode in the phy
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8.6.2.65 SGMII_STATUS Register (Address = 60Ah) [Reset = 0000h]
SGMII_STATUS is shown in 图8-84 and described in 表8-91.
Return to the 表8-25.
图8-84. SGMII_STATUS Register
15
14
13
12
11
10
9
8
RESERVED
sgmii_page_rec link_status_100 sgmii_autoneg_ cfg_align_en cfg_sync_status
eived
0bx
complete
R-0b
6
R-0b
R-0b
R-0b
R-0b
1
R-0b
0
7
5
4
3
2
cfg_align_idx
R-0b
RESERVED
R-0b
表8-91. SGMII_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12
RESERVED
R
0b
Reserved
sgmii_page_received
link_status_1000bx
R
0b
Clear on read bit. Indicates that a new auto neg page was received
11
R
0b
sgmii link status
0b = SGMII link is down
1b = SGMII link is up
10
sgmii_autoneg_complete
R
0b
sgmii autoneg complete indication
0b = SGMII autoneg incomplete
1b = SGMII autoneg completed
9
cfg_align_en
cfg_sync_status
cfg_align_idx
RESERVED
R
R
R
R
0b
0b
0b
0b
word boundary FSM - align indication
word boundary FSM - sync status indication
word boundary index selection
Reserved
8
7-4
3-0
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8.6.2.66 SGMII_EEE_CTRL_2 Register (Address = 60Bh) [Reset = 0005h]
SGMII_EEE_CTRL_2 is shown in 图8-85 and described in 表8-92.
Return to the 表8-25.
图8-85. SGMII_EEE_CTRL_2 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
cfg_sgmii_rx_quiet_timer_val
R/W-101b
表8-92. SGMII_EEE_CTRL_2 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15-4
3-0
R
0b
Reserved
cfg_sgmii_rx_quiet_timer_ R/W
val
101b
Configures the RX Quiet Timer Value.
Timer Value = (3100 + code*100)us
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8.6.2.67 SGMII_CTRL_2 Register (Address = 60Ch) [Reset = 0024h]
SGMII_CTRL_2 is shown in 图8-86 and described in 表8-93.
Return to the 表8-25.
图8-86. SGMII_CTRL_2 Register
15
14
13
12
11
10
2
9
8
RESERVED
sgmii_cdr_lock_
force_val
R-0b
R/W-0b
0
7
6
5
4
3
1
sgmii_cdr_lock_ sgmii_mr_restar
tx_half_full_th
rx_half_full_th
force_ctrl
t_an
R/W-0b
RH/W1S-0b
R/W-100b
R/W-100b
表8-93. SGMII_CTRL_2 Register Field Descriptions
Bit
15-9
8
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
sgmii_cdr_lock_force_val R/W
sgmii_cdr_lock_force_ctrl R/W
0b
SGMII cdr lock force value
SGMII cdr lock force enable
Restart sgmii autonegotiation
7
0b
6
sgmii_mr_restart_an
tx_half_full_th
RH/W1S
0b
5-3
2-0
R/W
R/W
100b
100b
SGMII TX sync FIFO half full threshold
SGMII RX sync FIFO half full threshold
rx_half_full_th
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8.6.2.68 SGMII_FIFO_STATUS Register (Address = 60Dh) [Reset = 0000h]
SGMII_FIFO_STATUS is shown in 图8-87 and described in 表8-94.
Return to the 表8-25.
图8-87. SGMII_FIFO_STATUS Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
sgmii_rx_af_full sgmii_rx_af_em sgmii_tx_af_full sgmii_tx_af_em
_err
pty_err
_err
pty_err
H-0b
H-0b
H-0b
H-0b
表8-94. SGMII_FIFO_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
3
RESERVED
R
0b
Reserved
sgmii_rx_af_full_err
H
0b
SGMII RX fifo full error
0b = No error indication
1b = SGMII RX fifo full error has been indicated
2
1
0
sgmii_rx_af_empty_err
sgmii_tx_af_full_err
H
H
H
0b
0b
0b
SGMII RX fifo empty error
0b = No error indication
1b = SGMII RX fifo empty error has been indicated
SGMII TX fifo full error
0b = No error indication
1b = SGMII TX fifo full error has been indicated
sgmii_tx_af_empty_err
SGMII TX fiff empty error
0b = No error indication
1b = SGMII TX fifo empty error has been indicated
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8.6.2.69 PRBS_STATUS_1 Register (Address = 618h) [Reset = 0000h]
PRBS_STATUS_1 is shown in 图8-88 and described in 表8-95.
Return to the 表8-25.
图8-88. PRBS_STATUS_1 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
prbs_err_ov_cnt
R-0b
表8-95. PRBS_STATUS_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
RESERVED
R
0b
Reserved
prbs_err_ov_cnt
R
0b
Holds number of error counter overflow that received by the PRBS
checker. Value in this register is locked when write is done to register
0x001B bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS
counters work in single mode, overflow counter is not active
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8.6.2.70 PRBS_CTRL_1 Register (Address = 619h) [Reset = 0574h]
PRBS_CTRL_1 is shown in 图8-89 and described in 表8-96.
Return to the 表8-25.
图8-89. PRBS_CTRL_1 Register
15
14
13
12
11
10
2
9
8
RESERVED
R-0b
cfg_pkt_gen_64
R/W-0b
send_pkt
RH/W1S-0b
RESERVED
R-0b
cfg_prbs_chk_sel
R/W-101b
7
6
5
4
3
1
0
RESERVED
R-0b
cfg_prbs_gen_sel
cfg_prbs_cnt_m cfg_prbs_chk_e cfg_pkt_gen_pr
pkt_gen_en
ode
nable
bs
R/W-111b
R/W-0b
R/W-1b
R/W-0b
R/W-0b
表8-96. PRBS_CTRL_1 Register Field Descriptions
Bit
15-14
13
Field
Type
Reset
Description
RESERVED
R
0b
Reserved
cfg_pkt_gen_64
R/W
0b
0b = Transmit 1518 byte packets in packet generation mode
1b = Transmit 64 byte packets in packet generation mode
12
send_pkt
RH/W1S
0b
Enables generating MAC packet with fix/incremental data w CRC
(pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear)
Cleared automatically when pkt_done is set
11
RESERVED
R
0b
Reserved
10-8
cfg_prbs_chk_sel
R/W
101b
000 : Checker receives from RGMII TX
001 : Checker receives from SGMII TX
010 : Checker receives from RMII RX
011 : Checker receives from MII
101 : Checker receives from Cu RX
110 : Reserved
111 : Reserved
7
RESERVED
R
0b
Reserved
6-4
cfg_prbs_gen_sel
R/W
111b
000 : PRBS transmits to RGMII RX
001 : PRBS transmits to SGMII RX
010 : PRBS transmits to RMII RX
011 : PRBS transmits to MII RX
101 : PRBS transmits to Cu TX
110 : Reserved
111 : Reserved
3
cfg_prbs_cnt_mode
R/W
0b
0b = Single mode, When one of the PRBS counters reaches max
value, PRBS checker stops counting.
1b = Continuous mode, when one of the PRBS counters reaches
max value, pulse is generated and counter starts counting from zero
again
2
1
cfg_prbs_chk_enable
cfg_pkt_gen_prbs
R/W
R/W
1b
0b
Enable PRBS checker
If set: (1) When pkt_gen_en is set, PRBS packets are generated
continuously (3) When pkt_gen_en is cleared, PRBS RX checker is
still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS
packet is generated (3) When pkt_gen_en is cleared, PRBS RX
checker is disabled as well
0
pkt_gen_en
R/W
0b
Enable/disable for prbs/packet generator
0b = Disable for prbs/packet generator
1b = Enable for prbs/packet generator
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8.6.2.71 PRBS_CTRL_2 Register (Address = 61Ah) [Reset = 05DCh]
PRBS_CTRL_2 is shown in 图8-90 and described in 表8-97.
Return to the 表8-25.
图8-90. PRBS_CTRL_2 Register
15
14
13
12
cfg_pkt_len_prbs
R/W-10111011100b
11
10
2
9
1
8
0
7
6
5
4
3
cfg_pkt_len_prbs
R/W-10111011100b
表8-97. PRBS_CTRL_2 Register Field Descriptions
Bit
15-0
Field
cfg_pkt_len_prbs
Type
Reset
Description
R/W
1011101110 Length (in bytes) of PRBS packets and MAC packets w CRC
0b
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8.6.2.72 PRBS_CTRL_3 Register (Address = 61Bh) [Reset = 007Dh]
PRBS_CTRL_3 is shown in 图8-91 and described in 表8-98.
Return to the 表8-25.
图8-91. PRBS_CTRL_3 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
cfg_ipg_len
R/W-1111101b
表8-98. PRBS_CTRL_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
RESERVED
cfg_ipg_len
R
0b
Reserved
R/W
1111101b
Inter-packet gap (in bytes) between packets
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8.6.2.73 PRBS_STATUS_2 Register (Address = 61Ch) [Reset = 0000h]
PRBS_STATUS_2 is shown in 图8-92 and described in 表8-99.
Return to the 表8-25.
图8-92. PRBS_STATUS_2 Register
15
14
13
12
11
10
2
9
1
8
0
prbs_byte_cnt
R-0b
7
6
5
4
3
prbs_byte_cnt
R-0b
表8-99. PRBS_STATUS_2 Register Field Descriptions
Bit
15-0
Field
prbs_byte_cnt
Type
Reset
Description
R
0b
Holds number of total bytes that received by the PRBS checker.
Value in this register is locked when write is done to register 0x001B
bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on
0xFFFF
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8.6.2.74 PRBS_STATUS_3 Register (Address = 61Dh) [Reset = 0000h]
PRBS_STATUS_3 is shown in 图8-93 and described in 表8-100.
Return to the 表8-25.
图8-93. PRBS_STATUS_3 Register
15
14
13
12
11
10
2
9
1
8
0
prbs_pkt_cnt_15_0
R-0b
7
6
5
4
3
prbs_pkt_cnt_15_0
R-0b
表8-100. PRBS_STATUS_3 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
prbs_pkt_cnt_15_0
R
0b
Bits [15:0] of number of total packets received by the PRBS checker
Value in this register is locked when write is done to register 0x001B
bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops
on 0xFFFFFFFF
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8.6.2.75 PRBS_STATUS_4 Register (Address = 61Eh) [Reset = 0000h]
PRBS_STATUS_4 is shown in 图8-94 and described in 表8-101.
Return to the 表8-25.
图8-94. PRBS_STATUS_4 Register
15
14
13
12
11
10
2
9
1
8
0
prbs_pkt_cnt_31_16
R-0b
7
6
5
4
3
prbs_pkt_cnt_31_16
R-0b
表8-101. PRBS_STATUS_4 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
prbs_pkt_cnt_31_16
R
0b
Bits [31:16] of number of total packets received by the PRBS
checker Value in this register is locked when write is done to register
0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count
stops on 0xFFFFFFFF
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8.6.2.76 PRBS_STATUS_5 Register (Address = 620h) [Reset = 0000h]
PRBS_STATUS_5 is shown in 图8-95 and described in 表8-102.
Return to the 表8-25.
图8-95. PRBS_STATUS_5 Register
15
14
13
12
11
10
9
8
RESERVED
R-0b
pkt_done
R-0b
pkt_gen_busy
R-0b
prbs_pkt_ov
R-0b
prbs_byte_ov
R-0b
prbs_lock
R-0b
7
6
5
4
3
2
1
0
prbs_err_cnt
R-0b
表8-102. PRBS_STATUS_5 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12
RESERVED
pkt_done
R
0b
Reserved
R
0b
Set when all MAC packets w CRC are transmitted
status of packet generator
11
pkt_gen_busy
prbs_pkt_ov
R
0b
10
R
0b
If set, packet counter reached overflow Overflow is cleared when
PRBS counters are cleared - done by setting bit[15] of 0x001B
9
prbs_byte_ov
R
0b
If set, bytes counter reached overflow Overflow is cleared when
PRBS counters are cleared - done by setting bit[15] of 0x001B
8
prbs_lock
R
R
0b
0b
prbs lock status
7-0
prbs_err_cnt
Holds number of errored bytes that received by the PRBS checker
Value in this register is locked when write is done to bit[0] or bit[1]
When PRBS Count Mode set to zero, count stops on 0xFF Notes:
Writing bit 0 generates a lock signal for the PRBS counters. Writing
bit 1 generates a lock and clear signal for the PRBS counters
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8.6.2.77 PRBS_STATUS_6 Register (Address = 622h) [Reset = 0000h]
PRBS_STATUS_6 is shown in 图8-96 and described in 表8-103.
Return to the 表8-25.
图8-96. PRBS_STATUS_6 Register
15
14
13
12
pkt_err_cnt_15_0
R-0b
11
10
2
9
1
8
0
7
6
5
4
3
pkt_err_cnt_15_0
R-0b
表8-103. PRBS_STATUS_6 Register Field Descriptions
Bit
15-0
Field
pkt_err_cnt_15_0
Type
Reset
Description
R
0b
bits [15:0] of counter which records number or PRBS erroneous
bytes received. This field gets cleared when bit[15] or bit[14] is
written as 1 to register 0x001B
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8.6.2.78 PRBS_STATUS_7 Register (Address = 623h) [Reset = 0000h]
PRBS_STATUS_7 is shown in 图8-97 and described in 表8-104.
Return to the 表8-25.
图8-97. PRBS_STATUS_7 Register
15
14
13
12
11
10
2
9
1
8
0
pkt_err_cnt_31_16
R-0b
7
6
5
4
3
pkt_err_cnt_31_16
R-0b
表8-104. PRBS_STATUS_7 Register Field Descriptions
Bit
15-0
Field
pkt_err_cnt_31_16
Type
Reset
Description
R
0b
bits [31:16] of counter which records number or PRBS erroneous
bytes received. This field gets cleared when bit[15] or bit[14] is
written as 1 to register 0x001B
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8.6.2.79 PRBS_CTRL_4 Register (Address = 624h) [Reset = 5511h]
PRBS_CTRL_4 is shown in 图8-98 and described in 表8-105.
Return to the 表8-25.
图8-98. PRBS_CTRL_4 Register
15
14
13
12
11
10
2
9
8
0
cfg_pkt_data
R/W-1010101b
7
6
5
4
3
1
cfg_pkt_mode
R/W-0b
cfg_pattern_vld_bytes
R/W-10b
cfg_pkt_cnt
R/W-1b
表8-105. PRBS_CTRL_4 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
1010101b
0b
Description
15-8
7-6
cfg_pkt_data
cfg_pkt_mode
Fixed data to be sent in Fix data mode
Selects the type of data sent
0b = Incremental Data
1b = Fixed Data
10b = PRBS Data (Random Data)
11b = PRBS Data (Random Data)
5-3
2-0
cfg_pattern_vld_bytes
cfg_pkt_cnt
R/W
R/W
10b
1b
Number of bytes of valid pattern in packet (Max - 6)
Configures the number of MAC packets to be transmitted by packet
generator
0b = 1 packet
1b = 10 packets
10b = 100 packets
11b = 1000 packets
100b = 10000 packets
101b = 100000 packets
110b = 1000000 packets
111b = Continuous packets
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8.6.2.80 PATTERN_CTRL_1 Register (Address = 625h) [Reset = 0000h]
PATTERN_CTRL_1 is shown in 图8-99 and described in 表8-106.
Return to the 表8-25.
图8-99. PATTERN_CTRL_1 Register
15
14
13
12
11
10
2
9
1
8
0
pattern_15_0
R/W-0b
7
6
5
4
3
pattern_15_0
R/W-0b
表8-106. PATTERN_CTRL_1 Register Field Descriptions
Bit
15-0
Field
pattern_15_0
Type
Reset
Description
R/W
0b
Bits 15:0 of pattern
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8.6.2.81 PATTERN_CTRL_2 Register (Address = 626h) [Reset = 0000h]
PATTERN_CTRL_2 is shown in 图8-100 and described in 表8-107.
Return to the 表8-25.
图8-100. PATTERN_CTRL_2 Register
15
14
13
12
11
10
2
9
1
8
0
pattern_31_16
R/W-0b
7
6
5
4
3
pattern_31_16
R/W-0b
表8-107. PATTERN_CTRL_2 Register Field Descriptions
Bit
15-0
Field
pattern_31_16
Type
Reset
Description
R/W
0b
Bits 31:16 of pattern
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8.6.2.82 PATTERN_CTRL_3 Register (Address = 627h) [Reset = 0000h]
PATTERN_CTRL_3 is shown in 图8-101 and described in 表8-108.
Return to the 表8-25.
图8-101. PATTERN_CTRL_3 Register
15
14
13
12
11
10
2
9
1
8
0
pattern_47_32
R/W-0b
7
6
5
4
3
pattern_47_32
R/W-0b
表8-108. PATTERN_CTRL_3 Register Field Descriptions
Bit
15-0
Field
pattern_47_32
Type
Reset
Description
R/W
0b
Bits 47:32 of pattern
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8.6.2.83 PMATCH_CTRL_1 Register (Address = 628h) [Reset = 0000h]
PMATCH_CTRL_1 is shown in 图8-102 and described in 表8-109.
Return to the 表8-25.
图8-102. PMATCH_CTRL_1 Register
15
14
13
12
11
10
2
9
1
8
0
pmatch_data_15_0
R/W-0b
7
6
5
4
3
pmatch_data_15_0
R/W-0b
表8-109. PMATCH_CTRL_1 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
pmatch_data_15_0
R/W
0b
Bits 15:0 of Perfect Match Data - used for DA (destination address)
match
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8.6.2.84 PMATCH_CTRL_2 Register (Address = 629h) [Reset = 0000h]
PMATCH_CTRL_2 is shown in 图8-103 and described in 表8-110.
Return to the 表8-25.
图8-103. PMATCH_CTRL_2 Register
15
14
13
12
11
10
2
9
1
8
0
pmatch_data_31_16
R/W-0b
7
6
5
4
3
pmatch_data_31_16
R/W-0b
表8-110. PMATCH_CTRL_2 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
pmatch_data_31_16
R/W
0b
Bits 31:16 of Perfect Match Data - used for DA (destination address)
match
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8.6.2.85 PMATCH_CTRL_3 Register (Address = 62Ah) [Reset = 0000h]
PMATCH_CTRL_3 is shown in 图8-104 and described in 表8-111.
Return to the 表8-25.
图8-104. PMATCH_CTRL_3 Register
15
14
13
12
11
10
2
9
1
8
0
pmatch_data_47_32
R/W-0b
7
6
5
4
3
pmatch_data_47_32
R/W-0b
表8-111. PMATCH_CTRL_3 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
pmatch_data_47_32
R/W
0b
Bits 47:32 of Perfect Match Data - used for DA (destination address)
match
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8.6.2.86 TX_PKT_CNT_1 Register (Address = 639h) [Reset = 0000h]
TX_PKT_CNT_1 is shown in 图8-105 and described in 表8-112.
Return to the 表8-25.
图8-105. TX_PKT_CNT_1 Register
15
14
13
12
tx_pkt_cnt_15_0
0b
11
10
2
9
1
8
0
7
6
5
4
3
tx_pkt_cnt_15_0
0b
表8-112. TX_PKT_CNT_1 Register Field Descriptions
Bit
15-0
Field
tx_pkt_cnt_15_0
Type
Reset
Description
0b
Lower 16 bits of Tx packet counter Note : Register is cleared when
0x60F, 0x610, 0x611 are read in sequence
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8.6.2.87 TX_PKT_CNT_2 Register (Address = 63Ah) [Reset = 0000h]
TX_PKT_CNT_2 is shown in 图8-106 and described in 表8-113.
Return to the 表8-25.
图8-106. TX_PKT_CNT_2 Register
15
14
13
12
tx_pkt_cnt_31_16
0b
11
10
2
9
1
8
0
7
6
5
4
3
tx_pkt_cnt_31_16
0b
表8-113. TX_PKT_CNT_2 Register Field Descriptions
Bit
15-0
Field
tx_pkt_cnt_31_16
Type
Reset
Description
0b
Upper 16 bits of Tx packet counter Note : Register is cleared when
0x60F, 0x610, 0x611 are read in sequence
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8.6.2.88 TX_PKT_CNT_3 Register (Address = 63Bh) [Reset = 0000h]
TX_PKT_CNT_3 is shown in 图8-107 and described in 表8-114.
Return to the 表8-25.
图8-107. TX_PKT_CNT_3 Register
15
14
13
12
11
10
2
9
1
8
0
tx_err_pkt_cnt
0b
7
6
5
4
3
tx_err_pkt_cnt
0b
表8-114. TX_PKT_CNT_3 Register Field Descriptions
Bit
15-0
Field
tx_err_pkt_cnt
Type
Reset
Description
0b
Tx packet w error (CRC error) counter Note : Register is cleared
when 0x60F, 0x610, 0x611 are read in sequence
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8.6.2.89 RX_PKT_CNT_1 Register (Address = 63Ch) [Reset = 0000h]
RX_PKT_CNT_1 is shown in 图8-108 and described in 表8-115.
Return to the 表8-25.
图8-108. RX_PKT_CNT_1 Register
15
14
13
12
rx_pkt_cnt_15_0
0b
11
10
2
9
1
8
0
7
6
5
4
3
rx_pkt_cnt_15_0
0b
表8-115. RX_PKT_CNT_1 Register Field Descriptions
Bit
15-0
Field
rx_pkt_cnt_15_0
Type
Reset
Description
0b
Lower 16 bits of Rx packet counter Note : Register is cleared when
0x612, 0x613, 0x614 are read in sequence
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8.6.2.90 RX_PKT_CNT_2 Register (Address = 63Dh) [Reset = 0000h]
RX_PKT_CNT_2 is shown in 图8-109 and described in 表8-116.
Return to the 表8-25.
图8-109. RX_PKT_CNT_2 Register
15
14
13
12
rx_pkt_cnt_31_16
0b
11
10
2
9
1
8
0
7
6
5
4
3
rx_pkt_cnt_31_16
0b
表8-116. RX_PKT_CNT_2 Register Field Descriptions
Bit
15-0
Field
rx_pkt_cnt_31_16
Type
Reset
Description
0b
Upper 16 bits of Rx packet counter Note : Register is cleared when
0x612, 0x613, 0x614 are read in sequence
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8.6.2.91 RX_PKT_CNT_3 Register (Address = 63Eh) [Reset = 0000h]
RX_PKT_CNT_3 is shown in 图8-110 and described in 表8-117.
Return to the 表8-25.
图8-110. RX_PKT_CNT_3 Register
15
14
13
12
11
10
2
9
1
8
0
rx_err_pkt_cnt
0b
7
6
5
4
3
rx_err_pkt_cnt
0b
表8-117. RX_PKT_CNT_3 Register Field Descriptions
Bit
15-0
Field
rx_err_pkt_cnt
Type
Reset
Description
0b
Rx packet w error (CRC error) counter Note : Register is cleared
when 0x612, 0x613, 0x614 are read in sequence
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8.6.2.92 RMII_CTRL_1 Register (Address = 648h) [Reset = 0120h]
RMII_CTRL_1 is shown in 图8-111 and described in 表8-118.
Return to the 表8-25.
图8-111. RMII_CTRL_1 Register
15
14
13
12
11
10
9
8
RESERVED
cfg_rmii_dis_del
ayed_txd_en
cfg_rmii_half_full_th
R-0b
5
R/W-0b
2
R/W-10b
7
6
4
3
1
0
cfg_rmii_half_fu cfg_rmii_mode cfg_rmii_bypass
cfg_xi_50
RESERVED
RESERVED cfg_rmii_rev1_0 cfg_rmii_enh
ll_th
_afifo_en
R/W-10b
R/W-0b
R/W-1b
R/W-0b
R/W-0b
R/W-0b R/W-0b R/W-0b
表8-118. RMII_CTRL_1 Register Field Descriptions
Bit
15-11
10
Field
RESERVED
Type
Reset
Description
R
0b
Reserved
cfg_rmii_dis_delayed_txd_ R/W
en
0b
If set, disables delay of TXD in RMII mode
9-7
6
cfg_rmii_half_full_th
cfg_rmii_mode
R/W
R/W
10b
0b
FIFO Half Full Threshold in nibbles for the RMII Rx FIFO
1 = RMII enabled 0 = RMII disabled if({RX_D2_strap, RX_D1_strap}
== 2'b01) reset_val = 1 else reset_val = 0
0b = RMII disabled
1b = RMII enabled
5
4
cfg_rmii_bypass_afifo_en R/W
1b
0b
1= RMII async fifo bypass enable 0= RMII async fifo not bypassed
0b = RMII async fifo not bypassed
1b = RMII async fifo bypass enable
cfg_xi_50
R/W
XI sel for RMII mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap}
== 3'b010) reset_val = 1 else reset_val = 0
3
2
1
0
RESERVED
RESERVED
cfg_rmii_rev1_0
cfg_rmii_enh
R/W
R/W
R/W
R/W
0b
0b
0b
0b
Reserved
Reserved
RMII Rev1.0 enable bit
RMII enahnced mode enable bit
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8.6.2.93 RMII_STATUS_1 Register (Address = 649h) [Reset = 0000h]
RMII_STATUS_1 is shown in 图8-112 and described in 表8-119.
Return to the 表8-25.
图8-112. RMII_STATUS_1 Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
RESERVED
R-0b
rmii_af_unf_err rmii_af_ovf_err
R-0b R-0b
表8-119. RMII_STATUS_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-2
RESERVED
R
0b
Reserved
1
0
rmii_af_unf_err
rmii_af_ovf_err
R
0b
Clear on read bit RMII fifo undeflow error status
Clear on Read bit RMII fifo overflow status
R
0b
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8.6.2.94 RMII_OVERRIDE_CTRL Register (Address = 64Ah) [Reset = 0010h]
RMII_OVERRIDE_CTRL is shown in 图8-113 and described in 表8-120.
Return to the 表8-25.
图8-113. RMII_OVERRIDE_CTRL Register
15
14
13
12
11
10
9
8
RESERVED
R-0b
cfg_clk50_tx_dll cfg_clk50_dll
RESERVED
R/W-0b
R/W-0b
R/W-0b
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-1b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
表8-120. RMII_OVERRIDE_CTRL Register Field Descriptions
Bit
15-11
10
Field
Type
Reset
Description
RESERVED
R
0b
Reserved
cfg_clk50_tx_dll
R/W
0b
1 = use 50M DLL clock in RMII master for TX 0 = legacy mode
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b011) reset_val
= 1 else reset_val = 0
0b = legacy mode
1b = use 50M DLL clock in RMII master for TX
9
cfg_clk50_dll
R/W
0b
1 = use 50M DLL clock in RMII slave for RX 0 = use legacy mode
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val
= 1 else reset_val = 0
0b = use legacy mode
1b = use 50M DLL clock in RMII slave for RX
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
1b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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8.6.2.95 dsp_reg_71 Register (Address = 871h) [Reset = 0000h]
dsp_reg_71 is shown in 图8-114 and described in 表8-121.
Return to the 表8-25.
图8-114. dsp_reg_71 Register
15
14
13
12
11
10
9
1
8
RESERVED
R-0b
7
6
worst_sqi_out
0b
5
4
3
2
0
RESERVED
R-0b
sqi_out
R-0b
RESERVED
R-0b
表8-121. dsp_reg_71 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-5
4
RESERVED
worst_sqi_out
RESERVED
sqi_out
R
0b
Reserved
0b
Worst SQI value since last read
Reserved
R
R
R
0b
3-1
0
0b
SQI value
RESERVED
0b
Reserved
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8.6.2.96 MMD1_PMA_CTRL_1 Register (Address = 1000h) [Reset = 0000h]
MMD1_PMA_CTRL_1 is shown in 图8-115 and described in 表8-122.
Return to the 表8-25.
图8-115. MMD1_PMA_CTRL_1 Register
15
14
13
12
11
10
9
1
8
PMA_reset
R/W-0b
RESERVED
R-0b
7
6
5
4
3
2
0
RESERVED
R-0b
PMA_loopback
R/W-0b
表8-122. MMD1_PMA_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
PMA_reset
R/W
0b
0 = PMA not reset 1= PMA reset
0b = PMA not reset
1b = PMA reset
14-1
0
RESERVED
R
0b
0b
Reserved
PMA_loopback
R/W
0 = PMA loopback not set 1= PMA loopback set
0b = PMA loopback not set
1b = PMA loopback set
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8.6.2.97 MMD1_PMA_STATUS_1 Register (Address = 1001h) [Reset = 0000h]
MMD1_PMA_STATUS_1 is shown in 图8-116 and described in 表8-123.
Return to the 表8-25.
图8-116. MMD1_PMA_STATUS_1 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
link_status
R-0b
RESERVED
R-0b
表8-123. MMD1_PMA_STATUS_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-3
2
RESERVED
link_status
R
0b
Reserved
R
0b
link status from link monitor state machine
0b = link status is down
1b = link status is up
1-0
RESERVED
R
0b
Reserved
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8.6.2.98 MMD1_PMA_STAUS_2 Register (Address = 1007h) [Reset = 003Dh]
MMD1_PMA_STAUS_2 is shown in 图8-117 and described in 表8-124.
Return to the 表8-25.
图8-117. MMD1_PMA_STAUS_2 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
PMA/PMD type selection
R-111101b
表8-124. MMD1_PMA_STAUS_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-6
5-0
RESERVED
R
0b
Reserved
PMA/PMD type selection
R
111101b
PMA or PMD type selection field
11111xb = reserved for future use
111100b = reserved for future use
1110xxb = reserved for future use
110xxxb = reserved for future use
111101b = 100BASE-T1 PMA or PMD
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8.6.2.99 MMD1_PMA_EXT_ABILITY_1 Register (Address = 100Bh) [Reset = 0800h]
MMD1_PMA_EXT_ABILITY_1 is shown in 图8-118 and described in 表8-125.
Return to the 表8-25.
图8-118. MMD1_PMA_EXT_ABILITY_1 Register
15
14
13
12
11
10
9
8
0
RESERVED
R-0b
BASE-T1
extended
abilities
RESERVED
R-1b
3
R-0b
1
7
6
5
4
2
RESERVED
R-0b
表8-125. MMD1_PMA_EXT_ABILITY_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11
RESERVED
R
0b
Reserved
BASE-T1 extended
abilities
R
1b
1 = PMA/PMD has BASE-T1 extended abilities listed in register 18 in
MMD1 0 = PMA/PMD does not have BASE-T1 extended abilities
0b = PMA/PMD does not have BASE-T1 extended abilities
1b = PMA/PMD has BASE-T1 extended abilities listed in register 18
in MMD1
10-0
RESERVED
R
0b
Reserved
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8.6.2.100 MMD1_PMA_EXT_ABILITY_2 Register (Address = 1012h) [Reset = 0001h]
MMD1_PMA_EXT_ABILITY_2 is shown in 图8-119 and described in 表8-126.
Return to the 表8-25.
图8-119. MMD1_PMA_EXT_ABILITY_2 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0b
7
6
5
4
3
2
RESERVED
R-0b
100BASE-T1
ability
R-1b
表8-126. MMD1_PMA_EXT_ABILITY_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
0
RESERVED
100BASE-T1 ability
R
0b
Reserved
R
1b
1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not
able to perform 100BASE-T1
0b = PMA/PMD is not able to perform 100BASE-T1
1b = PMA/PMD is able to perform 100BASE-T1
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8.6.2.101 MMD1_PMA_CTRL_2 Register (Address = 1834h) [Reset = 8000h]
MMD1_PMA_CTRL_2 is shown in 图8-120 and described in 表8-127.
Return to the 表8-25.
图8-120. MMD1_PMA_CTRL_2 Register
15
14
13
12
11
10
9
1
8
0
master_slave_
man_cfg_en
brk_ms_cfg
RESERVED
R-0b
R-1b
7
R/W-0b
6
5
4
3
2
RESERVED
R-0b
type selection
R-0b
表8-127. MMD1_PMA_CTRL_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
master_slave_man_cfg_e
n
R
1b
Value always 1
14
brk_ms_cfg
R/W
0b
1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE
pkg_36: reset_val = LED_0_strap pkg_28: reset_val = RX_D3_strap
0b = Configure PHY as SLAVE
1b = Configure PHY as MASTER
13-4
3-0
RESERVED
R
R
0b
0b
Reserved
type selection
type selection field 1xxxb = Reserved for future use 01xxb =
Reserved for future use 001xb = Reserved for future use 0001b =
Reserved for future use
0b = 100BASE-T1
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8.6.2.102 MMD1_PMA_TEST_MODE_CTRL Register (Address = 1836h) [Reset = 0000h]
MMD1_PMA_TEST_MODE_CTRL is shown in 图8-121 and described in 表8-128.
Return to the 表8-25.
图8-121. MMD1_PMA_TEST_MODE_CTRL Register
15
14
13
12
11
10
9
8
0
brk_test_mode
R/W-0b
RESERVED
R/W-0b
7
6
5
4
3
2
1
RESERVED
R/W-0b
表8-128. MMD1_PMA_TEST_MODE_CTRL Register Field Descriptions
Bit
15-13
Field
Type
Reset
Description
brk_test_mode
R/W
0b
100BASE-T1 test mode control
000b = Normal mode operation
001b = Test mode 1
010b = Test mode 2
011b = Reserved
100b = Test mode 4
101b = Test mode 5
110b = Reserved
111b = Reserved
12-0
RESERVED
R/W
0b
Reserved
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8.6.2.103 MMD3_PCS_CTRL_1 Register (Address = 3000h) [Reset = 0000h]
MMD3_PCS_CTRL_1 is shown in 图8-122 and described in 表8-129.
Return to the 表8-25.
图8-122. MMD3_PCS_CTRL_1 Register
15
14
13
12
11
10
9
1
8
PCS_Reset
PCS_loopback
RESERVED
rx_clock_stoppa
ble
RESERVED
R-0b
R/W-0b
7
R/W-0b
6
R-0b
4
R/W-0b
2
5
3
0
RESERVED
R-0b
表8-129. MMD3_PCS_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
PCS_Reset
R/W
0b
Reset bit, Self Clear. When write to this bit 1: 1. reset the registers
(not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please
notice: This register is WSC (write-self-clear) and not read-only!
14
13-11
10
PCS_loopback
RESERVED
R/W
R
0b
0b
0b
This bit is cleared by PCS_Reset
Reserved
rx_clock_stoppable
R/W
RW, reset value = 1. 1= PHY may stop receive clock during LPI 0=
Clock not stoppable Note: this flop implemented at glue logic
9-0
RESERVED
R
0b
Reserved
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8.6.2.104 MMD3_PCS_Status_1 Register (Address = 3001h) [Reset = 0000h]
MMD3_PCS_Status_1 is shown in 图8-123 and described in 表8-130.
Return to the 表8-25.
图8-123. MMD3_PCS_Status_1 Register
15
14
13
12
11
10
9
8
RESERVED
R-0b
TX_LPI_receive RX_LPI_receive Tx_LPI_indicati Rx_LPI_indicati
d
d
on
on
R-0b
R-0b
R-0b
R-0b
7
6
5
4
3
2
1
0
RESERVED tx_clock_stoppa
ble
RESERVED
R-0b
R-0b
R-0b
表8-130. MMD3_PCS_Status_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11
RESERVED
R
0b
Reserved
TX_LPI_received
R
0b
RO/LH
0b = LPI not received
1b = Tx PCS hs received LPI
10
9
RX_LPI_received
Tx_LPI_indication
R
R
0b
0b
RO/LH
0b = LPI not received
1b = Rx PCS hs received LPI
1= TX PCS is currently receiving LPI 0= PCS is not currently
receiving LPI
0b = PCS is not currently receiving LPI
1b = TX PCS is currently receiving LPI
8
Rx_LPI_indication
R
0b
1= RX PCS is currently receiving LPI 0= PCS is not currently
receiving LPI
0b = PCS is not currently receiving LPI
1b = RX PCS is currently receiving LPI
7
6
RESERVED
R
R
0b
0b
Reserved
tx_clock_stoppable
1= the MAC may stop the clock during LPI 0= Clock not stoppable
0b = Clock not stoppable
1b = the MAC may stop the clock during LPI
5-0
RESERVED
R
0b
Reserved
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The DP83TC813 is a single-port 100-Mbps Automotive Ethernet PHY. It supports IEEE 802.3bw and allows for
connections to an Ethernet MAC through MII, RMII, RGMII, or SGMII. When using the device for Ethernet
applications, it is necessary to meet certain requirements for normal operation. The following subsections are
intended to assist in appropriate component selection and required connections.
备注
Refer to SNLA389 Application Note for more information about the register settings used for
compliance testing. It is necessary to use these register settings to achieve the same performance as
observed during compliance testing.
9.2 Typical Applications
图9-1 through show some the typical applications for the DP83TC813x-Q1.
DC
Blocking
TX_CLK
TX_D[3:0]
TX_EN
CMC
4
TRD_P
TRD_N
Automotive
Connector
ESD
ESD
(op onal)
(op onal)
RX_CLK
RX_D[3:0]
RX_DV
4
CM
Termina on
VDDIO
Media Access Controller
DP83TC81XX-Q1
MDIO
MDC
MDI
Coupling
ESD
Shunt
GND
INT
图9-1. Typical Application (MII)
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DC
Blocking
CMC
2
2
TRD_P
TRD_N
TX_D[1:0]
TX_EN
Automotive
ESD
ESD
Connector
(op onal)
(op onal)
CM
Termina on
RX_D[1:0]
CRS_DV
VDDIO
Media Access Controller
DP83TC81XX-Q1
MDIO
MDC
MDI
Coupling
ESD
Shunt
GND
INT
XI
25-MHz
Reference
Clock
XI
RMII Reference Clock
50-MHz
Reference
Clock
图9-2. Typical Application (RMII Slave)
DC
Blocking
CMC
2
2
TRD_P
TRD_N
TX_D[1:0]
TX_EN
Automotive
Connector
ESD
ESD
(op onal)
(op onal)
CM
Termina on
RX_D[1:0]
CRS_DV
VDDIO
Media Access Controller
DP83TC81XX-Q1
MDIO
MDC
MDI
Coupling
ESD
Shunt
GND
INT
25-MHz
Reference
Clock
XI
RMII Reference Clock
RX_D3 (50-MHz)
图9-3. Typical Application (RMII Master)
DC
Blocking
TX_CLK
TX_D[3:0]
TX_CTRL
CMC
4
TRD_P
TRD_N
Automotive
Connector
ESD
ESD
(op onal)
(op onal)
RX_CLK
RX_D[3:0]
RX_CTRL
4
CM
Termina on
VDDIO
Media Access Controller
DP83TC81XX-Q1
MDIO
MDC
MDI
Coupling
ESD
Shunt
GND
INT
图9-4. Typical Application (RGMII)
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DC
Blocking
0.1 F
SIP
CMC
TRD_P
TRD_N
Automotive
Connector
0.1 F
0.1 F
ESD
ESD
SIN
(op onal)
(op onal)
CM
Termina on
SOP
0.1 F
VDDIO
SON
Media Access Controller
DP83TC81XS-Q1
MDIO
MDC
MDI
Coupling
ESD
Shunt
WAKE
INT
GND
25-MHz
Reference
Clock
图9-5. Typical Application (SGMII)
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9.2.1 Design Requirements
For these typical applications, use the following as design parameters from the table below. Refer to Power
Supply Recommendations section for detailed connection diagram.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
1.8 V, 2.5 V, or 3.3 V
1.8 V, 2.5 V, or 3.3 V
3.3 V
VDDIO
VDDMAC
VDDA
VSLEEP
3.3 V
(2) (3)
Decoupling capacitors VDDIO
0.01 μF
(3)
(Optional) ferrite bead for VDDIO
1 kΩat 100 MHz (BLM18KG601SH1D)
0.01 μF, 0.47 μF
(2)
Decoupling capacitors VDDMAC
Ferrite bead for VDDMAC
1 kΩat 100 MHz (BLM18KG601SH1D)
0.01 μF, 0.47 μF
(2)
Decoupling capacitors VDDA
(Optional) ferrite bead for VDDA
1 kΩat 100 MHz (BLM18KG601SH1D)
0.1 μF
Decoupling capacitors
VSLEEP
DC Blocking Capacitors (2)
Common-Mode Choke
0.1 μF
200 μH
1 kΩ
Common Mode Termination Resistors(1)
MDI Coupling Capacitor (2)
ESD Shunt(2)
4.7 nF
100 kΩ
25 MHz
Reference Clock
(1) 1% tolerance components are recommended.
(2) 10% tolerance components are recommended.
(3) If VDDIO is separate from VDDMAC then additional ferrite bead and 0.47μF capacitor will be
required on VDDIO.
9.2.1.1 Physical Medium Attachment
There must be no metal running beneath the common-mode choke. CMCs can inject noise into metal beneath
them, which can affect the emissions and immunity performance of the system. Because the is a voltage mode
line driver, no external termination resistors are required. The ESD shunt and MDI coupling capacitor must be
connected to ground. Ensure that the common mode termination resistors are 1% tolerance or better to improve
differential coupling.
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9.2.1.1.1 Common-Mode Choke Recommendations
The following CMCs are recommended for use with the DP83TC813S-Q1 :
表9-2. Recommended CMCs
MANUFACTURER
Pulse Electronics
Murata
PART NUMBER
AE2002
DLW43MH201XK2L
DLW32MH201XK2
ACT1210L-201
Murata
TDK
表9-3. CMC Electrical Specifications
PARAMETER
TYP
–0.5
–1.0
–26
–20
–24
–42
–25
–70
–50
–24
UNITS
CONDITIONS
dB
1 –30 MHz
30 –60 MHz
1 –30 MHz
30 –60 MHz
1 MHz
Insertion Loss
dB
dB
Return Loss
dB
dB
Common-Mode Rejection
dB
10 –100 MHz
400 MHz
dB
dB
1 –10 MHz
100 MHz
Differential Common-Mode Rejection
dB
dB
1000 MHz
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9.2.2 Detailed Design Procedure
When creating a new system design with an Ethernet PHY, follow this schematic capture procedure:
1. Select desired PHY hardware configurations in table .
2. Use the Electrical Characteristics table, the 表8-16 table and the 表8-17 table to select the correct external
bootstrap resistors.
3. If using LEDs, ensure the correct external circuit is applied as shown in 图8-19.
4. Select an appropriate clock source that adheres to either the CMOS-level oscillator or crystal resonator
requirements within the Electrical Characteristics table.
5. Select a CMC, a list of recommended CMCs are located in 表9-2.
6. Add common-mode termination, DC-blocking capacitors, an MDI-coupling capacitor, and an ESD shunt
found in 表9-1.
7. Ensure that there is sufficient supply decoupling on VDDIO and VDDA supply pins.
8. Add an external pullup resistor (tie to VDDIO) on MDIO line.
9. If operating with SGMII, place 0.1-μF, DC-blocking capacitors between the MAC and PHY SGMII pins.
10. If sleep modes are not desired, WAKE and EN pins must be tied to VSLEEP directly or through an external
pullup resistor.
The following layout procedure must be followed:
1. Locate the PHY near the edge of the board so that short MDI traces can be routed to the desired connector.
2. Place the MDI external components: CMC, DC-blocking capacitors, CM termination, MDI-coupling capacitor,
and ESD shunt.
3. Create a top-layer metal pour keepout under the CMC.
4. Ensure that the MDI TRD_M and TRD_P traces are routed such that they are 100-Ωdifferential.
5. Place the clock source near the XI and XO pins.
6. Ensure that when configured for MII, RMII, or RGMII operation, the xMII pins are routed 50-Ωand are
single-ended with reference to ground.
7. Ensure that transmit path xMII pins are routed such that setup and hold timing does not violate the PHY
requirements.
8. Ensure that receive path xMII pins are routed such that setup and hold timing does not violate the MAC
requirements.
9. Ensure that when configured for SGMII operation, the xMII RX_P, RX_M, TX_P, and TX_M pins are routed
100-Ωdifferential.
10. Place the MDIO pullup close to the PHY.
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9.2.3 Application Curves
The following curves were obtained using the PHY evaluation module under nominal conditions.
图9-6. MDI IDLE Stream
图9-7. MDI IDLE Stream (Variable Persistence)
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10 Power Supply Recommendations
The DP83TC813S-Q1is capable of operating with a wide range of IO supply voltages (3.3 V, 2.5 V, or 1.8 V). No
power supply sequencing is required. The recommended power supply de-coupling network is shown in the
figure below. For improved conducted emissions, an optional ferrite bead may be placed between the supply and
the PHY de-coupling network.
Typical TC-10 application block diagram along with supply and peripherals is shown below. TPS7B81-Q1 is the
recommended part number to be used as 3.3V LDO for the VSLEEP rail. The low quiescent current of this LDO
makes it ideal for TC-10 applications.
Opꢀonal Ferrite Bead
VDDA
0.01µF
0.47µF
Ferrite Bead
0.01µF
0.47µF
VREG
(3.3V)
VSLEEP
VBAT
VREG
(3.3V)
INH
0.1µF
0.01µF
TPS7B81
10k
GND
VDDIO
MII
RMII
RGMII
SGMII
100BASE-T1
IEEE 802.3bw
VDDMAC
CMC
DP83TC81XX-Q1
100BASE-T1
Ethernet PHY
CPU/MPU
MAC
Automotive
Connector
ESD
ESD
(3.3V)
(opꢀonal)
(opꢀonal)
WAKE
10k
GND
DC
Blocking
CM
Terminaꢀon
Downstream
PHYs
25MHz
Clock
Source
Output
Clock
Optional
Straps
Status
LEDs
MDI
Coupling
ESD
Shunt
NOTE: When VDDIO is separate from VDDMAC, extra ferrite bead and 0.47uF capacitor must
be used for decoupling.
GND
图10-1. Typical TC-10 Application With Peripherals
When VDDIO and VDDMAC are separate, both voltage rails must have a dedicated network of ferrite bead,
0.47uF, and 0.01uF capacitors. VSLEEP can also be connected to VDDA, 0.1uF capacitor must be retained in
this configuration.
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Current Consumption Break-Down
The following table highlights the break down of power consumption in active mode for each supply rail,
specifically highlighting the split between VDDMAC and VDDIO.
表10-1. Active Mode Current Consumption
VOLTAGE RAIL
VOLTAGE (V)
MAX CURRENT (mA)1
MII
3.3
3.3
2.5
1.8
3.3
2.5
1.8
3.3
VDDA
63
VDDIO
4
3
2
VDDMAC
VSLEEP
20
15
11
2
RMII
3.3
3.3
2.5
1.8
3.3
2.5
1.8
3.3
VDDA
63
6
VDDIO
4
3
VDDMAC
VSLEEP
17
13
10
2
RGMII
3.3
VDDA
63
4
VDDIO
3.3
2.5
3
1.8
2
VDDMAC
VSLEEP
3.3
17
13
10
2
2.5
1.8
3.3
SGMII
3.3
VDDA
95
4
VDDIO
3.3
2.5
3
1.8
2
VDDMAC
3.3
8
2.5
6
1.8
4
3.3
2
VSLEEP
1. Current consumption measured across voltage, temperature, and process with active data communication.
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11 Layout
11.1 Layout Guidelines
11.1.1 Signal Traces
PCB traces are lossy and long traces can degrade signal quality. Traces must be kept short as possible. Unless
mentioned otherwise, all signal traces must be 50-Ω, single-ended impedance. Differential traces must be 50-Ω
single-ended and 100-Ω differential. Take care to ensure impedance is controlled throughout. Impedance
discontinuities will cause reflections leading to emissions and signal integrity issues. Stubs must be avoided on
all signal traces, especially differential signal pairs.
图11-1. Differential Signal Trace Routing
Within the differential pairs, trace lengths must be run parallel to each other and matched in length. Matched
lengths minimize delay differences, avoiding an increase in common mode noise and emissions. Length
matching is also important for MAC interface connections. All transmit signal traces must be length matched to
each other and all receive signal traces must be length matched to each other. For SGMII differential traces, it is
recommended to keep the skew mismatch below 20ps.
Ideally, there must be no crossover on signal path traces. High speed signal traces must be routed on internal
layers to improved EMC performance. However, vias present impedance discontinuities and must be minimized
when possible. Route trace pairs on the same layer. Signals on different layers must not cross each other
without at least one return path plane between them. Differential pairs must always have a constant coupling
distance between them. For convenience and efficiency, TI recommends routing critical signals first (that is, MDI
differential pairs, reference clock, and MAC IF traces).
11.1.2 Return Path
A general best practice is to have a solid return path beneath all signal traces. This return path can be a
continuous ground or DC power plane. Reducing the width of the return path can potentially affect the
impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to
the width of the signal trace. Breaks in return path between the signal traces must be avoided at all cost. A signal
crossing a split plane may cause unpredictable return path currents and could impact signal quality and result in
emissions issues.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 183
Product Folder Links: DP83TC813S-Q1 DP83TC813R-Q1
DP83TC813S-Q1, DP83TC813R-Q1
ZHCSQL1 –MAY 2022
www.ti.com.cn
图11-2. Power and Ground Plane Breaks
11.1.3 Metal Pour
All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the
system, and there must be no metal between differential traces.
11.1.4 PCB Layer Stacking
To meet signal integrity and performance requirements, minimum four-layer PCB is recommended. However, a
six-layer PCB and above must be used when possible.
图11-3. Recommended PCB Layer Stack-Up
Copyright © 2022 Texas Instruments Incorporated
184 Submit Document Feedback
Product Folder Links: DP83TC813S-Q1 DP83TC813R-Q1
DP83TC813S-Q1, DP83TC813R-Q1
www.ti.com.cn
ZHCSQL1 –MAY 2022
11.2 Layout Example
There is an evaluation board references for the DP83TC813-Q1 . The DP83TC813EVM-MC is a media
converter board which can be used for interoperability and bit error rate testing.
Di eren al Rou ng
Void metal under CMC on top layer
Di eren al Rou ng
Power Ground
Di eren al Rou ng
CM Connec on
Automotive
Connector
图11-4. MDI Low-Pass Filter Layout Recommendation
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 185
Product Folder Links: DP83TC813S-Q1 DP83TC813R-Q1
DP83TC813S-Q1, DP83TC813R-Q1
ZHCSQL1 –MAY 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.3 Community Resources
12.4 Trademarks
PHYTER™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
186 Submit Document Feedback
Product Folder Links: DP83TC813S-Q1 DP83TC813R-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DP83TC813RRHFRQ1
DP83TC813RRHFTQ1
DP83TC813SRHFRQ1
DP83TC813SRHFTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
28
28
28
28
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
813R
813R
813S
813S
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DP83TC813RRHFRQ1
DP83TC813RRHFTQ1
DP83TC813SRHFRQ1
DP83TC813SRHFTQ1
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
28
28
28
28
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DP83TC813RRHFRQ1
DP83TC813RRHFTQ1
DP83TC813SRHFRQ1
DP83TC813SRHFTQ1
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
28
28
28
28
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0028B
VQFN - 1.0 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.13)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2.55 0.1
2X 2.5
(0.2) TYP
9
EXPOSED
14
THERMAL PAD
24X 0.5
15
8
(0.16)
TYP
3.55 0.1
A
SYMM
A
2X
29
3.5
1
22
0.30
28X
0.18
0.1
C A B
PIN 1 ID
28
23
SYMM
0.05
0.5
28X
0.3
4225972/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHF0028B
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.55)
SYMM
28
23
28X (0.6)
22
1
28X (0.24)
(3.55)
(1.525)
24X (0.5)
29
SYMM
(4.8)
(
0.2) TYP
VIA
8
15
(R0.05)
TYP
9
14
(1.025)
(3.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225972/A 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHF0028B
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.13)
(0.665) TYP
23
28
28X (0.6)
1
22
28X (0.24)
(0.865)
TYP
24X (0.5)
SYMM
(4.8)
29
4X (1.53)
(R0.05) TYP
8
15
METAL
TYP
14
9
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225972/A 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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