DP83TD510E [TI]
DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY;
| 型号： | DP83TD510E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY |
| 文件： | 总45页 (文件大小：1895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP83TD510L
SNLS656 – AUGUST 2020
DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY
1 Features
2 Applications
•
Long cable reach
•
Process automation
– 1200 meters+ with 1-V p2p
– 1200 meters+ with 2.4-V p2p
Ultra-low power
– Field transmitters and switches
Building automation
– HVAC controllers
•
•
– 45 mW for 1-V p2p mode
– 99 mW for 2.4-V p2p mode
Compliant to IEEE 802.3cg 10Base-T1L
IEC 61000-4-4 EFT ±4 KV at 5 KHz, 100 KHz
CISPR22 radiated emission class B
External MDI terminations for intrinsic safety
MAC interface:
– MII mode
– RMII master/slave mode
– RGMII mode
– RMII master low-power 5-MHz mode
– RMII back-2-back mode for range extender
Power supply
– single supply operations from 3.3 V
– dual supply operations for lowest power
dissipation
– Elevators and escalators
– Fire safety
Factory automation and control
•
•
•
•
•
•
3 Description
The DP83TD510E is an ultra-low power Ethernet
physical layer transceiver compliant with the IEEE
802.3cg 10Base-T1L specification. The PHY has very
low noise coupled receiver architecture enabling long
cable reach and very low power dissipation. The
DP83TD510E has external MDI termination to support
intrinsic safety requirements. It interfaces with MAC
layer through MII, Reduced MII (RMII) , RGMII, and
RMII low power 5-MHz master mode. It also supports
RMII back-to-back mode for applications that require
cable reach extension beyond 1200 meters. It
supports a 25MHz reference clock output to clock
other modules on the system. The DP83TD510E
offers integrated cable diagnostic tools; built-in self-
test, and loopback capabilities for ease of design or
debug.
•
•
•
I/O voltages: 1.8 V, 2.5 V or 3.3 V
Diagnostics tool kit
– cable open and short detection
– receiver SQI to measure cable degradation
– active link cable diagnostics
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
•
•
•
•
Clock output: 25 MHz, 50 MHz (RMII master)
±6-kV HBM ESD protection on MDI pins
Operating temperature range: –40°C to 105°C
Package: 5 mm x 5 mm, 32 pin with 0.5 mm pitch
DP83TD510E
QFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
25 MHz XTAL/Ref Clock
25/50 MHz
Interrupt
Tx+
Rx+
DP83TD510
M
A
C
IEEE802.3cg
10Base-T1L
RMII/MII
Rx-
Tx-
MDC,MDIO
VDDA :3V3 or 1V8
DVDD :1V0 ( Optional)
VDDIO:3V3/2V5/1V8
DP83TD510E Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
DP83TD510L
SNLS656 – AUGUST 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings ....................................... 7
6.2 ESD Ratings .............................................................. 7
6.3 Recommended Operating Conditions ........................7
6.4 Thermal Information ...................................................9
6.5 Electrical Characteristics ..........................................10
6.6 Timing Requirements ...............................................13
6.7 Timing Diagrams.......................................................15
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................25
7.5 Programming............................................................ 27
7.6 Register Maps...........................................................28
8 Application and Implementation..................................29
8.1 Application Information............................................. 29
8.2 Typical Applications.................................................. 29
9 Power Supply Recommendations................................33
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 37
11 Device and Documentation Support..........................38
11.1 Device Support........................................................38
11.2 Support Resources................................................. 38
11.3 Trademarks............................................................. 38
11.4 Electrostatic Discharge Caution..............................38
11.5 Glossary..................................................................38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2020
*
Advance Information Release
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5 Pin Configuration and Functions
27
31
30
28
26
32
25
29
DVDD
CEXT
1
2
TX_D0
24
TX_EN
23
22
DP83TD510E
3
VDDA
TX+
TX_CLK
TOP VIEW
(not to scale)
4
5
6
21
20
PWDN/INT_N
RX_ER/Strap6
RX+
RX-
32-pin QFN Package
5mmx5mm
DAP = GND
RX_CLK/50MHz_RMII_M
RX_DV/CRS_DV/Strap5
19
18
TX-
7
VDDIO
17
8
GPIO2/Strap10
11
12
13
14
15
16
9
10
Copyright © 2020, Texas Instruments Incorporated
Figure 5-1. RMQ Package 32-Pin VQFN Top View
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Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO
DVDD
1
2
3
A
Digital supply 1.0 V
•
•
For single-supply operation: Short this pin with CEXT (Pin 2)
Optional (dual-supply operation): Connect external 1.0 V to achieve lowest power
Refer to Power Connection Diagram in Application section
External capacitor for internal LDO
CEXT
VDDA
A
A
•
•
For single-supply operation: Connect 0.01- μF capacitor and short it with pin 1
For dual-supply operation, leave unconnected
Refer to Power Connection Diagram in Application section
Supply 3.3 V to support both long reach and short reach.
Supply 1.8 V to support only short reach.
Supplied voltage will be reflected in bit 13 of auto negotiation base page as capability to
support 2.4-V p2p or 1-V p2p.
0x20E, bit 13 = 1 when 3.3 V is selected.
0x20E, bit 13 = 0 when 1.8 V is selected.
Ensure the Strap7 "Reach Selection" strap is selected appropriately to request the output
voltage level in the auto negotiation page.
TX+
4
A
TX+, TX- : Differential Transmit Output (PMD): These differential outputs are configured to
2.4-V p2p or 1-V p2p signaling mode based on configuration chosen for PHY and auto
negotiation with Link Partner.
RX+
RX-
TX-
5
6
7
A
A
A
RX+, RX- : These differential inputs are automatically configured to accept 2.4-V p2p or 1-V
p2p signaling mode based on configuration chosen for PHY.
TX+, TX- : Differential Transmit Output (PMD): These differential outputs are configured to
2.4-V p2p or 1-V p2p signaling mode based on configuration chosen for PHY and auto
negotiation with Link Partner.
GPIO2
XO
8
9
Strap
GPIO: This pin can be configured for multiple configuration thru register configuration. It has
mandatory PU or PD strap. Refer to Straps sections for details.
A
A
Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin should be left
floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn
10
Crystal / Oscillator Input Clock
MII, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock
RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock
MDIO
MDC
11
12
Management Data I/O: Bi-directional management data signal that may be source by the
management station or the PHY. This pin requires an external pull of 2.2kΩ - 4.0 kΩ.
Management Data Clock: Synchronous clock to the MDIO serial management input/output
data. This clock may be asynchronous to the MAC transmit and receive clocks. The
maximum clock rate is 1.75 MHz.
RX_D3
RX_D2
RX_D1
RX_D0
13
14
15
16
Strap
Strap
Strap
Strap
Receive Data: Symbols received on the cable are decoded and presented on these pins
synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted.
A nibble RX_D[3:0] is received in MII modes. 2-bits RX_D[1:0] is received in RMII mode.
I/O Supply : 3.3 V/2.5 V/1.8 V. For decoupling capacitor requirements, refer to Application
section of data sheet.
VDDIO
17
Power
Receive Data Valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode
and on RX_D[1:0] for RMII mode. In RMII mode, this pin acts as CRS_DV and combines the
RMII arrier and Receive Data Valid indications. This pin can be configured to RX_DV to
enable RMII repeater mode using strap or register configuration.
RX_DV/
CRS_DV
18
Strap
RGMII mode: RGMII Receive Control: RX_CTRL combines receive data valid and receive
error signals. RX_DV is presented on the rising edge of RX_CLK and RX_ER on the falling
edge of RX_CLK.
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PIN
TYPE
DESCRIPTION
NAME
NO
MII Receive Clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps
speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received
data stream.
RX_CLK/
50MHz_RMII
_M
19
In RMII master mode, this provides 50-MHz reference clock. In RMII slave mode, this pin is
not used and remains Input/PD.
RGMII Receive Clock: RGMII Receive Clock provides a 2.5-MHz reference clock for 10-Mbps
speed, which is derived from the receive data stream.
Receive Error: This pin indicates that an error symbol has been detected within a received
packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the
rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising
edge of the reference clock. RX_ERR is asserted high for every reception error, including
errors during Idle.
RX_ER
20
21
22
Strap
Unused in RGMII mode.
Power Down(Default)/Interrupt: The default function of this pin is power down. Register
access is required to configure this pin as an interrupt. In power down function, an active low
signal on this pin places the device in power down mode. When this pin is configured as an
interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-
drain output with a weak internal pullup (9.5 kΩ). Some applications may require an external
PU resistor.
PWDN/INT
TX_CLK
MII Transmit Clock: MII Transmit Clock provides a 25-MHz reference clock for 100-Mbps
speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock
has constant phase referenced to the reference clock. Applications requiring such constant
phase may use this feature. Unused in RMII mode.
RGMII Transmit Clock: The clock is sourced from the MAC layer to the PHY. When operating
at 10-Mbps speed, this clock must be 2.5-MHz.
Transmit Enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the
presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode.
TX_EN is an active high signal.
TX_EN
23
RGMII Transmit Control: TX_CTRL combines transmit enable and transmit error signals.
TX_EN is presented on the rising edge of TX_CLK and TX_ER on the falling edge of
TX_CLK.
TX_D0
TX_D1
TX_D2
TX_D3
24
25
26
27
Transmit Data: In MII mode, the transmit data nibble received from the MAC is synchronous
to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] received from the MAC is
synchronous to the rising edge of the reference clock.
LED_2/
TX_ER
This pin acts as LED_2 by default. It can be configured as GPIO or TX_ER as well. The LED
is ON when link is negotiated for 10M (short reach). LED remains OFF otherwise.
28
29
Strap
Strap
LED : Activity Indication LED indicates transmit and receive activity in addition to the status of
the link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is
active. This pin can also act as GPIO using register configuration.
LED_0
This pin provides Reference CLKOUT of 25 MHz as default to clock other module on the
board. The pin can be configured to act as LED_1 using strap or register configuration. The
LED is ON when link is negotiated for 10M (long reach). The LED remains OFF otherwise.
When configured for CLK_OUT, reference clock is not affected by reset and switches off only
at IEEE Power Down.
CLKOUT/
LED_1
30
RST_N: This pin is an active low reset input. Asserting this pin low for at least 25μs will force
a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all
the internal registers of the PHY to default value.
RST_N
GPIO1
31
32
Strap
General Purpose Input or Output.
Table 5-1. Internal PU/PD in various states
Active State
( MII Mode)
Active State ( RMII
Master Mode)
Active State ( RMII Slave
Mode)
Pin #
Reset State
Active State (RGMII Mode)
1
A
A
A
A
A
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Table 5-1. Internal PU/PD in various states (continued)
Active State
( MII Mode)
Active State ( RMII
Master Mode)
Active State ( RMII Slave
Mode)
Pin #
Reset State
Active State (RGMII Mode)
2
3
4
5
6
7
8
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I,PD
I,PD
I,PD
I,PD
I,PD
9
A
A
A
A
A
A
A
A
A
A
10
11
12
13
IO
I
IO
I
IO
I
IO
I
IO
I
I,PD
O,Hi-Z
I,PD
I,PD
O,Hi-Z
14
I,PD
O,Hi-Z
I,PD
I,PD
O,Hi-Z
15
16
17
18
19
20
I,PD
I,PD
A
O,Hi-Z
O,Hi-Z
A
O,Hi-Z
O,Hi-Z
A
O,Hi-Z
O,Hi-Z
A
O,Hi-Z
O,Hi-Z
A
I,PD
I,PD
I,PD
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
I,PD
I,PU-9.5KΩ/
OPEN
DRAIN
I,PU-9.5KΩ/
OPEN DRAIN
I,PU-9.5KΩ/OPEN
DRAIN
21
I,PU-9.5KΩ/OPEN DRAIN
I,PU-9.5KΩ/OPEN DRAIN
22
23
24
25
26
27
28
29
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
O,Hi-Z
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
I,PD
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
I,PD(Only at
POR)
30
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
31
32
I,PU
I,PD
I,PU
I,PU
I,PU
I,PU
O,Hi-Z
O,Hi-Z
O,Hi-Z
O,Hi-Z
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
1.4
4
UNIT
V
DVDD 1.0
VDDA 1.8
V
VDDA 3.3
4
V
Supply voltage
VDDIO (3.3)
4
V
VDDIO (2.5)
VDDIO (1.8)
3
V
2.1
4
V
Pins
Pins
MDI (Tx+, Tx-, Rx+, Rx-)
V
VDDIO +
0.3
MAC Interface, MDIO, MDC, GPIO, LED
-0.3
-0.3
V
VDDIO +
0.3
Pins
Pins
INT/PWDN, RESET
XI Oscillator Input
V
V
-0.3 VDDIO+0.3
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
Parameter
VALUE UNIT
Human-body model (HBM),
V(ESD) V(ESD) Electrostatic discharge
V(ESD) V(ESD) Electrostatic discharge
All pins except MDI
MDI pins
+/-2000
+/-6000
V
V
perANSI/ESDA/JEDEC JS-001(1)
Human-body model (HBM),
perANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per
JEDEC specification JESD22-
C101(2)
V(ESD) V(ESD) Electrostatic discharge
All Pins
+/-500
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing
withless than 500 V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing
withless than 250 V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
MIN
0.90
1.62
3.0
NOM
1.0
1.8
3.3
1.8
2.5
3.3
MAX
1.1
UNIT
DVDD 1.0 Digital Supply
VDDA 1.8 Analog Supply
VDDA 3.3 Analog Supply
V
V
V
1.98
3.6
Digital Supply Voltage, 1.8V operation
Digital Supply Voltage, 2.5V operation
Digital Supply Voltage, 3.3V operation
Operating Ambient Temperature
1.62
2.25
3.0
1.98
2.75
3.6
VDDIO
V
TA
-40
105
℃
TX_D[0:3],RX_D[0:3], TX_CLK, RX_CLK, TX_EN, RX_DV, RX_ER, MDIO, VDDIO-10
VDDIO
+10%
Pins
VDDIO
VDDIO
VDDIO
V
MDC, LED0, LED1, LED2
%
VDDIO-10
%
VDDIO
+10%
Pins
Pins
INT/PWDN, RESET_N
V
V
VDDIO-10
%
VDDIO
+10%
XI Osclliator Input
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over operating free-air temperature range (unless otherwise noted)
Parameter
MIN
NOM
MAX
UNIT
VDDIO-10
%
VDDIO
+10%
Pins
GPIO
VDDIO
V
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6.4 Thermal Information
THERMAL METRIC(1)
32PIN QFN
52
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJC(bot)
RθJB
42
31.5
2.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
31.4
11.9
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IEEE Tx CONFORMANCE (10BaseT1L External Terminations)
1V p2p
Vod : Output Differential Voltage
Vod : Output Differential Voltage
0.85
2.04
1.0
2.4
1.05
2.56
V
V
2.4-V
p2p
POWER CONSUMPTION (Dual Analog Supply, 1-V p2p mode)
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
DVDD1.0
AVDD1.8
5
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
18
DVDD1.0
AVDD1.8
Reset
Reset
3
5
mA
mA
POWER CONSUMPTION (Dual Analog Supply, 2.4V p2p mode)
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
DVDD1.0
5
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
AVDD3.3
26.5
Power Consumption VDDIO (MII Interface)
VDDIO1.8
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
4
5
6
mA
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO2.5
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO3.3
Power Consumption VDDIO (RMII Master Interface)
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO1.8
8.5
12
16
mA
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO2.5
VDDIO3.3
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Consumption VDDIO (RMII Slave Interface)
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO1.8
VDDIO2.5
4
5
6
mA
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO3.3
Power Consumption VDDIO ( RMII Master 5 MHz)
VDDIO1.8
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
4
5
6
mA
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO2.5
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO3.3
Power Consumption VDDIO (RGMII Interface)
VDDIO1.8
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
4
5
6
mA
mA
mA
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO2.5
100% Traffic, Random Size : 64 to 1512
Bytes, Random Content
VDDIO3.3
BOOTSTRAP DC CHARACTERISTICS (2 Level)
VIH_3v3
VIL_3v3
VIH_2v5
VIL_2v5
VIH_1v8
VIL_1v8
High Level Bootstrap Threshold : 3V3
Low Level Bootstrap Threshold : 3V3
High Level Bootstrap Threshold: 2V5
Low Level Bootstrap Threshold : 2V5
High Level Bootstrap Threshold:1V8
Low Level Bootstrap Threshold :1V8
1.3
1.3
1.3
V
V
V
V
V
V
0.6
0.6
0.6
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX
UNIT
IO CHARACTERISTICS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
VDDIO = 3.3V ±10%
V
V
V
V
V
V
V
V
VDDIO = 3.3V ±10%
0.8
0.4
0.7
0.4
VOH
VOL
VIH
VIL
IOH = -2mA, VDDIO = 3.3V ±10%
IOL = 2mA, VDDIO = 3.3V ±10%
VDDIO = 2.5V ±10%
2.4
1.7
2
VDDIO = 2.5V ±10%
VOH
VOL
IOH = -2mA, VDDIO = 2.5V ±10%
IOL = 2mA, VDDIO = 2.5V ±10%
0.65*VD
DIO
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VDDIO = 1.8V ±10%
V
V
V
0.35*VD
DIO
VDDIO = 1.8V ±10%
VDDIO-0
.45
VOH
IOH = -2mA, VDDIO = 1.8V ±10%
VOL
Low Level Output Voltage
Input High Current
IOL = 2mA, VDDIO = 1.8V ±10%
TA = -40℃ to 105℃, VIN=VDDIO
TA = -40℃ to 105℃, VIN=GND
0.45
V
µA
µA
kΩ
kΩ
V
IIH
15
15
9
IIL
Input Low Current
Rpulldn
Rpullup
XI VIH
XI VIL
CIN
Internal Pull Down Resistor
Internal Pull Up Resistor
High Level Input Voltage
Low Level Input Voltage
Input Capacitance XI
9
1.2
0.6
V
1
5
pF
Input Capacitance INPUT PINS
(TX_D[3:0], TX_EN, TX_CLK, MDC)
CIN
pF
COUT
COUT
Output Capacitance XO
1
5
pF
pF
Output Capacitance OUTPUT PINS
Integrated MAC Series Termination
Resistor
Rseries
RX_D[3:0], RX_ER, RX_DV, RX_CLK
50
8
Ω
LED drive strength
mA
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6.6 Timing Requirements
TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
POWER-UP TIMING (Single and Dual supply mode)
Supply ramp rate: For all supplies (DVDD, VDDA, VDDIO)
(20% to 80%)
0.2
40
200
60
ms
ms
ms
ms
Supply ramp delay offset: For all supplies (DVDD, VDDA,
VDDIO)
First Supply ramp to
last supply ramp
T1
T2
Last Supply power up to RESET_N High
Powerup to SMI ready: Post power-up stabilization time prior to
MDC preamble for register access
60
Powerup to Strap latchin: Hardware configuration pins
transition to output drivers
T3
60
ms
V
Pedestal Voltage on DVDD, VDDA, VDDIO before Power
Ramp
0.3
RESET TIMING
Reset to SMI ready: Post reset stabilization time prior to MDC
preamble for register access
T1
30
10
us
RESET PULSE Width: Miminum Reset pulse width to be able
to reset
T3
T5
us
us
Reset to MAC clock (MII RX_CLK)
995
200
MII 10M Timings
10M TX_CLK High / Low Time
190
25
210
ns
ns
ns
ns
ns
TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK
TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK
RX_CLK High / Low Time
0
160
100
200
240
300
RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising
RGMII OUTPUT TIMING (10M)
TskewT
TskewR
TskewR
Tcyc
Data to Clock Output Skew (Non-Delay Mode)
5 pF Load
-2
30
2
ns
ns
ns
ns
%
Data to Clock Output Setup (Integrated Delay)
Data to Clock Output Hold \((Integrated Delay)
Clock Cycle Duration
30
-360
45
400
50
440
55
3
Duty Cycle
Rise / Fall Time ( 20% to 80%)
ns
RGMII INPUT TIMING (10M)
TskewR
TsetupR
TholdR
TX data to clock input skew (Integrated Delay Mode)
-4
40
40
4
ns
ns
ns
TX data to clock input setup (Non-Delay Mode)
TX clock to data input hold (Non-Delay Mode)
RMII MASTER TIMING
RMII Master Clock Period
20
ns
%
RMII Master Clock Duty Cycle
35
4
65
14
TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock
TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock
25 pF Load
25 pF Load
ns
ns
2
RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock
rising edge
25 pF Load
4
10
20
ns
RMII SLAVE TIMING
Input Reference Clock Period
ns
%
Reference Clock Duty Cycle
35
4
65
14
TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising
TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising
RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising
ns
ns
ns
2
4
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TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
RMII Master Timing ( 5 MHz)
Frequency
5
MHz
%
Duty Cycle
40
10
10
50
60
TX_D[3:0], TX_ER, TX_EN setup to Master Clock
TX_D[3:0], TX_ER, TX_EN from Master Clock
RX_D[3:0], RX_ER, RX_DV Delay from 5 MHz Clock
ns
ns
100
150
10
ns
SMI TIMING
T1
T2
T3
T4
MDC to MDIO (Output) Delay Time
MDIO (Input) to MDC Setup Time
MDIO (Input) to MDC Hold Time
MDC Frequency
0
10
10
ns
ns
ns
1
1.75
MHz
OUTPUT CLOCK TIMING (25MHz clockout)
Frequency (PPM)
Duty Cycle
-100
40
100
60
-
%
Rise Time
5000
5000
ps
Fall Time
ps
Frequency
25
MHz
Output Clock 50 MHz timing
Frequency (PPM)
Duty Cycle
-50
35
50
65
ppm
%
Rise time
5000
5000
ps
Fall Time
ps
25MHz INPUT CLOCK tolerance
Frequency Tolerance
Rise / Fall Time (10%-90%)
Duty Cycle
-100
40
+100
8
ppm
ns
60
%
50MHz Input Clock Tolerance
Frequency Tolerance
Rise / Fall Time (10%-90%)
Duty Cycle
-100
40
+100
8
ppm
ns
60
%
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6.7 Timing Diagrams
T4
VVDDIO
0.3V
0V
T4
T1
VVDDA
0.3V
0V
T4
T1
VDVDD (Optional)
0.3V
0V
XI
Clock shall be available at Power
Ramp
Hardware
RESET_N
tT2t
MDC
`
Figure 6-1. Power-Up Timing
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VVDD
XI
tT1
Hardware
RESET_N
32 Clocks
tT2
MDC
DME
Figure 6-2. Reset Timing
MDC
tT4t
tT1t
MDIO
(output)
MDC
tT2t
tT3t
MDIO
(input)
Valid Data
Figure 6-3. Serial Management Timing
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tT1t
tT1t
TX_CLK
tT2t
tT3t
TX_D [3:0]
TX_EN
Valid Data
Figure 6-4. 10-Mbps MII Transmit Timing
tT1t
tT1t
RX_CLK
tT2t
RX_D [3:0]
RX_DV
RX_ER
Valid Data
Figure 6-5. 10-Mbps MII Receive Timing
tT1t
XI
Master Clock
tT2t
tT3t
TX_D[1:0]
TX_EN
Valid Data
Figure 6-6. RMII Transmit Timing
tT1t
XI
RX_CLK
Master Clock
T4
RX_D[1:0]
CRS_DV
RX_DV
Valid Data
RX_ER
Figure 6-7. RMII Receive Timing
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7 Detailed Description
7.1 Overview
The DP83TD510E is a physical-layer transceiver compliant to IEEE 802.3cg 10BaseT1L standards. The PHY
use low noise coupled signal processing reciever architecture to offer longer cable reach along with ultra-low
power consumption. The device supports both 2.4-V p2p and 1-V p2p out put voltage as defined by IEEE
802.3cg 10Base-T1L specfications. It supports mulitple MAC interface (MII, Reduced Media Independent
Interface (RMII), RGMII and low power Reduced MII) for direct connection to Media Access Controller (MAC).
The device also supports back-to-back RMII mode in unmanaged mode to provide range extension and repeater
functionality.
The device is designed to operate from a single 3.3-V power supply and has integrated LDO to provide the
voltage rails required for internal blocks. The device has an option to feed digital power externally to achieve
lowest power consumption. The device allows I/O voltage interfaces for 3.3 V, 2.5 V or 1.8 V. Automatic supply
configuration within the DP83TD510E allows for any combination of VDDIO supply without the need for
additional configuration settings.
The DP83TD510E Diagonstic Tool includes TDR (Time Domain Reflectometry), ALCD (Active Link Cable
Diagnostics), SQI (Signal Quality Indicator), mulitple Loopbacks and Integrated PRBS Packet Generator to ease
debugging during development and detecting faulty conditions in field.
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7.2 Functional Block Diagram
RMII Option
Combined MII/RGMII
Serial
Management
MII / RMII Interface
TX
Data
RX
Data
TX_CLK
RX_CLK
MII
Registers
Auto-Negotiation
Transmit Block
Receive Block
Clock
Generation
DAC
ADC
BIST
LED
Driver
Cable Diagnostics
Reference
Clock
TX+
LEDs
RX+ TX- RX-
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7.3 Feature Description
7.3.1 Auto-Negotiation (Speed Selection)
Auto-Negotiation provides a mechanism for exchanging configuration information between the two ends of a link
segment. The DP83TD510E supports auto-negotiation for Low Speed Modes (LSM) as defined in IEEE 802.3cg
specification for 10BaseT1L. Auto-negotiation ensures that the highest common speed is selected based on the
advertised abilities of the link partner and the local device.
7.3.2 RMII Repeater Mode
The DP83TD510E provides an option to enable repeater mode functionality to extend the cable reach. Two
DP83TD510E can be connected in back to back mode without any external configuration. A hardware strap is
provided to configure the CRS_DV pin of RMII interface to RX_DV pin for back to back operation. Refer to
Figure 7-1 for the RMII pin connection to enable repeater mode on the DP83TD510E.
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( RMII Slave Mode)
( RMII Slave Mode)
RX_DV
TX_EN
RX_D1
RX_D0
TX_D1
TX_D0
TX_EN
RX_DV
RX_D0
RX_D1
TX_D0
TX_D1
XI
XI
XI 50 MHz
Figure 7-1. RMII Repeater Mode
7.3.3 Clock Output
The DP83TD510E has several clock output configuration options. An external crystal or CMOS-level oscillator
provides the stimulus for the internal PHY reference clock. The local reference clock acts as the central source
for all clocking within the device.
All clock configuration options are enabled using the IO MUX GPIO Control Register TBD
Clock options supported by the DP83TD510E include:
•
•
•
•
MAC IF clock
XI clock
Free-running clock
Recovered clock
7.3.4 Media Independent Interface (MII)
The Media Independent Interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the
MAC. The MII is fully compliant with IEEE 802.3-2002 clause 22.
The MII signals are summarized in Table 7-1.
Table 7-1. MII Signals
FUNCTION
PINS
TX_D[3:0]
RX_D[3:0]
TX_EN
Data Signals
Transmit and Receive Signals
RX_DV
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TX_CLK
TX_EN
TX_D[3:0]
RX_CLK
RX_DV
PHY
MAC
RX_ER
RX_D[3:0]
Figure 7-2. MII Signaling
Additionally, the MII interface includes the carrier sense signal (CRS), as well as a collision detect signal (COL).
The CRS signal asserts to indicate the reception or transmission of data. The COL signal asserts as an
indication of a collision which can occur during half-duplex mode when both transmit and receive operations
occur simultaneously.
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7.3.5 Reduced Media Independent Interface (RMII)
The DP83TD510E incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII
specification v1.2. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3
MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on
either side of the MII, but can be implemented in the absence of an MII. The DP83TD510E offers two types of
RMII operations: RMII Slave and RMII Master. In RMII Master operation, the DP83TD510E operates off of either
a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins. A
50-MHz output clock referenced from DP83TD510E can be connected to the MAC. In RMII Slave operation, the
DP83TD510E operates off of a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same
clock as the MAC. Alternatively, in RMII Slave mode, the PHY can run from a 50-MHz clock provided by the Host
MAC.
The RMII specification has the following characteristics:
•
•
•
Single clock reference sourced from the MAC to PHY (or from an external source)
Independent 2-bit wide transmit and receive data paths
Usage of CMOS signal levels, the same levels as the MII interface
In this mode, data transfers are two bits for every clock cycle using the internal 50-MHz reference clock for both
transmit and receive paths.
The RMII signals are summarized inTable 7-2.
Table 7-2. RMII Signals
FUNCTION
Receive Data Lines
PINS
TX_D[1:0]
RX_D[1:0]
TX_EN
Transmit Data Lines
Receive Control Signal
Transmit Control Signal
CRS_DV
TX_EN
TX_D[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER (optional)
RX_D[1:0]
PHY
MAC
CRS_DV
XI
(pin 23)
50-MHz Reference
Clock
Figure 7-3. RMII Slave Signaling
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TX_EN
TX_D[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER (optional)
RX_D[1:0]
PHY
MAC
CRS_DV
50-MHz Reference Clock
RX_D3
(pin 1)
25-MHz Reference
Clock
Figure 7-4. RMII Master Signaling
Data on TX_D[1:0] are latched at the PHY with reference to the clock edges on the XI pin. Data on RX_D[1:0]
are latched at the MAC with reference to the same clock edges on the XI pin.
In addition, CRX_DV can be configured as RX_DV signal. It allows a simpler method of recovering receive data
without the need to separate RX_DV from the CRS_DV indication.
7.3.6 RMII Low Power 5-MHz Mode
DP83TD510E supports a new MAC Mode called RMII Master Low Power Mode. The interface is similar to the
RMII master mode but runs at 5 MHz resulting in power dissipation savings. DP83TD510E offers 5-MHz clock
output and data is aligned to this clock. An application can use the same pin map as RMII for this mode.
7.3.7 RGMI Interface
DP83TD510E offers RGMII mode which runs at 2.5 MHz. The timing specifications are relaxed compared to
RGMII at 125 MHz. Refer to timing sections on timing specifications for this mode.
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7.3.8 Serial Management Interface
The Serial Management Interface provides access to the DP83TD510E internal register space for status
information and configuration. The SMI is compatible with IEEE 802.3 clause 22 and clause 45. The
implemented register set consists of the registers required by IEEE 802.3 plus several others to provide
additional visibility and controllability of the DP83TD510E.
The SMI includes the management clock (MDC) and the management input/output data pin (MDIO). MDC is
sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of
25 MHz. MDC is not expected to be continuous and can be turned off by the external management entity when
the bus is idle.
MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the
rising edge of the MDC. The MDIO pin requires a pullup resistor (2.2 kΩ) which pulls MDIO high during IDLE and
turnaround.
Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, during power up or hardware
reset, the DP83TD510E latches the Phy_Address[3:0] configuration pins to determine its address.
The management entity must not start an SMI transaction in the first cycle after power up or hardware reset. To
maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after reset is de-asserted. In
normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field,
thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific).
The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern
ensures that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time
inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no
device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83TD510E drives
the MDIO with a zero for the second bit of turnaround and follows this with the required data.
For write transactions, the station-management entity writes data to the addressed DP83TD510E, thus
eliminating the requirement for MDIO Turnaround. The turnaround time is filled by the management entity by
inserting <10>.
Table 7-3. SMI Protocol
SMI PROTOCOL
Read Operation
Write Operation
<idle><start><op code><PHY address><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><XXXX XXXX XXXX XXXX><idle>
<idle><01><01><AAAAA><RRRRR><10><XXXX XXXX XXXX XXXX><idle>
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7.3.9 Loopback Modes
There are several loopback options within the DP83TD510E that test and verify various functional blocks within
the PHY. Enabling loopback modes allow for in-circuit testing of the digital and analog data paths. The
DP83TD510E may be configured to any one of the Near-End Loopback modes or to the Far-End (reverse)
Loopback mode. MII Loopback is configured using the Control Register (BMCR, address TBD). All other
loopback modes are enabled using the BIST Control Register (BISCR, address TBD).
Reverse
Loopback
PCS
Loopback
Analog
Loopback
MAC
MII
Loopback
Digital
Loopback
Figure 7-5. Loopback Test Modes
7.3.9.1 MII Loopback
MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications
between the MAC and the PHY. When in MII Loopback, data transmitted from a connected MAC on the TX path
is internally looped back in the DP83TD510E to the RX pins where it can be checked by the MAC.
7.3.9.2 PCS Loopback
PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS
Loopback.
7.3.9.3 Digital Loopback
Digital Loopback includes the entire digital transmit and receive paths. Data is looped back prior to the analog
circuitry.
Digital Loopback is enabled by setting bit[2] in the BISCR.
7.3.9.4 Analog Loopback
Analog Signals can be looped back after the analog front-end. Detials: TBD.
7.3.9.5 Far-End (Reverse) Loopback
Far-End (Reverse) loopback is a special test mode to allow PHY testing with a link partner. In this mode, data
that is received from the link partner passes through the PHY’s receiver, is looped back at the MAC interface and
then transmitted back to the link partner. While in Reverse Loopback mode, all data signals that come from the
MAC are ignored.
7.3.10 BIST Configurations
The DP83TD510E incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit
testing and diagnostics. The BIST circuit can be used to test the integrity of transmit and receive data paths. The
BIST can be performed using both internal loopbacks (digital or analog) or external loopback using a cable
fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet
Gap (IPG) on the lines. The BIST allows full control of the packet lengths and the IPG.
7.4 Device Functional Modes
DP83TD510E can be used in MII Mode, RMII Master Mode and Slave Mode. Refer to RMII section for
connection diagram.
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7.4.1 Straps Configuration
The DP83TD510E uses many of the functional pins as strap options to place the device into specific modes of
operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap
options are internally reloaded from the values sampled at power up or hard reset. The strap option pin
assignments are defined below. Configuration of the device may be done through the strap pins or through the
management register interface. A pullup resistor or a pulldown resistor of suggested values may be used to set
the voltage ratio of the strap pin input and the supply to select one of the possible selected modes. The MAC
interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs are implemented on these
pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies depending on what voltage was
selected for I/O. All strap pins have two levels.
Internal PU pins
Internal PD pins
VDDIO
VDDIO
Rhi
10 kΩ
25%
10 kΩ
25%
Rlo
Figure 7-6. Strap Circuit
Table 7-4. 2-Level Strap Resistor Ratio
IDEAL RESISTORS
MODE
Rhi (kΩ)
OPEN
2.49
Rlo (kΩ)
2.49
0
1
OPEN
7.4.1.1 Straps for PHY Address
Table 7-5. PHY Address Strap Table
PIN NAME
STRAP NAME
PIN #
DEFAULT
PHY_ADD0
GPIO1
Strap9
32
0
MODE 0
0
MODE 1
1
PHY_ADD1
RX_ERR
RX_D0
RX_D3
Strap6
Strap4
Strap1
20
16
13
0
0
0
MODE 0
MODE 1
0
1
PHY_ADD2
MODE 0
MODE 1
0
1
PHY_ADD3
MODE 0
MODE 1
0
1
PHY Address strap is 4 bit strap on pin 13, 16, 20 and 32. It shall be read as [3:2:1:0] respectively. Default PHY Address is 0000.
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Table 7-6. Reach Selection Strap
PIN NAME
STRAP NAME
PIN #
DEFAULT
This Strap defines the voltage level
requested by PHY during auto
negotiation. It is reflected in bit 12 of
0x20E. While using Force mode for
Linkup, the strap controls the output
voltage and reflects in bit 12 of 0x18F6
0
1
LED_2
Strap7
28
0
0 : 1-V p2p
1: 2.4-V p2p
Table 7-7. MAC Mode Strap Table
Strap
3
PIN NAME
STRAP NAME
PIN #
DEFAULT
Strap8
0
0
1
1
0
1
0
1
MII (default)
RMII Master
Reserved
RX_D1
Strap3
Strap8
15
0
LED_0
29
0
RMII Slave
Table 7-8. RMII MAC Mode Strap Table
PIN NAME
STRAP NAME
PIN #
DEFAULT
CRS_DV/RX_DV Pin 18 is configured as
CRS_DV (default)
0
1
RX_D2
Strap2
14
0
CRS_DV/RX_DV Pin 18 is configured as
RX_DV (For RMII Repeater Mode)
Table 7-9. Terminations Selection
PIN NAME
STRAP NAME
PIN #
DEFAULT
Receiver with tapping at 50 Ω
(Recommended)
0
1
GPIO2
Strap10
8
Mandatory PU/PD
Receiver tapping at < 40 Ω
Table 7-10. Clockout/LED_1
PIN NAME
STRAP NAME
PIN #
DEFAULT
0
1
Clockout 25 M( default)
LED1
RX_DV/CRS_DV
Strap5
18
0
7.5 Programming
DP83TD510E provides an IEEE defined register set for programming and status. It also provides an additional
register set to configure other features not supported thru IEEE registers.
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7.6 Register Maps
7.6.1 MMD Register Address Map
Table 7-11. MMD Register Map Address Table
Register Address Range
0x1000 to 0x18F8
MMD
Example Usage
0x1
MMD=0x1, Address=0x08F8
MMD=0x3, Address=0x08E7
MMD=07, Address=0x20F
MMD=0x1F, Address=0x0000
0x3000 to 0x38E7
0x3
0x200 to 0x20F
0x7
0x0000 to 0x0130, 0x0300-0x0E01
0x1F
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
When using the device for Ethernet applications, it is necessary to meet certain requirements for normal
operation. The following subsections are intended to assist in appropriate component selection and required
circuit connections.
8.2 Typical Applications
Figure 8-1 shows a typical application for the DP83TD510E.
Vin 3V3/1V8
10Base-T1L
DP83TD510
MII/RMII
IEEE 802.3cg Single Pair
Ethernet
PHY
MAC
Connector
25-MHz / 50-MHz
Clock Source
Status
LEDs
Figure 8-1. Typical DP83TD510E Application
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8.2.1 Termination Circuit
DP83TD510E is expected to be used in Intrinsic Safe and non Intrinsic Safe Applications. Please refer to
appropriate termination circuit based on the application needs, see Figure 8-2 .
Note
Termination circuit and passive values are initial estimates and subject to change
8.2.1.1 Termination Circuit for Intrinsic Safe Applications
TRD_P
RTX2
CMC
C3 nF
C1 nF
C5
RTX1
RRX1
Optional for Improved EMC
Tx+
Rx+
Rt1
DP83TD510
RRX2
RTX3
Rd1
Rx-
Rd2
Rt2
Tx-
C4 nF
C2 nF
Cd
Rd3
TRD_N
CMC
C6
RTX4
Copyright © 2020, Texas Instruments Incorporated
Figure 8-2. Termination Circuit for Intrinsic Safe Applications
Table 8-1. Termination Circuit Component Value for Intrinsic Safe Applications
Applications
1v p2p Intrinsic Safe Config 1
1v p2p Intrinsic Safe Config 2
1
2
RTX1, RTX3
26.5
50
RTX2, RTX4 (Ω)
23.5
0
3
RRX1, RRX2 (Ω)
2K
2K
4
Rt1(Ω)
Rt2(Ω)
Rd1(Ω)
Rd2(Ω)
Rd3(Ω)
C1
NC
0
5
NC
0
6
1K
1K
7
1K
1K
8
160K
160K
9
230 nF
230 nF
10
11
12
13
14
15
C2
230 nF
230 nF
C3
5 nF
5 nF
NC
NC
C4
C5
100 pF < C < 400 pF ( default: 100 pF
100 pF < C < 400 pF ( default: 100 pF
0.01 uF
100 pF < C < 400 pF ( default: 100 pF
100 pF < C < 400 pF ( default: 100 pF
0.01 uF
C6
Cd
Please ensure over all impedance on the Transmitter shall be 50Ω. If additional components on path adding the
impedance, it shall be compensated by reducing Rtx1/Rtx3.
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8.2.1.2 Components Range for Power Coupling/Decoupling
Below table provides recommended component ranges for Power/Data decoupling network
Table 8-2. Recommended Components Range for Power Coupling/Decoupling
Components
Range
1
2
3
Cap of ESD diode between MDI lines (Surge protection)
Cap of TVS Diode (MDI line to ground)*
< 100 pF ( Differential Cap)
< 75 pF
Cap of Clamping Diodes (parallel to power coupling inductor)
< 50 pF
•
•
Inductance 500 uH < L <1.5
mH,
4
5
Power coupling inductor
Cap of Rectifier Diodes
DC Resistance < 200 mΩ
<50 pF
8.2.1.3 Termination Circuit for Non-Intrinsic Safe Applications
Following termination circuit is recommended for application in non intrinsic safe application like in Building
Automation, Factory Automation etc
230 nF
50Q
TRD_P
CMC
CMC
Tx+
Rx+
Optional for
Improved EMC
2KQ
C5
DP83TD510
2KQ
50Q
Rd1
Rd2
Rx-
230 nF
TRD_N
Cd
Tx-
Rd3
C6
Copyright © 2020, Texas Instruments Incorporated
Figure 8-3. Termination Circuit for Non-Intrinsic Safe Applications
8.2.1.4 CMC Specifications
Table 8-3. CMC Specifications
Parameters
Inductance
Range
450 uH
< 500 nH
< 200 mΩ
Leakage Inductance
DC Resistance
8.2.2 Design Requirements
The design requirements for the DP83TD510E are:
1. AVD Supply = 3.3 V
2. VDDIO Supply = 3.3 V or 1.8 V
3. Reference Clock Input = 25 MHz or 50 MHz (RMII Slave)
8.2.2.1 Clock Requirements
The DP83TD510E supports an external CMOS-level oscillator source or an internal oscillator with an external
crystal.
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8.2.2.1.1 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The
amplitude of the oscillator should be a nominal voltage of VDDIO.
8.2.2.1.2 Crystal
The use of a 25-MHz, parallel resonant, 20-pF load crystal is recommended if operating with a crystal. A typical
connection diagram is shown below for a crystal resonator circuit. The load capacitor values will vary with the
crystal vendors; check with the vendor for the recommended loads.
XI
(pin 23)
XO
(pin 22)
R
1
C
L1
C
L2
Figure 8-4. Crystal Oscillator Circuit
Table 8-4. 25-MHz Crystal Specification
PARAMETER
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
25
MHz
Frequency Tolerance
Including all parameters
(Temperature, aging etc)
-100
100 ppm
Load Capacitance
ESR
15
50
30
pF
150
Ohm
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9 Power Supply Recommendations
The DP83TD510E is capable of operating from Single Supply 3V3. It supports single supply operations from 1V8
for Short Reach ( 1v p2p) mode. It also supports Dual Supply Operations for Lowest Power Dissipation. It also
supports VDDIO to work at 3.3-V, 2.5-V or 1.8-V supply voltages PHY has capability to detect the power supply
levels automatically for both AVDD and VDDIO..
Single Power Supply Operations : Analog supply shall be powered by 3.3 V or 1.8 V. AVDD of 3V3 can support
both Long Reach ( 2.4-v p2p) and Short Reach( 1-v p2p).
Please note with AVDD 1.8 V, only Short Cable mode of 1-V p2p will be supported.
Appropriate straps shall be configured to ensure Auto Negotiation transmits the correct capabilities of the PHY.
The recommended power supply de-coupling network is shown below:
3.3-V or 2.5-V or
1.8-V Supply
VDDIO
Ferrite Bead
(Optional)
100 nF
10 nF
1 ꢀF
10 ꢀF
Ferrite Bead
(Optional)
3.3-V Supply or
1.8-V Supply
VDDA
10 ꢀF 1 ꢀF
100 nF 10 nF
CEXT
DVDD
0.01µF
Figure 9-1. DP83TD510E Single Power Supply Decoupling Recommendation
For Dual Supply Operations, digital voltage rail of 1.0 V externally shall be supplied seperately. This help reduce
the power consumption further of the DP83TD510E. See below connections for Dual Power Supply.
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3.3-V or 2.5-V or 1.8-V
Supply
VDDIO
Ferrite Bead
(Optional)
100 nF
10 nF
1 ꢀF
10 ꢀF
Ferrite Bead
(Optional)
3.3-V Supply or 1.8-V
Supply
VDDA
10 ꢀF
1 ꢀF
100 nF
10 nF
NC
CEXT
DVDD
Ferrite Bead
(Optional)
1.0V Supply
10 ꢀF
1 ꢀF
100 nF
10 nF
Figure 9-2. DP83TD510E Dual Supply Power Supply Decoupling Recommendation
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10 Layout
10.1 Layout Guidelines
10.1.1 Signal Traces
PCB traces are lossy and long traces can degrade signal quality. Keep traces as short as possible. Unless
mentioned otherwise, all signal traces must be 50-Ω single-ended impedance. Differential traces must 100-Ω
differential. Take care to ensure impedance is controlled throughout. Impedance discontinuities cause reflections
leading to emissions and signal integrity issues. Stubs should be avoided on all signal traces, especially
differential signal pairs.
Figure 10-1. Differential Signal Traces
Within the differential pairs, trace lengths should be run parallel to each other and matched in length. Matched
lengths minimize delay differences, avoiding an increase in common mode noise and emissions. Length
matching is also important for MAC interface connections. All RMII transmit signal traces should be length
matched to each other and all RMII receive signal traces should be length matched to each other.
Ideally, there should be no crossover or vias on signal path traces. Vias present impedance discontinuities and
should be minimized when possible. Route trace pairs on the same layer. Signals on different layers should not
cross each other without at least one return path plane between them. Differential pairs should always have a
constant coupling distance between them. For convenience and efficiency, TI recommends routing critical
signals first (that is, MDI differential pairs, reference clock, and MAC IF traces).
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10.1.2 Return Path
A general best practice is to have a solid return path beneath all MDI signal traces. This return path can be a
continuous ground or DC power plane. Reducing the width of the return path can potentially affect the
impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to
the width of the signal trace. Breaks in return path between the signal traces should be avoided at all cost. A
signal crossing a split plane may cause unpredictable return path currents and could impact signal quality and
result in emissions issues.
Figure 10-2. Differential Signal Pair and Plane Crossing
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10.1.3 Metal Pour
All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the
system, and there must be no metal between differential traces.
10.1.4 PCB Layer Stacking
To meet signal integrity and performance requirements, a minimum four-layer PCB is recommended. However, a
six-layer PCB should be used when possible.
Figure 10-3. Recommended Layer Stack-Up
10.2 Layout Example
Please refer DP83TD510E EVM for information regarding layout.
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11 Device and Documentation Support
11.1 Device Support
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Figure 12-1. DP83TD510E Package Drawing
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Figure 12-2. DP83TD510E Package Drawing
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Figure 12-3. DP83TD510E Package Drawing
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DP83TD510ERHBR
DP83TD510ERHBT
PDP83TD510ERHBR
PREVIEW
PREVIEW
ACTIVE
VQFN
VQFN
VQFN
RHB
RHB
RHB
32
32
32
3000
250
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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