DPA02257RGBR [TI]
适用于 DDR 内存终端的低输入电压、6A 同步降压 SWIFT™ 转换器 | RGB | 20 | -40 to 85;
| 型号： | DPA02257RGBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 DDR 内存终端的低输入电压、6A 同步降压 SWIFT™ 转换器 | RGB | 20 | -40 to 85 开关 双倍数据速率 控制器 开关式稳压器 开关式控制器 电源电路 转换器 开关式稳压器或控制器 |
| 文件： | 总25页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
3.3-V/5-V Input, 6-A, D-CAP+™ Mode Synchronous Step-Down Integrated FETs Converter
Check for Samples: TPS53317
1
FEATURES
APPLICATIONS
2
•
TI proprietary Integrated MOSFET and
Packaging Technology
External Tracking
Minimum External Components Count
1-V to 6-V Conversion Voltage
D-CAP+™ Mode Architecture
Supports All MLCC Output Capacitors and
SP/POSCAP
Selectable SKIP and Forced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable 600-kHz and 1-MHz Switching
Frequency
Selectable Overcurrent Limit (OCL)
Overvoltage Protection and Hiccup
Undervoltage Protection
Thermal Shutdown
Adjustable Output Voltage Ranging Between
0.6 V and 2 V
Small 3.5 mm × 4 mm, 20-Pin QFN Package
•
•
VTT Terminators
Low-Voltage Applications for 1-V to 6-V
Step-Down Rails
•
•
•
•
•
DESCRIPTION
The TPS53317 is a fully-integrated,synchronous buck
regulator employing D-CAP+™ technology. It is used
for rail step-downs from 1 V to 6 V where space is a
consideration, and an optimized component count is
required.
•
•
•
The TPS53317 features two switching frequency
settings (600 kHz and 1 MHz), synchronous operation
in skip (low ripple) mode, integrated droop support,
external tracking support, pre-bias startup, output soft
discharge, integrated bootstrap switch, power good
function, EN/Input UVLO protection, and both output
ceramic and SP/POS/AL capacitor support. It
supports supply and conversion voltages up to 6.0 V,
and output voltages adjustable from 0.6 V to 2.0 V. It
also provides external tracking support.
•
•
•
•
•
The TPS53317 is available in the 3.5 mm by 4 mm,
20-pin QFN package (Green RoHs compliant and Pb
free) with TI proprietary Integrated MOSFET and
packaging technology and is specified from -40°C to
85°C.
TPS53317
VIN
VIN
BST 16
SW
17 EN
VOUT
8
7
COMP PGOOD 19
PGOOD
VREF
PGND
VOUT 10
MODE 18
9
REFIN
PGNDGND
GND GND
5VIN
20 V5IN
GND
6
UDG-11105
PGND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
MINIMUM
QUANTITY
TA
PACKAGE(2)
ORDERING NUMBER
PINS
OUTPUT SUPPLY
ECO PLAN
TPS53317RGBR
TPS53317RGBT
20
20
Tape and reel
Mini reel
3000
Green (RoHS and
no Pb/Br)
Plastic QFN
(RGB)
-40°C to 85°C
250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
THERMAL INFORMATION
TPS53317
THERMAL METRIC(1)
RGB
20 PINS
35.5
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
39.6
12.4
°C/W
ψJT
0.5
ψJB
12.5
θJCbot
3.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
7.0
VIN, V5IN, BST (with respect to SW)
BST
–0.3
–0.3
–2
14.0
SW
Input voltage range
EN
7
V
7
–0.3
–0.3
–1
MODE, REFIN
VOUT
3.6
3.6
3.6
COMP, VREF
–0.3
–0.3
–0.3
–40
–55
Output voltage range
PGOOD
PGND
TJ
7.0
0.3
V
Junction temperature
Storage temperature
150
150
300
Tstg
˚C
˚C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VALUE
UNIT
MIN
–0.1
4.5
TYP
MAX
6.5
6.5
13.5
6.5
3.5
3.5
5.5
0.1
85
VIN, EN, BST (with respect fo SW)
V5IN
Input voltage range
BST
–0.1
–1.0
–0.1
–0.1
–0.1
–0.1
-40
V
SW
VOUT, MODE, REFIN
COMP, VREF
PGOOD
Output voltage range
V
PGND
Operating temperature range, TA
°C
Copyright © 2011, Texas Instruments Incorporated
3
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
MAX UNIT
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO
IVINSD
VIN shutdown current
5VIN supply voltage
5VIN supply current
5VIN shutdown current
V5IN UVLO
EN = 'LO'
0.02
5.0
5
6.5
2
µA
V
V5VIN
V5IN voltage range
4.5
I5VIN
EN =’HI’, V5IN supply current
EN = ‘LO’, V5IN shutdown current
Ramp up; EN = 'HI'
1.1
mA
µA
V
I5VINSD
0.2
7.0
4.50
VV5UVLO
VV5UVHYS
VVREFUVLO
VVREFUVHYS
VPOR5VFILT
4.20
4.37
440
1.8
V5IN UVLO hysteresis
REF UVLO(1)
REF UVLO hysteresis(1)
Falling hysteresis
mV
V
Rising edge of VREF, EN = 'HI'
100
2.3
mV
V
Reset
OVP latch is reset by V5IN falling below the reset threshold
1.5
3.1
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER
VOUTTOL
VOUT accuracy
VREFIN = 1 V, No droop
IVREF = 0 µA
–1%
1.98
0%
2.00
2.000
2.5
1%
2.02
VVREF
VREF
V
IVREF = 50 µA
1.975
2.025
IREFSNK
GM
VREF sink current
VVREF = 2.05 V
mA
mS
V
Transconductance
1.00
VCM
Common mode input voltage range(1)
Differential mode input voltage
COMP pin maximum sinking current
0
0
2
VDM
80
mV
µA
µA
mV
Ω
ICOMPSNK
ICOMPSRC
VOFFSET
RDSCH
f–3dbVL
VCOMP = 2 V, (VREFIN - VOUT) = 80 mV
80
-80
0
COMP pin maximum sourcing current VCOMP = 2 V
Input offset voltage
TA = 25°C
Output voltage discharge resistance
–3dB Frequency(1)
42
6.0
4.5
43
7.5
MHz
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING
Gain from the current of the low-side FET to PWM comparator
when PWM = "OFF"
ACSINT
Internal current sense gain
53
57 mV/A
IOCL
Positive overcurrent limit (valley)
Negative overcurrent limit (valley)
Zero crossing comp internal offset
7.6
–9.3
0
A
A
IOCL(neg)
VZXOFF
mV
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN
PGOOD deassert to lower
(PGOOD → Low)
VPGDLL
VPGHYSHL
VPGDLH
VPGHYSHH
VINMINPG
VOVP
Measured at the VOUT pin wrt/ VREFIN
84%
8%
PGOOD high hysteresis
PGOOD de-assert to higher
(PGOOD → Low)
Measured at the VOUT pin wrt/ VREFIN
116%
-8%
PGOOD high hysteresis
Minimum VIN voltage for valid
PGOOD
Measured at the VIN pin with a 2-mA sink current on PGOOD
pin
0.9
117%
65%
1.3
1.5
123%
71%
V
OVP threshold
UVP threshold
Measured at the VOUT pin wrt/ VREFIN
120%
68%
Measured at the VOUT pin wrt/ VREFIN, device latches OFF,
begins soft-stop
VUVP
THSD
Thermal shutdown(1)
Thermal Shutdown hysteresis(1)
Latch off controller, attempt soft-stop.
145
10
°C
°C
THSD(hys)
Controller re-starts after temperature has dropped
(1) Ensured by design, not production tested.
4
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
DRIVERS: BOOT STRAP SWITCH
RDSONBST
IBSTLK
Internal BST switch on-resistance
Internal BST switch leakage current
IBST = 10 mA, TA = 25°C
10
1
Ω
VBST = 14 V, VSW = 7 V
µA
TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS
VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz
VVIN = 5 V, VVOUT = 1.05 V, fSW = 600 kHz
210
310
(2)
tONESHOTC
PWM one-shot
ns
ns
VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz, DRVL on, SW =
PGND, VVOUT < VREFIN
tMIN(off)
Minimum OFF time
270
tINT(SS)
Soft-start time
From EN = HI to VOUT =95%, default setting
From EN = HI to VOUT ramp starts
External tracking
1.6
260
8
ms
µs
tINT(SSDLY)
tPGDDLY
Internal soft-start delay time
PGOOD startup delay time
ms
ms
µs
tPGDPDLYH
tPGDPDLYL
tOVPDLY
PGOOD high propagation delay time 50 mV over drive, rising edge
0.8
1
1.2
PGOOD low propagation delay time
OVP delay time
50 mV over drive, falling edge
10
10
2
Time from the VOUT pin out of +20% of REFIN to OVP fault
Time from EN_INT going high to undervoltage fault is ready
External tracking from VOUT ramp starts
µs
tUVDLYEN
tUVPDLY
Undervoltage fault enable delay
UVP delay time
ms
8
Time from the VOUT pin out of –30% of REFIN to UVP fault
256
µs
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGDPD
IPGDLKG
VENH
PGOOD pull-down voltage
PGOOD leakage current
EN logic high
PGOOD low impedance, ISINK = 4 mA, VV5IN = 4.5 V
PGOOD high impedance, forced to 5.5 V
EN, VCCP logic
0.3
1
V
µA
V
–1
0
2
VENL
EN logic low
EN, VCCP logic
0.5
1
V
IEN
EN input current
µA
Threshold 1
Threshold 2
Threshold 3
Threshold 4
80
200
130
250
180
300
470
1.850
mV
VMODETH
MODE threshold voltage(3)
MODE current
370
420
1.765
1.800
15
V
IMODE
µA
(2) Ensured by design, not production tested.
(3) See Table 3 for descriptions of MODE parameters.
Copyright © 2011, Texas Instruments Incorporated
5
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
TPS53317
RGB PACKAGE
(Top View)
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
PGND
PGND
PGND
VIN
SW
SW
SW
SW
SW
Exposed
Thermal Pad
VIN
6
7
8
9
10
Table 2. PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NO.
NAME
Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and
the SW pin.
16
BST
I
8
17
6
COMP
EN
O
I
Connect series R-C filter between this pin and VREF for loop compensation.
Enable of the SMPS (3.3-V logic compatible).
GND
MODE
–
I
Signal ground.
18
1
Allows selection of switching frequencies light-load modes. (See Table 3)
2
PGND
I
Power ground. Source terminal of the rectifying low-side power FET. Positive input for current sensing.
3
19
9
PGOOD
REFIN
O
Power good output. Connect pull-up resistor.
Target output voltageinput pin. Apply voltage between 0.6 V to 2.0 V.
11
12
13
14
15
20
4
SW
I/O
Switching node output. Connect to the external inductor. Also serve as current-sensing negative input.
V5IN
VIN
I
I
5-V power supply for analog circuits and gate drive.
Power supply input pin. Drain terminal of the switching high-side power FET.
5
10
7
VOUT
VREF
I
Output voltage monitor input pin.
O
2.0-V reference output. Connect a 0.22-µF ceramic capacitor to GND.
6
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
BLOCK DIAGRAM
TPS53317
19 PGOOD
VREFIN + 16%
+
+
VREFIN –30%
+
UV
Delay
+
OV
VREFIN – 16%
GND
VREFIN +20%
COMP
REFIN
8
9
10 ?A
VS
Amplifier
Control Logic
UVP
OVP
On-Time
Selection
·
·
·
·
·
On/Off Time
18 MODE
16 VBST
Minimum On/Off
SKIP/ODA/FPWM
OCL/OVP/UVP
DIsharge
+
+
Ramp
SS
+
PWM
EN 17
Comp
DAC
VIN
4
DVRH
VREF
7
5
VIN
VBG
VOUT 10
Current Sense
Amplifier
11 SW
12 SW
13 SW
14 SW
15 SW
18 V5IN
8 R
+
PGND
+
XCON
tON
One-
Shot
OC
R
SW
GND
Sample
and Hold
ZC
+
DVRL
ZC Threshold
Modulation
1
2
3
PGND
GND
6
Discharge
PGND
PGND
PGND
UDG-11106
Copyright © 2011, Texas Instruments Incorporated
7
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
Figure 1. VTT Application (Non-Droop Configuration)
8
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
Figure 2. Application Using Droop Configuration
Copyright © 2011, Texas Instruments Incorporated
9
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
APPLICATION INFORMATION
Functional Overview
The TPS53317 is a D-CAP+™ mode adaptive on-time converter. Integrated high-side and low-side FET supports
output current to a maximum of 6-ADC. The converter automatically runs in discontinuous conduction mode
(DCM) to optimize light-load efficiency. Multiple switching frequencies are provided to enable optimization of the
power chain for the cost, size and efficiency requirements of the design (see Table 3).
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters,
each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS53317, the
cycle begins when the current feedback reaches an error voltage level which is the amplified difference between
the reference voltage and the feedback voltage.
PWM Operation
Referring to Figure 3, in steady state, continuous conduction mode, the converter operates in the following way.
Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCS) is higher
than the error amplifier output (VCOMP). VCS falls until it hits VCOMP, which contains a component of the output
ripple voltage. VCS is not directly accessible by measuring signals on pins of TPS53317. The PWM comparator
senses where the two waveforms cross and triggers the on-time generator.
Current
Feedback
V
CS
V
COMP
V
REF
t
ON
t
Time (ms)
UDG-10187
Figure 3. D-CAP+™ Mode Basic Waveforms
The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side
FET on-time. The TPS53317 also provides a single-ended differential voltage (VOUT) feedback to increase the
system accuracy and reduce the dependence of circuit performance on layout.
10
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
PWM Frequency and Adaptive on Time Control
In general, the on-time (at the SW node) can be estimated by Equation 1.
V
1
OUT
t
=
´
ON
V
f
SW
IN
where
•
fSW is the frequency selected by the connection of the MODE pin
(1)
The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.
Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in .
Non-Droop Configuration
The TPS53317 can be configured as a non-droop solution. The benefit of a non-droop approach is that load
regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is
recommended. For the Intel system agent application, non-droop is recommended as the standard configuration.
The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and
the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the
phase delay at unity gain cross over frequency of the converter.
The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the
value of the capacitor (CC) can be calculated by knowing where the zero location is desired. An application tool
that calculates these values is available from your local TI Field Application Engineer.
Figure 4 shows the basic implementation of the non-droop mode using the TPS53317.
GMV = 1 mS
RC
CC
VREFIN
+
LOUT
+
+
GMC= 1 mS
–
Driver
+
ESR
RDS(on)
PWM
Comparator
ROUT
RLOAD
8 kW
COUT
+
VREF
–
UDG-11168
Figure 4. Non-Droop Mode Basic Implementation
Copyright © 2011, Texas Instruments Incorporated
11
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
Figure 5 shows shows the load regulation using non-droop configuration.
Figure 6 shows the transient response of TPS53317 using non-droop configuration, where COUT = 12 x 22 µF.
The applied step load is from 0 A to 3 A.
0.85
0.83
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
Non−Droop Configuration
0.65
1
2
3
4
5
6
Output Current (A)
Figure 5. Load Regulation for 1.5-V Input and
0.75-V Output (Non-Droop Configuration)
Figure 6. Non-Droop Configuration Transient
Response
Droop Configuration
The terminology for droop is the same as load line or voltage positioning as defined in the Intel CPU VCORE
specification. Based on the actual tolerance requirement of the application, load-line set points can be defined to
maximize either cost savings (by reducing output capacitors) or power reduction benefits.
Accurate droop voltage response is provided by the finite gain of the droop amplifier. The equation for droop
voltage is shown in Equation 2.
A
´I(L)
CSINT
V
=
DROOP
R
´ G
DROOP
M
where
•
•
•
•
•
low-side on-resistence is used as the current sensing element
ACSINT is a constant, which nominally is 53 mV/A.
I(L) is the DC current of the inductor, or the load current
RDROOP is the value of resistor from the COMP pin to the VREF pin
GM is the transconductance of the droop amplifier with nominal value of 1 mS
(2)
(3)
Equation 3 can be used to easily derive RDROOP for any load line slope/droop design target.
V
A
A
DROOP
CSINT
CSINT
R
=
=
\ R
=
LOAD _LINE
DROOP
I(L)
R
´ G
R
´ G
DROOP
M
LOAD _LINE M
12
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
Figure 7 shows the basic implementation of the droop mode using the TPS53317.
GMV = 1 mS
RDROOP
VREFIN
+
LOUT
+
+
GMC= 1 mS
–
Driver
+
ESR
ROUT
COUT
RDS(on)
PWM
Comparator
RLOAD
8 kW
+
VREF
–
UDG-11167
Figure 7. DROOP Mode Basic Implementation
The droop (voltage positioning) method was originally recommended to reduce the number of external output
capacitors required. The effective transient voltage range is increased because of the active voltage positioning
(see Figure 8).
Load insertion
I
LOAD
Load release
Droop
V
setpoint at 0 A
OUT
Maximum transient voltage
= (5%–1%) x 2 = 8% x V
OUT
V
setpoint at 6 A
OUT
Non-
Droop
Maximum overshoot voltage =(5%–1%) x 1 = 4% x V
OUT
V
setpoint at 0 A
OUT
Maximum undershoot voltage =(5%–1%) x 1 = 4% x V
OUT
UDG-11080
Figure 8. DROOP vs Non-DROOP in Transient Voltage Window
In applications where the DC and the AC tolerances are not separated, which means there is not a strict DC
tolerance requirement, the droop method can be used.
Copyright © 2011, Texas Instruments Incorporated
13
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
Table 3. Mode Definitions
LIGHT-LOAD
POWER SAVING
MODE
SWITCHING
FREQUENCY
(fSW
OVERCURRENT
LIMIT (OCL)
VALLEY (A)
MODE
RESISTANCE (kΩ)
MODE
)
1
2
3
4
5
6
7
8
0
12
600 kHz
600 kHz
1 MHz
6
4
4
6
6
4
4
6
SKIP
PWM
22
33
1 MHz
47
600 kHz
600 kHz
1 MHz
68
100
OPEN
1 MHz
Figure 9 shows the load regulation of the 1.5-V rail using an RDROOP value of 6.8 kΩ.
Figure 10 shows the transient response of the TPS53317 using droop configuration and COUT = 12 × 22 µF. The
applied step load is from 0 A to 3 A.
0.85
0.83
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
Droop Configuration
0.65
0
1
2
3
4
5
6
Output Current (A)
Figure 9. Load Regulation for 1.5-V Input and
0.75-V Output (Droop Configuration)
Figure 10. Droop Configuration Transient
Response
14
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
Light-Load Power Saving Features
The TPS53317 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range.
The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This
saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the
converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as
well.
TPS53317 also provides a special light-load power saving feature, called ripple reduction. Essentially, it reduces
the on-time in SKIP mode to effectively reduce the output voltage ripple associated with using an all MLCC
capacitor output power stage design.
Power Sequences
Non-Tracking Startup
The TPS53317 can be configured for non-tracking application. When non-tracking is configured, output voltage is
regulated to the REFIN voltage which taps off the voltage dividers from the 2VREF. Either the EN pin or the V5IN
pin can be used to start up the device. The TPS53317 uses internal voltage servo DAC to provide a precise
1.6-ms soft-start time during soft-start initialization. (See Figure 11)
Tracking Startup
TPS53317 can also be configured for tracking application. When tracking configuration is desired, output voltage
is also regulated to the REFIN voltage which comes from external power source. In order for TPS53317 to
differentiate between a non-tracking configuration or a tracking configuration, there is a minimum delay time of
260 µs required between the time when the EN pin or the 5VIN pin is validated to the time when the REFIN pin
voltage can be applied, in order for the TPS53317 to track properly (see Figure 12). The valid REFIN voltage
range is between 0.6 V to 2 V.
Protection Features
The TPS53317 offers many features to protect the converter power chain as well as the system electronics.
5-V Undervoltage Protection (UVLO)
The TPS53317 continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high enough
to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The converter
starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is reached, the
converter transitions the phase node into a off function. And the converter remains in the off state until the device
is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does not have an UVLO
function
Power Good Signals
The TPS53317 has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power good high
propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage condition
on V5IN or any other faults that require latch off action is detected.
Output Overvoltage Protection (OVP)
In addition to the power good function described above, the TPS53317 has additional OVP and UVP thresholds
and protection circuits.
An OVP condition is detected when the output voltage is approximately 120% × VREFIN. In this case, the
converter de-asserts the PGOOD signals and performs the overvoltage protection function. The converter
remains in this state until the device is reset by cycling 5 V until the 5-V POR threshold (2.3 V nominal) is
reached.
Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described in the Overcurrent
Protection and Overcurrent Limit sections. If the output voltage drops below 70% of VREFIN, after an 8-µs delay,
the device latches OFF. Undervoltage protection can be reset only by EN or a 5-V POR.
Copyright © 2011, Texas Instruments Incorporated
15
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
Overcurrent Protection
Both positive and negative overcurrent protection are provided in the TPS53317:
•
•
Overcurrent Limit (OCL)
Negative OCL (level same as positive OCL)
Overcurrent Limit
If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current
drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The TPS53317 uses a valley
current limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The
minimum valley OCL is 6 A over process and temperature.
During the overcurrent protection event, the output voltage likely droops until the UVP limit is reached. Then, the
converter de-asserts the PGOOD pin, and then latches OFF after an 8-µs delay. The converter remains in this
state until the device is reset.
1
I
= IOCL valley
)
+
´IP-P
OCL(dc)
(
2
(4)
Negative OCL
The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter
continues to act in a valley mode, the absolute value of the negative OCL set point is typically -6.5 A.
Thermal Protection
Thermal Shutdown
The TPS53317 has an internal temperature sensor. When the temperature reaches a nominal 145°C, the device
shuts down until the temperature cools by approximately 10°C. Then the converter restarts.
16
Copyright © 2011, Texas Instruments Incorporated
TPS53317
www.ti.com
SLUSAK4 –JUNE 2011
Startup Timing Diagrams
Figure 11. Non-Tracking Start-Up
Figure 12. Tracking Start-Up
Copyright © 2011, Texas Instruments Incorporated
17
TPS53317
SLUSAK4 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
95
90
85
80
75
70
65
60
55
0.760
0.758
0.756
0.754
0.752
0.750
0.748
0.746
Skip Mode, fSW = 600 kHz
Skip Mode, fSW = 600 kHz
Skip Mode, fSW =1 MHz
PWM Mode, fSW = 600 kHz
PWM Mode, fSW = 1 MHz
Skip Mode, fSW =1 MHz
PWM Mode, fSW = 600 kHz
PWM Mode, fSW = 1 MHz
0.744
0.742
0.740
50
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
G001
G001
Figure 13. Efficiency vs Output Current
(1.5-V Input and 0.75-V Output)
Figure 14. Output Voltage vs Output Current
(1.5-V Input and 0.75-V Output)
LAYOUT CONSIDERATIONS
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.
•
Connect PGND pins (or at least one of the pins) to the thermal PAD underneath the device. Also connect
GND pin to the thermal PAD underneath the device. Use four vias to connect the thermal pad to internal
ground planes.
•
•
Place VIN, V5IN and VREF decoupling capacitors as close to the device as possible.
Use wide traces for the VIN, VOUT, PGND and SW pins. These nodes carry high current and also serve as
heat sinks.
•
•
Place feedback and compensation components as close to the device as possible.
Place COMP analog signal away from noisy signals (SW, BST).
18
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS53317RGBR
TPS53317RGBT
ACTIVE
ACTIVE
VQFN
VQFN
RGB
RGB
20
20
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53317RGBR
TPS53317RGBT
VQFN
VQFN
RGB
RGB
20
20
3000
250
330.0
180.0
12.4
12.4
3.8
3.8
4.3
4.3
1.5
1.5
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53317RGBR
TPS53317RGBT
VQFN
VQFN
RGB
RGB
20
20
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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