DRA786 [TI]
适用于音频放大器且具有 2 个 500MHz C66x DSP 和 2 个双核 Arm Cortex-M4 和 EVE 的 SoC 处理器;
| 型号： | DRA786 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于音频放大器且具有 2 个 500MHz C66x DSP 和 2 个双核 Arm Cortex-M4 和 EVE 的 SoC 处理器 放大器 音频放大器 |
| 文件： | 总288页 (文件大小：4234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
DRA78x 信息娱乐系统 应用 处理器
1 器件概述
1.1 特性
1
• 专为信息娱乐应用设计的 架构
• 多达 2 个 C66x 浮点 VLIW DSP
– 对象代码与 C67x 和 C64x+ 完全兼容
– 每周期最多 32 次 16 × 16 位定点乘法
• 高达 512kB 片上 L3 RAM
• 3 级 (L3) 和 4 级 (L4) 互连
• 存储器接口 (EMIF) 模块
• 8 个 32 位通用计时器
• 3 个可配置通用异步接收发送器 (UART) 模块
• 4 个多通道串行外设接口 (McSPI)
• 四通道 SPI 接口
• 两个内部集成电路 (I2C) 端口
• 三个多通道音频串行端口 (McASP) 模块
• 多媒体卡/安全数字/安全数字输入输出接口
( MMC™/ SD®/SDIO)
– 支持 DDR3/DDR3L 至 DDR-1066
– 支持 DDR2 至 DDR-800
• 多达 126 个通用 I/O (GPIO) 引脚
• 电源、复位和时钟管理
• 片上调试，采用 CTool 技术
• 符合汽车级 AEC-Q100 标准
– 最高支持 2GB
• Dual Arm® Cortex®-M4 (IPU)
• Vision AccelerationPac
• 15mm × 15mm、0.65mm 间距、367 引脚 PBGA
– 嵌入式视觉引擎 (EVE)
• 显示子系统
(ABF)
• 可作为看门狗计时器使用的五个实时中断 (RTI) 模
块实例
– 采用 DMA 引擎的显示控制器
– CVIDEO/SD-DAC TV 模拟复合输出
• 可生成温度警报的片上温度传感器
• 通用存储器控制器 (GPMC)
• 增强型直接存储器存取 (EDMA) 控制器
• 3 端口（2 个外置）千兆以太网 (GMAC) 交换机
• 控制器局域网 (DCAN) 模块
– CAN 2.0B 协议
• 8 通道 10 位 ADC
• PWMSS
• 视频和图像处理支持
– 全高清视频 (1920 × 1080p，60fps)
– 视频输入和视频输出
– 非视频用途时提供 GPIO 端口支持
• 视频输入端口 (VIP) 模块
– 支持多达 4 个多路复用输入端口
• 模块化控制器局域网 (MCAN) 模块
– CAN 2.0B 协议
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRS975
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
1.2 应用
•
•
数字和模拟无线电
混合无线电
•
•
DSP 音频放大器
车载互联协处理器
1.3 说明
DRA78x 处理器采用 367 焊球、15mm×15mm、0.65mm 焊球间距（0.8mm 间距规则可用于信号）（通过
Channel™ 阵列 (VCA) 技术实现）、球栅阵列 (FCBGA) 封装。
此架构旨在昨用经济高效的解决方案，为汽车协处理、混合无线电和放大器应用提供高性能并发性 ， 实现
DRA75x（“Jacinto 6 EP”和“Jacinto 6 Ex”）、DRA74x“Jacinto 6”、DRA72x“Jacinto 6 Eco”和
DRA71x“Jacinto 6 Entry”信息娱乐处理器系列的全面可扩展性。
此外，德州仪器 (TI) 提供一整套针对 Arm 和 DSP 的开发工具，其中包括 C 语言编译器和一个实现源代码
执行可视化的调试接口。
DRA78x Jacinto 6 RSP（无线电音频处理器）系列器件符合 AEC-Q100 标准。
该器件 采用 简化的电源轨映射，这使得低成本电源管理集成电路 (PMIC) 解决方案得以实现。
器件信息
封装
器件型号
DRA780
DRA781
DRA782
DRA783
DRA784
DRA785
DRA786
DRA787
DRA788
封装尺寸
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
FCBGA (367)
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
15.0mm × 15.0mm
2
器件概述
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
1.4 功能框图
图 1-1 是该超集的功能框图。
Display
Subsystem
IPU with ECC
DSP Subsystem x2
L1P 32KiB
L2
2x Cortex-M4
16KiB ROM
C66x
256KiB
Cache
DVOUT
L1D 32KiB
Vision
Accelerator
SD-DAC
EDMA 2TC
EVE 16MAC
OSD
Resizing
CSC
Video Front End
Video Input Port
EDMA 2TC
up to 512KiB RAM
with ECC
Radio Accelerator
HD ATL
Interconnect
DRA78x
JTAG
PLLs
OSC
Serial Interfaces
Connectivity
System
I2C x2
McSPI x4
QSPI x1
SDIO x1
UART x3
EDMA
GPIO x4
PWMSS x1
MMU x1
PRCM
Timer x8
GEMAC Switch
McASP x3
Mailbox/Spinlock
10-bit ADC
DCAN (with ECC)
MCAN (CAN-FD)
with ECC
Control Module
RTI x5
Memory Controllers
GPMC 8b/16b
with up to 16b ECC
DDR2/DDR3/DDR3L
32b with 8b ECC
func_sprs968-001
Copyright © 2016, Texas Instruments Incorporated
图 1-1. DRA78x 框图
版权 © 2016–2019, Texas Instruments Incorporated
器件概述
3
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 .................................................. 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 ............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1 Pin Diagram ......................................... 10
4.2 Pin Attributes ........................................ 10
4.3 Signal Descriptions.................................. 40
4.4 Pin Multiplexing ..................................... 66
4.5 Connections for Unused Pins ....................... 77
Specifications ........................................... 78
5.1 Absolute Maximum Ratings......................... 79
5.2 ESD Ratings ........................................ 79
5.3 Power on Hour (POH) Limits........................ 79
5.4 Recommended Operating Conditions............... 81
5.5 Operating Performance Points ...................... 83
5.6 Power Consumption Summary...................... 92
5.7 Electrical Characteristics............................ 92
5.8 Thermal Characteristics ............................. 98
6.5 EVE ................................................ 190
6.6 Memory Subsystem................................ 192
6.7 Interprocessor Communication .................... 195
6.8 Interrupt Controller................................. 196
6.9 EDMA .............................................. 196
6.10 Peripherals ......................................... 198
6.11 On-Chip Debug .................................... 210
Applications, Implementation, and Layout ...... 214
7.1 Introduction ........................................ 214
7.2 Power Optimizations ............................... 215
7.3 Core Power Domains .............................. 226
7.4 Single-Ended Interfaces ........................... 236
7.5 Differential Interfaces .............................. 238
7.6 Clock Routing Guidelines .......................... 239
2
3
7
4
5
7.7
7.8
7.9
DDR2 Board Design and Layout Guidelines....... 240
DDR3 Board Design and Layout Guidelines....... 251
CVIDEO/SD-DAC Guidelines and Electrical
Data/Timing ........................................ 274
8
Device and Documentation Support.............. 276
8.1 Device Nomenclature .............................. 276
8.2 Tools and Software ................................ 278
8.3 Documentation Support............................ 279
8.4 Related Links ...................................... 279
8.5 Community Resources............................. 279
8.6 商标 ................................................ 279
8.7 静电放电警告....................................... 280
8.8 Export Control Notice .............................. 280
8.9 Glossary............................................ 280
5.9
Timing Requirements and Switching
Characteristics ..................................... 100
6
Detailed Description.................................. 183
6.1 Description ......................................... 183
6.2 Functional Block Diagram ......................... 183
6.3 DSP Subsystem ................................... 184
6.4 IPU ................................................. 189
9
Mechanical, Packaging, and Orderable
Information............................................. 281
9.1 Packaging Information ............................. 281
4
内容
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
2 修订历史记录
Changes from September 19, 2018 to March 31, 2019 (from F Revision (September 2018) to G Revision)
Page
•
•
•
•
•
更新了器件信息表，为每个器件增加了额外的行.................................................................................. 1
Added clarification notes regarding XTDA3SX part number to 表 3-1, Device Comparison................................ 8
Added Related Products section.................................................................................................... 9
Removed Internal pulldown for OSC0 and OSC1 oscillators from 表 4-1,Pin Attributes .................................. 12
Added clarification notes for EMU[1:0] connections in 表 4-20, GPIOs Signal Descriptions and 表 4-23, Debug
Signal Descriptions.................................................................................................................. 60
Added clarification note regarding TSHUT feature in Section 5.4, Recommended Operating Conditions ............. 83
Updated VD_CORE max value in 表 5-3, Voltage Domains Operating Performance Points ............................ 83
Updated FUNC_32K_CLK source name in 表 5-5, Maximum Supported Frequency...................................... 84
Updated paragraphs as per datasheet standard in Section 5.9.1.1.2, 1.8 V and 3.3 V Signal Transition Rates
and 节 5.9.5, Recommended Clock and Control Signal Transition Behavior.............................................. 101
Added missing "hsync" and "fld" signals to 表 5-28, VIN1 IOSETs ......................................................... 120
Fixed muxmode value for vin2a_hsync0 in 表 5-29, VIN2 IOSETs ......................................................... 121
Updated 节 8.1, Device Nomenclature, 节 8.2 Tools and Software, and 节 8.3, Documentation Support;
•
•
•
•
•
•
•
Removed section 9.3.1 FCC Warning, section 9.3.2 Information About Cautions and Warnings, and section 9.4
Receiving Notification of Documentation Updates; Fixed Arm trademark in section 9.7 Trademarks.................. 276
Updated note for cosmetic marks on package................................................................................. 276
Added clarification notes regarding XTDA3SX part number in 表 8-1, Nomenclature Description ..................... 276
Updated 节 9, Mechanical, Packaging, and Orderable Information as per datasheet standard ........................ 281
•
•
•
版权 © 2016–2019, Texas Instruments Incorporated
修订历史记录
5
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
3 Device Comparison
表 3-1 shows a comparison between devices, highlighting the differences.
6
Device Comparison
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 3-1. Device Comparison(4)
FEATURES
Features
DEVICE
DRA783
DRA780
DRA781
DRA784
DRA782
DRA785
DRA786
DRA787
DRA788
CTRL_WKUP_STD_FUSE_DIE_ID_2 [31:24] Base PN
register bitfield value(3)(4)
112 (0x70)
113 (0x71) 116 (0x74)
114 (0x72)
115 (0x73) 117 (0x75) 118 (0x76) 119 (0x77) 120 (0x78)
Processors/ Accelerators
Speed Grades
D
R
S
D
R
S
D
R
S
C66x VLIW DSP
DSP1
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DSP2
Display Subsystem
VOUT1
SD_DAC
EVE1
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Embedded Vision Engine (EVE)
Dual Arm Cortex-M4 Image Processing
Unit (IPU)
IPU1
Yes
Yes
Yes
Yes
Yes
Yes
Imaging Subsystem Processor (ISS) with ISP
MIPI CSI-2 and CPI ports
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
WDR & Mesh
LDC(1)
CAL_A
CAL_B
LVDS-RX
CPI
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Video Input
Port (VIP)
VIP1
vin1a
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
vin1b
vin2a
vin2b
Program/Data Storage
On-Chip Shared Memory (RAM)
OCMC_RAM1
GPMC
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
512kB
Yes
General-Purpose Memory Controller
(GPMC)
DDR2/DDR3/DDR3L Memory Controller
EMIF1
up to 2GB
up to 2GB
up to 2GB
up to 2GB
up to 2GB
up to 2GB
up to 2GB
up to 2GB
up to 2GB
(optional with
SECDED)
Radio Support
Audio Tracking Logic (ATL)
Peripherals
ATL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Controller Area Network Interface (CAN) DCAN1
版权 © 2016–2019, Texas Instruments Incorporated
Device Comparison
7
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 3-1. Device Comparison(4) (continued)
FEATURES
DEVICE
DRA783
FD(2)
DRA780
FD(2)
Yes
DRA781
FD(2)
Yes
DRA784
FD(2)
Yes
DRA782
FD(2)
Yes
DRA785
FD(2)
Yes
DRA786
FD(2)
Yes
DRA787
FD(2)
Yes
DRA788
FD(2)
Yes
MCAN
Enhanced DMA (EDMA)
EDMA
Yes
Embedded 8 channel ADC
Ethernet Subsystem (Ethernet SS)
ADC
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GMAC_SW[0]
GMAC_SW[1]
GPIO
RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only
RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only RGMII Only
General-Purpose IO (GPIO)
Up to 126
Up to 126
Up to 126
Up to 126
Up to 126
Up to 126
Up to 126
Up to 126
Up to 126
Inter-Integrated Circuit Interface (I2C)
System Mailbox Module
I2C
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MAILBOX
McASP1
2
2
Multichannel Audio Serial Port (McASP)
16 serializers
16
16
16 serializers
16
16
16
16
16
serializers
serializers
serializers
serializers
serializers
serializers
serializers
McASP2
McASP3
MMC
6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers
6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers 6 serializers
1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b
MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface
(MMC/SD/SDIO)
Multichannel Serial Peripheral Interface
(McSPI)
McSPI
4
4
4
4
4
4
4
4
4
Quad SPI ( QSPI™)
QSPI
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Yes
Yes
8
Spinlock Module
SPINLOCK
TIMER
DCC
Timers, General-Purpose
Dual Clock Comparators (DCC)
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Pulse-Width Modulation Subsystem
(PWMSS)
PWMSS1
Universal Asynchronous
Receiver/Transmitter (UART)
UART
CRC
3
3
3
3
3
3
3
3
3
Memory Cyclic Redundancy Check
(CRC)
No
No
No
No
No
No
No
No
No
TESOC (LBIST/PBIST)
LBIST/PBIST
ESM
No
No
5
No
No
5
No
No
5
No
No
5
No
No
5
No
No
5
No
No
5
No
No
5
No
No
5
Error Signaling Module (ESM)
Real Time Interrupt (RTI)
RTI
(1) Wide Dynamic Range and Lens Distortion Correction.
(2) MCAN with available FD (Flexible Data Rate) functionality. Devices that show MCAN = Yes do not support the Flexible Data Rate (FD) feature.
(3) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the DRA78x SoC for Automotive Infotainment Silicon Revision 2.0.
(4) XTDA3SX is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is
0x98.
8
Device Comparison
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
3.1 Related Products
Companion Products for DRA78x Review products that are frequently purchased or used in conjunction with this product.
Reference Designs for DRA78x TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor
and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block
diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
版权 © 2016–2019, Texas Instruments Incorporated
Device Comparison
9
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagram
图 4-1 shows the ball locations for the 367 plastic ball grid array (PBGA) package and are used in
conjunction with 表 4-1 through 表 4-28 to locate signal names and ball grid numbers.
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
10 12 18
22
6
8
2
4
14 16
20
SPRS916_BALL_01
图 4-1. ABF FCBGA-N367 Package (Bottom View)
注
The following bottom balls are not connected: C4 / C7 / C9 / C11 / C13 / C15 / C19 / D4 / D5
/ D9 / D11 / D13 / D17 / D18 / D19 / D20 / E4 / E5 / E6 / E9 / E11 / E13 / E15 / E18 / E19 /
F5 / F9 / F11 / F18 / G13 / G15 / G17 / G20 / H3 / H4 / H5 / H6 / J8 / J9 / J12 / J13 / J14 /
J18 / J19 / J20 / K3 / K4 / K5 / K6 / L9 / L10 / L11 / L13 / L14 / L17 / L18 / L19 / L20 / M3 /
M4 / M5 / M6 / N9 / N11 / N13 / N14 / N17 / N18 / N19 / N20 / P3 / P4 / P5 / P6 / R8 / R10 /
R11 / R13 / R14 / R15 / R17 / R18 / R19 / R20 / T3 / T6 / U5 / U10 / U12 / U14 / U18 / V4 /
V5 / V6 / V8 / V10 / V12 / V14 / V17 / V18 / V19 / W3 / W4 / W5 / W10 / W12 / W14 / W18 /
W19 / W20 / Y4 / Y7 / Y10 / Y12 / Y14 / Y16 / Y19.
These balls do not exist on the package.
4.2 Pin Attributes
表 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the
signal name in muxmode 0).
注
表 4-1 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in 节 4.3, Signal Descriptions.
注
In the Driver off mode, the buffer is configured in high-impedance.
10
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
注
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
c. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
–
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or Output
D = Open drain
DS = Differential Signaling
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
6. BALL RESET STATE: The state of the terminal at power-on reset:
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal).
–
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
注
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power, Reset, and Clock Management / Reset Management Functional Description
section of the Device TRM.
8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
An empty box means Not Applicable.
9. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
10. POWER: The voltage supply that powers the terminal IO buffers.
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
11
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
An empty box means Not Applicable.
11. HYS: Indicates if the input buffer is with hysteresis:
–
–
–
Yes: With hysteresis
No: Without hysteresis
An empty box: Not Applicable
注
For more information, see the hysteresis values in 节 5.7, DC Electrical Characteristics.
12. BUFFER TYPE: Drive strength of the associated output buffer.
An empty box means Not Applicable.
注
For programmable buffer strength:
–
–
The default value is given in 表 4-1.
A note describes all possible values according to the selected muxmode.
13. PULL UP / DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
–
–
–
–
–
–
PU: Internal pullup
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
PUx/PDy: Programmable internal pullup and pulldown
PDy: Programmable internal pulldown
An empty box means No pull
14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the CTRL_CORE_PADx registers.
–
–
–
0: Logic 0 driven on the peripheral's input signal port.
1: Logic 1 driven on the peripheral's input signal port.
blank: Pin state driven on the peripheral's input signal port.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
12
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
M19
M20
M21
M22
N22
N21
P19
P18
P20
N15
M15
M14
A11
adc_in0
adc_in1
adc_in2
adc_in3
adc_in4
adc_in5
adc_in6
adc_in7
adc_in0
adc_in1
adc_in2
adc_in3
adc_in4
adc_in5
adc_in6
adc_in7
adc_vrefp
0
A
A
A
A
A
A
A
A
A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
0
0
0
0
0
0
1.8
vdda_adc
vdda_adc
vdda_adc
vdda_adc
vdda_adc
vdda_adc
vdda_adc
vdda_adc
vdda_adc
GPADC
GPADC
GPADC
GPADC
GPADC
GPADC
GPADC
GPADC
GPADC
0
0
0
0
0
0
0
0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
adc_vrefp
cap_vddram_core1
cap_vddram_core2
cap_vddram_dspeve
csi2_0_dx0
cap_vddram_core1
cap_vddram_core2
cap_vddram_dspeve
csi2_0_dx0
CAP
CAP
CAP
I
0
0
0
0
0
0
0
0
0
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
0
0
0
0
0
0
0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
A12
A13
A15
A16
B11
B12
B13
B15
B16
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
I
I
I
I
I
I
I
I
I
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
T18
T17
P17
N6
cvideo_rset
cvideo_tvout
cvideo_vfb
dcan1_rx
cvideo_rset
cvideo_tvout
cvideo_vfb
dcan1_rx
gpio4_10
Driver off
dcan1_tx
gpio4_9
0
A
OFF
OFF
OFF
PU
OFF
OFF
OFF
PU
0
1.8
vdda_dac
vdda_dac
vdda_dac
vddshv1
AVDAC
AVDAC
AVDAC
0
A
0
1.8
0
A
0
1.8
0
IO
IO
I
15
1.8/3.3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
N5
dcan1_tx
IO
IO
I
PU
PU
15
1.8/3.3
vddshv1
Dual Voltage PU/PD
LVCMOS
14
15
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
13
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
F2
ddr1_casn
ddr1_casn
ddr1_ck
0
O
O
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PD
PD
PD
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
drive 1 (OFF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
G1
AB13
AB10
AA10
G2
F1
ddr1_ck
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
drive clk
(OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
ddr1_dqm_ecc
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_nck
ddr1_rasn
ddr1_rst
ddr1_dqm_ecc
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_nck
ddr1_rasn
ddr1_rst
PD
PU
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
drive clk
(OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
drive 1 (OFF)
drive 0 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
N1
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
E3
ddr1_wen
ddr1_a0
ddr1_wen
ddr1_a0
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
U4
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
C1
ddr1_a1
ddr1_a1
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
D3
ddr1_a2
ddr1_a2
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
R4
ddr1_a3
ddr1_a3
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
T4
ddr1_a4
ddr1_a4
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
N3
ddr1_a5
ddr1_a5
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
T2
ddr1_a6
ddr1_a6
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
N2
ddr1_a7
ddr1_a7
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
T1
ddr1_a8
ddr1_a8
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
U1
ddr1_a9
ddr1_a9
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
D1
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
R3
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
U2
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
C3
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
14
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
R2
ddr1_a14
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_cke0
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
0
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
drive 1 (OFF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
V1
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_cke0
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
B3
O
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
A3
O
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
D2
O
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
F3
O
drive 0 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
B2
O
drive 1 (OFF)
1.2/1.35/1.5/1 vdds_ddr2
.8
LVCMOS
DDR
AA6
AA8
Y8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
AA7
AB4
Y5
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
AA4
Y6
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
AA18
Y21
AA21
Y22
AA19
AB20
Y17
AB18
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
15
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
AA3
AA2
Y3
ddr1_d16
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
V2
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
U3
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
V3
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
Y2
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
Y1
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
U21
T20
R21
U20
R22
V20
W22
U22
AB8
Y18
AB3
W21
AA5
AA20
W1
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
16
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
T21
AB5
Y20
W2
ddr1_dqs3
ddr1_dqs3
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
PD
PU
PU
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_odt0
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_odt0
0
0
0
0
0
0
0
0
0
0
0
0
0
PU
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PU
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
PU
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
T22
Y11
AA12
AA11
Y9
PU
1.2/1.35/1.5/1 vdds_ddr3
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
AA13
AB11
AA9
AB9
P2
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
PD
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
drive 0 (OFF)
PU
1.2/1.35/1.5/1 vdds_ddr1
.8
LVCMOS
DDR
H1
emu0
emu0
0
IO
IO
I
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
gpio4_28
Driver off
emu1
14
15
0
H2
E8
emu1
IO
IO
I
PU
PU
0
Yes
Yes
Dual Voltage PU/PD
LVCMOS
gpio4_29
Driver off
gpmc_ad0
rgmii1_rxd2
gpio1_14
sysboot0
gpmc_ad1
rgmii1_rxd1
gpio1_15
sysboot1
14
15
0
gpmc_ad0
IO
I
OFF
OFF
15
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
0
IO
I
A7
gpmc_ad1
IO
I
OFF
OFF
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
IO
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
17
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
F8
B7
A6
F7
gpmc_ad2
gpmc_ad2
rgmii1_rxd0
gpio1_16
sysboot2
gpmc_ad3
qspi1_rtclk
gpio1_17
sysboot3
gpmc_ad4
cam_strobe
gpio1_18
sysboot4
gpmc_ad5
uart2_txd
timer6
0
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
0
IO
I
gpmc_ad3
gpmc_ad4
gpmc_ad5
IO
I
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
0
IO
I
IO
O
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
14
15
0
IO
O
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
spi3_d1
4
gpio1_19
14
15
sysboot5
mcasp2_aclkx
E7
C6
B6
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad6
uart2_rxd
timer5
0
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
2
3
IO
IO
IO
I
spi3_d0
4
0
gpio1_20
14
15
sysboot6
mcasp2_fsx
gpmc_ad7
cam_shutter
timer4
0
IO
O
0
Dual Voltage PU/PD
LVCMOS
0
0
1
3
IO
IO
IO
I
spi3_sclk
gpio1_21
4
14
15
Driver off
mcasp2_ahclkx
gpmc_ad8
timer7
0
IO
IO
IO
IO
I
15
Dual Voltage PU/PD
LVCMOS
0
1
3
spi3_cs0
gpio1_22
4
14
15
sysboot8
mcasp2_aclkr
18
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A5
gpmc_ad9
gpmc_ad9
0
IO
IO
IO
IO
I
OFF
OFF
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
eCAP1_in_PWM1_out
spi3_cs1
3
4
gpio1_23
14
15
sysboot9
mcasp2_fsr
D6
C5
gpmc_ad10
gpmc_ad11
gpmc_ad10
timer2
0
IO
IO
IO
I
OFF
OFF
OFF
OFF
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
3
gpio1_24
14
15
sysboot10
mcasp2_axr0
gpmc_ad11
timer3
0
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
3
gpio1_25
14
15
sysboot11
mcasp2_axr1
B5
D7
gpmc_ad12
gpmc_ad13
gpmc_ad12
gpio1_26
0
IO
IO
I
OFF
OFF
OFF
OFF
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
sysboot12
mcasp2_axr2
gpmc_ad13
rgmii1_rxc
gpio1_27
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
IO
I
sysboot13
mcasp2_axr3
B4
A4
gpmc_ad14
gpmc_ad15
gpmc_ad14
spi2_cs1
0
IO
IO
IO
I
OFF
OFF
OFF
OFF
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
4
gpio1_28
14
15
sysboot14
mcasp2_axr4
gpmc_ad15
spi2_cs0
0
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
4
gpio1_29
14
15
sysboot15
mcasp2_axr5
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
19
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
F12
gpmc_advn_ale
gpmc_advn_ale
rgmii1_txd2
ehrpwm1_tripzone_input
clkout1
0
O
O
IO
O
I
PD
PD
0
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
4
0
5
dma_evt4
gpio1_3
6
14
15
0
IO
I
Driver off
D12
E12
C12
gpmc_ben0
gpmc_ben1
gpmc_clk
gpmc_ben0
rgmii1_txctl
ehrpwm1A
dma_evt2
gpio1_1
O
O
O
I
PD
PD
PD
PD
PD
PD
0
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
4
6
14
15
0
IO
I
Driver off
gpmc_ben1
rgmii1_txd3
ehrpwm1B
dma_evt3
gpio1_2
O
O
O
I
15
Dual Voltage PU/PD
LVCMOS
1
4
6
14
15
0
IO
I
Driver off
gpmc_clk
rgmii1_txc
clkout0
IO
O
O
I
0
Dual Voltage PU/PD
LVCMOS
0
1
5
dma_evt1
gpio1_0
6
14
15
0
IO
I
Driver off
C10
E10
D10
gpmc_cs0
gpmc_cs1
gpmc_cs2
gpmc_cs0
rgmii1_rxctl
gpio1_6
O
I
PU
PU
PU
PU
PU
PU
0
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
0
14
15
0
IO
I
Driver off
gpmc_cs1
qspi1_cs0
gpio1_7
O
IO
IO
I
15
15
Dual Voltage PU/PD
LVCMOS
1
14
15
0
Driver off
gpmc_cs2
qspi1_d3
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
gpio1_8
14
15
Driver off
20
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A9
gpmc_cs3
gpmc_cs3
qspi1_d2
gpio1_9
0
O
IO
IO
I
PU
PU
PU
PU
PD
PU
PU
PU
PU
PD
15
15
15
15
0
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
0
14
15
0
Driver off
gpmc_cs4
qspi1_d0
gpio1_10
Driver off
gpmc_cs5
qspi1_d1
gpio1_11
Driver off
gpmc_cs6
qspi1_sclk
gpio1_12
Driver off
B9
gpmc_cs4
O
IO
IO
I
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
14
15
0
F10
C8
gpmc_cs5
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
14
15
0
gpmc_cs6
O
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
14
15
0
A10
gpmc_oen_ren
gpmc_oen_ren
rgmii1_txd1
ehrpwm1_synci
clkout2
O
O
I
Dual Voltage PU/PD
LVCMOS
1
4
0
5
O
IO
I
gpio1_4
14
15
0
Driver off
D8
gpmc_wait0
gpmc_wait0
rgmii1_rxd3
qspi1_rtclk
dma_evt4
gpio1_13
I
PU
PU
0
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
1
I
2
I
6
I
14
15
0
IO
I
Driver off
B10
gpmc_wen
gpmc_wen
rgmii1_txd0
ehrpwm1_synco
gpio1_5
O
O
O
IO
I
PD
PD
0
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
4
14
15
0
Driver off
L3
L4
L6
i2c1_scl
i2c1_sda
i2c2_scl
i2c1_scl
IO
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Dual Voltage PU
LVCMOS I2C
i2c1_sda
i2c2_scl
0
0
IO
IO
Dual Voltage PU
LVCMOS I2C
Dual Voltage PU
LVCMOS I2C
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
21
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
L5
i2c2_sda
mcan_rx
i2c2_sda
0
IO
OFF
PU
OFF
PU
0
1.8/3.3
1.8/3.3
vddshv1
vddshv6
Yes
Yes
Dual Voltage PU
LVCMOS I2C
W6
mcan_rx
0
IO
IO
I
15
Dual Voltage PU/PD
LVCMOS
1
1
0
1
cam_nreset
vin2a_vsync0
spi1_cs3
1
2
3
IO
O
O
I
uart3_txd
gpmc_cs7
vin1b_vsync1
gpio4_12
Driver off
mcan_tx
4
5
7
14
15
0
IO
I
W7
mcan_tx
IO
I
PU
PU
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
vin2a_de0
vin2a_hsync0
spi1_cs2
1
2
I
3
IO
I
1
1
1
0
0
uart3_rxd
gpmc_wait1
vin1b_hsync1
vin1b_de1
gpio4_11
Driver off
mdio_d
4
6
I
7
I
8
I
14
15
0
IO
I
B17
B19
G5
mdio_d
mdio_mclk
nmin
IO
IO
IO
I
PU
PU
PU
PU
PU
PU
15
15
0
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
spi4_d0
4
gpio3_18
Driver off
mdio_mclk
spi4_d1
14
15
0
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
4
gpio3_17
Driver off
nmin
14
15
0
I
Dual Voltage PU/PD
LVCMOS
1
G3
G4
porz
porz
0
0
I
I
OFF
PU
OFF
PU
0
0
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
IHHV1833
PU/PD
resetn
resetn
Dual Voltage PU/PD
LVCMOS
B18
rgmii0_rxc
rgmii0_rxc
cam_strobe
mmc_clk
0
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
0
1
3
O
IO
IO
I
5
gpio3_25
Driver off
14
15
22
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C18
rgmii0_rxctl
rgmii0_rxctl
0
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
0
1
cam_shutter
mmc_cmd
gpio3_26
Driver off
3
O
IO
IO
I
5
14
15
0
C16
rgmii0_txc
rgmii0_txc
cam_strobe
spi4_sclk
mmc_clk
O
O
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
3
4
0
1
5
gpio3_19
Driver off
14
15
0
C17
rgmii0_txctl
rgmii0_txctl
cam_shutter
spi4_cs0
O
O
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
3
4
1
1
mmc_cmd
gpio3_20
Driver off
5
14
15
0
A20
C20
B20
A19
F17
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txd0
rgmii0_rxd0
mmc_dat3
gpio3_30
Driver off
I
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv4
vddshv4
vddshv4
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
5
IO
IO
I
14
15
0
rgmii0_rxd1
mmc_dat2
gpio3_29
Driver off
I
Dual Voltage PU/PD
LVCMOS
0
1
5
IO
IO
I
14
15
0
rgmii0_rxd2
mmc_dat1
gpio3_28
Driver off
I
Dual Voltage PU/PD
LVCMOS
0
1
5
IO
IO
I
14
15
0
rgmii0_rxd3
mmc_dat0
gpio3_27
Driver off
I
Dual Voltage PU/PD
LVCMOS
0
1
5
IO
IO
I
14
15
0
rgmii0_txd0
mmc_dat3
gpio3_24
Driver off
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
5
1
14
15
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
23
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
E17
rgmii0_txd1
rgmii0_txd1
mmc_dat2
gpio3_23
0
O
IO
IO
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
5
1
14
15
0
Driver off
D16
rgmii0_txd2
rgmii0_txd3
rgmii0_txd2
eCAP1_in_PWM1_out
mmc_dat1
gpio3_22
O
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv4
Yes
Yes
Dual Voltage PU/PD
LVCMOS
3
0
1
5
14
15
0
Driver off
E16
rgmii0_txd3
mmc_dat0
gpio3_21
O
IO
IO
I
PD
PD
15
1.8/3.3
vddshv4
Dual Voltage PU/PD
LVCMOS
5
1
14
15
0
Driver off
F4
J6
rstoutn
rtck
rstoutn
O
PD
PU
drive 1 (OFF)
0
0
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
rtck
0
O
IO
I
drive clk
(OFF)
Dual Voltage PU/PD
LVCMOS
gpio4_27
Driver off
spi1_sclk
uart3_rxd
gpio4_0
14
15
0
M2
L1
spi1_sclk
spi2_sclk
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
14
15
0
IO
I
Driver off
spi2_sclk
uart3_rxd
ehrpwm1A
timer3
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
1
2
O
IO
IO
I
3
gpio4_5
14
15
0
Driver off
spi1_cs0
uart3_txd
gpio4_3
R6
R5
spi1_cs0
spi1_cs1
IO
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
14
15
0
Driver off
spi1_cs1
spi3_cs1
timer6
IO
IO
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
1
1
4
ehrpwm1_tripzone_input
gpio4_4
7
0
14
15
Driver off
24
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
T5
U6
L2
spi1_d0
spi1_d1
spi2_cs0
spi1_d0
uart3_rtsn
gpio4_2
Driver off
spi1_d1
uart3_ctsn
gpio4_1
Driver off
spi2_cs0
uart3_txd
ehrpwm1B
timer4
0
IO
O
IO
I
OFF
OFF
PU
OFF
OFF
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
1
14
15
0
IO
I
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
14
15
0
IO
I
IO
O
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
1
2
3
gpio4_8
Driver off
spi2_d0
uart3_rtsn
timer1
14
15
0
R7
N4
spi2_d0
spi2_d1
IO
O
IO
IO
I
OFF
OFF
OFF
OFF
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
3
gpio4_7
sysboot7
spi2_d1
uart3_ctsn
timer5
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
1
3
IO
IO
IO
I
eCAP1_in_PWM1_out
7
0
gpio4_6
Driver off
tclk
14
15
0
J2
J1
tclk
tdi
I
PU
PU
PU
PU
0
0
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
IQ1833
PU/PD
tdi
0
I
Dual Voltage PU/PD
LVCMOS
gpio4_25
Driver off
tdo
14
15
0
IO
I
J4
tdo
O
IO
I
PU
PU
0
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
gpio4_26
Driver off
tms
14
15
0
J3
J5
tms
IO
OFF
PD
OFF
PD
0
0
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
trstn
trstn
0
I
Dual Voltage PU/PD
LVCMOS
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
25
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
F14
uart1_ctsn
uart1_ctsn
xref_clk1
uart3_rxd
gpmc_a16
spi4_sclk
spi1_cs2
0
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
I
2
I
3
O
IO
IO
IO
I
4
0
1
5
timer3
6
ehrpwm1_synci
clkout0
7
0
8
O
I
vin2a_hsync0
gpmc_a12
gpmc_clk
dcan1_tx
gpio4_15
Driver off
uart1_rtsn
uart3_txd
gpmc_a17
spi4_cs0
9
10
11
12
14
15
0
O
IO
IO
IO
I
0
C14
uart1_rtsn
O
O
O
IO
IO
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
2
3
4
1
1
spi1_cs3
5
timer4
6
ehrpwm1_synco
qspi1_rtclk
vin2a_vsync0
gpmc_a13
dcan1_rx
gpio4_16
Driver off
uart1_rxd
spi4_d1
7
8
0
9
I
10
12
14
15
0
O
IO
IO
I
F13
uart1_rxd
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
4
IO
I
qspi1_rtclk
gpmc_a12
mcan_tx
5
10
12
14
15
O
IO
IO
I
1
gpio4_13
Driver off
26
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E14
uart1_txd
uart1_txd
spi4_d0
0
O
IO
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
4
0
1
gpmc_a13
mcan_rx
gpio4_14
Driver off
uart2_ctsn
xref_clk1
gpmc_a18
spi3_sclk
qspi1_cs1
timer7
10
12
14
15
0
F15
uart2_ctsn
I
OFF
OFF
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
2
I
3
O
IO
IO
IO
I
4
0
1
5
6
vin2a_hsync0
gpmc_clk
mcan_tx
9
10
12
14
15
0
IO
IO
IO
I
0
1
gpio4_19
Driver off
uart2_rtsn
eCAP1_in_PWM1_out
gpmc_a19
spi3_cs0
F16
uart2_rtsn
O
IO
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
3
4
timer8
6
vin2a_vsync0
mcan_rx
9
12
14
15
0
IO
IO
I
1
gpio4_20
Driver off
uart2_rxd
spi3_d1
D14
uart2_rxd
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
4
IO
IO
O
IO
O
IO
IO
I
timer1
6
ehrpwm1A
gpmc_clk
gpmc_a12
dcan1_tx
7
10
11
12
14
15
0
gpio4_17
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
27
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
D15
uart2_txd
uart2_txd
spi3_d0
timer2
0
O
IO
IO
O
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
4
0
6
ehrpwm1B
gpmc_a13
dcan1_rx
gpio4_18
Driver off
vdd
7
11
12
14
15
H12, H13, H7,
J10, J11, J15,
K12, L12, L15,
N12, N16, P10,
P14
vdd
PWR
P22
A14
U19
N8
vdda_adc
vdda_adc
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
vdda_csi
vdda_csi
vdda_dac
vdda_dac
vdda_ddr_dsp
vdda_gmac_core
vdda_osc
vdda_ddr_dsp
vdda_gmac_core
vdda_osc
M8
E21
H14
vdda_per
vdda_per
G12, J7, L16,
P13, T11
vdds18v
vdds18v
P7, T9
vdds18v_ddr1
vdds18v_ddr2
vdds18v_ddr3
vddshv1
vdds18v_ddr1
vdds18v_ddr2
vdds18v_ddr3
vddshv1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
G7
T16, V21
K2, K7, L7, M7
B8, G11, G8, G9 vddshv2
vddshv2
G14
vddshv3
vddshv4
vddshv5
vddshv3
A18, E20
H17, J16, J21
vddshv4
vddshv5
AA16, T10, T12, vddshv6
T13
vddshv6
AA1, AB6, R1, T7, vdds_ddr1
T8
vdds_ddr1
PWR
C2, E2, G6
vdds_ddr2
vdds_ddr2
vdds_ddr3
vdd_dspeve
PWR
PWR
PWR
AA22, AB19, T15 vdds_ddr3
K8, L8, M9, P11, vdd_dspeve
P12, P8, P9
28
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F22
vin1a_clk0
vin1a_clk0
cpi_pclk
clkout0
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
I
4
O
IO
I
gpio1_30
Driver off
14
15
mcasp3_aclkx
G18
G21
G22
H18
H20
H19
H22
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d0
0
I
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv5
vddshv5
vddshv5
vddshv5
vddshv5
vddshv5
vddshv5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
cpi_data2
gpio2_3
1
I
14
15
IO
I
Driver off
mcasp3_axr1
vin1a_d1
cpi_data3
gpio2_4
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_axr2
vin1a_d2
cpi_data4
gpio2_5
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_axr3
vin1a_d3
cpi_data5
gpio2_6
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_axr4
vin1a_d4
cpi_data6
gpio2_7
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_axr5
vin1a_d5
cpi_data7
gpio2_8
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
xref_clk2
mcasp3_ahclkx
vin1a_d6
cpi_data8
gpio2_9
0
I
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_fsx
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
29
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
H21
vin1a_d7
vin1a_d7
cpi_data9
gpio2_10
Driver off
vin1a_d8
cpi_data10
vin1b_d0
gpmc_a8
sys_nirq2
gpio2_11
Driver off
vin1a_d9
cpi_data11
vin1b_d1
gpmc_a9
sys_nirq1
gpio2_12
Driver off
vin1a_d10
cpi_data12
vin1b_d2
gpmc_a10
sys_nirq2
gpio2_13
Driver off
vin1a_d11
cpi_data13
vin1b_d3
gpmc_a11
sys_nirq1
gpio2_14
Driver off
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
0
IO
I
J17
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
I
7
14
15
0
IO
I
K22
K21
K18
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv5
vddshv5
vddshv5
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
I
7
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
I
7
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
I
7
14
15
IO
I
30
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
K17
vin1a_d12
vin1a_d12
cpi_data14
vin1b_d4
gpmc_a12
dma_evt1
gpio2_15
Driver off
vin1a_d13
cpi_wen
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
I
6
14
15
0
IO
I
K19
vin1a_d13
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
vin1b_d5
gpmc_a13
dma_evt2
gpio2_16
Driver off
vin1a_d14
cpi_fid
2
I
3
O
I
6
14
15
0
IO
I
K20
L21
F21
vin1a_d14
vin1a_d15
vin1a_de0
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv5
vddshv5
vddshv5
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
IO
I
vin1b_d6
gpmc_a14
gpio2_17
Driver off
vin1a_d15
cpi_data15
vin1b_d7
gpmc_a15
gpio2_18
Driver off
vin1a_de0
cpi_hsync
vin1b_clk1
clkout1
2
3
O
IO
I
14
15
0
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
3
O
IO
I
14
15
0
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
IO
I
2
4
O
IO
I
gpio1_31
14
15
Driver off
atl_clk1
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
31
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
F20
vin1a_fld0
vin1a_fld0
cpi_vsync
vin2b_clk1
clkout2
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
IO
I
2
4
O
IO
I
gpio2_0
14
15
Driver off
mcasp3_aclkr
F19
vin1a_hsync0
vin1a_hsync0
cpi_data0
vin1a_de0
gpio2_1
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
I
2
I
14
15
IO
I
Driver off
mcasp3_fsr
G19
vin1a_vsync0
vin1a_vsync0
cpi_data1
gpio2_2
0
I
PD
PD
15
1.8/3.3
vddshv5
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
I
14
15
IO
I
Driver off
mcasp3_axr0
L22
vin2a_clk0
vin2a_de0
vin2a_clk0
gpio2_19
0
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv5
vddshv5
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
IO
I
Driver off
M17
vin2a_de0
cam_strobe
vin2b_hsync1
vin2b_de1
gpio4_21
I
Dual Voltage PU/PD
LVCMOS
1
O
I
2
0
0
5
I
14
15
0
IO
I
Driver off
M18
vin2a_fld0
vout1_clk
vin2a_fld0
cam_shutter
vin2b_vsync1
gpio4_22
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv5
vddshv6
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
O
I
2
0
0
14
15
0
IO
I
Driver off
AB17
vout1_clk
vin1a_d12
clkout0
O
I
Dual Voltage PU/PD
LVCMOS
2
4
O
I
vin2a_clk0
gpio2_20
9
14
15
IO
I
Driver off
32
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
U17
vout1_de
vout1_de
0
O
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_aclkx
vin1a_d13
clkout1
1
0
0
2
4
O
IO
I
gpio2_21
14
15
0
Driver off
W17
vout1_fld
vout1_fld
O
IO
I
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_fsx
vin1a_d14
clkout2
1
0
0
2
4
O
IO
I
gpio2_22
14
15
0
Driver off
AA17
vout1_hsync
vout1_hsync
mcasp1_aclkr
vin1a_d15
vin2a_de0
gpio2_23
O
IO
I
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
2
9
I
14
15
0
IO
I
Driver off
U16
W16
V16
vout1_vsync
vout1_vsync
mcasp1_fsr
vin2a_fld0
gpio2_24
O
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
9
14
15
0
IO
I
Driver off
vout1_d0
vout1_d0
O
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
mcasp1_axr0
mmc_clk
1
0
1
5
gpio2_25
14
15
0
Driver off
vout1_d1
vout1_d1
O
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
mcasp1_axr1
mmc_cmd
gpio2_26
1
0
1
5
14
15
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
33
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
U15
V15
Y15
W15
vout1_d2
vout1_d2
0
O
IO
IO
IO
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr2
mcasp1_axr8
mmc_dat0
gpio2_27
1
0
0
1
4
5
14
15
0
Driver off
vout1_d3
vout1_d4
vout1_d5
vout1_d3
O
IO
IO
IO
IO
I
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr3
mcasp1_axr9
mmc_dat1
gpio2_28
1
0
0
1
4
5
14
15
0
Driver off
vout1_d4
O
IO
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
mcasp1_axr4
mcasp1_axr10
mmc_dat2
gpio2_29
1
0
0
1
4
5
14
15
0
Driver off
vout1_d5
O
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
mcasp1_axr5
mcasp1_axr11
mmc_dat3
vin2a_clk0
gpio2_30
1
0
0
1
4
5
9
14
15
0
IO
I
Driver off
AA15
vout1_d6
vout1_d6
O
IO
IO
O
I
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr6
mcasp1_axr12
emu2
1
0
0
4
6
vin2a_de0
gpio2_31
9
14
15
IO
I
Driver off
34
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AB15
vout1_d7
vout1_d7
0
O
IO
IO
IO
O
I
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr7
eCAP1_in_PWM1_out
mcasp1_axr13
emu3
1
0
0
0
3
4
6
vin2a_fld0
gpio3_0
9
14
15
0
IO
I
Driver off
vout1_d8
mcasp1_axr8
vin2a_d0
gpmc_a20
emu4
AA14
AB14
U13
vout1_d8
vout1_d9
vout1_d10
vout1_d11
O
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
vddshv6
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_1
14
15
0
Driver off
vout1_d9
mcasp1_axr9
vin2a_d1
gpmc_a21
emu5
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_2
14
15
0
Driver off
vout1_d10
mcasp1_axr10
vin2a_d2
gpmc_a22
emu6
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_3
14
15
0
Driver off
vout1_d11
mcasp1_axr11
vin2a_d3
gpmc_a23
emu7
V13
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_4
14
15
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
35
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
Y13
W13
U11
V11
vout1_d12
vout1_d12
mcasp1_axr12
vin2a_d4
gpmc_a24
emu8
0
O
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_5
14
15
Driver off
mcasp2_ahclkx
vout1_d13
vout1_d14
vout1_d15
vout1_d13
mcasp1_axr13
vin2a_d5
gpmc_a25
emu9
0
O
IO
I
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_6
14
15
Driver off
mcasp2_aclkr
vout1_d14
mcasp1_axr14
vin2a_d6
gpmc_a26
emu10
0
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_7
14
15
Driver off
mcasp2_aclkx
vout1_d15
mcasp1_axr15
vin2a_d7
gpmc_a27
emu11
0
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
2
3
O
O
IO
I
6
gpio3_8
14
15
Driver off
mcasp2_fsx
36
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
U9
vout1_d16
vout1_d16
0
O
O
I
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_ahclkx
vin2a_d8
1
2
0
gpmc_a0
3
O
IO
I
mcasp1_axr8
vin2b_d0
4
0
0
5
emu12
6
O
IO
I
gpio3_9
14
15
Driver off
atl_clk0
W11
vout1_d17
vout1_d18
vout1_d19
vout1_d17
vin2a_d9
gpmc_a1
mcasp1_axr9
vin2b_d1
emu13
0
O
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_10
14
15
Driver off
mcasp2_fsr
V9
vout1_d18
vin2a_d10
gpmc_a2
mcasp1_axr10
vin2b_d2
emu14
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_11
14
15
Driver off
mcasp2_axr0
W9
vout1_d19
vin2a_d11
gpmc_a3
mcasp1_axr11
vin2b_d3
emu15
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_12
14
15
Driver off
mcasp2_axr1
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
37
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
[1]
U8
W8
U7
V7
vout1_d20
vout1_d20
vin2a_d12
gpmc_a4
mcasp1_axr12
vin2b_d4
emu16
0
O
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv6
vddshv6
vddshv6
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_13
14
15
Driver off
mcasp2_axr2
vout1_d21
vout1_d22
vout1_d23
vout1_d21
vin2a_d13
gpmc_a5
mcasp1_axr13
vin2b_d5
emu17
0
O
I
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_14
14
15
Driver off
mcasp2_axr3
vout1_d22
vin2a_d14
gpmc_a6
mcasp1_axr14
vin2b_d6
emu18
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_15
14
15
Driver off
mcasp2_axr4
vout1_d23
vin2a_d15
gpmc_a7
mcasp1_axr15
vin2b_d7
emu19
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
3
O
IO
I
4
0
0
5
6
O
IO
I
gpio3_16
14
15
Driver off
mcasp2_axr5
38
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
BALL
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
RESET RESET REL.
STATE [6] STATE [7]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A1, A17, A22, A8, vss
AB1, AB12, AB16,
AB2, AB21, AB22,
AB7, B22, E1,
vss
GND
G10, G16, H10,
H11, H15, H16,
H8, H9, J22, K1,
K10, K11, K13,
K14, K15, K16,
K9, M10, M11,
M12, M13, M16,
N10, N7, P1, P15,
P16, R12, R16,
R9, T14, V22
P21
B14
T19
D21
C22
E22
vssa_adc
vssa_csi
vssa_adc
vssa_csi
vssa_dac
vssa_osc0
vssa_osc1
xi_osc0
GND
GND
GND
GND
GND
I
vssa_dac
vssa_osc0
vssa_osc1
xi_osc0
0
0
1.8
vdda_osc
vdda_osc
vdda_osc
vdda_osc
vddshv1
Yes
LVCMOS
Analog
B21
D22
C21
M1
xi_osc1
xo_osc0
xo_osc1
xref_clk0
xi_osc1
xo_osc0
xo_osc1
0
0
0
I
0
1.8
Yes
Yes
Yes
Yes
LVCMOS
Analog
O
O
0
1.8
LVCMOS
Analog
0
1.8
LVCMOS
Analog
xref_clk0
clkout0
0
I
PD
PD
15
1.8/3.3
Dual Voltage PU/PD
LVCMOS
1
O
IO
IO
IO
IO
IO
I
spi3_cs0
spi2_cs1
spi1_cs0
spi1_cs1
gpio3_31
Driver off
4
1
1
1
1
5
6
7
14
15
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Section 5.4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) In PUx / PDy, x and y = 60 to 300 μA.
The output impedance settings (or drive strengths) of this IO are programmable (60 Ω, 80 Ω, 120 Ω) depending on the values of the I[2:0] registers.
4.3 Signal Descriptions
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
39
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options.
1. SIGNAL NAME: The name of the signal passing through the pin.
注
The subsystem multiplexing signals are not described in 表 4-1 and 表 4-29.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or output
D = Open Drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
4. BALL: Associated ball(s) bottom
注
For more information, see the Control Module / Control Module Register Manual section of the Device TRM.
4.3.1 VIP
注
For more information, see the Video Input Port (VIP) section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid for VIN1 and
VIN2 if signals within a single IOSET are used. The IOSETs are defined in 表 5-28 and 表 5-29.
表 4-2. VIP Signal Descriptions
SIGNAL NAME
Video Input 1
DESCRIPTION
TYPE
BALL
40
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vin1a_clk0
Video Input 1 Port A Clock input. Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on
the CLK0 edge.
I
F22
vin1a_d0
vin1a_d1
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Field ID input
Video Input 1 Port A Field ID input
Video Input 1 Port A Horizontal Sync input
Video Input 1 Port A Vertical Sync input
Video Input 1 Port B Clock input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Field ID input
Video Input 1 Port B Horizontal Sync input
Video Input 1 Port B Vertical Sync input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
G18
G21
vin1a_d2
G22
vin1a_d3
H18
vin1a_d4
H20
vin1a_d5
H19
vin1a_d6
H22
vin1a_d7
H21
vin1a_d8
J17
vin1a_d9
K22
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_de0
vin1a_fld0
vin1a_hsync0
vin1a_vsync0
vin1b_clk1
vin1b_d0
K21
K18
AB17, K17
K19, U17
K20, W17
AA17, L21
F19, F21
F20
F19
G19
F21
J17
vin1b_d1
K22
vin1b_d2
K21
vin1b_d3
K18
vin1b_d4
K17
vin1b_d5
K19
vin1b_d6
K20
vin1b_d7
L21
vin1b_de1
vin1b_hsync1
vin1b_vsync1
W7
W7
W6
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
41
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
Video Input 2
DESCRIPTION
TYPE
BALL
vin2a_clk0
vin2a_d0
Video Input 2 Port A Clock input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Field ID input
Video Input 2 Port A Field ID input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AB17, L22, W15
AA14
vin2a_d1
AB14
vin2a_d2
U13
vin2a_d3
V13
vin2a_d4
Y13
vin2a_d5
W13
vin2a_d6
U11
vin2a_d7
V11
vin2a_d8
U9
vin2a_d9
W11
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2b_clk1
vin2b_d0
V9
W9
U8
W8
U7
V7
AA15, AA17, M17, W7
AB15, M18, U16
Video Input 2 Port A Horizontal Sync input
Video Input 2 Port A Vertical Sync input
Video Input 2 Port B Clock input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Field ID input
Video Input 2 Port B Horizontal Sync input
F14, F15, W7
C14, F16, W6
F20
U9
vin2b_d1
W11
V9
vin2b_d2
vin2b_d3
W9
U8
vin2b_d4
vin2b_d5
W8
U7
vin2b_d6
vin2b_d7
V7
vin2b_de1
vin2b_hsync1
M17
M17
42
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
vin2b_vsync1
DESCRIPTION
Video Input 2 Port B Vertical Sync input
TYPE
BALL
I
M18
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
43
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.2 DSS
表 4-3. DSS Signal Descriptions
SIGNAL NAME
DPI Video Output 1
vout1_clk
DESCRIPTION
TYPE
BALL
Video Output 1 Clock output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AB17
W16
V16
U15
V15
Y15
W15
AA15
AB15
AA14
AB14
U13
V13
Y13
W13
U11
V11
U9
vout1_d0
vout1_d1
vout1_d2
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_de
W11
V9
W9
U8
W8
U7
V7
Video Output 1 Data Enable output
U17
W17
AA17
vout1_fld
Video Output 1 Field ID output.This signal is not used for embedded sync modes.
vout1_hsync
Video Output 1 Horizontal Sync output.This signal is not used for embedded sync
modes.
vout1_vsync
Video Output 1 Vertical Sync output.This signal is not used for embedded sync modes.
O
U16
4.3.3 SD_DAC
注
For more information, see theVideo Encoder / Video Encoder Overview of the Device TRM.
表 4-4. CVIDEO SD_DAC Signal Descriptions
SIGNAL NAME
cvideo_tvout
cvideo_vfb
DESCRIPTION
TYPE
BALL
T17
SD_DAC TV analog composite output
SD_DAC input feedback thru resistor to out
SD_DAC input reference current resistor setting
A
A
A
P17
cvideo_rset
T18
44
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.4 ADC
注
For more information, see the ADC / ADC Overview of the Device TRM.
表 4-5. ADC Signal Descriptions
SIGNAL NAME
adc_in0
DESCRIPTION
TYPE
BALL
M19
M20
M21
M22
N22
N21
P19
P18
P20
ADC analog channel input 0
ADC analog channel input 1
ADC analog channel input 2
ADC analog channel input 3
ADC analog channel input 4
ADC analog channel input 5
ADC analog channel input 6
ADC analog channel input 7
ADC positive reference voltage
A
A
A
A
A
A
A
A
A
adc_in1
adc_in2
adc_in3
adc_in4
adc_in5
adc_in6
adc_in7
adc_vrefp
4.3.5 Camera Control
注
Camera Control is not available on this device, and must be left unconnected.
注
For more information, see the Imaging Subsystem (ISS) section of the Device TRM.
表 4-6. Camera Control Signal Descriptions
SIGNAL NAME
cam_strobe
cam_shutter
cam_nreset
DESCRIPTION
TYPE
BALL
A6, B18, C16, M17
C6, C18, C17, M18
W6
Camera flash activation trigger
Camera mechanical shutter control
Camera sensor reset
O
O
IO
4.3.6 CPI
注
CPI is not available on this device, and must be left unconnected.
表 4-7. CPI Signal Descriptions
SIGNAL NAME
cpi_pclk
DESCRIPTION
TYPE
BALL
F22
Camera pixel clock
I
IO
IO
I
cpi_hsync
cpi_vsync
cpi_data0
cpi_data1
cpi_data2
cpi_data3
cpi_data4
Camera horizontal synchonization
Camera vertical synchonization
Camera parallel data 0
Camera parallel data 1
Camera parallel data 2
Camera parallel data 3
Camera parallel data 4
F21
F20
F19
I
G19
G18
G21
G22
I
I
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
45
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-7. CPI Signal Descriptions (continued)
SIGNAL NAME
cpi_data5
cpi_data6
cpi_data7
cpi_data8
cpi_data9
cpi_data10
cpi_data11
cpi_data12
cpi_data13
cpi_data14
cpi_data15
cpi_wen
DESCRIPTION
TYPE
BALL
H18
H20
H19
H22
H21
J17
Camera parallel data 5
I
I
Camera parallel data 6
Camera parallel data 7
I
Camera parallel data 8
I
Camera parallel data 9
I
Camera parallel data 10
I
Camera parallel data 11
I
K22
K21
K18
K17
L21
Camera parallel data 12
I
Camera parallel data 13
I
Camera parallel data 14
I
Camera parallel data 15
I
Camera parallel external write enable
Camera parallel field identification for interlaced sensors (i mode)
I
K19
K20
cpi_fid
IO
46
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.7 CSI2
注
ISS is not available on this device, and must be left unconnected.
注
For more information, see the Imaging Subsystem of the Device TRM.
表 4-8. CSI 2 Signal Descriptions
SIGNAL NAME
csi2_0_dx0
csi2_0_dy0
csi2_0_dx1
csi2_0_dy1
csi2_0_dx2
csi2_0_dy2
csi2_0_dx3
csi2_0_dy3
csi2_0_dx4
csi2_0_dy4
DESCRIPTION
TYPE
BALL
A11
B11
A12
B12
A13
B13
A15
B15
A16
B16
Serial Differential data/clock positive input - lane 0 (position 1)
Serial Differential data/clock negative input - lane 0 (position 1)
Serial Differential data/clock positive input - lane 1 (position 2)
Serial Differential data/clock negative input - lane 1 (position 2)
Serial Differential data/clock positive input - lane 2 (position 3)
Serial Differential data/clock negative input - lane 2 (position 3)
Serial Differential data/clock positive input - lane 3 (position 4)
Serial Differential data/clock negative input - lane 3 (position 4)
Serial Differential data positive input only - lane 4 (position 5) (1)
Serial Differential data negative input only - lane 4 (position 5) (1)
I
I
I
I
I
I
I
I
I
I
(1) Lane 4 (position 5) supports only data. For more information see Imaging Subsystem of the Device TRM.
4.3.8 EMIF
注
For more information, see the Memory Subsystem / EMIF Controller section of the Device
TRM.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-9, EMIF
Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type of
SDRAM memories.
表 4-9. EMIF Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
F3
ddr1_cke0
ddr1_nck
ddr1_odt0
ddr1_rasn
ddr1_rst
EMIF1 Clock Enable 0
EMIF1 Negative Clock
EMIF1 On-Die Termination for Chip Select 0
EMIF1 Row Address Strobe
EMIF1 Reset output
O
G2
P2
O
O
F1
O
N1
E3
ddr1_wen
ddr1_csn0
ddr1_ck
EMIF1 Write Enable
O
EMIF1 Chip Select 0
O
B2
EMIF1 Clock
O
G1
F2
ddr1_casn
ddr1_ba0
ddr1_ba1
ddr1_ba2
EMIF1 Column Address Strobe
EMIF1 Bank Address
O
O
B3
EMIF1 Bank Address
O
A3
EMIF1 Bank Address
O
D2
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
47
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-9. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
U4
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
O
C1
O
D3
O
R4
O
T4
O
N3
O
T2
O
N2
O
T1
O
U1
O
D1
O
R3
O
U2
O
C3
O
R2
O
V1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA6
AA8
Y8
AA7
AB4
Y5
AA4
Y6
AA18
Y21
AA21
Y22
AA19
AB20
Y17
AB18
AA3
AA2
Y3
V2
U3
V3
Y2
Y1
U21
T20
R21
U20
R22
V20
W22
48
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-9. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
U22
ddr1_d31
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
ddr1_dqs0
EMIF1 Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 Data Mask
Y11
AA12
AA11
Y9
AA13
AB11
AA9
AB9
AB8
Y18
EMIF1 Data Mask
EMIF1 Data Mask
AB3
W21
AB13
AA5
EMIF1 Data Mask
EMIF1 ECC Data Mask
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
IO
IO
AA20
W1
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
T21
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
Data strobe 0 invert
Data strobe 1 invert
Data strobe 2 invert
Data strobe 3 invert
IO
IO
IO
IO
IO
IO
AB5
Y20
W2
T22
ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe
AB10
AA10
ddr1_dqs_ecc
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
4.3.9 GPMC
注
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the Device TRM.
表 4-10. GPMC Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO
E8
A7
F8
B7
A6
F7
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
IO
IO
IO
IO
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
49
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-10. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad6
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
IO
E7
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
C6
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
B6
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
A5
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
D6
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
C5
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
B5
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
D7
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
B4
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
A4
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
U9
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
O
W11
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
O
V9
gpmc_a3
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
O
W9
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
O
U8
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
O
W8
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
O
U7
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
O
V7
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
O
J17
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
O
K22
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
O
K21
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K18
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
D14, F13, F14, K17
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
C14, D15, E14, K19
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K20
L21
F14
C14
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
50
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-10. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
F15
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
O
O
O
O
O
O
O
O
F16
AA14
AB14
U13
V13
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
Y13
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
W13
U11
V11
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
gpmc_cs0
gpmc_cs1
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC Chip Select 4 (active low)
GPMC Chip Select 5 (active low)
GPMC Chip Select 6 (active low)
GPMC Chip Select 7 (active low)
GPMC Clock output
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
I
C10
E10
gpmc_cs2
D10
gpmc_cs3
A9
gpmc_cs4
B9
gpmc_cs5
F10
gpmc_cs6
C8
gpmc_cs7
W6
gpmc_clk(1)
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_wait1
C12, D14, F14, F15
GPMC address valid active low or address latch enable
GPMC output enable active low or read enable
GPMC write enable active low
F12
A10
B10
D12
E12
D8
GPMC lower-byte enable active low
GPMC upper-byte enable active low
GPMC external indication of wait 0
GPMC external indication of wait 1
I
W7
(1) The gpio6_16.clkout0 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See 表 5-32, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load and 表 5-34,
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads for timing information.
4.3.10 Timers
注
For more information, see the Timers section of the Device TRM.
表 4-11. Timers Signal Descriptions
SIGNAL NAME
timer1
DESCRIPTION
TYPE
IO
BALL
D14, R7
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
timer2
IO
D15, D6
timer3
IO
C5, F14, L1
C14, C6, L2
timer4
IO
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
51
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-11. Timers Signal Descriptions (continued)
SIGNAL NAME
timer5
DESCRIPTION
TYPE
IO
BALL
E7, N4
F7, R5
B6, F15
F16
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
timer6
IO
timer7
IO
timer8
IO
4.3.11 I2C
注
For more information, see the Serial Communication Interface / Multimaster I2C Controller /
I2C Environment / I2C Pins for Typical Connections in I2C Mode section of the Device TRM.
表 4-12. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface (I2C1)
i2c1_scl
I2C1 Clock
I2C1 Data
IOD
IOD
L3
L4
i2c1_sda
Inter-Integrated Circuit Interface (I2C2)
i2c2_scl
I2C2 Clock
I2C2 Data
IOD
IOD
L6
L5
i2c2_sda
4.3.12 UART
注
For more information see the Serial Communication Interface UART section of the Device
TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-43.
表 4-13. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Asynchronous Receiver/Transmitter (UART1)
uart1_ctsn
uart1_rtsn
uart1_rxd
uart1_txd
UART1 clear to send active low
UART1 request to send active low
UART1 Receive Data
I
F14
C14
F13
E14
O
I
UART1 Transmit Data
O
Universal Asynchronous Receiver/Transmitter (UART2)
uart2_ctsn
uart2_rtsn
uart2_rxd
uart2_txd
UART2 clear to send active low
UART2 request to send active low
UART2 Receive Data
I
F15
F16
O
I
D14, E7
D15, F7
UART2 Transmit Data
O
Universal Asynchronous Receiver/Transmitter (UART3)
uart3_ctsn UART3 clear to send active low
I
N4, U6
52
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-13. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
uart3_rtsn
uart3_rxd
uart3_txd
UART3 request to send active low
UART3 Receive Data
O
I
R7, T5
F14, L1, M2, W7
C14, L2, R6, W6
UART3 Transmit Data
O
4.3.13 McSPI
注
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (McSPI) section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are applicable for all combinations of signals for SPI2 and SPI4.
However, the timings are only valid for SPI1 and SPI3 if signals within a single
IOSET are used. The IOSETs are defined in 表 5-46.
表 4-14. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Serial Peripheral Interface 1
spi1_sclk
spi1_d0
spi1_d1
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
SPI1 Clock
IO
IO
IO
IO
IO
IO
IO
M2
T5
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Chip Select
U6
M1, R6
M1, R5
F14, W7
C14, W6
SPI1 Chip Select
SPI1 Chip Select
SPI1 Chip Select
Serial Peripheral Interface 2
spi2_sclk
spi2_d0
spi2_d1
spi2_cs0
spi2_cs1
SPI2 Clock
IO
IO
IO
IO
IO
L1
R7
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Chip Select
N4
A4, L2
B4, M1
SPI2 Chip Select
Serial Peripheral Interface 3
spi3_sclk
spi3_d0
spi3_d1
spi3_cs0
spi3_cs1
SPI3 Clock
IO
IO
IO
IO
IO
C6, F15
D15, E7
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Chip Select
D14, F7
B6, F16, M1
A5, R5
SPI3 Chip Select
Serial Peripheral Interface 4
spi4_sclk
spi4_d0
spi4_d1
spi4_cs0
SPI4 Clock
IO
IO
IO
IO
C16, F14
B17, E14
B19, F13
C14, C17
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Chip Select
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
53
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.14 QSPI
注
For more information see the Serial Communication Interface / Quad Serial Peripheral
Interface section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-49.
表 4-15. QSPI Signal Descriptions
SIGNAL NAME
qspi1_sclk
DESCRIPTION
TYPE
BALL
C8
QSPI1 Serial Clock
O
I
qspi1_rtclk
QSPI1 Return Clock Input.Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
B7, C14, D8, F13
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
B9
qspi1_d1
qspi1_d2
QSPI1 Data[1]. Input read data in all modes.
IO
IO
F10
A9
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
IO
D10
qspi1_cs0
qspi1_cs1
QSPI1 Chip Select[0]. This pin is used for QSPI1 boot modes.
QSPI1 Chip Select[1]
IO
IO
E10
F15
4.3.15 McASP
注
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-56.
表 4-16. McASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Multichannel Audio Serial Port 1
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
McASP1 Transmit/Receive Data
IO
IO
IO
IO
IO
IO
W16
V16
U15
V15
Y15
W15
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
54
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-16. McASP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
BALL
AA15
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_fsx
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit Frame Sync
McASP1 Receive Bit Clock
AB15
AA14, U15, U9
AB14, V15, W11
U13, V9, Y15
V13, W15, W9
AA15, U8, Y13
AB15, W13, W8
U11, U7
V11, V7
W17
mcasp1_aclkr
mcasp1_fsr
AA17
McASP1 Receive Frame Sync
McASP1 Transmit High-Frequency Master Clock
McASP1 Transmit Bit Clock
U16
mcasp1_ahclkx
mcasp1_aclkx
U9
IO
U17
Multichannel Audio Serial Port 2
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
mcasp2_axr5
mcasp2_fsx
McASP2 Transmit/Receive Data
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
D6, V9
C5, W9
B5, U8
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit Frame Sync
McASP2 Receive Bit Clock
D7, W8
B4, U7
A4, V7
E7, V11
B6, W13
A5, W11
C6, Y13
F7, U11
mcasp2_aclkr
mcasp2_fsr
McASP2 Receive Frame Sync
McASP2 Transmit High-Frequency Master Clock
McASP2 Transmit Bit Clock
mcasp2_ahclkx
mcasp2_aclkx
IO
Multichannel Audio Serial Port 3
mcasp3_axr0
mcasp3_axr1
mcasp3_axr2
mcasp3_axr3
mcasp3_axr4
mcasp3_axr5
mcasp3_fsx
McASP3 Transmit/Receive Data
IO
IO
IO
IO
IO
IO
IO
O
G19
G18
G21
G22
H18
H20
H22
H19
F22
F20
F19
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit Frame Sync
McASP3 Transmit High-Frequency Master Clock
McASP3 Transmit Bit Clock
mcasp3_ahclkx
mcasp3_aclkx
mcasp3_aclkr
mcasp3_fsr
IO
IO
IO
McASP3 Receive Bit Clock
McASP3 Receive Frame Sync
4.3.16 DCAN and MCAN
注
For more information, see the Serial Communication Interface / DCAN section of the Device
TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
55
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-60.
表 4-17. DCAN and MCAN Signal Descriptions
SIGNAL NAME
DCAN 1
DESCRIPTION
TYPE
BALL
dcan1_rx
dcan1_tx
DCAN1 receive data pin
DCAN1 transmit data pin
IO
IO
C14, D15, N6
D14, F14, N5
MCAN
mcan_rx
mcan_tx
MCAN receive data pin
MCAN transmit data pin
IO
IO
E14, F16, W6
F13, F15, W7
4.3.17 GMAC_SW
注
For more information, see the Serial Communication Interfaces / Gigabit Ethernet Switch
(GMAC_SW) section of the Device TRM.
表 4-18. GMAC Signal Descriptions
SIGNAL NAME
rgmii0_rxc
DESCRIPTION
TYPE
BALL
B18
C18
A20
C20
B20
A19
C16
C17
F17
E17
D16
E16
D7
RGMII0 Receive Clock
RGMII0 Receive Control
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Transmit Clock
RGMII0 Transmit Enable
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII1 Receive Clock
RGMII1 Receive Control
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Transmit Clock
RGMII1 Transmit Enable
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
Management Data
I
I
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
I
I
I
I
O
O
O
O
O
O
I
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd0
rgmii1_rxd1
rgmii1_rxd2
rgmii1_rxd3
rgmii1_txc
I
C10
F8
I
I
A7
I
E8
I
D8
O
O
O
O
O
O
IO
C12
D12
B10
A10
F12
E12
B17
rgmii1_txctl
rgmii1_txd0
rgmii1_txd1
rgmii1_txd2
rgmii1_txd3
mdio_d
56
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-18. GMAC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
Management Data Serial Clock
TYPE
BALL
mdio_mclk
O
B19
4.3.18 SDIO Controller
注
For more information, see the SDIO Controller section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-75.
表 4-19. SDIO Controller Signal Descriptions
SIGNAL NAME
Multi Media Card 1
mmc_clk
DESCRIPTION
TYPE
BALL
MMC1 clock
IO
IO
IO
IO
IO
IO
B18, C16, W16
C17, C18, V16
A19, E16, U15
B20, D16, V15
C20, E17, Y15
A20, F17, W15
mmc_cmd
MMC1 command
MMC1 data bit 0
MMC1 data bit 1
MMC1 data bit 2
MMC1 data bit 3
mmc_dat0
mmc_dat1
mmc_dat2
mmc_dat3
4.3.19 GPIO
注
For more information, see the General-Purpose Interface section of the Device TRM.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in 表 5-76.
表 4-20. GPIOs Signal Descriptions
SIGNAL NAME
GPIO 1
DESCRIPTION
TYPE
BALL
gpio1_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
C12
D12
E12
F12
A10
B10
C10
E10
gpio1_1
gpio1_2
gpio1_3
gpio1_4
gpio1_5
gpio1_6
gpio1_7
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
57
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-20. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio1_8
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
D10
A9
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
gpio1_9
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
B9
F10
C8
D8
E8
A7
F8
B7
A6
F7
E7
C6
B6
A5
D6
C5
B5
D7
B4
A4
F22
F21
GPIO 2
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_20
gpio2_21
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
F20
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
J17
K22
K21
K18
K17
K19
K20
L21
L22
AB17
U17
58
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-20. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
gpio2_29
gpio2_30
gpio2_31
GPIO 3
DESCRIPTION
TYPE
IO
BALL
W17
AA17
U16
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
W16
V16
IO
IO
U15
IO
V15
IO
Y15
IO
W15
AA15
IO
gpio3_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AB15
AA14
AB14
U13
V13
Y13
W13
U11
V11
U9
gpio3_1
gpio3_2
gpio3_3
gpio3_4
gpio3_5
gpio3_6
gpio3_7
gpio3_8
gpio3_9
gpio3_10
gpio3_11
gpio3_12
gpio3_13
gpio3_14
gpio3_15
gpio3_16
gpio3_17
gpio3_18
gpio3_19
gpio3_20
gpio3_21
gpio3_22
gpio3_23
gpio3_24
gpio3_25
gpio3_26
gpio3_27
gpio3_28
gpio3_29
gpio3_30
gpio3_31
GPIO 4
W11
V9
W9
U8
W8
U7
V7
B19
B17
C16
C17
E16
D16
E17
F17
B18
C18
A19
B20
C20
A20
M1
gpio4_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
M2
U6
T5
gpio4_1
gpio4_2
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
59
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-20. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio4_3
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
R6
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
gpio4_4
R5
gpio4_5
L1
gpio4_6
N4
gpio4_7
R7
gpio4_8
L2
gpio4_9
N5
gpio4_10
gpio4_11
gpio4_12
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_19
gpio4_20
gpio4_21
gpio4_22
gpio4_25
gpio4_26
gpio4_27
gpio4_28(1)
gpio4_29(1)
N6
W7
W6
F13
E14
F14
C14
D14
D15
F15
F16
M17
M18
J1
J4
J6
H1
H2
(1) gpio4_28 is multiplexed with EMU0 and gpio4_29 is multiplexed with EMU1. These pins will be sampled at reset release by the test and
emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can
be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
4.3.20 ePWM
注
For more information, see Pulse Width Modulation Subsystem (PWMSS) section of the
Device TRM.
表 4-21. PWM Signal Descriptions
SIGNAL NAME
PWMSS1
DESCRIPTION
TYPE
BALL
ehrpwm1A
ehrpwm1B
EHRPWM1 Output A
O
O
D12, D14, L1
D15, E12, L2
F12, R5
EHRPWM1 Output B
ehrpwm1_tripzone_input
eCAP1_in_PWM1_out
EHRPWM1 Trip Zone Input
ECAP1 Capture Input / PWM Output
IO
IO
A5, AB15, D16, F16,
N4
ehrpwm1_synci
ehrpwm1_synco
EHRPWM1 Sync Input
EHRPWM1 Sync Output
I
A10, F14
B10, C14
O
60
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.21 ATL
注
For more information, see the Audio Tracking Logic (ATL) section of the Device TRM.
表 4-22. ATL Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
U9
atl_clk0
atl_clk1
Audio Tracking Logic Clock 0
Audio Tracking Logic Clock 1
O
F21
4.3.22 Test Interfaces
注
For more information, see the On-Chip Debug Support section of the Device TRM.
表 4-23. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
JTAG return clock
JTAG test clock
JTAG test data
TYPE
BALL
J6
rtck
tclk
tdi
O
I
J2
I
J1
tdo
tms
JTAG test port data
O
IO
J4
JTAG test port mode select. An external pullup resistor should be used on this
ball.
J3
trstn
emu0(1)
emu1(1)
emu2
JTAG test reset
Emulator pin 0
Emulator pin 1
Emulator pin 2
Emulator pin 3
Emulator pin 4
Emulator pin 5
Emulator pin 6
Emulator pin 7
Emulator pin 8
Emulator pin 9
Emulator pin 10
Emulator pin 11
Emulator pin 12
Emulator pin 13
Emulator pin 14
Emulator pin 15
Emulator pin 16
Emulator pin 17
Emulator pin 18
Emulator pin 19
I
J5
H1
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
H2
AA15
AB15
AA14
AB14
U13
V13
Y13
W13
U11
V11
U9
emu3
emu4
emu5
emu6
emu7
emu8
emu9
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
W11
V9
W9
U8
W8
U7
V7
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
61
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) EMU0 and EMU1 are multiplexed with GPIO. These pins will be sampled at reset release by the test and emulation logic. Therefore, if
they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven
from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
4.3.23 System and Miscellaneous
4.3.23.1 Sysboot
注
For more information, see the Initialization (ROM Code) section of the Device TRM.
表 4-24. Sysboot Signal Descriptions
SIGNAL NAME DESCRIPTION
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
TYPE
BALL
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
sysboot10
sysboot11
sysboot12
sysboot13
sysboot14
sysboot15
I
E8
will determine the boot mode configuration of the device.
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
A7
F8
B7
A6
F7
E7
R7
B6
A5
D6
C5
B5
D7
B4
A4
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
4.3.23.2 Power, Reset and Clock Management (PRCM)
注
For more information, see Power, Reset, and Clock Management section of the Device TRM.
62
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-25. PRCM Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
clkout0
Device Clock output 1. Can be used externally for devices with non-critical timing
requirements, or for debug, or as a reference clock on GPMC as described in 表 5-
32 ,GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1
Load and 表 5-34, GPMC/NOR Flash Interface Switching Characteristics -
Synchronous Mode - 5 Loads.
O
AB17, C12, F14, F22,
M1
clkout1
clkout2
rstoutn
Device Clock output 2. Can be used as a system clock for other devices.
Device Clock output 3. Can be used as a system clock for other devices.
O
O
O
F12, F21, U17
A10, F20, W17
F4
Reset out (Active low). This pin asserts low in response to any global reset condition
on the device.
resetn
porz
Device Reset Input
I
I
G4
G3
Power on Reset (active low). This pin must be asserted low until all device supplies
are valid (see reset sequence/requirements).
xref_clk0
xref_clk1
xref_clk2
xi_osc0
External Reference Clock 0. For Audio and other Peripherals.
External Reference Clock 1. For Audio and other Peripherals.
External Reference Clock 2. For Audio and other Peripherals.
I
I
I
I
M1
F14, F15
H19
System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input
connection to a crystal when the internal oscillator OSC0 is used. Functions as an
LVCMOS-compatible input clock when an external oscillator is used.
E22
xi_osc1
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the
input connection to a crystal when the internal oscillator OSC1 is used. Functions as
an LVCMOS-compatible input clock when an external oscillator is used
I
B21
xo_osc0
xo_osc1
System Oscillator OSC0 Crystal output
Auxiliary Oscillator OSC1 Crystal output
O
O
D22
C21
4.3.23.3 Enhanced Direct Memory Access (EDMA)
注
For more information, see the DMA Controllers / Enhanced DMA section of the Device TRM.
表 4-26. EDMA Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
C12, K17
D12, K19
E12
dma_evt1
dma_evt2
dma_evt3
dma_evt4
Enhanced DMA Event Input 1
Enhanced DMA Event Input 2
Enhanced DMA Event Input 3
Enhanced DMA Event Input 4
I
I
I
I
F12, D8
4.3.23.4 Interrupt Controllers (INTC)
注
For more information, see the Interrupt Controllers section of the Device TRM.
表 4-27. INTC Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
nmin
Non maskable interrupt input - active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the Arm cores.
I
G5
sys_nirq1
sys_nirq2
External interrupt event to any device INTC
External interrupt event to any device INTC
I
I
K18, K22
J17, K21
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
63
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.3.24 Power Supplies
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the Device TRM.
表 4-28. Power Supply Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vdd
Core voltage domain supply
PWR
H7 , H12 , H13 , J10 ,
J11 , J15 , K12 , L12 ,
L15 , N12 , N16 ,
P10 , P14
vss
Ground
GND
A1 , A8 , A17 , A22 ,
B22 , E1 , G10 ,
G16 , H8 , H9 , H10 ,
H11 , H15 , H16 ,
J22 , K1 , K9 , K10 ,
K11 , K13 , K14 ,
K15 , K16 , M10 ,
M11 , M12 , M13 ,
M16 , N7 , N10 , P1 ,
P15 , P16 , R9 , R12 ,
R16 , T14 , V22 ,
AB1 , AB2 , AB7 ,
AB12 , AB16 , AB21 ,
AB22
vdd_dspeve
DSP-EVE voltage domain supply
PWR
K8 , L8 , M9 , P8 ,
P9 , P11 , P12
vdda_per
PER PLL and PER HSDIVIDER analog power supply
PWR
PWR
PWR
H14
N8
vdda_ddr_dsp
vdda_gmac_core
EVE PLL, DPLL_DDR and DDR HSDIVIDER analog power supply
GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER
analog power supply
M8
vdda_osc
vssa_osc0
vssa_osc1
vdda_csi
vssa_csi
IO supply for oscillator section
OSC0 analog ground
PWR
GND
GND
PWR
GND
PWR
GND
PWR
GND
PWR
E21
D21
C22
A14
B14
U19
T19
P22
P21
OSC1 analog ground
CSI analog power supply
CSI analog ground
vdda_dac
vssa_dac
vdda_adc
vssa_adc
vdds18v
DAC analog power supply
DAC analog ground
ADC analog power supply
ADC analog ground
1.8V power supply and Power Group bias supply
G12, J7, L16, P13,
T11
vdds18v_ddr1
vdds18v_ddr2
vdds18v_ddr3
vdds_ddr1
1.8v bias supply for Byte0, Byte2, ECC Byte, Addr Cmd
1.8v bias supply for Addr Cmd
PWR
PWR
PWR
PWR
PWR
PWR
PWR
P7, T9
G7
1.8v bias supply for Byte1, Byte3
T16, V21
IO power supply for Byte0, Byte2, ECC Byte, Addr Cmd
IO power supply for Addr Cmd
R1, T7, T8, AA1, AB6
C2, E2, G6
vdds_ddr2
vdds_ddr3
IO power supply for Byte1, Byte3
T15, AA22, AB19
K2, K7, L7, M7
vddshv1
Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power
Group pins
vddshv2
vddshv3
Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group
pins
PWR
PWR
G8, G9, G11, B8
G14
Dual Voltage (1.8V or 3.3V) power supply for the UART1 and UART2
Power Group pins
64
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-28. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vddshv4
vddshv5
vddshv6
Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group
pins
PWR
A18, E20
Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group
pins
PWR
PWR
H17, J16, J21
Dual Voltage (1.8V or 3.3V) power supply for the VOUT1 Power Group
pins
T10, T12, T13, AA16
cap_vddram_core1(1)
cap_vddram_core2(1)
cap_vddram_dspeve(1)
SRAM array supply for core voltage domain memories
SRAM array supply for core voltage domain memories
SRAM array supply for DSP-EVE memories
CAP
CAP
CAP
N15
M15
M14
(1) This pin must always be connected via a 1-uF capacitor to vss.
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
65
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.4 Pin Multiplexing
表 4-29 describes the device pin multiplexing (no characteristics are provided in this table).
注
表 4-29, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in 节
4.3, Signal Descriptions.
注
For more information, see the Control Module / Control Module Functional Description / Pad Configuration Registers section of the Device
TRM.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (Hi-Z mode is not an input signal).
注
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
注
In some cases 表 4-29 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function
as selected via CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
CAUTION
The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid if signals
within a single IOSET are used. The IOSETs are defined in the corresponding tables.
66
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
E22
xi_osc0
N2
ddr1_a7
AB4
W1
U3
ddr1_d4
ddr1_dqs2
ddr1_d20
ddr1_a1
C1
M19
U1
adc_in0
ddr1_a9
Y6
ddr1_d7
A15
V1
csi2_0_dx3
ddr1_a15
ddr1_d17
ddr1_a8
AA2
T1
R3
ddr1_a11
ddr1_d16
ddr1_d23
ddr1_d14
ddr1_dqs1
ddr1_d0
AA3
Y1
Y17
AA20
AA6
F3
ddr1_cke0
ddr1_dqsn1
adc_in5
Y20
N21
T2
ddr1_a6
W2
E3
ddr1_dqsn2
ddr1_wen
adc_in7
P18
AA11
ddr1_ecc_d
2
B3
ddr1_ba0
cvideo_tvout
ddr1_d30
xi_osc1
T17
W22
B21
V3
ddr1_d21
ddr1_d25
csi2_0_dx0
ddr1_nck
ddr1_d24
T20
A11
G2
U21
Y9
ddr1_ecc_d
3
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
67
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
R21
U4
ddr1_d26
ddr1_a0
AB18
A3
ddr1_d15
ddr1_ba1
ddr1_ba2
csi2_0_dy3
ddr1_d10
ddr1_d1
D2
B15
AA21
AA8
B13
AB8
M22
D1
csi2_0_dy2
ddr1_dqm0
adc_in3
ddr1_a10
ddr1_d18
xo_osc1
Y3
C21
M20
R22
AA9
adc_in1
ddr1_d28
ddr1_ecc_d
6
N3
ddr1_a5
ddr1_odt0
ddr1_a4
P2
T4
AB10
ddr1_dqsn_
ecc
AB3
ddr1_dqm2
AA12
ddr1_ecc_d
1
AA4
T18
N22
R4
ddr1_d6
cvideo_rset
adc_in4
ddr1_a3
ddr1_d29
V20
AB13
ddr1_dqm_e
cc
AA5
A16
R2
ddr1_dqs0
csi2_0_dx4
ddr1_a14
ddr1_d22
ddr1_d9
Y2
Y21
W21
P20
ddr1_dqm3
adc_vrefp
68
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
Y5
ddr1_d5
F2
ddr1_casn
ddr1_d13
csi2_0_dy0
AB20
B11
AB9
ddr1_ecc_d
7
D22
U2
xo_osc0
ddr1_a12
adc_in6
P19
AA18
U22
Y18
A13
T22
G1
ddr1_d8
ddr1_d31
ddr1_dqm1
csi2_0_dx2
ddr1_dqsn3
ddr1_ck
P17
G3
cvideo_vfb
porz
T21
Y22
AA19
AB5
U20
AA13
ddr1_dqs3
ddr1_d11
ddr1_d12
ddr1_dqsn0
ddr1_d27
ddr1_ecc_d
4
B16
F1
csi2_0_dy4
ddr1_rasn
ddr1_a2
D3
AA10
ddr1_dqs_e
cc
AA7
B2
ddr1_d3
ddr1_csn0
ddr1_rst
N1
V2
ddr1_d19
ddr1_d2
Y8
B12
C3
csi2_0_dy1
ddr1_a13
csi2_0_dx1
A12
AB11
ddr1_ecc_d
5
M21
adc_in2
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
69
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
Y11
ddr1_ecc_d
0
0x1400
0x1404
0x1408
0x140C
0x1410
0x1414
0x1418
0x141C
0x1420
0x1424
0x1428
0x142C
0x1430
0x1434
0x1438
0x143C
0x1440
0x1444
0x1448
0x144C
CTRL_CORE_PAD_ C12
GPMC_CLK
gpmc_clk
rgmii1_txc
clkout0
dma_evt1
dma_evt2
dma_evt3
dma_evt4
gpio1_0
gpio1_1
gpio1_2
gpio1_3
gpio1_4
gpio1_5
gpio1_6
gpio1_7
gpio1_8
gpio1_9
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
CTRL_CORE_PAD_ D12
GPMC_BEN0
gpmc_ben0 rgmii1_txctl
gpmc_ben1 rgmii1_txd3
ehrpwm1A
ehrpwm1B
CTRL_CORE_PAD_ E12
GPMC_BEN1
CTRL_CORE_PAD_ F12
GPMC_ADVN_ALE
gpmc_advn_ rgmii1_txd2
ale
ehrpwm1_tri clkout1
pzone_input
CTRL_CORE_PAD_ A10
GPMC_OEN_REN
gpmc_oen_r rgmii1_txd1
en
ehrpwm1_sy clkout2
nci
CTRL_CORE_PAD_ B10
GPMC_WEN
gpmc_wen rgmii1_txd0
ehrpwm1_sy
nco
CTRL_CORE_PAD_ C10
GPMC_CS0
gpmc_cs0
gpmc_cs1
gpmc_cs2
gpmc_cs3
gpmc_cs4
gpmc_cs5
gpmc_cs6
rgmii1_rxctl
qspi1_cs0
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d1
qspi1_sclk
CTRL_CORE_PAD_ E10
GPMC_CS1
CTRL_CORE_PAD_ D10
GPMC_CS2
CTRL_CORE_PAD_ A9
GPMC_CS3
CTRL_CORE_PAD_ B9
GPMC_CS4
CTRL_CORE_PAD_ F10
GPMC_CS5
CTRL_CORE_PAD_ C8
GPMC_CS6
CTRL_CORE_PAD_ D8
GPMC_WAIT0
gpmc_wait0 rgmii1_rxd3 qspi1_rtclk
gpmc_ad0 rgmii1_rxd2
gpmc_ad1 rgmii1_rxd1
gpmc_ad2 rgmii1_rxd0
gpmc_ad3 qspi1_rtclk
dma_evt4
CTRL_CORE_PAD_ E8
GPMC_AD0
CTRL_CORE_PAD_ A7
GPMC_AD1
CTRL_CORE_PAD_ F8
GPMC_AD2
CTRL_CORE_PAD_ B7
GPMC_AD3
CTRL_CORE_PAD_ A6
GPMC_AD4
gpmc_ad4 cam_strobe
CTRL_CORE_PAD_ F7
GPMC_AD5
gpmc_ad5
uart2_txd
uart2_rxd
timer6
spi3_d1
sysboot5
mcasp2_acl
kx
0x1450
0x1454
CTRL_CORE_PAD_ E7
GPMC_AD6
gpmc_ad6
timer5
timer4
spi3_d0
gpio1_20
gpio1_21
sysboot6
mcasp2_fsx
CTRL_CORE_PAD_ C6
GPMC_AD7
gpmc_ad7 cam_shutter
spi3_sclk
Driver off
mcasp2_ahc
lkx
70
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x1458
CTRL_CORE_PAD_ B6
GPMC_AD8
gpmc_ad8
timer7
spi3_cs0
gpio1_22
sysboot8
mcasp2_acl
kr
0x145C
0x1460
CTRL_CORE_PAD_ A5
GPMC_AD9
gpmc_ad9
eCAP1_in_P spi3_cs1
WM1_out
gpio1_23
gpio1_24
sysboot9
mcasp2_fsr
CTRL_CORE_PAD_ D6
GPMC_AD10
gpmc_ad10
timer2
sysboot10
mcasp2_axr
0
0x1464
0x1468
0x146C
0x1470
0x1474
0x1478
CTRL_CORE_PAD_ C5
GPMC_AD11
gpmc_ad11
gpmc_ad12
timer3
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
sysboot11
mcasp2_axr
1
CTRL_CORE_PAD_ B5
GPMC_AD12
sysboot12
mcasp2_axr
2
CTRL_CORE_PAD_ D7
GPMC_AD13
gpmc_ad13 rgmii1_rxc
gpmc_ad14
sysboot13
mcasp2_axr
3
CTRL_CORE_PAD_ B4
GPMC_AD14
spi2_cs1
spi2_cs0
clkout0
sysboot14
mcasp2_axr
4
CTRL_CORE_PAD_ A4
GPMC_AD15
gpmc_ad15
sysboot15
mcasp2_axr
5
CTRL_CORE_PAD_ F22
VIN1A_CLK0
vin1a_clk0 cpi_pclk
Driver off
mcasp3_acl
kx
0x147C
0x1480
CTRL_CORE_PAD_ F21
VIN1A_DE0
vin1a_de0
vin1a_fld0
cpi_hsync
cpi_vsync
vin1b_clk1
vin2b_clk1
clkout1
clkout2
gpio1_31
gpio2_0
Driver off
atl_clk1
CTRL_CORE_PAD_ F20
VIN1A_FLD0
Driver off
mcasp3_acl
kr
0x1484
0x1488
CTRL_CORE_PAD_ F19
VIN1A_HSYNC0
vin1a_hsync cpi_data0
0
vin1a_de0
gpio2_1
gpio2_2
Driver off
mcasp3_fsr
CTRL_CORE_PAD_ G19
VIN1A_VSYNC0
vin1a_vsync cpi_data1
0
Driver off
mcasp3_axr
0
0x148C
0x1490
0x1494
0x1498
0x149C
CTRL_CORE_PAD_ G18
VIN1A_D0
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
cpi_data2
cpi_data3
cpi_data4
cpi_data5
cpi_data6
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
Driver off
mcasp3_axr
1
CTRL_CORE_PAD_ G21
VIN1A_D1
Driver off
mcasp3_axr
2
CTRL_CORE_PAD_ G22
VIN1A_D2
Driver off
mcasp3_axr
3
CTRL_CORE_PAD_ H18
VIN1A_D3
Driver off
mcasp3_axr
4
CTRL_CORE_PAD_ H20
VIN1A_D4
Driver off
mcasp3_axr
5
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
71
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x14A0
CTRL_CORE_PAD_ H19
VIN1A_D5
vin1a_d5
cpi_data7
gpio2_8
xref_clk2
mcasp3_ahc
lkx
0x14A4
0x14A8
0x14AC
0x14B0
0x14B4
0x14B8
0x14BC
0x14C0
0x14C4
0x14C8
0x14CC
0x14D0
0x14D4
0x14D8
0x14DC
0x14E0
0x14E4
0x14E8
0x14EC
0x14F0
0x14F4
0x14F8
CTRL_CORE_PAD_ H22
VIN1A_D6
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin2a_clk0
vin2a_de0
vin2a_fld0
vout1_clk
vout1_de
vout1_fld
cpi_data8
cpi_data9
gpio2_9
Driver off
mcasp3_fsx
CTRL_CORE_PAD_ H21
VIN1A_D7
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio4_21
gpio4_22
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ J17
VIN1A_D8
cpi_data10 vin1b_d0
cpi_data11 vin1b_d1
cpi_data12 vin1b_d2
cpi_data13 vin1b_d3
cpi_data14 vin1b_d4
gpmc_a8
sys_nirq2
sys_nirq1
sys_nirq2
sys_nirq1
CTRL_CORE_PAD_ K22
VIN1A_D9
gpmc_a9
CTRL_CORE_PAD_ K21
VIN1A_D10
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
CTRL_CORE_PAD_ K18
VIN1A_D11
CTRL_CORE_PAD_ K17
VIN1A_D12
dma_evt1
dma_evt2
CTRL_CORE_PAD_ K19
VIN1A_D13
cpi_wen
cpi_fid
vin1b_d5
vin1b_d6
CTRL_CORE_PAD_ K20
VIN1A_D14
CTRL_CORE_PAD_ L21
VIN1A_D15
cpi_data15 vin1b_d7
CTRL_CORE_PAD_ L22
VIN2A_CLK0
CTRL_CORE_PAD_ M17
VIN2A_DE0
cam_strobe vin2b_hsync
1
vin2b_de1
CTRL_CORE_PAD_ M18
VIN2A_FLD0
cam_shutter vin2b_vsync
1
CTRL_CORE_PAD_ AB17
VOUT1_CLK
vin1a_d12
clkout0
clkout1
clkout2
vin2a_clk0
CTRL_CORE_PAD_ U17
VOUT1_DE
mcasp1_acl vin1a_d13
kx
CTRL_CORE_PAD_ W17
VOUT1_FLD
mcasp1_fsx vin1a_d14
CTRL_CORE_PAD_ AA17
VOUT1_HSYNC
vout1_hsync mcasp1_acl vin1a_d15
kr
vin2a_de0
vin2a_fld0
CTRL_CORE_PAD_ U16
VOUT1_VSYNC
vout1_vsync mcasp1_fsr
CTRL_CORE_PAD_ W16
VOUT1_D0
vout1_d0
vout1_d1
vout1_d2
vout1_d3
mcasp1_axr
0
mmc_clk
CTRL_CORE_PAD_ V16
VOUT1_D1
mcasp1_axr
1
mmc_cmd
CTRL_CORE_PAD_ U15
VOUT1_D2
mcasp1_axr
2
mcasp1_axr mmc_dat0
8
CTRL_CORE_PAD_ V15
VOUT1_D3
mcasp1_axr
3
mcasp1_axr mmc_dat1
9
72
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x14FC
0x1500
0x1504
0x1508
0x150C
0x1510
0x1514
0x1518
0x151C
CTRL_CORE_PAD_ Y15
VOUT1_D4
vout1_d4
mcasp1_axr
4
mcasp1_axr mmc_dat2
10
gpio2_29
Driver off
CTRL_CORE_PAD_ W15
VOUT1_D5
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
mcasp1_axr
5
mcasp1_axr mmc_dat3
11
vin2a_clk0
vin2a_de0
vin2a_fld0
gpio2_30
gpio2_31
gpio3_0
gpio3_1
gpio3_2
gpio3_3
gpio3_4
gpio3_5
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ AA15
VOUT1_D6
mcasp1_axr
6
mcasp1_axr
12
emu2
emu3
emu4
emu5
emu6
emu7
emu8
CTRL_CORE_PAD_ AB15
VOUT1_D7
mcasp1_axr
7
eCAP1_in_P mcasp1_axr
WM1_out
13
CTRL_CORE_PAD_ AA14
VOUT1_D8
mcasp1_axr vin2a_d0
8
gpmc_a20
CTRL_CORE_PAD_ AB14
VOUT1_D9
mcasp1_axr vin2a_d1
9
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
CTRL_CORE_PAD_ U13
VOUT1_D10
vout1_d10 mcasp1_axr vin2a_d2
10
CTRL_CORE_PAD_ V13
VOUT1_D11
vout1_d11 mcasp1_axr vin2a_d3
11
CTRL_CORE_PAD_ Y13
VOUT1_D12
vout1_d12 mcasp1_axr vin2a_d4
12
Driver off
mcasp2_ahc
lkx
0x1520
0x1524
CTRL_CORE_PAD_ W13
VOUT1_D13
vout1_d13 mcasp1_axr vin2a_d5
13
gpmc_a25
gpmc_a26
emu9
gpio3_6
gpio3_7
Driver off
mcasp2_acl
kr
CTRL_CORE_PAD_ U11
VOUT1_D14
vout1_d14 mcasp1_axr vin2a_d6
14
emu10
Driver off
mcasp2_acl
kx
0x1528
0x152C
0x1530
0x1534
CTRL_CORE_PAD_ V11
VOUT1_D15
vout1_d15 mcasp1_axr vin2a_d7
15
gpmc_a27
gpmc_a0
gpmc_a1
gpmc_a2
emu11
emu12
emu13
emu14
gpio3_8
gpio3_9
gpio3_10
gpio3_11
Driver off
mcasp2_fsx
CTRL_CORE_PAD_ U9
VOUT1_D16
vout1_d16 mcasp1_ahc vin2a_d8
lkx
mcasp1_axr vin2b_d0
8
Driver off
atl_clk0
CTRL_CORE_PAD_ W11
VOUT1_D17
vout1_d17
vin2a_d9
mcasp1_axr vin2b_d1
9
Driver off
mcasp2_fsr
CTRL_CORE_PAD_ V9
VOUT1_D18
vout1_d18
vin2a_d10
mcasp1_axr vin2b_d2
10
Driver off
mcasp2_axr
0
0x1538
0x153C
0x1540
0x1544
0x1548
CTRL_CORE_PAD_ W9
VOUT1_D19
vout1_d19
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
mcasp1_axr vin2b_d3
11
emu15
emu16
emu17
emu18
emu19
gpio3_12
gpio3_13
gpio3_14
gpio3_15
gpio3_16
Driver off
mcasp2_axr
1
CTRL_CORE_PAD_ U8
VOUT1_D20
mcasp1_axr vin2b_d4
12
Driver off
mcasp2_axr
2
CTRL_CORE_PAD_ W8
VOUT1_D21
mcasp1_axr vin2b_d5
13
Driver off
mcasp2_axr
3
CTRL_CORE_PAD_ U7
VOUT1_D22
mcasp1_axr vin2b_d6
14
Driver off
mcasp2_axr
4
CTRL_CORE_PAD_ V7
VOUT1_D23
mcasp1_axr vin2b_d7
15
Driver off
mcasp2_axr
5
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
73
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x154C
0x1550
0x1554
0x1558
0x155C
0x1560
0x1564
0x1568
0x156C
0x1570
0x1574
0x1578
0x157C
0x1580
0x1584
0x1588
0x158C
0x1590
0x1594
0x1598
0x159C
0x15A0
0x15A4
0x15A8
CTRL_CORE_PAD_ W7
MCAN_TX
mcan_tx
vin2a_de0
vin2a_hsync spi1_cs2
0
uart3_rxd
gpmc_wait1 vin1b_hsync vin1b_de1
1
gpio4_11
gpio4_12
gpio3_17
gpio3_18
gpio3_19
gpio3_20
gpio3_21
gpio3_22
gpio3_23
gpio3_24
gpio3_25
gpio3_26
gpio3_27
gpio3_28
gpio3_29
gpio3_30
gpio3_31
gpio4_0
Driver off
CTRL_CORE_PAD_ W6
MCAN_RX
mcan_rx
cam_nreset vin2a_vsync spi1_cs3
0
uart3_txd
spi4_d1
spi4_d0
gpmc_cs7
vin1b_vsync
1
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ B19
MDIO_MCLK
mdio_mclk
mdio_d
CTRL_CORE_PAD_ B17
MDIO_D
CTRL_CORE_PAD_ C16
RGMII0_TXC
rgmii0_txc
rgmii0_txctl
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
xref_clk0
cam_strobe spi4_sclk
cam_shutter spi4_cs0
mmc_clk
CTRL_CORE_PAD_ C17
RGMII0_TXCTL
mmc_cmd
mmc_dat0
mmc_dat1
mmc_dat2
mmc_dat3
mmc_clk
CTRL_CORE_PAD_ E16
RGMII0_TXD3
CTRL_CORE_PAD_ D16
RGMII0_TXD2
eCAP1_in_P
WM1_out
CTRL_CORE_PAD_ E17
RGMII0_TXD1
CTRL_CORE_PAD_ F17
RGMII0_TXD0
CTRL_CORE_PAD_ B18
RGMII0_RXC
cam_strobe
cam_shutter
CTRL_CORE_PAD_ C18
RGMII0_RXCTL
mmc_cmd
mmc_dat0
mmc_dat1
mmc_dat2
mmc_dat3
spi2_cs1
CTRL_CORE_PAD_ A19
RGMII0_RXD3
CTRL_CORE_PAD_ B20
RGMII0_RXD2
CTRL_CORE_PAD_ C20
RGMII0_RXD1
CTRL_CORE_PAD_ A20
RGMII0_RXD0
CTRL_CORE_PAD_ M1
XREF_CLK0
clkout0
spi3_cs0
spi1_cs0
spi1_cs1
CTRL_CORE_PAD_ M2
SPI1_SCLK
spi1_sclk
spi1_d1
uart3_rxd
uart3_ctsn
uart3_rtsn
uart3_txd
spi3_cs1
uart3_rxd
uart3_ctsn
CTRL_CORE_PAD_ U6
SPI1_D1
gpio4_1
CTRL_CORE_PAD_ T5
SPI1_D0
spi1_d0
gpio4_2
CTRL_CORE_PAD_ R6
SPI1_CS0
spi1_cs0
gpio4_3
CTRL_CORE_PAD_ R5
SPI1_CS1
spi1_cs1
timer6
ehrpwm1_tri
pzone_input
gpio4_4
CTRL_CORE_PAD_ L1
SPI2_SCLK
spi2_sclk
spi2_d1
ehrpwm1A timer3
timer5
gpio4_5
CTRL_CORE_PAD_ N4
SPI2_D1
eCAP1_in_P
WM1_out
gpio4_6
74
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x15AC
0x15B0
0x15B8
0x15B4
0x15BC
0x15C0
0x15C4
0x15C8
0x15CC
0x15D0
0x15D4
0x15D8
0x15DC
0x15E0
0x15E4
0x15E8
0x15EC
0x15F0
0x15F4
0x15F8
0x15FC
0x1600
0x1604
0x1608
CTRL_CORE_PAD_ R7
SPI2_D0
spi2_d0
uart3_rtsn
timer1
gpio4_7
sysboot7
CTRL_CORE_PAD_ L2
SPI2_CS0
spi2_cs0
dcan1_rx
dcan1_tx
uart1_rxd
uart1_txd
uart3_txd
ehrpwm1B timer4
gpio4_8
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ N6
DCAN1_RX
gpio4_10
gpio4_9
CTRL_CORE_PAD_ N5
DCAN1_TX
CTRL_CORE_PAD_ F13
UART1_RXD
spi4_d1
spi4_d0
qspi1_rtclk
gpmc_a12
gpmc_a13
mcan_tx
mcan_rx
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_19
gpio4_20
CTRL_CORE_PAD_ E14
UART1_TXD
CTRL_CORE_PAD_ F14
UART1_CTSN
uart1_ctsn xref_clk1
uart1_rtsn
uart3_rxd
uart3_txd
gpmc_a16 spi4_sclk
gpmc_a17 spi4_cs0
spi3_d1
spi1_cs2
spi1_cs3
timer3
ehrpwm1_sy clkout0
nci
vin2a_hsync gpmc_a12 gpmc_clk
0
dcan1_tx
CTRL_CORE_PAD_ C14
UART1_RTSN
timer4
timer1
timer2
timer7
timer8
ehrpwm1_sy qspi1_rtclk vin2a_vsync gpmc_a13
dcan1_rx
nco
0
CTRL_CORE_PAD_ D14
UART2_RXD
uart2_rxd
ehrpwm1A
gpmc_clk
gpmc_a12 dcan1_tx
gpmc_a13 dcan1_rx
mcan_tx
CTRL_CORE_PAD_ D15
UART2_TXD
uart2_txd
spi3_d0
ehrpwm1B
CTRL_CORE_PAD_ F15
UART2_CTSN
uart2_ctsn
xref_clk1
gpmc_a18 spi3_sclk
gpmc_a19 spi3_cs0
qspi1_cs1
vin2a_hsync gpmc_clk
0
CTRL_CORE_PAD_ F16
UART2_RTSN
uart2_rtsn
i2c1_sda
i2c1_scl
i2c2_sda
i2c2_scl
tms
eCAP1_in_P
WM1_out
vin2a_vsync
0
mcan_rx
CTRL_CORE_PAD_ L4
I2C1_SDA
CTRL_CORE_PAD_ L3
I2C1_SCL
CTRL_CORE_PAD_ L5
I2C2_SDA
CTRL_CORE_PAD_ L6
I2C2_SCL
CTRL_CORE_PAD_ J3
TMS
CTRL_CORE_PAD_ J1
TDI
tdi
gpio4_25
gpio4_26
Driver off
Driver off
CTRL_CORE_PAD_ J4
TDO
tdo
CTRL_CORE_PAD_ J2
TCLK
tclk
CTRL_CORE_PAD_ J5
TRSTN
trstn
CTRL_CORE_PAD_ J6
RTCK
rtck
gpio4_27
gpio4_28
gpio4_29
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ H1
EMU0
emu0
emu1
CTRL_CORE_PAD_ H2
EMU1
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
75
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 4-29. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0x160C
0x1610
0x1614
CTRL_CORE_PAD_ G4
RESETN
resetn
CTRL_CORE_PAD_ G5
NMIN
nmin
CTRL_CORE_PAD_ F4
RSTOUTN
rstoutn
1. NA in table stands for Not Applicable.
76
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
4.5 Connections for Unused Pins
This section describes the connection requirements of the unused and reserved balls.
注
The following balls are reserved: A2 / F6 / A21 / B1
These balls must be left unconnected.
注
All unused power supply balls must be supplied with the voltages specified in the
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are
included in 节 4.3, Signal Descriptions.
表 4-30. Unused Balls Specific Connection Requirements
Balls
Connection Requirements
These balls must be connected to GND through an external pull
resistor if unused
B21 / E22 / J5 / AA10 / AA5 / AA20 / W1 / T21
These balls must be connected to the corresponding power supply
through an external pull resistor if unused
J2 / G5 / G4 / L3 / L4 / AB10 / J3 / AB5 / Y20 / W2 / T22 / L6 / L5
M19 / M20 / M21 / M22 / N22 / N21 / P19 / P18 / P20
These balls must be connected together to GND through a single
external 10k-ohm resistor if unused.
注
All other unused signal balls with a Pad Configuration Register can be left unconnected with
their internal pullup or pulldown resistor enabled.
注
All other unused signal balls without Pad Configuration Register can be left unconnected.
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
77
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5 Specifications
注
For more information, see Power, Reset and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 节 4.3.8,
EMIF, column "SIGNAL NAME" are not to be confused with DDR1 type of SDRAM
memories.
注
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
78
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
MIN
-0.3
-0.3
MAX
1.5
UNIT
V
VSUPPLY (Steady-State)
Supply Voltage Ranges (Steady-
State)
Core (vdd, vdd_dspeve)
Analog (vdda_per, vdda_ddr_dsp,
vdda_gmac_core, vdda_osc,
vdda_csi, vdda_dac, vdda_adc)
2.0
V
vdds_ddr1, vdds_ddr2, vdds_ddr3
(1.35V mode)
-0.3
-0.3
-0.3
-0.3
1.65
1.8
V
V
V
V
vdds_ddr1, vdds_ddr2, vdds_ddr3
(1.5V mode)
vdds_ddr1, vdds_ddr2, vdds_ddr3
(1.8V mode)
2.1
vdds18v, vdds18v_ddr1,
2.1
vdds18v_ddr2, vdds18v_ddr3
vddshv1-6 (1.8V mode)
vddshv1-6 (3.3V mode)
Core I/Os
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
2.1
3.8
1.5
2.0
1.65
1.8
2.1
3.8
105
V
V
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
V
Analog I/Os
V
I/O 1.35V
V
I/O 1.5V
V
1.8V I/Os
V
3.3V I/Os
V
SR
Maximum slew rate, all supplies
V/s
V
VIO (Transient Overshoot /
Undershoot)
Input and Output Voltage Ranges (Transient Overshoot / Undershoot)
Note: valid for up to 20% of the signal period
0.2×VDD
(4)
TJ
Operating junction temperature range Automotive
-40
-55
+125
+150
100
°C
°C
mA
V
TSTG
Storage temperature range after soldered onto PC Board
I-test(5), All I/Os (if different levels then one line per level)
Over-voltage Test(6), All supplies (if different levels then one line per level)
Latch-up I-Test
Latch-up OV-Test
-100
N/A
1.5×Vsup
ply max
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Section 5.4, Recommended Operating
Conditions, is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) See I/Os supplied by this power pin in 表 4-1 Pin Attributes.
(4) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(5) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(6) Per JEDEC JESD78 at 125°C.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-Body model (HBM), per AEC Q100-002(1)
All pins
VESD Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (A1,
AB1, A22, AB22)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Power on Hour (POH) Limits
IP
Duty Cycle
Voltage Domain
Voltage (V) (max)
Frequency (MHz)
(max)
Tj(°C)
POH
20000
All
100%
All
All Support OPPs
Automotive Profile(1)
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
79
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Power on Hour (POH) Limits (continued)
(1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
10%@125°C.
80
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
See 节 5.5
See 节 5.5
1.80
V
V
V
vdd_dspeve
vdda_per
DSP-EVE voltage domain supply
PER PLL and PER HSDIVIDER
analog power supply
1.71
1.71
1.71
1.836
1.836
1.836
1.89
1.89
1.89
Maximum noise (peak-peak)
50
mVPPmax
V
vdda_ddr_dsp
EVE PLL, DPLL_DDR and DDR
HSDIVIDER analog power supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
V
vdda_gmac_core
GMAC PLL, GMAC HSDIVIDER,
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.80
Maximum noise (peak-peak)
I/O supply for oscillator section
Maximum noise (peak-peak)
CSI analog power supply
50
1.80
50
mVPPmax
vdda_osc
vdda_csi
vdda_dac
vdda_adc
vdds18v
1.71
1.71
1.71
1.71
1.71
1.836
1.836
1.836
1.836
1.836
1.89
1.89
1.89
1.89
1.89
V
mVPPmax
1.80
50
V
Maximum noise (peak-peak)
DAC analog power supply
Maximum noise (peak-peak)
ADC analog power supply
Maximum noise (peak-peak)
mVPPmax
1.80
50
V
mVPPmax
V
1.80
50
mVPPmax
V
1.8V power supply and Power Group
bias supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
V
vdds18v_ddr1
1.8v bias supply for Byte0, Byte2,
ECC Byte, Addr Cmd
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
1.8v bias supply for Addr Cmd
Maximum noise (peak-peak)
1.8v bias supply for Byte1, Byte3
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdds18v_ddr2
vdds18v_ddr3
vdds_ddr1
1.71
1.71
1.28
1.836
1.836
1.377
1.89
1.89
1.42
V
mVPPmax
V
1.80
50
mVPPmax
V
EMIF power supply
1.35-V
Mode
1.35
(1.8V for DDR2 mode /
1.5V for DDR3 mode /
1.35V DDR3L mode)
1.5-V Mode
1.8-V Mode
1.43
1.71
1.50
1.80
50
1.53
1.57
1.89
1.836
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
vdds_ddr2
EMIF power supply
1.35-V
Mode
1.28
1.35
1.377
1.42
V
(1.8V for DDR2 mode /
1.5V for DDR3 mode /
1.35V DDR3L mode)
1.5-V Mode
1.8-V Mode
1.43
1.71
1.50
1.80
50
1.53
1.57
1.89
1.836
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
81
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
vdds_ddr3
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
EMIF power supply
1.35-V
Mode
1.28
1.35
1.377
1.42
V
(1.8V for DDR2 mode /
1.5V for DDR3 mode /
1.35V DDR3L mode)
1.5-V Mode
1.8-V Mode
1.43
1.71
1.50
1.80
50
1.53
1.57
1.89
1.836
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
1.8-V Mode
3.3-V Mode
vddshv1
vddshv2
vddshv3
vddshv4
vddshv5
vddshv6
Dual Voltage (1.8V or
3.3V) power supply for
the GENERAL Power
Group pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the GPMC Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the UART1 and UART2
Power Group pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the VIN1 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the VOUT1 Power
Group pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
vss
Ground supply
0
0
0
0
0
0
V
V
vssa_osc0
vssa_osc1
vssa_csi
vssa_dac
vssa_adc
OSC0 analog ground
OSC1 analog ground
CSI analog ground supply
DAC analog ground supply
ADC analog ground supply
V
V
V
V
(1)
TJ
Operating junction
temperature range
Automotive
-40
125(4)
°C
(1) Refer to Power on Hours table for limitations.
82 Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) The TSHUT feature of the SoC resets the device by default when one of the on-die temp sensors reports 123 °C. This is intended to
protect the device from exceeding 125 °C. Though not recommended, the TSHUT temperature threshold can be modified in software if
other mechanisms are in place to avoid exceeding 125 °C. Refer to the device TRM for details on the TSHUT feature.
5.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
表 5-1 describes the maximum supported frequency per speed grade for the devices.
表 5-1. Speed Grade Maximum Frequency
DEVICE SPEED
MAXIMUM FREQUENCY (MHz)
DSP
500
EVE
500
667
900
IPU
L3
DDR3/DDR3L
532 (DDR-1066)
532 (DDR-1066)
532 (DDR-1066)
DDR2
ADC
20
DRA78xxD
DRA78xxR
DRA78xxS
212.8
212.8
212.8
266
266
266
400 (DDR-800)
400 (DDR-800)
400 (DDR-800)
750
20
1000
20
5.5.1 AVS Requirements
Adaptive Voltage Scaling (AVS) is required on most of the vdd_* supplies as defined in 表 5-2.
表 5-2. AVS Requirements per vdd_* Supply
SUPPLY
vdd
AVS REQUIRED?
Yes, for all OPPs
Yes, for all OPPs
vdd_dspeve
5.5.2 Voltage And Core Clock Specifications
表 5-3 shows the recommended OPP per voltage domain.
表 5-3. Voltage Domains Operating Performance Points
OPP_NOM
OPP_OD
OPP_HIGH/OPP_PLUS(6)
DOMAIN
CONDITION
MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX DC (3) MAX (2)
BOOT (Before
AVS is enabled)
1.02
1.06
AVS
1.11
1.20
Not Applicable
Not Applicable
Not Applicable
Not Applicable
(4)
VD_CORE (V)
AVS
After AVS is
enabled (4)
Voltage
Voltage
(5)
–
(5)
3.5%
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
83
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-3. Voltage Domains Operating Performance Points (continued)
OPP_NOM
OPP_OD
OPP_HIGH/OPP_PLUS(6)
DOMAIN
CONDITION
MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX DC (3) MAX (2)
BOOT (Before
AVS is enabled)
1.02
1.06
AVS
1.11
1.11
Not Applicable
AVS
Not Applicable
(4)
VD_DSPEVE
(V)
AVS
AVS
AVS
AVS
AVS
AVS
AVS
After AVS is
enabled (4)
Voltage
Voltage
Voltage
Voltage
Voltage Voltage
Voltage Voltage (5) Voltage
(5)
(5)
(5)
–
–
–
(5)
(5)
(5)
(5) + 5%
+ 2%
(5) + 5%
3.5%
3.5%
3.5%
(1) In a typical implementation, the power supply should target the NOM voltage.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(5) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The
power supply should be adjustable over the following ranges for each required OPP:
–
–
–
–
OPP_NOM: 0.85V - 1.06V
OPP_OD: 0.94V - 1.15V
OPP_HIGH: 1.05V - 1.25V
OPP_PLUS: 1.05V - 1.25V
The AVS Voltages will be within the above specified ranges.
(6) The required PRCM and DCC software configuration sequence for OPP_PLUS (DSP 1 GHz or EVE 900 MHz) is different than other
OPPs. For details refer to DRA78x SoC for Automotive Infotainment Silicon Revision 2.0, section titled "PRCM Software Configuration
for OPP_PLUS".
表 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.
表 5-4. Supported OPP vs Max Frequency(1)(2)
DESCRIPTION
OPP_NOM
OPP_OD
OPP_HIGH
OPP_PLUS
MAX FREQ. (MHz)
MAX FREQ. (MHz)
MAX FREQ. (MHz)
MAX FREQ. (MHz)
VD_DSPEVE
DSP_CLK
EVE_FCLK
VD_CORE
CORE_IPU1_CLK
L3_CLK
500
500
709
667
750
667
1000
900
212.8
266
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DDR3 / DDR3L
DDR2
532 (DDR-1066)
400 (DDR-800)
20
ADC
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see 表 5-1).
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. 表 5-5 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
84
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
ADC
OCP_CLK
ADC_CLK
Int
133
20
L4PER2_L3_GICLK
ADC_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
SYS_CLK2
OSC1
XREF_CLK0
xref_clk0
DPLL_CORE
DPLL_CORE
OSC1
ATL
ATL_ICLK_L3
ATLPCLK
Int
266
266
ATL_L3_GICLK
ATL_GFCLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
Func
RTC Oscillator
OSC0
COUNTER_32K COUNTER_32K_FC
LK
Func
Int
0.032
38.4
5
FUNC_32K_CLK
WKUPAON_GICLK
L3INSTR_TS_GCLK
SYS_CLK1/610
SYS_CLK1
COUNTER_32K_IC
LK
OSC0
CTRL_MODULE_ L3INSTR_TS_GCLK
BANDGAP
Int
SYS_CLK1
ABE_LP_CLK
CORE_X2_CLK
OSC0
DPLL_DDR
DPLL_CORE
CTRL_MODULE_ L4CFG_L4_GICLK
CORE
Int
Int
133
L4_ICLK
CTRL_MODULE_ WKUPAON_GICLK
WKUP
38.4
WKUPAON_GICLK
SYS_CLK1
ABE_LP_CLK
SYS_CLK1
OSC0
DPLL_DDR
OSC0
DCAN1
DCAN1_FCLK
Func
Int
20
DCAN1_SYS_CLK
WKUPAON_GICLK
SYS_CLK2
OSC1
DCAN1_ICLK
133
SYS_CLK1
OSC0
ABE_LP_CLK
MCAN_CLK
DPLL_DDR
DPLL_GMAC_DSP
DPLL_CORE
DPLL_DDR
MCAN
MCAN_FCLK
MCAN_ICLK
Func
Int
80
133
MCAN_CLK
L4PER2_L3_GICLK
EMIF_DLL_GCLK
DSP1_GFCLK
CORE_X2_CLK
EMIF_DLL_GCLK
DSP_GFCLK
DLL
EMIF_DLL_FCLK
DSP1_FICLK
Func
266
DSP1
Int & Func
DSP_CLK
DPLL_EVE_VID_DS
P
DPLL_CORE
DPLL_GMAC_DSP
DSP2
DSP2_FICLK
Int & Func
DSP_CLK
DSP2_GFCLK
DSP_GFCLK
DPLL_EVE_VID_DS
P
DPLL_CORE
DPLL_GMAC_DSP
DPLL_PER
DSS
DSS_FCK_CLK
DSS_VP_CLK
Int & Func
Func
192
165
DSS_GFCLK
VID_PIX_CLK
DSS_GFCLK
VID_PIX_CLK
DPLL_EVE_VID_DS
P
DSS DISPC
DISPC_FCK_CLK
DISPC_CLK1
Int & Func
Int
192
165
DSS_GFCLK
VID_PIX_CLK
DSS_GFCLK
VID_PIX_CLK
DPLL_PER
DPLL_EVE_VID_DS
P
EFUSE_CTRL_C
UST
ocp_clk
sys_clk
Int
133
CUSTEFUSE_L4_G
ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
Func
38.4
CUSTEFUSE_SYS_
GFCLK
OSC0
ELM
ELM_ICLK
L3_CLK
Int
Int
133
266
133
DDR
266
L4PER_L3_GICLK
EMIF_L3_GICLK
EMIF_L4_GICLK
EMIF_PHY_GCLK
EMIF_DLL_GCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
EMIF_PHY_GCLK
-
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_DDR
DPLL_DDR
EMIF_OCP_FW
L4_CLKEN
Int
EMIF_PHY
EMIF_PHY_FCLK
EMIF_DLL_FCLK
Func
Int
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
85
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
EMIF
EMIF_ICLK
EMIF_L3_ICLK
EMIF_FICLK
EVE_FCLK
Int
Int
266
266
EMIF_L3_GICLK
L3_EOCP_GICLK
CORE_X2_CLK
-
DPLL_CORE
-
Func
Func
DDR/2
EVE_FCLK
EMIF_PHY_GCLK/2 EMIF_PHY_GCLK
DPLL_DDR
DPLL_CORE
DPLL_GMAC_DSP
EVE
EVE_CLK
EVE_GCLK
EVE_GFCLK
DPLL_EVE_VID_DS
P
GMAC_SW
CPTS_RFT_CLK
Func
266
GMAC_RFT_CLK
GMAC_MAIN_CLK
L3_ICLK
DPLL_CORE
OSC0
SYS_CLK1
MAIN_CLK
MHZ_250_CLK
MHZ_5_CLK
Int
125
250
5
GMAC_250M_CLK DPLL_GMAC_DSP
Func
Func
GMII_250MHZ_CLK GMII_250MHZ_CLK DPLL_GMAC_DSP
RGMII_5MHZ_CLK RMII_50MHZ_CLK/1 DPLL_GMAC_DSP
0
MHZ_50_CLK
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_
CLK
DPLL_GMAC_DSP
GPIO1
GPIO1_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC0
OSC0
GPIO1_DBCLK
Func
0.032
WKUPAON_32K_G
FCLK
SYS_CLK1/610
GPIO2
GPIO3
GPIO4
GPIO2_ICLK
GPIO2_DBCLK
GPIO3_ICLK
GPIO3_DBCLK
GPIO4_ICLK
GPIO4_DBCLK
GPMC_ICLK
Int
Func
Int
133
0.032
133
L4PER_L3_GICLK
FUNC_32K_CLK
L4PER_L3_GICLK
FUNC_32K_CLK
L4PER_L3_GICLK
FUNC_32K_CLK
CORE_X2_CLK
SYS_CLK1/610
CORE_X2_CLK
SYS_CLK1/610
CORE_X2_CLK
SYS_CLK1/610
CORE_X2_CLK
DPLL_CORE
OSC0
DPLL_CORE
OSC0
Func
Int
0.032
133
DPLL_CORE
OSC0
Func
Int & Func
0.032
266
GPMC
I2C1
L3MAIN1_L3_GICL
K
DPLL_CORE
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
PI_L3CLK
Int
Func
133
96
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L3INIT_L3_GICLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
I2C2
Int
133
96
Func
IEEE1500_2_OC
P
Int & Func
266
IPU1
IPU1_GFCLK
Int & Func
IPU_CLK
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_DDR
DPLL_CORE
DPLL_CORE
CORE_IPU_ISS_BO
OST_CLK
L3_INSTR
L3_CLK
Int
L3_CLK
L3INSTR_L3_GICL
K
CORE_X2_CLK
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
Int
Int
Int
Int
Int
133
133
133
133
38.4
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
ABE_LP_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_DDR
DPLL_CORE
DPLL_CORE
MAILBOX1
MAILBOX2
MAILBOX1_FLCK
MAILBOX2_FLCK
Int
Int
133
133
L4CFG_L3_GICLK
L4CFG_L3_GICLK
86
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
MCASP1
MCASP1_AHCLKR
Func
50
MCASP1_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
MCASP1_AHCLKX
Func
50
MCASP1_AHCLKX
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
L4_ICLK
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_CORE
OSC0
MCASP1_FCLK
MCASP1_ICLK
Func
Int
133
266
MCASP1_AUX_GF
CLK
SYS_CLK1
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
87
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
MCASP2
MCASP2_AHCLKR
Func
50
MCASP6_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
MCASP2_AHCLKX
Func
50
MCASP4_AHCLKX
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
L4_ICLK
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_CORE
OSC0
MCASP2_FCLK
MCASP2_ICLK
Func
Int
133
133
MCASP4_AUX_GF
CLK
SYS_CLK1
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
88
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
MCASP3
MCASP3_AHCLKR
MCASP3_AHCLKX
MCASP3_FCLK
Func
50
MCASP7_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_DDR
SYS_CLK1
DPLL_PER
OSC0
XREF_CLK1
XREF_CLK2
Func
50
MCASP5_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
FUNC_24M_GFCLK
SYS_CLK1
ATL_CLK0
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
REF_CLKIN0
REF_CLKIN1
REF_CLKIN2
DPLL_CORE
OSC0
XREF_CLK1
XREF_CLK2
Func
133
MCASP5_AUX_GF
CLK
L4_ICLK
SYS_CLK1
MCASP3_ICLK
SPI1_ICLK
Int
Int
133
133
48
L4PER2_L3_GICLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
FUNC_32K_CLK
MMC4_GFCLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
SYS_CLK1/610
FUNC_192M_CLK
FUNC_48M_FCLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
OSC0
MCSPI1
MCSPI2
MCSPI3
MCSPI4
MMC1
SPI1_FCLK
SPI2_ICLK
Func
Int
133
48
SPI2_FCLK
SPI3_ICLK
Func
Int
133
48
SPI3_FCLK
SPI4_ICLK
Func
Int
133
48
SPI4_FCLK
MMC_CLK_32K
MMC_FCLK
Func
Func
Func
0.032
192
48
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
MMC_ICLK
MMU_CLK
Int
Int
133
266
L3INIT_L3_GICLK
MMU_EDMA
OCMC_RAM
OCP_WP_NOC
PWMSS1
L3MAIN1_L3_GICL
K
OCMC_L3_CLK
PICLKOCPL3
Int
Int
266
266
133
L3MAIN1_L3_GICL
K
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
L3INSTR_L3_GICL
K
PWMSS1_GICLK
Int & Func
L4PER2_L3_GICLK
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
89
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
QSPI
QSPI_ICLK
QSPI_FCLK
Int
266
128
L4PER2_L3_GICLK
QSPI_GFCLK
CORE_X2_CLK
FUNC_128M_CLK
PER_QSPI_CLK
CORE_X2_CLK
SYS_CLK1/4
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
OSC0
Func
RTI1
RTI2
OCP_CLK_PI
RTI_CLK_PI
Int
133
13
WKUPAON_GICLK
RTI1_CLK
Func
SYS_CLK2/4
OSC1
FUNC_32K_CLK
CORE_X2_CLK
SYS_CLK1/4
OSC0
OCP_CLK_PI
RTI_CLK_PI
Int
133
13
WKUPAON_GICLK
RTI2_CLK
DPLL_CORE
OSC0
Func
SYS_CLK2/4
OSC1
FUNC_32K_CLK
CORE_X2_CLK
SYS_CLK1/4
OSC0
RTI3
OCP_CLK_PI
RTI_CLK_PI
Int
133
13
WKUPAON_GICLK
RTI3_CLK
DPLL_CORE
OSC0
Func
SYS_CLK2/4
OSC1
FUNC_32K_CLK
CORE_X2_CLK
SYS_CLK1/4
OSC0
RTI4
OCP_CLK_PI
RTI_CLK_PI
Int
133
13
WKUPAON_GICLK
RTI4_CLK
DPLL_CORE
OSC0
Func
SYS_CLK2/4
OSC1
FUNC_32K_CLK
CORE_X2_CLK
SYS_CLK1/4
OSC0
RTI5
OCP_CLK_PI
RTI_CLK_PI
Int
133
13
WKUPAON_GICLK
RTI5_CLK
DPLL_CORE
OSC0
Func
SYS_CLK2/4
OSC1
FUNC_32K_CLK
VID_PIX_CLK
OSC0
SD_DAC
CLKDAC
Func
50
VID_PIX_CLK
DPLL_EVE_VID_DS
P
SL2
piclk
Int
Int
Int
IVA_GCLK
133
IVA_GCLK
IVA_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_IVA
DPLL_CORE
OSC0
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
L4CFG_L3_GICLK
WKUPAON_GICLK
133
ABE_LP_CLK
SYS_CLK1
DPLL_DDR
OSC0
TIMER1_FCLK
Func
38.4
TIMER1_GFCLK
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
CORE_X2_CLK
SYS_CLK1
xref_clk0
xref_clk1
DPLL_DDR
DPLL_CORE
OSC0
TIMER2
TIMER2_ICLK
TIMER2_FCLK
Int
133
100
L4PER_L3_GICLK
TIMER2_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
xref_clk0
xref_clk1
DPLL_DDR
90
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
TIMER3
TIMER3_ICLK
TIMER3_FCLK
Int
133
100
L4PER_L3_GICLK
TIMER3_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
CORE_X2_CLK
SYS_CLK1
xref_clk0
xref_clk1
DPLL_DDR
DPLL_CORE
OSC0
TIMER4
TIMER4_ICLK
TIMER4_FCLK
Int
133
100
L4PER_L3_GICLK
TIMER4_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
CORE_X2_CLK
SYS_CLK1
xref_clk0
xref_clk1
DPLL_DDR
DPLL_CORE
OSC0
TIMER5
TIMER5_ICLK
TIMER5_FCLK
Int
133
100
IPU_L3_GICLK
TIMER5_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
xref_clk0
xref_clk1
DPLL_DDR
CLKOUTMUX0
CLKOUTMUX0_CL
K
TIMER6
TIMER6_ICLK
TIMER6_FCLK
Int
133
100
IPU_L3_GICLK
TIMER6_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
xref_clk0
xref_clk1
DPLL_DDR
CLKOUTMUX0
CLKOUTMUX0_CL
K
TIMER7
TIMER7_ICLK
TIMER7_FCLK
Int
133
100
IPU_L3_GICLK
TIMER7_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
xref_clk0
xref_clk1
DPLL_DDR
CLKOUTMUX0
CLKOUTMUX0_CL
K
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
91
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock Type
Max. Clock PRCM Clock Name PLL / OSC / Source PLL / OSC / Source
Allowed
(MHz)
Clock Name
Name
TIMER8
TIMER8_ICLK
TIMER8_FCLK
Int
133
100
IPU_L3_GICLK
TIMER8_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
ABE_GICLK
xref_clk0
xref_clk1
DPLL_DDR
CLKOUTMUX0
CLKOUTMUX0_CL
K
TPCC
TPTC1
TPTC2
UART1
TPCC_GCLK
TPTC0_GCLK
TPTC1_GCLK
UART1_FCLK
Int
Int
266
266
266
L3MAIN1_L3_GICL
K
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
L3MAIN1_L3_GICL
K
Int
L3MAIN1_L3_GICL
K
Func
192
48
UART1_GFCLK
FUNC_192M_CLK
FUNC_48M_FCLK
CORE_X2_CLK
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
UART1_ICLK
UART2_FCLK
Int
133
192
48
L4PER_L3_GICLK
UART2_GFCLK
UART2
UART3
Func
FUNC_192M_CLK
FUNC_48M_FCLK
CORE_X2_CLK
UART2_ICLK
UART3_FCLK
Int
133
192
48
L4PER_L3_GICLK
UART3_GFCLK
Func
FUNC_192M_CLK
FUNC_48M_FCLK
CORE_X2_CLK
UART3_ICLK
VCP1_CLK
Int
Int
133
266
L4PER_L3_GICLK
VCP1
VIP1
L3MAIN1_L3_GICL
K
CORE_X2_CLK
PROC_CLK
L3_CLK
Func
Int
266
133
VIP1_GCLK
L3_ICLK
DPLL_CORE
DPLL_CORE
CORE_ISS_MAIN_
CLK
L4_CLK
Int
VIP1_GCLKDIV2
VIP1_GCLK/2
DPLL_CORE
5.6 Power Consumption Summary
注
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
注
The data specified in 表 5-6 through 表 5-10 are subject to change.
92
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
The interfaces or signals described in 表 5-6 through 表 5-10 correspond to the interfaces or
signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
表 5-6. LVCMOS DDR DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals) ABF: ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0],
ddr1_cke[1:0], ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc;
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9×VDDS
V
V
0.1×VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
VREF+
-1%VDDS
1%VDDS
CPAD
Pad capacitance (including package capacitance)
pF
Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc;
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9×VDDS
V
V
0.1×VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
VREF+
-1%VDDS
1%VDDS
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
93
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-6. LVCMOS DDR DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
CPAD
Differential Receiver Mode
VSWING Input voltage swing
VCM Input common-mode voltage
Pad capacitance (including package capacitance)
3
pF
DDR3/DDR3L
0.4×vdds
0.6×vdds
V
V
VREF
VREF+
-1%VDDS
1%VDDS
CPAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more information on the power supply
name and the corresponding ball, see 表 4-1, POWER [10] column.
表 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;
Balls ABF: L3, L4, L6, L5;
MIN
NOM
MAX
UNIT
I2C Standard Mode – 1.8 V
VIH
VIL
Vhys
II
Input high-level threshold
Input low-level threshold
Hysteresis
0.7×VDDS
0.1×VDDS
V
V
0.3×VDDS
V
Input current at each I/O pin with an input voltage between 0.1×VDDS to
0.9×VDDS
12
12
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
µA
CI
Input capacitance
10
pF
V
VOL3
IOLmin
tOF
Output low-level threshold open-drain at 3-mA sink current
Low-level output current @VOL=0.2×VDDS
0.2×VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF
to 400 pF
250
I2C Fast Mode – 1.8 V
VIH
VIL
Vhys
II
Input high-level threshold
0.7×VDDS
0.1×VDDS
V
V
Input low-level threshold
Hysteresis
0.3×VDDS
V
Input current at each I/O pin with an input voltage between 0.1×VDDS to
0.9×VDDS
12
12
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
µA
CI
Input capacitance
10
pF
V
VOL3
IOLmin
tOF
Output low-level threshold open-drain at 3-mA sink current
Low-level output current @VOL=0.2×VDDS
0.2×VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF 20+0.1×C
250
to 400 pF
b
I2C Standard Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7×VDDS
V
V
V
Input low-level threshold
Hysteresis
0.3×VDDS
Vhys
0.05×VDD
S
II
Input current at each I/O pin with an input voltage between 0.1×VDDS to
0.9×VDDS
31
80
80
µA
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
31
94
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
10
UNIT
pF
CI
Input capacitance
VOL3
IOLmin
IOLmin
tOF
Output low-level threshold open-drain at 3-mA sink current
Low-level output current @VOL=0.4V
0.4
V
3
6
mA
mA
ns
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)
Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF
to 400 pF
250
I2C Fast Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7×VDDS
V
V
V
Input low-level threshold
Hysteresis
0.3×VDDS
Vhys
0.05×VDD
S
II
Input current at each I/O pin with an input voltage between 0.1×VDDS to
0.9×VDDS
31
80
80
µA
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
31
CI
Input capacitance
10
pF
V
VOL3
IOLmin
IOLmin
tOF
Output low-level threshold open-drain at 3-mA sink current
Low-level output current @VOL=0.4V
0.4
3
6
mA
mA
ns
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10
pF to 200 pF (Proper External Resistor Value should be used as per I2C
spec)
20+0.1×C
b
250
290
Output fall time from VIHmin to VILmax with a bus capacitance CB from 300
pF to 400 pF (Proper External Resistor Value should be used as per I2C
spec)
40
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
表 5-8. IQ1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk;
Balls ABF: J2;
1.8-V Mode
VIH
Input high-level threshold
Input low-level threshold
0.75 ×
VDDS
V
V
VIL
0.25 ×
VDDS
VHYS
IIN
Input hysteresis voltage
100
2
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
3.3-V Mode
VIH
Pad capacitance (including package capacitance)
Input high-level threshold
2.0
V
V
VIL
Input low-level threshold
0.6
VHYS
IIN
Input hysteresis voltage
400
5
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
11
1
CPAD
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv1). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
95
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-9. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: porz;
Balls ABF: G3;
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
0.02
1
1
CPAD
3.3-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
5
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
8
1
CPAD
表 5-10. LVCMOS Analog OSC Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: xi_osc0, xo_osc0, xi_osc1, xo_osc1;
Balls ABF: E22, D22, B21, C21;
VIH
VIL
IOH
Input high-level threshold
Input low-level threshold
0.65×VDDS
V
0.35×VDDS
V
hfenable=0
hfenable=1
hfenable=0
hfenable=1
MODE-1
1.18
2
mA
mA
mA
mA
mV
pF
IOL
2
3.2
150
12
VHYS
CPAD
Input hysteresis voltage
Capacitance connected on input and output Pad on
Board, CL1=CL2
24
(1) VDDS in this table stands for corresponding power supply (i.e. vdda_osc). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
表 5-11. Dual Voltage LVCMOS DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
1.8-V Mode
DESCRIPTION
MIN
NOM
MAX
0.35×VDDS
0.45
UNIT
VIH
VIL
Input high-level threshold
0.65×VDDS
V
V
Input low-level threshold
VHYS
VOH
VOL
Input hysteresis voltage
100
mV
V
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
VDDS-0.45
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-
0.45V
6
mA
IIN
Input current at each I/O pin
16
µA
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0
to VDDS and the Max(I(PAD)) is measured and is
reported as IOZ
11.5
96
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-11. Dual Voltage LVCMOS DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
IIN with pulldown enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
60
120
200
µA
IIN with pullup enabled
Input current at each I/O pin with weak pullup enabled
measured when PAD = 0
60
120
40
210
4
µA
CPAD
ZO
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
Ω
3.3-V Mode
VIH
VIL
Input high-level threshold
2
V
V
Input low-level threshold
0.8
0.2
VHYS
VOH
VOL
Input hysteresis voltage
200
mV
V
Output high-level threshold (IOH =100µA)
Output low-level threshold (IOL = 100µA)
VDDS-0.2
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-
0.45V
6
mA
IIN
Input current at each I/O pin
64
64
µA
µA
IOZ
IOZ(IPAD Current) at each IO pin. PAD is swept from 0
to VDDS and the Max(I(PAD)) is measured and is
reported as IOZ
IIN with pulldown enabled
IIN with pullup enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
10
40
100
100
290
200
4
µA
µA
Input current at each I/O pin with weak pullup enabled
measured when PAD = 0
CPAD
ZO
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
40
Ω
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see 表 4-1, POWER [10] column.
表 5-12. Analog-to-Digital ADC Subsystem Electrical Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Analog Input
CONDITIONS
MIN
NOM
MAX
UNIT
Full-scale Input Range
Vref
adc_vrefp
V
V
Should be less than or equal to vdds_18v.
1.62
-1
vdds_18v
Differential Non-Linearity
(DNL)
1
LSB
Integral Non-Linearity (INL)
Gain Error
adc_vrefp = vdds_18v
adc_vrefp = vdds_18v
adc_vrefp = vdds_18v
±2
LSB
LSB
LSB
pF
±4
±3
Offset Error
Input Sampling Capacitance
Input Frequency adc_in[7:0]
3.2
5
0
30
kHz
Input Signal: 30 kHz sine wave at -0.5 dB
Full Scale
Signal-to-Noise Ratio (SNR)
50
60
60
dB
dB
dB
Total Harmonic Distortion
(THD)
1.8 Vpp, 30 kHz sine wave
1.8 Vpp, 30 kHz sine wave
1.8 Vpp, 30 kHz sine wave
Spurious Free Dynamic
Range
Signal-to-Noise Plus
Distortion
50
20
dB
adc_vrefp Input Impedance
Ω
Sampling Dynamics
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
97
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-12. Analog-to-Digital ADC Subsystem Electrical Specifications (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
17
NOM
MAX
UNIT
Clock Cycles
Clock Cycles
Clock Cycles
MSPS
Time from Start to Start
Conversion Time + Error Correction
Acquisition time
10 + 1
4
Throughput Rate
CLK = 20 MHz (Pin : clk)
1
Channel to Channel Isolation
90
dB
See
表 5-1
ADC Clock Frequency
MHz
(1) Connect adc_vrefp to vdda_adc when not using a positive external reference voltage.
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
(3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted
digital value.
5.8 Thermal Characteristics
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Section 5.4, Recommended Operating Conditions.
A BCI compact thermal model for this Device is available and recommended for use when modeling
thermal performance in a system.
Therefore, it is recommended to perform thermal simulations at the system level with the worst case
device power consumption.
5.8.1 Package Thermal Characteristics
表 5-13 provides the thermal resistance characteristics for the package used on this device.
注
Power dissipation of 4.14 W and an ambient temperature of 65ºC is assumed for ABF
package.
表 5-13. Thermal Resistance Characteristics
NO.
PARAMET DESCRIPTION
ER
°C/W(1)
AIR FLOW (m/s)(2)
T1
T2
RΘJC
RΘJB
Junction-to-case
Junction-to-board
Junction-to-free air
1.41
5.96
15.4
13.1
12.2
11.6
0.94
0.94
0.94
0.94
5.12
4.78
4.63
4.52
N/A
N/A
0
T3
T4
1
RΘJA
T5
Junction-to-moving air
Junction-to-free air
Junction-to-package top
Junction-to-free air
Junction-to-board
2
T6
3
T7
0
T8
1
ΨJT
T9
2
T10
T11
T12
T13
T14
3
0
1
ΨJB
2
3
98
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
–
–
–
–
–
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
99
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9 Timing Requirements and Switching Characteristics
5.9.1 Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
Table 5-14. Timing Parameters
SUBSCRIPTS
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
100
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.1.1 Parameter Information
Tester Pin Electronics
Transmission Line
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to ensured timings,
unless specific instructions otherwise are given in the individual timing subsections of the datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
101
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.1.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing
Analysis application report. If needed, external logic hardware such as buffers may be used to
compensate any timing differences.
5.9.2 Interface Clock Specifications
5.9.2.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
5.9.2.2 Interface Clock Frequency
The two interface clock characteristics are:
•
•
The maximum clock frequency
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
102
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.3 Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation.
Figure 5-4 through Figure 5-8, and associated notes describes the device Recommended Power
Sequencing.
I/O Buffer Voltages
vdds18v, vdds18v_ddr1, vdds18v_ddr2,
vdds18v_ddr3
Note 3
Note 4
PLL and Analog PHY Voltages
EMIF Voltages
vdda_adc, vdda_csi, vdda_dac, vdda_ddr_dsp,
vdda_gmac_core, vdda_osc, vdda_per
vdds_ddr1, vdds_ddr2, vdds_ddr3
Note 5
CORE AVS Voltage
vdd
Note 6
DSPEVE AVS Voltage
vdd_dspeve
Note 7
vddshv1, vddshv2, vddshv3,
vddshv4, vddshv5(3), vddshv6
xi_osc0
Note 8
resetn, porz
Note 10
Note 9
sysboot[15:0]
rstoutn
Valid Config
Note 11
SPRS916_ELCH_01
Figure 5-4. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp-up a voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp-up possibilities based on whether I/O voltage levels are 1.8V or 3.3V
(see associated note for more details).
(3) vdds18v_* and vdda_* rails should not be combined for best performance to avoid transient switching noise impacts on analog domains.
vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached
until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an
inadvertent violation.
(4) vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence is to follow all vdds18v_* to ensure circuit components and
PCB design do not cause an inadvertent violation. vdds_ddr* can ramp-up before, concurrently or after vdda_*, there are no
dependencies between vdds_ddr* and vdda_* domains.
–
vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped up
together for simplified power sequencing.
–
If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come up together
or after the vdds18v_* supply. The DDR supply in this case should never ramp up before the vdds18v_*.
(5) vdd should not ramp-up before vdds18v_* or vdds_ddr* domains.
(6) vdd_dspeve must not exceed vdd core supply and maintain at least 150mV lower voltage on vdd_dspeve vs vdd. vdd_dspeve could
ramp concurrently with vdd if design ensures final operational voltage will not be reached until after vdd and maintains minimum of
150mV less than vdd during entire ramp time. The preferred sequence is to follow vdd to ensure circuit components and PCB design do
not cause an inadvertent violation.
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
103
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(7) If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.
If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.
(8) resetn and porz must remain asserted low for a minimum of 12P(12) after xi_osc0 is stable at a valid frequency.
(9) Setup time: SYSBOOT[15:0] pins must be valid 2P(12) before porz is de-asserted high.
(10) Hold time: SYSBOOT[15:0] pins must be valid 15P(12) after porz is de-asserted high.
(11) resetn to rstoutn delay is 2ms.
(12) P = 1/(SYS_CLK1/610) frequency in ns.
(13) Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about
voltage levels, refer to , Recommended Operating Conditions.
T0
T1
T2
T3
T4
Note 4
porz
vddshv1, vddshv2, vddshv3,
vddshv4, vddshv5, vddshv6
Note 5
Note 6
V1
Note 7
Note 8
DSPEVE voltage
CORE voltage
vdd_dspeve
vdd
EMIF voltage
Note 9
vdds_ddr1, vdds_ddr2, vdds_ddr3
vdda_osc, vdda_per, vdda_ddr_dsp,
vdda_gmac_core, vdda_csi,
vdda_dac, vdda_adc
Note 10
Note 12
Note 11
vdds18v_ddr1, vdds18v_ddr2,
vdds18v_ddr3, vdds18v,
xi_osc0
SPRS916_ELCH_02
Figure 5-5. Recommended Power-Down Sequencing
(1) T1 ≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval
times.
(2) Terminology:
–
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,
Recommended Operating Conditions.
–
–
VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
(3) General timing diagram items:
–
–
–
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit
performance.
(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
(5) vddshv[1-6] domains supplied by 3.3 V:
–
–
–
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-6, "vdds18v versus vddshv[1-6] Discharge
Relationship".
(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
(7) vdd_dspeve domain can ramp down before or concurrently with vdd.
(8) vdd must ramp down after or concurrently with vdd_dspeve.
(9) vdds_ddr[1-3] domains:
–
should ramp down after vdd begins ramping down.
104
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
–
If DDR2 memory is used (requiring 1.8V supply),
–
then vdds_ddr[1-3] can be combined with vdds18v and vdds18v_ddr[1-3] domains and sourced from a common supply.
Accordingly, all domains can ramp down concurrently with vdds18v.
–
if vdds_ddr[1-3] and vdds18v_ddr[1-3] are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can
ramp down before or concurrently with vdds18v.
(10) vdda_* domains:
–
–
–
can ramp down before, concurrently or after vdds_ddr[1-3], there is no dependency between these supplies.
can ramp down before or concurrently with vdds18v.
must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-8) if any of the vdda_* disable point is later or
discharge rate is slower than vdds18v.
(11) vdds18v domain:
–
–
–
should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
must satisfy the vdds18v versus vddshv[1-6] discharge relationship (see Figure 5-6) if any of the vddshv[1-6] is operating at 3.3 V.
must satisfy the vdds18v versus vdds_ddr[1-3] discharge relationship ( see Figure 5-7) if vdds_ddr[1-3] discharge rate is slower than
vdds18v.
Figure 5-6 describes vddshv[1-6] supplies falling before vdds18v supplies delta.
vddshv1, vddshv2, vddshv3,
vddshv4, vddshv5, vddshv6
vdds18v
Vdelta
(Note1)
SPRS916_ELCH_03
Figure 5-6. vdds18v versus vddshv[1-6] Discharge Relationship
(1) Vdelta MAX = 2V
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
105
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr*
discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time
period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is
less than 10 ms (Figure 5-7).
vdds18v
vdds_ddr1, vdds_ddr2,
vdds_ddr3
V1
V2
T1
SPRS916_ELCH_04
Figure 5-7. vdds18v and vdds_ddr* Discharge Relationship(1)
(1) V1 > 1.0 V; V2 < 0.6 V; T1 < 10ms.
Note 1
vdds18v
vdda_*
V1
Note 2
V2
SPRS916_ELCH_05
Figure 5-8. vdds18v and vdda_* Discharge Relationship(3)
(1) vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
(2) vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
(3) V1 = 1.62 V; V2 < 0.6 V.
106
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Figure 5-6 through Figure 5-9 and associated notes described the device Abrupt Power Down Sequence.
A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally,
the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of
elapsed time. This is the typical range of elapsed time available following a loss of power event, see 节
7.3.7, Loss of Input Power Event for design recommendations. If sufficient elapse time is not provided,
then an “abrupt” power-down sequence can be supported without impacting POH reliability if all of the
following conditions are met (Figure 5-9).
Tdelta1
Note 4
porz
V2
Note 5
V3
vddshv1, vddshv2, vddshv3,
V1
vddshv4, vddshv5, vddshv6
Note 7
vdd, vdd_dspeve
Note 7, Note 8
V4
vdds_ddr1, vdds_ddr2, vdds_dd3
Note 9
V7
V8
vdda_osc, vdda_per, vdda_ddr_dsp,
vdda_gmac_core, vdda_csi,
vdda_dac, vdda_adc
V5
V6
Tdelta2
vddshv1, vddshv2, vddshv3,
vddshv4, vddshv5, vddshv6,
vdds18v_ddr1, vdds18v_ddr2,
vdds18v_ddr3, vdds18v
V9
Note 6, Note 10
V10
V11
xi_osc0
SPRS916_ELCH_06
Figure 5-9. Abrupt Power-Down Sequencing(1)
(1) V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs;
Tdelta2 < 10 ms.
(2) Terminology:
–
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,
Recommended Operating Conditions.
–
–
VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
(3) General timing diagram items:
–
–
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit
performance.
(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
(5) vddshv[1-6] domains supplied by 3.3 V:
–
–
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after porz is asserted low.
must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).
(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
(7) vdd_dspeve, vdd, vdds_ddr[1-3], vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
(8) vdds_ddr* domains:
–
–
can remain at VOPR MIN or a level greater than vdds18v during ramp down.
elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
(9) vdda_* domains:
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
107
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
–
–
can start to ramp down before or concurrently with vdds18v.
must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
(10) vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.
5.9.4 Clock Specifications
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Clock Signals and Clock Management Functional Description section
of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
•
The system clocks, SYS_CLK1(Mandatory) and SYS_CLK2(Optional) are the main clock sources of
the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
Figure 5-10 shows the external input clock sources and the output clocks to peripherals.
DEVICE
rstoutn
Warm reset output.
Device reset input.
Power ON Reset.
resetn
porz
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xi_osc0
xo_osc0
To quartz (from oscillator output).
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xi_osc1
xo_osc1
clkout0
clkout1
clkout2
To quartz (from oscillator output).
Output clkout[0:2] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
xref_clk0
xref_clk1
External Reference Clock [0:2].
For Audio and other Peripherals
xref_clk2
Boot Mode Configuration
sysboot[15:0]
SPRS91v_CLK_01_SR2.0
Figure 5-10. Clock Interface
108
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.4.1 Input Clocks / Oscillators
•
•
The source of the internal system clock (SYS_CLK1) could be either:
–
A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc0 and xo_osc0.
The source of the internal system clock (SYS_CLK2) could be either:
–
A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc1 and xo_osc1.
SYS_CLK1 is received directly from oscillator OSC0. For more information about SYS_CLK1 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.9.4.1.1 OSC0 External Crystal
An external crystal is connected to the device pins. Figure 5-11 describes the crystal implementation.
Device
xo_osc0
vssa_osc0
xi_osc0
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS91v_CLK_02
Figure 5-11. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-11, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-12. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-15 summarizes
the required electrical constraints.
Table 5-15. OSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX
UNIT
MHz
pF
19.2, 20, 27
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
Cf2
pF
ESR(Cf1,Cf2) Crystal ESR
100
Ω
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
109
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Table 5-15. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz, 20 MHz, 27
MHz
7
pF
19.2 MHz, 20 MHz
27 MHz
7
5
7
pF
pF
pF
-
ESR = 50 Ω
ESR = 60 Ω
ESR = 80 Ω
ESR = 100 Ω
19.2 MHz, 20 MHz
27 MHz
CO
Crystal shunt capacitance
Not Supported
Not Supported
19.2 MHz, 20 MHz
27 MHz
5
3
pF
-
19.2 MHz, 20 MHz
27 MHz
pF
-
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
Ethernet not used
±200
±50
ppm
tj(xiosc0)
Frequency accuracy(1), xi_osc0
Ethernet RGMII using
derived clock
ppm
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-16 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-16. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time
19.2, 20, 27 MHz
tsX
4
5.9.4.1.2 OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK1 clock input to the system. The external connections to support this are shown in Figure 5-13.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (vss).
Device
xo_osc0
vssa_osc0
xi_osc0
NC
SPRS91v_CLK_03
Figure 5-13. 1.8-V LVCMOS-Compatible Clock Input
Table 5-17 summarizes the OSC0 input clock electrical characteristics.
110
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Table 5-17. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
19.2, 20, 27
2.384
MAX
UNIT
MHz
pF
f
Frequency
CIN
IIN
Input capacitance
2.184
4
2.584
10
Input current (3.3V mode)
6
µA
Table 5-18 details the OSC0 input clock timing requirements.
Table 5-18. OSC0 Input Clock Timing Requirements
NAME
CK0
DESCRIPTION
1 / tc(xiosc0) Frequency, xi_osc0
MIN
TYP
19.2, 20, 27
MAX
UNIT
MHz
ns
CK1
tw(xiosc0)
tj(xiosc0)
tR(xiosc0)
tF(xiosc0)
Pulse duration, xi_osc0 low or high
Period jitter(1), xi_osc0
Rise time, xi_osc0
0.45 × tc(xiosc0)
0.55 × tc(xiosc0)
0.01 × tc(xiosc0)
ns
5
5
ns
Fall time, xi_osc0
ns
Ethernet not used
±200
ppm
tj(xiosc0)
Frequency accuracy(2), xi_osc0
Ethernet RGMII using
derived clock
±50
ppm
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
SPRS91v_CLK_04
Figure 5-14. xi_osc0 Input Clock
5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.9.4.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. Figure 5-15 describes the crystal implementation.
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
111
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Device
xo_osc1
xi_osc1
vssa_osc1
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS91v_CLK_05
Figure 5-15. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-15, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-16. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-19 summarizes
the required electrical constraints.
Table 5-19. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX
UNIT
MHz
pF
pF
Ω
Range from 19.2 to 32
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
100
7
Cf2
ESR(Cf1,Cf2) Crystal ESR
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz ≤ fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 25 MHz
25 MHz < fp ≤ 27 MHz
27 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 23 MHz
23 MHz < fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 23 MHz
23 MHz < fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 20 MHz
20 MHz < fp ≤ 32 MHz
pF
pF
pF
pF
-
5
7
ESR = 50 Ω
ESR = 60 Ω
5
Not Supported
Not Supported
Not Supported
7
5
pF
pF
-
CO
Crystal shunt capacitance
5
3
pF
pF
-
ESR = 80 Ω
3
pF
-
ESR = 100 Ω
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
112
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Table 5-19. OSC1 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Ethernet not used
±200
ppm
tj(xiosc0)
Frequency accuracy(1), xi_osc1
Ethernet RGMII using
derived clock
±50
ppm
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 5-20 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-20. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time
Range from 19.2 to 32
tsX
4
5.9.4.1.3.2 OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK2 clock input to the system. The external connections to support this are shown in, Figure 5-17.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (VSS).
Device
xo_osc1
vssa_osc1
xi_osc1
NC
SPRS91v_CLK_06
Figure 5-17. 1.8-V LVCMOS-Compatible Clock Input
Table 5-21 summarizes the OSC1 input clock electrical characteristics.
Table 5-21. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
Frequency
Range from 12 to 38.4
CIN
IIN
Input capacitance
2.819
4
3.019
6
See(2)
3.219
10
Input current (3.3V mode)
Start-up time(1)
µA
tsX
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 5-20, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 5-22 details the OSC1 input clock timing requirements.
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
113
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Table 5-22. OSC1 Input Clock Timing Requirements
NAME
CK0
DESCRIPTION
1 / tc(xiosc1) Frequency, xi_osc1
MIN
TYP
MAX
UNIT
Range from 12 to 38.4
MHz
CK1
tw(xiosc1)
tj(xiosc1)
tR(xiosc1)
tF(xiosc1)
Pulse duration, xi_osc1 low or high
Period jitter(1), xi_osc1
Rise time, xi_osc1
0.45 × tc(xiosc1)
0.55 × tc(xiosc1)
ns
ns
(3)
0.01 × tc(xiosc1)
5
5
ns
Fall time, xi_osc1
ns
Ethernet not used
±200
ppm
tj(xiosc1)
Frequency accuracy(2), xi_osc1
Ethernet RGMII using
derived clock
±50
ppm
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a. The osc1/SYS_CLK2 clock bypasses all device PLLs
b. The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
CK0
CK1
CK1
xi_osc1
SPRS91v_CLK_07
Figure 5-18. xi_osc1 Input Clock
5.9.4.1.4 RC On-die Oscillator Clock
RCOSC_32K_CLK is received directly through a network of resistor and capacitor (an RC network) inside
of the SoC. This RC oscillator do not have good frequency stability. The Frequency range is described in
Table 5-23, which depends on the temperature. For more information about RCOSC_32K_CLK see the
Device TRM, Chapter: Power, Reset, and Clock Management.
Table 5-23. RC On-die Oscillator Clock Frequency Range
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
RCOSC_32K_CLK Internal RC Oscillator
Range from 28 to 42
kHz
5.9.4.2 Output Clocks
The device provides three output clocks. Summary of these output clocks are as follows:
•
clkout1 - Device Clock output 1. Can be used as a system clock for other devices. The source of the
clkout1 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
•
clkout2 - Device Clock output 2. Can be used as a system clock for other devices. The source of the
clkout2 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
114
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
clkout3 - Device Clock output 3. Can be used as a system clock for other devices. The source of the
clkout3 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
For more information about Output Clocks see Device TRM, Chapter: Power, Reset, and Clock
Management.
5.9.4.3 DPLLs, DLLs
NOTE
For more information, see:
•
Power, Reset, and Clock Management / Clock Management Functional Description /
Internal Clock Sources / Generators / Generic DPLL Overview Section
and
•
Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
•
They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
•
•
DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock , a
96-MHz functional clock to subsystems and peripherals.
•
•
DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.
DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK
and DSP1_CLK).
•
DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its
associated EMIF PHYs.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
•
DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
5.9.4.3.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
115
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.
Table 5-24 summarizes DPLL type described in Section 5.9.4.3, DPLLs, DLLs Specifications.
Table 5-24. DPLL Control
DPLL NAME
DPLL_CORE
CONTROLLED BY PRCM
(1)
Yes
(1)
DPLL_EVE_VID_DSP
DPLL_GMAC_DSP
DPLL_PER
Yes
(1)
Yes
(1)
Yes
(1)
DPLL_DDR
Yes
(1) DPLL is in the always-on domain.
Table 5-25 and summarize the DPLL characteristics and assume testing over recommended operating
conditions.
116
Specifications
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Table 5-25. DPLL Characteristics
NAME
finput
DESCRIPTION
MIN
0.032
0.15
10
TYP
MAX
52
UNIT
MHz
MHz
MHz
COMMENTS
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
FINP
finternal
52
REFCLK
FINPHIF
fCLKINPHIF
1400
Bypass mode: fCLKOUT
=
fCLKINPULOW
CLKINPULOW input frequency
0.001
600
MHz
MHz
fCLKINPULOW / (M1 + 1) if
ulowclken = 1
(6)
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)
(2)
fCLKOUT
CLKOUT output frequency
CLKOUTx2 output frequency
20
1800
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
(1)
(2)
(4)
(4)
fCLKOUTx2
40
2200
1400
2200
MHz
MHz
MHz
(3)
20
FINPHIF / M3 if clkinphifsel = 1
fCLKOUTHIF
CLKOUTHIF output frequency
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
(3)
40
DCOCLKLDO output
frequency
2 × [M / (N + 1)] × FINP (in
locked condition)
fCLKDCOLDO
tlock
40
2800
MHz
µs
6 + 350 ×
REFCLK
Frequency lock time
Phase lock time
6 + 500 ×
REFCLK
plock
µs
(5)
Relock time—Frequency lock
(LP relock time from bypass)
6 + 70 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
trelock-L
prelock-L
trelock-F
prelock-F
µs
(5)
Relock time—Phase lock (LP
relock time from bypass)
6 + 120 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
µs
(5)
Relock time—Frequency lock
(fast relock time from bypass)
3.55 + 70 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
µs
(5)
Relock time—Phase lock
3.55 + 120 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
µs
(fast relock time from bypass)
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
Copyright © 2016–2019, Texas Instruments Incorporated
Specifications
117
Submit Documentation Feedback
Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.4.3.2 DLL Characteristics
Table 5-26 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
Table 5-26. DLL Characteristics
NAME
finput
DESCRIPTION
Input clock frequency (EMIF_DLL_FCLK)
MIN
TYP
MAX
266
50k
UNIT
MHz
tlock
Lock time
cycles
cycles
trelock
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
5.9.4.3.2.1 DPLL and DLL Noise Isolation
NOTE
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
5.9.5 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
5.9.6 Peripherals
5.9.6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
118
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.6.2 VIP
The device includes 1 Video Input Ports (VIP).
表 5-27, 图 5-19 and 图 5-20 present timings and switching characteristics of the VIPs.
(1)(2)
表 5-27. Timing Requirements for VIP
NO.
V1
V2
V3
V4
PARAMETER
tc(CLK)
DESCRIPTION
Mode
MIN
MAX
UNIT
ns
(3)(5)
(1)
Cycle time, vinx_clki
5.99
0.45×P
0.45×P
2.52
2.52
3.7
(3)(5)
(2)
(2)
tw(CLKH)
Pulse duration, vinx_clki high
ns
(3)(5)
tw(CLKL)
Pulse duration, vinx_clki low
ns
tsu(CTL/DATA-CLK)
Input setup time, Control (vinx_dei,
vinx_vsynci, vinx_fldi, vinx_hsynci) and
Data (vinx_dn) valid to vinx_clki transition
All other IOSETs
VIN2 IOSET4
VIN2 IOSET5
VIN2 IOSET6
All other IOSETs
VIN2 IOSET4
VIN2 IOSET5
VIN2 IOSET6
ns
ns
(3)(4)(5)
ns
4.2
ns
V5
th(CLK-CTL/DATA)
Input hold time, Control (vinx_dei,
vinx_vsynci, vinx_fldi, vinx_hsynci) and
Data (vinx_dn) valid from vinx_clki
-0.05
3
ns
ns
(3)(4)(5)
1
ns
transition
1
ns
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a and 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b;
n = 0 to 23 when x = 1a and 2a;
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
V3
V2
V1
vinx_clki
SPRS91v_VIP_01
图 5-19. Video Input Ports Clock Signal
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
图 5-20. Video Input Ports Timings
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
119
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
CAUTION
The IO timings provided in this section are only valid for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in 表 5-28 and
表 5-29.
In 表 5-28 and 表 5-29 are presented the specific groupings of signals (IOSET) for use with vin1a, vin1b,
vin2a and vin2b.
表 5-28. VIN1 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
IOSET4
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin1a
vin1a_clk0
vin1a_de0
vin1a_fld0
vin1a_hsync0
vin1a_vsync0
vin1a_d0
F22
F21
F20
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
J17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F22
F21
F20
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
0
0
0
0
0
0
0
0
0
0
0
0
0
F22
F21
F20
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
J17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
F22
F19
F20
F19
G19
G18
G21
G22
H18
H20
H19
H22
H21
0
2
0
0
0
0
0
0
0
0
0
0
0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
K22
K21
K18
K17
K19
K20
L21
K22
K21
K18
AB17
U17
W17
AA17
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1b
vin1b_clk1
vin1b_hsync1
vin1b_vsync1
vin1b_d0
F21
W7
2
7
7
2
2
2
2
2
2
2
2
8
W6
J17
K22
K21
K18
K17
K19
K20
L21
W7
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
vin1b_de1
120
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
121
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-29. VIN2 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
IOSET4
IOSET5
IOSET6
BALL
MUX
BALL
MUX
BALL
MUX
vin2a
0
BALL
MUX
BALL
MUX
BALL
MUX
vin2a_clk0
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2a_d0
L22
M17
M18
0
0
0
AB17
AA17
U16
W7
9
9
9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
L22
L22
AA15
AB15
F15
0
9
9
9
9
2
2
2
2
2
2
2
2
L22
W7
0
1
9
9
9
2
2
2
2
2
2
2
2
W15
AA17
U16
W7
9
9
9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AB15
F15
F14
C14
AA14
AB14
U13
V13
9
9
2
2
2
2
2
2
2
2
W6
AA14
AB14
U13
V13
2
2
2
2
2
2
2
2
2
W6
F16
F16
W6
AA14
AB14
U13
V13
Y13
W13
U11
V11
U9
AA14
AB14
U13
AA14
AB14
U13
V13
Y13
W13
U11
V11
AA14
AB14
U13
V13
Y13
W13
U11
V11
U9
vin2a_d1
vin2a_d2
vin2a_d3
V13
vin2a_d4
Y13
Y13
Y13
vin2a_d5
W13
U11
V11
W13
U11
V11
W13
U11
vin2a_d6
vin2a_d7
V11
vin2a_d8
vin2a_d9
W11
V9
W11
V9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
W9
W9
U8
U8
W8
W8
U7
U7
V7
V7
vin2b
vin2b_clk1
vin2b_hsync1
vin2b_vsync1
vin2b_d0
F20
M17
M18
U9
2
2
2
5
5
5
5
5
5
vin2b_d1
W11
V9
vin2b_d2
vin2b_d3
W9
U8
vin2b_d4
vin2b_d5
W8
122
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
SIGNALS
表 5-29. VIN2 IOSETs (continued)
IOSET1
IOSET2
IOSET3
IOSET4
IOSET5
IOSET6
BALL
MUX
BALL
MUX
BALL
U7
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin2b_d6
vin2b_d7
5
5
V7
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
123
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.6.3 DSS
Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1.
Every VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
注
For more information, see the Display Subsystem section of the Device TRM.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
表 5-30 and 图 5-21 assume testing over the recommended operating conditions and electrical
characteristic conditions.
表 5-30. DPI Video Output 1 Switching Characteristics(1)(2)
NO.
D1
D2
D3
D5
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.73
MAX
UNIT
ns
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
tw(clkL)
P×0.5-1
P×0.5-1
-1.33
ns
tw(clkH)
ns
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
DPI1
1.01
1.01
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
-1.33
ns
124
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) P = output vout1_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D3
D1
D6
D4
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_clk
vouti_clk
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
even
vouti_fld
odd
SWPS049-018
图 5-21. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vout1_hsync and vout1_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vout1_clk frequency can be configured, refer to the DSS section of the device TRM.
5.9.6.4 EMIF
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
•
•
•
16-bit or 32-bit data path to external SDRAM memory
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)
One interface with associated DDR3/DDR3L PHYs
注
For more information, see the EMIF Controller section of the Device TRM.
5.9.6.5 GPMC
The GPMC is the unified memory controller that interfaces external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
125
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
表 5-31 and 表 5-32, 表 5-33 and 表 5-34 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see 图 5-22, 图 5-23, 图 5-24, 图 5-25, 图 5-26 and 图 5-27).
表 5-31. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load
NO.
F12
F13
F21
F22
PARAMETER
tsu(dV-clkH)
DESCRIPTION
MIN
1.9
1
MAX
UNIT
ns
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
th(clkH-dV)
ns
tsu(waitV-clkH)
th(clkH-waitV)
1.9
1
ns
ns
注
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
表 5-32. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load
NO.
F0
F2
F3
F4
F5
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period (12)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
MIN
11.3
MAX
UNIT
ns
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
td(clkH-ADDIV)
F-0.8
E-0.8
B-0.8
-0.8
F+3.1
E+3.1
B+3.1
ns
ns
ns
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus
invalid
ns
F6
F7
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14)
Delay time, gpmc_clk rising edge to gpmc_wen transition (14)
B-3.8
D-0.4
G-0.8
D-0.8
H-0.8
E-0.8
I-0.8
B+1.1
D+1.1
G+3.1
D+3.1
H+2.1
E+2.1
I+3.1
ns
ns
ns
ns
ns
ns
ns
ns
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
td(clkH-nOE)
td(clkH-nOEIV)
td(clkH-nWE)
td(clkH-Data)
F8
F9
F10
F11
F14
F15
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus
transition
J-1.1
J+3.92
F17
F18
F19
F20
F23
td(clkH-nBE)
tw(nCSV)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
J-1.1
A
J+3.8
ns
ns
ns
ns
ns
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
tw(nADVV)
td(CLK-GPIO)
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout0 transition (13)
K
1.2
6.1
表 5-33. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads
NO.
F12
F13
F21
PARAMETER
tsu(dV-clkH)
DESCRIPTION
MIN
2.5
1.9
2.5
MAX
UNIT
ns
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
th(clkH-dV)
ns
tsu(waitV-clkH)
ns
126
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-33. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F22
th(clkH-waitV)
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.9
ns
表 5-34. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads
NO.
F0
F2
F3
F4
F5
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period (12)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
MIN
MAX
UNIT
ns
15.04
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
td(clkH-ADDIV)
F+0.7 (6) F+6.1 (6)
E+0.7 (5) E+6.1 (5)
B+0.7 (2) B+6.1 (2)
0.7
ns
ns
ns
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus
invalid
ns
F6
F7
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14)
Delay time, gpmc_clk rising edge to gpmc_wen transition (14)
B-4.9
D-0.4
B+0.4
D+4.9
ns
ns
ns
ns
ns
ns
ns
ns
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
td(clkH-nOE)
td(clkH-nOEIV)
td(clkH-nWE)
td(clkH-Data)
F8
G+0.7 (7) G+6.1 (7)
D+0.7 (4) D+6.1 (4)
H+0.7 (8) H+5.1 (8)
E+0.7 (5) E+5.1 (5)
I+0.7 (9) I+6.1 (9)
F9
F10
F11
F14
F15
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus
transition
J-0.4 (10)
J+4.9
(10)
F17
td(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
J-0.4 (10)
J+4.9
(10)
ns
F18
F19
F20
F23
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A (1)
C (3)
K (11)
1.2
ns
ns
ns
ns
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
tw(nADVV)
td(CLK-GPIO)
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout0 transition (13)
6.1
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
with n the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For Burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK with n the page
burst access number.
(4) For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(5) For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(6) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 × CSExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
127
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F = (3 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
(7) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 3) is a multiple of 4)
For ADV rising edge (ADV deactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 3) is a multiple of 4)
(8) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay)) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE desactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
128
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 3) is a multiple of 4)
(9) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE desactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(11) For read:
K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(12) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(13) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(14) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
129
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F19
F6
F7
F7
gpmc_ben1
F6
F19
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F13
F4
F5
F12
D 0
gpmc_ad[15:0]
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout0
GPMC_01
图 5-22. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
130
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[27:1]
Address
F7
F19
gpmc_ben1
gpmc_ben0
F6
F7
F19
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout0
GPMC_02
图 5-23. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
131
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F7
F6
F19
gpmc_ben1
Valid
F6
F19
Valid
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
F10
F5
F11
gpmc_oen_ren
F12
F4
F13
D1
F12
gpmc_ad[15:0]
D0
D2
D3
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout0
GPMC_03
图 5-24. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
132
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
gpmc_a[27:1]
gpmc_ben1
gpmc_ben0
F4
F6
Address
F7
F19
Valid
F7
F6
F19
Valid
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F12
F13
D1
F12
gpmc_ad[15:0]
D0
D3
D2
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout0
GPMC_04
图 5-25. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
133
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F17
F6
F6
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
Address (LSB)
D 0
D 3
F22
F21
F23
F23
gpio6_16.clkout0
GPMC_05
图 5-26. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 0 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
134
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
F6
gpmc_a[27:1]
Address
F17
F17
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
D 0
D 3
F21
F22
F23
F23
gpio6_16.clkout0
GPMC_06
图 5-27. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
表 5-35 and 表 5-36 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-28, 图 5-29, 图 5-30, 图 5-31, 图 5-32 and 图 5-33).
表 5-35. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
FA5
PARAMETER
tacc(DAT)
DESCRIPTION
MIN
MAX
UNIT
cycles
cycles
(1)
Data Maximum Access Time (GPMC_FCLK cycles)
H
FA20
tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
P (2)
(1)
FA21
tacc2-pgmode(DAT)
tsu(DV-OEH)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
H
cycles
ns
-
-
1.9
1
th(OEH-DV)
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
135
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) H = Access Time × (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime × (TimeParaGranularity + 1)
表 5-36. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
-
PARAMETER
tr(DO)
DESCRIPTION
MIN
0.447
0.43
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rising time, gpmc_ad[15:0] output data
4.067
4.463
N
-
tf(DO)
Fallling time, gpmc_ad[15:0] output data
FA0
FA1
FA3
FA4
FA9
FA10
FA12
FA13
FA16
FA18
FA20
FA25
FA27
FA28
FA29
FA37
tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
td(nCSV-nADVIV)
td(nCSV-nOEIV)
td(AV-nCSV)
td(nBEV-nCSV)
td(nCSV-nADVV)
td(nCSV-nOEV)
tw(AIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
Delay time, address bus valid to gpmc_cs[7:0] valid
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, address invalid between 2 successive R/W accesses
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
Delay time, gpmc_ wen valid to data bus valid
Delay time, data bus valid to gpmc_cs[7:0] valid
B - 0.2
C - 0.2
J - 0.2
J - 0.2
K - 0.2
L - 0.2
G
B + 2.0
C + 2.0
J + 2.0
J + 2.0
K + 2.0
L + 2.0
td(nCSV-nOEIV)
tw(AV)
I - 0.2
D
I + 2.0
td(nCSV-nWEV)
td(nCSV-nWEIV)
td(nWEV-DV)
td(DV-nCSV)
td(nOEV-AIV)
E - 2
E + 2.0
F + 2.0
2
F - 0.2
J - 0.2
J + 2.0
2
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed
address bus phase end
(1) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
with n the page burst access number.
(3) For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK
(4) C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLKFor single read: C
= RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
(5) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK
(6) K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK
(7) L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK
(8) G = Cycle2CycleDelay × GPMC_FCLK × (TimeParaGranularity + 1)
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK
(10) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK
(11) E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
(12) F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
136
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
OUT
IN
OUT
DIR
GPMC_07
图 5-28. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
137
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csi
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA12
FA3
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
OUT
FA14
OUT
DIR
IN
IN
GPMC_08
图 5-29. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
138
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
gpmc_clk
FA21
FA20
Add1
FA20 FA20
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Add0
Add2
Add3
Add4
FA0
FA10
FA10
gpmc_ben0
FA0
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D2
D3
D0
D1
gpmc_waitj
FA15
FA14
OUT
OUT
DIR
IN
SPRS91v_GPMC_09
图 5-30. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note (ref …) and should be stored inside
AccessTime register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
139
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
gpmc_ad[15:0]
gpmc_waitj
DIR
Data OUT
OUT
GPMC_10
图 5-31. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
140
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
FA29
FA37
Data IN
Data IN
Address (LSB)
FA15
FA14
OUT
DIR
OUT
IN
gpmc_waitj
GPMC_11
图 5-32. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
141
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
gpmc_fclk
gpmc_clk
gpmc_csi
FA1
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
Valid Address (LSB)
FA28
Data OUT
gpmc_ad[15:0]
gpmc_waitj
DIR
OUT
GPMC_12
图 5-33. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
表 5-37 and 表 5-38 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-34, 图 5-35, 图 5-36 and 图 5-37).
表 5-37. GPMC/NAND Flash Interface Timing Requirements(1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
cycles
ns
GNF12 tacc(DAT)
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
J
-
-
tsu(DV-OEH)
th(OEH-DV)
1.9
1
ns
(1) J = AccessTime × (TimeParaGranularity + 1)
表 5-38. GPMC/NAND Flash Interface Switching Characteristics
NO.
PARAMETER
tr(DO)
DESCRIPTION
MIN
0.447
0.43
MAX
4.067
4.463
A (1)
UNIT
ns
-
Rising time, gpmc_ad[15:0] output data
Fallling time, gpmc_ad[15:0] output data
Pulse duration, gpmc_wen valid time
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
-
tf(DO)
ns
GNF0
GNF1
tw(nWEV)
ns
td(nCSV-nWEV)
B - 0.2 (2) B + 2.0
ns
(2)
142
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-38. GPMC/NAND Flash Interface Switching Characteristics (continued)
NO.
PARAMETER
td(CLEH-nWEV)
DESCRIPTION
MIN
MAX
UNIT
GNF2
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
C - 0.2 (3) C + 2.0
ns
(3)
GNF3
GNF4
GNF5
GNF6
GNF7
GNF8
GNF9
td(nWEV-DV)
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
Delay time, gpmc_advn_ale high to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
D - 0.2 (4) D + 2.0
ns
ns
ns
ns
ns
ns
(4)
td(nWEIV-DIV)
td(nWEIV-CLEIV)
td(nWEIV-nCSIV)
td(ALEH-nWEV)
td(nWEIV-ALEIV)
tc(nWE)
E - 0.2 (5) E + 2.0
(5)
F - 0.2 (6) F + 2.0
(6)
G - 0.2 (7) G + 2.0
(7)
C - 0.2 (3) C + 2.0
(3)
F - 0.2 (6) F + 2.0
(6)
(8)
Cycle time, write cycle time
H
ns
ns
ns
ns
ns
GNF10 td(nCSV-nOEV)
GNF13 tw(nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, gpmc_oen_ren valid time
Cycle time, read cycle time
I - 0.2 (9) I + 2.0 (9)
K
(10)
GNF14 tc(nOE)
L
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
M - 0.2
M + 2.0
(11)
(11)
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay ) × GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay ) × GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay ) × GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay ) × GPMC_FCLK
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay ) × GPMC_FCLK
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
143
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
gpmc_csi
GNF1
GNF2
GNF6
GNF5
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
GNF0
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
图 5-34. GPMC / NAND Flash - Command Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF7
GNF6
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Address
GPMC_14
图 5-35. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
144
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
图 5-36. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
图 5-37. GPMC / NAND Flash - Data Write Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented 表 4-29 and described in Device TRM, Control
Module section.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
145
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.6.6 GP Timers
The device has eight GP timers: TIMER1 through TIMER8.
•
TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating
system and it belongs to the PD_WKUPAON domain.
•
TIMER2 through TIMER8 belong to the PD_COREAON module.
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the
clock source at the power, reset, and clock management (PRCM) module level.
Each timer provides an interrupt through the device IRQ_CROSSBAR.
Each timer is connected to an external pin by their PWM output or their event capture input pin (for
external timer triggering).
5.9.6.6.1 GP Timer Features
The following are the main features of the GP timer controllers:
•
Level 4 (L4) slave interface support:
–
–
–
–
–
–
32-bit data bus width
32- or 16-bit access supported
8-bit access not supported
10-bit address bus width
Burst mode not supported
Write nonposted transaction mode supported
•
•
•
•
•
•
•
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Compare and capture modes
Autoreload mode
Start and stop mode
Programmable divider clock source (2n, where n = [0:8])
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
Dedicated GP output signal for using the TIMERi_GPO_CFG signal
On-the-fly read/write register (while counting)
1-ms tick with 32.768-Hz functional clock generated (only TIMER1)
5.9.6.7 I2C
The device includes 2 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
注
Note that, I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not
supported.
注
Inter-integrated circuit i (i=1 to 2) module is also referred to as I2Ci.
146
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
For more information, see the Multimaster I2C Controller section of the Device TRM.
表 5-39 and 图 5-38 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-39. Timing Requirements for I2C Input Timings(1)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
3
th(SDAL-SCLL)
0.6
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
0(3)
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
3.45(4)
0.9(4)
Pulse duration, SDA high between STOP and
START conditions
8
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
ns
ns
ns
ns
µs
20 + 0.1Cb
9
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
(5)
20 + 0.1Cb
10
11
12
13
(5)
20 + 0.1Cb
(5)
20 + 0.1Cb
300
(5)
Setup time, SCL high before SDA high (for
STOP condition)
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
14
15
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(5)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
147
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
9
11
I2Ci_SDA
6
8
14
4
13
5
10
I2Ci_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
SPRS91v_I2C_01
图 5-38. I2C Receive Timing
表 5-40 and 图 5-39 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-40. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
18
th(SDAL-SCLL)
0.6
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
Hold time, SDA valid after SCL low (for I2C
bus devices)
22
23
24
25
26
27
th(SCLL-SDAV)
tw(SDAH)
tr(SDA)
0
3.45
0
0.9
µs
µs
ns
ns
ns
ns
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
20 + 0.1Cb
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
(1)
20 + 0.1Cb
tr(SCL)
(1)
20 + 0.1Cb
tf(SDA)
(1)
20 + 0.1Cb
tf(SCL)
300
(1)
Setup time, SCL high before SDA high (for
STOP condition)
28
29
tsu(SCLH-SDAH)
Cp
4
0.6
µs
pF
Capacitance for each I2C pin
10
10
148
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
26
24
I2Ci_SDA
I2Ci_SCL
21
23
19
28
20
25
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
SPRS91v_I2C_02
图 5-39. I2C Transmit Timing
5.9.6.8 UART
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. There are 3 UART modules in the device. Each
UART can be used for configuration and data exchange with a number of external peripheral devices or
interprocessor communication between devices.
The UARTi (where i = 1 to 3) include the following features:
•
•
•
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
注
For more information, see the UART section of the Device TRM.
表 5-41, 表 5-42 and 图 5-40 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-41. Timing Requirements for UART
NO.
4
PARAMETER
DESCRIPTION
MIN
0.96U(1)
0.96U(1)
P(2)
MAX
UNIT
ns
tw(RX)
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
1.05U(1)
1.05U(1)
5
tw(CTS)
ns
td(RTS-TX)
td(CTS-TX)
ns
P(2)
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
149
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
表 5-42. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
MAX
12
UNIT
15 pF
30 pF
100 pF
f(baud)
Maximum programmable baud rate
0.23
MHz
0.115
U + 2(1)
U + 2(1)
2
3
tw(TX)
Pulse width, transmit data bit, 15/30/100 pF high or low
Pulse width, transmit start bit, 15/30/100 pF high or low
U - 2(1)
U - 2(1)
ns
ns
tw(RTS)
(1) U = UART baud time = 1/programmed baud rate
3
2
Start
Bit
UARTi_TXD
Data Bits
5
4
Start
Bit
UARTi_RXD
Data Bits
SPRS91v_UART_01
图 5-40. UART Timing
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-43.
In 表 5-43 are presented the specific groupings of signals (IOSET) for use with UART.
表 5-43. UART1-3 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
UART1
F13
MUX
BALL
MUX
uart1_rxd
uart1_txd
uart1_rtsn
uart1_ctsn
F13
E14
0
0
0
0
0
0
E14
C14
F14
UART2
D14
uart2_rxd
uart2_txd
uart2_rtsn
uart2_ctsn
E7
F7
2
2
0
0
0
0
D15
F16
F15
UART3
L1
uart3_rxd
uart3_txd
uart3_rtsn
W7
W6
4
4
1
1
1
M2
R6
T5
1
1
1
L2
R7
150
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-43. UART1-3 IOSETs (continued)
SIGNALS
uart3_ctsn
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
MUX
BALL
MUX
N4
1
U6
1
5.9.6.9 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
SPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
注
For more information, see the Serial Communication Interface section of the device TRM.
注
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
表 5-44, 图 5-41 and 图 5-42 present Timing Requirements for McSPI - Master Mode.
表 5-44. Timing Requirements for SPI - Master Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SM1
tc(SPICLK)
Cycle time, spi_sclk (1) (2)
SPI1/2/3/
4
20.8
ns
SM2
SM3
tw(SPICLKL)
tw(SPICLKH)
Typical Pulse duration, spi_sclk low (1)
Typical Pulse duration, spi_sclk high (1)
0.5×P-1
(3)
ns
ns
0.5×P-1
(3)
SM4
SM5
SM6
tsu(MISO-SPICLK)
th(SPICLK-MISO)
td(SPICLK-SIMO)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
Hold time, spi_d[x] valid after spi_sclk active edge (1)
Delay time, spi_sclk active edge to spi_d[x] transition (1)
2.29
2.67
ns
ns
ns
ns
ns
SPI1/2/4
SPI3
-3.57
-3.57
3.57
3.57
3.57
SM7
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
151
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-44. Timing Requirements for SPI - Master Mode (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SM8
td(CS-SPICLK)
Delay time, spi_cs[x] active to spi_sclk first edge (1)
MASTER B-4.2 (5)
ns
_PHA0
(4)
MASTER A-4.2 (6)
ns
ns
ns
_PHA1
(4)
SM9
td(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)
MASTER A-4.2 (6)
_PHA0
(4)
MASTER B-4.2 (5)
_PHA1
(4)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) P = SPICLK period.
(4) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(5) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(6) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(7) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
152
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
spim_cs(OUT)
spim_sclk(OUT)
PHA=0
EPOL=1
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SM1
SM3
SM2
spim_sclk(OUT)
spim_d(OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
spim_d(OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRS91v_McSPI_01
图 5-41. McSPI - Master Mode Transmit
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
153
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
SM2
POL=1
spim_sclk(OUT)
SM5
SM5
SM4
SM4
Bit n-2
Bit n-1
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS91v_McSPI_02
图 5-42. McSPI - Master Mode Receive
表 5-45, 图 5-43 and 图 5-44 present Timing Requirements for McSPI - Slave Mode.
表 5-45. Timing Requirements for SPI - Slave Mode(5)
NO.
PARAMETER
DESCRIPTION
MODE
SPI1
MIN
MAX
UNIT
ns
SS1 (1) tc(SPICLK)
Cycle time, spi_sclk
25
33.3
0.45×P
0.45×P
2.82
2.82
2
(2)
SPI2/3/4
ns
SS2 (1) tw(SPICLKL)
SS3 (1) tw(SPICLKH)
SS4 (1) tsu(SIMO-SPICLK)
SS5 (1) th(SPICLK-SIMO)
SS6 (1) td(SPICLK-SOMI)
Typical Pulse duration, spi_sclk low
ns
(3)
(3)
Typical Pulse duration, spi_sclk high
ns
Setup time, spi_d[x] valid before spi_sclk active edge
Hold time, spi_d[x] valid after spi_sclk active edge
Delay time, spi_sclk active edge to mcspi_somi transition
ns
ns
SPI1
9.8
21
16
ns
SPI2/3/4
2
ns
SS7 (4) td(CS-SOMI)
SS8 (1) tsu(CS-SPICLK)
Delay time, spi_cs[x] active edge to mcspi_somi transition
Setup time, spi_cs[x] valid before spi_sclk first edge
ns
2.82
ns
154
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-45. Timing Requirements for SPI - Slave Mode(5) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS9 (1) th(SPICLK-CS)
Hold time, spi_cs[x] valid after spi_sclk last edge
2.82
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) P = SPICLK period.
(4) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(5) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
SS1
SS2
spim_sclk(IN)
spim_d(OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
spim_sclk(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
spim_sclk(IN)
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRS91v_McSPI_03
图 5-43. McSPI - Slave Mode Transmit
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
155
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
spim_sclk(IN)
SS1
SS2
POL=1
spim_sclk(IN)
SS5
SS4
Bit n-1
SS4
SS5
Bit n-2
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
spim_sclk(IN)
spim_sclk(IN)
SS1
SS3
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS91v_McSPI_04
图 5-44. McSPI - Slave Mode Receive
CAUTION
The IO timings provided in this section are applicable for all combinations of
signals for SPI2 and SPI4. However, the timings are only valid for SPI1 and
SPI3 if signals within a single IOSET are used. The IOSETs are defined in 表 5-
46.
In 表 5-46 are presented the specific groupings of signals (IOSET) for use with McSPI.
表 5-46. McSPI1/3 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
SPI1
M2
MUX
BALL
MUX
spi1_sclk
spi1_d1
M2
U6
0
0
0
0
M2
U6
0
0
U6
156
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
SIGNALS
表 5-46. McSPI1/3 IOSETs (continued)
IOSET1
IOSET2
IOSET3
BALL
T5
MUX
BALL
T5
MUX
BALL
T5
MUX
spi1_d0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
0
0
0
0
0
0
0
R6
R6
R6
R5
F14
C14
SPI3
C6
5
5
spi3_sclk
spi3_d1
spi3_d0
spi3_cs0
F15
D14
D15
F16
4
4
4
4
4
4
4
4
F7
E7
B6
5.9.6.10 QSPI
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
•
•
•
•
•
•
•
•
Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer
注
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
表 5-47 and 表 5-48 present Timing and Switching Characteristics for Quad SPI Interface.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
157
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-47. Switching Characteristics for QSPI
No
PARAMETER
DESCRIPTION
Mode
MIN
MAX
UNIT
1
tc(SCLK)
Cycle time, sclk
Default
Timing
Mode,
Clock
10.4
ns
Mode 0
Default
Timing
Mode,
Clock
15.625
ns
Mode 3
2
3
4
tw(SCLKL)
tw(SCLKH)
td(CS-SCLK)
Pulse duration, sclk low
Y×P-1
(1)
ns
ns
ns
Pulse duration, sclk high
Y×P-1
(1)
Delay time, sclk falling edge to cs active edge, CS3:0
Default
Timing
Mode
-M×P-1
(2) (3)
-M×P+1
(2) (3)
5
6
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge, CS3:0
Delay time, sclk falling edge to d[0] transition
Default
Timing
Mode
N×P-1
(2) (3)
N×P+1
(2) (3)
ns
ns
td(SCLK-D1)
Default
Timing
Mode
-1
1
7
8
9
tena(CS-D1LZ)
tdis(CS-D1Z)
td(SCLK-D1)
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
Delay time, sclk first falling edge to first d[0] transition
-P-3.5
-P-2.5
-1-P
-P+2.5
-P+2.0
-1-P
ns
ns
ns
PHA=0
Only,
Default
Timing
Mode
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device TRM.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3. N = 2 when Clock Mode 0. N
= 3 when Clock Mode 3.
158
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
cs
Q5
Q1
PHA=1
POL=1
Q4
Q3
Q2
sclk
Q15
Q14
Q12
Q6
Q13
Read Data
Bit 1
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 0
d[0]
Q15
Q14
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_01
图 5-45. QSPI Read (Clock Mode 3)
cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
rtclk
POL=0
Q12
Q13
Q12 Q13
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
Read Data
Bit 0
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_02
图 5-46. QSPI Read (Clock Mode 0)
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
159
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-48. Timing Requirements for QSPI
No
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
12
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling rtclk edge
Default
Timing
Mode,
Clock
2.9
ns
Mode 0
tsu(D-SCLK)
th(RTCLK-D)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Default
Timing
Mode,
Clock
5.7
-0.1
0.1
ns
ns
ns
ns
ns
Mode 3
13
Default
Timing
Mode,
Clock
Mode 0
Hold time, d[3:0] valid after falling sclk edge
Default
Timing
Mode,
Clock
Mode 3
14
15
Setup time, final d[3:0] bit valid before final falling sclk edge
Hold time, final d[3:0] bit valid after final falling sclk edge
Default 5.7-P (1)
Timing
Mode,
Clock
Mode 3
Default 0.1+P (1)
Timing
Mode,
Clock
Mode 3
(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
cs
Q5
Q1
PHA=1
Q4
Q3
Q2
POL=1
sclk
Q8
Q6
Q6
Q6
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_03
图 5-47. QSPI Write (Clock Mode 3)
160
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_04
图 5-48. QSPI Write (Clock Mode 0)
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-29 and described in Device TRM, Control
Module section.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-49.
In 表 5-49 are presented the specific groupings of signals (IOSET) for use with QSPI.
表 5-49. QSPI IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
IOSET4
BALL
C8
MUX
BALL
C8
MUX
BALL
C8
MUX
BALL
C8
MUX
qspi1_sclk
qspi1_rtclk
qspi1_d0
qspi1_d1
qspi1_d2
qspi1_d3
qspi1_cs0
qspi1_cs1
1
8
1
1
1
1
1
5
1
1
1
1
1
1
1
5
1
5
1
1
1
1
1
5
1
2
1
1
1
1
1
5
C14
B9
B7
F13
B9
D8
B9
B9
F10
A9
F10
A9
F10
A9
F10
A9
D10
E10
F15
D10
E10
F15
D10
E10
F15
D10
E10
F15
5.9.6.11 McASP
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
161
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
For more information, see the Serial Communication Interface section of the Device TRM.
表 5-50, 表 5-51, 表 5-52 and 图 5-49 present Timing Requirements for McASP1 to McASP3.
(1)
表 5-50. Timing Requirements for McASP1
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
ns
(2)
3
tc(ACLKRX)
Cycle time, ACLKR/X
Any Other Conditions
20
ns
ns
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
15.258
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
0.5R - 3
ns
ns
(3)
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
0.38R
(3)
5
6
7
8
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
18.5
3
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
0.5
0.4
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
18.5
3
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
0.5
0.4
ns
ns
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
(1)
表 5-51. Timing Requirements for McASP2
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
ns
(2)
3
tc(ACLKRX)
Cycle time, ACLKR/X
Any Other Conditions
20
ns
ns
IOSET1 only,
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
15.258
162
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1)
表 5-51. Timing Requirements for McASP2 (continued)
NO.
PARAMETER
DESCRIPTION
Pulse duration, ACLKR/X high or low
MODE
Any Other Conditions
MIN
MAX
UNIT
4
tw(ACLKRX)
0.5R - 3
ns
(3)
IOSET1 only,
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
0.38R
ns
(3)
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
ACLKR/X int
18.5
4
ns
ns
IOSET1 (vout1_*):
ACLKR/X ext in
IOSET1 (vout1_*):
ACLKR/X ext out
IOSET2 (gpmc_*):
ACLKR/X ext in
3
ns
IOSET2 (gpmc_*):
ACLKR/X ext out
6
7
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
ACLKR/X int
0.5
0.4
ns
ns
ACLKR/X ext in
ACLKR/X ext out
tsu(AXR-ACLK)
ACLKR/X int
18.5
12
ns
ns
IOSET1 (vout1_*):
ACLKR/X ext in
IOSET1 (vout1_*):
ACLKR/X ext out
IOSET2 (gpmc_*):
ACLKR/X ext in
3
ns
IOSET2 (gpmc_*):
ACLKR/X ext out
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
0.5
0.4
ns
ns
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
(1)
表 5-52. Timing Requirements for McASP3
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
20
MAX
UNIT
ns
Cycle time, AHCLKX
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
Cycle time, ACLKR/X
0.35P
20
ns
3
tc(ACLKRX)
ns
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Setup time, AFSR/X input valid before ACLKR/X
0.5R - 3
18.2
4
ns
5
tsu(AFSRX-ACLK)
ACLKR/X int
ns
ACLKR/X ext in
ACLKR/X ext out
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
ACLKR/X int
0.5
0.4
ns
ns
ACLKR/X ext in
ACLKR/X ext out
tsu(AXR-ACLK)
ACLKX int (ASYNC=0)
18.2
12
ns
ns
ACLKR/X ext in
ACLKR/X ext out
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
163
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1)
表 5-52. Timing Requirements for McASP3 (continued)
NO.
PARAMETER
DESCRIPTION
Hold time, AXR input valid after ACLKX
MODE
MIN
0.5
MAX
UNIT
ns
8
th(ACLK-AXR)
ACLKX int (ASYNC=0)
ACLKR/X ext in
ACLKR/X ext out
0.5
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
2
1
2
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS91v_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
图 5-49. McASP Input Timing
164
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-53, 表 5-54, 表 5-55 and 图 5-50 present Switching Characteristics Over Recommended Operating
Conditions for McASP1 to McASP3.
(1)
表 5-53. Switching Characteristics Over Recommended Operating Conditions for McASP1
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
ns
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
22.2
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
22.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
(1)
表 5-54. Switching Characteristics Over Recommended Operating Conditions for McASP2
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
ns
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
22.2
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
22.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
(1)
表 5-55. Switching Characteristics Over Recommended Operating Conditions for McASP3
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5
ns
11
tc(ACLKRX)
Cycle time, ACLKR/X
20
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
165
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1)
表 5-55. Switching Characteristics Over Recommended Operating Conditions for McASP3 (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5P -
2.5
ns
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.1
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
ACLKR/X int
0
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.1
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
166
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
10
10
9
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
12
11
12
(A)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS91v_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
图 5-50. McASP Output Timing
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented 表 4-29 and described in Device TRM, Control
Module section.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
167
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-56.
In 表 5-56 and 表 5-57 are presented the specific groupings of signals (IOSET) for use with McASP1 and
McASP2.
表 5-56. McASP1 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
U17
MUX
1
BALL
U17
MUX
BALL
U17
MUX
mcasp1_aclkx
mcasp1_fsx
1
1
1
1
W17
AA17
U16
1
W17
W17
mcasp1_aclkr
mcasp1_fsr
1
1
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
W16
V16
1
W16
V16
1
1
W16
V16
1
1
1
U15
1
V15
1
Y15
1
W15
AA15
AB15
AA14
AB14
1
1
1
1
AA14
AB14
U13
V13
1
1
1
1
1
1
1
1
U15
V15
Y15
W15
AA15
AB15
U7
4
4
4
4
4
4
4
4
1
Y13
W13
U11
V11
V7
表 5-57. McASP2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
Y13
U11
V11
W13
W11
V9
MUX(1)
15
BALL
C6
F7
MUX(1)
mcasp2_ahclkx
mcasp2_aclkx
mcasp2_fsx
15
15
15
15
15
15
15
15
15
15
15
15
15
E7
mcasp2_aclkr
mcasp2_fsr
15
B6
15
A5
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
mcasp2_axr5
15
D6
C5
B5
W9
15
U8
15
W8
15
D7
B4
U7
15
V7
15
A4
168
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) All McASP2 signals are virtual functions that present alternate multiplexing options. These virtual functions are controlled via
CTRL_CORE_SMA_SW_* registers. For more information on how to use these options, please refer to Device TRM, Chapter Control
Module, Section Pad Configuration Registers.
5.9.6.12 DCAN and MCAN
5.9.6.12.1 DCAN
The device provides one DCAN interface for supporting distributed realtime control with a high level of
security.
The DCAN interface implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM single error correction and double error detection (SECDED) mechanism
Direct access to Message RAM during test mode
Support for two interrupt lines: Level 0 and Level 1, plus separate ECC interrupt line
Local power down and wakeup support
Automatic message RAM initialization
Support for DMA access
5.9.6.12.2 MCAN
The device supports one MCAN module connecting to the CAN network through external (for the device)
transceiver for connection to the physical layer. The MCAN module supports up to 5 Mbit/s data rate and
is compliant to ISO 11898-1:2015.
The MCAN module implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Conforms with ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)
AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 filter elements
Internal Loopback mode for self-test
Maskable interrupts, two interrupt lines
Two clock domains (CAN clock/Host clock)
Parity/ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
•
•
Local power-down and wakeup support
Timestamp Counter
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
169
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
For more information, see the Serial Communication Interfaces / DCAN and MCAN sections
of the Device TRM.
注
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter
tolerance calculations must be performed to validate the implementation.
表 5-58 and 表 5-59 present Timing and Switching characteristics for DCAN and MCAN Interface.
表 5-58. Timing Requirements for CAN Receive
NO.
PARAMETER
f(baud)
td(CANnRX)
DESCRIPTION
Maximum programmable baud rate
MIN
NOM
MAX
1
UNIT
Mbps
ns
-
Delay time, CANnRX pin to receive shift register
10
表 5-59. Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
NO.
PARAMETER
f(baud)
td(CANnTX)
DESCRIPTION
Maximum programmable baud rate
Delay time, Transmit shift register to CANnTX pin(1)
MIN
MAX
1
UNIT
Mbps
ns
-
10
(1) These values do not include rise/fall times of the output buffer.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-60.
In 表 5-60 are presented the specific groupings of signals (IOSET) for use with DCAN and MCAN.
表 5-60. DCAN and MCAN IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
IOSET4
BALL
MUX
BALL
MUX
DCAN1
12
BALL
MUX
BALL
MUX
dcan1_tx
dcan1_rx
N5
N6
0
0
D14
D15
F14
C14
12
12
12
MCAN
0
mcan_tx
mcan_rx
W7
W6
F13
E14
12
12
F15
F16
12
12
0
5.9.6.13 GMAC_SW
The two-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides Reduced Gigabit Media Independent Interface
(RGMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY) management.
注
For more information, see the Gigabit Ethernet Switch (GMAC_SW) section of the Device
TRM.
170
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
注
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
RGMIIn
5.9.6.13.1 GMAC MDIO Interface Timings
表 5-61, 表 5-62 and 图 5-51 present Timing Requirements for MDIO.
表 5-61. Timing Requirements for MDIO Input
No
1
PARAMETER
tc(MDC)
DESCRIPTION
MIN
400
160
160
90
MAX
UNIT
ns
Cycle time, MDC
2
tw(MDCH)
Pulse Duration, MDC High
Pulse Duration, MDC Low
Setup time, MDIO valid before MDC High
Hold time, MDIO valid from MDC High
ns
3
tw(MDCL)
ns
4
tsu(MDIO-MDC)
th(MDIO_MDC)
ns
5
0
ns
表 5-62. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
No
6
PARAMETER
tt(MDC)
DESCRIPTION
MIN
MAX
5
UNIT
ns
Transition time, MDC
7
td(MDC-MDIO)
Delay time, MDC High to MDIO valid
10
390
ns
1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
SPRS91v_GMAC_07
图 5-51. GMAC MDIO diagrams
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
171
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.6.13.2 GMAC RGMII Timings
表 5-63, 表 5-64 and 图 5-52 present timing requirements for receive RGMIIn operation.
表 5-63. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(RXC)
Cycle time, rgmiin_rxc
440
44
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(RXCH)
tw(RXCL)
tt(RXC)
Pulse duration, rgmiin_rxc high
Pulse duration, rgmiin_rxc low
Transition time, rgmiin_rxc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-64. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
NO.
5
PARAMETER
tsu(RXD-RXCH)
th(RXCH-RXD)
DESCRIPTION
MIN
1.15
1.15
MAX
UNIT
ns
Setup time, receive selected signals valid before rgmiin_rxc high/low
Hold time, receive selected signals valid after rgmiin_rxc high/low
6
ns
(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
(2) RGMII0 requires that the 4 data pins rgmii0_rxd[3:0] and rgmii0_rxctl have their board propagation delays matched within 50pS of
rgmii0_rxc.
(3) RGMII1 requires that the 4 data pins rgmii1_rxd[3:0] and rgmii1_rxctl have their board propagation delays matched within 50pS of
rgmii1_rxc.
1
4
2
4
3
rgmiin_rxc(A)
5
1st Half-byte
6
2nd Half-byte
rgmiin_rxd[3:0](B)
rgmiin_rxctl(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
SPRS91v_GMAC_08
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
图 5-52. GMAC Receive Interface Timing, RGMIIn operation
表 5-65, 表 5-66 and 图 5-53 present switching characteristics for rgmiin_txctl - RGMIIn Operation for
10/100/1000 Mbit/s
172
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-65. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX
440
44
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(TXC)
Cycle time, rgmiin_txc
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-66. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
5
tosu(TXD-TXC)
Output Setup time, transmit selected signals
valid to rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
ns
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
1.2
1.2
6
toh(TXC-TXD)
Output Hold time, transmit selected signals
valid after rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
RGMII0, Internal Delay
Enabled, 10/100 Mbps
RGMII1, Internal Delay
Enabled, 1000 Mbps
RGMII1, Internal Delay
Enabled, 10/100 Mbps
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
173
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 1000Mbps operation is not supported.
(3) RGMII1 1000Mbps operation is not supported.
1
4
2
4
3
rgmiin_txc(A)
[internal delay enabled]
5
rgmiin_txd[3:0](B)
rgmiin_txctl(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
6
SPRS91v_GMAC_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
图 5-53. GMAC Transmit Interface Timing RGMIIn operation
5.9.6.14 SDIO Controller
MMC interface is compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it
supports the following applications:
•
•
•
•
MMC 4-bit data, SD Default speed, SDR
MMC 4-bit data, SD High speed, SDR
MMC 4-bit data, UHS-I SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle
MMC 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
注
For more information, see the SDIO Controller chapter of the Device TRM.
5.9.6.14.1 MMC, SD Default Speed
图 5-54, 图 5-55, 表 5-67, and 表 5-68 present Timing requirements and Switching characteristics for MMC
- SD and SDIO Default speed in receiver and transmiter mode.
表 5-67. Timing Requirements for MMC - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 3
表 5-68. Switching Characteristics for MMC - SD/SDIO Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
24
0.5×P-
0.270
174
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-68. Switching Characteristics for MMC - SD/SDIO Default Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DS2
tw(clkL)
Pulse duration, mmc_clk low
0.5×P-
0.270
ns
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmc_clk
mmc_cmd
DS6
DS5
DS8
DS7
mmc_dat[3:0]
SPRS91v_MMC_01
图 5-54. MMC/SD/SDIOj in - Default Speed - Receiver Mode
DS2
DS1
DS0
mmc_clk
DS3
DS4
mmc_cmd
mmc_dat[3:0]
SPRS91v_MMC_02
图 5-55. MMC/SD/SDIOj in - Default Speed - Transmiter Mode
5.9.6.14.2 MMC, SD High Speed
图 5-56, 图 5-57, 表 5-69, and 表 5-70 present Timing requirements and Switching characteristics for MMC
- SD and SDIO High speed in receiver and transmiter mode.
表 5-69. Timing Requirements for MMC - SD/SDIO High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
ns
ns
th(clkH-dV)
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
175
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) i in [i:0] = 3
表 5-70. Switching Characteristics for MMC - SD/SDIO High Speed Mode
NO.
HS1
PARAMETER
fop(clk)
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
48
HS2H
tw(clkH)
0.5×P-
0.270
HS2L
tw(clkL)
Pulse duration, mmc_clk low
0.5×P-
0.270
ns
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
-7.6
-7.6
3.6
3.6
ns
ns
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
HS1
HS2H
HS2L
mmc_clk
mmc_cmd
HS4
HS3
HS7
HS8
mmc_dat[3:0]
SPRS91v_MMC_03
图 5-56. MMC/SD/SDIOj in - High Speed - Receiver Mode
HS1
HS2H
HS2L
mmc_clk
mmc_cmd
HS5
HS5
HS6
HS6
mmc_dat[3:0]
SPRS91v_MMC_04
图 5-57. MMC/SD/SDIOj in - High Speed - Transmiter Mode
5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
图 5-58, 图 5-59, 表 5-71, and 表 5-72 present Timing requirements and Switching characteristics for MMC
- SD and SDIO SDR12 in receiver and transmiter mode.
表 5-71. Timing Requirements for MMC - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
ns
25.99
1.6
ns
ns
176
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) i in [i:0] = 3
表 5-72. Switching Characteristics for MMC - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
24
0.5×P-
0.270
SDR122 tw(clkL)
Pulse duration, mmc_clk low
0.5×P-
0.270
ns
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
SDR122
SDR121
SDR120
mmc_clk
mmc_cmd
SDR126
SDR125
SDR128
SDR127
mmc_dat[3:0]
SPRS91v_MMC_05
图 5-58. MMC/SD/SDIOj in - SDR12 - Receiver Mode
SDR122
SDR121
SDR120
mmc_clk
SDR123
SDR124
mmc_cmd
mmc_dat[3:0]
SPRS91v_MMC_06
图 5-59. MMC/SD/SDIOj in - SDR12 - Transmiter Mode
5.9.6.14.4 MMC, SD SDR25 Mode
图 5-60, 图 5-61, 表 5-73, and 表 5-74 present Timing requirements and Switching characteristics for MMC
- SD and SDIO SDR25 in receiver and transmiter mode.
(1)
表 5-73. Timing Requirements for MMC - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR253 tsu(cmdV-clkH)
SDR254 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
ns
ns
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
177
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) i in [i:0] = 3
(2)
表 5-74. Switching Characteristics for MMC - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
48
SDR252 tw(clkH)
H
0.5×P-
0.270
SDR252L tw(clkL)
Pulse duration, mmc_clk low
0.5×P-
0.270
ns
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR253
SDR252H
mmc_clk
mmc_cmd
SDR254
SDR258
SDR257
mmc_dat[3:0]
SPRS91v_MMC_07
图 5-60. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
SDR255
mmc_clk
mmc_cmd
SDR255
SDR256
SDR256
mmc_dat[3:0]
SPRS91v_MMC_08
图 5-61. MMC/SD/SDIOj in - SDR25 - Transmiter Mode
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-75.
In 表 5-75 are presented the specific groupings of signals (IOSET) for use with MMC.
表 5-75. MMC IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
C16
C17
E16
MUX
BALL
W16
V16
MUX
BALL
B18
MUX
mmc_clk
mmc_cmd
mmc_dat0
mmc_dat1
5
5
5
5
5
5
5
5
5
5
5
5
C18
A19
U15
D16
V15
B20
178
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
SIGNALS
表 5-75. MMC IOSETs (continued)
IOSET1
IOSET2
IOSET3
BALL
E17
MUX
BALL
Y15
MUX
BALL
C20
MUX
mmc_dat2
mmc_dat3
5
5
5
5
5
5
F17
W15
A20
5.9.6.15 GPIO
The general-purpose interface combines four general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 126 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
•
Wake-up request generation in idle mode upon the detection of external events
注
For more information, see the General-Purpose Interface chapter of the Device TRM.
注
The general-purpose input/output i (i = 1 to 4) bank is also referred to as GPIOi.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in 表 5-76.
In 表 5-76 are presented the specific groupings of signals (IOSET) for use with GPIO.
表 5-76. GPIO2/3/4 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
GPIO2
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_20
gpio2_23
gpio2_24
gpio2_27
gpio2_28
gpio2_29
gpio2_30
gpio2_31
J17
K22
14
14
14
14
14
14
14
K21
K18
AB17
AA17
U16
AA17
U16
14
14
14
14
14
14
14
U15
V15
Y15
W15
AA15
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
179
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-76. GPIO2/3/4 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
GPIO3
14
BALL
MUX
gpio3_0
gpio3_9
AB15
U9
14
U9
W11
V9
14
14
14
14
14
14
gpio3_10
gpio3_11
gpio3_12
gpio3_13
gpio3_14
gpio3_15
gpio3_16
W11
V9
14
14
W9
U8
14
W9
U8
14
W8
U7
14
W8
14
V7
14
GPIO4
gpio4_4
gpio4_6
gpio4_7
gpio4_8
gpio4_9
gpio4_10
R5
N4
R7
L2
14
14
14
14
14
14
N5
N6
5.9.6.16 ATL
The device contains one ATL module that can be used for asynchronous sample rate conversion of audio.
The ATL calculates the error between two time bases, such as audio syncs, and optionally generates an
averaged clock using cycle stealing via software.
注
For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL)
chapter of the device TRM.
5.9.6.16.1 ATL Electrical Data/Timing
表 5-77 and 图 5-62 present switching characteristics for ATL
表 5-77. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
NO.
1
PARAMETER
tc(ATLCLKOUT)
tw(ATLCLKOUTL)
tw(ATLCLKOUTH)
DESCRIPTION
MIN
MAX
UNIT
ns
Cycle time, ATL_CLKOUTx
20
2
Pulse Duration, ATL_CLKOUTx low
Pulse Duration, ATL_CLKOUTx high
0.45×P - M(1)
0.45×P - M(1)
ns
3
ns
(1) P = ATL_CLKOUTx period.
M = internal ATL PCLK period.
1
2
atl_clkx
3
ATL_01
图 5-62. ATL_CLKOUTx Timing
180
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
5.9.7 Emulation and Debug Subsystem
The device includes the following Test interfaces:
•
•
IEEE 1149.1 Standard-Test-Access Port (JTAG)
Trace Port Interface Unit (TPIU)
5.9.7.1 JTAG Electrical Data/Timing
表 5-78, 表 5-79 and 图 5-63 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-78. Timing Requirements for IEEE 1149.1 JTAG
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
3
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
6.23
ns
4
31.15
31.15
ns
ns
表 5-79. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
30.5
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
图 5-63. JTAG Timing
表 5-80, 表 5-81 and 图 5-64 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-80. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
3
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
6.23
ns
4
31.15
31.15
ns
ns
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
181
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 5-81. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
DESCRIPTION
MIN
MAX
27
UNIT
5
td(TCK-RTCK)
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the Arm is in the scan chain, the delay
time is a function of the Arm functional clock).
0
ns
6
7
8
tc(RTCK)
Cycle time, RTCK
62.29
24.92
24.92
ns
ns
ns
tw(RTCKH)
tw(RTCKL)
Pulse duration, RTCK high (40% of tc)
Pulse duration, RTCK low (40% of tc)
5
TCK
6
7
8
RTCK
SPRS91v_JTAG_02
图 5-64. JTAG With RTCK Timing
5.9.7.2 Trace Port Interface Unit (TPIU)
5.9.7.2.1 TPIU PLL DDR Mode
表 5-82 and 图 5-65 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-82. Switching Characteristics for TPIU
NO.
PARAMETER
tc(clk)
DESCRIPTION
MIN
5.56
-1.61
-1.61
MAX
UNIT
ns
TPIU1
TPIU4
TPIU5
Cycle time, TRACECLK period
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL transition
Skew time, TRACECLK transition to TRACEDATA[17:0] transition
1.98
1.98
ns
td(clk-dataV)
ns
(1) P = TRACECLK period in ns
(2) The listed pulse duration is a typical value
TPIU1
TPIU2
TPIU3
TRACECLK
TRACECTL
TPIU4
TPIU4
TPIU5
TPIU5
TRACEDATA[X:0]
SPRS91v_TPIU_01
图 5-65. TPIU—PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
182
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6 Detailed Description
6.1 Description
The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can
be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (S-PBGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive co-processor,
hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the
DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x
"Jacinto 6 Entry" family of infotainment processors, including voice, HMI, multimedia and smartphone
projection mode capabilities.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers
and a debugging interface for visibility into source code execution.
The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-
Q100 standard.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
6.2 Functional Block Diagram
图 6-1 is functional block diagram for the device.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
183
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Display
Subsystem
IPU with ECC
DSP Subsystem x2
L1P 32KiB
L2
2x Cortex-M4
16KiB ROM
C66x
256KiB
Cache
DVOUT
L1D 32KiB
Vision
Accelerator
SD-DAC
EDMA 2TC
EVE 16MAC
OSD
Resizing
CSC
Video Front End
Video Input Port
EDMA 2TC
up to 512KiB RAM
with ECC
Radio Accelerator
HD ATL
Interconnect
DRA78x
JTAG
PLLs
OSC
Serial Interfaces
Connectivity
System
I2C x2
McSPI x4
QSPI x1
SDIO x1
UART x3
EDMA
GPIO x4
PWMSS x1
MMU x1
PRCM
Timer x8
GEMAC Switch
McASP x3
Mailbox/Spinlock
10-bit ADC
DCAN (with ECC)
MCAN (CAN-FD)
with ECC
Control Module
RTI x5
Memory Controllers
GPMC 8b/16b
with up to 16b ECC
DDR2/DDR3/DDR3L
32b with 8b ECC
func_sprs968-001
Copyright © 2016, Texas Instruments Incorporated
图 6-1. DRA78x Block Diagram
6.3 DSP Subsystem
The device includes two identical instances (DSP1 and DSP2) of a digital signal processor (DSP)
subsystem, based on the TI's standard TMS320C66x™ DSP CorePac core.
The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating
point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible
with the C64x+/C674x DSPs.
For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set
Reference Guide, (SPRUGH7).
184
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Each of the two DSP subsystems integrated in the device includes the following components:
• A TMS320C66x™ CorePac DSP core that encompasses:
–
–
–
–
–
–
–
L1 program-dedicated (L1P) cacheable memory
L1 data-dedicated (L1D) cacheable memory
L2 (program and data) cacheable memory
Extended Memory Controller (XMC)
External Memory Controller (EMC)
DSP CorePac located interrupt controller (INTC)
DSP CorePac located power-down controller (PDC)
•
Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and
peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The
external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from
the DSP1/DSP2 dedicated outputs of the device DMA Events Crossbar for each of the two
subsystems.
•
•
•
A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the
subsystem or the remainder of the device via the device L3_MAIN interconnect.
Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the
device L3_MAIN interconnect address space.
Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation,
and connection to the device power, reset, and clock management (PRCM) module
The TMS320C66x Instruction Set Architecture (ISA) is the latest for the C6000 family. As with its
predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional
units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total
of 64 general-purpose 32-bit registers.
Some features of the DSP C6000 family devices are:
•
•
•
•
Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:
–
–
Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
Allows designers to develop highly effective RISC-like code for fast development time
Instruction packing:
–
–
Gives code size equivalence for eight instructions executed serially or in parallel
Reduces code size, program fetches, and power consumption
Conditional execution of most instructions:
–
–
Reduces costly branching
Increases parallelism for higher sustained performance
Efficient code execution on independent functional units:
–
–
Industry's most efficient C compiler on DSP benchmark suite
Industry's first assembly optimizer for fast development and improved parallelization
•
•
8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications.
40-bit arithmetic options which add extra precision for vocoders and other computationally intensive
applications.
•
•
Saturation and normalization to provide support for key arithmetic operations.
Field manipulation and instruction extract, set, clear, and bit counting support common operation found
in control and data manipulation applications.
The C66x CPU has the following additional features:
•
•
•
Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.
Quad 8-bit and dual 16-bit instruction set extensions with data flow support.
Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
185
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Special communication-specific instructions have been added to address common operations in error-
correcting codes.
•
•
Bit count and rotate hardware extends support for bit-level algorithms.
Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce
code size.
•
Protected mode operation: A two-level system of privileged program execution to support higher-
capability operating systems and system features such as memory protection.
•
•
Exceptions support for error detection and program redirection to provide robust code execution
Hardware support for modulo loop operation to reduce code size and allow interrupts during fully-
pipelined code
•
•
Each multiplier can perform 32 × 32 bit multiplies
Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts
per clock cycle
The TMS320C66x has the following key improvements to the ISA:
•
•
•
•
4x Multiply Accumulate improvement for both fixed and floating point
Improvement of the floating point arithmetic
Enhancement of the vector processing capability for fixed and floating point
Addition of domain-specific instructions for complex arithmetic and matrix operations
On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD
instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD
operations for 8-bit data. C66x enhances this capabilities with the addition of SIMD instructions for 32-bit
data allowing operation on 128-bit vectors. For example the QMPY32 instruction is able to perform the
element to element multiplication between two vectors of four 32-bit data each.
C66x ISA includes a set of specific instructions to handle complex arithmetic and matrix operations.
186
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
TMS320C66x DSP CorePac memory components:
–
A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:
•
When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache
line
•
The DSP CorePac L1P memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
•
The L1P is capable of cache block and global coherence operations
The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM
The L1P memory can be fully configured as a cache or SRAM
Page size for L1P memory is 2KB
–
A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
•
When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache
line
•
The DSP CorePac L1D memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
The L1D memory can be fully configured as a cache or SRAM
No support for error correction or detection
Page size for L1D memory is 2KB
–
A 288-KiB (program and data) L2 memory, only part of which is cacheable:
•
When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte
cache line
•
•
•
Only 256 KiB of L2 memory can be configured as cache or SRAM
32 KiB of the L2 memory is always mapped as SRAM
The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including
necessary SRAM
•
•
The L2 memory controller supports hardware prefetching and also provides bandwidth
management, memory protection, and power-down functions.
Page size for L2 memory is 16KB
•
The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP
subsystem and device. It has :
–
a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA,
DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.
–
a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP
subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the
DSP subsystem is the slave in a transaction.
•
•
The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which
are a result of CPU instruction fetches, load/store commands, cache operations) to device resources
via the C66x DSP CorePac 128-bit master DMA (MDMA) port:
–
Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on
the MDMA port
–
Prefetch, multi-in-flight requests
A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to
the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt
controller supports up to 128 system events of which 64 interrupts are external to DSP subsystems,
collected from the DSP1/DSP2 dedicated outputs of the device Interrupt Crossbar.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
187
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Local Enhanced Direct Memory Access (EDMA) controller features:
–
–
Channel controller (CC) : 64-channel, 128 PaRAM, 2 Queues
2 x Third-party Transfer Controllers (TPTC0 and TPTC1):
•
•
Each TC has a 128-bit read port and a 128-bit write port
2KiB FIFOs on each TPTC
–
–
1-dimensional/2-dimensional (1D/2D) addressing
Chaining capability
•
DSP subsystem integrated MMUs:
Two MMUs are integrated:
–
•
The MMU0 is located between DSP MDMA master port and the device L3_MAIN interconnect
and can be optionally bypassed
•
The MMU1 is located between the EDMA master port and the device L3_MAIN interconnect
•
•
A DSP local Power-Down Controller (PDC) is responsible to power-down various parts of the DSP
C66x CorePac, or the entire DSP C66x CorePac.
The DSP subsystem System Control logic provides:
–
–
–
–
Slave idle and master standby protocols with device PRCM for powerdown
OCP Disconnect handshake for init and target busses
Asynchronous reset
Power-down modes:
•
"Clockstop" mode featuring wake-up on interrupt event. The DMA event wake-up is managed in
software.
•
•
The device DSP subsystem is supplied by a PRCM DPLL, but each DSP1/2 has integrated its own
PLL module outside the C66x CorePac for clock gating and division.
Each of the two device DSP subsystem has following port instances to connect to remaining part
of the device. See also :
–
–
–
–
A 128-bit initiator (DSP MDMA master) port for MDMA/Cache requests
A 128-bit initiator (DSP EDMA master) port for EDMA requests
A 32-bit initiator (DSP CFG master) port for configuration requests
A 128-bit target (DSP slave) port for requests to DSP memories and various peripherals
•
C66x DSP subsystems (DSPSS) safety aspects:
–
–
–
Above mentioned memory ECC/ED mechanisms
MMUs enable mapping of only the necessary application space to the processor
Memory Protection Units internal to the DSPSS (in L1P, L1D and L2 memory controllers) and
external to DSPSS (firewalls) to help define legal accesses and raise exceptions on illegal
accesses
–
Exceptions: Memory errors, various DSP errors, MMU errors and some system errors are detected
and cause exceptions. The exceptions could be handled by the DSP or by a designated safety
processor at the chip level. Note that it may not be possible for the safety processor to completely
handle some exceptions
Unsupported features on the C66x DSP core for the device are:
•
The Extended Memory Controller MPAX (memory protection and address extension) 36-bit addressing
is NOT supported
Known DSP subsystem power mode restrictions for the device are:
•
"Full logic / RAM retention" mode featuring wake-up on both interrupt or DMA event (logic in “always
on” domain). Only OFF mode is supported by DSP subsystem, requiring full boot.
For more information about C66x debug/trace support, see chapter On-Chip Debug Support of the device
TRM.
188
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.4 IPU
The Imaging Processor Unit (IPU) subsystem contains two Arm® Cortex-M4 cores (IPU_C0 and IPU_C1)
that share a common level 1 (L1) cache (called unicache). The two Cortex-M4 cores are completely
homogeneous to one another. Any task possible using one Cortex-M4 core is also possible using the
other Cortex-M4 core. Both Cortex-M4 cores could be used for tasks such as running RTOS, controlling
ISP, SIMCOP, DSS, and other functions. It is software responsibility to distribute the various tasks
between the Cortex-M4 cores for optimal performance. The integrated interrupt handling of the IPU
subsystem allows it to function as an efficient control unit.
IPU is the boot master of this device with its own boot ROM.
The key features of the IPU subsystem are:
•
Two Arm Cortex-M4 microprocessors (IPU_C0 and IPU_C1):
–
–
–
–
–
Armv7-M and Thumb®-2 instruction set architecture (ISA)
Armv6 SIMD and digital signal processor (DSP) extensions
Single-cycle MAC
Integrated nested vector interrupt controller (NVIC) (also called IPU_Cx_INTC, where x = 0, 1)
Integrated bus matrix:
•
•
•
•
Bus arbiter
Bit-banding – atomic bit manipulation
Write buffer
Memory interface (I and D) plus system interface (S) and private peripheral bus (PPB)
–
Registers:
•
•
•
•
•
Thirteen general-purpose 32-bit registers
Link register (LR)
Program counter (PC)
Program status register, xPSR
Two banked SP registers
–
–
Integrated power management
Extensive debug capabilities
•
•
Unicache interface:
–
–
–
AHBLite to unicache interface
Instruction and data interface
Supports interleaved Cortex-M4 requests
L1 cache (IPU_UNICACHE):
–
–
–
–
–
32KiB divided into 16 banks
4-way
Runs at twice the Cortex-M4 CPU frequency
Cache configuration lock/freeze/preload
Internal MMU:
•
•
•
•
•
16-entry region-based address translation
Read/write control and access type control
Runs at twice the Cortex-M4 CPU frequency
Execute Never (XN) MMU protection policy
Little-endian format
–
OCP port for configuration and cache maintenance
•
Subsystem counter timer module (SCTM) connected to unicache
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
189
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
L2 master interface (MIF):
–
–
Splitter for access to memory or OCP ports
Interleaved bank request for fast memory access
L2 internal memories:
–
–
16KiB ROM – IPU_ROM; used for device boot/initialization
64KiB banked RAM – IPU_RAM
•
•
•
L2 MMU (IPU_MMU): 32 entries with Table Walking Logic (TWL)
Wake-up generator (IPU_WUGEN): Generates wake-up request from external interrupts
Two OCP ports at IPU boundary (connected to the L3_MAIN interconnect):
–
–
Master port – allows the IPU to access system resources (memories and peripherals)
Slave port – allows other requestors to access a part of the IPU internal memory space
•
Power management:
–
–
–
–
–
Local power-management control: Configurable through the IPU_WUGEN registers.
Two sleep modes supported by Cortex-M4, controlled by its integrated interrupt controller (NVIC).
Cortex-M4 system is clock-gated in both sleep modes.
NVIC interrupt interface stays awake.
Supports L1 cache and L2 memories retention.
•
•
Error-Correcting Code (ECC) supported for both L1 unicache and L2 RAM
Debug/emulation features supported
For more information, see chapter Dual Cortex-M4 IPU Subsystem of the device TRM.
6.5 EVE
The embedded vision engine (EVE) module is a programmable imaging and vision processing engine,
intended for use in devices that serve customer electronics imaging and vision applications. Its
programmability meets late-in-development or post-silicon processing requirements, and lets third parties
or customers add differentiating features in imaging and vision products.
The device includes one instantiation of the EVE engine. A single EVE module consists of an ARP32
scalar core, a vector coprocessor (VCOP) vector core, and an Enhanced DMA (EDMA3) controller.
The EVE engine includes the following main features:
•
Two 128-bit interconnect initiator ports used for:
–
–
–
–
Paging between system-level memory (L3 SRAM/DDR) and EVE memory (primarily IBUF, WBUF)
ARP32 program fetches to system memory (through program cache)
ARP32 load or store requests to system memory
ARP32 program cache-related read requests, including prefetch/preload requests
•
•
128-bit interconnect target port used for system-level host or DMA access to EVE memory or MMR
space
Scalar core (ARP32) with the following features:
–
–
32KB program cache (direct mapped and prefetch)
32KB data memory (DMEM)
•
Vector core (VCOP):
–
–
–
–
–
32KB working buffer (WBUF)
16KB image buffer low copy A (IBUFLA)
16KB image buffer low copy B (IBUFLB)
16KB image buffer high copy A (IBUFHA)
16KB image buffer high copy B (IBUFHB)
•
•
EDMA channel controller (EDMACC): 128 PaRAM entries, 2 Queues
EDMA transfer controllers: two instances, 2k FIFO each
190
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Memory Management Units (MMUs):
–
–
–
–
32-entry TLB per MMU
Page walking with hardware
EDMA accesses and ARP32 program or data accesses to system memory space
Can limit EVE accesses to desired subset of system addresses
•
•
Configuration interconnect for MMR and debug accesses
High-performance interconnect for high throughput and high concurrency data transfers between
connected endpoints
•
•
•
•
Multiple interrupts for interrupt mapping, DMA event mapping, and interprocessor handshaking
Support for slave idle and master standby protocols for clock gating
No support for retention and memory array off modes
Error detection on all memories:
–
–
Single bit error detect on DMEM, WBUF, IBUFLA, IBUFLB, IBUFHA, and IBUFHB
Double bit error detect on program cache
•
•
Invalid instruction detection in the two processor units (ARP32 and VCOP)
Debug support:
–
Subsystem Counter Timer Module (SCTM) for counting and measuring of VCOP, EVE program
cache, and EDMA performance-related state
–
Software Messaging System Event Trace (SMSET) for trace of software messages and hardware
events
–
–
ARP32 debug support: State visibility, breakpoint, run control, cross-triggering
VCOP debug support: State visibility and run control
•
Interprocessor communication: Internal Mailbox for DSP/EVE communication
For more information, see chapter Embedded Vision Engine (EVE) of the device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
191
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.6 Memory Subsystem
6.6.1 EMIF
The EMIF module provides connectivity between DDR memory types and manages data bus read/write
accesses between external memory and device subsystems which have master access to the L3_MAIN
interconnect and DMA capability.
The EMIF module has the following capabilities:
•
•
•
•
Supports JEDEC standard-compliant DDR2-SDRAM and DDR3/DDR3L-SDRAM memory types
2-GiB SDRAM address range over one chip-select.
Supports SDRAM devices with one, two, four or eight internal banks
Data bus widths:
–
–
–
128-bit L3_MAIN (system) interconnect data bus width
32-bit SDRAM data bus width
16-bit SDRAM data bus width used in narrow mode
•
Supported CAS latencies:
–
–
DDR3: 5, 6, 7, 8, 9, 10 and 11
DDR2: 2, 3, 4, 5, 6 and 7
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports 256-, 512-, 1024-, and 2048-word page sizes
Supported burst length: 8
Supports sequential burst type
SDRAM auto initialization from reset or configuration change
Supports self refresh and power-down modes for low power
Partial array self-refresh mode for low power when DDR3 is used
Output impedance (ZQ) calibration for DDR3
Supports on-die termination (ODT) for DDR2 and DDR3
Supports prioritized refresh
Programmable SDRAM refresh rate and backlog counter
Programmable SDRAM timing parameters
Write and read leveling/calibration and data eye training for DDR3
ECC on the SDRAM data bus:
–
–
–
–
–
–
–
–
7-bit ECC over 32-bit data
6-bit ECC over 16-bit data when narrow mode is used
1-bit error correction and 2-bit error detection
Programmable address ranges to define ECC protected region
ECC calculated and stored on all writes to ECC protected address region
ECC verified on all reads from ECC protected address region
Statistics for 1-bit ECC and 2-bit ECC errors
The total width of the ECC DDR data bus is 8 bits
The EMIF module does not support:
•
•
•
•
•
•
Burst chop for DDR3
Interleave burst type
Auto precharge because of better Bank Interleaving performance
OCD calibration for DDR2
CAS Read Latency of 2 and CAS Write Latency of 1 for DDR2
DLL disabling from EMIF side
192
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem
of the device TRM.
6.6.2 GPMC
The General Purpose Memory Controller (GPMC) is an external memory controller of the device. Its data
access engine provides a flexible programming model for communication with all standard memories.
The GPMC supports the following various access types:
•
•
•
•
•
•
•
•
Asynchronous read/write access
Asynchronous read page access (4, 8, and 16 Word16)
Synchronous read/write access
Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16)
Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16)
Address-data-multiplexed (AD) access
Address-address-data (AAD) multiplexed access
Little- and big-endian access
The GPMC can communicate with a wide range of external devices:
•
•
•
•
•
•
External asynchronous or synchronous 8-bit wide memory or device (non burst device)
External asynchronous or synchronous 16-bit wide memory or device
External 16-bit non-multiplexed NOR flash device
External 16-bit address and data multiplexed NOR Flash device
External 8-bit and 16-bit NAND flash device
External 16-bit pseudo-SRAM (pSRAM) device
The main features of the GPMC are:
•
•
8- or 16-bit-wide data path to external memory device
Supports up to eight CS regions of programmable size and programmable base addresses in a total
address space of 1 GiB
•
•
Supports transactions controlled by a firewall
On-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or
Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with
512-byte page size or greater)
•
•
•
•
Fully pipelined operation for optimal memory bandwidth use
The clock to the external memory is provided from GPMC functional clock divided by 1, 2, 3, or 4
Supports programmable autoclock gating when no access is detected
Independent and programmable control signal timing parameters for setup and hold time on a per-chip
basis. Parameters are set according to the memory device timing parameters, with a timing granularity
of one GPMC functional clock cycle.
•
Flexible internal access time control (WAIT state) and flexible handshake mode using external WAIT
pin monitoring
•
•
•
Support bus keeping
Support bus turnaround
Prefetch and write posting engine associated with a device DMA to achieve full performance from the
NAND device with minimum effect on NOR/SRAM concurrent access
For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory
Subsystem of the device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
193
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.6.3 ELM
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction
process is delegated to the memory controller.
The ELM supports the following features:
•
•
•
•
4, 8, and 16 bits per 512-byte block error location based on BCH algorithm
Eight simultaneous processing contexts
Page-based and continuous modes
Interrupt generation when error location process completes:
–
–
When the full page has been processed in page mode
For each syndrome polynomial (checksum-like information) in continuous mode
For more information, see section Error Location Module (ELM) in chapter Memory Subsystem of the
device TRM.
6.6.4 OCMC
There is one on-chip memory controller (OCMC) in the device.
The OCM Controller supports the following features:
•
•
L3_MAIN data interface:
–
–
–
Used for maximum throughput performance
128-bit data bus width
Burst supported
L4 interface:
–
–
–
–
Used for access to configuration registers
32-bit data bus width
Only single accesses supported
The L4 associated OCMC clock is two times lower than the L3 associated OCMC clock
•
Error correction and detection:
–
–
Single error correction and dual error detection
9-bit Hamming error correction code (ECC) calculated on 128-bit data word which is concatenated
with memory address bits
–
–
–
–
–
–
Hamming distance of 4
Enable/Disable mode control through a dedicated register
Single bit error correction on a read transaction
Exclusion of repeated addresses from correctable error address trace history
ECC valid for all write transactions to an enabled region
Sub-128-bit writes supported via read modify write
•
•
ECC Error Status Reporting:
–
–
Trace history buffer (FIFO) with depth of 4 for corrected error address
Trace history buffer with depth of 4 for non correctable error address and also including double
error detection
–
Interrupt generation for correctable and uncorrectable detected errors
ECC Diagnostics Configuration:
–
Counters for single error correction (SEC), double error detection (DED) and address error events
(AEE)
–
–
–
Programmable threshold registers for exeptions associated with SEC, DED and AEE counters
Register control for enabling and disabling of diagnostics
Configuration registers and ECC status accessible through L4 interconnect
194
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Circular buffer for sliced based VIP frame transfers:
–
–
Up to 12 programmable circular buffers mapped with unique virtual frame addresses
On the fly (with no additional latency) address translation from virtual to OCMC circular buffer
memory space
–
–
–
–
Virtual frame size up to 8 MiB and circular buffer size up to 1 MiB
Error handling and reporting of illegal CBUF addressing
Underflow and Overflow status reporting and error handling
Last access read/write address history
•
Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events
The OCM controller does not have a memory protection logic and does not support endianism conversion.
For more information, see section On-Chip Memory (OCM) Subsystem in chapter Memory Subsystem of
the device TRM.
6.7 Interprocessor Communication
6.7.1 Mailbox
Communication between the on-chip processors of the device uses a queued mailbox-interrupt
mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel
between two processors through a set of registers and associated interrupt signals by sending and
receiving messages (mailboxes).
The device implements the following mailbox types:
•
System mailbox:
–
–
–
Number of instances: 2
Used for communication between: DSP1, DSP2, IPU subsystems
Reference name: MAILBOX1, MAILBOX2
Each mailbox module supports the following features:
•
Parameters configurable at design time
–
–
–
Number of users
Number of mailbox message queues
Number of messages (FIFO depth) for each message queue
•
•
•
•
32-bit message width
Message reception and queue-not-full notification using interrupts
Support of 16-/32-bit addressing scheme
Power management support
For more information, see chapter Mailbox of the device TRM.
6.7.2 Spinlock
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
•
•
Digital signal processor (DSP) subsystems – DSP1 and DSP2
Dual Cortex-M4 image processing unit (IPU) subsystems – IPU1 and IPU2
The Spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient
way to perform a lock operation of a device resource using a single read-access, avoiding the need of
a readmodify- write bus transfer that the programmable cores are not capable of.
For more information, see chapter Spinlock of the device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
195
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.8 Interrupt Controller
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The DSP (x2), and IPU, and EVE subsystems are capable of servicing these interrupts via their integrated
interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller
Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor
interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device
TRM.
C66x DSP Subsystem Interrupt Controller (DSPx_INTC, where x = 1, 2)
There are two Digital Signal Processing (DSP) subsystems in the device - DSP1, and DSP2. Each DSP
subsystem integrates an interrupt controller - DSPx_INTC, which interfaces the system events to the C66x
core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized interrupts
presented to the C66x CPU.
For detailed information about this module, see chapter DSP Subsystems of the Device TRM.
Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPU_Cx_INTC, where x = 1, 2)
There is one Image Processing Unit (IPU) subsystem in the device. The IPU subsystem integrates two
Arm® Cortex-M4 cores.
A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping
is the same for the two cores to facilitate parallel processing. The NVIC supports:
•
96 external interrupts (in addition to 16 Cortex-M4 internal interrupts), which are dynamically prioritized
with 16 levels of priority defined for each core
•
•
•
•
Low-latency exception and interrupt handling
Prioritization and handling of exceptions
Control of the local power management
Debug accesses to the processor core
For detailed information about this module, refer to Arm Cortex-M4 Technical Reference Manual (available
at infocenter.arm.com/help/index.jsp).
EVE Subsystem Interrupt Controller (EVE_INTC)
There is one Embedded Video Engine (EVE) subsystems in the device. The EVE subsystem integrates an
interrupt controller - EVE_INTC, which handles incoming interrupts, merging them with internal interrupt
sources to drive ARP32's interrupt inputs. It also allows ARP32 to generate outgoing interrupts or events
to synchronize with other system processors and EDMA.
The EVE_INTC supports up to 32 active-high level interrupt inputs. Its architecture allows both hardware
and software prioritization.
For detailed information about this module, see chapter Embedded Vision Engine of the Device TRM.
6.9 EDMA
The enhanced direct memory access module, also called EDMA, performs high-performance data
transfers between two slave points, memories and peripheral devices without microprocessor unit (MPU)
or digital signal processor (DSP) support during transfer. EDMA transfer is programmed through a logical
EDMA channel, which allows the transfer to be optimally tailored to the requirements of the application.
The EDMA can also perform transfers between external memories and between device subsystems
internal memories, with some performance loss caused by resource sharing between the read and write
ports.
EDMA controller is based on two major principal blocks:
•
•
EDMA third-party channel controller (EDMA_TPCC)
EDMA third-party transfer controller (EDMA_TPTC)
196
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
The EDMA_TPCC channel controller has following features:
Fully orthogonal transfer description:
•
•
–
–
–
–
–
Three transfer dimensions.
A-synchronized transfers: one-dimension serviced per event.
AB-synchronized transfers: two-dimensions serviced per event.
Independent indexes on source and destination.
Chaining feature allows a 3-D transfer based on a single event.
Flexible transfer definition:
–
–
–
Increment or FIFO transfer addressing modes.
Linking mechanism allows automatic PaRAM set update.
Chaining allows multiple transfers to execute with one event.
•
•
•
•
•
Interrupt generation for the following:
–
–
Transfer completion.
Error conditions.
Debug visibility:
–
–
Queue water marking/threshold.
Error and status recording to facilitate debug.
64 DMA request channels:
–
–
Event synchronization.
Chain synchronization (completion of one transfer triggers another transfer).
Eight QDMA channels:
–
–
QDMA channels trigger automatically upon writing to a parameter RAM (PaRAM) set entry.
Support for programmable QDMA channel to PaRAM mapping.
512 PaRAM sets:
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set.
–
•
•
•
Two transfer controllers/event queues.
16 event entries per event queue.
Memory protection support:
–
–
Proxy memory protection for TR submission.
Active memory protection for accesses to PaRAM and registers.
The EDMA_TPTC transfer controller has the following features:
•
•
•
•
•
Two transfer controllers (TC).
128-bit wide read and write ports per TC.
Up to four in-flight transfer requests (TRs).
Programmable priority level.
Supports two-dimensional transfers with independent indexes on source and destination
(EDMA_TPCC manages the 3rd dimension).
•
•
•
Support for increment or constant addressing mode transfers.
Interrupt and error support.
Memory-Mapped Register (MMR) bit fields are fixed position in 32-bit MMR regardless of
endianness.
EDMA controller uses the shared MMU1 module for transfering to and from DSP module. This
provides several benefits including:
•
•
Protection of Host CPU memory regions from accidental corruption by EDMA TPTCs.
Direct allocation of buffers in user space without the need for translation between CPU and DSP
applications using EDMA TPTCs.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
197
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Accesses by the EDMA TPTCs (both TPTC0 and TPTC1) may optionally be routed through the
MMU1.
The TPTC0 and TPTC1 routing allows EDMA transfer controller to be used to perform transfers using
only the virtual addresses of the associated buffers.
For more information chapter Enhanced DMA of the device TRM.
6.10 Peripherals
6.10.1 VIP
The VIP module provides video capture functions for the device. VIP incorporates a multichannel raw
video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)
engine to store incoming video in various formats. The device uses a single instantiation of the VIP
module giving the ability of capturing up to two video streams.
A VIP module includes the following main features:
•
Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which
has two video input ports, Port A and Port B, where Port A can be configured as a 16/8-bit port, and
Port B is a fixed 8-bit port.
•
Each video Port A can be operated as a port with clock independent input channels (with interleaved or
separated Y/C data input). Embedded sync and external sync modes are supported for all input
configurations.
•
•
Support for a single external asynchronous pixel clock, up to 165MHz per port.
Pixel Clock Input Domain Port A supports up to one 16-bit input data bus, including BT.1120 style
embedded sync for 16-bit data.
•
•
•
Embedded Sync data interface mode supports single or multiplexed sources
Discrete Sync data interface mode supports only single source input
16-bit data input plus discrete syncs can be configured to include:
–
–
–
–
8-bit YUV422 (Y and U/V time interleaved)
16-bit YUV422 (CbY and CrY time interleaved)
16-bit RGB565
16-bit RAW Capture
•
•
•
Discrete sync modes include:
–
–
–
–
VSYNC + HSYNC (FID determined by FID signal pin or HSYNC/VSYNC skew)
VSYNC + ACTVID + FID
VBLANK + ACTVID (ACTVID toggles in VBLANK) + FID
VBLANK + ACTVID (no ACTVID toggles in VBLANK) + FID
Multichannel parser (embedded syncs only)
–
–
–
–
Embedded syncs only
Pixel (2x or 4x) or Line multiplexed modes supported
Performs demultiplexing and basic error checking
Supports maximum of 9 channels in Line Mux (8 normal + 1 split line)
Ancillary data capture support
–
–
For 16-bit input, ancillary data may be extracted from any single channel
For 8-bit time interleaved input, ancillary data can be chosen from the Luma channel, the Chroma
channel, or both channels
–
–
Horizontal blanking interval data capture only supported when using discrete syncs (VSYNC +
HSYNC or VSYNC + HBLANK)
Ancillary data extraction supported on multichannel capture as well as single source streams
198
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Format conversion and scaling
–
–
–
–
–
Programmable color space conversion
YUV422 to YUV444 conversion
YUV444 to YUV422 conversion
YUV422 to YUV420 conversion
YUV422 Source: YUV422 to YUV422, YUV422 to YUV420, YUV422 to YUV444, YUV422 to
RGB888
–
–
Supports RAW to RAW (no processing)
Scaling and format conversions do not work for multiplexed input
•
•
Supports up to 2047 pixels wide input - when scaling is engaged
Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without
scaling
•
•
Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling
The maximum supported input resolution is further limited by pixel clock and feature-dependent
constraints
For more information, see chapter Video Input Port of the device TRM.
6.10.2 DSS
The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS integrates a DMA
engine as part of DISPC module, which allows direct access to the memory frame buffer. Various pixel
processing capabilities are supported, such as: color space conversion, filtering, scaling, blending, color
keying, etc.
The supported display interfaces are:
•
•
One parallel CMOS output, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120.
One TV output, which is connected to the internal Video Encoder module (VENC). The VENC drives a
single video digital-to-analog converter (SD_DAC) supporting composite video mode.
The modules integrated in the display subsystem are:
• Display controller (DISPC), with the following main features
–
–
One direct memory access (DMA) engine
One graphics pipeline (GFX), two video pipelines (VID1 and VID2), and one write-back pipeline
(WB)
–
–
–
Two overlay managers
Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values)
One Video Port (VP) with programmable timing generator to support:
•
•
DPI: up to 165 MHz pixel clock video formats defined in CEA-861-E and VESA DMT standards
VENC: NTSC/PAL standards with 60Hz/50Hz refresh rates
–
–
–
Supported maximum FrameBuffer width of 4096 for all pixel formats
Configurable output mode: progressive or interlaced
Selection between RGB and YUV422 output pixel formats (YUV4:2:2 only available when BT-656
or BT-1120 output mode is enabled)
For more information, see section Display Controller in chapter Display Subsystem of the device TRM.
Video Encoder (VENC) with 10-bit standard definition video DAC (SD_DAC).
•
For more information, see section Video Encoder in chapter Display Subsystem of the device TRM.
DSS provides two interfaces to L3_MAIN interconnect
•
One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master to
read/write data from/to device system memory.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
199
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
One 32-bit slave port. Used for registers configuration. It is further connected internally to DISPC and
VENC modules.
For more information, see chapter Display Subsystem of the device TRM.
6.10.3 ATL
The audio tracking logic (ATL) is used by HD Radio™ applications to synchronize the digital audio output
to the baseband clock. This same IP can also be used generically to track errors between two reference
signals (such as frame syncs) and generate a modulated clock output (using software-controlled cycle
stealing) which averages to some desired frequency. This process can be used as a hardware assist for
asynchronous sample rate conversion algorithms. The tracking range is limited, so direct conversion
between the two standard sample rate groups frequencies from 44.1 to 48 kHz is not possible.
The ATL includes the following main features:
•
One ATL module, containing four ATL instances, for HD Radio support and asynchronous sample rate
conversion assistance
•
Each instance tracks the time error between two syncs (local audio word select [AWS] and baseband
word select [BWS])
•
•
•
Each instance selects between 16 mux choices for each of AWS and BWS.
Each instance generates modulated ATCLK_OUT clock signal with software-initiated pulse stealing.
Selection between INTERCONNECT clock or functional ATLPCLK to run error couting timers and to
derive modulated ATCLK_OUT clock outputs
•
Clock and reset management: Receives clock and reset signals from the device power, reset, and
clock management (PRCM) module. The PRCM module has its own dedicated clock domain
(CD_ATL). The module receives hardware reset from the CORE_RST reset domain.
•
Power management: The ATL belongs to the PD_COREAON power domain.
For more information, see chapter Audio Tracking Logic of the device TRM.
6.10.4 ADC
The analog-to-digital converter (ADC) module is a successive-approximation-register (SAR) general-
purpose analog-to-digital converter.
The main features of the ADC include:
•
•
•
•
•
10-bit data.
8 general-purpose ADC channels.
750 KSPS at 13.5-MHz ADC_CLK.
Programmable FSM sequencer.
Support interrupts and status, with masking.
For more information, see chapter ADC of the device TRM.
6.10.5 Timers
The device includes several types of timers used by the system software, including eight general-purpose
(GP) timers, and a 32-kHz synchronized timer (COUNTER_32K).
6.10.5.1 General-Purpose Timers
The device has eight GP timers: TIMER1 through TIMER8.
•
TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating
system and it belongs to the PD_WKUPAON domain.
•
TIMER2 through TIMER8 belong to the PD_COREAON module.
200
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the
clock source at the power, reset, and clock management (PRCM) module level.
Each timer provides an interrupt through the device IRQ_CROSSBAR.
The following are the main features of the GP timer controllers:
•
Level 4 (L4) slave interface support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
10-bit address bus width
Burst mode not supported
Write nonposted transaction mode supported
•
•
•
•
•
•
•
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Compare and capture modes
Autoreload mode
Start and stop mode
Programmable divider clock source (2n, where n = [0:8])
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
Dedicated GP output signal for using the TIMERi_GPO_CFG signal
On-the-fly read/write register (while counting)
1-ms tick with 32.768-Hz functional clock generated (only TIMER1)
For more information, see section General-Purpose Timers in chapter Timers of the device TRM.
6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-
kHz system clock.
The main features of the 32-kHz synchronized timer controller are:
•
L4 slave interface (OCP) support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
16-bit address bus width
Burst mode not supported
Write nonposted transaction mode not supported
•
Only read operations are supported on the module registers; no write operation is supported (no
error/no action on write).
•
•
•
•
Free-running 32-bit upward counter
Start and keep counting after power-on reset
Automatic roll over to 0; highest value reached: 0xFFFF FFFF
On-the-fly read (while counting)
For more information, see section 32-kHz Synchronized Timer (COUNTER_32K) in chapter Timers of the
device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
201
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.10.6 I2C
The device contains five multimaster inter-integrated circuit (I2C) controllers (I2Ci modules, where i = 1, 2)
each of which provides an interface between a local host (LH), such as a digital signal processor (DSP),
and any I2C-bus-compatible device that connects through the I2C serial bus. External components
attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device
through the 2-wire I2C interface.
Each multimaster I2C controller can be configured to act like a slave or master I2C-compatible device.
For more information, see section Multimaster I2C Controller in chapter Serial Communication Interfaces
of the device TRM.
6.10.7 UART
The UART is a simple L4 slave peripheral that use the EDMA for data transfer or IRQ polling via CPU.
There are 3 UART modules in the device. Each UART can be used for configuration and data exchange
with a number of external peripheral devices or interprocessor communication between devices.
6.10.7.1 UART Features
The UARTi (where i = 1 to 3) include the following features:
•
•
•
•
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Programmable interrupt trigger levels for FIFOs
Baud generation based on programmable divisors N (where N = 1…16,384) operating from a fixed
functional clock of 48 MHz or 192 MHz
Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two
options:
•
•
•
Baud rate = (functional clock / 16) / N
Baud rate = (functional clock / 13) / N
This software programming mode enables higher baud rates with the same error amount without
changing the clock source
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
The 48 MHz functional clock option allows baud rates up to 3.6Mbps
The 192 MHz functional clock option allows baud rates up to 12Mbps
For more information, see section UART in chapter Serial Communication Interfaces of the device TRM.
6.10.8 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules are able to work as both master and slave
and support the following chip selects:
•
•
•
•
MCSPI1: spi1_cs[0], spi1_cs[1], spi1_cs[2], spi1_cs[3]
MCSPI2: spi2_cs[0], spi2_cs[1]
MCSPI3: spi3_cs[0], spi3_cs[1]
MCSPI4: spi4_cs[0]
The McSPI modules include the following main features:
202
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
SPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
•
•
•
Single interrupt line for multiple interrupt source events
Power management through wake-up capabilities
Enable the addition of a programmable start-bit for SPI transfer per channel (start-bit mode)
Supports start-bit write command
Supports start-bit pause and break sequence
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel
For more information, see section Multichannel Serial Peripheral Interface in chapter Serial
Communication Interfaces of the device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
203
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.10.9 QSPI
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only.
The QSPI supports the following features:
•
General SPI features:
–
–
–
–
–
–
–
–
–
–
–
–
Programmable clock divider
Six pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
4 external chip-select signals
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Programmable signal polarities
Programmable active clock edge
Software-controllable interface allowing for any type of SPI transfer
Control through L3_MAIN configuration port
•
Serial flash interface (SFI) features:
–
–
–
–
Serial flash read/write interface
Additional registers for defining read and write commands to the external serial flash device
1 to 4 address bytes
Fast read support, where fast read requires dummy bytes after address bytes; 0 to 3 dummy bytes
can be configured.
–
–
–
–
Dual read support
Quad read support
Little-endian support only
Linear increment addressing mode only
The QSPI supports only dual and quad reads. Dual or quad writes are not supported. In addition, there is
no "pass through" mode supported where the data present on the QSPI input is sent to its output.
For more information, see section Quad Serial Peripheral Interface in chapter Serial Communication
Interfaces of the device TRM.
6.10.10 McASP
The McASP functions as a general-purpose audio serial port optimized to the requirements of various
audio applications. The McASP module can operate in both transmit and receive modes. The McASP is
useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and
transmission as well as for an intercomponent digital audio interface transmission (DIT). The McASP has
the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer
component.
Although intercomponent digital audio interface reception (DIR) mode (i.e. S/PDIF stream receiving) is not
natively supported by the McASP module, a specific TDM mode implementation for the McASP receivers
allows an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
The device has integrated 3 McASP modules with:
•
•
McASP1 supports 16 channels with independent TX/RX clock/sync domain
McASP2 and McASP3 support 6 channels with independent TX/RX clock/sync domain
204
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
For more information, see section Multichannel Audio Serial Port in chapter Serial Communication
Interfaces of the device TRM.
6.10.11 DCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time applications. CAN has high immunity to electrical interference and the ability to self-
diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The device supports:
•
One DCAN module, referred to as DCAN1
The DCAN interface implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects in a dedicated message RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM single error correction and double error detection (SECDED) mechanism
Direct access to message RAM during test mode
Support for two interrupt lines: Level 0 and Level 1, plus separate ECC interrupt line
Local power down and wakeup support
Automatic message RAM initialization
Support for DMA access
For more information, see section DCAN in chapter Serial Communication Interfaces of the device TRM.
6.10.12 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time control with a high level of security. CAN has high immunity to electrical interference
and the ability to self-diagnose and repair data errors. In a CAN network, many short messages are
broadcast to the entire network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.
CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN
FD devices can coexist on the same network without any conflict.
The MCAN module implements the following features:
•
•
•
•
•
•
•
•
•
•
Conforms with ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)
AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 filter elements
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
205
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
•
•
Internal Loopback mode for self-test
Maskable interrupts, two interrupt lines
Two clock domains (CAN clock/Host clock)
Parity/ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
•
•
Local power-down and wakeup support
Timestamp Counter
For more information, see section MCAN in chapter Serial Communication Interfaces of the device TRM.
6.10.13 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the reduced gigabit media independent interface
(RGMII), and the management data input output (MDIO) for physical layer device (PHY) management.
The GMAC_SW subsystem provides the following features:
•
Two Ethernet ports (port 1 and port 2) with RGMII interfaces plus internal Communications Port
Programming Interface (CPPI 3.1) on port 0
•
•
•
•
•
•
•
•
Synchronous 10/100/1000 Mbit operation
Wire rate switching (802.1d)
Non-blocking switch fabric
Flexible logical FIFO-based packet buffer structure
Four priority level Quality Of Service (QOS) support (802.1p)
CPPI 3.1 compliant DMA controllers
Support for Audio/Video Bridging (P802.1Qav/D6.0)
Support for IEEE 1588 Clock Synchronization (2008 Annex D and Annex F)
–
Timing FIFO and time stamping logic embedded in the subsystem
•
•
•
•
Device Level Ring (DLR) Support
Energy Efficient Ethernet (EEE) support (802.3az)
Flow Control Support (802.3x)
Address Lookup Engine (ALE)
–
–
–
–
–
–
–
–
–
–
–
1024 total address entries plus VLANs
Wire rate lookup
Host controlled time-based aging
Multiple spanning tree support (spanning tree per VLAN)
L2 address lock and L2 filtering support
MAC authentication (802.1x)
Receive-based or destination-based multicast and broadcast rate limits
MAC address blocking
Source port locking
OUI (Vendor ID) host accept/deny feature
Remapping of priority level of VLAN or ports
•
•
VLAN support
802.1Q compliant
–
•
•
Auto add port VLAN for untagged frames on ingress
Auto VLAN removal on egress and auto pad to minimum frame size
Ethernet Statistics:
–
–
EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (shared)
Programmable statistics interrupt mask when a statistic is above one half its 32-bit value
206
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
•
•
•
•
•
•
•
Flow Control Support (802.3x)
Digital loopback and FIFO loopback modes supported
Maximum frame size 2016 bytes (2020 with VLAN)
8k (2048 × 32) internal CPPI buffer descriptor memory
Management Data Input/Output (MDIO) module for PHY Management
Programmable interrupt control with selected interrupt pacing
Emulation support
Programmable Transmit Inter Packet Gap (IPG)
Reset isolation (switch function remains active even in case of all device resets except for POR pin
reset and ICEPICK cold reset)
•
•
Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps.
IEEE 802.3 gigabit Ethernet conformant
For more information, see section Gigabit Ethernet Switch (GMAC_SW) in chapter Serial Communication
Interfaces of the device TRM.
6.10.14 SDIO
The SDIO host controller provides an interface between a local host (LH) such as a microprocessor unit or
digital signal processor and SDIO cards. It handles SDIO transactions with minimal LH intervention.
The SDIO host controller deals with SDIO protocol at transmission level, data packing, adding cyclic
redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.
The application interface can send every SDIO command and poll for the status of the adapter or wait for
an interrupt request, which is sent back in case of exceptions or to warn of end of operation.
The application interface can read card responses or flag registers. It can also mask individual interrupt
sources. All these operations can be performed by reading and writing control registers. The SDIO host
controller also supports two slave DMA channels.
Compliance with standards:
•
SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the
SD part E1 specification v3.00
•
•
SD command/response sets as defined in the SD Physical Layer specification v3.01
SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v3.00
Main features of the SD/SDIO host controllers:
•
•
•
•
•
Flexible architecture allowing support for new command structure
32-bit wide access bus to maximize bus throughput
Designed for low power
Programmable clock generation
L4 slave interface supports:
–
–
–
–
–
32-bit data bus width
8/16/32 bit access supported
9-bit address bus width
Streaming burst supported only with burst length up to 7
WNP supported
•
•
•
•
Built-in 1024-byte buffer for read or write
Two DMA channels, one interrupt line
Supported data transfer rates up to SDR25 mode
The SDIO controller is connected to 1,8V/3.3V compatible I/Os to support 1,8V/3.3V signaling
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
207
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
The differences between the SDIO host controller and a standard SD host controller defined by the SD
Card Specification, Part A2, SD Host Controller Standard Specification, v3.00 are:
•
The clock divider in the SDIO host controller supports a wider range of frequency than specified in the
SD Memory Card Specifications, v3.0. The SDIO host controller supports odd and even clock ratioes.
•
•
The SDIO host controller supports configurable busy time-out.
There is no external LED control
For more information, see chapter SDIO Controller of the device TRM.
208
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
6.10.15 GPIO
The general-purpose interface combines four general-purpose input/output (GPIO) banks.
Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus,
the general-purpose interface supports up to 126 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations.
•
Wake-up request generation in idle mode upon the detection of external events
For more information, see chapter General-Purpose Interface of the device TRM.
6.10.16 ePWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
Each ePWM module supports the following features:
•
•
Dedicated 16-bit time-base counter with period and frequency control
Two PWM outputs (EPWM1A and EPWM2B) that can be used in the following configurations:
–
–
–
Two independent PWM outputs with single-edge operation
Two independent PWM outputs with dual-edge symmetric operation
One independent PWM output with dual-edge asymmetric operation
•
•
•
•
•
•
•
Asynchronous override control of PWM signals through software.
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
Dead-band generation with independent rising and falling edge delay control.
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
Programmable event prescaling minimizes CPU overhead on interrupts.
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
For more information, see section Enhanced PWM (ePWM) Module in chapter Pulse-Width Modulation
Subsystem of the device TRM.
6.10.17 eCAP
Uses for eCAP include:
•
•
•
•
•
Sample rate measurements of audio inputs
Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
209
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
•
•
•
•
•
•
•
•
32-bit time base counter
4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event time-stamps
Continuous mode capture of time-stamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All above resources dedicated to a single input pin
When not used in capture mode, the ECAP module can be configured as a single channel PWM output
For more information, see section Enhanced Capture (eCAP) Module in chapter Pulse-Width Modulation
Subsystem of the device TRM.
6.10.18 eQEP
A single track of slots patterns the periphery of an incremental encoder disk. These slots create an
alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs
that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that
occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position.
Encoder manufacturers identify the index pulse using different terms such as index, marker, home
position, and zero reference.
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of
phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The
clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB
channel.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Pulse-
Width Modulation Subsystem of the device TRM.
6.11 On-Chip Debug
Debugging a system that contains an embedded processor involves an environment that connects high-
level debugging software running on a host computer to a low-level debug interface supported by the
target device. Between these levels, a debug and trace controller (DTC) facilitates communication
between the host debugger and the debug support logic on the target chip.
The DTC is a combination of hardware and software that connects the host debugger to the target system.
The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the
debugger user to JTAG® commands and scans that execute the core hardware.
The debug software and hardware components let the user control multiple central processing unit (CPU)
cores embedded in the device in a global or local manner. This environment provides:
•
•
Synchronized global starting and stopping of multiple processors
Starting and stopping of an individual processor
210
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Each processor can generate triggers that can be used to alter the execution flow of other processors
System topics include but are not limited to:
•
•
•
System clocking and power-down issues
Interconnection of multiple devices
Trigger channels
The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It
provides the following features:
•
External debug interfaces:
– Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)
•
•
Used for debugger connection
Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7
adapter module
•
Controls ICEPick™ (generic test access port [TAP] for dynamic TAP insertion) to allow the
debugger to access several debug resources through its secondary (output) JTAG ports (for
more information, see section ICEPick Secondary TAPs in chapter On-Chip Debug Support of
the Device TRM).
–
Debug (trace) port
•
•
•
Can be used to export processor or system trace off-chip (to an external trace receiver)
Can be used for cross-triggering with an external device
Configured through debug resources manager (DRM) module instantiated in the debug
subsystem
•
For more information about debug (trace) port, see sections Debug (Trace) Port and Concurrent
Debug Modes in chapter On-Chip Debug Support of the Device TRM.
•
•
JTAG based processor debug on:
–
–
C66x in DSP1, DSP2
Cortex-M4 (x2) in IPU
Dynamic TAP insertion
–
–
Controlled by ICEPick
For more information, see section Dynamic TAP Insertion in chapter On-Chip Debug Support of the
Device TRM
•
•
Power and clock management
–
–
–
–
Debugger can get the status of the power domain associated to each TAP.
Debugger may prevent the application software switching off the power domain.
Application power management behavior can be preserved during debug across power transitions.
For more information, see section Power and Clock Management in chapter On-Chip Debug
Support of the Device TRM.
Reset management
–
–
Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
For more information, see section Reset Management in chapter On-Chip Debug Support of the
Device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
211
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Cross-triggering
–
Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to
another:
•
Subsystem A can be programmed to generate a debug event, which can then be exported as a
global trigger across the device.
•
Subsystem B can be programmed to be sensitive to the trigger line input and to generate an
action on trigger detection.
–
–
Two global trigger lines are implemented
Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the
debug subsystem
–
For more information about cross-triggering, see section Cross-Triggering in chapter On-Chip
Debug Support of the Device TRM.
•
•
Suspend
–
Provides a way to stop a closely coupled hardware process running on a peripheral module when
the host processor enters debug state
–
For more information about suspend, see section Suspend in chapter On-Chip Debug Support of
the Device TRM.
Processor trace
–
–
C66x (DSP) processor trace is supported
Two exclusive trace sinks:
•
CoreSight Trace Port Interface Unit (CS_TPIU) – trace export to an external trace receiver
–
For more information, see section Processor Trace in chapter On-Chip Debug Support of the
Device TRM.
212
Detailed Description
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
System instrumentation (trace)
–
Supported by a CTools System Trace Module (CT_STM), implementing MIPI System Trace
Protocol (STP) (rev 2.0)
–
Real-time software trace
•
System-on-chip (SoC) software instrumentation through CT_STM (STP2.0)
–
–
OCP watchpoint (OCP_WP_NOC)
•
OCP target traffic monitoring: OCP_WP_NOC can be configured to generate a trigger upon
watchpoint match (that is, when target transaction attributes match the user-defined attributes).
•
•
SoC events trace
DMA transfer profiling
Statistics collector (performance probes)
•
Computes traffic statistics within a user-defined window and periodically reports to the user
through the CT_STM interface
•
•
Embedded in the L3_MAIN interconnect
10 instances:
–
–
1 instance dedicated to target (SDRAM) load monitoring
9 instances dedicated to master latency monitoring
–
–
Power-management events profiling (PM instrumentation [PMI])
•
Monitoring major power-management events. The PM state changes are handled as generic
events and encapsulated in STP messages.
Clock-management events profiling CM instrumentation [CMI]) for CM_CORE_AON clocks
•
Monitoring major clock management events. The CM state changes are handled as generic
events and encapsulated in STP messages.
•
One instances
–
CM1 Instrumentation (CMI1) module mapped in the PD_CORE_AON power domain
–
For more information, see section System Instrumentation in chapter On-Chip Debug Support of
the Device TRM.
•
Performance monitoring
Supported by subsystem counter timer module (SCTM) for IPU
–
For more information, see chapter On-Chip Debug Support of the device TRM.
版权 © 2016–2019, Texas Instruments Incorporated
Detailed Description
213
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test design implementation to confirm system functionality.
7.1 Introduction
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB
that can support TI’s latest Application Processor. This Processor is a high-performance processor
designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm
CMOS process technology.
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to
achieve the desirable high performance processing available on Device. The general principles and step-
by-step approach for implementing good power integrity (PI) with specific requirements will be described
for the key Device power domains.
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.
Ultimately for any high-volume product, TI recommends conducting a "Processor PDN Validation" test on
prototype PCBs across processor "split lots" to verify PDN robustness meets desired performance goals
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on
PDN PI modeling and validation testing.
Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces ,
single-ended interfaces (i.e. DDR3, QSPI) and general purpose interfaces using LVCMOS drivers that
meet timing requirements while minimizing signal integrity (SI) distortions on the PCB’s signaling traces.
Signal trace lengths and flight times are aligned with FR-4 standard specification for PCBs.
Several different PCB layout stack-up examples have been presented to illustrate a typical number of
layers, signal assignments and controlled impedance requirements. Different Device interface signals
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final
layer count and layer assignments in each customer’s PCB design.
This guideline must be used as a supplement in complement to TI’s Application Processor, Power
Management IC (PMIC) and Audio Companion components along with other TI component technical
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out
Spreadsheet, Application Notes, etc.).
注
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or
statutory, including any implied warranty of merchantability of fitness for a specific purpose,
for customer boards. The data described in this appendix are intended as guidelines only.
注
These PCB guidelines are in a draft maturity and consequently, are subject to change
depending on design verification testing conducted during IC development and validation.
Note also that any references to Application Processor’s ballout or pin muxing are subject to
change following the processor’s ballout maturity.
214
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.1.1 Initial Requirements and Guidelines
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.
The trace width and spacing must be chosen to yield the recommended differential impedance. For more
information see 节 7.5.1.
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power
nets from PMIC to the device.
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system
ESD.
7.2 Power Optimizations
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):
•
•
•
•
节 7.2.1, Step 1: PCB Stack-up
节 7.2.2, Step 2: Physical Placement
节 7.2.3, Step 3: Static Analysis
节 7.2.4, Step 4: Frequency Analysis
7.2.1 Step 1: PCB Stack-up
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these recommendations:
•
•
•
Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground
planes must be solid to provide continuous return path for return current.
Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)
maximizes the capacitance.
Optimize the power and ground plane pair carrying high current supplies to key component power
domains as close as possible to the same surface where these components are placed (see 图 7-1).
This will help to minimize "loop inductance" encountered between supply decoupling capacitors and
component supply inputs and between power and ground plane pairs.
注
1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,
helping to reduce Processor junction temperatures. In addition, it is preferable to have the
power / ground planes be adjacent to the PCB surface on which the Processor is mounted.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
215
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Capacitor
Trace
DIE
Package
Via
3
1
Power/Ground
Ground/Power
2
Loop inductance
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
SPRS91v_PCB_STACKUP_01
图 7-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
significant impact on the parasitic inductances of power current path as shown in 图 7-1. For this reason, it
is recommended to consider layer order in the early stages of the PCB PDN design cycle, putting high-
priority supplies in the top half of the stackup (assuming high load and priority components are mounted
on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown in the
examples below (vias have parasitic inductances which impact the bottom layers more, so it is advised to
put the sensitive and high-priority power supplies on the top/same layers).
7.2.2 Step 2: Physical Placement
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The
following points are important for optimizing a PCB’s PDN:
•
Minimizing the physical distance between power sources and key high load components is the first
step toward optimization. Placing source and load components on the same side of the PCB is
desirable. This will minimize via inductance impact for high current loads and steps
•
•
External trace routing between components must be as wide as possible. The wider the traces, the
lower the DC resistance and consequently the lower the static IR drop.
Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance
and improved high frequency performance of the PDN.
•
Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling
capacitors, power inductors and current sensing resistors). Do not share vias among multiple
capacitors for connecting power supply and ground planes.
•
•
Placement of vias must be as close as possible or even within a component’s solder pad if the PCB
technology you are using provides this capability.
To avoid any "ampacity” issue – maximum current-carrying capacity of each transitional via should be
evaluated to determine the appropriate number of vias required to connect components.
Adding vias to bring the "via-to-pad” ratio to 1:1 will improve PDN performance.
•
For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd
shield can be used to isolate coplanar supplies that may have high step currents or high frequency
switching transitions from coupling into low-noise supplies.
216
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
vdd_mpu
vss
vdd
SPRS91v_PCB_PHYS_05
图 7-2. Coplanar Shielding of Power Net Using Ground Guard-band
7.2.3 Step 3: Static Analysis
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the
board. Robust system performance can only be ensured by understanding how the system elements will
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC
Analysis.
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops
across power and ground planes, traces and vias. This ensures the application processor’s internal
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.
Components that are distant from their power source are particularly susceptible to IR drop. Designs that
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,
and copper area needed for load currents.
The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
r
1
L
Rs =
=
t
σ ×t
l
t
R = Rs ×
W
w
SPRS91v_PCB_STATIC_01
图 7-3. Depiction of Sheet Resistivity and Resistance
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate
power at high currents even though their resistance may be very small. Both voltage drop and power
dissipation are proportional to the resistance of the conductor.
图 7-4 shows a PCB-level static IR drop budget defined between the power management device (PMIC)
pins and the application processor’s balls when the PMIC is supplying power.
•
It is highly recommended to physically place the PMIC as close as possible to the processor and on
the same side. The orientation of the PMIC vs. the processor should be aligned to minimize distance
for the highest current rail.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
217
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
PCB
Static IR drop and Effective Resistance
Source Component
Load Component
BGA pad on PCB
SPRS906_PCB_STATIC_02
图 7-4. Static IR Drop Budget for PCB Only
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR
or dc analysis/design methodology consists of designing the PDN such that the voltage drop (under dc
operating conditions) across power and ground pads of the transistors of the application processor device
is within a specified value of the nominal voltage for proper functionality of the device.
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal
voltage. For a 1.35-V supply, this would be ≤20 mV.
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration
violations of current-carrying vias, and "Swiss-cheese” effects via placement has on power rails. It is
recommended to perform the following analyses:
•
•
Lumped resistance/IR drop analysis
Distributed resistance/IR drop analysis
注
The PMIC companion device supporting Processor has been designed with voltage sensing
feedback loop capabilities that enable a remote sense of the SMPS output voltage at the
point of use.
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As
such, the effective resistance of the PDN within this loop should be determined in order to optimize
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the
entire PDN route from SMPS output pin/ball to the Processor input power.
In the following sections each methodology is described in detail and an example has been provided of
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their
PCB PDN design.
218
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.2.3.1 PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement 图 7-5 illustrates the pin-grouping/lumped concept.
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Sources
Sources
Multiport net
Branch
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Port/Pin
Sinks
Sinks
SPRS91v_PCB_PDN_01
图 7-5. Pin-grouping concept: Lumped and Distributed Methodologies
7.2.4 Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
注
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
219
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and
resistance.
图 7-6 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC circuit
with effective series resistance (ESR) and effective series inductance (ESL).
C
ESL
ESR
SPRS91v_PCB_FREQ_01
图 7-6. Characteristics of a Real Capacitor With ESL and ESR
The magnitude of the impedance of this series model is given as:
1
æ
ö2
2
Z = ESR +
ωESL -
ç
÷
ωC
è
ø
where : w = 2π¦
SPRS91v_PCB_FREQ_02
图 7-7. Series Model Impedance Equation
图 7-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of 55
MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance
and inductance as shown in the equation above.
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+01
1.0e+00
1.0e–01
1.0e–02
XC=1/ωC
XL=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
1.00e+006
1.00e+008
Frequency (MHz)
SPRS91v_PCB_FREQ_03
图 7-8. Typical Impedance Profile of a Capacitor
220
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in 图 7-1. The capacitor mounting inductance and resistance values
include the inductance and resistance of the pads, trace, and vias. Whenever possible, use footprints that
have the lowest inductance configuration as shown in 图 7-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in 图 7-9. If the PCB manufacturing processes allow it and if cost-
effective, via-in-pad (VIP) geometries are strongly recommended.
In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in 图 7-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in 图 7-9 are
known as:
•
•
•
•
•
2-via, Skinny End Exit (2vSEE)
2-via, Wide End Exit (2vWEE)
2-via, Wide Side Exit (2vWSE)
4-via, Wide Side Exit (4vWSE)
2-via, In-Pad (2vIP)
Via
Via-in-pad
Pad
Trace
Mounting geometry for reduced inductance
SPRS91v_PCB_FREQ_04
图 7-9. Capacitor Placement Geometry for Improved Mounting Inductance
注
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
221
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see 图 7-9).
2. Place Dcaps on "same-side” as component within their power plane outline to minimize "decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
minimum inductance for top vs bottom-side placement.
3. Place Dcaps on "opposite-side” as component within their power plane outline if "same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
5. Place all voltage and gnd plane vias "as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a "Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the CORE power domain (vdd) has yielded the Impedance vs Frequency
responses shown in 节 7.3.8.2, vdd Example Analysis.
7.2.5 System ESD Generic Guidelines
7.2.5.1 System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in 图 7-10) from connector to external protection because the interconnect may see between 15-A to
30-A current in a short period of time during the ESD event.
222
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Stub
inductance
Interconnection
inductance
vcc
Signal
VCC
VCC
Protected
circuit
Signal
Stub
inductance
ESD
strike
Minimize such
inductance by
optimizing layout
External
protection
Ground
inductance
Keep distance
between protected
circuit and external
protection
Keep external
protection closed by
connector
SPRS91v_PCB_ESD_01
图 7-10. Placement Recommendation for an ESD External Protection
注
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground
the ESD protection to the board ground rather than any local ground (example isolated shield
or audio ground).
7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
•
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB
edges.
•
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the
drivers to minimize ESD coupling.
•
•
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled
current on the ring.
•
•
Fill unused portions of the PCB with ground plane.
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and
ground planes.
•
•
Shield long line length (strip lines) to minimize radiated ESD.
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in
one area.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
223
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
BAD
BETTER
SPRS91v_PCB_EMC_01
图 7-11. Trace Examples
Always route signal traces and their associated ground returns as close to one another as possible to
minimize the loop area enclosed by current flow:
•
–
–
At high frequencies current follows the path of least inductance.
At low frequencies current flows through the path of least resistance.
7.2.5.3 ESD Protection System Design Consideration
ESD protection system design consideration is covered in of this document. The following are additional
considerations for ESD protection in a system.
•
•
•
•
•
•
Metallic shielding for both ESD and EMI
Chassis GND isolation from the board GND
Air gap designed on board to absorb ESD energy
Clamping diodes to absorb ESD energy
Capacitors to divert ESD energy
The use of external ESD components on the DP/DM lines may affect signal quality and are not
recommended.
7.2.6 EMI / EMC Issues Prevention
All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed
by the EMC regulations if some preventative steps are not taken.
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked
up by the circuitry interconnections.
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.
7.2.6.1 Signal Bandwidth
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW
with respect to its rise time, tR:
fBW ≈ 0.35 / tR
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start
to decay at 40 dB per decade instead of 20 dB per decade.
224
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.2.6.2 Signal Routing
7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN
transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved
protection it is recommended to place these emission sources in a shield can. If the shield can have a
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.
Leave some space between the lid and the components under it to limit the high-frequency currents
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of
interest; see 图 7-8, Typical Impedance Profile of a Capacitor.
7.2.6.2.2 Signal Routing—Outer Layer Routing
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to
route only static signals and ensure that these static signals do not carry any high-frequency components
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor
near the signal source.
Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,
because their emissions energy is concentrated at the discrete harmonics and can become significant
even with poor radiators.
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is
effective only if the distance between the trace sides and the ground is smaller that the trace height above
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a
ground reference near the trace edges can increase EMI: see 节 7.2.6.3, Ground Guidelines.
7.2.6.3 Ground Guidelines
7.2.6.3.1 PCB Outer Layers
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be
filled with ground after the routing is completed and connected with an adequate number of vias to the
ground on the inner ground planes.
7.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
7.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
7.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in 图 7-12 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
225
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS91v_PCB_EMC_02
图 7-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS91v_PCB_EMC_03
图 7-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in 图 7-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
7.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
7.3 Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
7.3.1 General Constraints and Theory
•
•
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input
including any ground return losses.
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5% of supply voltage when using
TI recommended PMICs with remote sensing at the load as measured from PMIC’s power inductor
and filter capacitor node to Device’s supply input including any ground return losses.
226
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
PMIC component DM and guidelines should be referenced for the following:
–
–
Routing remote feedback sensing to optimize per each SMPS’s implementation
Selecting power filtering capacitor values and PCB placement.
•
•
•
•
Max Total Effective Resistance (Reff) budget can range from 4 – 100mΩ for key Device power rails not
including ground returns depending upon maximum load currents and maximum DC voltage drop
budget (as discussed above).
Max Device supply input voltage difference budget of 5mV under max current loading shall be
maintained across all balls connected to a common power rail. This represents any voltage difference
that may exist between a remote sense point to any power input.
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending
upon maximum transient load currents.
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device
including ground returns are as follows:
–
+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~
200kHz)
–
+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
•
Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output
power filter node including ground return is determined by applying the Frequency Domain Target
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general
regions of interest as can be seen in 图 7-14.
–
1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very
low due to power filtering and bulk capacitor values when PDN has very low trace resistance (i.e.
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over
this low frequency range. This will ensure that a max transient current event will not cause a
voltage drop more than the PMIC’s current step response can support (typ 3%).
–
2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient
current event will not cause a voltage drop to be more than 5% of the min supply voltage.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
227
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
图 7-14. PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events
such as transient noise, AC ripple, voltage dips etc.
2.Typical max transient current is defined as 50% of max current draw possible.
7.3.2 Voltage Decoupling
Recommended power supply decoupling capacitors main characteristics for commercial products whose
ambient temperature is not to exceed +85C are shown in table below:
表 7-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)
Value
Voltage
[V]
Package
Stability
Dielectric Capacitan
Temp
Temp
REFERENCE
ce
Range [°C] Sensitivity
[%]
Tolerance
22µF
10µF
4.7µF
2.2µF
1µF
6,3
4,0
6,3
6,3
6,3
0603
0402
0402
0402
0201
Class 2
Class 2
Class 2
Class 2
Class 2
X5R
X5R
X5R
X5R
X5R
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
GRM188R60J226MEA0L
GRM155R60G106ME44
GRM155R60J475ME95
GRM155R60J225ME95
GRM033R60J105MEA2
228
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3) (continued)
Value
Voltage
[V]
Package
Stability
Dielectric Capacitan
Temp
Temp
REFERENCE
ce
Range [°C] Sensitivity
[%]
Tolerance
470nF
220nF
100nF
6,3
6,3
6,3
0201
0201
0201
Class 2
Class 2
Class 2
X5R
X5R
X5R
- / + 20%
- / + 20%
- / + 20%
-55 to + 85
-55 to + 85
-55 to + 85
- / + 15
- / + 15
- / + 15
GRM033R60G474ME90
GRM033R60J224ME90
GRM033R60J104ME19
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation
factor.
Recommended power supply decoupling capacitors main characteristics for automotive products are
shown in table below:
表 7-2. Automotive Applications Recommended Decoupling Capacitors Characteristics (1)(2)
Value
Voltage [V]
Package
Stability
Dielectric Capacitanc
Temp
Temp
REFERENCE
e
Range [°C] Sensitivity
[%]
Tolerance
22µF
10µF
6,3
6,3
10
6,3
16
16
25
16
1206
0805
0805
0603
0603
0603
0603
0402
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
X7R
X7R
X7R
X7R
X7R
X7R
X7R
X7R
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 15
GCM31CR70J226ME23
GCM21BR70J106ME22
GCM21BC71A475MA73
GCM188R70J225ME22
GCM188R71C105MA64
GCM188R71C474MA55
GCM188L81C224MA37
GCM155R71C104MA55
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
4.7µF
2.2µF
1µF
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
470nF
220nF
100nF
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
7.3.3 Static PDN Analysis
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).
This is the total PCB power net routing resistance that is the sum of all the individual power net segments
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.
7.3.4 Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),
Impedance (Z) and PCB Frequency of Interest (Fpcb).
•
•
•
LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
"theoretical shorted” applied across the Processor’s supply inputs to ground reference.
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
229
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5)
PDN Analysis:
Supply
Static
Dynamic
Number of Recommended Decoupling Capacitors per
Supply
Frequency
range
of Interest
[MHz]
Max Reff
Dec. Cap.
Max
100
220
nF
470
nF
(7)
Max LL(8) (6) Impedance
1μF 2.2 μF 4.7 μF 10 μF 22 μF
nF(6)
[mΩ]
[nH]
[mΩ]
vdd_dspeve
vdd
33
83
2.5
2
54
87
≤20
≤50
6
6
1
1
1
1
1
1
1
1
1
1
1
1
vdds_ddr1,
vdds_ddr2,
vdds_ddr3
33
2.5
200
≤100
8
4
2
2
cap_vddram_cor
e1
N/A
N/A
N/A
6
6
6
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
cap_vddram_cor
e2
cap_vddram_dsp
eve
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Electrical Characteristics
chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Electrical Characteristics chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Total Reff from PMIC output to remote sensing feedback point located as close to the Device's point of load as possible.
(8) Maximum Loop Inductance for decoupling capacitor.
7.3.5 Power Supply Mapping
TPS65917 is a Power management IC (PMIC) that can be used for the Device design. TI is now
investigating an optimized solution for high power use cases so the TPS65917 is subject to change. An
alternate dual converter power solution using LP8732Q and LP8733Q are recommended. TI requires the
use of one of these PMIC solutions for the following reasons:
•
•
TI has validated its use with the Device
Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
•
•
Support for power sequencing requirements (refer to Section 5.9.3 Power Sequencing)
Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
•
•
The AVS voltage of active rail in the combined rail needs to be used to set the power supply
The decoupling capacitance should be set according to the active rail in the combined rail
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
230
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 and LP8732 combined with LP8733 PMICs.
表 7-4. Power Supply Connections
TPS65917
SMPS1
SMPS2
SMPS3
SMPS4
Dual Converter Solution
LP8733Q Buck0
Valid Combination 1:
vdd_dspeve
LP8733Q Buck1
vdd
LP8732Q Buck0
vdds18v, vdds18v_ddr[3:1], vddshv[6:1]
vdds_ddr1, vdds_ddr2, vdds_ddr3
LP8732Q Buck1
表 7-5 illustrates the LP8733 and LP8732 OTP IDs required for DRA78x processor systems using different
DDR memory types.
表 7-5. OTP ID Memory Types Support
DDR Type
LP8733Q
LP8732Q
OTP Version
OTP Version
DDR2
DDR3
2A
2A
2A
2D
2F
2E
DDR3L
7.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 PMIC LDOLN output or LDO0 on LP8733Q dual power solution is specifically designed to
meet this low noise requirement.
注
For more information about Input Voltage Sources, see DPLLs, DLLs Specifications
表 7-6 present the voltage inputs that supply the DPLLs.
表 7-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_EVE_VID_DSP, DPLL_DDR and DDR HSDIVIDER analog power supply
vdda_ddr_dsp
vdda_gmac_core
GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER analog power
supply
7.3.7 Loss of Input Power Event
A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for
a “Loss of Input Power” event are:
•
“Loss of Input Power” early warning
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using the 1st Stage
Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the 2nd Stage
PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different 1st Stage Converter is used,
care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided that
can disable 2nd Stage PMIC to begin a controlled and compliant SoC power down sequence. The
total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage reaches minimum
level of 2.75V should be minimum of 1.5ms and 2ms preferred.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
231
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Maximize discharge time of 1st Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load
switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3V IO load
current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to
maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down
sequence. Care should be taken to either disable or isolate any additional peripheral components
that may be loading the VSYS_3V3 rail as well.
•
•
Sufficient bulk decoupling capacitance on the 1st Stage Vout (VSYS_3V3 per PDN) that allows for
desired 1.5 – 2ms elapsed time as described above.
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200uF of total
capacitance on VSYS_3V3. The 1st Stage Converter (i.e. LM536033-Q1) can typically drive a max
of 400uF to help extend VSYS_3V3 discharge time for a compliant SoC power down sequence.
Optimizing the 2nd Stage SoC PMIC’s OTP settings that determines SoC power up and down
sequences and total elapsed time needed for a controlled sequence.
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per
the SCH and components used. The definition of these OTPs is captured in the detailed timing
diagrams for both power up and down sequences. The PDN diagram typically shows a
recommended PMIC OTP ID based upon the SoC and DDR memory types.
7.3.8 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_dspeve key processor power domain.
注
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
7.3.8.1 Example Stack-up
Layer Assignments:
•
Layer Top: Signal and Segmented Power Plane
Processor and PMIC components placed on Top-side
–
•
•
•
•
•
•
•
Layer 2: Gnd Plane1
Layer 3: Signals
Layer n: Power Plane1
Layer n+1: Power Plane 2
Layer n+2: Signal
Layer n+3: Gnd Plane2
Layer Bottom: Signal and Segmented Power Planes
–
Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
•
•
½ oz for all signal layers.
1-2oz for all power plane for improved PCB heat spreading.
7.3.8.2 vdd_dspeve Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 33mΩ per 表 7-3 and (7).
232
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.5nH per 表 7-3 and (7) (ESL NOT included).
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 54mΩ per 表 7-3 and (7).
表 7-7. Example PCB vdd_dspeve PI Analysis Summary
Parameter
OPP
Recommendation
OPP_NOM
500 MHz
1 V
Example PCB
Clocking Rate
Voltage Level
Max Current Draw
1 V
1 A
1 A
Max Effective Resistance: Power
Inductor Segment Total Reff
13 mΩ
11.4 mΩ
Max Loop Inductance
Impedance Target
< 2.5 nH
0.73 - 1.58 nH
54 mΩ for F < 20 MHz
28.8 mΩ for F < 20 MHz
图 7-15 shows a PCB layout example and the resulting PI analysis results.
U1401
LP8733 PMIC
Buck0 (3A)
FB_VPO_S1_AVS
FB_B0
(2)
U5000
DRA78x
VDD_DSPEVE_AVS
L1402
0.47uH, 4A, 2520
DFE252012PD-R47M
VDD_DSPEVE
(P12, P11, M9, P9,
K8, L8, P8)
VPO_S1_AVS
VPO_S1_SW
C5079, 5080, 5085,
Buck 0__SW
(22,23)
5100, 5101, 5111
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C1409
22uF, 6.3V, X7R, 1206
GCM31CR70J226ME23
R1010
10mOhm, 1210
INA226&
Power Bench
C5021
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C5019
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C5018
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C5037
2.2uF, 6.3V, X5R, 0603
C1005X5R0J225M
C5030
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
C5026
22uF, 6.3V, X7R, 1206
GCM31CR70J226ME23
SPRS975_PCB_CORE_02
图 7-15. vdd_dspeve Simplified SCH Diagram
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
233
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-8. DCap Scheme
Vaule [uF]
Size
Qty
Capacitance [uF]
Cap Type: Automotive GCM series, X7R
22
4.7
2.2
1
1206
805
603
603
603
603
402
1
1
1
1
1
1
6
22
4.7
2.2
1
0.47
0.22
0.1
0.47
0.22
0.6
Totals
12
31.19
IR Drop: vdd_dspeve
图 7-16. vdd_dspeve Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the CORE power domain determined the vdd_dspeve decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 0.68 –1.79nH and were less than maximum 2.0nH recommended.
表 7-9. Decoupling Design Detail Summary
Cap Reference
Description
Loop Inductacne at
50MHz [nH]
Footprint Types
PCB Side
Distance to
Ball-Field [mils]
Value
Size
C5101
C5100
0.73
0.78
2vWEE
2vWEE
Bottom
Bottom
82
0.1
0.1
0402
0402
107
234
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-9. Decoupling Design Detail Summary (continued)
Cap Reference
Description
Loop Inductacne at
50MHz [nH]
Footprint Types
PCB Side
Distance to
Ball-Field [mils]
Value
Size
C5085
C5019
C5111
C5030
C5037
C5018
C5021
C5026
C5079
C5080
0.84
1.09
1.09
1.11
1.11
1.14
1.17
1.18
1.32
1.58
2vWEE
4vWE
4vWE
4vWE
4vWE
4vWE
4vWE
4vWE
4vWE
4vWE
Bottom
Top
35
0.1
0.47
0.1
4.7
2.2
1
0402
0603
0402
0805
0603
0603
0603
1206
0402
0402
631
681
738
563
681
761
792
542
602
Bottom
Top
Top
Top
Top
0.22
22
Top
Bottom
Bottom
0.1
0.1
(1) Distances are wrt "middle of Ball Field", Ref pt between: U5000-M9 to middle of Dcap's power pad unless specifed
图 7-17 shows vdd_dspeve Impedance vs Frequency characteristics.
图 7-17. vdd_dspeve Impedance vs Frequency
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
235
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.4 Single-Ended Interfaces
7.4.1 General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
•
Line spacing:
For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
–
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see 图 7-18).
W
D+
S = 2 W = 200 µm
SPRS91v_PCB_SE_GND_01
图 7-18. Ground Guard Illustration
•
Length matching (unless otherwise specified):
–
For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
–
For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
•
•
Characteristic impedance
–
Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
–
For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
7.4.2 QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
•
•
The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
•
The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
236
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in 图 7-19.
Propagation delays and matching:
–
–
–
–
A to C = C to D = E to F
Matching skew: < 60pS
A to B < 450pS
B to C = as small as possible (<60pS)
Locate both R2 resistors
close together near the QSPI device
A
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
D
qspi1_rtclk
E
F
QSPI device
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS906_PCB_QSPI_01
图 7-19. QSPI Interface High Level Schematic Mode 0 (POL=0, PHA=0)
注
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
•
•
The qspi1_rtclk input can be left unconnected.
The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
•
•
The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be
< 450pS (~7cm as stripline or ~8cm as microstrip).
50 Ω PCB routing is recommended along with series terminations, as shown in 图 7-20.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
237
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
Propagation delays and matching:
–
–
–
A to C = E to F.
Matching skew: < 60Ps
A to B < 450pS
A
C
R1
0 Ω*
qspi1_sclk
QSPI device
clock input
E
F
QSPI deice
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS91v_PCB_QSPI_01
图 7-20. QSPI Interface High Level Schematic Mode 3 (POL=1, PHA=1)
注
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
7.5 Differential Interfaces
7.5.1 General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
•
As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
•
Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
•
•
•
•
Minimize external components on differential lanes (like external ESD, probe points).
Through-hole pins are not recommended.
Differential lanes mustn’t cross image planes (ground planes).
No sharp bend on differential lanes.
238
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
•
•
Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
7.6 Clock Routing Guidelines
7.6.1 Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground. 图 7-21 shows the grounding scheme for slow (low
frequency) clock generated from the internal oscillator.
Device
rtc_osc_xo
Rd
rtc_osc_xi_clkin32
Crystal
(Optional)
Cf2
Cf1
SPRS91v_PCB_CLK_OSC_02
图 7-21. Grounding Scheme for Low-Frequency Clock
图 7-22 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
vssa_oscj
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS91v_PCB_CLK_OSC_03
(1) j in *_osc = 0 or 1
图 7-22. Grounding Scheme for High-Frequency Clock
7.7 DDR2 Board Design and Layout Guidelines
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
239
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.7.1 DDR2 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
•
•
•
•
•
•
•
•
•
•
•
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
7.7.2 DDR2 Board Design and Layout Guidelines
7.7.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory controller are shown in 表 7-10 and 图 7-23.
表 7-10. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
PARAMETE
NO.
DESCRIPTION
MIN
MAX
UNIT
R
DDR21
tc(DDR_CLK)
Cycle time, DDR_CLK
2.5
8
ns
1
ddrx_ck
PCB_DDR2_0
图 7-23. DDR2 Memory Controller Clock Timing
7.7.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
7.7.2.2.1 DDR2 Interface Schematic
图 7-24 shows the DDR2 interface schematic for a x32 DDR2 memory system. In 图 7-25 the x16 DDR2
system schematic is identical except that the high-word DDR2 device is deleted.
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and
ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not
being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use
of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
240
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR2
DQ0
ddrx_d0
ddrx_d7
DQ7
DQM0
DQS0
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_d8
DQS0n
DQ8
ddrx_d15
ddrx_dqm1
ddrx_dqs1
DQ15
DQM1
DQS1
ddrx_dqsn1
ddrx_odt0
DQS1n
ODT
ddrx_d16
DQ16
ddrx_d23
ddrx_dqm2
ddrx_dqs2
DQ23
DQM2
DQS2
DQS2n
DQ24
ddrx_dqsn2
ddrx_d24
DQ31
ddrx_d31
ddrx_dqm3
ddrx_dqs3
ddrx_dqsn3
DQM3
DQS3
DQS3n
ddrx_ba0
BA0
ddrx_ba2
ddrx_a0
BA2
A0
ddrx_a14
A14
CS
ddrx_csn0
vdds_ddrx(A)
ddrx_casn
ddrx_rasn
CAS
RAS
ddrx_wen
ddrx_cke
ddrx_ck
WE
CKE
CK
0.1 µF
0.1 µF
1 K Ω 1%
CK
ddrx_nck
VREF
VREF
1 K Ω 1%
ddrx_rst
NC
PCB_DDR2_1
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
图 7-24. 32-Bit DDR2 High-Level Schematic
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
241
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR2
DQ0
ddrx_d0
ddrx_d7
DQ7
LDM
LDQS
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_d8
LDQS
DQ8
ddrx_d15
ddrx_dqm1
ddrx_dqs1
ddrx_dqsn1
ddrx_odt0
DQ15
UDM
UDQS
UDQS
ODT
ddrx_d16
NC
vdds_ddrx(A)
ddrx_d23
NC
NC
ddrx_dqm2
1 KΩ
1 KΩ
ddrx_dqsn2
ddrx_dqs2
NC
ddrx_d24
vdds_ddrx(A)
ddrx_d31
NC
NC
1 KΩ
1 KΩ
ddrx_dqm3
ddrx_dqsn3
ddrx_dqs3
ddrx_ba0
NC
BA0
ddrx_ba2
ddrx_a0
BA2
A0
ddrx_a14
A14
CS
ddrx_csn0
CAS
RAS
ddrx_casn
ddrx_rasn
vdds_ddrx(A)
WE
ddrx_wen
ddrx_cke
ddrx_ck
CKE
CK
CK
1 K Ω 1%
0.1 µF
0.1 µF
ddrx_nck
VREF
VREF
1 K Ω 1%
ddrx_rst
NC
PCB_DDR2_2
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
图 7-25. 16-Bit DDR2 High-Level Schematic
242
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.7.2.2.2 Compatible JEDEC DDR2 Devices
表 7-11 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16/x32 DDR2-800 speed grade DDR2 devices.
表 7-11. Compatible JEDEC DDR2 Devices (Per Interface)
NO.
PARAMETER
JEDEC DDR2 device speed grade(1)
MIN
DDR2-800
x16
MAX
UNIT
CJ21
CJ22
CJ23
JEDEC DDR2 device bit width
JEDEC DDR2 device count(2)
x32
1
Bits
1
Devices
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) One DDR2 device is used for a 16-bit DDR2 and 32-bit DDR2 memory system.
7.7.2.2.3 PCB Stackup
The minimum stackup required for routing the Device is a six-layer stackup as shown in 表 7-12.
Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size
of the PCB footprint.
表 7-12. Minimum PCB Stackup
LAYER
TYPE
Signal
Plane
Plane
Signal
Plane
Signal
DESCRIPTION
External Routing
Ground
1
2
3
4
5
6
Power
Internal routing
Ground
External Routing
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
243
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
Complete stackup specifications are provided in 表 7-13.
表 7-13. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
MAX
UNIT
PS21
PS22
PS23
PS24
PCB routing/plane layers
6
3
1
1
Signal routing layers
Full ground reference layers under DDR2 routing region(1)
Full vdds_ddrx power reference layers under the DDR2 routing
region(1)
PS25
PS26
PS27
PS28
PS29
PS210
Number of reference plane cuts allowed within DDR routing region(2)
Number of layers between DDR2 routing layer and reference plane(3)
PCB routing feature size
0
0
4
4
Mils
Mils
Ω
PCB trace width, w
Single-ended impedance, Zo
Impedance control(4)
50
75
Z-5
Z
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers. A full ground reference layer should be placed adjacent to each DDR routing
layer in PCB stack up.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) Z is the nominal singled-ended impedance selected for the PCB specified by PS29.
244
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.7.2.2.4 Placement
图 7-26 shows the required placement for the Device as well as the DDR2 devices. The dimensions for
this figure are defined in 表 7-14. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device is omitted
from the placement.
X1
A1
DDR2
Memory
DDR2 Controller
Y1
PCB_DDR2_3
图 7-26. Device and DDR2 Device Placement
表 7-14. Placement Specifications DDR2
NO.
PARAMETER
MIN
MAX
1100
500
UNIT
Mils
KOD21
KOD22
KOD24
KOD25
X1
Y1
Mils
DDR2 keepout region (1)
Clearance from non-DDR2 signal to DDR2 keepout region (2) (3)
4
W
(1) DDR2 keepout region to encompass entire DDR2 routing area.
(2) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR2 and should be
separated by this specification.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
245
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.7.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in 图 7-27. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in 表 7-14.
The region shown in 表 7-14 should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keepout
region. Non-DDR2 signals may be routed in the region, provided they are routed on layers separated from
DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the vdds_ddrx power plane should cover the entire keepout region. Routes for the two
DDR interfaces must be separated by at least 4x; the more separation, the better.
DDR2 Controller
A1
Device
PCB_DDR2_4
图 7-27. DDR2 Keepout Region
7.7.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. 表 7-
15 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk bypass
capacitance may be needed for other circuitry.
表 7-15. Bulk Bypass Capacitors
NO.
PARAMETER
vdds_ddrx bulk bypass capacitor (≥1µF) count(1)
MIN
TYP
10
MAX
UNIT
Devices
μF
BC21
BC22
vdds_ddrx bulk bypass total capacitance
50
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR2 signal routing.
7.7.2.2.7 High-Speed Bypass Capacitors
TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and
placement is optimal for a given implementation. This section provides guidelines that can serve as a
good starting point.
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. 表 7-16 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
246
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
1. Fit as many HS bypass capacitors as possible.
2. HS bypass capacitor value is < 1µF
3. Minimize the distance from the bypass cap to the pins/balls being bypassed.
4. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
5. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
6. Minimize via sharing. Note the limites on via sharing shown in 表 7-16.
表 7-16. High-Speed Bypass Capacitors
NO.
PARAMETER
HS bypass capacitor package size(1)
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
Processor HS bypass capacitor count (12)
MIN
TYP
MAX
0402
400(12)
UNIT
10 Mils
Mils
HS21
HS22
HS23
HS24
0201
12(11)
3.4
Devices
μF
Processor HS bypass capacitor total capacitance per vdds_ddrx rail
(12)
HS25
Number of connection vias for each device power/ground ball per
vdds_ddrx rail (5)
1
Vias
HS26
HS27
Trace length from device power/ground ball to connection via(2)
Distance, HS bypass capacitor to DDR device being bypassed(6)
Number of connection vias for each HS capacitor(8)(9)
DDR2 device HS bypass capacitor count(7)
DDR2 device HS bypass capacitor total capacitance(7)
Trace length from bypass capacitor connect to connection via(2)(9)
35
70
Mils
Mils
150
(14)
HS28
4
Vias
Devices
μF
(13)
HS29
12
HS210
HS211
HS212
0.85
1
35
35
100
60
Mils
Number of connection vias for each DDR2 device power/ground
ball(10)
Vias
HS213
Trace length from DDR2 device power/ground ball to connection
via(2)(8)
Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of vdds_ddrx balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR2 device power/ground ball to the center of the capacitor package.
(7) Per DDR2 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see 节 7.3, Core Power Domains
(13) For more information refer to DDR2 specification.
(14) Preferred configuration is 4 vias: 2 to power and 2 to ground.
7.7.2.2.8 Net Classes
表 7-17 lists the clock net classes for the DDR2 interface. 表 7-18 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
247
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-17. Clock Net Class Definitions
CLOCK NET CLASS PIN NAMES
CK
ddrx_ck / ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR2 memory systems.
表 7-18. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
PIN NAMES
NET CLASS
ADDR_CTRL
CK
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
DQ0
DQ1
DQ2(1)
DQ3(1)
DQS0
DQS1
DQS2
DQS3
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
(1) Only used on 32-bit wide DDR2 memory systems.
7.7.2.2.9 DDR2 Signal Termination
Signal terminators are NOT required in CK, ADDR_CTRL, and DATA net classes. Serial terminators may
be used to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are integrated
on the data byte net classes. They should be enabled to ensure signal integrity. 表 7-19 shows the
specifications for the series terminators.
表 7-19. DDR2 Signal Terminations
NO.
PARAMETER
MIN
0
TYP
MAX
10
UNIT
Ω
ST21
ST22
ST23
CK net class(1)(2)
ADDR_CTRL net class(1) (2)(3)(4)
Data byte net classes (DQS0-DQS3, DQ0-DQ3)(5)
0
Zo
Ω
0
Zo
Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.
(2) Only required for EMI reduction.
(3) Terminator values larger than typical only recommended to address EMI issues.
(4) Termination value should be uniform across net class.
(5) No external terminations allowed for data byte net classes ODT is to be used.
7.7.2.2.10 VREF Routing
VREF (ddrx_vref0) is used as a reference by the input buffers of the DDR2 memories. VREF is intended
to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in 图
7-25. Other methods of creating VREF are not recommended. 图 7-28 shows the layout guidelines for
VREF.
248
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
VREF Nominal Max Trace
width is 20 mils
VREF Bypass Capacitor
vdds_ddrx(A)
1 K Ω 1%
VREF
0.1 µF
0.1 µF
DDR2 Controller
1 K Ω 1%
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
PCB_DDR2_5
图 7-28. VREF Routing and Topology
7.7.2.3 DDR2 CK and ADDR_CTRL Routing
图 7-29 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a point to
point connection with required skew matching.
DDR2 Controller
A’
PCB_DDR2_6
图 7-29. CK and ADDR_CTRL Routing and Topology
表 7-20. CK and ADDR_CTRL Routing Specification
NO.
PARAMETER
Center-to-center ddrx_ck - ddrx_nck spacing
MIN
MAX
2w
5
UNIT
RSC21
RSC22
RSC25
RSC26
RSC27
RSC28
RSC29
ddrx_ck / ddrx_nck skew
ps
Center-to-center CK to other DDR2 trace spacing(2)
CK/ADDR_CTRL trace length(3)
4w
680
25
ps
ps
ps
ADDR_CTRL-to-CK skew mismatch
ADDR_CTRL-to-ADDR_CTRL skew mismatch
Center-to-center ADDR_CTRL to other DDR2 trace spacing(2)
25
4w
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
249
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-20. CK and ADDR_CTRL Routing Specification (continued)
NO.
PARAMETER
MIN
MAX
UNIT
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(2)
RSC210
3w
(1) Series terminator, if used, should be located closest to the Device.
(2) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) This is the longest routing length of the CK and ADDR_CTRL net classes.
图 7-30 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended. The termination resistor should be placed
near the processor.
E0
E1
DDR2 Controller
E2
E3
PCB_DDR2_7
图 7-30. DQS and DQ Routing and Topology
表 7-21. DQS and DQ Routing Specification
NO.
PARAMETER
Center-to-center DQS-DQSn spacing in E0|E1|E2|E3
DQS-DQSn skew in E0|E1|E2|E3
Center-to-center DQS to other DDR2 trace spacing(1)
DQS/DQ trace length (2)(3)(4)
DQ-to-DQS skew mismatch(2)(3)(4)
DQ-to-DQ skew mismatch(2)(3)(4)
DQ-to-DQ/DQS via count mismatch(2)(3)(4)
Center-to-center DQ to other DDR2 trace spacing(1)(5)
Center-to-center DQ to other DQ trace spacing(1)(6)(7)
DQ/DQS E skew mismatch(2)(3)(4)
MIN
MAX
UNIT
RSDQ21
RSDQ22
RSDQ23
RSDQ24
RSDQ25
RSDQ26
RSDQ27
RSDQ28
RSDQ29
RSDQ210
2w
5
ps
4w
325
10
10
1
ps
ps
ps
Vias
4w
3w
25
ps
(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data
byte1.
(5) DQs from other DQS domains are considered other DDR2 trace.
(6) DQs from other data bytes are considered other DDR2 trace.
(7) This is the longest routing distance of each of the DQS and DQ net classes.
7.8 DDR3 Board Design and Layout Guidelines
250
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.8.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
•
•
•
•
•
•
•
•
•
Avoid crossing splits in the power plane.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
7.8.2 DDR3 Board Design and Layout Guidelines
7.8.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in 表 7-22 and 图
7-31.
表 7-22. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CLK)
Cycle time, DDR_CLK
1.875
2.5(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS91v_PCB_DDR3_01
图 7-31. DDR3 Memory Controller Clock Timing
7.8.2.2 DDR3 Device Combinations
There are several possible combinations of device counts and single- or dual-side mounting, 表 7-23
summarizes the supported device configurations.
表 7-23. Supported DDR3 Device Combinations
NUMBER OF DDR3
DEVICES
DDR3 DEVICE WIDTH
(BITS)
ECC DEVICE WIDTH
(BITS)
DDR3 EMIF WIDTH
(BITS)
MIRRORED?
1
2
2
2
2
3
3
1x16
2x8
-
-
N
Y(1)
N
16
16
32
32
16
16
32
2x16
2x16
1x16
2x8
-
-
Y(1)
1x8
1x8
1x8
N
N
2x16
N
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
251
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
7.8.2.3 DDR3 Interface Schematic
7.8.2.3.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. 图 7-32 and show the schematic connections for 32-bit interfaces using
x16 devices.
7.8.2.3.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see 图 7-32);
only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddr and vdds18v_ddrx power supply pins need to be connected to their respective power
supplies even if upper data byte lanes are not being used. All other DDR interface pins can be left
unconnected. Note that the supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or
not used.
252
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
32-bit DDR3 EMIF
16-Bit DDR3
Devices
ddrx_d31
ddrx_d24
DQ15
DQ8
8
ddrx_dqm3
ddrx_dqs3
ddrx_dqsn3
UDM
UDQS
UDQS
ddrx_d23
DQ7
8
ddrx_d16
D08
ddrx_dqm2
ddrx_dqs2
ddrx_dqsn2
LDM
LDQS
LDQS
ddrx_d15
DQ15
DQ8
8
ddrx_d8
ddrx_dqm1
ddrx_dqs1
ddrx_dqsn1
UDM
UDQS
UDQS
ddrx_d7
DQ7
8
ddrx_d0
DQ0
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
LDM
LDQS
LDQS
0.1 µF
Zo
Zo
ddrx_ck
CK
CK
CK
CK
DDR_1V5
ddrx_nck
ddrx_odt0
ddrx_csn0
ddrx_ba0
ddrx_ba1
ddrx_ba2
ODT
ODT
CS
CS
BA0
BA1
BA2
BA0
BA1
BA2
DDR_VTT
Zo
Zo
ddrx_a0
A0
A0
16
ddrx_a15
A15
A15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
CAS
CAS
RAS
WE
RAS
WE
CKE
CKE
RST
DDR_VREF
RST
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
0.1 µF
0.1 µF
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
图 7-32. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
253
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.8.2.4 Compatible JEDEC DDR3 Devices
表 7-24 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths.
表 7-24. Compatible JEDEC DDR3 Devices
N
PARAMETER
CONDITION
MIN
MAX
UNIT
O.
1
JEDEC DDR3 device speed grade(1)
DDR clock rate = 400MHz
DDR3-800
DDR3-1600
400MHz< DDR clock rate ≤ 533MHz
DDR3-1066
DDR3-1600
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(2)
x8
1
x16
3
Bits
Devices
(1) Refer to 表 7-22 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see 表 7-23 DDR3 Device Combinations.
7.8.2.5 PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in 表 7-25.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
表 7-26.
表 7-25. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
1
2
3
4
5
6
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
254
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-26. PCB Stackup Specifications
NO.
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PARAMETER
MIN
6
TYP
MAX
UNIT
PCB routing/plane layers
Signal routing layers
3
Full ground reference layers under DDR3 routing region(1)
Full 1.5-V power reference layers under the DDR3 routing region(1)
Number of reference plane cuts allowed within DDR routing region(2)
Number of layers between DDR3 routing layer and reference plane(3)
PCB routing feature size
1
1
0
0
4
4
Mils
Mils
Ω
PCB trace width, w
Single-ended impedance, Zo
50
75
Impedance control(5)
Z-5
Z
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
7.8.2.6 Placement
图 7-33 shows the required placement for the processor as well as the DDR3 devices. The dimensions for
this figure are defined in 表 7-27. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are
omitted from the placement.
x1
y2
DDR3
Controller
y2
Three Devices
SPRS91v_PCB_DDR3_04
图 7-33. Placement Specifications
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
255
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-27. Placement Specifications
No.
PARAMETER
MIN
MAX
1700
1800
600
UNIT
Mils
Mils
Mils
KOD31
KOD34
KOD35
KOD36
X1
Y1
Y2
DDR3 keepout
region(1)
KOD37
Clearance from non-
DDR3 signal to
DDR3 keepout
region (2)(3)
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
7.8.2.7 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in 图 7-34. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in 表 7-27.
Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-
DDR3 signals may be routed in the region, provided they are routed on layers separated from the DDR
signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region.
In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two
signals from the DDR3 controller should be separated from each other by the specification in 表 7-27 (see
KOD37).
256
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR3 Keepout Region
DDR3
Controller
Three Devices
SPRS91v_PCB_DDR3_05
图 7-34. DDR3 Keepout Region
7.8.2.8 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. 表 7-
28 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass
capacitance may be needed for other circuitry.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
257
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-28. Bulk Bypass Capacitors
NO.
1
PARAMETER
vdds_ddrx bulk bypass capacitor count(1)
vdds_ddrx bulk bypass total capacitance
MIN
1
MAX
UNIT
Devices
μF
2
22
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
7.8.2.9 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. 表 7-29 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in 表 7-29.
表 7-29. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
0402
400
UNIT
10 Mils
Mils
0201
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
Processor HS bypass capacitor count per vdds_ddrx rail(12)
Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)
Number of connection vias for each device power/ground ball(5)
Trace length from device power/ground ball to connection via(2)
Distance, HS bypass capacitor to DDR device being bypassed(6)
DDR3 device HS bypass capacitor count(7)
3
See 表 7-3 and (11)
See 表 7-3 and (11)
Devices
μF
4
5
Vias
6
35
70
Mils
7
150
Mils
8
12
0.85
2
Devices
μF
9
DDR3 device HS bypass capacitor total capacitance(7)
10 Number of connection vias for each HS capacitor(8)(9)
11 Trace length from bypass capacitor connect to connection via(2)(9)
12 Number of connection vias for each DDR3 device power/ground ball(10)
13 Trace length from DDR3 device power/ground ball to connection via(2)(8)
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
Vias
35
35
100
60
Mils
1
Vias
Mils
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see 节 7.3, Core Power Domains.
258
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.8.2.9.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. These are returns for signal current, the signal via size may be used for these capacitors.
7.8.2.10 Net Classes
表 7-30 lists the clock net classes for the DDR3 interface. 表 7-31 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
表 7-30. Clock Net Class Definitions
CLOCK NET CLASS processor PIN NAMES
CK
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR3 memory systems.
表 7-31. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
processor PIN NAMES
NET CLASS
ADDR_CTRL
CK
ddrx_ba[2:0], ddrx_a[15:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
DQ0
DQ1
DQ2(1)
DQ3(1)
DQS0
DQS1
DQS2
DQS3
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
(1) Only used on 32-bit wide DDR3 memory systems.
7.8.2.11 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
7.8.2.12 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in 表 7-32.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
259
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.8.2.13.1 Three DDR3 Devices
Three DDR3 devices are supported on the DDR EMIF consisting of two x16 DDR3 devices and one
device for ECC, arranged as one bank (CS). These three devices may be mounted on a single side of the
PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and
parts on the backside of the PCB.
7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
图 7-35 shows the topology of the CK net classes and 图 7-36 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
–
+
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
A4
A4
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS91v_PCB_DDR3_06
图 7-35. CK Topology for Three DDR3 Devices
DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
AT
Vtt
SPRS91v_PCB_DDR3_07
图 7-36. ADDR_CTRL Topology for Three DDR3 Devices
7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
图 7-37 shows the CK routing for three DDR3 devices placed on the same side of the PCB. 图 7-38 shows
the corresponding ADDR_CTRL routing.
260
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
AT
AT
0.1 µF
=
SPRS91v_PCB_DDR3_08
图 7-37. CK Routing for Three Single-Side DDR3 Devices
Rtt
A2
A3
A4
AT
Vtt
=
SPRS91v_PCB_DDR3_09
图 7-38. ADDR_CTRL Routing for Three Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as one mirrored pair at a cost of
increased routing and assembly complexity. 图 7-39 and 图 7-40 show the routing for CK and
ADDR_CTRL, respectively, for two DDR3 devices mirrored in a pair configuration.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
261
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS91v_PCB_DDR3_10
图 7-39. CK Routing for Two Mirrored DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
SPRS91v_PCB_DDR3_11
图 7-40. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
7.8.2.13.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
图 7-41 shows the topology of the CK net classes and 图 7-42 shows the topology for the corresponding
ADDR_CTRL net classes.
262
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
Processor
+
–
Differential Clock
Output Buffer
0.1 µF
Rcp
Routed as Differential Pair
SPRS91v_PCB_DDR3_12
图 7-41. CK Topology for Two DDR3 Devices
DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
AT
Vtt
SPRS91v_PCB_DDR3_13
图 7-42. ADDR_CTRL Topology for Two DDR3 Devices
7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
图 7-43 shows the CK routing for two DDR3 devices placed on the same side of the PCB. 图 7-44 shows
the corresponding ADDR_CTRL routing.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
263
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS91v_PCB_DDR3_14
图 7-43. CK Routing for Two Single-Side DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
SPRS91v_PCB_DDR3_15
图 7-44. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. 图 7-45 and 图 7-46 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
264
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS91v_PCB_DDR3_16
图 7-45. CK Routing for Two Mirrored DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
SPRS91v_PCB_DDR3_17
图 7-46. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
7.8.2.13.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
图 7-47 shows the topology of the CK net classes and 图 7-48 shows the topology for the corresponding
ADDR_CTRL net classes.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
265
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR Differential CK Input Buffer
–
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A2
A2
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
A1
Routed as Differential Pair
SPRS91v_PCB_DDR3_18
图 7-47. CK Topology for One DDR3 Device
DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
AT
Vtt
SPRS91v_PCB_DDR3_19
图 7-48. ADDR_CTRL Topology for One DDR3 Device
7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
图 7-49 shows the CK routing for one DDR3 device placed on the same side of the PCB. 图 7-50 shows
the corresponding ADDR_CTRL routing.
266
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DDR_1V5
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
SPRS91v_PCB_DDR3_20
图 7-49. CK Routing for One DDR3 Device
Rtt
A2
AT
Vtt
=
SPRS91v_PCB_DDR3_21
图 7-50. ADDR_CTRL Routing for One DDR3 Device
7.8.2.14 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
267
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. 图 7-51 and 图
7-52 show these topologies.
Processor
DQS
DDR
DQSn+
DQSn-
DQS
IO Buffer
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
SPRS91v_PCB_DDR3_22
图 7-51. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
Dn
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS91v_PCB_DDR3_23
图 7-52. DQ/DM Topology
7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
图 7-53 and 图 7-54 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2
SPRS91v_PCB_DDR3_24
图 7-53. DQS Routing With Any Number of Allowed DDR3 Devices
268
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DQ and DM
Dn
n = 0, 1, 2
SPRS91v_PCB_DDR3_25
图 7-54. DQ/DM Routing With Any Number of Allowed DDR3 Devices
7.8.2.15 Routing Specification
7.8.2.15.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-55 and 图 7-56 show this
distance for three loads and two loads, respectively. It is from this distance that the specifications on the
lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for
other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class.
For CK and ADDR_CTRL routing, these specifications are contained in 表 7-32.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
269
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
A8(A)
Rtt
A2
A3
A4
AT
Vtt
=
SPRS91v_PCB_DDR3_26
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-55. CACLM for Three Address Loads on One Side of PCB
270
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
Vtt
=
SPRS91v_PCB_DDR3_27
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-56. CACLM for Two Address Loads on One Side of PCB
表 7-32. CK and ADDR_CTRL Routing Specification(2)(3)
NO.
PARAMETER
MIN
TYP
MAX
500(1)
29
UNIT
ps
CARS31
CARS32
CARS33
CARS34
CARS35
CARS36
CARS37
CARS38
CARS39
CARS310
CARS311
CARS312
CARS313
CARS314
CARS315
CARS316
CARS317
CARS318
CARS319
CARS320
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
A4 length
ps
125
6
ps
ps
6
ps
125
6
17(1)
14(1)
12
ps
A4 skew
ps
AS length
5
1.3
5
ps
AS skew
ps
AS+/AS- length
AS+/AS- skew
AT length(6)
AT skew(7)
AT skew(8)
ps
1
ps
75
14
ps
ps
1
ps
CK/ADDR_CTRL trace length
1020
3(1)
1(15)
ps
Vias per trace
vias
vias
Via count difference
Center-to-center CK to other DDR3 trace spacing(9)
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
4w
3w
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
271
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-32. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CK center-to-center spacing(11)(12)
CK spacing to other net(9)
Rcp(13)
MIN
TYP
MAX
UNIT
CARS321
CARS322
CARS323
CARS324
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
Ω
Ω
Rtt(13)(14)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
7.8.2.15.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are three
DQLMs, DQLM0-DQLM2. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
注
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-57 shows this distance for four
loads. It is from this distance that the specifications on the lengths of the transmission lines for the data
bus are determined. For DQS and DQ/DM routing, these specifications are contained in 表 7-33.
272
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
DQLMX0
DB0
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DB1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMY0
DQLMX2
DQLMY1
DQLMY2
2
1
0
DB0 - DB2 represent data bytes 0 - 2.
SPRS91v_PCB_DDR3_28
There are three DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
图 7-57. DQLM for Any Number of Allowed DDR3 Devices
表 7-33. Data Routing Specification(2)
NO.
PARAMETER
MIN
TYP
MAX
340
340
340
5
UNIT
ps
DRS31
DRS32
DRS33
DRS35
DRS36
DRS37
DRS38
DRS39
DRS310
DRS311
DRS312
DRS313
DB0 length
DB1 length
ps
DB2 length
DBn skew(3)
ps
ps
DQSn+ to DQSn- skew
DQSn to DBn skew(3)(4)
Vias per trace
1
ps
5(10)
2(1)
0(10)
ps
vias
vias
w(5)
w(5)
Via count difference
Center-to-center DBn to other DDR3 trace spacing(6)
Center-to-center DBn to other DBn trace spacing(7)
DQSn center-to-center spacing(8)(9)
4
3
DQSn center-to-center spacing to other net
4
w(5)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
273
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
The device's analog video CVIDEO/SD-DAC TV analog composite output can be operate in one of two
modes: Normal mode and TVOUT Bypass mode. In Normal mode, the device’s internal video amplifier is
used. In TVOUT Bypass mode, the internal video amplifier is bypassed and an external amplifier is
required.
图 7-58 shows a typical circuit that permits connecting the analog video output from the device to standard
75-Ω impedance video systems in Normal mode.
Reconstruction
Filter(A)
~9.5 MHz
cvideo_tvout
(B)
CAC
ROUT
cvideo_vfb
A. Reconstruction Filter (optional)
B. AC coupling capacitor (optional)
图 7-58. TV Output (Normal Mode)
图 7-59 shows a typical circuit that permits connecting the analog video output from the device to standard
75-Ω impedance video systems in TVOUT Bypass mode.
75 W
Reconstruction
Filter(A)
~9.5 MHz
Amplifier
3.7 V/V
cvideo_vfb
(B)
CAC
RLOAD
A. Reconstruction Filter (optional). Note: An amplifier with an integrated reconstruction filter can alternatively be used
instead of a discrete reconstruction filter.
B. AC coupling capacitor (optional)
图 7-59. TV Output (TVOUT Bypass Mode)
During board design, the onboard traces and parasitics must be matched for the channel. The video DAC
output pins (cvideo_tvout / cvideo_vfb) are very high-frequency analog signals and must be routed with
extreme care. As a result, the paths of these signals must be as short as possible, and as isolated as
possible from other interfering signals. In TVOUT Bypass mode, the load resistor and amplifier/buffer
should be placed as close as possible to the cvideo_vfb pin. Other layout guidelines include:
•
•
Take special care to bypass the vdda_dac power supply pin with a capacitor.
In TVOUT Bypass mode, place the RLOAD resistor as close as possible to the Reconstruction Filter
and Amplifier. In addition, place the 75-Ω resistor as close as possible (< 0.5 inch) to the
Amplifier/buffer output pin. To maintain a high-quality video signal, the onboard traces after the 75-Ω
resistor should have a characteristic impedance of 75 Ω (± 20%).
•
In Normal mode,cvideo_vfb is the most sensitive pin in the TV out system. The ROUT resistor should
be placed as close as possible to the device pins. To maintain a high-quality video signal, the onboard
traces leading to the cvideo_tvout pin should have a characteristic impedance of 75 Ω (± 20%) starting
from the closest possible place to the device pin output.
•
•
•
Minimize input trace lengths to the device to reduce parasitic capacitance.
Include solid ground return paths.
Match trace lengths as close as possible within a video format group.
274
Applications, Implementation, and Layout
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 7-34 and 表 7-35 present the Static and Dynamic CVIDEO / SD-DAC TV analog composite output
specifications
表 7-34. Static CVIDEO/SD-DAC Specifications
PARAMETER
TEST CONDITIONS
MIN
4653
9900
2673
TYP
4700
10000
2700
MAX
4747
10100
2727
UNIT
Ω
Reference Current Setting Resistor Normal Mode
(RSET
)
TVOUT Bypass Mode
Normal Mode
Ω
Output resistor between
Ω
cvideo_tvout and cvideo_vfb pins
TVOUT Bypass Mode
N/A
(ROUT
)
Load Resistor (RLOAD
)
Normal Mode
75-Ω Inside the Display
TVOUT Bypass Mode
Normal Mode
1485
220
1500
1515
Ω
AC-Coupling Capacitor (Optional)
[CAC
uF
]
TVOUT Bypass Mode
Normal Mode
See External Amplifier Specification
Total Capacitance from
cvideo_tvout to vssa_dac
300
pF
TVOUT Bypass Mode
N/A
Resolution
10
Bits
LSB
LSB
LSB
LSB
V
Integral Non-Linearity (INL), Best
Fit
Normal Mode
-4
-1
4
TVOUT Bypass Mode
Normal Mode
1
Differential Non-Linearity (DNL)
-2.5
-1
2.5
1
TVOUT Bypass Mode
Normal Mode (RLOAD = 75 Ω)
Full-Scale Output Voltage
1.3
TVOUT Bypass Mode (RLOAD
1.5 kΩ)
=
0.7
V
Full-Scale Output Current
Gain Error
Normal Mode
N/A
TVOUT Bypass Mode
470
uA
Normal Mode (Composite) and
TVOUT Bypass Mode
-10
-20
10
%FS
%FS
Normal Mode (S-Video)
20
Gain Mismatch (Luma-to-Chroma)
Output Impedance
Normal Mode (Composite)
Normal Mode (S-Video)
N/A
-10
10
%
Looking into cvideo_tvout nodes
75
Ω
表 7-35. Dynamic CVIDEO/SD-DAC Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
54
6
MAX
UNIT
MHz
MHz
Output Update Rate (FCLK
)
60
Signal Bandwidth
3 dB
Spurious-Free Dynamic Range
(SFDR) within bandwidth
FCLK = 54 MHz, FOUT = 1 MHz
FCLK = 54 MHz, FOUT = 1 MHz
50
54
6
dBc
dB
Signal-to-Noise Ration (SNR)
Normal Mode, 100 mVpp @ 6
MHz on vdda_dac
Power Supply Rejection (PSR)
dB
TVOUT Bypass Mode, 100
mVpp @ 6 MHz on vdda_dac
20
版权 © 2016–2019, Texas Instruments Incorporated
Applications, Implementation, and Layout
275
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
8 Device and Documentation Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules are listed below.
8.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, DRA78x). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of DRA78x devices in the ABF package type, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the DRA78x SoC for
Automotive Infotainment Silicon Revision 2.0.
8.1.1 Standard Package Symbolization
注
Some devices may have a cosmetic circular marking visible on the top of the device package
which results from the production test process. In addition, some devices may also show a
color variation in the package substrate which results from the substrate manufacturer.
These differences are cosmetic only with no reliability impact.
276
Device and Documentation Support
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
图 8-1. Printed Device Reference
8.1.2 Device Naming Convention
表 8-1. Nomenclature Description
FIELD PARAMETER
FIELD DESCRIPTION
VALUE
DESCRIPTION
a
Device evolution
stage(1)
X
P
Prototype
Preproduction (production test flow, no reliability data)
Production
BLANK
(2)
BBBBBB
Base production part
number
DRA780 Indicates base production part number. For more information see 表 3-1,
Device Comparison Table.
DRA781
DRA782
DRA783
DRA784
DRA785
DRA786
DRA787
DRA788
r
Device revision
Device Speed
BLANK
SR 1.0
SR 1.0A
SR 2.0
A
B
z
D
Indicates the speed grade for each of the cores in the device. For more
information see 表 3-1, Device Comparison Table.
R
S
OTHER
G
Y
Device type
General purpose (Prototype and Production)
Emulation (E) devices
E
D
High security prototype devices with TI Development keys (D)
Letter followed by number indicates HS device with customer key
ABF FCBGA-N367 (15mm x 15mm) Package
Yn
PPP
Package designator
ABF
版权 © 2016–2019, Texas Instruments Incorporated
Device and Documentation Support
277
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
表 8-1. Nomenclature Description (continued)
FIELD PARAMETER
FIELD DESCRIPTION
VALUE
BLANK
Q1
DESCRIPTION
Not meeting automotive qualification
Meeting Q100 equal requirements, with exceptions as specified in DM
Q1
Automotive Designator
XXXXXXX
YYY
ZZZ
Lot Trace Code
Production Code, For TI use only
Production Code, For TI use only
Pin one designator
O
G1
ECAT—Green package designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) XTDA3SX is the base part number for the superset device. Software should constrain the features used to match the intended
production device.
注
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
8.2 Tools and Software
The following products support development for DRA78x platforms:
Design Kits and Evaluation Modules
DRA78X Evaluation Module
The Jacinto™ DRA78x evaluation module (EVM) is an evaluation platform designed to
speed up development efforts and reduce time-to-market for Radio Signal Processor (RSP)
applications.The EVM also integrates a host of peripherals including multicamera interfaces
(both parallel and serial) displays, CAN, and GigB Ethernet AVB. The EVM also integrates
key peripherals such as Ethernet, FPD-Link and HDMI.
Software
Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS
Processor SDK Linux Automotive is the foundational software development platform for TI's
Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to
develop feature-rich Infotainment solutions such as reconfigurable digital instrument cluster,
integrated cockpit, in-vehicle infotainment, telematics, rear seat entertainment, etc for next
generation automobiles. The SDK is based on common Processor SDK platform.
Development Tools
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is
an interactive clock tree configuration software that provides information about the clocks
and modules in these TI devices. It allows the user to: Visualize the device clock tree.
Interact with clock tree elements and view the effect on PRCM registers. Interact with the
PRCM registers and view the effect on the device clock tree. View a trace of all the device
registers affected by the user interaction with clock tree.
Models
DRA78X BSDL Model BSDL Model
DRA78X IBIS Model IBIS Model
DRA78x Thermal Model Thermal Model
278
Device and Documentation Support
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
8.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The following documents describe the DRA78x devices.
Technical Reference Manual
DRA78x SoC for Automotive Infotainment Silicon Revision 2.0
Details the integration, the environment, the functional description, and the programming
models for each peripheral and subsystem in the DRA78x family of devices.
Errata
DRA78x SoC for Automotive Infotainment Silicon Revision 2.0
Describes the known exceptions to the functional specifications for the device.
8.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表 8-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DRA780
DRA781
DRA782
DRA783
DRA784
DRA785
DRA786
DRA787
DRA788
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.6 商标
E2E is a trademark of Texas Instruments.
TMS320C674x, C674x, C64x+, ICEPick are trademarks of Texas Instruments Inc.
Arm, Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Arm, Thumb are registered trademarks of Arm Limited.
版权 © 2016–2019, Texas Instruments Incorporated
Device and Documentation Support
279
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
QSPI is a trademark of Cadence Design Systems, Inc.
JTAG is a registered trademark of JTAG Technologies, Inc.
MIPI is a registered trademark of Mobile Industry Processor Interface (MIPI) Alliance.
MMC is a trademark of MultiMediaCard Association.
SD is a registered trademark of Toshiba Corporation.
HD Radio is a trademark of iBiquity Digital Corporation.
All other trademarks are the property of their respective owners.
8.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.8 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
280
Device and Documentation Support
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
DRA780, DRA781, DRA782, DRA783, DRA784
DRA785, DRA786, DRA787, DRA788
ZHCSI52G –AUGUST 2016–REVISED MARCH 2019
www.ti.com.cn
9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
版权 © 2016–2019, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
281
提交文档反馈意见
产品主页链接: DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRA780BDGABFQ1
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
ABF
367
367
367
367
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 125
DRA780BDGABFQ1
JACINTO
775
775 ABF
DRA780BDGABFRQ1
DRA781BRGABFQ1
DRA781BRGABFRQ1
ACTIVE
ACTIVE
ACTIVE
ABF
ABF
ABF
750
90
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
DRA780BDGABFQ1
JACINTO
775
775 ABF
DRA781BRGABFQ1
JACINTO
775
775 ABF
750
DRA781BRGABFQ1
JACINTO
775
775 ABF
DRA782BDGABFQ1
DRA782BDGABFRQ1
DRA783BRGABFQ1
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ABF
ABF
ABF
367
367
367
90
750
90
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Call TI
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 125
-40 to 125
-40 to 125
DRA782BDGABFQ1
775
775 ABF
DRA782BDGABFQ1
775
775 ABF
DRA783BRGABFQ1
JACINTO
775
775 ABF
DRA783BRJABFQ1
DRA783BRJABFRQ1
DRA786BDGABFQ1
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ABF
ABF
ABF
367
367
367
90
90
90
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
RoHS & Green
Level-3-250C-168 HR
DRA786BDGABFQ1
JACINTO
775
775 ABF
DRA786BDGABFRQ1
ACTIVE
FCBGA
ABF
367
750
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 125
DRA786BDGABFQ1
JACINTO
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
775
775 ABF
DRA787BRGABFQ1
DRA787BRGABFRQ1
ACTIVE
ACTIVE
FCBGA
FCBGA
ABF
367
367
90
RoHS & Green
RoHS & Green
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 125
-40 to 125
DRA787BRGABFQ1
JACINTO
775
775 ABF
ABF
750
Call TI
DRA787BRGABFQ1
JACINTO
775
775 ABF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OUTLINE
ABF0367A
FCBGA - 2.82 mm max height
SCALE 0.900
BALL GRID ARRAY
15.12
14.88
A
B
BALL A1 CORNER
15.12
14.88
(
11.6)
(
14.6)
(1.3)
(2.39)
0.25 C
C
2.82 MAX
SEATING PLANE
NOTE 4
(0.99)
BALL TYP
0.1 C
0.4
0.2
TYP
13.65 TYP
SYMM
(0.68) TYP
(0.68) TYP
0.65 TYP
AB
AA
Y
V
T
W
U
R
N
L
13.65
P
M
K
H
F
TYP
SYMM
J
G
E
C
A
0.45
0.35
367X
D
B
0.15
0.08
C A B
C
NOTE 3
1
3
5
7
9
11 13 15 17 19 21
10 12 18
22
0.65 TYP
6
8
2
4
14 16
20
4221430/C 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crown of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
ABF0367A
FCBGA - 2.82 mm max height
BALL GRID ARRAY
(0.65) TYP
1
2
3 4 6 7
5 8
9 10 11 12 13
14 15 16 17 18 19 20 21 22
A
B
C
(0.65) TYP
D
E
F
0.365
0.335
367X
G
H
J
K
SYMM
L
M
N
P
R
T
U
V
W
Y
AA
AB
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
0.05 MAX
0.05 MIN
METAL
UNDER
MASK
(
0.35)
METAL
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221430/C 04/2019
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ABF0367A
FCBGA - 2.82 mm max height
BALL GRID ARRAY
(0.65) TYP
1
2
3 4 6 7
5 8
9 10 11 12 13
14 15 16 17 18 19 20 21 22
A
B
C
(0.65)
TYP
D
E
0.365
0.335
F
362X
G
H
J
K
SYMM
L
M
N
P
R
T
U
V
W
Y
AA
AB
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4221430/C 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明