DRA821U-Q1 [TI]
具有双核 Arm® Cortex®-A72、四核 Cortex-R5F、四端口以太网交换机、PCIe 的汽车网关 SoC;
| 型号： | DRA821U-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双核 Arm® Cortex®-A72、四核 Cortex-R5F、四端口以太网交换机、PCIe 的汽车网关 SoC 以太网 PC |
| 文件： | 总259页 (文件大小：5023K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
DRA821 Jacinto™ 处理器
• 加密硬件加速器–带ECC 的PKA、AES、SHA、
RNG、DES 和3DES
1 特性
处理器内核：
功能安全：
• 双核64 位Arm® Cortex®-A72 微处理器子系统，性
能高达2.0GHz、24K DMIPS
• 以功能安全合规型为目标（在部分器件型号上）
– 专为功能安全应用开发
– 每个双核Cortex®-A72 集群具有1MB L2 共享缓
存
– 每个A72 内核具有32KB L1 数据缓存和48KB
L1 指令缓存
– 将提供使ISO 26262 和IEC 61508 功能安全系
统设计满足ASIL-D/SIL-3 要求的文档
– 系统功能符合ASIL-D/SIL-3 要求
– 对于MCU 域，硬件完整性符合ASIL-D/SIL-3
要求
– 对于MAIN 域的扩展MCU (EMCU) 部分，硬件
完整性符合ASIL-D/SIL-3 要求
– 对于MAIN 域的其余部分，硬件完整性符合
ASIL-B/SIL-2 要求
• 4 个Arm® Cortex®-R5F MCU，性能高达
1.0GHz，具有可选锁步操作，8K DMIPS
– 32K 指令缓存，32K 数据缓存，64K L2 TCM
– 隔离MCU 子系统中有2 个Arm® Cortex®-R5F
MCU
– 通用计算分区中有2 个Arm® Cortex®-R5F
– 在EMCU 和MAIN 域的其余部分之间提供FFI
隔离
– 安全相关认证
MCU
存储器子系统：
• 1MB 的片上L3 RAM（具有ECC 和一致性）
• 计划的ISO 26262 和IEC 61508 认证
• 符合AEC-Q100 标准（以Q1 结尾的器件型号）
• 高速接口：
– ECC 错误保护
– 共享一致性缓存
– 集成以太网TSN/AVB 交换机，支持最多4 个
(DRA821U4) 或2 个(DRA821U2) 外部端口：
– 支持内部DMA 引擎
• 外部存储器接口(EMIF) 模块（具有ECC）
• 一个端口支持5Gb、10Gb USXGMII/XFI
• 所有端口均支持2.5Gb SGMII
• 所有端口均支持1Gb SGMII/RGMII
• DRA821U4：任一个端口都可以支持
QSGMII（使用所有4 个内部端口）
• 无阻塞线速存储和转发交换机
• InterVLAN（第3 层）路由支持
• 通过IEEE 1588（附件D、E 和F）提供时
间同步支持
– 支持符合JESD209-4B 规范的LPDDR4 存储器
类型。（不支持字节模式LPDDR4 存储器或具
有超过17 行地址位的存储器）
– 支持高达3200MT/s 的速度
– 具有内联ECC 总线的32 位和16 位数据总线，
数据速率高达12.8GB/s
• 通用存储器控制器(GPMC)
• MAIN 域中的512KB 片上SRAM，受ECC 保护
虚拟化：
• TSN/AVB 对流量调度和整形的支持
• 用于调试和诊断的端口监视功能
• 管制和速率限制支持
• Arm® Cortex®-A72 中的管理程序支持
• 独立处理子系统，带Arm® Cortex®-A72、Arm®
Cortex®-R5F，采用隔离式安全MCU 岛
• IO 虚拟化支持
– 安全MCU 岛中一个RGMII/RMII 端口
• 一个PCI-Express® 第3 代控制器
– 外设虚拟化单元(PVU)，用于低延迟高带宽的外
设流量
– 第1 代、第2 代和第3 代均可使用，具有自动
协商功能
• 针对存储器和外设隔离的多区域防火墙支持
• 通过以太网、PCIe 和DMA 提供虚拟化支持
• 器件安全（在部分器件型号上）：
• 安全引导，提供安全运行时支持
• 客户可编程的根密钥，级别高达RSA-4K 或
ECC-512
– 4 个通道
• 一个USB 3.1 第1 代双重角色器件子系统
– 支持Type-C 开关
– 独立配置为USB 主机、USB 外设或USB 双重
角色器件
汽车接口：
• 嵌入式硬件安全模块
• 20 个CAN-FD 端口
• 12 个通用异步接收器/发射器(UART)
• 11 个串行外设接口(SPI)
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
• 一个8 通道ADC
• 16nm FinFET 技术
• 10 个内部集成电路(I2C™)
• 2 个改进的内部集成电路(I3C®)
• 17.2mm x 17.2mm，0.8mm 间距，IPC 3 类PCB
2 应用
音频接口：
• 3 个多通道音频串行端口(McASP) 模块
• 汽车网关
• 车辆计算
• 车身控制模块
• 远程信息处理控制单元
• V2X/V2V
• 工厂自动化网关
• 通信设备
• 工业运输
闪存接口：
• 嵌入式多媒体卡(eMMC™ 5.1) 接口
– 支持高达HS400 的速度
• 一个安全数字® 3.0/安全数字输入输出3.0 (SD3.0/
SDIO3.0) 接口
• 一个Octal SPI/Xccela™/HyperBus™ 存储器控制器
• 楼宇自动化网关
(HBMC) 接口
3 说明
Jacinto™ DRA821x 处理器基于 Armv8 64 位架构，针对具有云连接能力的网关系统进行了优化。片上系统 (SoC)
设计可通过集成（尤其是系统 MCU、功能安全和安全性特性以及可实现高速通信的以太网交换机）降低系统级成
本和复杂性。集成式诊断和功能安全特性满足ASIL-D 和SIL-3 认证要求。实时控制和低延迟通信由PCIe 控制器
和支持TSN 的千兆位以太网交换机提供支持。
多达四种通用 Arm® Cortex®-R5F 子系统可以处理简单的时序关键型处理任务，从而使 Arm® Cortex®-A72 核心
不受高级应用和基于云的应用的影响。
Jacinto DRA821x 处理器还包含扩展 MCU (eMCU) 域的概念。该域是MAIN 域上处理器和外围设备的子集，旨在
实现更高的功能安全性，例如 ASIL-D/SIL-3。功能方框图突出显示了哪个 IP 包含在 eMCU 中。有关 eMCU 和功
能安全的更多详细信息，请参阅DRA821 安全手册处理器德州仪器(TI) Jacinto™ 7 产品系列(SPRUIX4)。
封装信息
封装(1)
封装尺寸(2)
器件型号
DRA821U4-Q1
ALM（FCBGA，433）
17.2mm × 17.2mm
DRA821U4
DRA821U2-Q1
DRA821U2
ALM（FCBGA，433）
ALM（FCBGA，433）
17.2mm × 17.2mm
17.2mm × 17.2mm
XJ7200GB
(1) 如需了解更多信息，请参阅机械、封装和可订购信息。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
3.1 功能方框图
图3-1 是器件的功能方框图。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
2
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
DRA821
Navigator Subsystem(E)
System Services(E)
Mailboxes UDMA
2x Arm®
Cortex®-R5F(E)
(with optional Lockstep)
Dual Arm®
Cortex®-A72
SecProxy
UDMA
PVU
CPTS
Proxy/RA
WWDT
GPIO
INTR
Mailbox
GP Timers
Debug
MCRC
INTA
Spinlock
TIMER-MGR
Channelized FW
64K L2 RAM
per Core(E)
1MB Shared L2
Cache with ECC
Spinlock
Memory Subsystem
Security Accelerators
3DES AES
RNG
DES
SHA
PKA
MSMC
1MB SRAM with ECC(E)
MCU Island
EMIF 1x32 LPDDR4 with ECC(E)
Navigator Subsystem
2x Arm®
Cortex®-R5F
(with optional Lockstep)
DMSC
10x GP Timers
2x RTI/WWDT
Safety DTK
Proxy
INTA
UDMA
INTR
RA
GPMC
ELM
SA2UL
MCRC
Channelized FW
512KB SRAM(E)
SP RAM 512B
1 MB SRAM
Interconnect
Media and Data Storage
Control Interfaces
General Connectivity
High-Speed Serial Interfaces
1x PCIe®4-Lane Port (B)
6x EPWM
3x ECAP
3x EQEP
1x eMMC
2x WKUP GPIO
2x GPIO(F)
1x USB 3.0 DRD(B)
8x MCSPI(D)(F)
1x SD/SDIO
(D)
3x MCSPI(A)
Ethernet Switch(B)
(Up to 4-ports
QSGMII/SGMII/RGMII/RMII/
XFI/USXGMII)
1x OSPI or
1x HyperBus(A)(C)
11x UART(F)
1x UART (A)
8x I2C(F)
Automotive Interfaces
Audio Peripherals
18x CAN-FD(E)
3x MCASP
10/100/1000 Ethernet(A)
1x ADC(A)
1x I3C
2x CAN-FD(A)
1x I3C(A)
2x I2C(A)
A. WKUP 和MCU 域实例都位于MCU 岛上，但可供整个系统访问。
B. SGMII、USB3.0 和PCIE 共用总共四个串行器/解串器通道。最多可同时使用三个IP（例如SGMII 和USB）中的两个。
C. 闪存接口可配置为OSPI0 或HyperBus。
D. 一个端口仅在内部连接。未连接到任何引脚。
E. 黑色实线框表示IP 是扩展MCU (eMCU) 的一部分。
F. 黑色虚线框表示IP 的某些实例存在于eMCU 中，而某些实例存在于主域的非eMCU 部分中。
图3-1. 功能方框图
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
7.8 Thermal Resistance Characteristics....................... 108
7.9 Timing and Switching Characteristics..................... 109
8 Detailed Description....................................................225
8.1 Overview.................................................................225
8.2 Processor Subsystems........................................... 226
8.3 Other Subsystems.................................................. 226
9 Applications, Implementation, and Layout............... 233
9.1 Power Supply Mapping...........................................233
9.2 Device Connection and Layout Fundamentals....... 237
9.3 Peripheral- and Interface-Specific Design
Information................................................................ 237
10 Device and Documentation Support........................244
10.1 Device Nomenclature............................................244
10.2 Tools and Software............................................... 248
10.3 Documentation Support........................................ 249
10.4 支持资源................................................................249
10.5 Trademarks...........................................................249
10.6 静电放电警告........................................................ 249
10.7 术语表................................................................... 249
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
3.1 功能方框图..................................................................2
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 7
6 Terminal Configuration and Functions..........................8
6.1 Pin Diagram................................................................ 8
6.2 Pin Attributes...............................................................9
6.3 Signal Descriptions................................................... 47
6.4 Pin Multiplexing.........................................................82
6.5 Connections for Unused Pins................................... 91
7 Specifications................................................................ 94
7.1 Absolute Maximum Ratings...................................... 94
7.2 ESD Ratings............................................................. 96
7.3 Recommended Operating Conditions.......................96
7.4 Power-On-Hours (POH)............................................98
7.5 Operating Performance Points..................................99
7.6 Electrical Characteristics.........................................100
7.7 VPP Specifications for One-Time Programmable
Information.................................................................. 250
11.1 Packaging Information.......................................... 250
(OTP) eFuses............................................................107
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
4 Revision History
Changes from December 17, 2022 to June 30, 2023 (from Revision D (December 2022) to
Revision E (June 2023))
Page
•
（封装信息）：更新/更改了表以便与新的内容标准一致.................................................................................... 2
• (Device Comparison): Updated/Changed the "DRA821U2 CPSW5G supports …" footnote clarifying
options/restrictions..............................................................................................................................................6
• (MAIN Domain/ MMC0 Signal Descriptions): Deleted the external pull-up resistor connection requirements
footnote on the MMC command and data signals for MMC0........................................................................... 72
• (Recommended Operating Conditions): Added clarification to the "…supply inputs" footnote, specifically for
VDD_CORE, VDD_MCU, and VDD_CPU domains plus, added cross-references to the MIN/MAX values....96
• (Operating Performance Points): Added "Supported OPP vs Max Frequency" table to include "OPP_LOW"
and "OPP_NOM" plus footnote cross-references.............................................................................................99
• (MMCSD1 Timing Conditions): Deleted the SRI, Input slew rate specification for UHS-I DDR50 mode........207
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
5 Device Comparison
表5-1 shows the features of the SoC, highlighting the differences.
表5-1. Device Comparison
Same table as the unhidden one. Done to remove columns A4 and A2
FEATURES
REFERENCE NAME
DRA821U4
DRA821U2
Features
PROCESSORS AND ACCELERATORS
Speed Grades (see 表7-1)
T, L, E
Dual Core
Quad Core
Optional(5)
Yes
E, C
Dual Core
Quad Core
Optional(5)
Yes
Arm Cortex-A72 Microprocessor Subsystem
Arm Cortex-R5F
Arm A72
Arm R5F
Lockstep
DMSC
Device Management Security Controller
Security Accelerators
SA
Yes
Yes
SAFETY AND SECURITY
Safety Targeted
Safety
Security
Q1
Optional(5)
Optional(6)
Optional(7)
Optional(5)
Optional(6)
Optional(7)
Device Security
AEC-Q100 Qualified
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain
On-Chip Shared Memory (RAM) in MCU Domain
Multicore Shared Memory Controller
OCSRAM
512KB SRAM
1MB SRAM
512KB SRAM
1MB SRAM
MCU_MSRAM
1MB (On-Chip SRAM 1MB (On-Chip SRAM
with ECC) with ECC)
MSMC
LPDDR4 DDR Subsystem
Up to 8GB (16/32-bit Up to 8GB (16/32-bit
data) with inline ECC data) with inline ECC
DDRSS
SECDED
GPMC
7-bit
7-bit
General-Purpose Memory Controller
PERIPHERALS
Up to 1GB with ECC Up to 1GB with ECC
Modular Controller Area Network Interface with Full CAN-FD Support
Navigator Subsystem
MCAN
NAVSS
GPIO
20
20
2
Up to 141
10
2
Up to 141
10
General-Purpose I/O
Inter-Integrated Circuit Interface
Improved Inter-Integrated Circuit Interface
Analog-to-Digital Converter
I2C
I3C
2
2
ADC
1
1
Multichannel Serial Peripheral Interface
Multichannel Audio Serial Port
MCSPI
MCASP0
MCASP1
MCASP2
MMCSD0
11 (8)
11 (8)
16 Serializers
12 Serializers
6 Serializers
eMMC (8-bits)
16 Serializers
12 Serializers
6 Serializers
eMMC (8-bits)
MultiMedia Card/ Secure Digital Interface
Flash Subsystem (FSS)
SD/SDIO
(4-bits)
SD/SDIO
(4-bits)
MMCSD1
OSPI
HyperBus
PCIE
8-bits(4)
8-bits(4)
Yes(4)
Yes(4)
PCI Express Port with Integrated PHY
Ethernet Interface
Up to Four Lanes(1)
Up to Four Lanes(1)
CPSW2G
CPSW5G
TIMER
1 Port(3)
1 Port(3)
4 Ports (1) (2)
2 Ports(1) (2)
General-Purpose Timers
30
6
30
6
Enhanced Pulse-Width Modulator Module
EPWM
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
6
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表5-1. Device Comparison (continued)
Same table as the unhidden one. Done to remove columns A4 and A2
FEATURES
REFERENCE NAME
DRA821U4
DRA821U2
Enhanced Capture Module
ECAP
EQEP
UART
3
3
3
3
Enhanced Quadrature Encoder Pulse Module
Universal Asynchronous Receiver and Transmitter
12
12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD)
Ports with SS PHY
USB
Yes(1)
Yes(1)
(1) SGMII, USB3.0, and PCIE share total of four SerDes lanes.
(2) DRA821U4 CPSW5G supports the following instances, signals, and modes of operation:
•
PORT1 Signals: RMII1/RGMII1/SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII,
100Mb RMII, 5Gb QSGMII
•
•
•
•
PORT2 Signals: RMII2/RGMII2/SGMII2, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII
PORT3 Signals: RMII3/RGMII3/SGMII3, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII
PORT4 Signals: RMII4/RGMII4/SGMII4, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII
QSGMII mode combines all four internal ports of the CPSW onto a single SERDES lane. Each port in this mode operates at 1-Gb
full duplex
– Any one of the port signals SGMII1:4 can be selected for this SERDES connectivity where upon the non-selected signals are
unused by the CPSW
DRA821U2 CPSW5G supports a maximum of TWO RMIIn/RGMIIn/SGMIIn ports to be used in a system. A system design can choose
any TWO of the available ports between PORT1, PORT2, PORT3, or PORT4. QSGMII is not supported since QSGMII combines all
four internal ports of the CPSW onto a single SERDES lane.
(3) CPSW2G supports the following instances, signals, and modes of operation:
•
PORT1 Signals: MCU_RMII1/MCU_RGMII1, Modes: One of 1Gb RGMII, 100Mb RMII
(4) Flash interface can be configured as OSPI0, or HyperBus.
(5) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the
Device Type (Y) identifier in the 节10.1.2, Nomenclature Description Table.
(6) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as
indicated by the Device Type (Y) identifier in the 节10.1.2, Nomenclature Description table.
(7) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the 节
10.1.2, Nomenclature Description table.
(8) Two ports are internally connected only. Not connected to any pins.
5.1 Related Products
Companion Products for DRA821U Review products that are frequently purchased or used in conjunction with
this product.
Software Development Kit for DRA821 Jacinto™ Processors Processor SDK RTOS (PSDK RTOS) can be
used together with Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX), to form a multi-
processor software development platform for DRA821 SoCs within the TI’s Jacinto™ Processors platform. The
SDK provides a comprehensive set of software tools and components to help users develop and deploy their
applications on supported J7 SoCs. PSDK RTOS and either PSDK Linux or PSDK QNX can be used together to
implement various use-cases in factory and building automation, and gateway systems.
DRA821 Evaluation Module The J700XSOMXEVM paired with the J721EXCP01EVM Common Processor
Board is an evaluation platform designed to speed up development efforts and reduce time to market for
networking applications throughout automotive and industrial markets.
The EVM is supported by Processor SDK, which includes foundational drivers, compute and vision kernels, and
example application frameworks and demonstrations that show you how to take advantage of the powerful,
heterogeneous architecture of Jacinto 7 processors.
Application Notes and White Paper Gateway application processor with integrated system MCU.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6 Terminal Configuration and Functions
6.1 Pin Diagram
备注
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
图 6-1 shows the ball locations for the 433-ball flip chip ball grid array (FCBGA) package that are used in
conjunction with 表6-1 through 表6-107 to locate signal names and ball grid numbers.
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
10 12 14 16 18 20
2
4
6
8
图6-1. ALM FCBGA-N433 Pin Diagram (Bottom View)
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.2 Pin Attributes
表6-1. Pin Attributes
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
DSIS
[13]
[5]
[12]
M7
CAP_VDDS0
CAP_VDDS0
PWR
G14
F9
CAP_VDDS0_MCU
CAP_VDDS1_MCU
CAP_VDDS2
CAP_VDDS0_MCU
CAP_VDDS1_MCU
CAP_VDDS2
PWR
PWR
PWR
PWR
PWR
IO
T12
F10
L15
H1
CAP_VDDS2_MCU
CAP_VDDS5
CAP_VDDS2_MCU
CAP_VDDS5
DDR0_CKN
DDR0_CKN
1.1 V
VDDS_DDR,
DDR
VDDS_DDR_C,
VDDS_DDR_BIAS
G1
J5
DDR0_CKP
DDR0_RESETn
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CAL0
DDR0_CKE0
DDR0_CKE1
DDR0_CKP
DDR0_RESETn
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CAL0
DDR0_CKE0
DDR0_CKE1
IO
IO
IO
IO
IO
IO
IO
IO
A
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
G4
H3
J4
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
K1
J2
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
H5
K5
G2
H2
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDRCALR
DDR
IO
IO
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
DDR
VDDS_DDR_C,
VDDS_DDR_BIAS
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
G3
DDR0_CSn0_0
DDR0_CSn0_0
IO
1.1 V
VDDS_DDR,
DDR
VDDS_DDR_C,
VDDS_DDR_BIAS
K2
G5
J3
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
A3
E4
N1
R4
B4
A4
C4
C1
C3
C2
A2
B3
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
10
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
D1
D2
F2
E3
F3
F4
D4
F5
K4
L4
M4
L3
L2
L1
M3
N2
DDR0_DQ8
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
IO
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
R3
T1
P1
P2
N4
P3
P4
N5
B1
B2
E1
E2
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
IO
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
M1
M2
R1
R2
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
12
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
R5
U3
DDR_RET
DDR_RET
I
1.1 V
VDDS_DDR,
VDDS_DDR_C,
VDDS_DDR_BIAS
DDR
ECAP0_IN_APWM_OUT
ECAP0_IN_APWM_OUT
SYNC0_OUT
CPTS0_RFT_CLK
I2C1_SCL
0
1
2
3
4
5
6
7
0
0
0
7
0
1
3
4
5
6
7
4
5
7
8
IO
O
OFF
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
0
I
I
IOD
I
1
0
1
1
Yes
CPTS0_HW1TSPUSH
UART3_RXD
SPI7_CS0
I
IO
IO
IO
IO
I
GPIO0_58
pad
A13
D12
U6
EMU0
EMU0
OFF
OFF
OFF
0
0
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
I2C OD FS
PU/PD
PU/PD
0/0
0/0
EMU1
EMU1
EXTINTn
EXTINTn
1
Yes
GPIO0_0
IO
I
pad
0
T3
EXT_REFCLK1
EXT_REFCLK1
SYNC1_OUT
I2C1_SDA
OFF
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
PU/PD
PU/PD
O
IOD
I
1
0
CPTS0_HW2TSPUSH
UART3_TXD
SPI7_CLK
Yes
O
IO
IO
O
0
GPIO0_59
pad
U12
GPIO0_41
RGMII2_TX_CTL
RMII2_TXD0
GPIO0_41
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
Yes
O
IO
IO
I
pad
0
SPI6_D1
Yes
UART4_RXD
MCASP2_ACLKX
GPMC0_A13
GPMC0_CLK
USB0_DRVVBUS
RGMII4_RD3
GPIO0_44
11
12
13
0
1
IO
OZ
IO
O
0
U13
GPMC0_CLK
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
0
Yes
1
4
I
0
Yes
Yes
7
IO
IO
I
pad
1
SPI0_CS3
10
11
0
UART9_RXD
I2C0_SCL
1
V3
I2C0_SCL
IOD
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
I2C OD FS
1
GPIO0_56
7
pad
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W2
I2C0_SDA
I2C0_SDA
GPIO0_57
MCAN0_RX
0
7
0
4
6
7
9
IOD
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
I2C OD FS
LVCMOS
1
Yes
Yes
IO
I
pad
1
V20
MCAN0_RX
OFF
7
VDDSHV2
PU/PD
Yes
RGMII4_RD1
MCAN0_RX
GPIO0_10
I
0
I
1
IO
IO
OZ
IO
O
I
pad
0
1/0
EQEP2_S
GPMC0_A2
MCASP0_AXR10
MCAN0_TX
RGMII4_RD0
MCAN0_TX
GPIO0_9
11
12
0
0
0
V18
MCAN0_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
6
O
IO
I
7
pad
0
Yes
1/0
EQEP2_B
9
GPMC0_A1
MCASP0_AXR9
AUDIO_EXT_REFCLK0
MCAN1_RX
RGMII4_RD2
RMII2_TXD1
MCAN1_RX
GPIO0_12
11
12
14
0
OZ
IO
IO
I
0
0
1
0
V16
MCAN1_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
I
5
O
I
6
1
7
IO
IO
IO
IO
I
pad
1
SPI6_CS1
8
Yes
1/0
EQEP2_I
9
0
GPMC0_AD7
UART6_CTSn
MCASP0_AXR12
OBSCLK1
10
11
12
14
0
1
IO
O
0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
14
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W21
MCAN1_TX
MCAN1_TX
0
4
5
6
7
8
9
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII2_TXC
RMII2_TX_EN
MCAN1_TX
O
O
O
IO
IO
O
OZ
IO
I
GPIO0_11
Yes
pad
1/0
SPI6_CS0
1
EHRPWM_SOCA
GPMC0_A3
11
12
0
MCASP0_AXR11
MCAN2_RX
RGMII1_TD1
RMII4_RXD1
MCAN2_RX
GPIO0_14
0
1
Y19
MCAN2_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
O
I
5
0
6
I
1
7
IO
IO
IO
O
O
IO
O
IO
O
O
I
pad
1
SPI5_CS2
8
Yes
1/0
EHRPWM0_B
TRC_DATA2
UART3_TXD
MCASP1_ACLKX
UART9_RTSn
GPMC0_AD9
MCAN2_TX
9
0
10
11
12
13
14
0
0
0
Y18
MCAN2_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII1_TD0
RMII4_RXD0
MCAN2_TX
4
5
0
6
O
IO
IO
IO
O
I
GPIO0_13
7
pad
1
SPI5_CS3
8
Yes
1/0
EHRPWM1_A
TRC_DATA3
UART3_RXD
MCASP1_AFSX
UART9_CTSn
GPMC0_AD8
9
1
10
11
12
13
14
1
0
1
0
IO
I
IO
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W16
MCAN3_RX
MCAN3_RX
RGMII1_TD3
0
4
5
6
7
8
9
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
O
I
RMII4_RX_ER
MCAN3_RX
GPIO0_16
0
1
I
IO
IO
I
pad
1
SPI5_CS0
Yes
Yes
Yes
1/0
1/0
1/0
EHRPWM_TZn_IN0
TRC_DATA0
GPMC0_A4
MCASP0_AXR0
SYNC2_OUT
MCAN3_TX
RGMII1_TD2
RMII4_CRS_DV
MCAN3_TX
GPIO0_15
0
10
11
12
14
0
O
OZ
IO
O
O
O
I
0
0
Y21
MCAN3_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
5
6
O
IO
IO
IO
O
IO
IO
I
7
pad
0
SPI5_D0
8
EHRPWM0_A
TRC_DATA1
MCASP0_AXR1
GPMC0_AD10
MCAN4_RX
RGMII1_TXC
RMII4_TX_EN
MCAN4_RX
GPIO0_18
9
0
10
12
14
0
0
0
1
Y20
MCAN4_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
O
O
I
5
6
1
7
IO
IO
IO
O
IOD
IO
IO
pad
0
SPI5_D1
8
EHRPWM1_B
TRC_DATA4
I2C2_SDA
9
0
10
11
12
14
1
0
0
MCASP0_AXR2
GPMC0_AD12
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
16
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W15
MCAN4_TX
MCAN4_TX
0
4
5
6
7
8
9
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII1_TX_CTL
RMII4_TXD0
MCAN4_TX
O
O
O
IO
IO
I
GPIO0_17
pad
SPI5_CLK
Yes
0
0
1/0
EHRPWM0_SYNCI
TRC_CLK
10
11
12
14
0
O
IOD
IO
IO
I
I2C2_SCL
1
MCASP0_ACLKX
GPMC0_AD11
MCAN5_RX
RGMII3_RD0
RMII3_RXD0
MCAN5_RX
GPIO0_20
0
0
V19
MCAN5_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
4
I
0
5
I
0
6
I
1
7
IO
IOD
I
pad
1
Yes
1/0
I2C3_SCL
8
EHRPWM_TZn_IN5
TRC_DATA21
GPMC0_A5
9
0
10
11
12
0
O
OZ
IO
O
I
MCASP1_AXR7
MCAN5_TX
0
0
V21
MCAN5_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII3_RXC
RMII4_TXD1
MCAN5_TX
4
5
O
O
IO
IO
IO
O
O
IO
O
O
6
GPIO0_19
7
pad
1
SPI5_CS1
8
Yes
1/0
EHRPWM4_B
TRC_DATA17
UART6_RTSn
MCASP0_AXR7
GPMC0_DIR
SYNC3_OUT
9
0
10
11
12
13
14
0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
U14
MCAN6_RX
MCAN6_RX
0
4
5
6
7
9
I
I
I
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
0
0
1
Yes
RGMII3_RD2
RMII3_CRS_DV
MCAN6_RX
GPIO0_22
IO
IO
O
Yes
pad
0
1/0
EHRPWM5_A
TRC_DATA19
MCASP1_AXR5
GPMC0_AD13
MCAN6_TX
10
12
14
0
IO
IO
O
0
0
T13
MCAN6_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII3_RD1
RMII3_RXD1
MCAN6_TX
4
I
0
0
5
I
6
O
GPIO0_21
7
IO
IOD
IO
O
pad
1
Yes
1/0
I2C3_SDA
8
EHRPWM5_B
TRC_DATA20
GPMC0_A6
9
0
10
11
12
0
OZ
IO
I
MCASP1_AXR6
MCAN7_RX
RGMII3_RX_CTL
RMII3_TXD0
MCAN7_RX
GPIO0_24
0
1
0
U15
MCAN7_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
I
5
O
6
I
1
7
IO
IO
IO
O
pad
1
Yes
1/0
SPI3_CS1
8
EHRPWM3_A
TRC_DATA11
MCASP0_AFSR
GPMC0_AD15
9
0
10
12
14
IO
IO
0
0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
18
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
U16
MCAN7_TX
MCAN7_TX
0
4
5
6
7
8
9
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII3_RD3
RMII3_RX_ER
MCAN7_TX
I
0
0
I
O
IO
IO
I
GPIO0_23
pad
1
Yes
1/0
SPI3_CS0
EHRPWM_TZn_IN4
TRC_DATA18
MCASP1_AXR4
GPMC0_AD14
MCAN8_RX
0
10
12
14
0
O
IO
IO
I
0
0
1
U19
MCAN8_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII3_TD1
RMII3_TXD1
MCAN8_RX
4
O
O
I
5
6
1
GPIO0_26
7
IO
IO
O
O
O
IO
OZ
I
pad
1
SPI3_CS3
8
Yes
1/0
EHRPWM3_SYNCO
TRC_DATA14
UART3_RTSn
MCASP0_AXR4
GPMC0_A8
9
10
11
12
13
14
0
0
1
UART0_DSRn
MCAN8_TX
T15
MCAN8_TX
O
OZ
O
O
O
IO
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
GPMC0_A7
3
RGMII3_TD0
RMII3_TX_EN
MCAN8_TX
4
5
6
GPIO0_25
7
pad
1
Yes
1/0
SPI3_CS2
8
EHRPWM_TZn_IN3
TRC_DATA15
UART3_CTSn
MCASP0_AXR5
UART0_DCDn
9
0
10
11
12
14
O
I
1
0
1
IO
I
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
U18
MCAN9_RX
MCAN9_TX
MCAN10_RX
MCAN9_RX
RGMII3_TD3
MCAN9_RX
GPIO0_28
SPI3_D0
0
4
6
7
8
9
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
PU/PD
PU/PD
1
1
Yes
O
I
IO
IO
IO
O
pad
0
Yes
1/0
EHRPWM3_B
TRC_DATA12
MCASP1_ACLKR
GPMC0_A10
MCASP1_AXR11
MCAN9_TX
0
10
12
13
14
0
IO
OZ
IO
O
0
0
T14
OFF
7
VDDSHV2
LVCMOS
Yes
RGMII3_TD2
MCAN9_TX
4
O
6
O
GPIO0_27
7
IO
IO
I
pad
0
SPI3_CLK
8
Yes
1/0
EHRPWM3_SYNCI
TRC_DATA13
MCASP1_AFSR
GPMC0_A9
9
0
10
12
13
14
0
O
IO
OZ
IO
I
0
MCASP1_AXR10
MCAN10_RX
RGMII3_TXC
MCAN10_RX
GPIO0_30
0
1
U20
OFF
7
VDDSHV2
LVCMOS
Yes
4
O
6
I
1
7
IO
IO
IO
O
pad
1
SPI2_CLK
8
EHRPWM4_A
TRC_DATA16
UART2_RTSn
MCASP0_AXR6
GPMC0_BE0n_CLE
GPMC0_A16
9
Yes
0
1/0
10
11
12
13
14
O
IO
O
0
OZ
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
20
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
U17
MCAN10_TX
MCAN10_TX
0
4
6
7
8
9
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII3_TX_CTL
MCAN10_TX
GPIO0_29
O
O
IO
IO
O
O
I
pad
SPI3_D1
0
EHRPWM_SOCB
TRC_DATA10
UART2_CTSn
MCASP0_ACLKR
GPMC0_WAIT1
GPMC0_A22
MCAN11_RX
RGMII2_RD0
MCAN11_RX
GPIO0_32
Yes
Yes
Yes
1/0
1/0
1/0
10
11
12
13
14
0
1
0
0
IO
I
OZ
I
Y13
MCAN11_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
4
I
0
6
I
1
7
IO
IO
I
pad
1
SPI2_CS1
8
EQEP0_B
9
0
UART3_TXD
MCASP0_AXR14
GPMC0_A12
UART0_RIn
MCAN11_TX
RGMII2_RXC
MCAN11_TX
GPIO0_31
11
12
13
14
0
O
IO
OZ
I
0
1
0
Y14
MCAN11_TX
O
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
6
O
IO
IO
I
7
pad
1
SPI2_CS0
8
EQEP0_A
9
0
SPI0_CS2
10
11
12
13
14
IO
I
1
UART3_RXD
MCASP0_AXR13
GPMC0_A11
UART0_DTRn
1
IO
OZ
O
0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
AA14
MCAN12_RX
MCAN12_TX
MCAN13_RX
MCAN12_RX
0
4
6
7
8
9
I
I
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
PU/PD
PU/PD
1
0
1
Yes
RGMII2_RD2
MCAN12_RX
GPIO0_34
IO
IO
I
pad
1
SPI2_CS3
EQEP1_B
Yes
0
1/0
I2C6_SDA
10
11
12
13
14
0
IOD
O
1
UART2_TXD
MCASP1_AXR8
I3C0_SDAPULLEN
GPMC0_A18
MCAN12_TX
RGMII2_RD1
MCAN12_TX
GPIO0_33
IO
OD
OZ
O
0
0
AA15
OFF
7
VDDSHV2
LVCMOS
Yes
4
I
6
O
7
IO
IO
I
pad
1
SPI2_CS2
8
EQEP1_A
9
Yes
0
1/0
I2C6_SCL
10
11
12
13
14
0
IOD
I
1
UART2_RXD
MCASP0_AXR15
GPMC0_BE1n
GPMC0_A17
MCAN13_RX
RGMII2_RX_CTL
GPMC0_CSn3
MCAN13_RX
GPIO0_36
1
IO
O
0
OZ
I
AA16
OFF
7
VDDSHV2
LVCMOS
1
0
Yes
4
I
5
O
6
I
1
7
IO
IO
IO
IOD
O
pad
0
SPI2_D1
8
Yes
1/0
EQEP0_I
9
0
I2C5_SDA
10
11
12
13
14
1
UART8_RTSn
MCASP2_AXR0
I3C0_SDA
IO
IO
OZ
0
1
GPMC0_A20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
22
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
AA18
MCAN13_TX
MCAN13_TX
0
4
5
6
7
8
9
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RGMII2_RD3
GPMC0_WPn
MCAN13_TX
GPIO0_35
I
0
O
O
IO
IO
IO
IOD
I
pad
0
SPI2_D0
Yes
1/0
EQEP0_S
0
I2C5_SCL
10
11
12
13
14
0
1
UART8_CTSn
MCASP1_AXR9
I3C0_SCL
1
IO
IO
OZ
I
0
1
GPMC0_A19
MCAN15_RX
RGMII2_TD1
RMII2_RXD1
GPIO0_38
W20
MCAN15_RX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
4
O
5
I
0
7
IO
IO
IO
I
pad
1
SPI6_CS3
8
Yes
1/0
EQEP1_I
9
0
MCAN15_RX
MCASP2_AXR2
GPMC0_A15
GPMC0_ADVn_ALE
MCAN15_TX
RGMII2_TD0
RMII2_RXD0
GPIO0_37
10
12
13
14
0
1
IO
OZ
O
0
W17
MCAN15_TX
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
O
5
I
0
7
IO
IO
IO
O
pad
1
SPI6_CS2
8
EQEP1_S
9
Yes
0
1/0
MCAN15_TX
GPMC0_CSn2
MCASP2_AXR1
GPMC0_A0
GPMC0_A21
10
11
12
13
14
O
IO
OZ
OZ
0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
U21
MCAN16_RX
MCAN16_RX
0
1
4
7
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
CLKOUT
OZ
O
RGMII4_TD0
GPIO0_46
IO
I
Yes
pad
1
1/0
UART7_RXD
12
13
14
0
GPMC0_CSn1
O
AUDIO_EXT_REFCLK1
MCAN16_TX
IO
O
0
V15
MCAN16_TX
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
RMII_REF_CLK
RGMII4_RX_CTL
GPIO0_45
1
I
0
4
I
0
Yes
1/0
7
IO
O
pad
UART7_TXD
12
13
0
GPMC0_A14
OZ
A
H17
K18
M17
L18
J18
J17
K17
L17
G21
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
MCU_I2C0_SCL
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
MCU_I2C0_SCL
WKUP_GPIO0_66
MCU_I2C0_SDA
WKUP_GPIO0_67
MCU_MCAN0_RX
WKUP_GPIO0_63
MCU_MCAN0_TX
WKUP_GPIO0_62
MCU_MDIO0_MDC
WKUP_GPIO0_55
MCU_MDIO0_MDIO
WKUP_GPIO0_54
MCU_OSPI0_CLK
MCU_HYPERBUS0_CK
WKUP_GPIO0_16
0
0
0
0
0
0
0
0
0
1.8 V
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDA_ADC_MCU
VDDSHV0_MCU
ADC12BT
ADC12BT
ADC12BT
ADC12BT
ADC12BT
ADC12BT
ADC12BT
ADC12BT
I2C OD FS
0
A
1.8 V
0
A
1.8 V
0
A
1.8 V
0
A
1.8 V
0
A
1.8 V
0
A
1.8 V
0
A
1.8 V
0
IOD
IO
IOD
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1.8 V/3.3 V
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
pad
1
G20
A17
A16
D9
MCU_I2C0_SDA
0
0
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV1_MCU
I2C OD FS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
7
pad
0
MCU_MCAN0_RX
MCU_MCAN0_TX
MCU_MDIO0_MDC
MCU_MDIO0_MDIO
MCU_OSPI0_CLK
0
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
1/0
1/0
1/0
1/0
7
IO
O
pad
0
7
IO
O
pad
0
7
IO
IO
IO
O
pad
0
C9
0
7
pad
B6
0
1
O
Yes
7
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
24
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
B7
C8
D6
D7
C6
MCU_OSPI0_DQS
MCU_OSPI0_LBCLKO
MCU_OSPI0_CSn0
MCU_OSPI0_CSn1
MCU_OSPI0_CSn2
MCU_OSPI0_DQS
0
1
7
0
1
7
0
1
7
0
1
7
0
1
2
3
4
6
7
0
1
2
3
5
6
7
0
1
7
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1_MCU
VDDSHV1_MCU
VDDSHV1_MCU
VDDSHV1_MCU
VDDSHV1_MCU
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
MCU_HYPERBUS0_RWDS
WKUP_GPIO0_18
IO
IO
IO
O
IO
O
O
IO
O
O
IO
O
O
I
Yes
Yes
Yes
Yes
pad
0
MCU_OSPI0_LBCLKO
MCU_HYPERBUS0_CKn
WKUP_GPIO0_17
OFF
OFF
OFF
OFF
7
7
7
7
LVCMOS
LVCMOS
LVCMOS
LVCMOS
pad
pad
pad
I
MCU_OSPI0_CSn0
MCU_HYPERBUS0_CSn0
WKUP_GPIO0_27
1/0
1/0
MCU_OSPI0_CSn1
MCU_HYPERBUS0_RESETn
WKUP_GPIO0_28
MCU_OSPI0_CSn2
MCU_OSPI0_CSn2
MCU_HYPERBUS0_RESETOn
MCU_HYPERBUS0_WPn
MCU_HYPERBUS0_CSn1
MCU_OSPI0_RESET_OUT0
WKUP_GPIO0_30
O
O
O
IO
O
O
I
Yes
pad
D5
MCU_OSPI0_CSn3
MCU_OSPI0_CSn3
OFF
7
1.8 V/3.3 V
VDDSHV1_MCU
LVCMOS
PU/PD
MCU_OSPI0_CSn3
MCU_HYPERBUS0_INTn
MCU_HYPERBUS0_WPn
MCU_OSPI0_RESET_OUT1
MCU_OSPI0_ECC_FAIL
WKUP_GPIO0_31
I
O
O
I
Yes
1
IO
IO
IO
IO
I
pad
0
D8
C7
MCU_OSPI0_D0
MCU_OSPI0_D1
MCU_OSPI0_D0
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1_MCU
VDDSHV1_MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_HYPERBUS0_DQ0
WKUP_GPIO0_19
0
Yes
Yes
1/0
1/0
pad
BOOTMODE00
Bootstrap
MCU_OSPI0_D1
0
IO
IO
IO
I
0
MCU_HYPERBUS0_DQ1
WKUP_GPIO0_20
1
0
7
pad
BOOTMODE01
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
C5
A5
A6
MCU_OSPI0_D2
MCU_OSPI0_D2
0
1
7
0
1
7
0
1
7
IO
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1_MCU
VDDSHV1_MCU
VDDSHV1_MCU
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
MCU_HYPERBUS0_DQ2
WKUP_GPIO0_21
MCU_OSPI0_D3
IO
IO
IO
IO
IO
IO
IO
IO
I
Yes
Yes
1/0
1/0
pad
0
MCU_OSPI0_D3
MCU_OSPI0_D4
OFF
OFF
7
7
LVCMOS
LVCMOS
MCU_HYPERBUS0_DQ3
WKUP_GPIO0_22
MCU_OSPI0_D4
0
pad
0
MCU_HYPERBUS0_DQ4
WKUP_GPIO0_23
BOOTMODE02
0
Yes
1/0
1/0
pad
Bootstrap
B8
MCU_OSPI0_D5
MCU_OSPI0_D5
0
IO
IO
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV1_MCU
LVCMOS
PU/PD
0
MCU_HYPERBUS0_DQ5
WKUP_GPIO0_24
BOOTMODE03
1
0
Yes
Yes
7
pad
Bootstrap
A8
A7
MCU_OSPI0_D6
MCU_OSPI0_D7
MCU_OSPI0_D6
0
1
7
0
1
7
IO
IO
IO
IO
IO
IO
I
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1_MCU
VDDSHV1_MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
0
MCU_HYPERBUS0_DQ6
WKUP_GPIO0_25
MCU_OSPI0_D7
0
1/0
1/0
pad
0
MCU_HYPERBUS0_DQ7
WKUP_GPIO0_26
MCU_PORz
Yes
Yes
0
pad
G19
B13
MCU_PORz
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
FS RESET
LVCMOS
MCU_RESETSTATz
MCU_RESETSTATz
WKUP_GPIO0_79
MCU_RESETz
0
7
0
0
1
7
0
1
7
0
1
7
0
1
7
O
IO
I
PD
0
1.8 V/3.3 V
VDDSHV0_MCU
PU/PD
Yes
Yes
pad
A18
B10
MCU_RESETz
0
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV2_MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_RGMII1_RXC
MCU_RGMII1_RXC
MCU_RMII1_REF_CLK
WKUP_GPIO0_49
MCU_RGMII1_RX_CTL
MCU_RMII1_RX_ER
WKUP_GPIO0_43
MCU_RGMII1_TXC
MCU_RMII1_TX_EN
WKUP_GPIO0_48
MCU_RGMII1_TX_CTL
MCU_RMII1_CRS_DV
WKUP_GPIO0_29
I
OFF
OFF
OFF
OFF
0
I
Yes
Yes
Yes
Yes
0
1/0
1/0
1/0
1/0
IO
I
pad
0
A11
A12
D11
MCU_RGMII1_RX_CTL
MCU_RGMII1_TXC
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
I
0
IO
O
O
IO
O
I
pad
pad
MCU_RGMII1_TX_CTL
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
26
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
A9
MCU_RGMII1_RD0
MCU_RGMII1_RD1
MCU_RGMII1_RD2
MCU_RGMII1_RD3
MCU_RGMII1_TD0
MCU_RGMII1_TD1
MCU_RGMII1_TD2
MCU_RGMII1_RD0
MCU_RMII1_RXD0
WKUP_GPIO0_53
MCU_RGMII1_RD1
MCU_RMII1_RXD1
WKUP_GPIO0_52
MCU_RGMII1_RD2
MCU_TIMER_IO5
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
3
7
0
1
3
7
0
I
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
VDDSHV2_MCU
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
Yes
Yes
Yes
Yes
Yes
Yes
1/0
1/0
1/0
1/0
1/0
1/0
IO
I
pad
0
B9
OFF
OFF
OFF
OFF
OFF
OFF
7
7
7
7
7
7
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
I
0
IO
I
pad
0
A10
C10
D10
B11
B12
IO
IO
I
0
WKUP_GPIO0_51
MCU_RGMII1_RD3
MCU_TIMER_IO4
pad
0
IO
IO
O
O
IO
O
O
IO
O
IO
I
0
WKUP_GPIO0_50
MCU_RGMII1_TD0
MCU_RMII1_TXD0
WKUP_GPIO0_47
MCU_RGMII1_TD1
MCU_RMII1_TXD1
WKUP_GPIO0_46
MCU_RGMII1_TD2
MCU_TIMER_IO3
pad
pad
pad
0
Yes
Yes
1/0
1/0
MCU_ADC_EXT_TRIGGER1
WKUP_GPIO0_45
MCU_RGMII1_TD3
MCU_TIMER_IO2
0
IO
O
IO
I
pad
C12
MCU_RGMII1_TD3
OFF
7
1.8 V/3.3 V
VDDSHV2_MCU
LVCMOS
PU/PD
0
MCU_ADC_EXT_TRIGGER0
WKUP_GPIO0_44
MCU_SAFETY_ERRORn
0
IO
IO
pad
G18
C13
MCU_SAFETY_ERRORn
MCU_SPI0_CLK
OFF
OFF
0
7
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
LVCMOS
LVCMOS
PU/PD
PU/PD
Yes
Yes
MCU_SPI0_CLK
0
7
IO
IO
I
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
0
Yes
WKUP_GPIO0_56
MCU_BOOTMODE00
MCU_SPI0_CS0
pad
1/0
1/0
1/0
Bootstrap
A19
A20
MCU_SPI0_CS0
MCU_SPI0_D0
0
IO
IO
IO
IO
IO
I
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
LVCMOS
LVCMOS
PU/PD
PU/PD
1
Yes
Yes
MCU_TIMER_IO1
WKUP_GPIO0_59
MCU_SPI0_D0
4
Yes
Yes
0
7
pad
0
0
WKUP_GPIO0_57
MCU_BOOTMODE01
7
pad
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
B17
MCU_SPI0_D1
MCU_SPI0_D1
0
4
7
IO
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
LVCMOS
PU/PD
0
0
Yes
MCU_TIMER_IO0
WKUP_GPIO0_58
MCU_BOOTMODE02
MMC0_CALPAD
IO
IO
I
Yes
1/0
pad
Bootstrap
P20
P18
R17
P19
P21
MMC0_CALPAD
MMC0_CLK
MMC0_CMD
MMC0_DS
A
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
eMMCPHY
eMMCPHY
eMMCPHY
eMMCPHY
SDIO
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
MMC0_CLK
MMC0_CMD
MMC0_DS
O
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
IO
IO
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
1
1
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
MMC1_CLK
MMC1_CLK
UART8_RXD
TIMER_IO4
UART4_CTSn
GPIO0_66
0
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV5
0
1
1
3
IO
I
0
5
1
Yes
7
IO
IO
O
pad
0
SPI1_CLK
8
UART0_RTSn
I2C6_SDA
9
10
0
IOD
IO
O
1
1
M20
MMC1_CMD
MMC1_CMD
UART8_TXD
TIMER_IO5
UART4_RTSn
GPIO0_67
OFF
7
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
1
3
IO
O
0
5
Yes
7
IO
IO
IOD
IO
pad
0
SPI1_D1
8
I2C6_SCL
10
1
R16
P17
R18
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT0
1.8 V
1.8 V
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
eMMCPHY
eMMCPHY
eMMCPHY
PU/PD
PU/PD
PU/PD
1
MMC0_DAT1
MMC0_DAT2
IO
IO
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
1
1
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
28
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
R20
R19
P16
R21
T21
M19
MMC0_DAT3
MMC0_DAT3
IO
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
eMMCPHY
eMMCPHY
eMMCPHY
eMMCPHY
eMMCPHY
SDIO
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
1
1
1
1
1
1
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
MMC1_DAT0
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
IO
IO
IO
IO
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
1.8 V
VDDS_MMC0,
VDDA_0P8_DLL_MM
C0
MMC1_DAT0
UART7_RTSn
ECAP1_IN_APWM_OUT
TIMER_IO3
0
1
2
3
5
7
8
9
IO
O
OFF
7
1.8 V/3.3 V
VDDSHV5
IO
IO
O
IO
0
UART4_TXD
GPIO0_65
Yes
IO
IO
O
pad
0
SPI1_D0
UART5_RTSn
I2C4_SCL
10
11
0
IOD
O
1
UART2_TXD
MMC1_DAT1
UART7_CTSn
ECAP0_IN_APWM_OUT
TIMER_IO2
N21
MMC1_DAT1
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
1
1
1
2
IO
IO
I
IO
0
3
UART4_RXD
GPIO0_64
5
1
Yes
7
IO
IO
I
pad
1
SPI1_CS2
8
UART5_CTSn
I2C4_SDA
9
1
10
11
IOD
I
1
UART2_RXD
1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
N20
MMC1_DAT2
MMC1_DAT2
0
1
3
7
8
9
IO
OFF
7
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
1
0
UART7_TXD
TIMER_IO1
O
IO
IO
IO
O
GPIO0_63
pad
1
Yes
SPI1_CS1
CPTS0_TS_SYNC
I2C3_SDA
10
11
0
IOD
O
1
UART5_TXD
MMC1_DAT3
UART7_RXD
PCIE1_CLKREQn
TIMER_IO0
N19
MMC1_DAT3
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
1
1
1
2
IO
IO
IO
IO
I
IO
0
3
GPIO0_62
7
Yes
pad
1
SPI1_CS0
8
UART0_CTSn
I2C3_SCL
9
1
10
11
IOD
I
1
UART5_RXD
OSC1_XI
1
K19
J19
C15
OSC1_XI
I
1.8 V
VDDA_OSC1
VDDA_OSC1
VDDSHV0_MCU
Yes
Yes
HFOSC
HFOSC
LVCMOS
OSC1_XO
OSC1_XO
O
1.8 V
PMIC_POWER_EN1
PMIC_WAKE0n
PORz
PMIC_POWER_EN1
MCU_I3C0_SDAPULLEN
WKUP_GPIO0_68
PMIC_WAKE0n
RGMII4_TD1
GPIO0_1
0
5
7
0
4
7
0
O
OFF
OFF
7
7
0
1.8 V/3.3 V
PU/PD
PU/PD
Yes
OD
IO
OD
O
Yes
pad
pad
T19
H20
1.8 V/3.3 V
VDDSHV2
LVCMOS
Yes
Yes
IO
I
PORz
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
FS RESET
U2
RESETSTATz
RESET_REQz
RESETSTATz
RESET_REQz
0
0
O
I
PD
0
0
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
A15
OFF
VDDSHV0_MCU
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
30
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
AA20
RMII1_CRS_DV
RMII1_CRS_DV
0
4
5
7
9
I
I
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
0
Yes
RGMII1_RD2
RMII1_CRS_DV
GPIO0_4
IO
IO
O
O
IO
IO
I
pad
0
EHRPWM2_B
TRC_DATA7
UART4_TXD
MCASP1_AXR1
GPMC0_AD2
RMII1_RX_ER
RGMII1_RD3
RMII1_RX_ER
GPIO0_5
Yes
Yes
Yes
Yes
1/0
1/0
1/0
1/0
10
11
12
14
0
0
0
Y17
RMII1_RX_ER
OFF
OFF
OFF
7
7
7
VDDSHV2
VDDSHV2
VDDSHV2
LVCMOS
LVCMOS
LVCMOS
0
Yes
Yes
Yes
4
I
0
5
I
0
7
IO
IO
O
O
IO
IO
O
I
pad
0
EHRPWM2_A
TRC_DATA6
UART6_TXD
MCASP1_AXR0
GPMC0_AD3
RMII1_TX_EN
RGMII4_RXC
RMII1_TX_EN
GPIO0_7
9
10
11
12
14
0
0
0
V17
RMII1_TX_EN
4
0
5
O
IO
I
7
pad
0
EQEP2_A
9
UART9_TXD
MCASP0_AXR8
I2C1_SCL
11
12
13
14
0
O
IO
IOD
IO
I
0
1
0
0
0
0
GPMC0_AD5
RMII1_RXD0
RGMII1_RD0
RMII1_RXD0
MCAN14_TX
GPIO0_2
AA17
RMII1_RXD0
4
I
5
I
6
O
IO
O
O
IO
IO
7
pad
TRC_DATA9
UART5_TXD
MCASP1_AXR3
GPMC0_AD0
10
11
12
14
0
0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
Y15
RMII1_RXD1
RMII1_RXD1
0
4
5
6
7
9
I
I
I
I
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
0
0
0
1
Yes
RGMII1_RD1
RMII1_RXD1
MCAN14_RX
GPIO0_3
IO
I
pad
0
Yes
Yes
Yes
1/0
1/0
1/0
EHRPWM_TZn_IN2
TRC_DATA8
UART5_RXD
MCASP1_AXR2
GPMC0_AD1
RMII1_TXD0
RGMII1_RX_CTL
RMII1_TXD0
GPIO0_6
10
11
12
14
0
O
I
1
0
0
IO
IO
O
I
Y16
RMII1_TXD0
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
0
5
O
IO
O
O
I
7
pad
EHRPWM0_SYNCO
TRC_CTL
9
10
11
12
14
0
UART6_RXD
MCASP0_AFSX
GPMC0_AD4
RMII1_TXD1
RGMII1_RXC
RMII1_TXD1
GPIO0_8
1
0
0
IO
IO
O
I
AA19
RMII1_TXD1
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
0
5
O
IO
I
7
pad
0
EHRPWM_TZn_IN1
TRC_DATA5
UART9_RXD
MCASP0_AXR3
I2C1_SDA
9
10
11
12
13
14
O
I
1
0
1
0
IO
IOD
IO
A
GPMC0_AD6
SERDES0_REXT
V7
SERDES0_REXT
0.8 V
VDDA_0P8_SERDES0
SERDES
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
32
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
AA8
AA9
AA11
SERDES0_REFCLK_N
SERDES0_REFCLK_P
SERDES0_RX0_N
SERDES0_REFCLK_N
SERDES0_REFCLK_P
SERDES0_RX0_N
IO
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
IO
0.8 V
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SERDES
I
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII3_RX0_N
PCIE1_RX0_N
I
I
I
I
USB0_SSRX1N
SERDES0_RX0_P
AA12
SERDES0_RX0_P
SERDES0_RX1_N
SERDES0_RX1_P
0.8 V
0.8 V
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SERDES
SERDES
SGMII3_RX0_P
PCIE1_RX0_P
I
I
I
I
USB0_SSRX1P
SERDES0_RX1_N
W8
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII4_RX0_N
PCIE1_RX1_N
I
I
I
I
USB0_SSRX2N
SERDES0_RX1_P
W9
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII4_RX0_P
PCIE1_RX1_P
USB0_SSRX2P
I
I
I
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
Y7
SERDES0_RX2_N
SERDES0_RX2_P
SERDES0_RX3_N
SERDES0_RX3_P
SERDES0_TX0_N
SERDES0_RX2_N
I
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII1_RX0_N
PCIE1_RX2_N
I
I
I
I
USB0_SSRX1N
SERDES0_RX2_P
Y8
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SERDES
SERDES
SERDES
SGMII1_RX0_P
PCIE1_RX2_P
I
I
I
I
USB0_SSRX1P
SERDES0_RX3_N
W5
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII2_RX0_N
PCIE1_RX3_N
I
I
I
I
USB0_SSRX2N
SERDES0_RX3_P
W6
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII2_RX0_P
PCIE1_RX3_P
I
I
I
USB0_SSRX2P
SERDES0_TX0_N
W11
O
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII3_TX0_N
PCIE1_TX0_N
USB0_SSTX1N
O
O
O
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
34
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W12
Y10
Y11
AA5
AA6
SERDES0_TX0_P
SERDES0_TX0_P
O
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII3_TX0_P
PCIE1_TX0_P
O
O
O
O
USB0_SSTX1P
SERDES0_TX1_N
SERDES0_TX1_N
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SERDES
SERDES
SERDES
SGMII4_TX0_N
PCIE1_TX1_N
O
O
O
O
USB0_SSTX2N
SERDES0_TX1_P
SERDES0_TX1_P
SERDES0_TX2_N
SERDES0_TX2_P
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII4_TX0_P
PCIE1_TX1_P
O
O
O
O
USB0_SSTX2P
SERDES0_TX2_N
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII1_TX0_N
PCIE1_TX2_N
O
O
O
O
USB0_SSTX1N
SERDES0_TX2_P
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII1_TX0_P
PCIE1_TX2_P
USB0_SSTX1P
O
O
O
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
Y4
SERDES0_TX3_N
SERDES0_TX3_N
O
0.8 V
VDDA_0P8_SERDES0
SERDES
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII2_TX0_N
PCIE1_TX3_N
O
O
O
O
USB0_SSTX2N
SERDES0_TX3_P
Y5
SERDES0_TX3_P
0.8 V
VDDA_0P8_SERDES0
SERDES
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SGMII2_TX0_P
PCIE1_TX3_P
USB0_SSTX2P
SOC_SAFETY_ERRORn
SPI0_CLK
O
O
O
V2
Y1
SOC_SAFETY_ERRORn
SPI0_CLK
0
0
1
2
7
0
2
7
0
1
2
7
0
1
2
7
0
7
0
0
0
IO
IO
I
OFF
0
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
OFF
7
0
1
UART1_CTSn
I2C2_SCL
IOD
IO
IO
I
IOD
pad
1
GPIO0_53
W3
U5
SPI0_CS0
SPI0_CS1
SPI0_CS0
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
LVCMOS
LVCMOS
PU/PD
PU/PD
UART0_CTSn
GPIO0_51
Yes
Yes
I
IO
IO
O
pad
1
SPI0_CS1
CPTS0_TS_COMP
UART0_RTSn
GPIO0_52
O
O
IO
IO
O
pad
0
V4
T5
SPI0_D0
SPI0_D1
SPI0_D0
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
LVCMOS
LVCMOS
PU/PD
PU/PD
UART1_RTSn
I2C2_SDA
Yes
Yes
IOD
IO
IO
IO
I
IOD
pad
0
GPIO0_54
SPI0_D1
GPIO0_55
pad
B15
F19
F21
TCK
TDI
TCK
0
0
0
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
TDI
I
OFF
OFF
TDO
TDO
OZ
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
36
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
V1
TIMER_IO0
TIMER_IO0
0
1
2
5
6
7
8
0
1
2
5
6
7
8
9
0
0
0
4
7
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
0
0
O
1
0
ECAP1_IN_APWM_OUT
SYSCLKOUT0
UART3_CTSn
SPI7_D0
IO
O
I
Yes
IO
IO
I
GPIO0_60
pad
1
MMC1_SDCD
TIMER_IO1
W1
TIMER_IO1
IO
IO
O
O
IO
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
0
ECAP2_IN_APWM_OUT
OBSCLK0
0
O
UART3_RTSn
SPI7_D1
Yes
0/0
0
GPIO0_61
pad
1
MMC1_SDWP
PCIE1_CLKREQn
TMS
IO
I
0
U4
TMS
OFF
OFF
0
0
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
B20
T16
TRSTn
TRSTn
I
VDDSHV0_MCU
VDDSHV2
UART0_RXD
UART0_RXD
RGMII4_TXC
GPIO0_47
I
1
Yes
O
IO
I
Yes
Yes
0/0
pad
0
GPMC0_WAIT0
UART0_TXD
RGMII4_TD2
GPIO0_48
14
0
T17
T18
UART0_TXD
UART1_RXD
O
O
IO
O
I
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
LVCMOS
LVCMOS
PU/PD
PU/PD
Yes
Yes
4
7
pad
1
GPMC0_WEn
UART1_RXD
MCAN17_TX
TIMER_IO6
14
0
1
O
IO
O
IO
O
3
0
Yes
RGMII4_TD3
GPIO0_49
4
7
pad
GPMC0_OEn_REn
14
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
T20
UART1_TXD
UART1_TXD
0
1
3
4
7
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
MCAN17_RX
TIMER_IO7
I
1
0
IO
O
IO
O
I
Yes
RGMII4_TX_CTL
GPIO0_50
pad
1
GPMC0_CSn0
UART2_RXD
RGMII2_TD2
RMII2_CRS_DV
GPIO0_39
14
0
V14
UART2_RXD
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
O
I
5
0
7
IO
IO
O
O
I
pad
0
SPI6_CLK
8
Yes
0/0
GPMC0_CLKOUT
GPMC0_FCLK_MUX
UART2_RXD
MCASP2_AXR3
OBSCLK2
9
10
11
12
14
0
1
0
IO
O
O
O
I
V13
UART2_TXD
UART2_TXD
RGMII2_TD3
RMII2_RX_ER
GPIO0_40
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
4
5
0
7
IO
IO
O
IO
I
Yes
pad
0
SPI6_D0
8
UART2_TXD
MCASP2_AFSX
UART8_RXD
I2C4_SCL
11
12
0
0
W14
UART8_RXD
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
1
Yes
2
IOD
IO
IO
O
I
IOD
0
MDIO0_MDIO
GPIO0_42
5
7
pad
Yes
TRC_DATA22
UART8_RXD
MCASP2_AFSR
MCASP2_AXR4
10
11
12
13
1
0
0
IO
IO
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
38
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
W19
UART8_TXD
UART8_TXD
SPI1_CS3
I2C4_SDA
0
1
2
5
7
O
OFF
7
1.8 V/3.3 V
VDDSHV2
LVCMOS
PU/PD
Yes
IO
IOD
O
1
IOD
MDIO0_MDC
GPIO0_43
IO
O
Yes
pad
TRC_DATA23
UART8_TXD
MCASP2_ACLKR
MCASP2_AXR5
USB0_DM
10
11
12
13
O
IO
IO
IO
0
0
AA3
AA2
USB0_DM
USB0_DP
3.3 V
3.3 V
VDDA_0P8_USB ,VD
DA_1P8_USB,
VDDA_3P3_USB
USB2PHY
USB2PHY
USB0_DP
IO
VDDA_0P8_USB ,VD
DA_1P8_USB,
VDDA_3P3_USB
T4
V6
USB0_DRVVBUS
USB0_ID
USB0_DRVVBUS
GPIO0_68
0
7
O
IO
A
OFF
7
1.8 V/3.3 V
3.3 V
VDDSHV0
LVCMOS
PU/PD
Yes
pad
USB0_ID
VDDA_0P8_USB ,VD
DA_1P8_USB,
USB2PHY
VDDA_3P3_USB
V5
Y2
USB0_RCALIB
USB0_VBUS
USB0_RCALIB
USB0_VBUS
IO
A
3.3 V
5.0 V
VDDA_0P8_USB ,VD
DA_1P8_USB,
VDDA_3P3_USB
USB2PHY
USB2PHY
VDDA_0P8_USB ,VD
DA_1P8_USB,
VDDA_3P3_USB
K14, P14
J11, M10
H12, J14
K7
VDDAR_CORE
VDDAR_CORE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDDAR_CPU
VDDAR_CPU
VDDAR_MCU
VDDAR_MCU
VDDA_0P8_PLL_DDR
VDDA_0P8_USB
VDDA_0P8_PLL_DDR
VDDA_0P8_USB
P7
M18
VDDA_0P8_DLL_MMC0
VDDA_0P8_SERDES0
VDDA_0P8_SERDES0_C
VDDA_1P8_USB
VDDA_0P8_DLL_MMC0
VDDA_0P8_SERDES0
VDDA_0P8_SERDES0_C
VDDA_1P8_USB
R8, T7, U8
R9
R6
P8
VDDA_1P8_SERDES0
VDDA_3P3_USB
VDDA_1P8_SERDES0
VDDA_3P3_USB
R7
J16
VDDA_ADC_MCU
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
VDDA_ADC_MCU
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
F15
F16
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
G17
VDDA_OSC1
VDDA_OSC1
PWR
N14
N9
VDDA_PLLGRP0
VDDA_PLLGRP4
VDDA_PLLGRP6
VDDA_PLLGRP8
VDDA_POR_WKUP
VDDA_TEMP0
VDDA_TEMP1
VDDA_WKUP
VDDA_PLLGRP0
VDDA_PLLGRP4
VDDA_PLLGRP6
VDDA_PLLGRP8
VDDA_POR_WKUP
VDDA_TEMP0
VDDA_TEMP1
VDDA_WKUP
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
J9
L7
J15
J8
P15
H16
N6, P6
VDDSHV0
VDDSHV0
E13, E14, F13, VDDSHV0_MCU
F14
VDDSHV0_MCU
E7, E8, F8
VDDSHV1_MCU
VDDSHV2
VDDSHV1_MCU
VDDSHV2
PWR
PWR
PWR
PWR
PWR
T10, U11, U9
F11, F12, G11 VDDSHV2_MCU
K16, L16 VDDSHV5
VDDSHV2_MCU
VDDSHV5
A1, G7, H6, J7, VDDS_DDR
K6, M5, U1
VDDS_DDR
F7, L6
J6
VDDS_DDR_BIAS
VDDS_DDR_BIAS
VDDS_DDR_C
VDDS_MMC0
VDD_CORE
PWR
PWR
PWR
PWR
VDDS_DDR_C
VDDS_MMC0
M16, N16
H8, K12, L13, VDD_CORE
M12, M14,
N13, N15, N7,
P10, P12, R11,
R13, R15
J10, L11, M9,
N11, N8
VDD_CPU
VDD_CPU
VDD_MCU
PWR
PWR
G9, H10, H14, VDD_MCU
J13, K15
G13
P11
G15
D16
E17
F17
L14
N17
E11
VDD_MCU_WAKE1
VDD_MCU_WAKE1
VDD_WAKE0
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDD_WAKE0
VMON1_ER_VSYS
VMON2_IR_VCPU
VMON3_IR_VEXT1P8
VMON4_IR_VEXT1P8
VMON5_IR_VEXT3P3
VPP_CORE
VMON1_ER_VSYS
VMON2_IR_VCPU
VMON3_IR_VEXT1P8
VMON4_IR_VEXT1P8
VMON5_IR_VEXT3P3
VPP_CORE
VPP_MCU
VPP_MCU
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
40
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
B5,AA1, AA10, VSS
AA13, AA4,
VSS
GND
AA7, C11,
D15, D17, D3,
E10, E12, E15,
E16, E6, E9,
F1, G10, G12,
G16, G6, G8,
H11, H13, H15,
H19, H4, H7,
H9, J1, J12,
J21, K11, K13,
K3, L12, L19,
L5, M11, M13,
M15, M21, M6,
M8, N10, N12,
N3, P13, P5,
P9, R10, R12,
R14, T11, T2,
T6, T8, T9,
U10, U7, V11,
V12, V9, W10,
W13, W18,
W4, W7, Y12,
Y3, Y6, Y9
B18
B19
D14
WKUP_GPIO0_0
MCU_SPI1_CLK
MCU_SPI1_CLK
WKUP_GPIO0_0
MCU_BOOTMODE03
MCU_SPI1_D0
0
1
7
IO
IO
IO
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
Yes
Yes
Yes
pad
Bootstrap
WKUP_GPIO0_1
0
IO
IO
IO
I
OFF
OFF
7
7
LVCMOS
LVCMOS
0
Yes
Yes
MCU_SPI1_D0
1
0
1/0
1/0
WKUP_GPIO0_1
MCU_BOOTMODE04
MCU_SPI1_D1
7
pad
Bootstrap
WKUP_GPIO0_2
0
IO
IO
IO
I
0
MCU_SPI1_D1
1
0
Yes
Yes
WKUP_GPIO0_2
MCU_BOOTMODE05
MCU_SPI1_CS0
MCU_SPI1_CS0
WKUP_GPIO0_3
MCU_MCAN1_TX
MCU_MCAN1_TX
MCU_SPI0_CS3
MCU_ADC_EXT_TRIGGER0
WKUP_GPIO0_4
7
pad
Bootstrap
B21
D13
WKUP_GPIO0_3
WKUP_GPIO0_4
0
1
7
0
1
2
3
7
IO
IO
IO
O
OFF
OFF
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
1
Yes
Yes
1
pad
O
IO
I
Yes
IO
pad
pad
IO
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
B16
WKUP_GPIO0_5
MCU_MCAN1_RX
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
4
5
7
I
I
OFF
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
1
1
Yes
MCU_MCAN1_RX
MCU_SPI1_CS3
IO
I
Yes
Yes
Yes
IO
pad
pad
1
MCU_ADC_EXT_TRIGGER1
WKUP_GPIO0_5
IO
I
C14
C18
C21
WKUP_GPIO0_6
WKUP_GPIO0_7
WKUP_GPIO0_8
WKUP_UART0_CTSn
WKUP_UART0_CTSn
MCU_CPTS0_HW1TSPUSH
MCU_I2C1_SCL
OFF
OFF
OFF
7
7
7
LVCMOS
LVCMOS
LVCMOS
Yes
Yes
Yes
I
1
I
I
IOD
IO
O
1
WKUP_GPIO0_6
pad
WKUP_UART0_RTSn
WKUP_UART0_RTSn
MCU_CPTS0_HW2TSPUSH
MCU_I2C1_SDA
O
I
I
IOD
IO
IOD
IOD
O
1
WKUP_GPIO0_7
pad
1
MCU_I2C1_SCL
MCU_I2C1_SCL
1
MCU_CPTS0_TS_SYNC
MCU_I3C0_SCL
O
1
Yes
IO
IO
IO
IOD
IOD
O
MCU_TIMER_IO6
0
WKUP_GPIO0_8
pad
1
C19
WKUP_GPIO0_9
MCU_I2C1_SDA
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
LVCMOS
PU/PD
Yes
MCU_I2C1_SDA
1
MCU_CPTS0_TS_COMP
MCU_I3C0_SDA
O
1
Yes
IO
IO
IO
I
MCU_TIMER_IO7
0
WKUP_GPIO0_9
pad
0
C20
WKUP_GPIO0_10
MCU_EXT_REFCLK0
MCU_EXT_REFCLK0
MCU_UART0_TXD
MCU_ADC_EXT_TRIGGER0
MCU_CPTS0_RFT_CLK
MCU_SYSCLKOUT0
WKUP_GPIO0_10
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
LVCMOS
PU/PD
Yes
I
0
O
O
0
I
Yes
I
0
O
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
42
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
C16
WKUP_GPIO0_11
MCU_OBSCLK0
0
1
2
3
4
5
6
7
0
1
7
O
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
LVCMOS
PU/PD
Yes
MCU_OBSCLK0
O
I
MCU_UART0_RXD
MCU_ADC_EXT_TRIGGER1
MCU_TIMER_IO1
MCU_I3C0_SDAPULLEN
MCU_CLKOUT0
I
I
0
0
Yes
IO
OD
OZ
IO
O
IO
IO
I
WKUP_GPIO0_11
MCU_UART0_TXD
MCU_SPI0_CS1
pad
D19
D20
E20
WKUP_GPIO0_12
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
Yes
Yes
Yes
Yes
Yes
WKUP_GPIO0_12
MCU_BOOTMODE08
MCU_UART0_RXD
MCU_SPI1_CS1
pad
1
Bootstrap
WKUP_GPIO0_13
WKUP_GPIO0_14
0
I
1
IO
IO
I
WKUP_GPIO0_13
MCU_BOOTMODE09
MCU_UART0_CTSn
MCU_SPI0_CS2
7
pad
1
Bootstrap
0
I
1
IO
IO
IO
I
MCU_TIMER_IO8
WKUP_GPIO0_14
MCU_BOOTMODE06
MCU_UART0_RTSn
MCU_SPI1_CS2
4
Yes
0
7
pad
Bootstrap
E21
WKUP_GPIO0_15
0
O
IO
IO
IO
I
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
LVCMOS
PU/PD
Yes
1
MCU_TIMER_IO9
WKUP_GPIO0_15
MCU_BOOTMODE07
MCU_TIMER_IO6
WKUP_GPIO0_77
BOOTMODE04
4
Yes
Yes
0
7
pad
Bootstrap
D21
E19
D18
WKUP_GPIO0_77
WKUP_GPIO0_78
WKUP_GPIO0_80
4
IO
IO
I
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
Yes
Yes
Yes
7
pad
Bootstrap
MCU_TIMER_IO7
WKUP_GPIO0_78
BOOTMODE05
4
IO
IO
I
0
7
Yes
Yes
pad
Bootstrap
7
WKUP_GPIO0_80
BOOTMODE06
IO
I
pad
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (continued)
BALL
RX
ACTIVE/
TX
DISABLE
[14]
BALL
RESET
STATE
[6]
I/O
VOLTAGE
VALUE
[8]
PULL
UP/DOWN
TYPE
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
RESET
REL. MUX
MODE
[7]
BUFFER
TYPE
[11]
IO
RET
[15]
TYPE
[5]
POWER
[9]
HYS
[10]
DSIS
[13]
[12]
C17
WKUP_GPIO0_81
WKUP_LF_CLKIN
1
7
I
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
LVCMOS
PU/PD
pad
Yes
WKUP_GPIO0_81
BOOTMODE07
IO
I
Yes
Yes
pad
Bootstrap
E18
WKUP_GPIO0_84
PMIC_WAKE1n
0
1
2
7
0
7
0
7
OD
I
OFF
7
1.8 V/3.3 V
LVCMOS
PU/PD
MCU_EXT_REFCLK0
MCU_CPTS0_RFT_CLK
WKUP_GPIO0_84
WKUP_I2C0_SCL
WKUP_GPIO0_64
WKUP_I2C0_SDA
WKUP_GPIO0_65
WKUP_OSC0_XI
0
I
I
IO
IOD
IO
IOD
IO
I
pad
1
F20
H21
WKUP_I2C0_SCL
WKUP_I2C0_SDA
OFF
OFF
0
0
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
I2C OD FS
I2C OD FS
Yes
Yes
Yes
Yes
pad
1
pad
K21
L21
B14
WKUP_OSC0_XI
WKUP_OSC0_XO
WKUP_UART0_RXD
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
HFOSC
HFOSC
LVCMOS
Yes
Yes
WKUP_OSC0_XO
O
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
WKUP_UART0_RXD
WKUP_GPIO0_60
WKUP_UART0_TXD
WKUP_GPIO0_61
0
7
0
7
I
OFF
OFF
7
7
1.8 V/3.3 V
VDDSHV0_MCU
VDDSHV0_MCU
PU/PD
PU/PD
1
Yes
Yes
Yes
Yes
1/0
1/0
IO
O
IO
pad
A14
WKUP_UART0_TXD
1.8 V/3.3 V
LVCMOS
pad
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
备注
表6-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in 节
6.3, Signal Descriptions.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
备注
The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
44
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate
functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
c. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
• I = Input
• O = Output
• OD = Open drain terminal - Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor.
6. BALL RESET STATE: The state of the terminal at power-on reset:
• DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
• DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
• OFF: High-impedance
• PD: High-impedance with an active pulldown resistor
• PU: High-impedance with an active pullup resistor
• An empty box means Not Applicable.
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the RESETSTATz and MCU_RESETSTATz signals.
An empty box means Not Applicable.
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
9. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
10. HYS: Indicates if the input buffer has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis
An empty box means No.
For more information, see the hysteresis values in 节7.6, Electrical Characteristics.
11. BUFFER TYPE: This column describes the associated output buffer type
An empty box means Not Applicable.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
For drive strength of the associated output buffer, refer to 节7.6, Electrical Characteristics.
12. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
• PU: Internal pullup
• PD: Internal pulldown
• PU/PD: Internal pullup and pulldown
• An empty box means No pull.
13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "pad" level) when the peripheral pin
function is not selected by any of the PINCNTLx registers.
• 0: Logic 0 driven on the input signal port of the peripheral.
• 1: Logic 1 driven on the input signal port of the peripheral.
• pad: Logic state of the pad is driven on the input signal port of the peripheral.
• An empty box means Not Applicable.
14. RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
• RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
• TXDISABLE: 0 = driver enabled, 1 = driver disabled.
• An empty box means Not Applicable.
备注
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (HiZ mode is not an input signal).
备注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
15. IO RET: Indicates if wakeup and IO retention are supported.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
46
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
备注
Signal names provided in each Signal Descriptions table, (表6-1 through 表6-106) represent the
pin layer multiplexed signal function which is selected via the PADCONFIG registers. Device
subsystems may provide an additional layer of signal multiplexing, which means the signal names
described in these tables may have additional signal functions. For more information, see the
respective peripheral chapter of the device TRM.
2. DESCRIPTION: Description of the signal
3. PIN TYPE: Signal direction and type:
• I = Input
• O = Output
• OD = Opent drain terminal - Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor
4. BALL: Associated balls bottom
For more information on the I/O cell configurations, see Pad Configuration Registers section in Device
Configuration chapter of the device TRM.
6.3.1 ADC
备注
The ADC can be configured to be used as a GPI. For more information, see Analog-to-Digital
Converter (ADC) section in Peripherals chapter in the device TRM.
6.3.1.1 MCU Domain
表6-2. ADC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_ADC0_AIN0
DESCRIPTION [2]
BALL [4]
[3]
A
A
A
A
A
A
A
A
I
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
ADC Trigger Input
H17
K18
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
MCU_ADC_EXT_TRIGGER0
M17
L18
J18
J17
K17
L17
C12, C20, D13
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-2. ADC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_ADC_EXT_TRIGGER1
ADC Trigger Input
I
B12, B16, C16
6.3.2 DDRSS
6.3.2.1 MAIN Domain
表6-3. DDRSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR_RET
External IO Retention Enable
DDRSS Differential Clock (negative)
DDRSS Differential Clock (positive)
DDRSS Reset
I
R5
H1
G1
J5
DDR0_CKN
DDR0_CKP
DDR0_RESETn
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CAL0(1)
DDR0_CKE0
DDR0_CKE1
DDR0_CSn0_0
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
IO Pad Calibration Resistor
DDRSS Clock Enable
DDRSS Clock Enable
DDRSS Chip Select
DDRSS Chip Select
DDRSS Chip Select
DDRSS Chip Select
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data
G4
H3
J4
K1
J2
H5
K5
G2
H2
G3
K2
G5
J3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A3
E4
N1
R4
B4
A4
C4
C1
C3
C2
A2
B3
D1
D2
F2
E3
F3
F4
D4
F5
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
48
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-3. DDRSS0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
K4
L4
M4
L3
L2
L1
M3
N2
R3
T1
P1
P2
N4
P3
P4
N5
B1
B2
E1
E2
M1
M2
R1
R2
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
(1) An external 240 Ω±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.2.2 DDRSS Mapping
表6-4 presents DDRSS interface signal mapping.
表6-4. DDRSS Signal Mapping
SIGNAL NAME [1]
MEMORY TYPE
PIN TYPE [3]
BALL [4]
LPDDR4
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CKP
DDR0_CKN
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
CA0_A
CA1_A
CA2_A
CA3_A
CA4_A
CA5_A
CK_t_A
CK_c_A
DQ0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
G4
H3
J4
K1
J2
H5
H1
G1
B4
A4
C4
C1
C3
DQ1
DQ2
DQ3
DQ4
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-4. DDRSS Signal Mapping (continued)
SIGNAL NAME [1]
MEMORY TYPE
PIN TYPE [3]
BALL [4]
LPDDR4
DDR0_DQ5
DQ5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
C2
A2
B3
D1
D2
F2
E3
F3
F4
D4
F5
K4
L4
DDR0_DQ6
DQ6
DDR0_DQ7
DQ7
DDR0_DQ8
DQ8
DDR0_DQ9
DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DM0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DMI0
M4
L3
L2
L1
M3
N2
R3
T1
P1
P2
N4
P3
P4
N5
A3
E4
N1
R4
B1
B2
E1
E2
M1
M2
R1
R2
J5
DDR0_DM1
DMI1
DDR0_DM2
DMI2
DDR0_DM3
DMI3
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
DDR0_RESETn
DDR0_CAL0
DDR0_CKE0
DDR0_CKE1
DDR0_CSn0_0
DQS0
DQS0_n
DQS1
DQS1_n
DQS2
DQS2_n
DQS3
DQS3_n
RESET_n
VTP
K5
G2
H2
G3
IO
IO
IO
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
50
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-4. DDRSS Signal Mapping (continued)
SIGNAL NAME [1]
MEMORY TYPE
PIN TYPE [3]
BALL [4]
LPDDR4
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
IO
IO
IO
K2
G5
J3
6.3.3 GPIO
6.3.3.1 MAIN Domain
表6-5. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
GPIO0_8
GPIO0_9
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO0_32
GPIO0_33
GPIO0_34
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
U6
T19
AA17
Y15
AA20
Y17
Y16
V17
AA19
V18
V20
W21
V16
Y18
Y19
Y21
W16
W15
Y20
V21
V19
T13
U14
U16
U15
T15
U19
T14
U18
U17
U20
Y14
Y13
AA15
AA14
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-5. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
GPIO0_35
GPIO0_36
GPIO0_37
GPIO0_38
GPIO0_39
GPIO0_40
GPIO0_41
GPIO0_42
GPIO0_43
GPIO0_44
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
GPIO0_51
GPIO0_52
GPIO0_53
GPIO0_54
GPIO0_55
GPIO0_56
GPIO0_57
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPIO0_63
GPIO0_64
GPIO0_65
GPIO0_66
GPIO0_67
GPIO0_68
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA18
AA16
W17
W20
V14
V13
U12
W14
W19
U13
V15
U21
T16
T17
T18
T20
W3
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
U5
Y1
V4
T5
V3
W2
U3
T3
V1
W1
N19
N20
N21
M19
P21
M20
T4
6.3.3.2 WKUP Domain
表6-6. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
ALF [4]
[3]
WKUP_GPIO0_0
WKUP_GPIO0_1
WKUP_GPIO0_2
WKUP_GPIO0_3
WKUP_GPIO0_4
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
B18
B19
D14
B21
D13
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
52
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-6. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
ALF [4]
[3]
WKUP_GPIO0_5
WKUP_GPIO0_6
WKUP_GPIO0_7
WKUP_GPIO0_8
WKUP_GPIO0_9
WKUP_GPIO0_10
WKUP_GPIO0_11
WKUP_GPIO0_12
WKUP_GPIO0_13
WKUP_GPIO0_14
WKUP_GPIO0_15
WKUP_GPIO0_16
WKUP_GPIO0_17
WKUP_GPIO0_18
WKUP_GPIO0_19
WKUP_GPIO0_20
WKUP_GPIO0_21
WKUP_GPIO0_22
WKUP_GPIO0_23
WKUP_GPIO0_24
WKUP_GPIO0_25
WKUP_GPIO0_26
WKUP_GPIO0_27
WKUP_GPIO0_28
WKUP_GPIO0_29
WKUP_GPIO0_30
WKUP_GPIO0_31
WKUP_GPIO0_43
WKUP_GPIO0_44
WKUP_GPIO0_45
WKUP_GPIO0_46
WKUP_GPIO0_47
WKUP_GPIO0_48
WKUP_GPIO0_49
WKUP_GPIO0_50
WKUP_GPIO0_51
WKUP_GPIO0_52
WKUP_GPIO0_53
WKUP_GPIO0_54
WKUP_GPIO0_55
WKUP_GPIO0_56
WKUP_GPIO0_57
WKUP_GPIO0_58
WKUP_GPIO0_59
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B16
C14
C18
C21
C19
C20
C16
D19
D20
E20
E21
B6
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
C8
B7
D8
C7
C5
A5
A6
B8
A8
A7
D6
D7
D11
C6
D5
A11
C12
B12
B11
D10
A12
B10
C10
A10
B9
A9
C9
D9
C13
A20
B17
A19
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-6. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
WKUP_GPIO0_60
DESCRIPTION [2]
General Purpose Input/Output
ALF [4]
[3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B14
A14
A16
A17
F20
H21
G21
G20
C15
D21
E19
B13
D18
C17
E18
WKUP_GPIO0_61
WKUP_GPIO0_62
WKUP_GPIO0_63
WKUP_GPIO0_64
WKUP_GPIO0_65
WKUP_GPIO0_66
WKUP_GPIO0_67
WKUP_GPIO0_68
WKUP_GPIO0_77
WKUP_GPIO0_78
WKUP_GPIO0_79
WKUP_GPIO0_80
WKUP_GPIO0_81
WKUP_GPIO0_84
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
6.3.4 I2C
6.3.4.1 MAIN Domain
表6-7. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I2C0_SCL
I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
V3
W2
表6-8. I2C1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I2C1_SCL
I2C1_SDA
I2C Clock
I2C Data
IOD
IOD
U3, V17
AA19, T3
表6-9. I2C2 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C2_SCL
I2C2_SDA
I2C Clock
I2C Data
IOD
IOD
W15, Y1
V4, Y20
表6-10. I2C3 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C3_SCL
I2C3_SDA
I2C Clock
I2C Data
IOD
IOD
N19, V19
N20, T13
表6-11. I2C4 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C4_SCL
I2C4_SDA
I2C Clock
I2C Data
IOD
IOD
M19, W14
N21, W19
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
54
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-12. I2C5 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
I2C5_SCL
I2C5_SDA
I2C Clock
I2C Data
IOD
IOD
AA18
AA16
表6-13. I2C6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I2C6_SCL
I2C6_SDA
I2C Clock
I2C Data
IOD
IOD
AA15, M20
AA14, P21
6.3.4.2 MCU Domain
表6-14. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I2C0_SCL
MCU_I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
G21
G20
表6-15. I2C1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I2C1_SCL
MCU_I2C1_SDA
I2C Clock
I2C Data
IOD
IOD
C14, C21
C18, C19
6.3.4.3 WKUP Domain
表6-16. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_I2C0_SCL
WKUP_I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
F20
H21
6.3.5 I3C
6.3.5.1 MAIN Domain
表6-17. I3C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I3C0_SCL
I3C Clock
IO
IO
O
AA18
AA16
AA14
I3C0_SDA
I3C Data
I3C0_SDAPULLEN
MAIN domain I3C Data Pull Enable
6.3.5.2 MCU Domain
表6-18. I3C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I3C0_SCL
I3C Clock
IO
IO
O
C21
C19
MCU_I3C0_SDA
I3C Data
MCU_I3C0_SDAPULLEN
MCU domain I3C Data Pull Enable
C15, C16
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.6 MCAN
6.3.6.1 MAIN Domain
表6-19. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN0_RX
MCAN0_TX
MCAN Receive Data
MCAN Transmit Data
I
V20
V18
O
表6-20. MCAN1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN1_RX
MCAN1_TX
MCAN Receive Data
MCAN Transmit Data
I
V16
O
W21
表6-21. MCAN2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN2_RX
MCAN2_TX
MCAN Receive Data
MCAN Transmit Data
I
Y19
Y18
O
表6-22. MCAN3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN3_RX
MCAN3_TX
MCAN Receive Data
MCAN Transmit Data
I
W16
Y21
O
表6-23. MCAN4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN4_RX
MCAN4_TX
MCAN Receive Data
MCAN Transmit Data
I
Y20
O
W15
表6-24. MCAN5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN5_RX
MCAN5_TX
MCAN Receive Data
MCAN Transmit Data
I
V19
V21
O
表6-25. MCAN6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN6_RX
MCAN6_TX
MCAN Receive Data
MCAN Transmit Data
I
U14
T13
O
表6-26. MCAN7 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN7_RX
MCAN7_TX
MCAN Receive Data
MCAN Transmit Data
I
U15
U16
O
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
56
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-27. MCAN8 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MCAN8_RX
MCAN8_TX
MCAN Receive Data
MCAN Transmit Data
I
U19
T15
O
表6-28. MCAN9 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCAN9_RX
MCAN9_TX
MCAN Receive Data
MCAN Transmit Data
I
U18
T14
O
表6-29. MCAN10 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN10_RX
MCAN10_TX
MCAN Receive Data
MCAN Transmit Data
I
U20
U17
O
表6-30. MCAN11 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN11_RX
MCAN11_TX
MCAN Receive Data
MCAN Transmit Data
I
Y13
Y14
O
表6-31. MCAN12 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN12_RX
MCAN12_TX
MCAN Receive Data
MCAN Transmit Data
I
AA14
AA15
O
表6-32. MCAN13 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN13_RX
MCAN13_TX
MCAN Receive Data
MCAN Transmit Data
I
AA16
AA18
O
表6-33. MCAN14 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN14_RX
MCAN14_TX
MCAN Receive Data
MCAN Transmit Data
I
Y15
O
AA17
表6-34. MCAN15 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN15_RX
MCAN15_TX
MCAN Receive Data
MCAN Transmit Data
I
W20
W17
O
表6-35. MCAN16 Signal Descriptions
DESCRIPTION [2]
PIN TYPE
BALL [4]
[3]
MCAN16_RX
MCAN Receive Data
I
U21
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-35. MCAN16 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
MCAN Transmit Data
BALL [4]
[3]
MCAN16_TX
O
V15
表6-36. MCAN17 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN17_RX
MCAN17_TX
MCAN Receive Data
MCAN Transmit Data
I
T20
T18
O
6.3.6.2 MCU Domain
表6-37. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MCAN0_RX
MCU_MCAN0_TX
MCAN Receive Data
MCAN Transmit Data
I
A17
A16
O
表6-38. MCAN1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MCAN1_RX
MCU_MCAN1_TX
MCAN Receive Data
MCAN Transmit Data
I
B16
D13
O
6.3.7 MCSPI
6.3.7.1 MAIN Domain
表6-39. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI0_CLK
SPI0_CS0
SPI0_CS1
SPI0_CS2
SPI0_CS3
SPI0_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
Y1
W3
U5
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
Y14
U13
V4
SPI0_D1
SPI Data 1
T5
表6-40. MCSPI1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI1_CLK
SPI1_CS0
SPI1_CS1
SPI1_CS2
SPI1_CS3
SPI1_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
P21
N19
N20
N21
W19
M19
M20
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI1_D1
SPI Data 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
58
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-41. MCSPI2 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
SPI2_CLK
SPI2_CS0
SPI2_CS1
SPI2_CS2
SPI2_CS3
SPI2_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
U20
Y14
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
Y13
AA15
AA14
AA18
AA16
SPI2_D1
SPI Data 1
表6-42. MCSPI3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI3_CLK
SPI3_CS0
SPI3_CS1
SPI3_CS2
SPI3_CS3
SPI3_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
T14
U16
U15
T15
U19
U18
U17
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI3_D1
SPI Data 1
表6-43. MCSPI5 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI5_CLK
SPI5_CS0
SPI5_CS1
SPI5_CS2
SPI5_CS3
SPI5_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
W15
W16
V21
Y19
Y18
Y21
Y20
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI5_D1
SPI Data 1
表6-44. MCSPI6 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI6_CLK
SPI6_CS0
SPI6_CS1
SPI6_CS2
SPI6_CS3
SPI6_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
V14
W21
V16
W17
W20
V13
U12
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI6_D1
SPI Data 1
表6-45. MCSPI7 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI7_CLK
SPI7_CS0
SPI7_D0
SPI Clock
IO
IO
IO
T3
U3
V1
SPI Chip Select 0
SPI Data 0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-45. MCSPI7 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI7_D1
SPI Data 1
IO
W1
6.3.7.2 MCU Domain
表6-46. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_SPI0_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CS3
MCU_SPI0_D0
MCU_SPI0_D1
SPI Clock
IO
IO
IO
IO
IO
IO
IO
C13
A19
D19
E20
D13
A20
B17
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI Data 1
表6-47. MCSPI1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_SPI1_CLK
MCU_SPI1_CS0
MCU_SPI1_CS1
MCU_SPI1_CS2
MCU_SPI1_CS3
MCU_SPI1_D0
MCU_SPI1_D1
SPI Clock
IO
IO
IO
IO
IO
IO
IO
B18
B21
D20
E21
B16
B19
D14
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI Data 1
6.3.8 UART
6.3.8.1 MAIN Domain
表6-48. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART0_CTSn
UART0_DCDn
UART0_DSRn
UART0_DTRn
UART0_RIn
UART Clear to Send (active low)
UART Data Carrier Detect (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
I
I
N19, W3
T15
I
U19
O
I
Y14
Y13
UART0_RTSn
UART0_RXD
UART0_TXD
UART Request to Send (active low)
UART Receive Data
O
I
P21, U5
T16
UART Transmit Data
O
T17
表6-49. UART1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART1_CTSn
UART1_RTSn
UART1_RXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
O
I
Y1
V4
T18
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
60
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-49. UART1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
UART Transmit Data
BALL [4]
[3]
UART1_TXD
O
T20
表6-50. UART2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART2_CTSn
UART2_RTSn
UART2_RXD
UART2_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
U17
O
I
U20
AA15, N21, V14
AA14, M19, V13
UART Transmit Data
O
表6-51. UART3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART3_CTSn
UART3_RTSn
UART3_RXD
UART3_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
T15, V1
U19, W1
O
I
U3, Y14, Y18
T3, Y13, Y19
UART Transmit Data
O
表6-52. UART4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART4_CTSn
UART4_RTSn
UART4_RXD
UART4_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
P21
M20
O
I
N21, U12
AA20, M19
UART Transmit Data
O
表6-53. UART5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART5_CTSn
UART5_RTSn
UART5_RXD
UART5_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
N21
M19
O
I
N19, Y15
AA17, N20
UART Transmit Data
O
表6-54. UART6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART6_CTSn
UART6_RTSn
UART6_RXD
UART6_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
V16
V21
Y16
Y17
O
I
UART Transmit Data
O
表6-55. UART7 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART7_CTSn
UART7_RTSn
UART7_RXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
O
I
N21
M19
N19, U21
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-55. UART7 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
UART Transmit Data
BALL [4]
[3]
UART7_TXD
O
N20, V15
表6-56. UART8 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART8_CTSn
UART8_RTSn
UART8_RXD
UART8_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
AA18
AA16
O
I
P21, W14
M20, W19
UART Transmit Data
O
表6-57. UART9 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART9_CTSn
UART9_RTSn
UART9_RXD
UART9_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
Y18
Y19
O
I
AA19, U13
V17
UART Transmit Data
O
6.3.8.2 MCU Domain
表6-58. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_UART0_CTSn
MCU_UART0_RTSn
MCU_UART0_RXD
MCU_UART0_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
E20
O
I
E21
C16, D20
C20, D19
UART Transmit Data
O
6.3.8.3 WKUP Domain
表6-59. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_UART0_CTSn
WKUP_UART0_RTSn
WKUP_UART0_RXD
WKUP_UART0_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
C14
C18
B14
A14
O
I
UART Transmit Data
O
6.3.9 MDIO
6.3.9.1 MCU Domain
表6-60. MDIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MDIO0_MDC
MCU_MDIO0_MDIO
MDIO Clock
MDIO Data
O
D9
C9
IO
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
62
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.9.2 MAIN Domain
表6-61. MDIO0 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MDIO0_MDC
MDIO0_MDIO
MDIO Clock
MDIO Data
O
W19
W14
IO
6.3.10 CPSW2G
6.3.10.1 MCU Domain
表6-62. CPSW2G0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_RGMII1_RXC
MCU_RGMII1_TXC
MCU_RGMII1_RX_CTL
MCU_RGMII1_TX_CTL
MCU_RGMII1_RD0
MCU_RGMII1_RD1
MCU_RGMII1_RD2
MCU_RGMII1_RD3
MCU_RGMII1_TD0
MCU_RGMII1_TD1
MCU_RGMII1_TD2
MCU_RGMII1_TD3
MCU_RMII1_CRS_DV
MCU_RMII1_REF_CLK
MCU_RMII1_RX_ER
MCU_RMII1_TX_EN
MCU_RMII1_RXD0
MCU_RMII1_RXD1
MCU_RMII1_TXD0
MCU_RMII1_TXD1
RGMII Receive Clock
RGMII Transmit Clock
RGMII Receive Control
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
I
O
I
B10
A12
A11
D11
A9
O
I
I
B9
I
A10
C10
D10
B11
B12
C12
D11
B10
A11
A12
A9
I
O
O
O
O
I
I
I
O
I
I
B9
O
O
D10
B11
6.3.11 CPSW5G
6.3.11.1 MAIN Domain
表6-63. CPSW5G0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
RMII Clock Output (50 MHz). This pin is used for clock
source to the external PHY and must be routed back to
the RMII_REF_CLK pin for proper device operation.
CLKOUT
OZ
U21
RGMII1_RXC
RGMII1_TXC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RD0
RGMII1_RD1
RGMII1_RD2
RGMII Receive Clock
RGMII Transmit Clock
RGMII Receive Control
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
I
O
I
AA19
Y20
Y16
O
I
W15
AA17
Y15
I
I
AA20
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-63. CPSW5G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Data 3
BALL [4]
[3]
RGMII1_RD3
RGMII1_TD0
RGMII1_TD1
RGMII1_TD2
RGMII1_TD3
RGMII2_RXC
RGMII2_TXC
I
O
O
O
O
I
Y17
Y18
Y19
Y21
W16
Y14
W21
AA16
U12
Y13
AA15
AA14
AA18
W17
W20
V14
V13
V21
U20
U15
U17
V19
T13
U14
U16
T15
U19
T14
U18
V17
T16
V15
T20
V18
V20
V16
U13
U21
T19
T17
T18
AA20
Y17
V17
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Clock
RGMII Transmit Clock
RGMII Receive Control
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Clock
RGMII Transmit Clock
RGMII Receive Control
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Clock
RGMII Transmit Clock
RGMII Receive Control
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
O
I
RGMII2_RX_CTL
RGMII2_TX_CTL
RGMII2_RD0
RGMII2_RD1
RGMII2_RD2
RGMII2_RD3
RGMII2_TD0
RGMII2_TD1
RGMII2_TD2
RGMII2_TD3
RGMII3_RXC
RGMII3_TXC
RGMII3_RX_CTL
RGMII3_TX_CTL
RGMII3_RD0
RGMII3_RD1
RGMII3_RD2
RGMII3_RD3
RGMII3_TD0
RGMII3_TD1
RGMII3_TD2
RGMII3_TD3
RGMII4_RXC
RGMII4_TXC
RGMII4_RX_CTL
RGMII4_TX_CTL
RGMII4_RD0
RGMII4_RD1
RGMII4_RD2
RGMII4_RD3
RGMII4_TD0
RGMII4_TD1
RGMII4_TD2
RGMII4_TD3
RMII1_CRS_DV
RMII1_RX_ER
RMII1_TX_EN
O
I
I
I
I
O
O
O
O
I
O
I
O
I
I
I
I
O
O
O
O
I
O
I
O
I
I
I
I
O
O
O
O
I
I
O
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
64
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-63. CPSW5G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
RMII Receive Data 0
BALL [4]
[3]
RMII1_RXD0
RMII1_RXD1
RMII1_TXD0
RMII1_TXD1
RMII2_CRS_DV
RMII2_RX_ER
RMII2_TX_EN
RMII2_RXD0
RMII2_RXD1
RMII2_TXD0
RMII2_TXD1
RMII3_CRS_DV
RMII3_RX_ER
RMII3_TX_EN
RMII3_RXD0
RMII3_RXD1
RMII3_TXD0
RMII3_TXD1
RMII4_CRS_DV
RMII4_RX_ER
RMII4_TX_EN
RMII4_RXD0
RMII4_RXD1
RMII4_TXD0
RMII4_TXD1
RMII_REF_CLK
I
I
AA17
Y15
Y16
AA19
V14
V13
W21
W17
W20
U12
V16
U14
U16
T15
V19
T13
U15
U19
Y21
W16
Y20
Y18
Y19
W15
V21
V15
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Reference Clock
O
O
I
I
O
I
I
O
O
I
I
O
I
I
O
O
I
I
O
I
I
O
O
I
6.3.12 ECAP
6.3.12.1 MAIN Domain
表6-64. ECAP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP0_IN_APWM_OUT
IO
N21, U3
表6-65. ECAP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP1_IN_APWM_OUT
IO
M19, V1
表6-66. ECAP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP2_IN_APWM_OUT
IO
W1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.13 EQEP
6.3.13.1 MAIN Domain
表6-67. EQEP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP0_A
EQEP0_B
EQEP0_I
EQEP0_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
Y14
Y13
I
IO
IO
AA16
AA18
EQEP Strobe
表6-68. EQEP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP1_A
EQEP1_B
EQEP1_I
EQEP1_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
AA15
AA14
W20
W17
I
IO
IO
EQEP Strobe
表6-69. EQEP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP2_A
EQEP2_B
EQEP2_I
EQEP2_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
V17
V18
V16
V20
I
IO
IO
EQEP Strobe
6.3.14 EPWM
6.3.14.1 MAIN Domain
表6-70. EPWM Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM_SOCA
EHRPWM_SOCB
EHRPWM Start of Conversion A
EHRPWM Start of Conversion B
O
O
W21
U17
表6-71. EPWM0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM0_A
EHRPWM Output A
IO
IO
I
Y21
Y19
W15
Y16
W16
EHRPWM0_B
EHRPWM Output B
EHRPWM0_SYNCI
EHRPWM0_SYNCO
EHRPWM_TZn_IN0
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 0 (active low)
O
I
表6-72. EPWM1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM1_A
EHRPWM Output A
IO
IO
I
Y18
Y20
EHRPWM1_B
EHRPWM Output B
EHRPWM_TZn_IN1
EHRPWM Trip Zone Input 1 (active low)
AA19
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
66
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-73. EPWM2 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM2_A
EHRPWM Output A
IO
IO
I
Y17
AA20
Y15
EHRPWM2_B
EHRPWM Output B
EHRPWM_TZn_IN2
EHRPWM Trip Zone Input 2 (active low)
表6-74. EPWM3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM3_A
EHRPWM Output A
IO
IO
I
U15
U18
T14
U19
T15
EHRPWM3_B
EHRPWM Output B
EHRPWM3_SYNCI
EHRPWM3_SYNCO
EHRPWM_TZn_IN3
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 3 (active low)
O
I
表6-75. EPWM4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM4_A
EHRPWM Output A
IO
IO
I
U20
V21
U16
EHRPWM4_B
EHRPWM Output B
EHRPWM_TZn_IN4
EHRPWM Trip Zone Input 4 (active low)
表6-76. EPWM5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM5_A
EHRPWM Output A
IO
IO
I
U14
T13
V19
EHRPWM5_B
EHRPWM Output B
EHRPWM_TZn_IN5
EHRPWM Trip Zone Input 5 (active low)
6.3.15 USB
6.3.15.1 MAIN Domain
备注
USB3 functionality is available on the SERDES pins. For more information, refer to 节 6.3.16,
SERDES.
表6-77. USB0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
IO
IO
O
USB0_DM
USB0_DP
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
USB 2.0 Dual-Role Device Role Select
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
AA3
AA2
T4, U13
V6
USB0_DRVVBUS
USB0_ID
USB0_RCALIB(2)
USB0_VBUS(1)
A
IO
A
V5
Y2
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.3.3, USB Design
Guidelines.
(2) An external 500 Ω±1% resistor must be connected between this pin and VSS, even when the pin is unused.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.16 SERDES
备注
The functionality of these pins is controlled by SERDES0_LN[4:0]_CTRL LANE_FUNC_SEL.
6.3.16.1 MAIN Domain
表6-78. SERDES0 Lane0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SERDES0_RX0_N
DESCRIPTION [2]
BALL [4]
[3]
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
AA11
AA12
W11
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
I
O
O
W12
表6-79. SERDES0 Lane1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SERDES0_RX1_N
SERDES0_RX1_P
SERDES0_TX1_N
SERDES0_TX1_P
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
W8
W9
I
O
O
Y10
Y11
表6-80. SERDES0 Lane2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SERDES0_RX2_N
SERDES0_RX2_P
SERDES0_TX2_N
SERDES0_TX2_P
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
Y7
Y8
I
O
O
AA5
AA6
表6-81. SERDES0 Lane3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SERDES0_RX3_N
SERDES0_RX3_P
SERDES0_TX3_N
SERDES0_TX3_P
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
W5
W6
Y4
I
O
O
Y5
表6-82. SERDES0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PCIE1_CLKREQn
PCIE Clock Request Signal
IO
A
N19, W1
V7
SERDES0_REXT(1)
SERDES0_REFCLK_N
SERDES0_REFCLK_P
External Calibration Resistor
Serdes Reference Clock Input/Output (negative)
Serdes Reference Clock Input/Output (positive)
IO
IO
AA8
AA9
(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
68
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.17 OSPI
6.3.17.1 MCU Domain
表6-83. OSPI0 Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_OSPI0_CLK
MCU_OSPI0_DQS
MCU_OSPI0_ECC_FAIL
MCU_OSPI0_LBCLKO
MCU_OSPI0_CSn0
MCU_OSPI0_CSn1
MCU_OSPI0_CSn2
MCU_OSPI0_CSn3
MCU_OSPI0_D0
OSPI Clock
O
I
B6
B7
D5
C8
D6
D7
C6
D5
D8
C7
C5
A5
A6
B8
A8
A7
C6
D5
OSPI Data Strobe (DQS) or Loopback Clock Input
OSPI ECC Status
I
OSPI Loopback Clock Output
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Chip Select 2 (active low)
OSPI Chip Select 3 (active low)
OSPI Data 0
IO
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
O
MCU_OSPI0_D1
OSPI Data 1
MCU_OSPI0_D2
OSPI Data 2
MCU_OSPI0_D3
OSPI Data 3
MCU_OSPI0_D4
OSPI Data 4
MCU_OSPI0_D5
OSPI Data 5
MCU_OSPI0_D6
OSPI Data 6
MCU_OSPI0_D7
OSPI Data 7
MCU_OSPI0_RESET_OUT0
MCU_OSPI0_RESET_OUT1
OSPI Reset
OSPI Reset
O
6.3.18 Hyperbus
6.3.18.1 MCU Domain
表6-84. HYPERBUS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_HYPERBUS0_CK
MCU_HYPERBUS0_CKn
MCU_HYPERBUS0_INTn
MCU_HYPERBUS0_RESETn
Hyperbus Differential Clock (positive)
Hyperbus Differential Clock (negative)
Hyperbus Interrupt (active low)
O
O
I
B6
C8
D5
D7
Hyperbus Reset (active low) Output
O
Hyperbus Reset Status Indicator (active low) from
Hyperbus Memory
MCU_HYPERBUS0_RESETOn
I
C6
MCU_HYPERBUS0_RWDS
MCU_HYPERBUS0_WPn
MCU_HYPERBUS0_CSn0
MCU_HYPERBUS0_CSn1
MCU_HYPERBUS0_DQ0
MCU_HYPERBUS0_DQ1
MCU_HYPERBUS0_DQ2
MCU_HYPERBUS0_DQ3
MCU_HYPERBUS0_DQ4
MCU_HYPERBUS0_DQ5
MCU_HYPERBUS0_DQ6
Hyperbus Read-Write Data Strobe
Hyperbus Write Protect (Not in use)
Hyperbus Chip Select 0
Hyperbus Chip Select 1
Hyperbus Data 0
IO
O
B7
C6, D5
D6
O
O
C6
IO
IO
IO
IO
IO
IO
IO
D8
Hyperbus Data 1
C7
Hyperbus Data 2
C5
Hyperbus Data 3
A5
Hyperbus Data 4
A6
Hyperbus Data 5
B8
Hyperbus Data 6
A8
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-84. HYPERBUS0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCU_HYPERBUS0_DQ7
DESCRIPTION [2]
BALL [4]
[3]
Hyperbus Data 7
IO
A7
6.3.19 GPMC
6.3.19.1 MAIN Domain
表6-85. GPMC0 Signal Descriptions
DESCRIPTION [2]
PIN TYPE
SIGNAL NAME [1]
GPMC0_CLK
BALL [4]
U13
[3]
GPMC clock
IO
O
GPMC Address Valid (active low) or Address Latch
Enable
GPMC0_ADVn_ALE
W20
GPMC0_CLKOUT
GPMC0_DIR
GPMC clock generated for external synchronization
GPMC Data Bus Signal Direction Control
O
O
V14
V21
GPMC Output Enable (active low) or Read Enable
(active low)
GPMC0_OEn_REn
O
T18
GPMC0_WEn
GPMC0_WPn
GPMC Write Enable (active low)
O
O
T17
GPMC Flash Write Protect (active low)
AA18
GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
GPMC0_A0
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
W17
V18
V20
W21
W16
V19
T13
T15
U19
T14
U18
Y14
Y13
U12
V15
W20
U20
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
GPMC address 10 Output in A/D non-multiplexed mode
and Address 26 in A/D multiplexed mode
GPMC address 11 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 12 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 13 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 14 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 15 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 16 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
70
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-85. GPMC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
AA15
AA14
AA18
AA16
W17
[3]
GPMC address 17 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC0_A17
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
OZ
OZ
OZ
OZ
OZ
OZ
GPMC address 18 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 19 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 20 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 21 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 22 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
U17
GPMC Data 0 Input/Output in A/D non-multiplexed mode
and additionally Address 1 Output in A/D multiplexed
mode
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA17
Y15
AA20
Y17
Y16
V17
AA19
V16
Y18
Y19
Y21
W15
Y20
U14
GPMC Data 1 Input/Output in A/D non-multiplexed mode
and additionally Address 2 Output in A/D multiplexed
mode
GPMC Data 2 Input/Output in A/D non-multiplexed mode
and additionally Address 3 Output in A/D multiplexed
mode
GPMC Data 3 Input/Output in A/D non-multiplexed mode
and additionally Address 4 Output in A/D multiplexed
mode
GPMC Data 4 Input/Output in A/D non-multiplexed mode
and additionally Address 5 Output in A/D multiplexed
mode
GPMC Data 5 Input/Output in A/D non-multiplexed mode
and additionally Address 6 Output in A/D multiplexed
mode
GPMC Data 6 Input/Output in A/D non-multiplexed mode
and additionally Address 7 Output in A/D multiplexed
mode
GPMC Data 7 Input/Output in A/D non-multiplexed mode
and additionally Address 8 Output in A/D multiplexed
mode
GPMC Data 8 Input/Output in A/D non-multiplexed mode
and additionally Address 9 Output in A/D multiplexed
mode
GPMC Data 9 Input/Output in A/D non-multiplexed mode
and additionally Address 10 Output in A/D multiplexed
mode
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-85. GPMC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
GPMC0_AD14
IO
U16
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
GPMC0_AD15
IO
O
U15
U20
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
GPMC0_BE0n_CLE
GPMC0_BE1n
GPMC0_CSn0
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
GPMC0_WAIT1
GPMC Upper-Byte Enable (active low)
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC External Indication of Wait
GPMC External Indication of Wait
O
O
O
O
O
I
AA15
T20
U21
W17
AA16
T16
I
U17
6.3.20 MMC
6.3.20.1 MAIN Domain
表6-86. MMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MMC0_CALPAD(1)
MMC0_CLK
MMC/SD/SDIO Calibration Resistor
MMC/SD/SDIO Clock
MMC/SD/SDIO Command
MMC Data Strobe
A
P20
P18
R17
P19
R16
P17
R18
R20
R19
P16
R21
T21
O
MMC0_CMD
MMC0_DS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
(1) An external 10 kΩ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
表6-87. MMC1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
BALL [4]
[3]
IO
IO
I
MMC1_CLK(1)
MMC1_CMD
P21
M20
V1
MMC/SD/SDIO Command
SD Card Detect
MMC1_SDCD(2)
MMC1_SDWP
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
SD Write Protect
I
W1
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
IO
IO
IO
M19
N21
N20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
72
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-87. MMC1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MMC1_DAT3
DESCRIPTION [2]
MMC/SD/SDIO Data
BALL [4]
[3]
IO
N19
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG63 register should be set to 0x1 because of
retiming purposes.
(2) For ROM boot to work properly, the MMC1_SDCD pin should be pulled low externally with a resistor.
6.3.21 CPTS
6.3.21.1 MAIN Domain
表6-88. CPTS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
CPTS0_RFT_CLK
DESCRIPTION [2]
CPTS Reference Clock
BALL [4]
[3]
I
U3
U5
CPTS0_TS_COMP
CPTS0_TS_SYNC
CPTS Time Stamp Counter Compare
CPTS Time Stamp Counter Bit
O
O
I
N20
U3
CPTS0_HW1TSPUSH
CPTS0_HW2TSPUSH
CPTS Hardware Time Stamp Push 1
CPTS Hardware Time Stamp Push 2
I
T3
6.3.21.2 MCU Domain
表6-89. CPTS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_CPTS0_RFT_CLK
MCU_CPTS0_TS_COMP
MCU_CPTS0_TS_SYNC
MCU_CPTS0_HW1TSPUSH
MCU_CPTS0_HW2TSPUSH
CPTS Reference Clock
I
O
O
I
C20, E18
C19
CPTS Time Stamp Counter Compare
CPTS Time Stamp Counter Bit
CPTS Hardware Time Stamp Push 1
CPTS Hardware Time Stamp Push 2
C21
C14
I
C18
6.3.22 MCASP
6.3.22.1 MAIN Domain
表6-90. MCASP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP0_ACLKR
MCASP0_ACLKX
MCASP0_AFSR
MCASP0_AFSX
MCASP0_AXR0
MCASP0_AXR1
MCASP0_AXR2
MCASP0_AXR3
MCASP0_AXR4
MCASP0_AXR5
MCASP0_AXR6
MCASP0_AXR7
MCASP0_AXR8
MCASP0_AXR9
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
U17
W15
U15
Y16
W16
Y21
Y20
AA19
U19
T15
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
U20
V21
V17
V18
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-90. MCASP0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCASP0_AXR10
DESCRIPTION [2]
BALL [4]
[3]
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
IO
IO
IO
IO
IO
IO
V20
W21
V16
MCASP0_AXR11
MCASP0_AXR12
MCASP0_AXR13
MCASP0_AXR14
MCASP0_AXR15
Y14
Y13
AA15
表6-91. MCASP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP1_ACLKR
MCASP1_ACLKX
MCASP1_AFSR
MCASP1_AFSX
MCASP1_AXR0
MCASP1_AXR1
MCASP1_AXR2
MCASP1_AXR3
MCASP1_AXR4
MCASP1_AXR5
MCASP1_AXR6
MCASP1_AXR7
MCASP1_AXR8
MCASP1_AXR9
MCASP1_AXR10
MCASP1_AXR11
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
U18
Y19
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
T14
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Y18
Y17
AA20
Y15
AA17
U16
U14
T13
V19
AA14
AA18
T14
U18
表6-92. MCASP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP2_ACLKR
MCASP2_ACLKX
MCASP2_AFSR
MCASP2_AFSX
MCASP2_AXR0
MCASP2_AXR1
MCASP2_AXR2
MCASP2_AXR3
MCASP2_AXR4
MCASP2_AXR5
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
W19
U12
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
W14
V13
AA16
W17
W20
V14
W14
W19
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
74
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.23 DMTIMER
6.3.23.1 MAIN Domain
表6-93. DMTIMER Signal Descriptions
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
TIMER_IO0
DESCRIPTION [2]
Timer Inputs and Outputs (not tied to single timer
instance)
IO
IO
IO
IO
IO
IO
IO
IO
N19, V1
N20, W1
N21
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO1
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO2
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO3
M19
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO4
P21
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO5
M20
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO6
T18
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO7
T20
6.3.23.2 MCU Domain
表6-94. DMTIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_TIMER_IO0
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
MCU_TIMER_IO4
MCU_TIMER_IO5
MCU_TIMER_IO6
MCU_TIMER_IO7
MCU_TIMER_IO8
MCU_TIMER_IO9
DESCRIPTION [2]
BALL [4]
B17
[3]
Timer Inputs and Outputs (not tied to single timer
instance)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Timer Inputs and Outputs (not tied to single timer
instance)
A19, C16
C12
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
B12
Timer Inputs and Outputs (not tied to single timer
instance)
C10
Timer Inputs and Outputs (not tied to single timer
instance)
A10
Timer Inputs and Outputs (not tied to single timer
instance)
C21, D21
C19, E19
E20
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
E21
6.3.24 Emulation and Debug
6.3.24.1 MAIN Domain
表6-95. JTAG Signal Descriptions
DESCRIPTION [2]
PIN TYPE
SIGNAL NAME [1]
BALL [4]
[3]
EMU0
Emulation Control 0
IO
A13
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-95. JTAG Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
Emulation Control 1
BALL [4]
[3]
EMU1
TCK
IO
D12
B15
F19
F21
U4
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Reset
I
TDI
I
TDO
TMS
TRSTn
OZ
I
I
B20
表6-96. Trace Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
TRC_CLK
Trace Clock
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
W15
Y16
W16
Y21
Y19
Y18
Y20
AA19
Y17
AA20
Y15
AA17
U17
U15
U18
T14
TRC_CTL
Trace Control
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
Trace Data 4
Trace Data 5
Trace Data 6
Trace Data 7
Trace Data 8
Trace Data 9
Trace Data 10
Trace Data 11
Trace Data 12
Trace Data 13
Trace Data 14
Trace Data 15
Trace Data 16
Trace Data 17
Trace Data 18
Trace Data 19
Trace Data 20
Trace Data 21
Trace Data 22
Trace Data 23
TRC_DATA0
TRC_DATA1
TRC_DATA2
TRC_DATA3
TRC_DATA4
TRC_DATA5
TRC_DATA6
TRC_DATA7
TRC_DATA8
TRC_DATA9
TRC_DATA10
TRC_DATA11
TRC_DATA12
TRC_DATA13
TRC_DATA14
TRC_DATA15
TRC_DATA16
TRC_DATA17
TRC_DATA18
TRC_DATA19
TRC_DATA20
TRC_DATA21
TRC_DATA22
TRC_DATA23
U19
T15
U20
V21
U16
U14
T13
V19
W14
W19
6.3.25 System and Miscellaneous
6.3.25.1 Boot Mode Configuration
6.3.25.1.1 MAIN Domain
表6-97. Sysboot Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
BOOTMODE00
BOOTMODE01
Bootmode pin 0
Bootmode pin 1
I
I
D8
C7
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
76
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-97. Sysboot Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
Bootmode pin 2
Bootmode pin 3
Bootmode pin 4
Bootmode pin 5
Bootmode pin 6
Bootmode pin 7
I
I
I
I
I
I
A6
B8
D21
E19
D18
C17
6.3.25.1.2 MCU Domain
表6-98. Sysboot Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_BOOTMODE00
MCU_BOOTMODE01
MCU_BOOTMODE02
MCU_BOOTMODE03
MCU_BOOTMODE04
MCU_BOOTMODE05
MCU_BOOTMODE06
MCU_BOOTMODE07
MCU_BOOTMODE08
MCU_BOOTMODE09
Bootmode pin 00
Bootmode pin 01
Bootmode pin 02
Bootmode pin 03
Bootmode pin 04
Bootmode pin 05
Bootmode pin 06
Bootmode pin 07
Bootmode pin 08
Bootmode pin 09
I
I
I
I
I
I
I
I
I
I
C13
A20
B17
B18
B19
D14
E20
E21
D19
D20
6.3.25.2 Clock
6.3.25.2.1 MAIN Domain
表6-99. Clock1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
OSC1_XI
High frequency oscillator input
High frequency oscillator output
I
K19
J19
OSC1_XO
O
6.3.25.2.2 WKUP Domain
表6-100. Clock0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_LF_CLKIN
WKUP_OSC0_XI
WKUP_OSC0_XO
Low frequency (32.768 KHz) oscillator input
High frequency oscillator input
I
I
C17
K21
L21
High frequency oscillator output
O
6.3.25.3 System
6.3.25.3.1 MAIN Domain
表6-101. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
External clock routed to ATL or McASP as one of the
selectable input clock sources, or as a output clock
output for ATL or McASP
AUDIO_EXT_REFCLK0
IO
V18
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-101. System0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
External clock routed to ATL or McASP as one of the
selectable input clock sources, or as a output clock
output for ATL or McASP
AUDIO_EXT_REFCLK1
IO
I
U21
U6
EXTINTn
External Interrupt
External clock input to Main Domain, routed to Timer
clock muxes as one of the selectable input clock sources
for Timer/WDT modules, or as reference clock to
MAIN_PLL2 (PER1 PLL)
EXT_REFCLK1
I
T3
GPMC functional clock output selected through a mux
logic
GPMC0_FCLK_MUX
OBSCLK0
O
O
O
O
V14
W1
Observation clock output for test and debug purposes
only
Observation clock output for test and debug purposes
only
OBSCLK1
V16
V14
Observation clock output for test and debug purposes
only
OBSCLK2
RESETSTATz
Main Domain warm reset status output
Error signal output from Main Domain ESM
CPTS Time Stamp Generator Bit 0
CPTS Time Stamp Generator Bit 1
CPTS Time Stamp Generator Bit 2
CPTS Time Stamp Generator Bit 3
O
IO
O
O
O
O
U2
V2
SOC_SAFETY_ERRORn
SYNC0_OUT
U3
SYNC1_OUT
T3
SYNC2_OUT
W16
V21
SYNC3_OUT
SYSCLK0 output from Main PLL controller (divided by 6)
for test and debug purposes only
SYSCLKOUT0
O
V1
6.3.25.3.2 WKUP Domain
表6-102. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Reference clock output for Ethernet PHYs (50MHz or
25MHz)
MCU_CLKOUT0
OZ
I
C16
C20, E18
C16
MCU_EXT_REFCLK0
MCU_OBSCLK0
External system clock input
Observation clock output for test and debug purposes
only
O
MCU_PORz
MCU Domain cold reset
I
O
I
G19
B13
A18
G18
MCU_RESETSTATz
MCU_RESETz
MCU Domain warm reset status output
MCU Domain warm reset
MCU_SAFETY_ERRORn
Error signal output from MCU Domain ESM
IO
MCU Domain system clock output for test and debug
purposes only
MCU_SYSCLKOUT0
O
C20
PMIC_POWER_EN1
PMIC_WAKE0n
PMIC_WAKE1n
PORz
Power enable output for MAIN Domain supplies
PMIC WakeUp (active low)
O
OD
OD
I
C15
T19
E18
H20
A15
PMIC WakeUp (active low)
Main Domain cold reset
RESET_REQz
Main Domain external warm reset request input
I
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
78
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.3.25.3.3 VMON
表6-103. VMON Signal Decription
PIN TYPE
BALL [4]
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
Voltage Monitor, fixed 0.45V (+/-3%) threshold. Use with
external precision voltage divider to monitor a higher
voltage rail such as the PMIC input supply.
VMON1_ER_VSYS
PWR
G15
VMON2_IR_VCPU
Must be externally connected directly to VDD_CPU
PWR
PWR
D16
E17
General purpose voltage monitor for external supplies,
1.8V threshold. With internal resistor Divider.
VMON3_IR_VEXT1P8
General purpose voltage monitor for external supplies,
1.8V threshold. With internal resistor Divider.
VMON4_IR_VEXT1P8
VMON5_IR_VEXT3P3
PWR
PWR
F17
L14
General purpose voltage monitor for external supplies,
3.3V threshold. With internal resistor Divider.
6.3.25.4 EFUSE
表6-104. EFUSE Signal Description
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
VPP_CORE(1)
VPP_MCU(1)
Programming voltage for MAIN Domain efuses
Programming voltage for MCU Domain efuses
PWR
PWR
N17
E11
(1) This signal is valid only for High-Security devices. For more details, see 节7.7, VPP Specification for One-Time Programmable (OTP)
eFUSEs. For General-Purpose devices do not connect any signal, test point, or board trace to this signal.
6.3.26 Power Supply
备注
All power balls must be supplied with the voltages specified in 节 7.3, Recommended Operating
Conditions, unless otherwise specified in 节6.3, Signal Descriptions.
表6-105. Power Supply Signal Description
PIN TYPE
SIGNAL NAME [1]
CAP_VDDS0(1)
DESCRIPTION [2]
BALL [4]
[3]
External capacitor connection for MAIN domain
GENERAL IO group 0
PWR
M7
CAP_VDDS0_MCU(1)
CAP_VDDS1_MCU(1)
External capacitor connection for MCUSS IO group 0
External capacitor connection for MCUSS IO group 1
PWR
PWR
G14
F9
External capacitor connection for MAIN domain
CANUART IO group 2
CAP_VDDS2(1)
PWR
PWR
PWR
T12
F10
L15
CAP_VDDS2_MCU(1)
CAP_VDDS5(1)
External capacitor connection for MCUSS IO group 2
External capacitor connection for MAIN domain MMC1
IO group 5
VDDAR_CORE
MAIN domain RAM supply
CPU RAM supply
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
K14, P14
J11, M10
H12, J14
K7
VDDAR_CPU
VDDAR_MCU
MCUSS RAM supply
VDDA_0P8_PLL_DDR
VDDA_0P8_USB
DDR PLL analog supply
USB0 0.8 V analog supply
MMC0 DLL analog supply
SERDES0 analog supply low
SERDES0 clock supply
USB0 1.8 V analog supply
P7
VDDA_0P8_DLL_MMC0
VDDA_0P8_SERDES0
VDDA_0P8_SERDES0_C
VDDA_1P8_USB
M18
R8, T7, U8
R9
R6
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-105. Power Supply Signal Description (continued)
PIN TYPE
SIGNAL NAME [1]
VDDA_1P8_SERDES0
DESCRIPTION [2]
SERDES0 analog supply high
BALL [4]
[3]
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
P8
R7
VDDA_3P3_USB
VDDA_ADC_MCU
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
VDDA_PLLGRP0
VDDA_PLLGRP4
VDDA_PLLGRP6
VDDA_PLLGRP8
VDDA_POR_WKUP
VDDA_TEMP0
USB0 3.3 V analog supply
ADC analog supply and high voltage reference (VREFP)
Analog supply for MCU PLL group 0
J16
F15
F16
N14
N9
Analog supply for temperature sensor 0 in MCU domain
Analog supply for MAIN PLL group 0
Analog supply for MAIN PLL group 4
Analog supply for MAIN PLL Group 6
Analog supply for MAIN PLL group 8
J9
L7
WKUP domain analog supply
J15
J8
Analog supply for MAIN domain TEMP sensor 0
Analog supply for MAIN domain TEMP sensor 1
Oscillator supply for WKUP domain
VDDA_TEMP1
P15
H16
N6, P6
VDDA_WKUP
VDDSHV0
IO supply for MAIN domain GENERAL IO group
IO supply MCUSS general IO group, and MCU and MAIN
domain warm reset pins
VDDSHV0_MCU
PWR
E13, E14, F13, F14
VDDSHV1_MCU
VDDSHV2
IO supply for MCUSS IO group 1
PWR
PWR
PWR
PWR
E7, E8, F8
T10, U11, U9
F11, F12, G11
K16, L16
IO supply for MAIN domain CANUART IO group 2
IO supply for MCUSS IO group 2
VDDSHV2_MCU
VDDSHV5
IO supply for MAIN domain MMC1 IO group 5
A1, G7, H6, J7, K6,
M5, U1
VDDS_DDR
DDR inteface power supply
PWR
VDDS_DDR_BIAS
VDDS_DDR_C
VDDS_MMC0
VDDA_OSC1
Bias supply for LPDDR4
PWR
PWR
PWR
PWR
F7, L6
J6
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
M16, N16
G17
HFOSC1 supply
H8, K12, L13, M12,
M14, N13, N15, N7,
P10, P12, R11, R13,
R15
VDD_CORE
VDD_CPU
MAIN domain core supply
CPU core supply
PWR
PWR
J10, L11, M9, N11,
N8
G9, H10, H14, J13,
K15
VDD_MCU
MCUSS core supply
PWR
PWR
PWR
VDD_MCU_WAKE1
VDD_WAKE0
Core supply for MCU WAKE function
G13
P11
Core supply for MAIN domain WAKE function which
includes all "CANUART" IO.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
80
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-105. Power Supply Signal Description (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
B5, AA1, AA10,
AA13, AA4, AA7,
C11, D15, D17, D3,
E10, E12, E15, E16,
E6, E9, F1, G10,
G12, G16, G6, G8,
H11, H13, H15, H19,
H4, H7, H9, J1, J12,
J21, K11, K13, K3,
L12, L19, L5, M11,
M13, M15, M21, M6,
M8, N10, N12, N3,
P13, P5, P9, R10,
R12, R14, T11, T2,
T6, T8, T9, U10, U7,
V11, V12, V9, W10,
W13, W18, W4, W7,
Y12, Y3, Y6, Y9
VSS
Ground
GND
(1) This pin must always be connected via a 1-μF ± 10% capacitor to VSS.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.4 Pin Multiplexing
备注
Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins.
Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
表 6-106, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see
Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the
device TRM for information associated with peripheral signal multiplexing.
备注
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
备注
表 6-106, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter
in the device TRM.
备注
The PRU contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper
multiplexing is described in the PRU chapter in the device TRM.
For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.
表6-106. Pin Multiplexing
ADDR
ESS
OFFSE
T
MUXMODE[15:0] SETTINGS
BALL
NUMB
ER
REGISTER
NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C00 WKUP_PADCON B6
FIG_0
MCU_OSPI MCU_HYP
WKUP_GP
IO0_16
0
0_CLK
ERBUS0_
CK
0x1C00 PADCONFIG_0
0
U6
EXTINTn
GPIO0_0
0x1C00 WKUP_PADCON C8
FIG_1
MCU_OSPI MCU_HYP
0_LBCLKO ERBUS0_
CKn
WKUP_GP
IO0_17
4
0x1C00 PADCONFIG_1
4
AA17
RMII1_RX
D0
RGMII1_R RMII1_RX MCAN14_T GPIO0_2
D0 D0
TRC_DATA UART5_TX MCASP1_
AXR3
GPMC0_A
D0
X
9
D
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
82
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
MUXMODE[15:0] SETTINGS
BALL
NUMB
ER
ESS
OFFSE
T
REGISTER
NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C00 PADCONFIG_2
8
Y15
RMII1_RX
D1
RGMII1_R RMII1_RX MCAN14_ GPIO0_3
D1 D1 RX
EHRPWM_ TRC_DATA UART5_RX MCASP1_
TZn_IN2 AXR2
GPMC0_A
D1
8
D
0x1C00 WKUP_PADCON B7
FIG_2
MCU_OSPI MCU_HYP
WKUP_GP
IO0_18
8
0_DQS
ERBUS0_
RWDS
0x1C00 PADCONFIG_3
C
AA20
RMII1_CR
S_DV
RGMII1_R RMII1_CR
D2 S_DV
GPIO0_4
EHRPWM2 TRC_DATA UART4_TX MCASP1_
_B AXR1
GPMC0_A
D2
7
D
0x1C00 WKUP_PADCON D8
FIG_3
MCU_OSPI MCU_HYP
WKUP_GP
IO0_19
BOOTMOD
E00
C
0_D0
ERBUS0_
DQ0
0x1C01 PADCONFIG_4
0
Y17
RMII1_RX_
ER
RGMII1_R RMII1_RX_
D3 ER
GPIO0_5
EHRPWM2 TRC_DATA UART6_TX MCASP1_
_A AXR0
GPMC0_A
D3
6
D
0x1C01 WKUP_PADCON C7
FIG_4
MCU_OSPI MCU_HYP
WKUP_GP
IO0_20
BOOTMOD
E01
0
0_D1
ERBUS0_
DQ1
0x1C01 WKUP_PADCON C5
FIG_5
MCU_OSPI MCU_HYP
WKUP_GP
IO0_21
4
0_D2
ERBUS0_
DQ2
0x1C01 PADCONFIG_5
4
Y16
RMII1_TXD
0
RGMII1_R RMII1_TXD
X_CTL
GPIO0_6
EHRPWM0 TRC_CTL UART6_RX MCASP0_
GPMC0_A
D4
0
_SYNCO
D
AFSX
0x1C01 WKUP_PADCON A5
FIG_6
MCU_OSPI MCU_HYP
WKUP_GP
IO0_22
8
0_D3
ERBUS0_
DQ3
0x1C01 PADCONFIG_6
8
V17
RMII1_TX_
EN
RGMII4_R RMII1_TX_
XC EN
GPIO0_7
GPIO0_8
EQEP2_A
UART9_TX MCASP0_ I2C1_SCL GPMC0_A
AXR8 D5
D
0x1C01 PADCONFIG_7
C
AA19
RMII1_TXD
1
RGMII1_R RMII1_TXD
EHRPWM_ TRC_DATA UART9_RX MCASP0_ I2C1_SDA GPMC0_A
TZn_IN1
XC
1
5
D
AXR3
D6
0x1C01 WKUP_PADCON A6
FIG_7
MCU_OSPI MCU_HYP
WKUP_GP
IO0_23
BOOTMOD
E02
C
0_D4
ERBUS0_
DQ4
0x1C02 WKUP_PADCON B8
FIG_8
MCU_OSPI MCU_HYP
WKUP_GP
IO0_24
BOOTMOD
E03
0
0_D5
ERBUS0_
DQ5
0x1C02 PADCONFIG_8
0
V18
V20
MCAN0_T
X
RGMII4_R
D0
MCAN0_T GPIO0_9
X
EQEP2_B
EQEP2_S
GPMC0_A MCASP0_
AXR9
AUDIO_EX
T_REFCLK
0
1
0x1C02 PADCONFIG_9
4
MCAN0_R
X
RGMII4_R
D1
MCAN0_R GPIO0_10
X
GPMC0_A MCASP0_
AXR10
2
0x1C02 WKUP_PADCON A8
FIG_9
MCU_OSPI MCU_HYP
WKUP_GP
IO0_25
4
0_D6
ERBUS0_
DQ6
0x1C02 PADCONFIG_10 W21
8
MCAN1_T
X
RGMII2_T RMII2_TX_ MCAN1_T GPIO0_11 SPI6_CS0 EHRPWM_
XC EN SOCA
GPMC0_A MCASP0_
3 AXR11
X
0x1C02 WKUP_PADCON A7
MCU_OSPI MCU_HYP
WKUP_GP
IO0_26
8
FIG_10
0_D7
ERBUS0_
DQ7
0x1C02 PADCONFIG_11
C
V16
MCAN1_R
X
RGMII4_R RMII2_TXD MCAN1_R GPIO0_12 SPI6_CS1 EQEP2_I
D2
GPMC0_A UART6_CT MCASP0_
D7 Sn AXR12
OBSCLK1
1
X
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
BALL
MUXMODE[15:0] SETTINGS
ESS
OFFSE
T
REGISTER
NAME
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C02 WKUP_PADCON D6
FIG_11
MCU_OSPI MCU_HYP
WKUP_GP
IO0_27
C
0_CSn0
ERBUS0_
CSn0
0x1C03 WKUP_PADCON D7
FIG_12
MCU_OSPI MCU_HYP
WKUP_GP
IO0_28
0
0_CSn1
ERBUS0_
RESETn
0x1C03 PADCONFIG_12 Y18
0
MCAN2_T
X
RGMII1_T RMII4_RX MCAN2_T GPIO0_13 SPI5_CS3 EHRPWM1 TRC_DATA UART3_RX MCASP1_ UART9_CT GPMC0_A
D0 D0 _A AFSX Sn D8
X
3
D
0x1C03 PADCONFIG_13 Y19
4
MCAN2_R
X
RGMII1_T RMII4_RX MCAN2_R GPIO0_14 SPI5_CS2 EHRPWM0 TRC_DATA UART3_TX MCASP1_ UART9_RT GPMC0_A
D1
D1
X
_B
2
D
ACLKX
Sn
D9
0x1C03 PADCONFIG_14 Y21
8
MCAN3_T
X
RGMII1_T RMII4_CR MCAN3_T GPIO0_15 SPI5_D0
EHRPWM0 TRC_DATA
MCASP0_
AXR1
GPMC0_A
D10
D2
S_DV
X
_A
1
0x1C03 WKUP_PADCON C6
MCU_OSPI MCU_OSPI MCU_HYP MCU_HYP MCU_HYP
0_CSn2 0_CSn2 ERBUS0_ ERBUS0_ ERBUS0_
RESETOn WPn CSn1
MCU_OSPI WKUP_GP
0_RESET_ IO0_30
OUT0
8
FIG_14
0x1C03 WKUP_PADCON D5
FIG_15
MCU_OSPI MCU_OSPI MCU_HYP MCU_HYP
MCU_OSPI MCU_OSPI WKUP_GP
0_RESET_ 0_ECC_FA IO0_31
C
0_CSn3
0_CSn3
ERBUS0_I ERBUS0_
NTn WPn
OUT1
IL
0x1C03 PADCONFIG_15 W16
C
MCAN3_R
X
RGMII1_T RMII4_RX_ MCAN3_R GPIO0_16 SPI5_CS0 EHRPWM_ TRC_DATA GPMC0_A MCASP0_
SYNC2_O
UT
D3 ER TZn_IN0 AXR0
X
0
4
0x1C04 PADCONFIG_16 W15
0
MCAN4_T
X
RGMII1_T RMII4_TXD MCAN4_T GPIO0_17 SPI5_CLK EHRPWM0 TRC_CLK I2C2_SCL MCASP0_
X_CTL _SYNCI ACLKX
GPMC0_A
D11
0
X
0x1C04 PADCONFIG_17 Y20
4
MCAN4_R
X
RGMII1_T RMII4_TX_ MCAN4_R GPIO0_18 SPI5_D1
EHRPWM1 TRC_DATA I2C2_SDA MCASP0_
GPMC0_A
D12
XC EN _B AXR2
X
4
0x1C04 PADCONFIG_18 V21
8
MCAN5_T
X
RGMII3_R RMII4_TXD MCAN5_T GPIO0_19 SPI5_CS1 EHRPWM4 TRC_DATA UART6_RT MCASP0_ GPMC0_DI SYNC3_O
XC
1
X
_B
17
Sn
AXR7
R
UT
0x1C04 PADCONFIG_19 V19
C
MCAN5_R
X
RGMII3_R RMII3_RX MCAN5_R GPIO0_20 I2C3_SCL EHRPWM_ TRC_DATA GPMC0_A MCASP1_
D0 D0 TZn_IN5 21 AXR7
X
5
0x1C05 PADCONFIG_20 T13
0
MCAN6_T
X
RGMII3_R RMII3_RX MCAN6_T GPIO0_21 I2C3_SDA EHRPWM5 TRC_DATA GPMC0_A MCASP1_
D1
D1
X
_B
20
6
AXR6
0x1C05 PADCONFIG_21 U14
4
MCAN6_R
X
RGMII3_R RMII3_CR MCAN6_R GPIO0_22
EHRPWM5 TRC_DATA
_A 19
MCASP1_
AXR5
GPMC0_A
D13
D2 S_DV
X
0x1C05 PADCONFIG_22 U16
8
MCAN7_T
X
RGMII3_R RMII3_RX_ MCAN7_T GPIO0_23 SPI3_CS0 EHRPWM_ TRC_DATA
D3 ER TZn_IN4 18
MCASP1_
AXR4
GPMC0_A
D14
X
0x1C05 PADCONFIG_23 U15
C
MCAN7_R
X
RGMII3_R RMII3_TXD MCAN7_R GPIO0_24 SPI3_CS1 EHRPWM3 TRC_DATA
X_CTL _A 11
MCASP0_
AFSR
GPMC0_A
D15
0
X
0x1C06 PADCONFIG_24 T15
0
MCAN8_T
X
GPMC0_A RGMII3_T RMII3_TX_ MCAN8_T GPIO0_25 SPI3_CS2 EHRPWM_ TRC_DATA UART3_CT MCASP0_
D0 EN TZn_IN3 15 Sn AXR5
UART0_D
CDn
7
X
0x1C06 PADCONFIG_25 U19
4
MCAN8_R
X
RGMII3_T RMII3_TXD MCAN8_R GPIO0_26 SPI3_CS3 EHRPWM3 TRC_DATA UART3_RT MCASP0_ GPMC0_A UART0_DS
D1
1
X
_SYNCO
14
Sn
AXR4
8
Rn
0x1C06 WKUP_PADCON D11
MCU_RGM MCU_RMII
II1_TX_CT 1_CRS_DV
L
WKUP_GP
IO0_29
8
FIG_26
0x1C06 PADCONFIG_26 T14
8
MCAN9_T
X
RGMII3_T
D2
MCAN9_T GPIO0_27 SPI3_CLK EHRPWM3 TRC_DATA
_SYNCI 13
MCASP1_ GPMC0_A MCASP1_
AFSR AXR10
X
9
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
84
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
MUXMODE[15:0] SETTINGS
BALL
NUMB
ER
ESS
OFFSE
T
REGISTER
NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C06 WKUP_PADCON A11
FIG_27
MCU_RGM MCU_RMII
II1_RX_CT 1_RX_ER
L
WKUP_GP
IO0_43
C
0x1C06 PADCONFIG_27 U18
C
MCAN9_R
X
RGMII3_T
D3
MCAN9_R GPIO0_28 SPI3_D0
X
EHRPWM3 TRC_DATA
_B 12
MCASP1_ GPMC0_A MCASP1_
ACLKR 10 AXR11
0x1C07 WKUP_PADCON C12
MCU_RGM MCU_TIME
MCU_ADC
_EXT_TRI
GGER0
WKUP_GP
IO0_44
0
FIG_28
II1_TD3
R_IO2
0x1C07 PADCONFIG_28 U17
0
MCAN10_T
X
RGMII3_T
X_CTL
MCAN10_T GPIO0_29 SPI3_D1
X
EHRPWM_ TRC_DATA UART2_CT MCASP0_ GPMC0_W GPMC0_A
SOCB 10 Sn ACLKR AIT1 22
0x1C07 PADCONFIG_29 U20
4
MCAN10_
RX
RGMII3_T
XC
MCAN10_ GPIO0_30 SPI2_CLK EHRPWM4 TRC_DATA UART2_RT MCASP0_ GPMC0_B GPMC0_A
RX _A 16 Sn AXR6 E0n_CLE 16
0x1C07 WKUP_PADCON B12
MCU_RGM MCU_TIME
II1_TD2 R_IO3
MCU_ADC
_EXT_TRI
GGER1
WKUP_GP
IO0_45
4
FIG_29
0x1C07 WKUP_PADCON B11
FIG_30
MCU_RGM MCU_RMII
WKUP_GP
IO0_46
8
II1_TD1
1_TXD1
0x1C07 PADCONFIG_30 Y14
8
MCAN11_T
X
RGMII2_R
XC
MCAN11_T GPIO0_31 SPI2_CS0 EQEP0_A SPI0_CS2 UART3_RX MCASP0_ GPMC0_A UART0_DT
X
D
AXR13
11
Rn
0x1C07 PADCONFIG_31 Y13
C
MCAN11_
RX
RGMII2_R
D0
MCAN11_ GPIO0_32 SPI2_CS1 EQEP0_B
RX
UART3_TX MCASP0_ GPMC0_A UART0_RI
D
AXR14 12
n
0x1C07 WKUP_PADCON D10
MCU_RGM MCU_RMII
WKUP_GP
IO0_47
C
FIG_31
II1_TD0
1_TXD0
0x1C08 PADCONFIG_32 AA15
0
MCAN12_T
X
RGMII2_R
D1
MCAN12_T GPIO0_33 SPI2_CS2 EQEP1_A I2C6_SCL UART2_RX MCASP0_ GPMC0_B GPMC0_A
AXR15 E1n 17
X
D
0x1C08 WKUP_PADCON A12
MCU_RGM MCU_RMII
II1_TXC 1_TX_EN
WKUP_GP
IO0_48
0
FIG_32
0x1C08 WKUP_PADCON B10
MCU_RGM MCU_RMII
WKUP_GP
IO0_49
4
FIG_33
II1_RXC
1_REF_CL
K
0x1C08 PADCONFIG_33 AA14
4
MCAN12_
RX
RGMII2_R
D2
MCAN12_ GPIO0_34 SPI2_CS3 EQEP1_B I2C6_SDA UART2_TX MCASP1_ I3C0_SDA GPMC0_A
RX AXR8 PULLEN 18
D
0x1C08 PADCONFIG_34 AA18
8
MCAN13_T
X
RGMII2_R GPMC0_W MCAN13_T GPIO0_35 SPI2_D0
D3 Pn
EQEP0_S I2C5_SCL UART8_CT MCASP1_ I3C0_SCL GPMC0_A
Sn AXR9 19
X
0x1C08 WKUP_PADCON C10
MCU_RGM MCU_TIME
WKUP_GP
IO0_50
8
FIG_34
II1_RD3
R_IO4
0x1C08 PADCONFIG_35 AA16
C
MCAN13_
RX
RGMII2_R GPMC0_C MCAN13_ GPIO0_36 SPI2_D1
X_CTL Sn3 RX
EQEP0_I
I2C5_SDA UART8_RT MCASP2_ I3C0_SDA GPMC0_A
Sn AXR0 20
0x1C08 WKUP_PADCON A10
MCU_RGM MCU_TIME
II1_RD2 R_IO5
WKUP_GP
IO0_51
C
FIG_35
0x1C09 WKUP_PADCON B9
MCU_RGM MCU_RMII
WKUP_GP
IO0_52
0
FIG_36
II1_RD1
1_RXD1
0x1C09 PADCONFIG_36 W17
0
MCAN15_T
X
RGMII2_T RMII2_RX
D0 D0
GPIO0_37 SPI6_CS2 EQEP1_S MCAN15_T GPMC0_C MCASP2_ GPMC0_A GPMC0_A
X
Sn2
AXR1
0
21
0x1C09 PADCONFIG_37 W20
4
MCAN15_
RX
RGMII2_T RMII2_RX
D1 D1
GPIO0_38 SPI6_CS3 EQEP1_I
MCAN15_
RX
MCASP2_ GPMC0_A GPMC0_A
AXR2 15 DVn_ALE
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
BALL
MUXMODE[15:0] SETTINGS
ESS
OFFSE
T
REGISTER
NAME
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C09 WKUP_PADCON A9
FIG_37
MCU_RGM MCU_RMII
WKUP_GP
IO0_53
4
II1_RD0
1_RXD0
0x1C09 PADCONFIG_38 V14
8
UART2_RX
D
RGMII2_T RMII2_CR
D2 S_DV
GPIO0_39 SPI6_CLK GPMC0_C GPMC0_F UART2_RX MCASP2_
LKOUT CLK_MUX AXR3
OBSCLK2
D
0x1C09 WKUP_PADCON C9
MCU_MDI
O0_MDIO
WKUP_GP
IO0_54
8
FIG_38
0x1C09 PADCONFIG_39 V13
C
UART2_TX
D
RGMII2_T RMII2_RX_
D3 ER
GPIO0_40 SPI6_D0
UART2_TX MCASP2_
AFSX
D
0x1C09 WKUP_PADCON D9
MCU_MDI
O0_MDC
WKUP_GP
IO0_55
C
FIG_39
0x1C0 WKUP_PADCON C13
A0 FIG_40
MCU_SPI0
_CLK
WKUP_GP
IO0_56
MCU_BOO
TMODE00
0x1C0 PADCONFIG_40 U12
A0
RGMII2_T RMII2_TXD
GPIO0_41 SPI6_D1
UART4_RX MCASP2_ GPMC0_A
D ACLKX 13
X_CTL
0
0x1C0 WKUP_PADCON A20
MCU_SPI0
_D0
WKUP_GP
IO0_57
MCU_BOO
TMODE01
A4
FIG_41
0x1C0 PADCONFIG_41 W14
A4
UART8_RX
D
I2C4_SCL
MDIO0_M
DIO
GPIO0_42
TRC_DATA UART8_RX MCASP2_ MCASP2_
22 AFSR AXR4
D
0x1C0 WKUP_PADCON B17
MCU_SPI0
_D1
MCU_TIME
R_IO0
WKUP_GP
IO0_58
MCU_BOO
TMODE02
A8
FIG_42
0x1C0 PADCONFIG_42 W19
A8
UART8_TX SPI1_CS3 I2C4_SDA
D
MDIO0_M
DC
GPIO0_43
TRC_DATA UART8_TX MCASP2_ MCASP2_
23 ACLKR AXR5
D
0x1C0 WKUP_PADCON A19
MCU_SPI0
_CS0
MCU_TIME
R_IO1
WKUP_GP
IO0_59
AC
FIG_43
0x1C0 PADCONFIG_43 U13
AC
GPMC0_C USB0_DR
RGMII4_R
D3
GPIO0_44
SPI0_CS3 UART9_RX
D
LK
VVBUS
0x1C0 WKUP_PADCON B14
WKUP_UA
RT0_RXD
WKUP_GP
IO0_60
B0
FIG_44
0x1C0 PADCONFIG_44 T16
B0
UART0_RX
D
RGMII4_T
XC
GPIO0_47
GPMC0_W
AIT0
0x1C0 PADCONFIG_45 T17
B4
UART0_TX
D
RGMII4_T
D2
GPIO0_48
GPMC0_W
En
0x1C0 WKUP_PADCON A14
WKUP_UA
RT0_TXD
WKUP_GP
IO0_61
B4
FIG_45
0x1C0 PADCONFIG_46 T18
B8
UART1_RX MCAN17_T
TIMER_IO RGMII4_T
6 D3
GPIO0_49
GPMC0_O
En_REn
D
X
0x1C0 WKUP_PADCON A16
MCU_MCA
N0_TX
WKUP_GP
IO0_62
B8
FIG_46
0x1C0 PADCONFIG_47 T20
BC
UART1_TX MCAN17_
TIMER_IO RGMII4_T
7 X_CTL
GPIO0_50
GPMC0_C
Sn0
D
RX
0x1C0 WKUP_PADCON A17
MCU_MCA
N0_RX
WKUP_GP
IO0_63
BC
FIG_47
0x1C0 PADCONFIG_48 W3
C0
SPI0_CS0
UART0_CT
Sn
GPIO0_51
0x1C0 WKUP_PADCON B18
MCU_SPI1 MCU_SPI1
_CLK _CLK
WKUP_GP
IO0_0
MCU_BOO
TMODE03
C0
FIG_48
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
86
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
MUXMODE[15:0] SETTINGS
BALL
NUMB
ER
ESS
OFFSE
T
REGISTER
NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C0 PADCONFIG_49 U5
C4
SPI0_CS1 CPTS0_TS UART0_RT
GPIO0_52
_COMP
Sn
0x1C0 WKUP_PADCON B19
MCU_SPI1 MCU_SPI1
WKUP_GP
IO0_1
MCU_BOO
TMODE04
C4
FIG_49
_D0
_D0
0x1C0 PADCONFIG_50 Y1
C8
SPI0_CLK UART1_CT I2C2_SCL
Sn
GPIO0_53
0x1C0 WKUP_PADCON D14
MCU_SPI1 MCU_SPI1
WKUP_GP
IO0_2
MCU_BOO
TMODE05
C8
FIG_50
_D1
_D1
0x1C0 WKUP_PADCON B21
CC FIG_51
MCU_SPI1 MCU_SPI1
WKUP_GP
IO0_3
_CS0
_CS0
0x1C0 PADCONFIG_51 V4
CC
SPI0_D0
UART1_RT I2C2_SDA
Sn
GPIO0_54
0x1C0 WKUP_PADCON D13
MCU_MCA MCU_MCA MCU_SPI0 MCU_ADC
WKUP_GP
IO0_4
D0
FIG_52
N1_TX
N1_TX
_CS3
_EXT_TRI
GGER0
0x1C0 PADCONFIG_52 T5
D0
SPI0_D1
I2C0_SCL
GPIO0_55
GPIO0_56
0x1C0 PADCONFIG_53 V3
D4
0x1C0 WKUP_PADCON B16
MCU_MCA MCU_MCA MCU_SPI1 MCU_ADC
WKUP_GP
IO0_5
D4
FIG_53
N1_RX
N1_RX
_CS3
_EXT_TRI
GGER1
0x1C0 PADCONFIG_54 W2
D8
I2C0_SDA
GPIO0_57
0x1C0 WKUP_PADCON C14
WKUP_UA WKUP_UA MCU_CPT MCU_I2C1
RT0_CTSn RT0_CTSn S0_HW1T _SCL
SPUSH
WKUP_GP
IO0_6
D8
FIG_54
0x1C0 PADCONFIG_55 U3
DC
ECAP0_IN SYNC0_O CPTS0_RF I2C1_SCL CPTS0_H UART3_RX SPI7_CS0 GPIO0_58
_APWM_O UT
UT
T_CLK
W1TSPUS
H
D
0x1C0 WKUP_PADCON C18
WKUP_UA WKUP_UA MCU_CPT MCU_I2C1
RT0_RTSn RT0_RTSn S0_HW2T _SDA
SPUSH
WKUP_GP
IO0_7
DC
FIG_55
0x1C0 PADCONFIG_56 T3
E0
EXT_REFC SYNC1_O
LK1 UT
I2C1_SDA CPTS0_H UART3_TX SPI7_CLK GPIO0_59
W2TSPUS
H
D
0x1C0 WKUP_PADCON C21
MCU_I2C1 MCU_I2C1 MCU_CPT MCU_I3C0 MCU_TIME
WKUP_GP
IO0_8
E0
FIG_56
_SCL
_SCL
S0_TS_SY _SCL
NC
R_IO6
0x1C0 PADCONFIG_57 V1
E4
TIMER_IO ECAP1_IN SYSCLKO
UART3_CT SPI7_D0
Sn
GPIO0_60 MMC1_SD
CD
0
_APWM_O UT0
UT
0x1C0 WKUP_PADCON C19
MCU_I2C1 MCU_I2C1 MCU_CPT MCU_I3C0 MCU_TIME
WKUP_GP
IO0_9
E4
FIG_57
_SDA
_SDA
S0_TS_CO _SDA
MP
R_IO7
0x1C0 PADCONFIG_58 W1
E8
TIMER_IO ECAP2_IN OBSCLK0
UART3_RT SPI7_D1
Sn
GPIO0_61 MMC1_SD PCIE1_CL
WP KREQn
1
_APWM_O
UT
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
BALL
MUXMODE[15:0] SETTINGS
ESS
OFFSE
T
REGISTER
NAME
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C0 WKUP_PADCON C20
E8 FIG_58
MCU_EXT MCU_EXT MCU_UAR MCU_ADC MCU_CPT MCU_SYS
_REFCLK0 _REFCLK0 T0_TXD _EXT_TRI S0_RFT_C CLKOUT0
GGER0 LK
WKUP_GP
IO0_10
0x1C0 WKUP_PADCON C16
EC FIG_59
MCU_OBS MCU_OBS MCU_UAR MCU_ADC MCU_TIME MCU_I3C0 MCU_CLK WKUP_GP
CLK0
CLK0
T0_RXD
_EXT_TRI R_IO1
GGER1
_SDAPULL OUT0
EN
IO0_11
0x1C0 PADCONFIG_59 N19
EC
MMC1_DA UART7_RX PCIE1_CL TIMER_IO
GPIO0_62 SPI1_CS0 UART0_CT I2C3_SCL UART5_RX
Sn
T3
D
KREQn
0
D
0x1C0 WKUP_PADCON D19
MCU_UAR MCU_SPI0
T0_TXD _CS1
WKUP_GP
IO0_12
MCU_BOO
TMODE08
F0
FIG_60
0x1C0 PADCONFIG_60 N20
F0
MMC1_DA UART7_TX
T2
TIMER_IO
1
GPIO0_63 SPI1_CS1 CPTS0_TS I2C3_SDA UART5_TX
_SYNC
D
D
0x1C0 PADCONFIG_61 N21
F4
MMC1_DA UART7_CT ECAP0_IN TIMER_IO
UART4_RX
D
GPIO0_64 SPI1_CS2 UART5_CT I2C4_SDA UART2_RX
Sn
T1
Sn
_APWM_O
UT
2
D
0x1C0 WKUP_PADCON D20
MCU_UAR MCU_SPI1
T0_RXD _CS1
WKUP_GP
IO0_13
MCU_BOO
TMODE09
F4
FIG_61
0x1C0 PADCONFIG_62 M19
F8
MMC1_DA UART7_RT ECAP1_IN TIMER_IO
UART4_TX
D
GPIO0_65 SPI1_D0
UART5_RT I2C4_SCL UART2_TX
Sn
T0
Sn
_APWM_O
UT
3
D
0x1C0 WKUP_PADCON E20
MCU_UAR MCU_SPI0
T0_CTSn _CS2
MCU_TIME
R_IO8
WKUP_GP
IO0_14
MCU_BOO
TMODE06
F8
FIG_62
0x1C0 WKUP_PADCON E21
FC FIG_63
MCU_UAR MCU_SPI1
T0_RTSn _CS2
MCU_TIME
R_IO9
WKUP_GP
IO0_15
MCU_BOO
TMODE07
0x1C10 PADCONFIG_64 P21
0
MMC1_CL UART8_RX
TIMER_IO
4
UART4_CT
Sn
GPIO0_66 SPI1_CLK UART0_RT I2C6_SDA
Sn
K
D
0x1C10 WKUP_PADCON F20
WKUP_I2C
0_SCL
WKUP_GP
IO0_64
0
FIG_64
0x1C10 PADCONFIG_65 M20
4
MMC1_CM UART8_TX
TIMER_IO
5
UART4_RT
Sn
GPIO0_67 SPI1_D1
I2C6_SCL
D
D
0x1C10 WKUP_PADCON H21
WKUP_I2C
0_SDA
WKUP_GP
IO0_65
4
FIG_65
0x1C10 WKUP_PADCON G21
MCU_I2C0
_SCL
WKUP_GP
IO0_66
8
FIG_66
0x1C10 PADCONFIG_66 U2
8
RESETSTA
Tz
0x1C10 WKUP_PADCON G20
MCU_I2C0
_SDA
WKUP_GP
IO0_67
C
FIG_67
0x1C11 WKUP_PADCON C15
PMIC_PO
WER_EN1
MCU_I3C0
_SDAPULL
EN
WKUP_GP
IO0_68
0
FIG_68
0x1C11 PADCONFIG_68 V2
0
SOC_SAF
ETY_ERR
ORn
0x1C11 WKUP_PADCON G18
MCU_SAF
ETY_ERR
ORn
4
FIG_69
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
88
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
MUXMODE[15:0] SETTINGS
BALL
NUMB
ER
ESS
OFFSE
T
REGISTER
NAME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C11 WKUP_PADCON A18
FIG_70
MCU_RES
ETz
8
0x1C11 PADCONFIG_71 U4
C
TMS
0x1C11 WKUP_PADCON B13
MCU_RES
ETSTATz
WKUP_GP
IO0_79
C
FIG_71
0x1C12 WKUP_PADCON D21
MCU_TIME
R_IO6
WKUP_GP
IO0_77
BOOTMOD
E04
0
FIG_72
0x1C12 PADCONFIG_72 T4
0
USB0_DR
VVBUS
GPIO0_68
0x1C12 WKUP_PADCON B15
TCK
4
FIG_73
0x1C12 PADCONFIG_73 T19
4
PMIC_WA
KE0n
RGMII4_T
D1
GPIO0_1
0x1C12 WKUP_PADCON B20
TRSTn
EMU0
EMU1
8
FIG_74
0x1C12 WKUP_PADCON A13
C
FIG_75
0x1C13 WKUP_PADCON D12
0
FIG_76
0x1C13 WKUP_PADCON H17
MCU_ADC
0_AIN0
4
FIG_77
0x1C13 WKUP_PADCON K18
MCU_ADC
0_AIN1
8
FIG_78
0x1C13 WKUP_PADCON M17
MCU_ADC
0_AIN2
C
FIG_79
0x1C14 WKUP_PADCON L18
MCU_ADC
0_AIN3
0
FIG_80
0x1C14 WKUP_PADCON J18
MCU_ADC
0_AIN4
4
FIG_81
0x1C14 WKUP_PADCON J17
MCU_ADC
0_AIN5
8
FIG_82
0x1C14 WKUP_PADCON K17
MCU_ADC
0_AIN6
C
FIG_83
0x1C15 WKUP_PADCON L17
MCU_ADC
0_AIN7
0
FIG_84
0x1C16 PADCONFIG_89 V15
4
MCAN16_T RMII_REF_
CLK
RGMII4_R
X_CTL
GPIO0_45
GPIO0_46
UART7_TX GPMC0_A
D 14
X
0x1C16 PADCONFIG_90 U21
8
MCAN16_ CLKOUT
RX
RGMII4_T
D0
UART7_RX GPMC0_C AUDIO_EX
D
Sn1
T_REFCLK
1
0x1C17 WKUP_PADCON A15
RESET_R
EQz
4
FIG_93
0x1C17 WKUP_PADCON H20
PORz
8
FIG_94
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-106. Pin Multiplexing (continued)
ADDR
BALL
MUXMODE[15:0] SETTINGS
ESS
OFFSE
T
REGISTER
NAME
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x1C17 WKUP_PADCON E19
FIG_95
MCU_TIME
R_IO7
WKUP_GP
IO0_78
BOOTMOD
E05
C
0x1C18 WKUP_PADCON D18
FIG_96
WKUP_GP
IO0_80
BOOTMOD
E06
0
0x1C18 WKUP_PADCON C17
FIG_97
WKUP_LF
_CLKIN
WKUP_GP
IO0_81
BOOTMOD
E07
4
0x1C18 WKUP_PADCON F19
FIG_98
TDI
8
0x1C18 WKUP_PADCON F21
FIG_99
TDO
C
0x1C19 WKUP_PADCON E18
PMIC_WA MCU_EXT MCU_CPT
WKUP_GP
IO0_84
0
FIG_100
KE1n
_REFCLK0 S0_RFT_C
LK
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
90
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
6.5 Connections for Unused Pins
This section describes the Unused/Reserved balls connection requirements.
备注
All power balls must be supplied with the voltages specified in 节 7.3, Recommended Operating
Conditions, unless otherwise specified in 节6.3, Signal Descriptions.
表6-107. Unused Balls Specific Connection Requirements
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
V7
SERDES0_REXT
V5
USB0_RCALIB
K19
B20
H17
K18
M17
L18
J18
J17
K17
L17
B2
OSC1_XI
TRSTN
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
DDR0_DQS0P
Each of these balls must be connected to VSS through a separate
external pull resistor to ensure these balls are held to a valid logic
low level if unused.
E2
DDR0_DQS1P
M2
DDR0_DQS2P
R2
DDR0_DQS3P
V1
MMC1_SDCD
G15
D16
E17
F17
L14
VMON1_ER_VSYS
VMON2_IR_VCPU
VMON3_IR_VEXT1P8
VMON4_IR_VEXT1P8
VMON5_IR_VEXT3P3
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-107. Unused Balls Specific Connection Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
A18
G19
H20
B15
U4
MCU_RESETZ
MCU_PORZ
PORZ
TCK
TMS
F20
H21
G20
G21
W2
WKUP_I2C0_SCL
WKUP_I2C0_SDA
MCU_I2C0_SDA
MCU_I2C0_SCL
I2C0_SDA
Each of these balls must be connected to the corresponding
power supply through a separate external pull resistor to ensure
these balls are held to a valid logic high level if unused.(1)
V3
I2C0_SCL
U6
EXTINTN
F19
F21
D12
A13
B1
TDI
TDO
EMU1
EMU0
DDR0_DQS0N
DDR0_DQS1N
DDR0_DQS2N
DDR0_DQS3N
VPP_CORE
E1
M1
R1
N17
E11
P20
AA8
AA9
AA11
AA12
W11
W12
W8
VPP_MCU
MMC0_CALPAD
SERDES0_REFCLK_N
SERDES0_REFCLK_P
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
SERDES0_RX1_N
SERDES0_RX1_P
SERDES0_TX1_N
SERDES0_TX1_P
SERDES0_RX2_N
SERDES0_RX2_P
SERDES0_TX2_N
SERDES0_TX2_P
SERDES0_RX3_N
SERDES0_RX3_P
SERDES0_TX3_N
SERDES0_TX3_P
W9
Each of these balls must be left unconnected if unused.
Y10
Y11
Y7
Y8
AA5
AA6
W5
W6
Y4
Y5
(1) To determine which power supply is associated with any IO refer to 表6-1, Pin Attributes.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
92
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表6-108. Reserved Balls Specific Connection Requirements
BALLS
CONNECTION REQUIREMENTS
These balls do not exist on the package.
These balls must be left unconnected.
A21 / AA21 / K8 / K9 / K10 / L8 / L9 / L10
H18 / F18 / N18 / L20 / K20 / J20 / V8 / V10 / E5 / F6
备注
All other unused signal balls without Pad Configuration Register can be left unconnected.
备注
All other unused signal balls with a Pad Configuration Register can be left unconnected with their
multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on
the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This may be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which are
only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be
required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state
which could damage the IO cell.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
UNIT
VDD_CORE
VDD_MCU
MAIN domain core supply
MCUSS core supply
1.05
1.05
1.05
1.05
1.05
V
V
V
V
V
VDD_CPU
CPU core supply
VDD_MCU_WAKE1
VDD_WAKE0
Core supply for MCU WAKE function
Core supply for MAIN domain WAKE function which
includes all "CANUART" IO.
VDDA_0P8_DLL_MMC0
VDDAR_CORE
MMC0 DLL analog supply
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
2.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MAIN domain RAM supply
VDDAR_MCU
MCUSS RAM supply
VDDAR_CPU
CPU RAM supply
VDDA_0P8_SERDES0
VDDA_0P8_SERDES0_C
VDDA_0P8_USB
VDDA_0P8_PLL_DDR
VDDA_1P8_USB
VDDA_1P8_SERDES0
VDDA_3P3_USB
VDDA_MCU_PLLGRP0
VDDA_PLLGRP0
VDDA_PLLGRP4
VDDA_PLLGRP6
VDDA_PLLGRP8
VDDA_WKUP
SERDES0 analog supply low
SERDES0 clock supply
USB0 0.8 V analog supply
DDR PLL analog supply
USB0 1.8 V analog supply
SERDES0 analog supply high
USB0 3.3 V analog supply
2.2
3.8
Analog supply for MCU PLL Group 0
Analog supply for MAIN PLL Group 0
Analog supply for MAIN PLL Group 4
Analog supply for MAIN PLL Group 6
Analog supply for MAIN PLL Group 8
Oscillator supply for WKUP domain
ADC analog supply
2.2
2.2
2.2
2.2
2.2
2.2
VDDA_ADC_MCU
VDDA_MCU_TEMP
VDDA_POR_WKUP
VDDA_TEMP0
2.2
Analog supply for temperature sensor 0 in MCU domain
WKUP domain analog supply
Analog supply for temperature sensor 0
Analog supply for temperature sensor 1
DDR inteface power supply
2.2
2.2
2.2
VDDA_TEMP1
2.2
VDDS_DDR(10)
1.2
VDDS_DDR_BIAS(10)
VDDS_DDR_C(10)
VDDS_MMC0
Bias supply for LPDDR4
1.2
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
1.2
2.2
VDDA_OSC1
HFOSC1 supply
2.2
VDDSHV0_MCU
IO supply MCUSS general IO group, and MCU and
MAIN domain warm reset pins
3.8
VDDSHV0
IO supply for MAIN domain general
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3.8
3.8
V
V
V
V
V
V
V
V
VDDSHV1_MCU
VDDSHV2_MCU
VDDSHV2
IO supply for MCUSS IO group 1
IO supply for MCUSS IO group 2
3.8
IO supply for MAIN domain IO group 2
IO supply for MAIN domain IO group 5
Supply voltage range for CORE EFUSE domain
Supply voltage range for MCU EFUSE domain
Voltage range for USB VBUS comparator input
3.8
VDDSHV5
3.8
VPP_CORE
VPP_MCU
1.89
1.89
3.6
USB0_VBUS(9)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
94
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
MAX
UNIT
I2C0_SCL, I2C0_SDA, WKUP_I2C0_SCL,
WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA,
EXTINTn
3.8
V
–0.3
MCU_PORz, PORz
3.8
V
V
–0.3
Steady State Max. Voltage at
all fail-safe IO pins
VMON2_IR_VCPU
-0.3
1.05
VMON3_IR_VEXT1P8, VMON4_IR_VEXT1P8,
VMON1_ER_VSYS(8)
2.2
3.8
V
V
V
–0.3
–0.3
–0.3
VMON5_IR_VEXT3P3
All other IO pins
Steady State Max. Voltage at
all other IO pins(3)
IO supply voltage +
0.3
Transient Overshoot and
Undershoot specification at
IO pin
20% of IO supply voltage for up to 20% of signal period
(see 图7-1, IO Transient Voltage Ranges)
0.2 × VDD(6)
V
Latch-up Performance, Class I-Test
II (125°C)(4)
100
1.5 × VDD(7)
+150
mA
V
–100
NA
Over-Voltage (OV) Test
Storage temperature
(5)
TSTG
-55
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the 节7.3, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage
range, including power supply ramp-up and ramp-down sequences.
(4) For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.
(5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends
returning to ambient room temperature before usage.
(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(7) An external resistor divider is required to create the VMON input value that triggers with VTH = 0.45 when the VSYS level reaches the
minimum allowed threshold. A series resistor R2 (VMON_ER_VSYS = VSYS × R1 / (R1 + R2)) of at least 10kΩ is recommended to limit
current.
(8) The VMON1_ER_VSYS pin provides a way to monitor the system power supply. For more information, see 节9.3.4 System Power
Supply Monitor Design Guidelines.
(9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.3.3, USB VBUS
Design Guidelines.
(10) A single 1.1V source must drive all three VDDS_DDR, VDDS_DDR_BIAS, VDDS_DDR_C supplies.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The I2C0_SCL, I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,
MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn, MCU_PORz, PORz, VMON1_ER_VSYS, VMON2_IR_VCPU,
VMON3_IR_VEXT1P8, VMON4_IR_VEXT1P8, VMON5_ER_VEXT3P3 are the only fail-safe IO terminals. All
other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the
Steady State Max. Voltage at all IO pins parameter in 节7.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A. Tovershoot + Tundershoot < 20% of Tperiod
图7-1. IO Transient Voltage Ranges
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
All pins
V(ESD)
Electrostatic discharge
V
Corner pins (A1,
AJ29)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
VDD_CORE(3)
DESCRIPTION
MIN(1)
0.76(1)
0.76(1)
0.76(1)
NOM
0.8
MAX(1)
0.84(1)
0.89(1)
0.84(1)
UNIT
Boot/Active voltage for MAIN domain core supply
Boot/Active voltage for MCUSS core supply
V
V
V
VDD_MCU
VDD_CPU
0.8
Boot voltage for CPU core supply, applied at cold
power up event
0.8
Active voltage for CPU core supply, after AVS mode
enabled in software
AVS(5)-5%
AVS(5) AVS(5)+5%
V
(1)
(1)
VDD_CPU AVS Range
VDD_MCU_WAKE1
VDD_WAKE0
Efuse valid voltage range for VDD_CPU voltage
Core supply for MCU WAKE function
0.6
0.76
0.76
0.9
V
V
V
0.8
0.8
0.89
0.89
Core supply for MAIN domain WAKE function which
includes all "CANUART" IO.
VDDA_0P8_DLL_MMC0
VDDAR_CORE
MMC PLL analog supply
Main domain RAM supply
MCUSS RAM supply
0.76
0.81
0.81
0.81
0.76
0.76
0.76
1.71
1.71
0.8
0.85
0.85
0.85
0.8
0.84
0.89
0.89
0.89
0.84
0.84
0.84
1.89
1.89
V
V
V
V
V
V
V
V
V
VDDAR_MCU
VDDAR_CPU
CPU RAM supply
VDDA_0P8_SERDES0(3)
VDDA_0P8_SERDES0_C(3)
VDDA_0P8_USB(3)
VDDA_1P8_USB
SERDES0 analog supply low
SERDES0-1 clock supply
USB 0.8v analog supply
USB 1.8v analog supply
SERDES0 analog supply high
0.8
0.8
1.8
VDDA_1P8_SERDES0
1.8
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
96
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
3.14
1.71
1.71
1.71
1.71
1.71
1.71
1.71
0.76
1.71
NOM
3.3
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.8
1.8
MAX(1)
3.46
1.89
1.89
1.89
1.89
1.89
1.89
1.89
0.84
1.89
UNIT
V
VDDA_3P3_USB
USB 3.3v analog supply
VDDA_MCU_PLLGRP0
VDDA_PLLGRP0
VDDA_PLLGRP4
VDDA_PLLGRP6
VDDA_PLLGRP8
VDDA_WKUP
Analog supply for MCU PLL Group 0
Analog supply for MAIN PLL Group 0
Analog supply for MAIN PLL Group 4
Analog supply for MAIN PLL Group 6
Analog supply for MAIN PLL Group 8
Oscillator supply for WKUP domain
ADC analog supply
V
V
V
V
V
V
VDDA_ADC_MCU
VDDA_0P8_PLL_DDR
VDDA_MCU_TEMP
V
DDR PLL analog supply
V
Analog supply for temperature sensor 0 in MCU
domain
V
VDDA_POR_WKUP
VDDA_TEMP0
VDDA_TEMP1
VDDS_DDR(2)
VDDS_DDR_BIAS(2)
VDDS_DDR_C(2)
VDDS_MMC0
VDDA_OSC1
VDDA_*
WKUP domain analog supply
Analog supply for temperature sensor 0
Analog supply for temperature sensor 1
DDR inteface power supply
1.71
1.71
1.71
1.05
1.05
1.05
1.71
1.71
1.8
1.8
1.8
1.1
1.1
1.1
1.8
1.8
1.89
1.89
1.89
1.15
1.15
1.15
1.89
1.89
25
V
V
V
V
Bias supply for LPDDR4
V
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
V
V
HFOSC1 supply
V
Peak to Peak Noise for all VDDA inputs
mV
V
VDDSHV0
IO supply for main domain
general
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.71
3.14
1.71
3.14
1.8
3.3
1.8
3.3
1.89
3.46
1.89
3.46
V
VDDSHV0_MCU
IO supply MCUSS general IO
group, and MCU and Main
domain warm reset pins
V
V
VDDSHV1_MCU
VDDSHV2
IO supply for MCUSS IO group 1 1.8-V operation
3.3-V operation
1.71
3.14
1.71
3.14
1.71
3.14
1.71
3.14
0
1.8
3.3
1.89
3.46
1.89
3.46
1.89
3.46
1.89
3.46
3.46
V
V
IO supply for main domain IO
group 2
1.8-V operation
3.3-V operation
1.8
V
3.3
V
VDDSHV2_MCU
VDDSHV5
IO supply for MCUSS IO group 2 1.8-V operation
3.3-V operation
1.8
V
3.3
V
IO supply for main domain IO
group 5
1.8-V operation
3.3-V operation
1.8
V
3.3
V
USB0_VBUS
USB0_ID
VSS
Voltage range for USB VBUS comparator input
Voltage range for the USB ID input
Ground
See(6)
See(4)
0
V
V
V
TJ
Operating junction temperature
range
Automotive
Extended
125
105
90
°C
°C
°C
–40
–40
0
Commercial
(1) For all VDD* supply inputs, the voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any
amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.
This is required for all supply inputs, but special care should be given to the VDD_CORE, VDD_MCU, and VDD_CPU domains which
have higher transient current demand compared to other rails.
(2) A single 1.1-V source must drive all three VDDS_DDR, VDDS_DDR_BIAS, VDDS_DDR_C supplies. These supplies are required to
still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.
(3) A single 0.8-V source must drive the VDD_CORE and VDDA_0P8_ PHY input supplies. Also, include Analog filter components on the
individual VDDA_0P8_ PHY input supplies for interfaces that are used in the system.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
(4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ωor greater than 100 kΩ. The terminal should
be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any
external voltage source.
(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager
section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.3.3, USB VBUS
Design Guidelines
7.4 Power-On-Hours (POH)
IP1 2 3
VOLTAGE (V) (MAX)
FREQUENCY (MHz)
(MAX)
VOLTAGE DOMAIN
Tj(°C)
POH
All
100%
All
All
All
All Supported OPPs
All Supported OPPs
All Supported OPPs
Automotive -40°C to
125°C
20000
All
100%
100%
Extended -40°C to
105°C
100000
100000
All
Commercial 0°C to
90°C
1. This information is provided solely for your convenience and does not extend or modify the warranty
provided under TI's standard terms and conditions for TI semiconductor products.
2. Unless specified in the table above, all voltage domains and operating conditions are supported in the device
at the noted temperatures.
3. POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in
a reduction in POH.
4. Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C,
65%@70°C, 20%@110°C, and 10%@125°C.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
98
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.5 Operating Performance Points
This section describes the maximum operating conditions of the device in 表 7-1. This section also contains the
description of each Operating Performance Point (OPP) for processor clocks and device core clocks in 表7-2.
表7-1. Speed Grade Maximum Frequency
MAXIMUM FREQUENCY (MHz)
DEVICE
A72SS0
2000
1500
1000
750
R5FSS0
1000
1000
1000
500
MCU_R5FSS0
CBASS0
DMSC
333
LPDDR4(1)
DRA821xT
DRA821xL
DRA821xE
DRA821xC
1000
500
1600 (DDR-3200)
1600 (DDR-3200)
1600 (DDR-3200)
1600 (DDR-3200)
1000
500
333
1000
500
333
1000
500
333
(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. TI
strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,
PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout
Guidelines for details.
表7-2. Supported OPP vs Max Frequency
see (1) (2)
MAXIMUM FREQUENCY(MHz)
CLOCK
OPP_LOW(4)
1000
OPP_NOM(3)
2000
MPU_CLK (A72SS0)
MSMC_CLK
500
1000
1066 (2133 MT/s)
or
DDRn_CLKP/DDRn_CKN
1600 (3200 MT/s)
1333 (2666 MT/s)(5)
(1) OPP and VDD_CPU voltage should be selected/set at boot time. DVFS is not supported.
(2) Frequency must be limited based on the lower frequency constraint from this table and Speed Grade Maximum Frequency. For
example, the T speed grade can operate A72SS/MSMC at 2 GHz/1GHz or 1 GHz/500 MHz. A72SS/MSMC at 2 GHz/1GHz operation
must use OPP_NOM. A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage. Similarly, the E speed
grade can operate A72SS/MSMC at a maximum of 1 GHz/500 MHz. In this case, OPP_NOM or OPP_LOW voltage is allowed (though
OPP_LOW voltage is recommended to reduce power consumption).
(3) OPP_NOM AVS voltage for VDD_CPU should be set based on the OPP_1 register setting.
(4) If OPP_0 is not equal to 0, OPP_LOW AVS voltage for VDD_CPU should be set based on the OPP_0 register setting. If OPP_0 is
equal to 0, OPP_1 register setting should be used.
(5) DDR can be configured for up to 2666 MT/s in OPP_LOW. 2132 MT/s is recommended in OPP_LOW as it more closely matches the
MPU_CLK scaling and also saves power compared to 2666 MT/s.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.6 Electrical Characteristics
备注
The interfaces or signals described in 节 7.6.10 through 节 7.6.10 correspond to the interfaces or
signals available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.6.1 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, EXTINTN
BALL NUMBERS: H21 / F20 / G20 / G21 / W2 / V3 / U6
1.8 V MODE
VIL
Input Low Voltage
0.3 ×
V
V
VDDSHV(1)
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
0.3 ×
VDDSHV(1)
0.7 ×
V
VDDSHV(1)
Input High Voltage Steady State
Input Hysteresis Voltage
0.7 ×
V
VDDSHV(1)
0.1 ×
mV
VDDSHV(1)
IIN
Input Leakage Current.
Output Low Voltage
VI = 1.8 V or 0 V
±10
µA
V
VOL
0.2 ×
VDDSHV(1)
IOL
Low Level Output Current
VOL(MAX)
10
mA
3.3 V MODE (2)
VIL
Input Low Voltage
0.3 ×
V
V
VDDSHV(1)
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
0.25 ×
VDDSHV(1)
0.7 ×
V
VDDSHV(1)
Input High Voltage Steady State
Input Hysteresis Voltage
0.7 ×
V
VDDSHV(1)
0.05 ×
mV
VDDSHV(1)
IIN
Input Leakage Current.
Output Low Voltage
VI = 3.3 V or 0 V
VOL(MAX)
±10
0.4
µA
V
VOL
IOL
Low Level Output Current
10
mA
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表
6-1, POWER column.
(2) I2C HS-mode is not supported when operating the IO in 3.3 V mode.
7.6.2 Fail-Safe Reset (FS Reset) Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_PORz, PORz
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
100 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NUMBERS: G19 / H20
VIL
Input low-level threshold
0.3 ×
V
V
V
V
VDDSHV(1)
VILSS
VIH
Input low-level threshold steady state
Input high-level threshold
0.3 ×
VDDSHV(1)
0.7 ×
VDDSHV(1)
VIHSS
Input high-level threshold steady state
0.7 ×
VDDSHV(1)
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current
200
mV
µA
VI = 1.8 V or 0 V
±10
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Pin
Attributes, POWER column.
7.6.3 HFOSC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
HIGH FREQUENCY OSCILLATOR
BALL NAMES: OSC1_XI, WKUP_OSC0_XI
BALL NUMBERS: K19 / K21
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
Low-level input voltage
Input Hysteresis Voltage
0.65 ×
V
V
VDDSHV(1)
VIL
0.35 ×
VDDSHV(1)
VHYS
49
mV
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表
6-1, POWER column.
7.6.4 eMMCPHY Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK
BALL NUMBERS: R16 / P17 / R18 / R20 / R19 / P16 / R21 / T21 / P20 / R17 / P19 / P18
VIL
Input Low Voltage
0.35 ×
V
VDDSHV(1)
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.20
V
V
0.65 ×
VDDSHV(1)
VIHSS
IIN
Input High Voltage Steady State
Input Leakage Current.
Tri-state Output Leakage Current.
Pull-up Resistor
1.4
V
μA
μA
kΩ
kΩ
V
VI = 1.8 V or 0 V
VO = 1.8 V or 0 V
±10
±10
25
IOZ
RPU
RPD
VOL
VOH
15
15
20
20
Pull-down Resistor
25
Output Low Voltage
0.30
Output High Voltage
VDDSHV(1)
-
V
0.30
IOL
IOH
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
2
mA
mA
2
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 101
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SRI
Input Slew Rate
5E+8
V/s
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表
6-1, POWER column.
7.6.5 SDIO Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0]
BALL NUMBERS: P21 / M20 / M19 / N21 / N20 / N19
1.8 V MODE
VIL
Input Low Voltage
0.58
0.58
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
1.27
1.7
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
V
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
VOH
40
40
50
50
Pull-down Resistor
60
Output Low Voltage
0.45
Output High Voltage
VDDSHV(1)
-
V
0.45
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
4
4
mA
mA
IOH
3.3 V MODE
VIL
Input Low Voltage
0.25 ×
V
V
V
V
VDDSHV(1)
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.15 ×
VDDSHV(1)
0.625 ×
VDDSHV(1)
VIHSS
Input High Voltage Steady State
0.625 ×
VDDSHV(1)
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
40
40
50
50
Pull-down Resistor
Output Low Voltage
60
0.125 ×
VDDSHV(1)
VOH
Output High Voltage
0.75 ×
V
VDDSHV(1)
IOL
IOH
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
6
mA
mA
10
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表
6-1, POWER column.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
102 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.6.6 ADC12BT Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0]
BALL NUMBERS: J18 / H17 / K18 / J17 / M17 / K17 / L18 / L17
VMCU_ADC0_AIN[7:0]
Full-scale Input Range
Differential Non-Linearity
Integral Non-Linearity
Gain Error
VSS
-1
VDDA(2)
V
DNL
0.5
±1
±2
±2
5.5
70
4
LSB
LSB
LSB
LSB
pF
INL
±4
LSBGAIN-ERROR
LSBOFFSET-ERROR
CIN
Offset Error
Input Sampling Capacitance
Signal-to-Noise Ratio
SNR
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
dB
THD
Total Harmonic Distortion
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
75
80
69
dB
dB
dB
Ω
SFDR
Spurious Free Dynamic Range
Signal-to-Noise Plus Distortion
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
SNR(PLUS)
RMCU_ADC0_AIN[0:7]
IIN
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
Input Impedance of
MCU_ADC0_AIN[7:0]
f = input frequency
[1/((65.97 × 10–-12) ×
fSMPL_CLK)]
Input Leakage
MCU_ADC0_AIN[7:0] = VSS
5
μA
μA
MCU_ADC0_AIN[7:0] =
VDDA_ADC_MCU
10
Sampling Dynamics
FSMPL_CLK
tC
SMPL_CLK Frequency
Conversion Time
60
13
MHz
ADC0 SMPL_CLK
Cycles
tACQ
Acquisition time
2
257 ADC0 SMPL_CLK
Cycles
TR
Sampling Rate
ADC0 SMPL_CLK = 60 MHz
4
MSPS
dB
CCISO
Channel to Channel Isolation
100
General Purpose Input Mode (1)
VIL
Input Low Voltage
0.35 × VDDA(2)
0.35 × VDDA(2)
V
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.65 × VDDA(2)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
103
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.65 × VDDA(2)
200
TYP
MAX
UNIT
V
VIHSS
VHYS
II
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current
mV
μA
VI = 1.8 V or 0 V
2
(1) MCU_ADC0 can be configured to operate in General Purpose Input mode, where all MCU_ADC0_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0_CTRL
register (gpi_mode_en = 1).
(2) VDDA stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表6-1, POWER column.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
104
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.6.7 LVCMOS Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BALL NAMES: ALL other IOs
BALL NUMBERS: ALL other IOs
1.8-V MODE
VIL
Input Low Voltage
0.35 × VDD(1)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.3 × VDD(1)
0.65 × VDD(1)
0.85 × VDD(1)
150
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
V
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
30
RPU
RPD
VOL
VOH
IOL
15
15
22
22
Pull-down Resistor
30
Output Low Voltage
0.45
Output High Voltage
VDD(1) - 0.45
V
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
3
3
mA
mA
IOH
3.3-V MODE
VIL
Input Low Voltage
0.8
0.6
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
2.0
2.0
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-down Resistor
V
150
mV
µA
kΩ
V
VI = 3.3 V or 0 V
±10
30
RPD
VOL
VOH
IOL
15
22
Output Low Voltage
0.4
Output High Voltage
2.4
5
V
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
mA
mA
IOH
6
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表
6-1, POWER column.
7.6.8 USB2PHY Electrical Characteristics
备注
USB0 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification
dated April 27, 2000 including ECNs and Errata as applicable.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 105
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.6.9 SERDES Electrical Characteristics
备注
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal
termination enabled, as described by parameter VREFCLK_TERM in 表 7-3, SERDES REFCLK Electrical
Characteristics. Internal termination is enabled by default and must be disabled before applying a
reference clock signal that exceeds the limits defined by VREFCLK_TERM. External termination should
always be enabled on the source side.
表7-3. SERDES REFCLK Electrical Characteristics
Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: SERDES0_REFCLK_P, SERDES0_REFCLK_N
BALL NUMBERS:AA9 / AA8
VREFCLK_TER Single ended voltage threshold at the reference clock
400
mV
pin when internal termination is enabled
M
RTERM
Internal termination
40
50
62.5
Ω
备注
The SerDes USB interface is compliant with the USB3.1 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision
1.0 , July 26, 2013.
备注
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3
Clause 70.
备注
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
备注
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.
备注
USXGMII supports IEEE 802.3 TX and RX electrical characteristics of Clause 72-7 and Annex 69B.
IEEE 802.3 Tables 72-7 and 72-8 are not required by USXGMII since these tables are associated with
training (Clause 72-6), which is not a requirement of USXGMII.
The pre, main, and post cursors should be set by using BER sweeps.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
106 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
备注
The XFI interface electrical characteristics are compliant with the INF-8077_XFP_XFI_10Gbps_1X
specification revision 4.5, August 31, 2005.
7.6.10 DDR Electrical Characteristics
备注
The DDR interface is compatible with JEDEC JESD209-4B standards compliant LPDDR4 SDRAM
devices.
7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only
for High-Security Devices.
7.7.1 Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
See 节7.3
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
V
VDD_MCU
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
V
V
See 节7.3
VPP_CORE
Supply voltage range for the eFuse ROM
domain during normal operation
N/A
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.71
1.71
1.8
1.8
1.89
VPP_MCU
SR(VPP)
Supply voltage range for the eFuse ROM
domain during normal operation
N/A
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.89
V
VPP Slew Rate
6E + 4
V/s
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family
is a example device that meets the supply voltage range needed for VPP_CORE and VPP_MCU.
7.7.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.
• The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up
sequence (for more details, see 节7.9.2).
7.7.3 Programming Sequence
Programming sequence for OTP eFuses:
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP_CORE and
VPP_MCU terminals during power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
• Apply the voltage on the VPP_CORE and VPP_MCU terminals according to the specification in 节7.7.1.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP_CORE and VPP_MCU
terminals.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 107
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.7.4 Impact to Your Hardware Warranty
You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You
acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure
may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device
specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI
DEVICES THAT HAVE BEEN eFUSED.
7.8 Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in 节7.3, Recommended Operating Conditions.
7.8.1 Thermal Resistance Characteristics
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
ALM PACKAGE
NO.
PARAMETER
DESCRIPTION
AIR FLOW
(m/s)(2)
°C/W(1)(3)
T1
0.54
2.9
12.8
9.1
8.1
7.5
0.5
0.3
0.3
0.3
2.8
2.8
2.7
2.7
N/A
N/A
0
Junction-to-case
Junction-to-board
Junction-to-free air
RΘJC
T2
RΘJB
T3
T4
1
RΘJA
T5
Junction-to-moving air
2
T6
3
T7
0
T8
1
Junction-to-package top
ΨJT
T9
2
T10
T11
T12
T13
T14
3
0
1
Junction-to-board
ΨJB
2
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
108 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9 Timing and Switching Characteristics
备注
The timings presented in this section are valid when the DRV_STR (Drive Strength) control in the
associated PADCONFIG registers are set to the default “0h –Nominal (recommended)”value.
7.9.1 Timing Parameters and Information
The timing parameter symbols used in 节 7.9 are created in accordance with JEDEC Standard 100. To shorten
the symbols, some pin names and other related terminologies have been abbreviated in 表7-4:
表7-4. Timing Parameters Subscripts
SYMBOL
PARAMETER
c
d
Cycle time (period)
Delay time
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 109
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.2 Power Supply Sequencing
This section describes power supply sequencing required to ensure proper device operation. The power supply
names described in this section comprise a superset of a family of compatible devices. Some members of this
family will not include a subset of these power supplies and their associated device modules.
7.9.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 100 mV/µs. For instance, as shown in 图 7-2, TI recommends
having the supply ramp slew for a 1.8-V supply of more than 18 μs.
图7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
slew rate < 100 mV/µs
slew > (supply value) / (100 mV/µs)
or
supply value x 10 µs
J7VC_ELCH_03
图7-2. Power Supply Slew and Slew Rate
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
110
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing
图 7-3 describes the primary power-up sequencing when similar MCU and Main voltage domains are combined
into common power rails. Combining MCU and Main voltage domains makes an SoC’s MCU and Main
processor sub-systems operational dependent on common power rails. The main reason an SoC’s PDN
design may want to group MCU and Main voltage domains is simplify the PDN by reducing total number of
power rails and sources. This simplified PDN would be used in systems that do not desire independent MCU and
Main processor sub-system operations.
T0
T1
T2
T3
T4
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV2, VDDSHV5(D) (B), VDDA_3P3_USB(E)
)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV2, VDDSHV5(D) (C),VDDS_MMC0
)
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,
VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)(F)
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(H)
VDD_MCU(I), VDD_MCU_WAKE1, VDD_CORE,
VDD_WAKE0, VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB,
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(I)
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C,
OSC1_XI, OSC1_XO
(optional)
WKUP_OSC0_XI, WKUP_OSC0_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](J)
MCU_PORz(J)(K)
Valid Configuration
PORz(J)(K)
J7VCL_ELCH_01
A. Terminology:
•
•
•
•
Primary = Essential power up sequence of all voltage domains to full active state.
VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
Ramp Up = Voltage supply transition time from off condition to VOPR MIN
.
Domain_“n”= multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0,
VDDSHV1, VDDSHV2 …VDDSHV6)
•
Domain_“xxx”= different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =
VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Time stamps:
Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping.
Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
111
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
T0 –All 3.3-V voltages start supply ramp-up to VOPR MIN. (0 ms)
T1 –All 1.8-V voltages start supply ramp-up to VOPR MIN. (0.5 ms)
T2 –All core voltages start supply ramp-up to VOPR MIN. (1.0 ms)
T3 –All RAM array voltages start supply ramp-up to VOPR MIN. (1.5 ms)
T4 –OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (11 ms)
B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.
D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed
SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be
grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO
1.8-V power rail.
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,
then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-
line supply filter is allowed.
H. VDDA_0P8_<dll/pll> are 0.8 V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively
impact jitter performance of PLL and DLL signals.
I.
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or
0.85-V RAM array (VDDAR_xxx) domains.
J. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced
to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power-up sequence.
K. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached
depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10- ms elapsed time defined by (T4
–T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock
generator) and PCB designs.
图7-3. Combined MCU and Main Domains, Primary Power-Up Sequence
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
112
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
图7-4 describes the device power-down sequencing.
T0
T1
T2
T3
T4
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV2, VDDSHV5(D) (B), VDDA_3P3_USB(E)
)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV2, VDDSHV5(D) (C),VDDS_MMC0
)
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,
VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)(F)
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(H)
VDD_MCU(I), VDD_MCU_WAKE1, VDD_CORE,
VDD_WAKE0, VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB,
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(I)
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
TΔ1
OSC1_XI, OSC1_XO
(optional)
WKUP_OSC0_XI, WKUP_OSC0_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
MCU_PORz(J)
Valid Configuration
PORz(J)
J7VCL_ELCH_02
A. Terminology:
•
•
•
•
Primary = Essential power down sequence of all voltage domains to complete off state.
VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
Ramp-down = voltage supply transition time from VOPR MIN to off condition.
Domain_“n”= multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0,
VDDSHV1, VDDSHV2 …VDDSHV6)
•
Domain_“xxx”= different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =
VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Time stamps:
Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping.
Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
T0 –MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)
T1 –Main DDR, SRAM Core and SRAM CPU power domains start ramp-down. (0.5 ms)
T2 –All core voltages start supply ramp-down. (2.5 ms)
T3 –All 1.8V voltages start supply ramp-down. (3.0 ms)
T4 –All 3.3-V voltages start supply ramp-down. (3.5 ms)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
113
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.
D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed
SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be
grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO
1.8-V power rail.
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,
then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-
line supply filter is allowed.
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively
impact jitter performance of PLL and DLL signals.
I.
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or
0.85-V RAM array (VDDAR_xxx) domains.
J. MCU_PORz and PORz must be asserted low for TΔ1 = 200 μs min to ensure SoC resources enter into safe state before any voltage
begins to ramp down.
图7-4. Combined MCU and Main Domains, Primary Power-Down Sequence
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
114
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.2.4 Independent MCU and Main Domains Power- Up Sequencing
Independent MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to
operate independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and
Main processor functionality. First is to provide flexibility to enable SoC low power modes that can significant
reduce SoC power dissipation when processor operations are not needed. Second is to enable robustness to
gain freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems
which is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number
of additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels. If
only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO
signaling is desired, then 4 additional power rails could be needed.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
115
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
T1
T2
T3
T4
T0
Note 1
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(C)
Note 1
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(E), VDDSHV6)(C),VDDA_3P3_USB(F)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(D)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(E), VDDSHV6)(D), VDDS_MMC0
(VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP)(G)
VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0,
(VDDA_1P8_SERDES, VDDA_1P8_USB)(H)
VDD_MCU(J),VDD_MCU_WAKE1, VDDAR_MCU
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(I)
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB
VDDAR_CORE, VDDAR_CPU
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
OSC1_XI, OSC1_XO
(optional)
WKUP_OSC0_XI, WKUP_OSC0_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](K)
MCU_PORz(K)(L)
Valid Configuration
PORz(K)(L)
J7VCL_ELCH_03
A. Terminology:
•
•
•
•
Primary = Essential power up sequence of all voltage domains to full active state.
VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
Ramp Up = Voltage supply transition time from off condition to VOPR MIN
.
Domain_“n”= multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0,
VDDSHV1, VDDSHV2 …VDDSHV6)
•
Domain_“xxx”= different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =
VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
116
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Time stamp markers show approximate elapsed times that are dependent upon PDN feature set, component
selection and power mapping. Values shown are typical for PDNs supporting independent MCU and Main
voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
T0 –All 3.3V voltages start supply ramp-up to VOPR MIN. (0 ms)
T1 –All 1.8V voltages start supply ramp-up to VOPR MIN. (2 ms)
T2 –All core voltages start supply ramp-up to VOPR MIN. (3 ms)
T3 –All RAM array voltages start supply ramp-up to VOPR MIN. (4 ms)
T4 –OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)
B. VDDSHVx 3.3V IO domains may have additional ramp-up delay due to following:
1. Minimizing PMIC power dissipation during low power mode that includes disabling PMIC’s VIO_IN supply for GPIO output
buffers.
2. PDN component turn-on and ramp-up delays needed to isolate MCU and Main IO domains
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.
D. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.
E. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed
SD card operations. If SD card is not needed or standard data rates with fixed 3.3 V operation is acceptable, then domain can be
grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO
1.8-V power rail.
F. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,
then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.
G. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
H. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-
line supply filter is allowed.
I.
VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively
impact jitter performance of PLL and DLL signals.
J. VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or
0.85-V RAM array (VDDAR_xxx) domains.
K. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced
to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence.
L. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached
depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10-ms elapsed time defined by (T4
–T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock
generator) and PCB designs.
图7-5. Independent MCU and Main Domains, Primary Power-Up Sequence
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
117
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing
图7-6 describes the device power-down sequencing.
T4
T0
T1
T2
T3
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(B)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(D), VDDSHV6)(B),VDDA_3P3_USB(E)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(C)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(D), VDDSHV6)(C), VDDS_MMC0
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP,
VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP)(F)
VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP01, VDDA_TEMP0,
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)
VDD_MCU(8) VDD_MCU_WAKE1, VDDAR_MCU
VDD_CPU
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(H)
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB
VDDAR_CORE, VDDAR_CPU
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
TΔ1
OSC1_XI, OSC1_XO
(optional)
WKUP_OSC0_XI, WKUP_OSC0_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
MCU_PORz(J)
Valid Configuration
PORz(J)
J7VCL_ELCH_04
A. Terminology:
•
•
•
•
Primary = Essential power down sequence of all voltage domains to complete off state.
VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
Ramp-down = voltage supply transition time from VOPR MIN to off condition.
Domain_“n”= multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0,
VDDSHV1, VDDSHV2 …VDDSHV6)
•
Domain_“xxx”= different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =
VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Time stamps:
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
118
Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping.
Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
T0 –MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)
T1 –Main DDR, SRAM Core and SRAM CPU power domains start ramp-down. (0.5 ms)
T2 –All core voltages start supply ramp-down. (2.5 ms)
T3 –All 1.8V voltages start supply ramp-down. (3.0 ms)
T4 –All 3.3-V voltages start supply ramp-down. (3.5 ms)
B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.
D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed
SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be
grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO
1.8-V power rail.
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,
then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-
line supply filter is allowed.
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively
impact jitter performance of PLL and DLL signals.
I.
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or
0.85-V RAM array (VDDAR_xxx) domains.
J. MCU_PORz and PORz must be asserted low for TΔ1 = 200 μs min to ensure SoC resources enter into safe state before any voltage
begins to ramp down.
图7-6. Independent MCU and Main Domains, Primary Power- Down Sequencing
7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
Entry into MCU Only state is accomplished by executing a power down sequence except for the 4 MCU domains
that remain energized. Exit from MCU Only state is accomplished by executing a power up sequence with the 4
MCU domains remaining energized throughout the sequence. The example diagram shown is for an Isolated
MCU & Main PDN type with eMMC support.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
119
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Entry into MCU only
Active
MCU only
Exit from MCU only
Active
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(2)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2),VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6)(3) VDDS_MMC0
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP)(6)
(VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0)(7)
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU
VDD_CPU
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(8)
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB
VDDAR_CORE, VDDAR_CPU
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
TΔ1
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)
MCU_PORz(10)(11)
Valid Configuration
PORz(10)(11)
J7VCL_ELCH_05
图7-7. Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
7.9.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
Entry into DDR Retention state is accomplished by executing a power down sequence except for the 4 DDR
domains that remain energized. Exit from DDR Retention state is accomplished by executing a power up
sequence with the 3 DDR domains remaining energized throughout the sequence.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
120 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Entry into MCU only
Active
DDR Retention
Exit from MCU only
Active
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
Note1
Note1
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(2)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2), VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV54,VDDSHV6)(3), VDDS_MMC0
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP)(6)
VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1,
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU
VDD_CPU
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(9)
VDD_CORE, VDD_WAKE0VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB
VDDAR_CORE, VDDAR_CPU
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
TΔ1
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)
MCU_PORz(10)(11)
Valid Configuration
PORz(10)(11)
J7VCL_ELCH_06
图7-8. Independent MCU and Main Domains, Entry and Exit of DDR Retention State
7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
Entry into GPIO Retention state is accomplished by executing a power down sequence except for the 2 or 4
wake domains that remain energized. Exit from GPIO Retention state is accomplished by executing a power up
sequence with the 2 or 4 wake DDR domains remaining energized throughout the sequence.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Entry into MCU only
Active
DDR Retention
Exit from MCU only
Active
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
Note1
Note1
( VDDSHV1_MCU, VDDSHV2_MCU)(2)
(VDDSHV0, VDDSHV1, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2), VDDA_3P3_USB(5)
(VDDSHV1_MCU, VDDSHV2_MCU)(3)
(VDDSHV0, VDDSHV1, VDDSHV3,
VDDSHV4, VDDSHV54,VDDSHV6)(3), VDDS_MMC0
VDDSHV0_MCU, VDDSHV2
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,
VDDA_POR_WKUP, VDDA_WKUP)(6)
VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1,
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU
VDD_CPU
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(9)
VDD_CORE, VDD_WAKE0VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C, VDDA_0P8_USB
VDDSHV0_MCU, VDDSHV2(8)
VDDAR_CORE, VDDAR_CPU
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C
TΔ1
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)
MCU_PORz(10)(11)
Valid Configuration
PORz(10)(11)
J7VCL_ELCH_07
图7-9. Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
122 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description..
表7-5. System Timing Conditions
PARAMETER
MIN
0.5
3
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
2
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
30
7.9.3.1 Reset Timing
Tables and figures provided in this section define timing requirements and switching characteristics for reset
related signals.
表7-6. MCU_PORz Timing Requirements
see 图7-10
NO.
MIN
TYP
MAX UNIT
Hold time, MCU_PORz active (low) at Power-up
after all MCU DOMAIN supplies valid (using
external crystal)
N +
RST1
9500000
ns
1200(2)
th(MCUD_SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-up
after all MCU DOMAIN supplies(1) valid and
external clock stable (using external LVCMOS
oscillator)
RST2
1200
1200
ns
ns
Pulse Width minimum, MCU_PORz low after
Power-up (without removal of Power or system
reference clock MCU_OSC0_XI/XO)
RST3 tw(MCU_PORzL)
(1) For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.
(2) N = oscillator start-up time
RST1
RST2
RST3
MCU_PORz
MCU DOMAIN
SUPPLIES VALID
MCU_OSC0_XI,
MCU_OSC0_XO
图7-10. MCU_PORz Timing Requirements
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 123
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-7. PORz Timing Requirements
see 图7-11
NO.
MIN
1200
1200
MAX UNIT
Hold time, PORz active (low) at Power-up after all MAIN
DOMAIN supplies1 valid
RST4 th(MAIND_SUPPLIES_VALID - PORz)
RST5 tw(PORzL)
ns
ns
Pulse Width minimum, PORz low after Power-up
1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up
sequence TBD.
RST4
RST5
PORz
MAIN DOMAIN
SUPPLIES VALID
图7-11. PORz Timing Requirements
表7-8. MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see 图7-12
NO.
PARAMETER
MODE
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
RST10 td(MCU_PORzL-MCU_RESETSTATzL)
0
ns
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
POST
bypass
RST11 td(MCU_PORzH-MCU_RESETSTATzH)
RST12 td(MCU_PORzL-RESETSTATzL)
RST13 td(MCU_PORzH-RESETSTATzH)
12000*S(1)
0
ns
ns
ns
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RESETSTATz inactive (high)
14500*S(1)
Pulse Width Minimum MCU_RESETSTATz
low
RST16 tw(MCU_RESETSTATzL)
RST17 tw(RESETSTATzL)
3900*S(1)
2650*S(1)
ns
ns
Pulse Width Minimum RESETSTATz low
(1) S = MCU_OSC0_XI/XO clock period.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
124 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
RST12
RST13
MCU_PORz
RST10
RST11
RST16
MCU_RESETSTATz
RST17
RESETSTATz
图7-12. MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 125
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
MAX UNIT
表7-9. PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics
see 图7-13
NO.
PARAMETER
MODE
MIN
T(1)
td(PORzL-
Delay time, PORz active (low) to RESETSTATz
active (low)
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0
RST20
RST21
RESETSTATzL)
0
ns
ns
td(PORzH-
Delay time, PORz active (high) to RESETSTATz
active (high)
14500*S
(2)
RESETSTATzH)
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
PORz
RST20
RST21
RESETSTATz
图7-13. PORz initiates; RESETSTATz Switching Characteristics
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
126 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-10. MCU_RESETz Timing Requirements
see 图7-14
NO.
MIN
MAX UNIT
(1)
RST22 tw(MCU_RESETzL)
Pulse Width minimum, MCU_RESETz active (low)
1200
ns
(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
表7-11. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see 图7-14
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST23 td(MCU_RESETzL-MCU_RESETSTATzL)
800
ns
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST24 td(MCU_RESETzH-MCU_RESETSTATzH)
RST25 td(MCU_RESETzL-RESETSTATzL)
RST26 td(MCU_RESETzH-RESETSTATzH)
(1) S = MCU_OSC0_XI/XO clock period.
3900*S(1)
800
ns
ns
ns
Delay time, MCU_RESETz active (low) to RESETSTATz
active (low)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
3900*S(1)
RST23
RST24
MCU_RESETz
RST22
MCU_RESETSTATz
RESETSTATz
RST25
RST26
图7-14. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and
Switching Characteristics
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 127
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-12. RESET_REQz Timing Requirements
see 图7-15
NO.
MIN
MAX UNIT
(1)
RST27 tw(RESET_REQzL)
Pulse Width minimum, RESET_REQz active (low)
1200
ns
(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
表7-13. RESET_REQz initiates; RESETSTATz Switching Characteristics
see 图7-15
NO.
PARAMETER
MODE
MIN
MAX UNIT
software control of
SOC_WARMRST_ISO_DONE
_Z
T(1)
Delay time, RESET_REQz active (low)
to RESETSTATz active (low)
RST28 td(RESET_REQzL-RESETSTATzL)
CTRLMMR_WKUP_MAIN_WA
RM
740
ns
ns
_RST_CTRL[0].SOC_
WARMRST_ISO_DONE_Z = 0
Delay time, RESET_REQz inactive
(high) to RESETSTATz inactive (high)
2650*S
RST29 td(RESET_REQzH-RESETSTATzH)
(2)
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
RST27
RST28
RESET_REQz
RST29
RESETSTATz
图7-15. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
128 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-14. EMUx Timing Requirements
see 图7-16
NO.
MIN
3*S(1)
10
MAX UNIT
RST30 tsu(EMUx-MCU_PORz)
RST31 th(MCU_PORz - EMUx)
Setup time, EMU[1:0] before MCU_PORz inactive (high)
Hold time, EMU[1:0] after MCU_PORz inactive (high)
ns
ns
(1) S = MCU_OSC0_XI/XO clock period.
RST30
MCU_PORz
EMU[1:0]
RST31
图7-16. EMUx Timing Requirements
表7-15. MCU_BOOTMODE Timing Requirements
see 图7-17
NO.
MIN
MAX UNIT
Setup time, MCU_BOOTMODE[09:00] before
MCU_PORz high
RST32 tsu(MCU_BOOTMODE-MCU_PORz)
RST33 th(MCU_PORz - MCU_BOOTMODE)
(1) S = MCU_OSC0_XI/XO clock period.
3*S(1)
ns
Hold time, MCU_BOOTMODE[09:00] after MCU_
PORz high
0
ns
RST32
MCU_PORz
MCU_BOOTMODE[09:00]
RST33
图7-17. MCU_BOOTMODE Timing Requirements
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 129
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-16. BOOTMODE Timing Requirements
see 图7-18
NO.
MIN
3*S(1)
0
MAX UNIT
RST34 tsu(BOOTMODE-PORz)
RST35 th(PORz - BOOTMODE)
Setup time, BOOTMODE[7:0] before PORz high
Hold time, BOOTMODE[7:0] after PORz high
ns
ns
(1) S = MCU_OSC0_XI/XO clock period.
RST34
PORz
BOOTMODE[7:0]
RST35
图7-18. BOOTMODE Timing Requirements
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
130 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.3.2 Safety Signal Timing
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn and
SOC_SAFETY_ERRORn.
表7-17. MCU_SAFETY_ERRORn Switching Characteristics
see 图7-19
NO.
PARAMETER
MIN
MAX UNIT
Pulse width minimum, MCU_SAFETY_ERRORn active
(PWM mode disabled)
SFTY1 tw(MCU_SAFETY_ERRORn)
P*R(1) (2)
ns
Delay time, ERROR CONDITION to
SFTY2 td (ERROR_CONDITION-MCU_SAFETY_ERRORnL) MCU_SAFETY_ERRORn
active
50*P(1)
ns
(1) P = ESM functional clock (MCU_SYSCLK0 /6).
(2) R = Error Pin Counter Pre-Load Register count value.
Internal Error Condition
(Active High)
SFTY1
SFTY2
MCU_SAFETY_ERRORn
(PWM Mode Disabled)
图7-19. MCU_SAFETY_ERRORn Switching Characteristics
表7-18. SOC_SAFETY_ERRORn Switching Characteristics
see 图7-20
NO.
PARAMETER
MIN
MAX UNIT
Pulse width minimum,SOC_SAFETY_ERRORn active
(PWM mode disabled)
SFTY3 tw(SOC_SAFETY_ERRORn)
P*R(1) (2)
ns
Delay time, ERROR CONDITION to
SFTY4 td (ERROR_CONDITION-SOC_SAFETY_ERRORnL) SOC_SAFETY_ERRORn
active
50*P(1)
ns
Internal Error Condition
(Active High)
SFTY3
SFTY4
SOC_SAFETY_ERRORn
(PWM Mode Disabled)
图7-20. SOC_SAFETY_ERRORn Switching Characteristics
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 131
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.3.3 Clock Timing
Tables and figures provided in this section define timing requirements and switching characteristics for clock
signals.
表7-19. Clock Timng Requiements
see 图7-21
NO.
MIN
10
MAX UNIT
CLK1 tc(EXT_REFCLK1)
CLK2 tw(EXT_REFCLK1H)
CLK3 tw(EXT_REFCLK1L)
Cycle time minimum, EXT_REFCLK1
ns
Pulse Duration minimum, EXT_REFCLK1 high
Pulse Duration minimum, EXT_REFCLK1 low
E*0.45(1)
E*0.45(1)
E*0.55(1)
E*0.55(1)
ns
ns
(1) E = EXT_REFCLK1 cycle time.
CLK1
CLK2
CLK3
EXT_REFCLK1
CLK19
CLK20
CLK21
MCU_EXT_REFCLK0
图7-21. Clock Timing Requirements
表7-20. Clock Switching Characteristics
see 图7-22
NO.
PARAMETER
MIN
8
MAX UNIT
CLK4 tc(SYSCLKOUT0)
CLK5 tw(SYSCLKOUT0H)
CLK6 tw(SYSCLKOUT0L)
CLK7 tc(OBSCLK0)
Cycle time minimum,SYSCLKOUT0
Pulse Duration minimum, SYSCLKOUT0 high
Pulse Duration minimum, SYSCLKOUT0 low
Cycle time minimum, OBSCLK0
ns
A*0.4(1)
A*0.4(1)
5
A*0.6(1)
ns
ns
ns
ns
ns
ns
ns
ns
A*0.6(1)
CLK8 tw(OBSCLK0H)
CLK9 tw(OBSCLK0L)
CLK10 tc(CLKOUT0)
Pulse Duration minimum, OBSCLK0 high
Pulse Duration minimum,OBSCLK0 low
Cycle time minimum, CLKOUT0
B*0.4(2)
B*0.4(2)
20
B*0.6(2)
B*0.6(2)
CLK11 tw(CLKOUT0H)
CLK12 tw(CLKOUT0L)
Pulse Duration minimum, CLKOUT0 high
Pulse Duration minimum,CLKOUT0 low
C*0.4(3)
C*0.4(3)
C*0.6(3)
C*0.6(3)
(1) A = SYSCLKOUT0 cycle time.
(2) B = OBSCLK0 cycle time.
(3) C = CLKOUT0 cycle time.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
132 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
CLK4
CLK7
CLK5
CLK8
CLK6
CLK9
SYSCLKOUT0
OBSCLK0
CLKOUT0
CLK10
CLK11
CLK12
CLK13
CLK16
CLK14
CLK17
CLK15
CLK18
MCU_SYSCLKOUT0
MCU_OBSCLK0
图7-22. Clock Switching Characteristics
7.9.4 Clock Specifications
7.9.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
• OSC1_XO/OSC1_XI —Еxternal main crystal interface pins connected to internal oscillator which sources
reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-
frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
• High frequency oscillators inputs
– OSC1_XO/OSC1_XI —external main crystal interface pins connected to internal oscillator which sources
reference clock. Provides reference clock to PLLs within MAIN domain. This highfrequency oscillator is
used to provide audio clock frequencies to MCASPs.
– WKUP_OSC0_XO/WKUP_OSC0_XI —external main crystal interface pins of the internal oscillator which
sources a reference clock. Provides reference clock to PLLs within WKUP/MCU and MAIN domain.
• Low frequency oscillator input
– WKUP_LF_CLKIN —External 32.768 kHz clock input.
• General purpose clock inputs
– MCU_EXT_REFCLK0 —optional external. Provides system clock input (MCU domain).
– EXT_REFCLK1 —optional external system clock input (MAIN domain). Optionally PLL2 (PER1) and
MCASP can be sourced by EXT_REFCLK1 (sourced externally).
– SERDES0_REFCLK_P/N —SerDes reference clock input for PCIe or Optional USB3 and SGMII
interfaces.
• External CPTS reference clock inputs
– MCU_CPTS0_RFT_CLK —CPTS reference clock inputs for MCU_CPTS_RFT_CLK.
– CPTS0_RFT_CLK —CPTS reference clock inputs for CPTS_RFT_CLK.
• External audio reference clock input/output pins
– AUDIO_EXT_REFCLK0
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 133
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
– AUDIO_EXT_REFCLK1
图7-23 shows the external input clock sources and the output clocks to peripherals.
DEVICE
Reference clock output
CLKOUT
MCU_CLKOUT0
Reference clock output for Ethernet PHYs (50MHz or 25MHz)
Selects Main PLL output divide-by-6
SYSCLKOUT0
MCU_SYSCLKOUT0
Optional pins to provide reference clock input to the PLLs.
WKUP_OSC0_XI
External Wake-up crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MAIN domain, and
audio clock frequencies to MCASPs.
WKUP_OSC0_XO
WKUP_LFOSC0_XI
External Low frequency interface pin connected to internal oscillator
which provides a 32.768 KHz clock for low power operation
in deeper sleep modes.
OSC1_XI
External main crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MCU domain
and MAIN domain.
OSC1_XO
JTAG Clock Input
TCK
MCU Warm Reset Input / Device Warm Reset Input
MCU_RESETz/ RESET_REQz
MCU_PORz / PORz
BOOTMODE[07:00]
MCU Power ON Reset / Device Power ON Reset
Boot Mode Configuration / devices select
MCU_BOOTMODE[09:00]
DDR0_CKP / DDR0_CKN
SERDES0_REFCLK_P/N
MCU Boot Mode system clock speed and fail-safe boot device
DDR Differential Clock outputs
SerDes reference clock input for PCIe or Optional USB3 and SGMII interfaces
Observation clock outputs for MCU Domain clock / MAIN Domain clocks
External audio reference clock input/output pins
MCU_OBSCLK0 / OBSCLK[2:0]
AUDIO_EXT_REFCLK[1:0]
MCU_EXT_REFCLK0 / EXT_REFCLK1
Optional external System clock inputs - (MCU domain) / (MAIN domain)
CPTS reference clock input for CPTS_RFT_CLK / MCU_CPTS_RFT_CLK
MCU_CPTS0_RFT_CLK / CPTS0_RFT_CLK
J7ES_CLOCK_01
图7-23. Input Clocks Interface
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
图 7-24 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit
should be placed as close as possible to the WKUP_OSC0_XI and WKUP_OSC0_XO pins.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
134 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Device
WKUP_OSC0_XO
WKUP_OSC0_XI
Crystal
Cf2
Cf1
PCB Ground
J7ES_WKUP_OSC_INT_02
图7-24. WKUP_OSC0 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-21 summarizes the
required electrical constraints.
表7-21. WKUP_OSC0 Crystal Circuit Requirements
PARAMETER
Fxtal
MIN
19.2, 20, 24, 25, 26, 27
±100
TYP
MAX UNIT
Crystal Parallel Resonance Frequency
Crystal Frequency Stability and Tolerance
MHz
ppm
Fxtal
Ethernet RGMII and RMII
not used
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
7
pF
pF
pF
pF
Cshunt
Crystal Circuit Shunt Capacitance
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 30 Ω
ESRxtal = 40 Ω
ESRxtal = 50 Ω
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
5
5
pF
pF
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
19.2 MHz, 20 MHz, 24 MHz
19.2 MHz, 20 MHz
25 MHz
5
5
pF
pF
pF
pF
ESRxtal = 60 Ω
ESRxtal = 80 Ω
3
19.2 MHz, 20 MHz
3
ESRxtal = 100 Ω
ESRxtal
Crystal Effective Series Resistance
100
Ω
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
表7-22 details the switching characteristics of the oscillator.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 135
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-22. WKUP_OSC0 Switching Characteristics –Crystal Mode
NAME
CXI
DESCRIPTION
MIN
TYP
MAX UNIT
XI Capacitance
1.55
1.35
0.01
pF
pF
pF
ms
CXO
CXIXO
ts
XO Capacitance
XI to XO Mutual Capacitance
Start-up Time
9.5(1)
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
VDD_WKUP (min.)
VDD_WKUP
VSS
VDDA_WKUP (min.)
VDDA_WKUP
WKUP_OSC0_XO
VSS
tsX
Time
J7ES_WKUP_OSC_STARTUP_04
图7-25. WKUP_OSC0 Start-up Time
7.9.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
WKUP_OSC0_XI and WKUP_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The WKUP_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in 表7-22.
Device
Crystal Circuit
Components
PCB
Signal Traces
WKUP_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
WKUP_OSC0_XO
J7ES_WKUP_OSC_CC_05
图7-26. Load Capacitance
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
136 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Load capacitors, CL1 and CL2 in 图 7-24, should be chosen such that the below equation is satisfied. CL in the
equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.9.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
WKUP_OSC0 operating conditions defined in 表 7-21. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in 表7-22.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
WKUP_OSC0_XI
CPCBXIXO
CXIXO
CO
WKUP_OSC0_XO
J7ES_WKUP_OSC_SC_06
图7-27. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
C
shunt ≥CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
图 7-28 shows the recommended oscillator connections when WKUP_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 137
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
备注
A DC steady-state condition is not allowed on WKUP_OSC0_XI when the oscillator is powered up.
This is not allowed because WKUP_OSC0_XI is internally AC coupled to a comparator that may enter
a unknown state when DC is applied to the input. Therefore, application software should power down
WKUP_OSC0 any time WKUP_OSC0_XI is not toggling between logic states.
Device
WKUP_OSC0_XO
WKUP_OSC0_XI
PCB Ground
J7VC_LF_OSC_INT_12
图7-28. 1.8-V LVCMOS-Compatible Clock Input
7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
图 7-29 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit
should be placed as close as possible to the OSC1_XI and OSC1_XO pins.
Device
OSC1_XO
OSC1_XI
Crystal
Cf2
Cf1
PCB Ground
J7ES_AUX_OSC_INT_07
图7-29. OSC1 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-23 summarizes the
required electrical constraints.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
138 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-23. OSC1 Crystal Electrical Characteristics
PARAMETER
Fxtal
MIN
TYP
MAX UNIT
Crystal Parallel Resonance Frequency
19.2
27
MHz
Fxtal
Crystal Frequency Stability and Tolerance
Ethernet RGMII and RMII
not used
±100
ppm
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
pF
pF
pF
pF
Cshunt
Crystal Circuit Shunt Capacitance
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 30 Ω
ESRxtal = 40 Ω
ESRxtal = 50 Ω
7
5
5
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
pF
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
19.2 MHz, 20 MHz, 24 MHz
19.2 MHz, 20 MHz
25 MHz
pF
pF
pF
pF
5
5
ESRxtal = 60 Ω
ESRxtal = 80 Ω
3
19.2 MHz, 20 MHz
3
ESRxtal = 100 Ω
ESRxtal
Crystal Effective Series Resistance
100
Ω
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
表7-24 details the switching characteristics of the oscillator and the requirements of the input clock.
表7-24. OSC1 Switching Characteristics –Crystal Mode
PARAMETER
MIN
TYP
MAX UNIT
CXI
XI Capacitance
1.55
pF
pF
pF
ms
CXO
CXIXO
ts
XO Capacitance
1.35
XI to XO Mutual Capacitance
Start-up Time
0.01
9.5(1)
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 139
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
VDD_CORE (min.)
VSS
VDD_CORE
VDDA_OSC1
VDDA_OSC1 (min.)
OSC1_XO
tsX
VSS
Time
J7ES_AUX_OSC_STARTUP_08
图7-30. OSC1 Start-up Time
7.9.4.1.3.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1_XI
and OSC1_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB designer should be
able to extract parasitic capacitance for each signal trace. The OSC1 circuits and device package have
combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic capacitance values are
defined in 表7-22.
Device
Crystal Circuit
Components
PCB
Signal Traces
OSC1_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
OSC1_XO
J7ES_AUX_OSC_CC_05
图7-31. Load Capacitance
Load capacitors, CL1 and CL2 in 图 7-24, should be chosen such that the below equation is satisfied. CL in the
equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2 pF, CXI = 1 pF, CPCBXO = 2 pF, CXO = 1 pF, the
value of CL1 = CL2 = [(2CL) - (CPCBXI + CXI)] = [(2CL) - (CPCBXO + CXO)] = [(2 × 10 pF) - 2 pF - 1 pF)] = 17 pF.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
140 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.4.1.3.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for OSC1
operating conditions defined in 表 7-21. Shunt capacitance, Cshunt, of the crystal circuit is a combination of
crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal circuit
components to OSC1 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB designer
should be able to extract mutual parasitic capacitance between these signal traces. The device package also
has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined in 表7-22.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
OSC1_XI
CPCBXIXO
CXIXO
CO
OSC1_XO
J7ES_AUX_OSC_SC_06
图7-32. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
C
shunt ≥CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.7 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.29 pF.
7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
图 7-33 shows the recommended oscillator connections when OSC1_XI is connected to a 1.8-V LVCMOS
square-wave digital clock source.
备注
A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not
allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state
when DC is applied to the input. Therefore, application software should power down OSC1 any time
OSC1_XI is not toggling between logic states.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 141
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Device
OSC1_XO
OSC1_XI
PCB Ground
J7VC_LF_OSC_INT_12
图7-33. 1.8-V LVCMOS-Compatible Clock Input
7.9.4.1.5 Auxiliary OSC1 Not Used
图 7-34 shows the recommended oscillator connections when OSC1 is not used. OSC1_XI must be connected
to VSS through an external pull resistor (Rpd) to ensure this input is held to a valid low level when unused since
the internal pull-down resistor is disabled by default.
Device
OSC1_XO
OSC1_XI
Rpd
NC
PCB Ground
J7ES_AUX_OSC_NOT_USED_11
图7-34. OSC1 Not Used
7.9.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
图 7-35 shows the recommended oscillator connections when WKUP_LF_CLKIN is connected to an LVCMOS
square-wave digital clock source.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
142 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Device
VSS
WKUP_LF_CLKIN
PCB Ground
J7VC_LF_OSC_INT_12
图7-35. WKUP_LF_CLKIN Crystal Implementation
表7-25 details the WKUP_LF_CLKIN input clock timing requirements..
表7-25. WKUP_LF_CLKIN Input Clock Timing Requirements(2)
NAME DESCRIPTION
MIN
TYP
MAX UNIT
CK0
1 /
Frequency, WKUP_LF_CLKIN
32768
Hz
tc(WKUP_LF_CLKIN
)
CK1
tw(WKUP_LF_CLKIN Pulse duration, WKUP_LF_CLKIN low or high
0.45*P(1)
0.55*P(1)
ns
)
(1) P is WKUP_LF_CLKIN cycle time in ns.
(2) Refer to 节7.6.7 LVCMOS Electrical Characteristics for voltage and slew rate information.
CK0
CK1
CK1
WKUP_LF_CLKIN
J7VC_WKUP_OSC_CLK_06
图7-36. WKUP_LF_CLKIN Start-up Time
7.9.4.1.7 WKUP_LF_CLKIN Not Used
图 7-37 shows the recommended oscillator connections when WKUP_LF_CLKIN is not used. WKUP_LF_CLKIN
may be a no-connect while the oscillator remains disabled since the internal pull-down resistor is enabled by
default.
Device
VSS
WKUP_LF_CLKIN
NC
PCB Ground
J7VC_LF_OSC_NOT_USED_14
图7-37. WKUP_LF_CLKIN Not Used
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 143
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
• MCU_CLKOUT0
– Reference clock output for Ethernet PHYs (50 MHz or 25 MHz)
• MCU_SYSCLKOUT0
– SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• MCU_OBSCLK0
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
• SYSCLKOUT0
– SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS
clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• CLKOUT
– Reference clock output
• OBSCLK[2:0]
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
144 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive their power from
off-chip power sources.
There are total of three PLLs in the device in WKUP and MCU domains:
• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0
• MCU_PLL1 (MCU PERIPHERAL PLL)
• MCU_PLL2 (MCU CPSW PLL)
There are total of ten PLLs in MAIN domain:
• PLL0 (MAIN PLL) with PLLCTRL0
• PLL1 (PER0 PLL)
• PLL2 (PER1 PLL)
• PLL3 (CPSW5X PLL)
• PLL4 (AUDIO0 PLL)
• PLL7 (MSMC PLL)
• PLL8 (ARM0 PLL)
• PLL12 (DDR PLL)
• PLL13 (C66 PLL)
• PLL14 (R5FSS PLL)
备注
For more information, see:
• Device Configuration / Clocking / PLLs section in the device TRM.
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit
(PRU) section in the device TRM.
备注
The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL
controller, as documented in the Device Configuration chapter in the device TRM.
7.9.4.4 Recommended Clock and Control Signal Transition Behavior
All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are
more susceptible to glitches due to noise, and special care must be taken for slow input clocks.
7.9.4.5 Interface Clock Specifications
7.9.4.5.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and to control transfers accordingly with the
interface protocol.
7.9.4.5.2 Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented here is the maximum clock frequency, which corresponds to the
maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by
the Device IC and does not take into account any system consideration (PCB, peripherals).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 145
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
The system designer must take into account these system considerations and the Device IC timing
characteristics to properly define the maximum operating frequency that corresponds to the maximum frequency
supported to transfer the data on this interface.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
146 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5 Peripherals
7.9.5.1 ATL
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL
calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock
using cycle stealing via software.
备注
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the
device TRM.
表7-26 represents ATL timing conditions.
表7-26. ATL Timing Conditions
PARAMETER
MODE
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
External reference CLK
Internal reference CLK
OUTPUT CONDITIONS
CL
Output load capacitance
10
节 7.9.5.1.1, 节 7.9.5.1.2, 节 7.9.5.1.3, and 节 7.9.5.1.4 present timing requirements and switching
characteristics for ATL.
7.9.5.1.1 ATL_PCLK Timing Requirements
NO.
PARAMETER
MODE
MIN
MAX UNIT
External reference
CLK
D1 tc(pclk)
Cycle time, ATL_PCLK
5
ns
External reference
CLK
D2 tw(pclkL)
Pulse Duration, ATL_PCLK low
Pulse Duration, ATL_PCLK high
0.45 × M(1) + 2.5
0.45 × M(1) + 2.5
ns
ns
External reference
CLK
D3 tw(pclkH)
(1) M = ATL_CLK[x] period
7.9.5.1.2 ATL_AWS[x] Timing Requirements
NO.
MODE
MIN
MAX UNIT
External reference
CLK
D4 tc(aws)
D5 tw(awsL)
D6 tw(awsH)
Cycle Time, ATL_AWS[x](3)
2 × M(1)
ns
External reference
CLK
Pulse Duration, ATL_AWS[x](3) low
Pulse Duration, ATL_AWS[x](3) high
0.45 × A(2) + 2.5
0.45 × A(2) + 2.5
ns
ns
External reference
CLK
(1) M = ATL_CLK[x] period
(2) A = ATL_AWS[x] period
(3) x = 0 to 3
7.9.5.1.3 ATL_BWS[x] Timing Requirements
NO.
MODE
MIN
MAX UNIT
External reference
clock
D7 tc(bws)
Cycle Time, ATL_BWS[x](3)
2 × M(1)
ns
External reference
clock
D8 tw(bwsL)
Pulse Duration, ATL_BWS[x] low(3)
0.45 × B(2) + 2.5
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 147
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
MAX UNIT
ns
NO.
MODE
MIN
External reference
clock
D9 tw(bwsH)
Pulse Duration, ATL_BWS[x] high(3)
0.45 × B(2) + 2.5
(1) M = ATL_CLK[x] period
(2) B = ATL_BWS[x] period
(3) x = 0 to 3
7.9.5.1.4 ATCLK[x] Switching Characteristics
NO.
PARAMETER
MODE
MIN
MAX UNIT
Internal reference
CLK
D10 tc(atclk)
Cycle time, ATCLK[x](3)
20
ns
Internal reference
CLK
D11 tw(atclkL)
D12 tw(atclkH)
Pulse Duration, ATCLK[x] low(3)
Pulse Duration, ATCLK[x] high(3)
0.45 × P(2) - M(1) - 0.3
0.45 × P(2) - M(1) - 0.3
ns
ns
Internal reference
CLK
(1) M = ATL_CLK[x] period
(2) P = ATCLK[x] period
(3) x = 0 to 3
D10
D12
ATCLK[x]
D11
atl_01
图7-38. ATCLK[x] Timing
7.9.5.2 CPSW2G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
表7-27 represents CPSW2G timing conditions.
表7-27. CPSW2G Timing Conditions
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
INPUT CONDITIONS
tR
Input signal rise time
Input signal fall time
1
1
5
5
V/ns
V/ns
tF
OUTPUT CONDITIONS
CLOAD
Output load capacitance
2
20
pF
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
Propagation delay mismatch across
all traces
td(Trace Mismatch Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
7.9.5.2.1 CPSW2G RMII Timings
节7.9.5.2.1.1, 节7.9.5.2.1.2, and 图7-39 present timing requirements for CPSW2G RMII receive.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
148 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK –RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
20.001
13
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
Cycle time, REF_CLK
19.999
Pulse Duration, REF_CLK High
Pulse Duration, REF_CLK Low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
图7-39. RMII[x]_REFCLK Timing –RMII Mode
7.9.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER –RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
4
TYP
MAX
UNIT
ns
RMII4 tsu(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK
4
ns
tsu(RX_ER-REF_CLK)
RMII5 th(REF_CLK-RXD)
th(REF_CLK-CRS_DV)
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
4
ns
2
ns
2
ns
th(REF_CLK-RX_ER)
2
ns
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
图7-40. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing –RMII Mode
节7.9.5.2.1.3, and 节7.9.5.2.1.3, present switching characteristics for CPSW2G RMII Transmit.
7.9.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN –RMII Mode
NO.
PARAMETER
DESCRIPTION
Delay time, REF_CLK High to TXD[1:0] valid
Delay time, REF_CLK to TXEN valid
Rise Time, TXD Outputs
MIN
2
TYP
MAX
10
10
5
UNIT
ns
RMII6 td(REF_CLK-TXD)
td(REF_CLK-TXEN)
RMII7 tr(TXD)
tr(TX_EN)
2
ns
1
ns
Rise Time, TX_EN Output
1
5
ns
RMII8 tf(TXD)
tf(TX_EN)
Fall Time, TXD Outputs
1
5
ns
Fall Time, TX_EN Output
1
5
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 149
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
RMII6
RMII[x]_REFCLK (input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (outputs)
RMII8
RMII7
SPRSP08_CPSW2G_RMIITX
图7-41. SPI Master Mode Receive Timing
7.9.5.2.2 CPSW2G RGMII Timings
节7.9.5.2.2.1, 节7.9.5.2.2.2, and 图7-42 present timing requirements for receive RGMII operation.
7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
360
36
TYP
MAX UNIT
RGMII1 tc(RXC)
RGMII2 tw(RXCH)
RGMII3 tw(RXCL)
RGMII4 tt(RXC)
Cycle time, RXC
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
Pulse duration, RXC high
Pulse duration, RXC low
Transition time, RXC
240
24
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
10Mbps
3.6
4.4
0.75
0.75
0.75
100Mbps
1000Mbps
7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
TYP
MAX UNIT
RGMII5 tsu(RD-RXC)
Setup time, RD[3:0] valid before RXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RX_CTL valid before RXC high/low
Hold time, RD[3:0] valid after RXC high/low
Hold time, RX_CTL valid after RXC high/low
1
100Mbps
1000Mbps
10Mbps
1
1
RGMII6 th(RXC-RD)
1
100Mbps
1000Mbps
10Mbps
1
1
th(RXC-RX_CTL)
1
100Mbps
1000Mbps
1
1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
150 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
TYP
MAX UNIT
RGMII7 tt(RD)
Transition time, RD
0.75
0.75
0.75
0.75
0.75
0.75
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
tt(RX_CTL)
Transition time, RX_CTL
100Mbps
1000Mbps
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
2nd Half-byte
RXERR
RXDV
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
图7-42. CPSW2G Receive Interface Timing, RGMII Operation
节7.9.5.2.2.3, 节7.9.5.2.2.4, and 图7-43 present switching characteristics for transmit - RGMII for 10 Mbps, 100
Mbps, and 1000 Mbps.
7.9.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
360
36
TYP
MAX UNIT
RGMII1 tc(TXC)
RGMII2 tw(TXCH)
RGMII3 tw(TXCL)
RGMII4 tt(TXC)
Cycle time, TXC
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
Pulse duration, TXC high
Pulse duration, TXC low
Transition time, TXC
240
24
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
10Mbps
3.6
4.4
0.75
0.75
0.75
100Mbps
1000Mbps
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 151
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1.2
TYP
MAX UNIT
RGMII5 tosu(TD-TXC)
Output setup time, RGMII[x]_TD[3:0] valid to
RGMII[x]_TXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
tosu(TX_CTL-TXC)
Output setup time, RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII6 toh(TD-TXC)
Output hold time, RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
1.2
1.0
toh(TX_CTL-TXC)
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
1.2
100Mbps
1000Mbps
1.2
1.05
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
RGMII10
TXERR
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
图7-43. CPSW2G Transmit Interface Timing RGMII Mode
For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device
TRM.
7.9.5.3 CPSW5G
The Gigabit Ethernet MAC supports standards shown in 表7-28.
表7-28. CPSW5G Supported Standards
INDUSTRIAL STANDARDS
BAUD(1)
LINK/ DATA RATE(1)
5.15625 GBaud
10.3125 GBaud
5 Gbps
USXGMII/ XFI
10 Gbps
QSGMII
XAUI (2.5G SGMII)
1G SGMII
5 GBaud
3.125 GBaud
1.25 GBaud
4x 1Gbps
2.5 Gbps
1 Gbps
(1) Lower data rates are achieved through replication
For more details about features and additional description on the device Gigabit Ethernet MAC, see the
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
152 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-29 represents CPSW5G timing conditions.
表7-29. CPSW5G Timing Conditions
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
INPUT CONDITIONS
tR
Input signal rise time
Input signal fall time
1
1
5
5
V/ns
V/ns
tF
OUTPUT CONDITIONS
CLOAD
Output load capacitance
2
20
pF
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
Propagation delay mismatch across
all traces
td(Trace Mismatch Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
7.9.5.3.1 CPSW5G MDIO Interface Timings
表7-30, 表7-31, 表7-32, and 图7-44 present timing requirements for MDIO.
表7-30. CPSW5G MDIO Timing Conditions
PARAMETER
INPUT CONDITIONS
SRI
DESCRIPTION
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
Input signal slew rate
OUTPUT CONDITIONS
CL Output load capacitance
470
表7-31. Timing Requirements for MDIO Input
PARAMETER
NO.
MIN
MAX
UNIT
MDIO1 tsu(MDIO_MDC)
MDIO2 th(MDIO_MDC)
Setup time, MDIO_DATA valid before MDIO_CLK high
Hold time, MDIO_DATA valid after MDIO_CLK high
90
0
ns
ns
表7-32. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO.
PARAMETER
MIN
400
160
160
MAX
UNIT
MDIO3 tc(MDC)
MDIO4 tw(MDCH)
MDIO5 tw(MDCL)
MDIO6 tt(MDC)
MDIO7 td(MDC_MDIO)
Cycle time, MDIO_CLK
ns
Pulse Duration, MDIO_CLK high
Pulse Duration, MDIO_CLK low
ns
ns
Transition time, MDIO_CLK
5
ns
Delay time, MDIO_CLK High to MDIO_DATA valid
-150
150
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 153
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
图7-44. CPSW5G MDIO Diagrams Receive and Transmit
7.9.5.3.2 CPSW5G RMII Timings
节7.9.5.3.2.1, 节7.9.5.3.2.2, and 图7-45 present timing requirements for CPSW5G RMII receive.
7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK –RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
Cycle time, REF_CLK
19.999
20.001
13
Pulse Duration, REF_CLK High
Pulse Duration, REF_CLK Low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
图7-45. RMII[x]_REFCLK Timing –RMII Mode
7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER –RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
4
TYP
MAX
UNIT
ns
RMII4 tsu(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK
4
ns
tsu(RX_ER-REF_CLK)
RMII5 th(REF_CLK-RXD)
th(REF_CLK-CRS_DV)
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
4
ns
2
ns
2
ns
th(REF_CLK-RX_ER)
2
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
154 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
图7-46. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing –RMII Mode
节7.9.5.3.2.3, 节7.9.5.2.1.3, and present switching characteristics for CPSW5G RMII transmit.
7.9.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN –RMII Mode
NO.
PARAMETER
DESCRIPTION
Delay time, REF_CLK High to TXD[1:0] valid
Delay time, REF_CLK to TXEN valid
Rise Time, TXD Outputs
MIN
2
TYP
MAX
10
10
5
UNIT
ns
RMII6 td(REF_CLK-TXD)
td(REF_CLK-TXEN)
RMII7 tr(TXD)
tr(TX_EN)
2
ns
1
ns
Rise Time, TX_EN Output
1
5
ns
RMII8 tf(TXD)
tf(TX_EN)
Fall Time, TXD Outputs
1
5
ns
Fall Time, TX_EN Output
1
5
ns
7.9.5.3.3 CPSW5G RGMII Timings
节7.9.5.3.3.1, 节7.9.5.3.3.2, and 图7-47 present timing requirements for receive RGMII operation.
7.9.5.3.3.1 Timing Requirements for RGMII[x]_RCLK –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
360
36
TYP
MAX UNIT
RGMII1 tc(RXC)
RGMII2 tw(RXCH)
RGMII3 tw(RXCL)
RGMII4 tt(RXC)
Cycle time, RXC
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
Pulse duration, RXC high
Pulse duration, RXC low
Transition time, RXC
240
24
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
10Mbps
3.6
4.4
0.75
0.75
0.75
100Mbps
1000Mbps
7.9.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
TYP
MAX UNIT
RGMII5 tsu(RD-RXC)
Setup time, RD[3:0] valid before RXC high/low
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RX_CTL valid before RXC high/low
1
100Mbps
1000Mbps
1
1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 155
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
TYP
MAX UNIT
RGMII6 th(RXC-RD)
Hold time, RD[3:0] valid after RXC high/low
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
th(RXC-RX_CTL)
Hold time, RX_CTL valid after RXC high/low
Transition time, RD
1
100Mbps
1000Mbps
10Mbps
1
1
RGMII7 tt(RD)
0.75
0.75
0.75
0.75
0.75
0.75
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
tt(RX_CTL)
Transition time, RX_CTL
100Mbps
1000Mbps
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
图7-47. CPSW5G Receive Interface Timing, RGMII Operation
节7.9.5.3.3.3, 节7.9.5.3.3.4, and 图7-48 present switching characteristics for transmit - RGMII for 10 Mbps, 100
Mbps, and 1000 Mbps.
7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
360
36
TYP
MAX UNIT
RGMII1 tc(TXC)
RGMII2 tw(TXCH)
RGMII3 tw(TXCL)
RGMII4 tt(TXC)
Cycle time, TXC
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
Pulse duration, TXC high
Pulse duration, TXC low
Transition time, TXC
240
24
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
10Mbps
3.6
4.4
0.75
0.75
0.75
100Mbps
1000Mbps
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
156 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL –RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1.2
TYP
MAX UNIT
RGMII5 tosu(TD-TXC)
Output setup time, RGMII[x]_TD[3:0] valid to
RGMII[x]_TXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
tosu(TX_CTL-TXC)
Output setup time, RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII6 toh(TD-TXC)
Output hold time, RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
toh(TX_CTL-TXC)
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
1.2
1.05
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
RGMII10
TXERR
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
图7-48. CPSW5G Transmit Interface Timing RGMII Mode
For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.
7.9.5.4 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory
Interfaces, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4
SDRAM devices with the following features:
• 32-bit and 16-bit data path to external SDRAM memory
• Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank)
• No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits
表7-33 and 图7-49 present switching characteristics for DDRSS.
表7-33. Switching Characteristics for DDRSS
NO.
PARAMETER
DDR TYPE
MIN
MAX UNIT
3.003 ns
tc(DDR_CKP/
1
Cycle time, DDR0_CKP and DDR0_CKN
LPDDR4
0.625(1)
DDR_CKN)
(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB
implementation.Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 157
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
implementation. TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing,
vias/backdrill, PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board Design and
Layout Guidelines for details.
1
DDR0_CKP
DDR0_CKN
图7-49. DDRSS Memory Interface Clock Timing
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
7.9.5.5 ECAP
The supported features by the device ECAP are:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Independent edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt capabilities on any of the four capture events
• Input capture signal pre-scaling (from 1 to 16)
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp
capture or difference mode time-stamp capture)
表7-34 represents ECAP timing conditions.
表7-34. ECAP Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
1
MAX
UNIT
V/ns
pF
Input slew rate
4
7
Output Conditions
CLOAD
Output load capacitance
2
节7.9.5.5.1 and 节7.9.5.5.2 present timing and switching characteristics for ECAP (see 图7-50 and 图7-51).
7.9.5.5.1 Timing Requirements for ECAP
NO.
PARAMETER
DESCRIPTION
Pulse duration, CAP (asynchronous)
MIN
2 + 2P(1)
MAX
UNIT
CAP1 tw(CAP)
ns
(1) P = sysclk period in ns
CAP1
CAP
EPERIPHERALS_TIMNG_01
图7-50. ECAP Input Timings
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
158 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.5.2 Switching Characteristics for ECAP
NO.
PARAMETER
DESCRIPTION
Pulse duration, APWMx high/low
MIN
-2 + 2P(1)
MAX
UNIT
CAP2 tw(APWM)
ns
(1) P = sysclk period in ns
CAP2
APWM
EPERIPHERALS_TIMNG_02
图7-51. ECAP Output Timings
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
7.9.5.6 EPWM
The supported features by the device EPWM are:
• Dedicated 16-bit time-base counter with period and frequency control
• Two independent PWM outputs which can be used in different configurations (with single-edge operation,
with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)
• Asynchronous override control of PWM signals during fault conditions
• Programmable phase-control support for lag or lead operation relative to other EPWM modules
• Dead-band generation with independent rising and falling edge delay control
• Programmable trip zone allocation of both latched and un-latched fault conditions
• Events enabling to trigger both CPU interrupts and start of ADC conversions
表7-35 represents EPWM timing conditions.
表7-35. EPWM Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
MAX
UNIT
V/ns
pF
Input slew rate
1
4
7
Output Conditions
CLOAD
Output load capacitance
2
节 7.9.5.6.1, and 节 7.9.5.6.2 present timing and switching characteristics for EPWM (see 图 7-52, 图 7-53, 图
7-54, and 图7-55).
7.9.5.6.1 Timing Requirements for EPWM
NO.
PARAMETER
DESCRIPTION
Pulse duration, PWM output high/low
MIN
P -3(1)
P -3(1)
MAX
UNIT
ns
PWM1 tw(PWM)
PWM2 tw(SYNCOUT)
PWM3 td(TZ-PWM)
PWM4 td(TZ-PWMZ)
Pulse duration, Sync output
ns
Delay time, trip input active to PWM forced high/low
Delay time, trip input active to PWM Hi-Z
11
11
ns
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 159
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PWM5 tw(SOC)
Pulse duration, SOC output (asynchronous)
P -3(1)
ns
(1) P = sysclk period in ns
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
PWM5
EHRPWM_SOCA/B
EPERIPHERALS_TIMNG_04
图7-52. EPWM_A/B_out, ePWM_SYNCO, and ePWM_SOCA/B Input Timings
PWM3
EHRPWM_A/B
EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05
图7-53. EPWM_A/B and ePWM_TZn_IN Forced High/Low Input Timings
PWM4
EHRPWM_A/B
EHRPWM_TZn_IN
图7-54. EPWM_A/B and ePWM_TZn_IN Hi–Z Input Timings
7.9.5.6.2 Switching Characteristics for EPWM
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PWM6 tw(SYNCIN)
Pulse duration, Sync input (asynchronous)
2 + 2P(1)
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
160 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PWM7 tw(TZ)
Pulse duration, TZx input low (asynchronous)
2 + 3P(1)
ns
(1) P = sysclk period in ns
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
图7-55. ePWM_SYNCI and ePWM_TZn_IN Output Timings
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
7.9.5.7 EQEP
The supported features by the device EQEP are:
• Input Synchronization
• Three Stage/Six Stage Digital Noise Filter
• Quadrature Decoder Unit
• Position Counter and Control unit for position measurement
• Quadrature Edge Capture unit for low speed measurement
• Unit Time base for speed/frequency measurement
• Watchdog Timer for detecting stalls
表7-36 represents EQEP timing conditions.
表7-36. EQEP Timing Conditions
PARAMETER
Input Conditions
SRI
DESCRIPTION
MIN
MAX
UNIT
V/ns
pF
Input slew rate
1
4
7
Output Conditions
CL
Output load capacitance
2
节7.9.5.7.1 and 节7.9.5.7.2 present timing requirements and switching characteristics for EQEP (see 图7-56).
7.9.5.7.1 Timing Requirements for EQEP
NO.
PARAMETER
tw(QEP)
DESCRIPTION
MIN
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
MAX
UNIT
ns
QEP1
QEP2
QEP3
QEP4
Pulse duration, QEP_A/B
Pulse duration, QEP_I high
Pulse duration, QEP_I low
tw(QEPIH)
tw(QEPIL)
tw(QEPSH)
ns
ns
Pulse duration, QEP_S high
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 161
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
tw(QEPSL)
DESCRIPTION
MIN
2 + 2P(1)
MAX
UNIT
QEP5
Pulse duration, QEP_S low
ns
(1) P = sysclk period in ns
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
图7-56. EQEP Input Timings
7.9.5.7.2 Switching Characteristics for EQEP
NO.
PARAMETER
td(QEP-CNTR)
DESCRIPTION
MIN
MAX
UNIT
QEP6
Delay time, external clock to counter increment
24
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
7.9.5.8 GPIO
The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.
• Group one: WKUP_GPIO0 and WKUP_GPIO1
• Group two: GPIO0, GPIO2, GPIO4, and GPIO6
• Group three: GPIO1, GPIO3, GPIO5, and GPIO7
Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts.
The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to
144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface
supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),
GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general
purpose interface supports up to 248 I/O pins.
For more details about features and additional description information on the device General-Purpose Interface,
see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
备注
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.
表7-37, 表7-38, and 表7-39 present timing conditions, requirements, and switching characteristics for GPIO.
表7-37. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX UNIT
INPUT CONDITIONS
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
162 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-37. GPIO Timing Conditions (continued)
PARAMETER
BUFFER TYPE
MIN
0.2
MAX UNIT
6.6 V/ns
0.8 V/ns
LVCMOS
SRI
Input slew rate
I2C OD FS
0.2
OUTPUT CONDITIONS
CL Output load capacitance
LVCMOS
3
3
10
pF
pF
I2C OD FS
100
表7-38. GPIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
MODE
1.8 V
3.3 V
MIN
MAX UNIT
2P + 2.6(1)
2P + 3.4(1)
ns
ns
GPIO1 tw(GPIO_IN)
Pulse width, GPIOn_x
(1) P = functional clock period in ns.
表7-39. GPIO Switching Characteristics
NO.
GP3
GP4
GP5
PARAMETER
tw(GPIO_OUT)
tw(GPIO_OUT)
tw(GPIO_OUT)
DESCRIPTION
Minimum Output Pulse Width
Minimum Output Pulse Width Low
Minimum Output Pulse Width High
BUFFER TYPE
MIN
MAX UNIT
LVCMOS
-3.6 + 0.975P(1)
ns
ns
ns
I2C Open Drain
I2C Open Drain
160
60
(1) P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
7.9.5.9 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
表7-40. GPMC Timing Conditions
PARAMETER
Input Conditions
SRI
DESCRIPTION
MIN
1.65
5
MAX
4
UNIT
V/ns
pF
Input slew rate
Output Conditions
CL
Output load capacitance
20
PCB Connectivity Requirements
td(Trace Delay)
Propagation delay of each trace 133 MHz
140
140
360
ps
Synchronous Mode
All other modes
720
200
td(Trace Mismatch Delay)
Propagation mismatch across all traces
ps
7.9.5.9.1 GPMC and NOR Flash —Synchronous Mode
节 7.9.5.9.1.1 and 节 7.9.5.9.1.2 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图7-57 through 图7-61).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 163
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements —Synchronous Mode
MIN
MAX
MIN
MAX
UNIT
PARAMETE
NO.
DESCRIPTION
Setup time, input data
GPMC_AD[15:0] valid before output
clock GPMC_CLK high
MODE(2)
R
100 MHz
133 MHz
F12 tsu(dV-clkH)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81
1.11
ns
ns
ns
ns
ns
ns
ns
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06
1.78
1.78
1.81
1.06
1.78
1.78
F13 th(clkH-dV)
Hold time, input data GPMC_AD[15:0]
valid after output clock GPMC_CLK
high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.28
1.11
2.28
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[j]
valid before output clock GPMC_CLK
high(1)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F22 th(clkH-waitV)
Hold time, input wait GPMC_WAIT[j]
valid after output clock GPMC_CLK
high(1)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(1) In GPMC_WAIT[j], j is equal to 0 or 1.
(2) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For not_div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics –Synchronous Mode
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(19)
UNIT
(2)
100 MHz
133 MHz
F0 1 / tc(clk)
F1 tw(clkH)
Period, output clock GPMC_CLK(18)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
10
7.52
ns
Typical pulse duration, output clock
GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-0.3+
0.475*
P(15)
-0.3+
0.475*
P(15)
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
164 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
MIN
MAX
MIN
MAX
PARAMETER
DESCRIPTION
MODE(19)
UNIT
(2)
100 MHz
133 MHz
F1 tw(clkL)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-0.3+
0.475*
P(15)
-0.3+
0.475*
P(15)
ns
F2 td(clkH-csnV)
Delay time, output clock GPMC_CLK
rising edge to output chip select
GPMC_CSn[i] transition(14)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+F 3.75+F -2.2+F 3.75+F ns
(6)
(6)
(6)
(6)
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK
rising edge to output chip select
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+E 3.75+E -2.2+E 3.75+E ns
(5)
(5)
(5)
(5)
GPMC_CSn[i] invalid(14)
F4 td(aV-clk)
Delay time, output address
GPMC_A[27:1] valid to output clock
GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+B 4.5+B -2.3+B 4.5+B ns
(2)
(2)
(2)
(2)
F5 td(clkH-aIV)
Delay time, output clock GPMC_CLK
rising edge to output address
GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3
4.5
-2.3
4.5 ns
F6 td(be[x]nV-clk)
Delay time, output lower byte enable
and command latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
-2.3+B 1.9+B -2.3+B 1.9+B ns
(2)
(2)
(2)
(2)
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1
enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK
rising edge to output lower byte
div_by_1_mode;
GPMC_FCLK_MUX;
-2.3+D 1.9+D -2.3+D 1.9+D ns
(4)
(4)
(4)
(4)
enable and command latch enable
TIMEPARAGRANULARITY_X1
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid(11)
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D -2.3+D 1.9+D ns
(4)
(4)
(4)
(4)
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D -2.3+D 1.9+D ns
(4)
(4)
(4)
(4)
F8 td(clkH-advn)
F9 td(clkH-advnIV)
F10 td(clkH-oen)
F11 td(clkH-oenIV)
F14 td(clkH-wen)
F15 td(clkH-do)
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+G 4.5+G -2.3+G 4.5+G ns
(7)
(7)
(7)
(7)
GPMC_ADVn_ALE transition
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+D 4.5+D -2.3+D 4.5+D ns
(4)
(4)
(4)
(4)
GPMC_ADVn_ALE invalid
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3H(8) 3.5+H -2.3H(8) 3.5+H ns
(8)
(8)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+E 3.5+E -2.3+E 3.5+E ns
(8)
(8)
(8)
(8)
Delay time, output clock GPMC_CLK
rising edge to output write enable
GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+I(9) 4.5+I(9) -2.3+I 4.5+I(9) ns
(9)
Delay time, output clock GPMC_CLK
rising edge to output data
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J
2.7+J ns
(10)
(10)
(10)
(10)
GPMC_AD[15:0] transition(11)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 165
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
MIN
MAX
MIN
MAX
UNIT
NO.
PARAMETER
DESCRIPTION
MODE(19)
(2)
100 MHz
133 MHz
F15 td(clkL-do)
F15 td(clkL-do).
F17 td(clkH-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J 2.7+J ns
(10)
(10)
(10)
(10)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J
2.7+J ns
(10)
(10)
(10)
(10)
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
GPMC_BE0n_CLE transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
1.9+J ns
(10)
(10)
(10)
(10)
F17 td(clkL-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
1.9+J ns
(10)
(10)
(10)
(10)
F17 td(clkL-be[x]n).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
1.9+J ns
(10)
(10)
(10)
(10)
F18 tw(csnV)
Pulse duration, output chip select
GPMC_CSn[i] low(14)
Read
Write
Read
Write
A(1)
A(1)
C(3)
C(3)
A(1)
A(1)
C(3)
C(3)
ns
ns
ns
ns
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
F20 tw(advnV)
Pulse duration, output address valid
and address latch enable
GPMC_ADVn_ALE low
Read
Write
K(16)
K(16)
K(16)
K(16)
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
•
Case GPMCFCLKDIVIDER = 0:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
166 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•
Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
•
Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 167
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
•
Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
•
Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(19) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
168 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
GPMC_A[MSB:1]
Valid Address
F19
F7
GPMC_BE0n_CLE
GPMC_BE1n
F19
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F12
D 0
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-57. GPMC and NOR Flash —Synchronous Single Read (GPMCFCLKDIVIDER = 0)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 169
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
GPMCA[MSB:1]
Valid Address
F6
F7
F7
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F13
F12
F12
D 0
F22
GPMC_AD[15:0]
GPMC_WAIT[j]
D 1
D 2
D 3
F21
GPMC_02
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-58. GPMC and NOR Flash —Synchronous Burst Read —4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1
F0
GPMC_CLK
GPMC_CSn[i]
F2
F3
F4
F6
Valid Address
GPMC_A[MSB:1]
F17
F17
F17
F17
F17
F17
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
D 0
D 3
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
170 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-59. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F7
GMPC_BE0n_CLE
Valid
F6
F7
Valid
GPMC_BE1n
F4
GPMC_A[27:17]
Address (MSB)
F5
F12
F13
F4
Address (LSB)
F12
GPMC_AD[15:0]
D0
D1
D2
D3
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-60. GPMC and Multiplexed NOR Flash —Synchronous Burst Read
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 171
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
GPMC_A[27:17]
Address (MSB)
F17
F17
F6
F17
F17
F17
F17
GPMC_BE1n
F6
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
Address (LSB)
D 0
D 3
F22
F21
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-61. GPMC and Multiplexed NOR Flash —Synchronous Burst Write
7.9.5.9.2 GPMC and NOR Flash —Asynchronous Mode
节 7.9.5.9.2.1 and 节 7.9.5.9.2.2 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图7-62 through 图7-67).
7.9.5.9.2.1 GPMC and NOR Flash Timing Requirements –Asynchronous Mode
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
FA5(1) tacc(d)
Data access time
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
FA2 tacc1-pgmode(d)
0(2)
Page mode successive data access time
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
P(3) ns
FA2 tacc2-pgmode(d)
1(1)
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
172 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics –Asynchronous Mode
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
N(12) ns
N(12)
A(1) ns
A(1)
133 MHz
FA0 tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
Write
FA1 tw(csnV)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
Write
Read
Write
FA3 td(csnV-advnIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
-2+B(2)
-2+B(2)
2+B(2) ns
2+B(2)
FA4 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+C(3)
2+C(3) ns
2+J(9) ns
2+J(9) ns
FA9 td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+J(9)
-2+J(9)
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+K(10)
-2+L(11)
G(7)
2+K(10) ns
2+L(11) ns
ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+I(8)
2+I(8) ns
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX;
D(4)
ns
TIMEPARAGRANULARITY_X1
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+E(5)
-2+F(6)
2+E(5) ns
2+F(6) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2
ns
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+J(9)
2+J(9) ns
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX;
2
ns
TIMEPARAGRANULARITY_X1
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 173
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data IN 0
Data IN 0
GPMC_WAIT[j]
GPMC_06
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
174 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-62. GPMC and NOR Flash —Asynchronous Read —Single Word
GPMC_FCLK
GPMC_CLK
FA5
FA5
FA1
FA1
GPMC_CSn[i]
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
GPMC_A[MSB:1]
FA10
FA10
Valid
FA0
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-63. GPMC and NOR Flash —Asynchronous Read —32–Bit
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 175
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GPMC_CLK
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
GPMC_CSn[i]
FA9
Add0
Add4
GPMC_A[MSB:1]
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D0
D1
D2
D3
GPMC_WAIT[j]
GPMC_08
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-64. GPMC and NOR Flash —Asynchronous Read —Page Mode 4x16–Bit
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
176 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
GPMC_BE0n_CLE
GPMC_BE1n
Valid Address
FA0
FA10
FA10
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
GPMC_AD[15:0]
GPMC_WAIT[j]
FA29
Data OUT
GPMC_09
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-65. GPMC and NOR Flash —Asynchronous Write —Single Word
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 177
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
Address (MSB)
FA0
GPMC_A[27:17]
FA10
GPMC_BE0n_CLE
Valid
FA0
FA10
GPMC_BE1n
Valid
FA3
FA12
GPMC_ADVn_ALE
GPMC_OEn_REn
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_10
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-66. GPMC and Multiplexed NOR Flash —Asynchronous Read —Single Word
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
178 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
FA1
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
FA28
GPMC_AD[15:0]
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-67. GPMC and Multiplexed NOR Flash —Asynchronous Write —Single Word
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 179
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.9.3 GPMC and NAND Flash —Asynchronous Mode
节 7.9.5.9.3.1 and 节 7.9.5.9.3.2 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图7-68 through 图7-71).
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements –Asynchronous Mode
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
133 MHz
GNF12(1) tacc(d)
Access time, input data GPMC_AD[15:0](3)
div_by_1_mode;
GPMC_FCLK_MUX;
J(2) ns
TIMEPARAGRANULARITY_X1
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics –Asynchronous Mode
NO.
PARAMETER
MODE(15)
MIN
MAX UNIT
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
A(1)
ns
TIMEPARAGRANULARITY_X1
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+B(2)
-2+C(3)
-2+D(4)
-2+E(5)
-2+F(6)
-2+G(7)
-2+C(3)
2+B(2) ns
2+C(3) ns
2+D(4) ns
2+E(5) ns
2+F(6) ns
2+G(7) ns
2+C(3) ns
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
180 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
PARAMETER
MODE(15)
MIN
MAX UNIT
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+F(6)
2+F(6) ns
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
H(8) ns
2+I(9) ns
K(10) ns
ns
GNF10 td(csnV-oenV)
GNF13 tw(oenV)
GNF14 tc(oen)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+I(9)
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX;
L(11)
TIMEPARAGRANULARITY_X1
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+M(12)
2+M(12) ns
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 181
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF2
GNF6
GNF5
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF0
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-68. GPMC and NAND Flash —Command Latch Cycle
GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF6
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF7
GNF8
GPMC_OEn_REn
GPMC_WEn
GNF9
GNF0
GNF3
GNF4
Address
GPMC_AD[15:0]
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-69. GPMC and NAND Flash —Address Latch Cycle
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
182 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
GPMC_FCLK
GNF12
GNF10
GNF15
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
DATA
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-70. GPMC and NAND Flash —Data Read Cycle
GPMC_FCLK
GNF1
GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
DATA
GPMC_15
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-71. GPMC and NAND Flash —Data Write Cycle
7.9.5.10 HyperBus
For more details about features and additional description information on the device HyperBus, see the
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
节 7.9.5.10.1, 节 7.9.5.10.2, and 节 7.9.5.10.3 assume testing over the recommended operating conditions and
electrical characteristic conditions (see 图7-72, 图7-73, and 图7-74).
表7-41 represents HyperBus timing conditions.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 183
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-41. HyperBus Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
MAX
5
UNIT
V/ns
pF
Input slew rate
2
Output Conditions
CLOAD
Output load capacitance
1.5
10
7.9.5.10.1 Timing Requirements for HyperBus Initialization
NO.
D1
D2
D3
D4
PARAMETER
tw(RESETn)
DESCRIPTION
MIN
MAX
UNIT
ns
RESETn Pulse Width
200
tw(csL)
Chip Select Pulse Width
1000
200.34
115
ns
td(RESETnH-csL)
td(csL-RWDSL)
Delay time, RESETn inactive to CSn active
Delay time, CSn active to RWDS falling
ns
ns
7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
NO.
D5
PARAMETER
tskn(rwdsX-dV)
DESCRIPTION
Input skew, RWDS transitioning to D0:D7 valid
CLK period, CLK/CLKn
MIN
-0.46
6
MAX
UNIT
ns
0.46
D6
tc(clk/clkn)
ns
D7
tw(clk/clkn)
Pulse width, CLK/CLKn
2.7
6
ns
D8
tw(csIV)
Pulse width, CS0 invalid between operations
Delay time, CS0 active to CLK rising/ CLKn falling
ns
D9
td(clkH-csL)
td(clkL[LE]-csH)
td(clkX-rwdsV)
td(clkX-d[0:7]V)
-3.34
ns
D10
D11
D12
Delay time, last falling CLK/ rising CLKn edge to CS0 inactive
Delay time, CLK transition to RWDS valid
0.41
1.01
0.84
ns
2.08
2.17
ns
Delay time, CLK transitioning to D0:D7 valid
ns
7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
NO.
PARAMETER
tskn(rwdsX-dV)
DESCRIPTION
Input skew, RWDS transitioning to D0:D7 valid
CLK period, CLK
MIN
-0.81
10
MAX
UNIT
ns
LFD5
LFD6
LFD7
LFD8
LFD9
0.81
tc(clk)
ns
tw(clk)
Pulse width, CLK
4.75
10
ns
tw(csIV)
td(clkH-csL)
Pulse width, CS0 invalid between operations
Delay time, CS0 active to CLK rising
Delay time, last falling CLK edge to CS0 inactive
Delay time, CLK transition to RWDS valid
Delay time, CLK transitioning to D0:D7 valid
ns
-3.51
ns
LFD10 td(clkL[LE]-csH)
LFD11 td(clkX-rwdsV)
LFD12 td(clkX-d[0:7]V)
0.51
1.51
1.34
ns
3.49
3.66
ns
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
184 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
D8/LFD8
D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D6/LFD6
D7/LFD7
D4
D11/LFD11
RWDS
D12/LFD12
D12/LFD12
Dn
A
Dn
B
Dn+1 Dn+1
A
39:32 31:24 23:16
7:0
47:40
15:8
DQ[7:0]
B
CK and Data are center aligned
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0] and RWDS
HYPERBUS_TIMING_01
图7-72. HyperBus Timing Diagrams –Transmitter Mode
D8/LFD8
D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D6/LFD6
D4
D7/LFD7
RWDS
D5/LFD5
D12/LFD12
D5/LFD5
Dn
A
Dn
B
Dn+1 Dn+1
A
39:32 31:24 23:16
7:0
47:40
15:8
DQ[7:0]
B
CK and Data are center aligned
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0] and RWDS
HYPERBUS_TIMING_02
图7-73. HyperBus Timing Diagrams –Receiver Mode
D1
RESETn
D3
CSn
HYPERBUS_TIMING_03
图7-74. HyperBus Timing Diagrams –Reset
For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.
7.9.5.11 I2C
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not fully
compliant to the I2C electrical specification. The speeds supported and exceptions are described per port below:
• MCU_I2C1, I2C1, I2C2, I2C3, I2C4, I2C5 and I2C6
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 185
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
– Exceptions:
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C
specification because they are implemented with higher performance LVCMOS push-pull IOs that were
designed to support other signal functions that could not be implemented with I2C compatible IOs. The
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z
state.
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
• WAKEUP_I2C0, MCU_I2C0, and I2C0
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
• Hs-mode (up to 3.4 Mbit/s)
– 1.8 V
– Exceptions:
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So
Hs-mode is limited to 1.8-V operation.
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C
specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
Refer to the Philips I2C-bus specification version 2.1 for timing details.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.9.5.12 I3C
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
表 7-42, 表 7-43, 图 7-75, 表 7-44, and 图 7-76 assume testing over the recommended operating conditions and
electrical characteristic conditions.
表7-42. I3C Open Drain Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.2276
5
V/ns
OUTPUT CONDITIONS
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
186 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-42. I3C Open Drain Timing Conditions (continued)
PARAMETER
MIN
MAX
UNIT
CL
Output load capacitance
50
pF
表7-43. I3C Open Drain Timing Parameters
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
D1
tLOW_OD
Low Period of SCL Clock
Controller
200
ns
ns
tDIG_OD_L
tLOW_OD
+
MIN
tFDA_OD
MIN
D2
tHIGH
High Period of SCL Clock
Controller
41
tHIGH + tCF
12
ns
ns
ns
ns
ns
tDIG_H
tfDA_OD
tSU_OD
tCAS
D3
D4
D5
Fall Time of SDA Signal
Controller, Target
Controller, Target
tCF
3
SDA Data Setup Time During Open Drain Mode
Clock After START (S) Condition
Controller,
ENTAS0
38.4
1000
100000
Controller,
ENTAS1
38.4
38.4
ns
ns
ns
ns
ns
Controller,
ENTAS2
2000000
Controller,
ENTAS3
38.4 50000000
D6
D7
tCBP
Clock Before STOP (P) Condition
Controller
tCAS MIN
/
2
tMMOVERLAP
Current Controller to Secondary Controller Overlap
time during handoff
Controller
tDIG_OD_L
min
D8
D9
tAVAL
Bus Available Condition
Bus Idle Condition
Controller
Controller
Controller
1000
1000000
tAVALmin
ns
ns
ns
tIDLE
D10
tMMLOCK
Time Internal Where New Controller Not Driving SDA
Low
1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin
.
2. The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already
above VIH.
3. Based on tSPIKE, rise and fall times, and interconnect.
4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices,
and/or in consideration of the interconnect (for example: a short Bus).
5. On a Legacy Bus where I2C Devices need to see Start, the tCAS Min value is further constrained.
6. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3.
7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300ns shorter than the Fm Bus Free Condition time
(tBUF).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 187
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
D4
D3
0.7xVDD
0.3xVDD
SDA
D5
D6
D1
0.7xVDD
0.3xVDD
SCL
D2
Stop
Start
Repeated
Start
Stop
- Open drain with weak pull-up
- Open drain with weak pull-up
I3C_TIMING_01
图7-75. I3C Open Drain Timing
表7-44. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
D1
D2
fSCL
SCL Clock Period
Controller
Controller
80 100000
ns
ns
ns
ns
ns
ns
ns
ns
ns
tLOW
SCL Clock Low Period
24
32
24
32
24
32
12
tDIG_L
D3
D4
tHIGH_MIXED
tDIG_H_MIXED
tHIGH
SCL Clock High Period of Mixed Bus (Mixed Bus Topology
Not Supported)
Controller
Controller
Target
45
SCL Clock High Period
tDIG_H
D5
D6
tSCO
Clock in to Data Out for Target
SCL Clock Rise Time
tCR
Controller 150 × 1 /
fSCL
60
60
D7
D8
tCF
SCL Clock Fall Time
Controller 150 × 1 /
fSCL
ns
ns
tHD_PP
SDA Signal Data Hold in Push Pull Mode
Controller
tCR + 3
and tCF
+
3
Target
0
3
ns
ns
D9
tSU_PP
SDA Signal Data Setup In Push-Pull Mode
Controller,
Target
D10
D11
tCASr
tCBSr
Clock After Repeated START (Sr)
Clock Before Repeated START (Sr)
Controller
tCAS MIN
ns
ns
Controller tCAS MIN
/
2
1. FSCL = 1 / (tDIG_L + tDIG_H
)
2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL
and VIH.
3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained to
make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling.
4. As both edges are used, the hold time needs to be satisfied for the respective edges; tCF + 3 for falling edge
clocks, and tCR + 3 for rising edge clocks.
5. Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
188 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
0.7xVDD
0.3xVDD
SDA
D5
D11
D9
D10
D1
D5
D8
D2
D9
0.7xVDD
SCL
0.3xVDD
D4
D7
D6
Stop
Start
Repeated
Start
Stop
- Open drain with weak pull-up
- Open drain with weak pull-up
I3C_TIMING_02
图7-76. I3C Push-Pull Timing (SDR and HDR-DDR Modes)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 189
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.13 MCAN
表7-45 and 表7-46 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
备注
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
表7-45. MCAN Timing Conditions
PARAMETER
MIN
2
MAX
15
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
5
20
表7-46. MCAN Switching Characteristics
NO.
PARAMETER
DESCRIPTION
Delay time, transmit shift register to MCANn_TX
Delay time, MCANn_RX to receive shift register
MIN
MAX
10
UNIT
ns
MCAN1 td(MCAN_TX)
MCAN2 td(MCAN_RX)
10
ns
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
7.9.5.14 MCASP
For more details about features and additional description information on the device Multichannel Audio Serial
Port, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
节7.9.5.14.1 and 图7-77 present timing requirements for MCASP0 to MCASP11.
表7-47. MCASP Timing Conditions
PARAMETER
Input Conditions
SRI
DESCRIPTION
MIN
0.7
1
MAX
5
UNIT
V/ns
pF
Input slew rate
Output Conditions
CL
Output load capacitance
10
PCB Connectivity Requirements
td(Trace Delay)
Propagation delay of each trace
Propagation mismatch across all traces
100
1100
100
ps
ps
td(Trace Mismatch Delay)
7.9.5.14.1 Timing Requirements for MCASP
NO.1 PARAMETER
ASP1 tc(AHCLKRX)
ASP2 tw(AHCLKRX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKR/X
15.26
ns
ns
Pulse duration, AHCLKR/X high or low
-1.53 +
0.5P2
ASP3 tc(ACLKRX)
ASP4 tw(ACLKRX)
Cycle time, ACLKR/X
15.26
ns
ns
Pulse duration, ACLKR/X high or low
-1.53 +
0.5R3
ASP5 tsu(AFSRX-ACLKRX) Setup time, AFSR/X input valid before ACLKR/X
ACLKR/X int
ACLKR/X ext in/out
12.3
4
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
190 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.1 PARAMETER
DESCRIPTION
MODE
ACLKR/X int
MIN
-1
MAX UNIT
ASP6 th(ACLKRX-AFSRX) Hold time, AFSR/X input valid after ACLKR/X
ns
ACLKR/X ext in/out
ACLKR/X int
1.6
12.3
4
ASP7 tsu(AXR-ACLKRX)
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ns
ns
ACLKR/X ext in/out
ACLKR/X int
ASP8 th(ACLKRX-AXR)
-1
ACLKR/X ext in/out
1.6
1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
2. P = AHCLKR/X period in ns.
3. R = ACLKR/X period in ns.
ASP2
ASP1
ASP2
MCASP[x]_AHCLKR/X (Falling Edge Priority)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP4
ASP4
ASP3
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 191
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
图7-77. MCASP Input Timing
1. x in MCASP[x]_* is 0, 1 or 2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
192 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表 7-48 and 图 7-78 present switching characteristics over recommended operating conditions for MCASP0 to
MCASP11.
表7-48. Switching Characteristics Over Recommended Operating Conditions for MCASP
NO.1
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
ASP9 tc(AHCLKRX)
ASP10 tw(AHCLKRX)
ASP11 tc(ACLKRX)
ASP12 tw(ACLKRX)
Cycle time, AHCLKR/X
20
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
-2 + 0.5P2
20
Pulse duration, ACLKR/X high or low
-2 + 0.5R3
ASP13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSR/X
output valid
ACLKR/X int
0
-15.28
0
7.25
12.84
7.25
12.84
7.25
14
ns
ns
ns
ACLKR/X ext in/out
ASP14 td(ACLKX-AXR)
Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int
ACLKR/X ext in/out
ACLKR/X int
-15.28
0
ASP15 tdis(ACLKX-AXR)
Disable time, ACLKX transmit edge to AXR output
high impedance
ACLKR/X ext in/out
-14.9
1. ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
2. P = AHCLKR/X period in ns.
3. R = ACLKR/X period in ns.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 193
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
ASP10
ASP10
ASP9
MCASP[x]_AHCLKR/X (Falling Edge Priority)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP12
ASP12
ASP11
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
ASP13
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP13
ASP13
ASP13
MCASP[x]_AXR[x] (Data Out/Transmit)
ASP14
ASP15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
图7-78. MCASP Output Timing
1. x in MCASP[x]_* is 0, 1 or 2
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
7.9.5.15 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
表7-49 represents MCSPI timing conditions.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
194 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-49. MCSPI Timing Conditions
PARAMETER
MIN
MAX
UNIT
Input Conditions
SRI
Input slew rate
2
8.5
V/ns
Output Conditions
Output load capacitance
CLK
6
6
24
12
pF
pF
CL
D[x], CSi
7.9.5.15.1 MCSPI —Controller Mode
表 7-50, 图 7-79, 表 7-51, and 图 7-80 present timing requirements and switching characteristics for MCSPI –
Controller Mode.
表7-50. MCSPI Timing Requirements - Controller Mode
see 图7-79
PARAMETER
MIN
MAX
UNIT
tsu(misoV-
SM4
SM5
Setup time, SPI_D[x] valid before SPI_CLK active edge
2.9
ns
spiclkV)
th(spiclkV-
Hold time, SPI_D[x] valid after SPI_CLK active edge
2
ns
misoV)
表7-51. MCSPI Switching Characteristics - Controller Mode
see 图7-80
PARAMETER
MODE
MIN
MAX UNIT
SM1 tc(spiclk)
SM2 tw(spiclkL)
Cycle time, SPI_CLK
20.8
ns
0.5P -
1(1)
Pulse duration, SPI_CLK low
Pulse duration, SPI_CLK high
ns
ns
0.5P -
1(1)
SM3 tw(spiclkH)
Delay time, SPI_CLK active edge to SPI_D[x]
transition
SM6 td(spiclkV-simoV)
SM7 td(csV-simoV)
SM8 td(csV-spiclk)
2
ns
–2
Delay time, SPI_CSi active edge to SPI_D[x] transition
5
B - 4(3)
A - 4(4)
A - 4(4)
B - 4(3)
ns
ns
ns
ns
ns
PHA = 0(2)
PHA = 1 (2)
PHA = 0(2)
PHA = 1(2)
Delay time, SPI_CSi active to SPI_CLK first edge
SM9 td(spiclkV-csV)
Delay time, SPI_CLK last edge to SPI_CSi inactive
(1) P = SPI_CLK period in ns
(2) SPI_CLK phase is programmable with the PHA bit of the MCSPI_CHCONF_0/1/2/3 register
(3) B = (TCS + .5) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register and Fratio = Even >= 2.
(4) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.
When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 195
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SM5
SM5
SM4
Bit n-1
SM4
Bit n-2
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_02
图7-79. SPI Controller Mode Receive Timing
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
196 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
图7-80. MCSPI Controller Mode Transmit Timing
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 197
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.15.2 MCSPI —Peripheral Mode
表 7-52, 图 7-81, 表 7-53, and 图 7-82 present timing requirements and switching characteristics for MCSPI –
Peripheral Mode.
表7-52. MCSPI Timing Requirements - Peripheral Mode
PARAMETER
MIN
MAX
UNIT
ns
SS1
SS2
SS3
SS4
SS5
SS8
SS9
tc(spiclk)
Cycle time, SPI_CLK
20.8
tw(spiclkL)
Pulse duration, SPI_CLK low
0.45P(1)
ns
tw(spiclkH)
Pulse duration, SPI_CLK high
0.45P(1)
ns
tsu(simoV-spiclkV)
th(spiclkV-simoV)
tsu(csV-spiclkV)
th(spiclkV-csV)
Setup time, SPI_D[x] valid before SPI_CLK active edge
Hold time, SPI_D[x] valid after SPI_CLK active edge
Setup time, SPI_CSi valid before SPI_CLK first edge
Hold time, SPI_CSi valid after SPI_CLK last edge
5
5
5
5
ns
ns
ns
ns
表7-53. MCSPI Switching Characteristics - Peripheral Mode
PARAMETER
MIN
MAX
UNIT
SS6
td(spiclkV-
Delay time, SPI_CLK active edge to SPI_D[x] transition
2
17.12
ns
somiV)
SS7
tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition
20.95
ns
(1) P = SPI_CLK period in ns.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
198 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SPI_SCLK (IN)
SPI_SCLK (IN)
SS1
SS2
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
SPI_CS[i] (IN)
PHA=1
EPOL=1
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SPI_SCLK (IN)
SPI_SCLK (IN)
SS1
SS3
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_04
图7-81. SPI Peripheral Mode Receive Timing
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 199
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SPI_SCLK (IN)
SS1
SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
图7-82. MCSPI Peripheral Mode Transmit Timing
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
7.9.5.16 eMMC/SD/SDIO
The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure
Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO
protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,
and checking for syntactical correctness.
For more details about features and additional description information on the device Multi Media Card, see the
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
备注
MMC modes require software configuration of the delay settings, as shown in 表7-54 and 表7-64.
Tuning algorithm should be implemented to meet input setup/hold time requirements for SDR50,
DDR50 (only on MMCSD1), SDR104, HS200 and HS400 modes.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
200 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.1 MMCSD0 - eMMC Interface
MMCSD0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports
the following eMMC applications:
• Default speed
• High speed SDR
• High speed DDR
• High speed HS200
• High speed HS400
表7-54 presents the required DLL software configuration settings for MMC0 timing modes.
表7-54. MMC0 DLL Delay Mapping for All Timing Modes
REGISTER NAME
BIT FIELD
MMCSD0_SS_PHY_CTRL_4_REG
[15:12]
MMCSD0_SS_PHY_CTRL_5_REG
[31:24]
[20]
[8]
[4:0]
[17:16]
[10:8]
[2:0]
SELDLYTXCLK
SELDLYRXCLK
BIT FIELD NAME
STRBSEL
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
FRQSEL
CLKBUFSEL
OUTPUT
DELAY
ENABLE
OUTPUT
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DLL/
DELAY CHAIN
SELECT
DELAY
BUFFER
DURATION
STROBE
DELAY
DLL REF
FREQUENCY
MODE DESCRIPTION
8-bit PHY
Legacy
operating 1.8 V,
SDR
0x0
0x0
0x0
0x0
0x1
0x1
0x1
NA
NA
0x1
0x1
0x1
0x1
0x1
0x10
0xA
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x4
0x0
0x0
0x7
0x7
0x7
0x7
0x7
25 MHz
High
8-bit PHY
Speed operating 1.8 V,
SDR
High
50 MHz
8-bit PHY
Speed operating 1.8 V,
0x0
0x6
0x8
0x5
0x3
DDR
50 MHz
8-bit PHY
HS200 operating 1.8 V,
200 MHz
0x0
Tuning
Tuning
8-bit PHY
HS400 operating 1.8 V,
200 MHz
0x77
表7-55 represents MMCSD0 timing conditions.
表7-55. MMCSD0 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Legacy SDR
0.05
0.3
1.24 V/ns
1.65 V/ns
1.65 V/ns
High Speed SDR
SRI
Input slew rate
High Speed DDR (CMD) [DDR52]
0.3
High Speed DDR (DAT[7:0])
[DDR52]
0.3
1.65 V/ns
OUTPUT CONDITIONS
Legacy SDR
High Speed SDR
High Speed DDR
HS200
1
1
1
1
1
18
18
18
12
6
pF
pF
pF
pF
pF
CL
Output load capacitance
HS400
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
All modes
134
756
100
8
ps
ps
ps
Legacy SDR, High Speed SDR
High Speed DDR, HS200, HS400
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 201
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.1.1 Legacy SDR Mode
表 7-56 and 表 7-57 present Timing requirements and Switching characteristics in MMCSD0 - Legacy SDR
Mode (see 图7-83 and 图7-84).
表7-56. MMCSD0 Timing Requirements - Legacy SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
2.5
6.5
2.5
6.5
MAX
UNIT
ns
LSDR1 tsu(cmdV-clkH)
LSDR2 th(clkH-cmdV)
LSDR3 tsu(dV-clkH)
LSDR4 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
ns
ns
ns
图7-83. MMCSD0 - Legacy SDR - Receive Mode
表7-57. MMCSD0 Switching Characteristics - Legacy SDR Mode
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC0_CLK
Cycle time, MMC0_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
25
LSDR5
LSDR6
LSDR7
LSDR8
LSDR9
tc(clk)
40
tw(clkH)
Pulse duration, MMC0_CLK high
18.7
18.7
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
3.8
3.8
ns
–3.2
–3.2
ns
图7-84. MMC0 - Legacy SDR - Transmit Mode
7.9.5.16.1.2 High Speed SDR Mode
表 7-58 and 表 7-59 present Timing requirements and Switching characteristics for MMCSD0 – High Speed
SDR Mode (see 图7-85 and 图7-86 ).
表7-58. MMCSD0 Timing Requirements - High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
2.99
2.67
2.99
MAX
UNIT
ns
HSSDR1 tsu(cmdV-clkH)
HSSDR2 th(clkH-cmdV)
HSSDR3 tsu(dV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
ns
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
202 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.
表7-58. MMCSD0 Timing Requirements - High Speed SDR Mode (continued)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HSSDR4 th(clkH-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
2.67
ns
图7-85. MMCSD0 –High Speed SDR Mode –Receive Mode
表7-59. MMCSD0 Switching Characteristics - High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
HSSDR5 tc(clk)
Cycle time, MMC0_CLK
20
9.2
HSSDR6 tw(clkH)
HSSDR7 tw(clkL)
HSSDR8 td(clkL-cmdV)
HSSDR9 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
3.8
3.8
ns
–3.2
–3.2
ns
图7-86. MMCSD0 –High Speed SDR Mode –Transmit Mode
7.9.5.16.1.3 High Speed DDR Mode
表 7-60 and 表 7-61 present Timing requirements and Switching characteristics for MMCSD0 – High Speed
DDR Mode (see 图7-87 and 图7-88).
表7-60. MMCSD0 Timing Requirements - High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
HSDDR1 tsu(cmdV-clkH)
HSDDR2 th(clkH-cmdV)
HSDDR3 tsu(dV-clkV)
HSDDR4 th(clkV-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition
2.5
2.67
0.83
1.76
ns
ns
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 203
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
图7-87. MMCSD0 –High Speed DDR Mode –Receive Mode
表7-61. MMCSD0 Switching Characteristics - High Speed DDR Mode
NO.
PARAMETER
fop(clk)
HSDDR5 tc(clk)
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
Operating frequency, MMC0_CLK
50
Cycle time, MMC0_CLK
20
9.2
HSDDR6 tw(clkH)
HSDDR7 tw(clkL)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
HSDDR8 td(clkH-cmdV)
HSDDR9 td(clkV-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
3.31
2.81
9.8
ns
6.94
ns
图7-88. MMCSD0 –High Speed DDR Mode –Transmit Mode
7.9.5.16.1.4 HS200 Mode
表7-62 presents Switching characteristics for MMCSD0 –HS200 Mode (see 图7-89).
表7-62. MMCSD0 Switching Characteristics - HS200 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
HS2005
HS2006
HS2007
HS2008
HS2009
tc(clk)
Cycle time, MMC0_CLK
5
2.08
2.08
0.99
0.99
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
3.28
3.28
ns
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
204 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
图7-89. MMCSD0 –HS200 Mode –Transmit Mode
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 205
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.1.5 HS400 Mode
表7-63 presents Switching characteristics for MMCSD0 –HS400 Mode (see 图7-90).
表7-63. MMCSD0 Switching Characteristics - HS400 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
HS4005
HS4006
HS4007
HS4008
tc(clk)
Cycle time, MMC0_CLK
5
2.08
2.08
0.99
tw(clkH)
Pulse duration, MMC0_CLK high
Pulse duration, MMC0_CLK low
ns
tw(clkL)
ns
td(clkH-cmdV)
Delay time, MMC0_CLK rising clock edge to MMC0_CMD
transition
3.28
1.84
ns
HS4009
td(clkV-dV)
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
0.59
ns
HS4005
HS4006
HS4007
MMC0_CLK
MMC0_CMD
HS4008
HS4009
HS4009
MMC0_DAT[7:0]
图7-90. MMCSD0 –HS400 Mode –Transmit Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
206 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.2 MMCSDi —MMCSD1 —SD/SDIO Interface
备注
The MMCSDi (i = 1) controller is also referred to as MMCi.
MMCSDi interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I SDR104
• UHS–I DDR50
表7-64 presents the required delay software configuration settings for MMC1 timing modes.
表7-64. MMC1 Delay Mapping for All Timing Modes
REGISTER NAME
MMCSD12_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD12_SS_PHY_CTRL_5_REG
BIT FIELD
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0xF
0xF
0xC
0xC
0x5
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x0
0x0
0x7
0x7
0x7
0x7
0x7
0x7
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
Tuning
Tuning
Tuning
UHS-I
DDR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
表7-65 represents MMCSD1 timing conditions.
表7-65. MMCSD1 Timing Conditions
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
INPUT CONDITIONS
Default Speed, High
Speed
0.69
0.34
2.06 V/ns
1.34 V/ns
SRI
Input slew rate
UHS-I SDR12, UHS-I
SDR25
OUTPUT CONDITIONS
CL
Output load capacitance
All Speed Modes
1
10
pF
PCB CONNECTIVITY REQUIREMENTS
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 207
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-65. MMCSD1 Timing Conditions (continued)
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Default Speed, High
Speed
126
1200
ps
td(Trace Delay)
Propagation delay of each trace
UHS-I DDR50
All Other Modes
UHS-I DDR50
UHS-I SDR104
All Other Modes
255
134
1134
1276
20
ps
ps
ps
ps
ps
Propagation delay mismatch across all
traces
td(Trace Mismatch Delay)
8
100
7.9.5.16.2.1 Default speed Mode
表 7-66 and 表 7-67 present timing requirements and switching characteristics for MMCSDi – Default Speed
Mode (see 图7-91 and 图7-92)
表7-66. MMCSD1 Timing Requirements –Default Speed Mode
NO.
DS1
DS2
DS3
DS4
PARAMETER
DESCRIPTION
MIN
2.15
4.56
2.15
4.56
MAX
UNIT
ns
tsu(cmdV-clkH)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
ns
ns
ns
1. x = 1 for MMC1
MMC[x]_CLK
DS2
DS4
DS1
DS3
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-91. MMCSD1 –Default Speed –Receive Mode
表7-67. MMCSD1 Switching Characteristics –Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMC[x]_CLK
40
18.7
tw(clkH)
Pulse duration, MMC[x]_CLK high
ns
tw(clkL)
Pulse duration, MMC[x]_CLK low
18.7
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition
3.53
3.53
ns
–3.53
–3.53
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
图7-92. MMCSD1 –Default Speed –Transmit Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
208 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.2.2 High Speed Mode
表7-68 and 表7-69 present timing requirements and switching characteristics for MMCSDi –High Speed Mode
(see 图7-93 and 图7-94).
表7-68. MMCSD1 Timing Requirements –High Speed Mode
NO.
HS1
HS2
HS3
HS4
PARAMETER
DESCRIPTION
MIN
2.15
2.26
2.15
2.26
MAX
UNIT
ns
tsu(cmdV-clkH)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
ns
ns
ns
MMC[x]_CLK
HS1
HS3
HS2
HS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-93. MMCSD1 –High Speed –Receive Mode
表7-69. MMCSD1 Switching Characteristics –High Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
Cycle time. MMC[x]_CLK
20
9.2
tw(clkH)
Pulse duration, MMC[x]_CLK high
ns
tw(clkL)
Pulse duration, MMC[x]_CLK low
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition
2.07
2.07
ns
–2.07
–2.07
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0]
transition
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-94. MMCSD1 –High Speed –Transmit Mode
7.9.5.16.2.3 UHS–I SDR12 Mode
表 7-70 and 表 7-71 present timing requirements and switching characteristics for MMCSDi – UHS-I SDR12
Mode(see 图7-95 and 图7-96).
表7-70. MMCSD1 Timing Requirements –UHS-I SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.46
1.67
5.46
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
ns
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 209
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-70. MMCSD1 Timing Requirements –UHS-I SDR12 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR124 th(clkH-dV)
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
1.67
ns
MMC[x]_CLK
MMC[x]_CMD
SDR122
SDR124
SDR121
SDR123
MMC[x]_DAT[3:0]
图7-95. MMCSD1 –UHS-I SDR12 –Receive Mode
表7-71. MMCSD1 Switching Characteristics –UHS-I SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
25
SDR125 tc(clk)
Cycle time, MMC[x]_CLK
40
18.7
18.7
1.2
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkH-cmdV)
SDR129 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
13.55
13.55
ns
1.2
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
图7-96. MMCSD1 –UHS-I SDR12 –Transmit Mode
7.9.5.16.2.4 UHS–I SDR25 Mode
表 7-72 and 表 7-73 present timing requirements and switching characteristics for MMCSDi – UHS-I SDR25
Mode (see 图7-97 and 图7-98).
表7-72. MMCSD1 Timing Requirements –UHS-I SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
2.1
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
1.67
2.1
ns
ns
1.67
ns
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
210 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
MMC[x]_CLK
MMC[x]_CMD
SDR252
SDR254
SDR251
SDR253
MMC[x]_DAT[3:0]
图7-97. MMCSD1 –UHS-I SDR25 –Receive Mode
表7-73. MMCSD1 Switching Characteristics –UHS-I SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
50
SDR255 tc(clk)
Cycle time, MMC[x]_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkH-cmdV)
SDR259 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
9.37
9.37
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
图7-98. MMCSD1 –UHS-I SDR25 –Transmit Mode
7.9.5.16.2.5 UHS–I SDR50 Mode
表 7-74 presents timing requirements and switching characteristics for MMCSDi – UHS-I SDR50 Mode (see
and 图7-99).
表7-74. MMCSD1 Switching Characteristics –UHS-I SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
100
SDR505 tc(clk)
Cycle time, MMC[x]_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkH-cmdV)
SDR509 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
211
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
SDR505
SDR506
SDR507
MMC[x]_CLK
MMC[x]_CMD
SDR508
SDR508
SDR509
SDR509
MMC[x]_DAT[3:0]
图7-99. MMCSD1 –UHS-I SDR50 –Transmit Mode
7.9.5.16.2.6 UHS–I DDR50 Mode
表7-75 present switching characteristics for MMCSDi –UHS-I DDR50 Mode (see 图7-100).
表7-75. MMCSD1 Switching Characteristics –UHS-I DDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMC[x]_CLK
20
9.2
9.2
1.2
1.2
tw(clkH)
Pulse duration, MMC[x]_CLK high
ns
tw(clkL)
Pulse duration, MMC[x]_CLK low
ns
td(clkH-cmdV)
td(clk-dV)
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK transition to MMC[x]_DAT[3:0] transition
3.46
6.12
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
图7-100. MMCSD1 –UHS-I DDR50 –Transmit Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
212 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.16.2.7 UHS–I SDR104 Mode
表7-76 presents timing requirements and switching characteristics for MMCSDi –UHS-I SDR104 Mode (see 图
7-101)
表7-76. MMCSD1 Switching Characteristics –UHS-I SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
200
SDR1045 tc(clk)
Cycle time, MMC[x]_CLK
5
2.12
2.12
2.12
2.12
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkH-cmdV)
SDR1049 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
3.2
3.2
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
MMC[x]_CMD
SDR1049
SDR1049
MMC[x]_DAT[3:0]
图7-101. MMCSD1 –UHS-I SDR104 –Transmit Mode
7.9.5.17 NAVSS
表7-77 represents CPTS timing conditions.
表7-77. CPTS Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
0.5
2
MAX
5
UNIT
Input slew rate
V/ns
pF
Output Conditions
CLOAD
Output load capacitance
10
节 7.9.5.17.1, 节 7.9.5.17.2, 图 7-102, and 图 7-103 present timing requirement and switching characteristics of
the CPTS interface.
7.9.5.17.1 Timing Requirements for CPTS Input
NO.
T1
PARAMETER
tw(HWn_TS_PUSHH)
tw(HWn_TS_PUSHL)
tc(RFT_CLK)
DESCRIPTION
HWn_TS_PUSH Pulse duration, high
HWn_TS_PUSH pulse duration, low
RFT_CLK cycle time
MIN
2.1 + 12P(1)
2.1 + 12P(1)
5
MAX
UNIT
ns
T2
ns
T3
8
ns
T4
tw(RFT_CLKH)
RFT_CLK pulse duration, high
0.45 ×
ns
tc(RFT_CLK)
T5
tw(RFT_CLKL)
RFT_CLK pulse duration, low
0.45 ×
ns
tc(RFT_CLK)
(1) P = functional clock period in ns.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 213
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
T1
T2
CPTS_HWn_TS_PUSH
CPTS_RFT_CLK
T3
T4
T5
图7-102. CPTS Input Timing
7.9.5.17.2 Switching Characteristics for CPTS Output
NO.
T6
PARAMETER
tw(TS_COMPH)
DESCRIPTION
NAVSS-CPTS TS_COMP, high
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+36P(1)
-2.1+5P(1)
T7
tw(TS_COMPL)
tw(TS_COMPH)
tw(TS_COMPL)
tw(TS_SYNCH)
tw(TS_SYNCL)
tw(TS_SYNCH)
tw(TS_SYNCL)
tw(SYNC_OUTH)
tw(SYNC_OUTL)
tw(SYNC_OUTH)
tw(SYNC_OUTL)
NAVSS-CPTS TS_COMP, low
CPSW-CPTS TS_COMP, high
CPSW-CPTS TS_COMP, low
T8
T9
T10
T11
T12.1
T13
T14
T15
T16
T17
NAVSS-CPTS TS_SYNC, high
NAVSS-CPTS TS_SYNC, low
CPSW-CPTS TS_SYNC, high
CPSW-CPTS TS_SYNC, low
TS_SYNC sourcing SYNCn_OUT, high
TS_SYNC sourcing SYNCn_OUT, low
GENF sourcing SYNCn_OUT, high
GENF sourcing SYNCn_OUT, low
-2.1+5P(1)
(1) P = functional clock period in ns.
T6
T7
CPTS_TS_COMP
T8
T9
CPTS_TS_SYNC
T10
T11
CPTS_SYNC_OUT
图7-103. CPTS Output Switching Characteristics
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter
in the device TRM.
7.9.5.18 OSPI
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
表7-78 represents OSPI timing conditions.
表7-78. OSPIx Timing Conditions
PARAMETER
MODE
MIN
MAX UNIT
INPUT CONDITIONS
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
214 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-78. OSPIx Timing Conditions (continued)
PARAMETER
Input slew rate
MODE
MIN
MAX UNIT
SRI
1
6
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
3
10
pF
PCB CONNECTIVITY REQUIREMENTS
No Loopback
Propagation delay of OSPI0_CLK traces
Internal PHY Loopback
Internal Pad Loopback
450
ps
td(Trace Delay)
Propagation delay of OSPI0_LBCLKO
traces
External Board Loopback
2L(1) - 30
L(1) - 30
2L(1) + 30
L(1) + 30
ps
ps
Propagation delay of OSPI0_DQS traces DQS
Propagation delay mismatch of
OSPIx_D[7:0] and OSPIx_CSn[3:0]
relative to OSPIx_CLK
td(Trace Mismatch
All modes
60
ps
Delay)
(1) L = Propagation delay of OSPIx_CLK trace
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
7.9.5.18.1 OSPI With Data Training
7.9.5.18.1.1 OSPI Switching Characteristics –Data Training
PARAMETER
DESCRIPTION
MODE
MIN
6.02
MAX
UNIT
ns
tc(CLK)
Cycle time, CLK
Cycle time, CLK
DDR, 1.8V
DDR, 3.3V
SDR, 1.8V
SDR, 3.3V
7.52
6.02
7.52
ns
tc(CLK)
ns
ns
7.9.5.18.2 OSPI Without Data Training
备注
The I/O Timings provided in this section are only applicable when data training is not implemented.
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL
Delays are configured as described in 表7-79 found in this section.
节 7.9.5.18.2.1, 节 7.9.5.18.2.2, 图 7-104, and 图 7-105 present switching characteristics for OSPI DDR and
SDR Mode.
7.9.5.18.2.1 OSPI Switching Characteristics –DDR Mode
NO.(1) PARAMETER
DESCRIPTION
MODE
1.8V
MIN
MAX
UNIT
ns
O1 tc(CLK)
Cycle time, CLK
19
19
3.3V
ns
O2 tw(CLKL)
O3 tw(CLKH)
O4 td(CLK-CSn)
Pulse duration, CLK low
Pulse duration, CLK high
-0.3+0.475*P
ns
(2)
-0.3+0.475*P
ns
ns
(2)
Delay time, CSn[3:0] active edge to CLK rising
edge
1.8V, OSPI0 DDR TX; -7-0.475 * P
0.525 * P +
1.8V, OSPI1 DDR TX
1.025 * M * R
–0.975 * N *
+ 1 (3) (4) (5)
R (3) (4) (5)
3.3V, OSPI0 DDR TX; -7-0.475 * P
0.525 * P +
1.025 * M * R
+ 1 (3) (4) (5)
ns
3.3V, OSPI1 DDR TX
–0.975 * N *
R (3) (4) (5)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 215
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
NO.(1) PARAMETER
DESCRIPTION
MODE
MIN
MAX
0.525 * P +
UNIT
O5 td(CLK-CSn)
Delay time, CLK rising edge to CSn inactive
edge
1.8V, OSPI0 DDR TX; -7+0.475 * P
1.8V, OSPI1 DDR TX + 0.975 * N * 1.025 * N * R
ns
R (3) (4) (5)
+ 1 (3) (4) (5)
3.3V, OSPI0 DDR TX; -7+0.475 * P
0.525 * P +
ns
3.3V, OSPI1 DDR TX + 0.975 * N * 1.025 * N * R
R (3) (4) (5)
+ 1 (3) (4) (5)
O6 td(CLK-D)
Delay time, CLK active edge to D[i:0] transition
1.8V, OSPI0 DDR TX;
1.8V, OSPI1 DDR TX
-7.7
-1.56
ns
ns
3.3V, OSPI0 DDR TX;
3.3V, OSPI1 DDR TX
-7.7
-1.56
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) P = CLK cycle time
(3) P = SCLK period
(4) M = OSPI_DEV_DELAY_REG[D_INIT_FLD], N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(5) R = refclk
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O6
O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
图7-104. OSPI Switching Characteristics –DDR
7.9.5.18.2.2 OSPI Switching Characteristics –SDR Mode
NO.(1) PARAMETER
DESCRIPTION
MODE
1.8V
MIN
MAX
UNIT
ns
O7 tc(CLK)
Cycle time, CLK
7
3.3V
7.52
ns
O8 tw(CLKL)
O9 tw(CLKH)
O10 td(CLK-CSn)
Pulse duration, CLK low
Pulse duration, CLK high
-0.3+0.475*P
ns
(2)
-0.3+0.475*P
ns
ns
(2)
Delay time, CSn[3:0] active edge to CLK rising
edge
1.8V
3.3V
1.8V
3.3V
-1-0.475 * P
–0.975 * N *
R (3) (4) (5)
0.525 * P +
1.025 * M * R
+ 1 (3) (4) (5)
-1-0.475 * P
–0.975 * N *
R (3) (4) (5)
0.525 * P +
1.025 * M * R
+ 1 (3) (4) (5)
ns
ns
ns
O11 td(CLK-CSn)
Delay time, CLK rising edge to CSn inactive
edge
-1+0.475 * P
0.525 * P +
+ 0.975 * N * 1.025 * N * R
R (3) (4) (5)
+ 1(3) (4) (5)
-1+0.475 * P
0.525 * P +
+ 0.975 * N * 1.025 * N * R
R (3) (4) (5)
+ 1 (3) (4) (5)
O12 td(CLK-D)
Delay time, CLK active edge to D[i:0] transition
1.8V
3.3V
-1.15
1.25
ns
ns
-1.33
1.51
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
216 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
(2) P = CLK cycle time
(3) P = SCLK period
(4) M = OSPI_DEV_DELAY_REG[D_INIT_FLD], N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(5) R = refclk
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
图7-105. OSPI Switching Characteristics –SDR
节 7.9.5.18.2.3, 节 7.9.5.18.2.4, 图 7-106, 图 7-107, 图 7-108, and 图 7-109 presents timing requirements for
OSPI DDR and SDR Mode.
7.9.5.18.2.3 OSPI Timing Requirements –DDR Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
5.23
MAX
UNIT
(1)
O13 tsu(D-CLK)
O14 th(CLK-D)
O15 tsu(D-LBCLK)
O16 th(LBCLK-D)
O17 tsu(D-DQS)
O18 th(DQS-D)
Setup time, D[i:0] valid before active CLK edge
1.8V, No Loopback Clock; 1.8V,
Internal Pad Loopback Clock
ns
3.3V, No Loopback Clock; 3.3V,
Internal Pad Loopback Clock
6.19
1.84
2.34
0.52
1.97
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold time, D[i:0] valid after active CLK edge
1.8V, No Loopback Clock; 1.8V,
Internal Pad Loopback Clock
3.3V, No Loopback Clock; 3.3V,
Internal Pad Loopback Clock
Setup time, D[i:0] valid before active LBCLK (DQS) 1.8V, External Board Loopback
edge
Clock
3.3V, External Board Loopback
Clock
Hold time, D[i:0] valid after active LBCLK (DQS)
edge
1.8V, External Board Loopback 1.2 (2)
Clock
3.3V, External Board Loopback 1.44 (2)
Clock
Setup time, DQS edge to D[i:0] transition
Hold time, DQS edge to D[i:0] transition
1.8V, OSPI0 DQS;
1.8V, OSPI1 DQS
-0.46
-0.66
3.59
7.92
3.3V, OSPI0 DQS;
3.3V, OSPI1 DQS
1.8V, OSPI0 DQS;
1.8V, OSPI1 DQS
3.3V, OSPI0 DQS;
3.3V, OSPI1 DQS
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external
loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 217
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
OSPI_CLK
OSPI_D[i:0]
O13 O14 O13 O14
OSPI_TIMING_03
图7-106. OSPI Timing Requirements –DDR, No Loopback Clock and Internal Pad Loopback Clock
OSPI_DQS
O15 O16 O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
图7-107. OSPI Timing Requirements –DDR, External Loopback Clock and DQS
7.9.5.18.2.4 OSPI Timing Requirements –SDR Mode
NO. PARAMETE
DESCRIPTION
MODE
MIN
4.8
MAX UNIT
(1)
R
O19 tsu(D-CLK)
Setup time, D[i:0] valid before active CLK
edge
1.8V, No Loopback Clock
3.3V, No Loopback Clock
ns
ns
ns
ns
ns
ns
ns
ns
5.39
-0.5
-0.5
0.6
0.9
1.7
2
O20 th(CLK-D)
Hold time, D[i:0] valid after active CLK edge
1.8V, No Loopback Clock
3.3V, No Loopback Clock
O21 tsu(D-LBCLK)
Setup time, D[i:0] valid before active LBCLK
input (DQS) edge
1.8V, External Board Loopback Clock
3.3V, External Board Loopback Clock
1.8V, External Board Loopback Clock
3.3V, External Board Loopback Clock
O22 th(LBCLK-D)
Hold time, D[i:0] valid after active LBCLK
input (DQS) edge
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
图7-108. OSPI Timing Requirements –SDR, No Loopback Clock and Internal Pad Loopback Clock
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
218 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
OSPI_DQS
OSPI_D[i:0]
O21
O22
OSPI_TIMING_06
图7-109. OSPI Timing Requirements –SDR, External Loopback Clock
表7-79. OSPI DLL Delay Mapping for Timing Modes
OSPI_PHY_CONFIGURATION_REG
MODE
TRANSMIT
DELAY VALUE
BIT FIELD
1.8 V
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
0x54
0x55
3.3 V
RECEIVE
1.8 V, DQS
3.3 V, DQS
All other modes
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
0x2D
0x29
0x0
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
7.9.5.19 PCIE
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express, see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed
Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
7.9.5.20 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.
表7-80 represents Timers timing conditions.
表7-80. Timers Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MODE
CAPTURE
PWM
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
Input slew rate
Output Conditions
CLOAD
Output load capacitance
10
节7.9.5.20.1, 节7.9.5.20.2 and 图7-110 present timings and switching characteristics of the Timers.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 219
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.20.1 Timing Requirements for Timers
NO.
PARAMETER
tw(TINPH)
DESCRIPTION
MODE
MIN
MAX UNIT
T1
Pulse duration, high
Pulse duration, low
CAPTURE
2.5 +
4P(1)
ns
T2
tw(TINPL)
CAPTURE
2.5 +
4P(1)
ns
(1) P = functional clock period in ns.
7.9.5.20.2 Switching Characteristics for Timers
NO.
PARAMETER
tw(TOUTH)
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
Pulse duration, high
Pulse duration, low
PWM
-2.5 +
4P(1)
ns
T4
tw(TOUTL)
PWM
-2.5 +
4P(1)
ns
(1) P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
图7-110. Timer Timing
For more information, see Timers section in Peripherals chapter in the device TRM.
7.9.5.21 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed
Description.
表7-81 represents UART timing conditions.
表7-81. UART Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
Input slew rate
Output Conditions
CLOAD
Output load capacitance
30(1)
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
节 7.9.5.21.1, 节 7.9.5.21.2, and 图 7-111 present timing requirements and switching characteristics for UART
interface.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
220 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
7.9.5.21.1 UART Timing Requirements
NO.
PARAMETER
tw(RX)
DESCRIPTION
MIN
MAX
UNIT
4
Pulse width, receive data bit, high or low
0.95U(1)
1.05U(1)
ns
(2)
(2)
5
tw(CTS)
Pulse width, receive start bit, high or low
0.95U(1)
ns
(2)
(1) U = UART baud time = 1/Programmed baud rate
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
7.9.5.21.2 UART Switching Characteristics
NO.
PARAMETER
f(baud)
DESCRIPTION
Maximum programmable baud rate
MIN
MAX
12
UNIT
Mbps
ns
2
3
tw(TX)
Pulse width, transmit data bit, high or low
Pulse width, transmit start bit, high or low
U - 2(1)
U - 2(1)
U + 2(1)
tw(RTS)
ns
(1) U = UART baud time = 1/Programmed baud rate
2
1
Start
Bit
VIH
UARTi_RXD
VIL
Data Bits
4
3
Start
Bit
UARTi_TXD
Data Bits
UART_TIMING_01_RCVRVIHVIL
图7-111. UART Timing
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.9.5.22 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1
Specification, revision 1.0. Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed
Description.
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
7.9.6 Emulation and Debug
7.9.6.1 Debug Trace
表7-83 represents Debug Trace timing conditions.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 221
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表7-82. Debug Trace Timing Conditions
PARAMETER
MIN
MAX
5
UNIT
pF
Output Conditions
CL
Output load capacitance
2
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch) Propagation delay mismatch across all traces
200
ps
表 7-83 and 图 7-112 assume testing over the recommended operating conditions and electrical characteristic
conditions.
表7-83. Debug Trace Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1.8 V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
6.50
2.50
2.50
0.81
ns
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
DBTR4 tosu(TRC_DATAV-
Output setup time, TRC_DATA valid to TRC_CLK edge
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.81
0.81
0.81
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
3.3 V Mode
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
9.75
4.13
4.13
1.22
ns
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
DBTR4 tosu(TRC_DATAV-
Output setup time, TRC_DATA valid to TRC_CLK edge
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.22
1.22
1.22
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
图7-112. Debug Trace Timing
7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
For more details about features and additional description information on the device IEEE 1149.1 Standard–
Test–Access Port, see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed
Description.
表7-84 represents JTAG timing conditions.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
222 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
备注
The JTAG signals are split across two IO power domains on the device. Timings parameters defined
in this section only apply when the two IO power domains are operating at the same voltage and level-
shifters are not inserted into the signal path. Values for the following timing parameters are not defined
when operating the two IO power domains at different voltages since propagation delay through the
device IO buffers differ when some are operating at 1.8V while others are operating at 3.3V. This
effectively reduces timing margin beyond the values defined in this section. The JTAG interface is still
expected to function when the two IO power domains are operated at different voltages, assuming the
system designer has implemented appropriate level-shifters and the operating frequency is reduced to
accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages
表7-84. JTAG Timing Conditions
PARAMETER
MIN
0.50
5
MAX
2.00
15
UNIT
V/ns
pF
Input Conditions
tSR
Input slew rate
Output Conditions
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
83.5
1000(1)
100
ps
ps
Propagation delay mismatch across all
traces
td(Trace Mismatch Delay)
(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
7.9.6.2.1 JTAG Electrical Data and Timing
节 7.9.6.2.1.1, 节 7.9.6.2.1.2, and 图 7-113 assume testing over the recommended operating conditions and
electrical characteristic conditions.
7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
NO.
J1
MIN
46.5(1)
0.4P(2)
0.4P(2)
4.5
MAX
UNIT
ns
tc(TCK)
Cycle time minimum, TCK
J2
tw(TCKH)
Pulse width minimum, TCK high
ns
J3
tw(TCKL)
Pulse width minimum, TCK low
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
Input setup time minimum, TDI valid to TCK high
Input setup time minimum, TMS valid to TCK high
Input hold time minimum, TDI valid from TCK high
Input hold time minimum, TMS valid from TCK high
ns
J4
J5
4.5
ns
2
ns
2
ns
(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
•
•
Minimum TDO setup time of 4.6 ns relative to the rising edge of TCK
TDI and TMS output delay in the range of -16.5 ns to 14.0 ns relative to the falling edge of TCK
(2) P = TCK cycle time in ns
7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
J6
PARAMETER
td(TCKL-TDOI)
td(TCKL-TDOV)
DESCRIPTION
Delay time minimum, TCK low to TDO invalid
Delay time maximum, TCK low to TDO valid
MIN
MAX
UNIT
ns
0
J7
12
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 223
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
J1
J2
J3
TCK
J4
J5
J4
J5
TDI / TMS
J7
J6
TDO
图7-113. JTAG Test–Port Timing
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
224 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
8 Detailed Description
8.1 Overview
Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are System-on-Chip (SoCs) that provide
lower system cost through integration of features including system MCU, Ethernet switch, safety, security. Multi-
core system enables ECU consolidation for automotive applications such as automotive gateway and vehicle
compute systems. The integrated diagnostics and functional safety features are targeted to ASIL-D certification/
requirements. The Integrated Microcontroller (MCU) island eliminates the need for an external system MCU. In
addition to the PCIe hub, the device features up to four Gigabit Ethernet ports with integrated switch to meet
networking use cases that require heavy data bandwidth and also includes PCIe hub functionality. Twenty CAN-
FD and up to twelve UART interfaces are available on the device. Up to four general purpose Arm® Cortex®-R5F
subsystems can handle low level, timing critical processing tasks and leave the Arm® Cortex®-A72’s
unencumbered for advanced applications.
备注
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 225
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
8.2 Processor Subsystems
8.2.1 Arm Cortex-A72
The device implements one dual-core Arm® Cortex®-A72 MPU, which is integrated inside the Compute Cluster,
along with other modules. The Cortex-A72 cores are general-purpose processors that can be used for running
customer applications.
The A72SS is built around the Arm Cortex-A72 MPCore (A72 cluster), which is provided by Arm and configured
by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and
optimal power management and debug capabilities.
The A72 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 instruction and
data caches, compatible with Armv8-A architecture. The Armv8-A architecture brings a number of new features.
These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers.
For more information, see Dual-A72 MPU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.2 Arm Cortex-R5F
The MCU_ARMSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®
CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and
various wrappers for protocol conversion and address translation for easy integration into the SoC.
For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.3 Other Subsystems
8.3.1 MSMC
The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster
(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected
processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute
cluster.
For more information, see Multicore Shared Memory Controller (MSMC) section in Device Configuration chapter
in the device TRM.
8.3.2 NAVSS
8.3.2.1 NAVSS0
Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and
Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), Virtualization translation (VirtSS), and
a North Bridge (NBSS).
8.3.2.2 MCU_NAVSS
MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated
in the MCU domain.
MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator
(UDMASS), and Peripherals (Module subsystem [MODSS]).
For more information, see Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem (MCU NAVSS)
sections in Data Movement Architecture (DMA) chapter in the device TRM.
8.3.3 PDMA Controller
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of
peripherals, which perform data transfers using memory mapped registers accessed via a standard non-
coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
226 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and
supporting only statically configured Transfer Request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer
complexity at each point in the system to match the requirements of whatever is being transferred to or from.
Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and
employs round-robin scheduling between channels in order to share the underlying DMA hardware.
For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.
8.3.4 Peripherals
8.3.4.1 ADC
The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1
of 8 analog inputs (channels).
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
8.3.4.2 ATL
The Audio Tracking Logic (ATL) is used by HD Radio™ applications to synchronize the digital audio output to the
baseband clock. This same IP can also be used generically to track errors between two reference signals (such
as frame syncs) and generate a modulated clock output (using software-controlled cycle stealing) which
averages to some desired frequency. This process can be used as a hardware assist for asynchronous sample
rate conversion algorithms.
For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.
8.3.4.3 CPSW2G
The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication for the
device and is configured in a similar manner as an Ethernet switch. MCU_CPSW0 features the Reduced Gigabit
Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data
Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.
8.3.4.4 CPSW5G
The 5-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device
and can be configured as an Ethernet switch. CPSW0 features the 1G and 2.5G Serial Gigabit Media
Independent Interface (SGMII), Universal Serial 10G Media Independent Interface (USXGMII), 10G Form-factor
Interface (XFI), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface
(RMII) and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device
TRM.
8.3.4.5 DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution
of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 227
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.
8.3.4.6 DDRSS
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these
blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to
external SDRAM devices which can be utilized for storing program or data. Specifically, the DDR subsystem
supports LPDDR4 devices compliant to the JEDEC JESD209-4B standard. DDRSS0 is accessed via MSMC,
and not directly through the system interconnect.
备注
The DDRSS does not support byte mode LPDDR4 memories, or memories with more than 17 row
address bits.
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.
8.3.4.7 ECAP
The enhanced Capture (ECAP) module can be used for:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
8.3.4.8 EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so
forth.
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules
can also operate stand-alone.
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
8.3.4.9 ELM
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then
correct the data block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
228 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.
8.3.4.10 ESM
The Error Signaling Module (ESM) aggregates events and/or errors from throughout the device into one location.
It can signal both low and high priority interrupts to a processor to deal with an event and/or manipulate an I/O
error pin to signal an external hardware that an error has occurred. Therefore an external controller is able to
reset the device or keep the system in a safe, known state.
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.
8.3.4.11 EQEP
The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined
as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is
added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate
an absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position and zero reference.
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
8.3.4.12 GPIO
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
8.3.4.13 GPMC
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external
memory devices like:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
• NAND flash
• Pseudo-SRAM devices
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
8.3.4.14 Hyperbus
The Hyperbus module is a part in the device Flash Subsystem (FSS).
The Hyperbus module is a low pin count memory interface that provides high read/write performance. The
Hyperbus module connects to Hyperbus memory (HyperFlash or HyperRAM) and uses simple Hyperbus
protocol for read and write transactions.
There is one Hyperbus™ module inside the device. The Hyperbus module includes one Hyperbus Memory
Controller (HBMC).
For more information, see Hyperbus Interface section in Peripherals chapter in the device TRM.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 229
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
8.3.4.15 I2C
The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface
between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I2C-bus-compatible
device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit
and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.
The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and
support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1,
I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate
open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by
configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device
TRM.
8.3.4.16 I3C
The device contains three Improved Inter-Integrated Circuit (I3C) controllers each of which provides an interface
between a local host (LH), such as an Arm, and any I3C-bus-compatible device that connects via the I3C serial
bus.
For more information, see Improved Inter-Integrated Circuit (I3C) Interface section in Peripherals chapter in the
device TRM.
8.3.4.17 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are
broadcast to the entire network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device
TRM.
8.3.4.18 MCASP
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio
applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for
time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for
an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly
connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.
Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not
natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows
an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
8.3.4.19 MCRC Controller
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the
signature for a set of data and then compare the calculated signature value against a predetermined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
230 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC
controller compresses each data being read through CPU read data bus.
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device
TRM.
8.3.4.20 MCSPI
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.
There are total of eleven MCSPI modules in the device.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
8.3.4.21 MMC/SD
The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure
Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO
protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,
and checking for syntactical correctness.
For more information, see Multimedia Card/Secure Digital (MMC/SD) Interface section in Peripherals chapter in
the device TRM.
8.3.4.22 OSPI
The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI) module
which allows single, dual, quad or octal read and write access to external flash devices.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up
to silently perform some requested operation, signaling its completion via interrupts or status registers.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
8.3.4.23 PCIE
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe
controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps
per lane for serial links on backplanes and printed wiring boards.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
8.3.4.24 SerDes
SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed
electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can
be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the
external analog interface as well as the internal digital logic.
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.
8.3.4.25 WWDT
The Windowed Watchdog Timer provides timer functionality for operating systems and for benchmarking code.
The module incorporates several counters, which define the timebases needed for scheduling in the operating
system. The module is implemented with an RTI module, but only WWDT is supported.
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for
Automotive Electronics”) as well as OSEK/Time compliant operating systems.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 231
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.
8.3.4.26 Timers
All timers include specific functions to generate accurate tick interrupts to the operating system.
Each timer can be clocked from several different independent clocks. The selection of clock source is made from
registers in the MCU_CTRL_MMR0/CTRL_MMR0.
In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer
PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0
through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each
MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[9-0] PWM output.
In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM
outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances.
System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0]
source for each TIMER_IO[7-0] PWM output.
Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous
even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be
cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.
When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32- bit
prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at
the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.
For more information, see Timers section in Peripherals chapter in the device TRM.
8.3.4.27 UART
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There
are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function
clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
Peripherals chapter in the device TRM.
8.3.4.28 USB
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports one USB subsystem:
• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY
and HS/FS/LS (1) (USB2.0) PHY
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
232 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
9 Applications, Implementation, and Layout
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test design
implementation to confirm system functionality.
9.1 Power Supply Mapping
TPS6594x and LP8764x are the Power Management ICs (PMIC) that should be used for Power Distribution
Network (PDN) designs to support this device. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for the
entire system
• Support for power sequencing requirements (refer to 节7.9.2, Power Supply Sequences)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
When combining device voltage domains into a common power rail is allowed, the most strigent voltage domain
PDN guideline must be implemented for the common power rail.
It is possible that some device voltage domains may be unused in some systems. In such cases, all unused
voltage domain supply pins must still be connected to a valid power rail with a proper voltage level in order to
ensure device reliability (refer to Section 4.3, Signal Descriptions). For example, if MCU is not used, then
vdd_mcu domain can be combined with the CORE domain (vdd_core) that has the same voltage specifications.
A buck converter power stage connected to the common power rail would then supply both CORE and MCU
domains.
For the combined rail, the following relaxations apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
图 9-1 shows an example of the detailed power mapping between the processor and TPS659414-Q1 and
LP876441-Q1 PMICs. In this configuration, both PMIC devices use a 3.3V input voltage. For more details, refer
to the appnote titled “User's Guide for Powering DRA821 with the TPS6594-Q1 and LP8764-Q1 PMICs".
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 233
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
TPS6594-Q1
Processor
ON REQUEST
ENABLE
SAFETY MCU CONTROLS
Safety MCU GPIO
INTn
nRSTOUT
MCU_PORz
SCL_I2C1
SDA_I2C1
WKUP_I2C0_SCL/SDA
GPIO_1 (SCL_I2C2)
GPIO_2 (SDA_I2C2)
GPIO_3 (GPO)
MCU_I2C0_SCL/SDA
MCU_SAFETY_ERRORn
PMIC_POWER_EN1
PORz
GPIO_4 (LP_WKUP1)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (nERR_MCU)
GPIO_8 (DISABLE_WDOG)
GPIO_9 (nSLEEP)
SoC MAIN CONTROLS
PMIC_WAKE0
GND
GPIO_10 (GPI)
MMC1 IO
DDR_RET
GPIO_11 (nRSTOUT_SoC)
ENABLE MCU I/O
RESETSTATz
TPS22965-Q1
LP8764-Q1
Board
Warm Reset
INTn
SCL_I2C1
SDA_I2C1
Disable Watchdog
CAN Wakeup
Enable DDR I/O (Optional)
GPIO_1 (GPO)
GPIO_2 (GPO)
TPS6594-Q1, BUCK4
D
GPIO_3 (GPO)
PMIC VOLTAGE DOMAINS
SET
CLR
GPIO_4 (ENABLE)
GPIO_5 (GPO)
VRTC – 1.8V
VINT – 1.8V
GPIO_6 (GPO)
VIO – 1.8V or 3.3V
GPIO_7 (GPO)
GPIO_8 (SCLK_SPMI)
GPIO_9 (SDATA_SPMI)
GPIO_10 (GPO)
PDN OPTIONS
MCU-only
DDR Retention
GPIO Retention
TPS22966-Q1
ON1
ENABLE MAIN I/O
ENABLE DDR RET
ON2
ENABLE USB
TLV70033-Q1
ENABLE
EFUSE
TLV70018-Q1
ENABLE
3.3V SD
TLV7103318-Q1
EN1
ENABLE 1.8V SD
EN2
图9-1. TPS6594-Q1 and LP8764-Q1 Digital Connections
Copyright © 2023 Texas Instruments Incorporated
234 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
TYPES
表9-1. Combined MCU and Main Voltage Domain Power Rail Mapping
VOLTAGE [V]
DOMAIN NAMES
DOMAIN TYPES
POWER RAILS
#
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU,
VDDSHVn_MCU,VDDSH
Vn, VDDA_3P3_USB(1)
Digital IO
Digital IO
3.3
VDD_IO_3V3
1
2
VDDSHV0, VDDSHV2,
VDDSHV5(3) (1)
) ,
VDDA_3P3_USB(4)
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU,
VDDSHVn_MCU3
1.8
VDD_IO_1V8
(3)
VDDSHV0, VDDSHV2,
VDDSHVn(2)
,
VDDSHV5(3) (2)
,
)
VDDS_MMC0
(VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
VDDA_ADC_MCU,
VDDA_POR_WKUP,
VDDA_WKUP,
VDDA_1P8_<clk/
meas>(5)
(7)
Analog PHY
1.8
VDA_LN_1V8(6)
,
3
VDDA_1P8_<phy>(6)
VDDA_OSC1,
VDDA_PLLGRP8,6,4,0,
VDDA_TEMP1:0)(5)
VDDA_1P8_USB,
,
VDDA_1P8_SERDES)(6)
(VDDA_0P8_PLL_DDR,
VDDA_0P8_DLL_MMC0
Analog, low
voltage
0.80
VDDA_0P8_DPLL
VDD_CPU
VDA_DPLL_0V8
VDD_CPU_AVS
4
5
(7)
)
Digital, AVS low
voltage
VDD_CPU
0.77 –0.84
VDD_MCU9,
VDD_MCU
VDD_CORE
VDD_MCU_WAKE1,VD
D_CORE,VDD_WAKE0,
(VDDA_0P8_SERDES,
VDDA_0P8_USB)
Digital, low
voltage
0.80
VDD_CORE_0V8
6
VDDA_0P8_<phy>
Digital, low
voltage
VDDAR_MCU,VDDAR_
CORE, VDDAR_CPU
0.85
1.1
VDDAR
VDD_RAM_0V85
VDD_DDR_1V1
7
8
VDDS_DDR_BIAS,
VDDS_DDR,
VDDS_DDR_C
Digital, low
voltage
VDDS_DDR
(1) Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces
(2) Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces
(3) VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required for compliant, high-speed
SD card operations. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then domain can be
grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO
1.8V power rail.
(4) VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,
then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter.
(5) VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
(6) VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-
line supply filter is allowed.
(7) VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It
is not recommended to combine these domains with any other 0.8V domains since high frequency switching noise could negatively
impact jitter performance of PLL and DLL signals.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 235
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
表9-2. Independent MCU and Main Voltage Domain Power Rail Mapping
TYPES
VOLTAGE [V]
DOMAIN NAMES
DOMAIN GROUPS
POWER RAILS
#
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU)1
Digital IO
3.3
VDDSHVn_MCU
VDD_MCUIO_3V3
1
2
3
4
(VDDSHV0, VDDSHV2,
VDDSHV53)2,
VDDA_3P3_USB4
VDDSHVn,
VDDA_3P3_USB11
Digital IO
Digital IO
Digital IO
3.3
1.8
1.8
VDD_IO_3V3
VDD_MCUIO_1V8
VDD_IO_1V8
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU)2
VDDSHVn_MCU2
VDDSHVn2 3
(VDDSHV0, VDDSHV2,
VDDSHV53)2,
VDDS_MMC0
(VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
VDDA_ADC_MCU,
VDDA_POR_WKUP,
VDDA_WKUP)2
VDDA_MCU1P8_<clk/
meas>
Analog Clk, Meas
1.8
VDA_MCU_1V8
5
VDDA_OSC1,
Analog Clk, Meas
Analog PHY
1.8
1.8
VDDA_PLLGRP8,6,4,0, VDDA_1P8_<clk/meas>
VDDA_TEMP1:0
VDA_PLL_1V8
6
7
8
(VDDA_1P8_USB,
VDDA_1P8_<phy>6
VDDA_1P8_SERDES)6
VDA_PHY_1V87
(VDDA_0P8_PLL_DDR,
Analog, low
voltage
0.80
0.85
VDDA_0P8_DLL_MMC0
)7
VDDA_0P8_DPLL
VDA_DLL_0V8
VDD_MCU_0V8
Digital, low
voltage
VDD_MCU8,
VDD_MCU_WAKE1,
VDDAR_MCU
VDD_MCU
VDDAR_MCU
Digital, AVS low
voltage
VDD_CPU
VDD_CPU
VDD_CPU_AVS
VDD_CORE_0V8
9
0.77 –0.84
Digital, low
voltage
0.80
VDD_CORE,VDD_WAK
E0,
VDD_CORE
VDDA_0P8_<phy>
10
(VDDA_0P8_SERDES,
VDDA_0P8_USB)
Digital, low
voltage
0.85
1.1
VDDAR_CORE,
VDDAR_CPU
VDDAR
VDD_RAM_0V85
VDD_DDR_1V1
11
12
Digital, low
voltage
VDDS_DDR_BIAS,
VDDS_DDR,
VDDS_DDR
VDDS_DDR_C
1. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
2. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces
3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required
for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed
3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB
interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO
power rail either directly or through a supply filter.
5. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine digital
VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
236 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy> domains should be
avoided but if grouped, then in-line ferrite bead supply filtering is required.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply
for optimal performance. It is not recommended to combine these domains with any other 0.8V domains
since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
8. VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either
0.8V VDD_CORE or 0.85V RAM array (VDDAR_xxx) domains.
9.2 Device Connection and Layout Fundamentals
9.2.1 Power Supply Decoupling and Bulk Capacitors
9.2.1.1 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that
follow the board design guidelines contained in the application report.
9.2.2 External Oscillator
For more information about External Oscillators, see 节7.9.4, Clock Specifications
9.2.3 JTAG and EMU
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual
9.2.4 Reset
The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and
two reset status pins (MCU_RESETSTATz and RESETSTATz). These pins can be driven by an external power
good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz pins should be held active low
during the entire power-up phase, and until all power supplies as well as the HFOSC0 clock are stable.
All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main
domain (MCU domain is reset isolated from all Main domain resets).
9.2.5 Unused Pins
For more information about Unused Pins, see 节6.5, Connections for Unused Pins
9.2.6 Hardware Design Guide for JacintoTM 7 Devices
The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design
considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid during
the development of application hardware.
9.3 Peripheral- and Interface-Specific Design Information
9.3.1 LPDDR4 Board Design and Layout Guidelines
The goal of the Jacinto 7 DDR Board Design and Layout Guidelines is to make the LPDDR4 system
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.
TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 237
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
9.3.2 OSPI and QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the OSPI and QSPI
interfaces.
9.3.2.1 No Loopback and Internal Pad Loopback
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm
as stripline or ~8cm as microstrip)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-2
• Propagation delays and matching:
– A to B < 450 ps
– Matching skew: < 60 ps
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
MCU_OSPI[x]_CLK
MCU_OSPI[x]_LBCLKO
OSPI Device DQS
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
MCU_OSPI_Board_01
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
图9-2. OSPI Interface High Level Schematic
9.3.2.2 External Board Loopback
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
Copyright © 2023 Texas Instruments Incorporated
238 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must
be approximately equal to the signal propagation delay of the control and data signals between the flash
device and the SoC device (E to F, or F to E)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-3
• Propagation delays and matching:
– A to B = E to F = (C to D) / 2
– Matching skew: < 60 ps
备注
The OSPI Board Loopback Hold time requirement (described in 节 7.9.5.18, OSPI) is larger than the
Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin to
the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
MCU_OSPI[x]_CLK
C
R1
0 Ω*
MCU_OSPI[x]_LBCLKO
D
OSPI Device DQS
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
MCU_OSPI_Board_02
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine
tuning, if needed.
图9-3. OSPI Interface High Level Schematic
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 239
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
9.3.2.3 DQS (only available in Octal Flash devices)
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS
output pin (C to D)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-4
• Propagation delays and matching:
– A to B = C to D
– Matching skew: < 60 ps
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
D
OSPI device DQS
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
J7ES_OSPI_Board_03
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
图9-4. OSPI Interface High Level Schematic
9.3.3 USB VBUS Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the
图 9-5), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these external
resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be less than
100 nA.(1)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
240 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
Device
USBn_VBUS
16.5 kΩ
1%
3.5 kΩ
1%
VBUS signal
10 kΩ
1%
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
图9-5. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in 图 9-5 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
9.3.4 System Power Supply Monitor Design Guidelines
The VMON1_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is
typically a single pre-regulated power source for the entire system. This supply is monitored by comparing the
output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with a
power fail event being triggered when the voltage applied to VMON1_ER_VSYS drops below the internal
reference voltage. The actual system power supply voltage trip point is determined by the system designer when
selecting component values used to implement the external resistor voltage divider circuit. When designing the
resistor divider circuit it is important to understand various factors which contribute to variability in the system
power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON1_ER_VSYS input
threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar
thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability
contributed by resistor value tolerances. Input leakage current associated with VMON1_ER_VSYS must also be
considered since any current flowing into the pin creates a loading error on the voltage divider output. The
VMON1_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V.
备注
The resistor voltage divider shall be designed such that its output voltage never exceeds themaximum
value defined in 节7.3, Recommended Operating Conditions during normal operating conditions.
图9-6 presents an example, where the system power supply is nominally 5 V and the maximum trigger threshold
is 5 V - 10%, or 4.5 V.
For this example, it is important to understand which variables effect the maximum trigger threshold when
selecting resistor values. It is obvious a device which has a VMON1_ER_VSYS input threshold of 0.45 V + 3%
needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops
10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions
effect the maximum trigger point may not be obvious. When selecting component values which produce a
maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and
the value of R2 is 1% high combined with a condition where input leakage current for the VMON1_ER_VSYS pin
is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a
maximum trigger threshold of 4.523 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 241
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.008 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.
Approximately 250 mV of this range is introduced by VMON1_ER_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this
range is introduced by loading error when VMON1_ER_VSYS input leakage current is 2.5 μA.
The resistor values selected in this example produces approximately 100 μA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor
divider bias current vs loading error is something the system designer needs to consider when selecting
component values.
The system designer should also consider implementing a noise filter on the voltage divider output since
VMON1_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done
by installing a capacitor across R1 as shown in 图 9-6. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
图 9-6 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger
threshold is -10% or 4.5 V.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ 1%
C1
Value = Determined by system designer
(System Power Supply)
4.81 kΩ
1%
R1
VSS
SPRSP56_VMON_ER_MON_01
图9-6. System Supply Monitor Voltage Divider Circuit
The VMON2_IR_VCPU pin provides a way to monitor VDD_CPU power supply. Must be externally connected as
close as possible to VDD_CPU pin on the board.
The VMON3_IR_VEXT1P8 and VMON4_IR_VEXT1P8 pins provide a way to monitor an external 1.8V power
supply. The VMON5_IR_VEXT3P3 pin provides a way to monitor an external 3.3V power supply. An internal
resistor divider with software control is implemented inside the SoC. Software can program the internal resistor
divider to create appropriate under voltage and over voltage interrupts. These pins should not be sourced from
an external resistor divider. If the monitored voltage requires adjustment, be sure to buffer the divided voltage
prior connecting to monitor pin.
9.3.5 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application
report.
9.3.6 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
Copyright © 2023 Texas Instruments Incorporated
242 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application report.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 243
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
10 Device and Documentation Support
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, DRA821). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of DRA821 devices in the ALM package type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
244 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
10.1.1 Standard Package Symbolization
备注
Some devices can have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices can also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
xBBBBBBBBzYrPPPcQ1
PIN ONE INDICATOR
XXXXXXX
G1
ZZZ
YYY
O
J7ES_SPRSP28_PACK_01
图10-1. Printed Device Reference
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 245
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
10.1.2 Device Naming Convention
表10-1. Nomenclature Description
VALUE
FIELD
PARAMETER
FIELD
DESCRIPTION
DESCRIPTION
MARKING
ORDERABLE
X
P
Prototype
Device Evolution
Stage
x(1)
Preproduction (production test flow, no reliability data)
Production
BLANK
BBBBBBBB(3)
Base Production
Part Number
J7200
DRA821U4
See 表5-1, Device Comparison
DRA821U2
T
L
See 表7-1, Speed Grade Maximum Frequency
z
Device Speed
E
C
OTHER
Alternate speed grade
G
C
0
General purpose
General purpose, R5F Lockstep capable
High Security capable
5
High Security capable, R5F Lockstep capable
High Security Prime(4) capable, R5F Lockstep capable
Y
Device Type(4)
R
High Security capable, R5F Lockstep capable, Customer Dev
Keys (Preview)(5)
D
P
High Security Prime(4) capable, R5F Lockstep capable,
Customer Dev Keys (Preview)(5)
r
Device Revision
A or BLANK
SR 1.0
B
SR 2.0
PPP
c
Package Designator
Carrier Designator
Carrier Designator
ALM
ALM FCBGA-N433 (17.2 mm × 17.2 mm) Package
N/A
N/A
BLANK
Tray
R
Tape and Reel
Not automotive qualified.
Supports TJ = –40 °C to 105 °C
BLANK
Automotive
Designator
Q1(2)
Meets AEC-Q100 qualification requirements, with exceptions as
specified in this document (data sheet)
Q1
Supports TJ = –40 °C to 125 °C
XXXXXXX
YYY
ZZZ
Lot Trace Code
Production Code
Production Code
Pin one
As Marked
As Marked
As Marked
As Marked
As Marked
N/A
N/A
N/A
N/A
N/A
Lot Trace Code (LTC)
Production Code; For TI use only
Production Code; For TI use only
Pin one designator
O
G1
ECAT
ECAT—Green package designato
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
(3) XJ7200GALM base part number with X speed grade indicator is the part number for the superset device. Software should constrain
the features and speed used to match the intended production device.
(4) For High Security (HS) device support, TI recommends the 0, 5 or D device types. The R and P (High Security Prime) device types are
not recommended for most applications, as extra steps are required in the manufacturing process and, therefore, these device types
are offered at a higher price point.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
246 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
(5) Only available on preproduction J7200 devices. (Advance Information/Preview)
备注
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 247
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
10.2 Tools and Software
The following products support development for DRA821 platforms:
Development Tools
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step
of the application development flow. Familiar tools and interfaces allow users to get started faster than ever
before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for
embedded developers.
SYSCONFIG Tool System Configuration Tool: To help simplify configuration challenges and accelerate software
development, TI created SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring
pins, peripherals, radios, subsystems, and other components. SysConfig helps you manage, expose, and
resolve conflicts visually so that you have more time to create differentiated applications. The SysConfig tool is
integrated in Code Composer Studio™ (CCS) IDE, as a standalone installer, or can be used via the dev.ti.com
cloud tools portal.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
248 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
10.3 Documentation Support
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
The following documents describe the DRA821 devices.
Technical Reference Manual
J7200 DRA821 Processor Silicon Revision 1.0 Texas Instruments Families of Products Technical
Reference Manual Details the integration, the environment, the functional description, and the programming
models for each peripheral and subsystem in the DRA821 family of devices.
Errata
J7200 DRA821 Processor Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the
functional specifications for the device.
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
I2C™ is a trademark of NXP Semiconductors.
eMMC™ is a trademark of MultiMediaCard Association.
Xccela™ is a trademark of Micron Technology, Ink.
HyperBus™ is a trademark of Mobiveil Inc.
Jacinto™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
PCI-Express® is a registered trademark of PCI-SIG.
I3C® is a registered trademark of MIPI Alliance, Inc.
安全数字® is a registered trademark of SD Card Association.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 249
Product Folder Links: DRA821U-Q1 DRA821U
English Data Sheet: SPRSP57
DRA821U-Q1, DRA821U
ZHCSKS2E –APRIL 2020 –REVISED JUNE 2023
www.ti.com.cn
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP57
250 Submit Document Feedback
Product Folder Links: DRA821U-Q1 DRA821U
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2023
PACKAGING INFORMATION
Orderable Device
DRA821U4TCBALMQ1
DRA821U4TCBALMRQ1
DRA821U4TGBALM
DRA821U4TGBALMR
XDRA821UXXGALM
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
ALM
433
433
433
433
433
84
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
TBD
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
DRA821U4TCBALMQ1
Samples
Samples
Samples
Samples
Samples
357
357 G1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ALM
ALM
ALM
ALM
500
84
Call TI
Call TI
Call TI
Call TI
DRA821U4TCBALMQ1
357
357 G1
DRA821U4TGBALM
357
357 G1
500
84
DRA821U4TGBALM
357
357 G1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRA821U, DRA821U-Q1 :
Catalog : DRA821U
•
Automotive : DRA821U-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRA821U4TGBALMR
FCBGA
ALM
433
500
330.0
32.4
17.6
17.6
3.74
24.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
FCBGA ALM 433
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
DRA821U4TGBALMR
500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DRA821U4TCBALMQ1
DRA821U4TGBALM
ALM
ALM
FCBGA
FCBGA
433
433
84
84
6 X 14
6 X 14
150
150
315 135.9 7620
315 135.9 7620
22
22
14.5 14.45
14.5 14.45
Pack Materials-Page 3
PACKAGE OUTLINE
ALM0433A
FCBGA - 2.57 mm max height
SCALE 0.900
BALL GRID ARRAY
17.3
17.1
A
B
BALL A1 CORNER
PIN 1 ID
(OPTIONAL)
17.3
17.1
(
12.8)
0.1 C
(
11)
16.8)
(
(1.45)
2.57
2.29
0.2 C
C
SEATING PLANE
0.15 C
(0.577)
0.5
TYP
0.3
16 TYP
SYMM
(0.6) TYP
(0.6) TYP
0.8 TYP
AA
Y
W
V
U
T
R
P
N
M
L
SYMM
16
K
J
TYP
H
G
F
E
D
C
B
A
0.55
0.45
C A B
433X
0.25
0.1
1
2
3
4
5
6 7 8 9 10 12 14 16 18 20
11 13 15 17 19 21
C
0.8 TYP
4225658/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ALM0433A
FCBGA - 2.57 mm max height
BALL GRID ARRAY
(0.8) TYP
433X ( 0.4)
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SNOWN
SCALE:6X
0.07 MAX
0.07 MIN
METAL UNDER
SOLDER MASK
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225658/A 01/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ALM0433A
FCBGA - 2.57 mm max height
BALL GRID ARRAY
(0.8) TYP
433X 0.4
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 6X
4225658/A 01/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DRA821U4TCBALMQ1
具有双核 Arm® Cortex®-A72、四核 Cortex-R5F、四端口以太网交换机、PCIe 的汽车网关 SoC | ALM | 433 | -40 to 125
TI
DRA821U4TCBALMRQ1
具有双核 Arm® Cortex®-A72、四核 Cortex-R5F、四端口以太网交换机、PCIe 的汽车网关 SoC | ALM | 433 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明