DRV102_15 [TI]
PWM SOLENOID/VALVE DRIVER;
| 型号： | DRV102_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PWM SOLENOID/VALVE DRIVER 驱动 |
| 文件： | 总27页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV102
DR
V102
D
RV
102
SBVS009B – JANUARY 1998 – REVISED MAY 2009
www.ti.com
PWM SOLENOID/VALVE DRIVER
APPLICATIONS
FEATURES
● ELECTROMECHANICAL DRIVERS:
● HIGH OUTPUT DRIVE: 2.7A
Solenoids
Actuators
Valves
Positioners
High Power Relays/Contactors
Clutches/Brakes
● WIDE SUPPLY RANGE: +8V to +60V
● COMPLETE FUNCTION
PWM Output
● SOLENOID OVERHEAT PROTECTORS
● FLUID AND GAS FLOW CONTROLLERS
● PART HANDLERS
Internal 24kHz Oscillator
Digital Control Input
Adjustable Delay and Duty Cycle
Over/Under Current Indicator
● ELECTRICAL HEATERS/COOLERS
● MOTOR SPEED CONTROLLERS
● INDUSTRIAL CONTROL
● FULLY PROTECTED
Thermal Shutdown with Indicator
Internal Current Limit
● FACTORY AUTOMATION
● POWER PACKAGES: 7-Lead TO-220 and
7-Lead Surface-Mount DDPAK
● MEDICAL ANALYSIS
● PHOTOGRAPHIC PROCESSING
The DRV102 can be set to provide a strong initial
closure, automatically switching to a soft hold mode for
power savings. Duty cycle can be controlled by a
resistor, analog voltage, or digital-to-analog converter
for versatility. A flag output indicates thermal shutdown
and over/under current limit. A wide supply range
allows use with a variety of actuators.
DESCRIPTION
The DRV102 is a high-side power switch employing a
pulse-width modulated (PWM) output. Its rugged de-
sign is optimized for driving electromechanical devices
such as valves, solenoids, relays, actuators, and
positioners. The DRV102 is also ideal for driving
thermal devices such as heaters and lamps. PWM
operation conserves power and reduces heat rise in
the device, resulting in higher reliability. In addition,
adjustable PWM allows fine control of the power
delivered to the load. Time from dc output to PWM
output is externally adjustable.
The DRV102 is available in a 7-lead staggered TO-220
package and a 7-lead surface-mount DDPAK plastic
power package. It operates from –55°C to +125°C.
Flag
7
DRV102
Thermal Shutdown
Over/Under Current
5
(+8V to +60V)
VS
24kHz
Oscillator
Input
(TTL-Compatible)
1
PWM
On
6
Delay
Off
Out
Gnd(1)
4
Load
2
3
Delay
Adjust
Duty Cycle
Adjust
(Gnd electrically
connected to tab)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2009, Texas Instruments Incorporated
www.ti.com
SPECIFICATIONS
At TC = +25°C, VS = +24V, load = series diode MUR415 and 100Ω, and 4.99kΩ Flag pull-up to +5V, unless otherwise noted.
DRV102T, F
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT
Output Saturation Voltage, Source
IO = 1A
+1.7
+1.3
2.7
+2.2
+1.7
3.4
V
V
IO = 0.1A
Current Limit
2
A
Under-Scale Current
Leakage Current
16
mA
mA
Output Transistor Off, VS = +60V, VO = 0V
±0.01
±2
DIGITAL CONTROL INPUT(1)
VCTR Low (output disabled)
VCTR High (output enabled)
ICTR Low (output disabled)
ICTR High (output enabled)
Propagation Delay: On-to-Off
Off-to-On
0
+1.2
VS
V
+2.2
V
VCTR = 0V
–80(2)
20(2)
0.9
µA
µA
µs
µs
VCTR = +5V
1.8
DELAY TO PWM(3)
dc to PWM Mode
Delay Equation(4)
Delay to PWM ≈ CD • 106 (CD in F)
s
Delay Time
Minimum Delay Time(5)
CD = 0.1µF
CD = 0
80
97
15
110
ms
µs
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity(6)
10 to 90
%
%
49% Duty Cycle, RPWM = 25.5kΩ
49% Duty Cycle, VS = 8V to 60V
20% to 80% Duty Cycle
±1
±1
±2
±7
±5
%
% FSR
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
Oscillator Frequency
VO = 10% to 90% of VS
VO = 90% to 10% of VS
0.25
0.25
24
2.5
2.5
29
µs
µs
19
+4
kHz
FLAG
Normal Operation
Fault(7)
20kΩ Pull-Up to +5V, IO < 1.5A
Sinking 1mA
+4.9
+0.2
2
V
V
+0.4
Sink Current
Under-Current Flag: Set
Reset
VFLAG = 0.4V
mA
µs
µs
µs
µs
5.2
11
Over-Current Flag: Set
Reset
5.2
11.5
THERMAL SHUTDOWN
Junction Temperature
Shutdown
+165
+150
°C
°C
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
+24
6.5
V
V
+8
+60
9
IO = 0
mA
TEMPERATURE RANGE
Specified Range
–55
–55
+125
+125
°C
°C
Storage Range
Thermal Resistance, θJC
7-Lead DDPAK, 7-Lead TO-220
Thermal Resistance, θJA
7-Lead DDPAK, 7-Lead TO-220
3
°C/W
°C/W
No Heat Sink
65
NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-width
modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay.
(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature,
over-current, or under-current conditions.
DRV102
2
SBVS009B
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ABSOLUTE MAXIMUM RATINGS(1)
CONNECTION DIAGRAMS
Supply Voltage, VS .............................................................................. 60V
Input Voltage .......................................................................... –0.2V to VS
PWM Adjust Input ................................................ –0.2V to VS (24V max)
Delay Adjust Input ................................................ –0.2V to VS (24V max)
Operating Temperature Range ......................................–55°C to +125°C
Storage Temperature Range .........................................–55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s)(2) ........................................... +300°C
Top Front View
TO-220, DDPAK
7-Lead
Stagger-Formed
TO-220
7-Lead
DDPAK
Surface-Mount
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) Vapor-phase or IR reflow techniques are recom-
mended for soldering the DRV102F surface-mount package. Wave soldering
is not recommended due to excessive thermal shock and “shadowing” of
nearby devices.
ELECTROSTATIC
1
2
3
4
1 2 3 4
5
5
6
7
6
7
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
In PWM
Delay
VS
Flag
Gnd Out
In
Delay
VS
Gnd Out
PWM
Flag
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
NOTE: Tabs are electrically connected to ground (pin 4).
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.
DRV102
SBVS009B
3
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PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
Pin 1
Input
The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above
the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises
to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be driven to the power supply (VS)
without damage.
Pin 2
Pin 3
Pin 4
Delay Adjust
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less
than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator.
When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),
so the first pulse may be extended by any portion of the programmed duty cycle.
Duty Cycle Adjust
(PWM)
Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source
from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,
or output of a D/A converter. The active voltage range is from 0.55V to 3.7V to facilitate the use of single-supply control
electronics. At 0.56V (or RPWM = 4.4kΩ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM
frequency is a constant 24kHz.
Ground
This pin is electrically connected to the package tab. It must be connected to system ground for the DRV102 to function. It
carries the 6.5mA quiescent current.
Pin 5
Pin 6
VS
This is the power supply pin. Operating range is +8V to +60V.
Out
The output is the emitter of a power npn with the collector connected to VS. Low power dissipation in the DRV102 is obtained
by low saturation voltage and fast switching transitions. Rise time is less than 250ns, fall time depends on load impedance.
A flyback diode is (D1) needed with inductive loads to conduct the load current during the off cycle. The external diode should
be selected for low forward voltage. The internal clamp diode provides protection but should not be used to conduct load
currents. An additional diode (D2), located in series with Out pin, is required for inductive loads.
Pin 7
Flag
Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under-
current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal
shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output
requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.
LOGIC BLOCK DIAGRAM
Flag
7
DRV102
Over/Under Current
5
Thermal
Shutdown
(+8V to +60V)
VS
1
PWM
Input
On
Off
(2)
6
Delay
Out
D2
Load
(1)
D1
Gnd
4
2
3
RPWM
CD
NOTES: (1) Schottky Power Rectifier for low
power dissipation. (2) Schottky or appropriately
rated silicon diode.
DRV102
4
SBVS009B
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TYPICAL PERFORMANCE CURVES
At TC = +25°C and VS = +24V, unless otherwise noted.
DUTY CYCLE vs TEMPERATURE
DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE
54
53
52
51
50
49
48
90
80
70
60
50
40
30
20
10
8
RPWM = 25.5kΩ
6
Duty Cycle
VS = +8V
4
IO = 0.1A
2
Error
VS = +24V
0
–2
–4
–6
–8
IO = 1A
IO = 0.1A to 1A
VS = +60V
–75
–75
–75
–50
–25
0
25
50
75
100
125
125
125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Temperature (°C)
V
PWM (V)
CURRENT LIMIT vs TEMPERATURE
OUTPUT SATURATION VOLTAGE vs TEMPERATURE
3.25
3
2.25
2
VS = +8V, Load = 1Ω
I
= 2A
O
I
= 1.5A
O
1.75
1.5
1.25
1
VS = +60V, Load = 5Ω
2.75
2.5
2.25
2
I
= 1A
O
I
= 0.1A
O
VS = +24V, Load = 5Ω
0.75
–50
–25
0
25
50
75
100
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT vs TEMPERATURE
UNDER-SCALE CURRENT vs TEMPERATURE
VS = +8V to +60V
20
18
16
14
12
10
8
7.5
7
VS = +60V
VS = +24V
6.5
6
VS = +8V
5.5
–75
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
DRV102
SBVS009B
5
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TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.
FLAG OPERATION
OVER-CURRENT LIMIT
FLAG OPERATION
UNDER-CURRENT
(VS = +60V, CD = 220pF, RPWM = 25.5kΩ, Load = 350mH || 47Ω)
(VS = +60V, CD = 120pF, RPWM = 25.5kΩ, No Load)
Onset of current limit where
V
OUT begins to drop
60V
40V
20V
60V
40V
20V
Flag only on during constant output
or “ON” portion of PWM mode
0
0
Flag only set during
constant output mode
or “ON” portion of
PWM mode
4V
4V
2V
0
2V
0
Constant Output
PWM Mode
50µs/div
50µs/div
DC TO PWM MODE
DRIVING INDUCTIVE LOAD
(VS = +60V, CD = 120pF, RPWM = 30.1kΩ, Load = 350mH)
TYPICAL SOLENOID CURRENT WAVEFORM
(VS = +60V, CD = 0.1µF, RPWM = 30.1kΩ, Load = 350mH)
4V
0
60V
40V
20V
Solenoid
Motion
Period
0
1A
1A
0.5A
0
PWM Mode
0.5A
0
Solenoid Closure
Inductive load ramp current
25ms/div
50µs/div
CURRENT LIMIT REPSONSE
(Load = 1Ω, 2kΩ pull-up to +5V on Flag pin)
OSCILLATOR FREQUENCY vs TEMPERATURE
24.2
24.0
23.8
23.6
23.4
5V
2.5V
0
VS = +8V
3A
2A
1A
0
VS = +60V
–75 –55 –35 –15
5
25
45
65
85 105 125
10µs/div
Temperature (°C)
DRV102
6
SBVS009B
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TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.
NOMINAL DELAY TIME TO PWM vs TEMPERATURE
OUTPUT LEAKAGE CURRENT vs TEMPERATURE
Output Transistor Off
103
101
99
–200
–175
–150
–125
–100
–75
CD = 0.1µF
VS = +8V
V
O = 0V
VS = +24V
97
VS = +60V
95
VS = +24V
VS = +60V
93
VS = +8V
45 65 85 105 125
91
–75
–50
–25
0
25
50
75
100
125
–75 –55 –35 –15
5
25
Temperature (°C)
Temperature (°C)
DELAY TIME TO PWM
CURRENT LIMIT
PRODUCTION DISTRIBUTION
PRODUCTION DISTRIBUTION
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
Typical distribution
of packaged units.
DRV102F and
Typical distribution
of packaged units.
DRV102F and
CD = 0.1µF
DRV102T included.
DRV102T included.
0
80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110
Delay Time to PWM (ms)
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
Current Limit (A)
DUTY CYCLE ACCURACY
PRODUCTION DISTRIBUTION
30
25
20
15
10
5
Nominal Duty Cycle = 49%
Typical distribution
of packaged units.
DRV102F and
RPWM = 25.5kΩ
DRV102T included.
0
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
Duty Cycle Accuracy (%)
DRV102
SBVS009B
7
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pin connected to 0.1µF and duty cycle set for 25%. See the
“Delay Adjust” and “Duty Cycle Adjust” text for equations
and further explanation.
BASIC OPERATION
The DRV102 is a high-side, bipolar power switch employ-
ing a pulse-width modulated (PWM) output for driving
electromechanical and thermal devices. Its design is opti-
mized for two types of applications: a two-state driver
(open/close) for loads such as solenoids and actuators, and
a linear driver for valves, positioners, heaters, and lamps. Its
wide supply range, adjustable delay to PWM mode, and
adjustable duty cycle make it suitable for a wide range of
applications. Figure 1 shows the basic circuit connections to
operate the DRV102. A 0.1µF bypass capacitor is shown
connected to the power supply pin.
Ground (pin 4) is electrically connected to the package tab.
This pin must be connected to system ground for the
DRV102 to function. This serves as the DRV102 reference
ground.
The load (solenoid, valve, etc.) is connected between the
output (pin 6) and ground. For an inductive load, an external
flyback diode (D1 in Figure 1a) across the output is required.
The diode serves to maintain the hold force during PWM
operation. Depending on the application, the flyback diode
should be placed near the DRV102 or close to the solenoid
(see “Flyback Diode” text). The device’s internal clamp
diode, connected between the output and ground, should not
be used to carry load current. When driving inductive loads,
an additional diode in series with the out pin, D2, is required
(see “Series Diode” text).
The Input (pin 1) is compatible with standard TTL levels.
Input voltages between +2.2V and +5.5V turn the device
output on, while pulling the pin low (0V to +1.2V), shuts the
DRV102 output off. Input current is typically 80µA.
Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allow
external adjustment of the PWM output signal. The Delay
Adjust pin can be left floating for minimum delay to PWM
mode (typically 15µs) or a capacitor can be used to set the
delay time. Duty cycle of the PWM output can be controlled
by a resistor, analog voltage, or D/A converter. Figure 1b
provides an example timing diagram with the Delay Adjust
The Flag (pin 7) provides fault status for under-current,
over-current, and thermal shutdown conditions. This pin is
active low with pin voltage typically +0.2V during a fault
condition. A small value capacitor may be needed between
Flag and ground for noisy applications.
1a). Basic Circuit Connections
Flag
7
VS
(+8V to +60V)
DRV102
Thermal Shutdown
Over/Under Current
0.1µF
5
24kHz
Oscillator
VS
1
PWM
D2
Input
(TTL-Compatible)
6
Delay
2
Out
On
(1)
Load
D1
Off
3
Gnd
4
(Gnd electrically
connected to tab)
Duty
Cycle
Adjust
Delay
Adjust
CD
RPWM
NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle.
Flyback diode shown near DRV102. For some applications with remotely located load, it may be desirable
to place the diode near the solenoid—see “Flyback Diode” text. Motorola MSRS1100T3 (1A, 100V) or
MBRS360T3 (3A, 60V).
1b). Simplified Timing Diagram
CD = 0.1µF (92ms constant dc output before PWM)
RPWM = 90.9kΩ
+2.2V to +5.5V
0V to +1.2V
VS
• • •
INPUT
OUTPUT
CD = 0.1µF
92ms
• • •
0
tON
RPWM = 90.9kΩ
t
t
ON ≈ 10.4µs
tP
P ≈ 41.6µs (1/24kHz)
tON
tP
Duty Cycle =
= 25%
Initial dc Output
PWM Mode
(set by value (resistor or voltage
of CD controlled)
)
FIGURE 1. Basic Circuit Connections and Timing Diagram.
DRV102
8
SBVS009B
www.ti.com
vidual situations may defy logic; if one location seems to
create noise problems, try the other.
APPLICATIONS INFORMATION
POWER SUPPLY
The DRV102 operates from a single +8V to +60V supply
with excellent performance. Most behavior remains un-
changed throughout the full operating voltage range. Param-
eters which vary significantly with operating voltage are
shown in the Typical Performance Curves.
SERIES DIODE FOR INDUCTIVE LOADS
An additional bias diode, located in series with the output, is
required when driving inductive loads. Any silicon diode,
such as the 1N4002, appropriately rated for current will
work. The diode biases the emitter of the internal power
device such that it can be fully shut off during the “off”
portion of the PWM cycle. Note that the voltage at the load
drops below ground due to the flyback diode. If it is not used,
apparent leakage current can rise to hundreds of milliamps,
resulting in unpredictable operation and thermal shutdown.
CONNECTIONS TO LOAD
The PWM switching voltage and currents can cause electro-
magnetic radiation. Proper physical layout of the load cur-
rent will help minimize radiation. Load current flows from
the DRV102 output terminal to the load and returns through
the ground return path. This current path forms a loop. To
minimize radiation, make the area of the enclosed loop as
small as possible. Twisted pair leading to the load is excel-
lent. If the ground return current must flow through a chassis
ground, route the output current line directly over the chassis
surface in the most direct path to the load.
ADJUSTABLE INITIAL 100% DUTY CYCLE
A unique feature of the DRV102 is its ability to provide an
initial constant dc output (100% duty cycle) and then switch
to PWM mode to save power. This function is particularly
useful when driving solenoids which have a much higher
pull-in current requirement than hold current requirement.
The duration of this constant dc output (before PWM output
begins) can be externally and independently controlled with
a capacitor connected from Delay Adjust (pin 2) to ground
according to the following equation:
FLYBACK DIODE LOCATION
Physical location of the flyback diode may affect electro-
magnetic radiation. With most solenoid loads, inductance is
large enough that load current is virtually constant during
PWM operation. When the switching transistor is off, load
current flows though the flyback diode. If the flyback diode
is located near the DRV102 (Figure 2a), the current flowing
in long lines to the load is virtually constant. If the flyback
diode is, instead, located directly across the load (Figure 2b),
pulses of current must flow from the DRV102 to the distant
load. While theory seems to favor placing the diode at the
DRV102 output (constant current in the long lines), indi-
Delay Time ≈ CD • 106
(time in seconds, CD in Farads)
Leaving the Delay Adjust pin open results in a constant
output time of approximately 15µs. The duration of this
initial output can be reduced to less than 3µs by connecting
the pin to 5V. Table I provides examples of desired “delay”
times (constant output before PWM mode) and the appropri-
ate capacitor values or pin connection.
CONSTANT OUTPUT DURATION
(Delay Time to PWM Mode)
2a) Flyback Diode Near DRV102
CD
3µs
15µs
97µs
0.97ms
97ms
Pin Connected to 5V
DRV102
5
Pin Open
100pF
1nF
VS
0.1µF
6
TABLE I. Delay Adjust Pin Connections.
Out
Load
4
The internal Delay Adjust circuitry is composed of a 3µA
current source and a 3V comparator as shown in Figure 3.
Thus, when the pin voltage is less than 3V, the output device
is 100% on (dc output mode).
2b) Flyback Diode Near Load
DRV102
DRV102
5
3V Reference
VS
VS
3µA
6
Out
Comparator
Load
4
2
CD
Delay Adjust
FIGURE 3. Simplified Circuit Model of the Delay Adjust Pin.
FIGURE 2. Location of External Flyback Diode.
DRV102
SBVS009B
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ADJUSTABLE DUTY CYCLE
Voltage-Controlled Duty Cycle
The DRV102’s externally adjustable duty cycle provides an
accurate means of controlling power delivered to the load.
Duty cycle can be set from 10% to 90% with an external
resistor, analog voltage, or the output of a D/A converter.
Reduced duty cycle results in reduced power dissipation.
This keeps the DRV102 and load cooler, resulting in in-
creased reliability for both devices. PWM frequency is a
constant 24kHz.
Duty cycle can also be programmed with an analog voltage,
VPWM. With VPWM ≈ 0.5V, duty cycle is 100%. Increasing
this voltage results in decreased duty cycles. For 0% duty
cycle, VPWM is approximately 4V. Table II provides VPWM
values for typical duty cycles. See the “Duty Cycle vs
Voltage” typical performance curve for additional duty cycle
values.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a 1kΩ series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 5) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
Resistor-Controlled Duty Cycle
Duty cycle is independently programmed with a resistor
(RPWM) connected between the Duty Cycle Adjust pin and
ground. Increased resistor values correspond to decreased
duty cycles. Table II provides resistor values for typical duty
cycles. Resistor values for additional duty cycles can be
obtained from Figure 4. For reference purposes, the equation
for calculating RPWM is included in Figure 4.
DRV102
5
VS
RESISTOR(1)
RPWM (kΩ)
VOLTAGE(2)
VPWM (V)
DUTY CYCLE
PWM
10
20
30
40
50
60
70
80
90
536
137
3.67
3.31
2.91
2.49
2.07
1.66
1.26
0.88
0.56
6
Out
66.5
39.2
24.9
16.2
10.5
6.65
4.42
3
Gnd 4
VPWM
D/A
Converter
(or analog
voltage)
1kΩ(1)
NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not
drive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typical
performance curve.
NOTE: (1) Required if voltage source can go below 0.1V.
TABLE II. Duty Cycle Adjust. TA= +25°C, VS = +24V.
FIGURE 5. Using a Voltage Source to Program Duty Cycle.
The DRV102’s internal 24kHz oscillator sets the PWM
period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200µA current
source and connects to the input of a comparator and a 19kΩ
resistor as shown in Figure 6. The DRV102’s PWM control
design is inherently monotonic. That is, a decreased voltage
(or resistor value) always produces an increased duty cycle.
1000
100
10
3.8V
f = 24kHz
1
0.7V
10
20
40
60
80 100
VS
Duty Cycle (%)
Comparator
200µA
RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]–1
where: a = –4.9686 x 10–8 d = –5.4837 x 10–10
b = –5.9717 x 10–8 e = 5.9361 x 10–12
c = 2.9889 x 10–8
19kΩ
DRV102
3
DC = duty cycle in %
Resistor or
Voltage Source(1)
For 50% duty cycle:
RPWM = [–4.9686 x 10–8 + (–5.9717 x 10–8) (50) + (2.9889 x 10–8) (50)2
+ (–5.4837 x 10–10) (50)3 + (5.9361 x 10–12) (50)4]–1
Duty Cycle
Adjust
NOTE: (1) Do not drive pin below 0.1V.
= 24.9kΩ
FIGURE 4. RPWM versus Duty Cycle.
FIGURE 6. Simplified Circuit Model of the Duty Cycle
Adjust Pin.
DRV102
10
SBVS009B
www.ti.com
STATUS FLAG
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a
fault condition, Flag output is driven low (pin voltage
typically drops to 0.2V). A pull-up resistor, as shown in
Figure 7, is required to interface with standard logic. A small
value capacitor may be needed between Flag and ground in
noisy applications.
+5V
5kΩ
(LED)
HLMP-Q156
Figure 7 gives an example of a non-latching fault monitoring
circuit, while Figure 8 provides a latching version. The Flag
pin can sink several milliamps, sufficient to drive external
logic circuitry or an LED (Figure 9) to indicate when a fault
has occurred. In addition, the Flag pin can be used to turn off
other DRV102’s in a system for chain fault protection.
Flag
7
Thermal Shutdown
Over/Under Current
5
VS
6
DRV102
Out
Gnd
4
+5V
5kΩ
TTL or HCT
Pull-Up
FIGURE 9. LED to Indicate Fault Condition.
Flag
7
Over/Under Current Fault
Thermal Shutdown
Over/Under Current
5
6
An over-current fault occurs when the output current ex-
ceeds the current limit. All units are guaranteed to drive 2A
without current limiting. Typically, units will limit at 2.7A.
The status flag is not latched. Since current during PWM
mode is switched on and off, the flag output will be modu-
lated with PWM timing (see flag waveforms in the Typical
Performance Curves).
VS
DRV102
Out
Gnd
4
An under-current fault occurs when the output current is
below the under-scale current threshold (typically 16mA).
For example, this function indicates when the load is discon-
nected. Again, the flag output is not latched, so an under-
current condition during PWM mode will produce a flag
output that is modulated by the PWM waveform. An initial,
brief under-current flag normally appears driving inductive
loads and may be avoided by adding a parallel resistor
sufficient to move the initial current above the under-current
threshold. Avoid adding capacitance to pin 6 (Out) as it may
cause momentary current limiting.
FIGURE 7. Non-Latching Fault Monitoring Circuit.
+5V
74XX76A
VS
Q
20kΩ
Flag
Flag
J
Q
Flag Reset
CLR
CLK
K
(1)
GND
Over-Temperature Fault
A thermal fault occurs when the die reaches approximately
165°C, producing a similar effect as pulling the input low.
Internal shutdown circuitry disables the output and resets the
Delay Adjust pin. The Flag is latched in the low state (fault
condition) until the die has cooled to approximately 150°C.
A thermal fault can occur in any mode of operation. Recov-
ery from thermal fault will start in delay mode (constant dc
output).
Flag
7
Thermal Shutdown
Over/Under Current
5
6
VS
DRV102
Out
Gnd
4
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
FIGURE 8. Latching Fault Monitoring Circuit.
DRV102
11
SBVS009B
www.ti.com
For best thermal performance, the tab of the DDPAK sur-
face-mount version should be soldered directly to a circuit
board copper area. Increasing the copper area improves heat
dissipation. Figure 12 shows typical thermal resistance from
junction-to-ambient as a function of the copper area.
PACKAGE MOUNTING
Figure 10 provides recommended PCB layouts for both the
TO-220 and DDPAK power packages. The tab of both
packages is electrically connected to ground (pin 4). It may
be desirable to isolate the tab of TO-220 package from its
mounting surface with a mica (or other film) insulator (see
Figure 11). For lowest overall thermal resistance, it is best to
isolate the entire heat sink/DRV102 structure from the
mounting surface rather than to use an insulator between the
semiconductor and heat sink.
POWER DISSIPATION
Power dissipation depends on power supply, signal, and load
conditions. Power dissipation is equal to the product of
(1)
7-Lead TO-220
KVT Package
7-Lead DDPAK
KTW Package
(2)
(2)
0.51
0.04
0.05
0.035
0.05
Mean dimensions given in inches. Refer to the end of
this data sheet for tolerances and detailed package
drawings. For further information on solder pads for
surface-mount devices, consult Application Bulletin
AB-132 (SBFA015), available for download at
www.ti.com.
0.105
NOTES:(1) For improved thermal performance increase footprint area.
See Figure 11, Thermal Resistance vs Circuit Board Copper Area.
(2) Refer to the mechanical drawings at the end of this document.
FIGURE 10. TO-220 and DDPAK Solder Footprints.
THERMAL RESISTANCE
vs ALUMINUM PLATE AREA
18
Aluminum Plate Area
Vertically Mounted
Flat, Rectangular
Aluminum Plate
in Free Air
16
θ
14
0.030
12
0.050
10
Aluminum Plate
Thickness (inches)
0.062
5
8
Optional mica or film insulator
0
1
2
3
4
6
7
8
for electrical isolation. Adds
approximately 1°C/W.
DRV102
TO-220 Package
Aluminum Plate Area (inches2)
FIGURE 11. TO-220 Thermal Resistance versus Aluminum Plate Area.
DRV102
12
SBVS009B
www.ti.com
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
50
40
30
20
10
0
DRV102
DDPAK
Surface-Mount Package
1oz. copper
Circuit Board Copper Area
DRV102
DDPAK
Surface-Mount Package
0
1
2
3
4
5
Copper Area (inches2)
FIGURE 12. DDPAK Thermal Resistance versus Circuit Board Copper Area.
output current times the voltage across the conducting out-
put transistor times the duty cycle. Power dissipation can be
minimized by using the lowest possible duty cycle necessary
to assure the required hold force.
low as possible for increased reliability. Junction tempera-
ture can be determined according to the equation:
TJ = TA + PDθJA
(1)
where, θJA = θJC + θCH + θHA
(2)
THERMAL PROTECTION
TJ = Junction Temperature (°C)
Power dissipated in the DRV102 will cause the junction
temperature to rise. The DRV102 has thermal shutdown
circuitry that protects the device from damage. The thermal
protection circuitry disables the output when the junction
temperature reaches approximately +165°C, allowing the de-
vice to cool. When the junction temperature cools to approxi-
mately +150°C, the output circuitry is again enabled. Depend-
ing on load and signal conditions, the thermal protection
circuit may cycle on and off. This limits the dissipation of the
driver but may have an undesirable effect on the load.
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJC = Junction-to-Case Thermal Resistance (°C/W)
θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
θHA
= Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
Figure 13 shows maximum power dissipation versus ambi-
ent temperature with and without the use of a heat sink.
Using a heat sink significantly increases the maximum
power dissipation at a given ambient temperature as shown.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to +125°C, maximum. To estimate the margin of
safety in a complete design (including heat sink), increase
the ambient temperature until the thermal protection is
triggered. Use worst-case load and signal conditions. For
good reliability, thermal protection should trigger more than
40°C above the maximum expected ambient condition of
your application. This produces a junction temperature of
125°C at the maximum expected ambient condition.
MAXIMUM POWER DISSIPATION
vs AMBIENT TEMPERATURE
10
PD = (TJ (max) – TA) /θ JA
TO-220 with Thermalloy
TJ (max) = 125°C
6030B Heat Sink
8
θ
= 16.5°C/W
JA
With infinite heat sink
θJA = 3°C/W),
(
6
4
2
0
max PD = 33W
at TA = 25°C
The internal protection circuitry of the DRV102 was designed
to protect against overload conditions. It was not intended to
replace proper heat sinking. Continuously running the
DRV102 into thermal shutdown will degrade reliability.
DDPAK
= 26°C/W (3 in 1 oz.
copper mounting pad)
2
θ
JA
DDPAK or TO-220
= 65°C/W (no heat sink)
θ
JA
0
25
50
75
100
125
HEAT SINKING
Ambient Temperature (°C)
Most applications will not require a heat sink to assure that
the maximum operating junction temperature (125°C) is not
exceeded. However, junction temperature should be kept as
FIGURE 13. Maximum Power Dissipation versus Ambient
Temperature.
DRV102
SBVS009B
13
www.ti.com
The difficulty in selecting the heat sink required lies in
determining the power dissipated by the DRV102. For dc
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor times the duty cycle. Other loads
are not as simple. Once power dissipation for an application
is known, the proper heat sink can be selected.
To maintain junction temperature below 125°C, the heat
sink selected must have a θHA less than 18.5°C/W. In other
words, the heat sink temperature rise above ambient must be
less than 37°C (18.5°C/W • 2W). For example, at 2 Watts
Thermalloy model number 6030B has a heat sink
temperature rise of about 33°C above ambient, which is
below the 37°C required in this example. Figure 13 shows
power dissipation versus ambient temperature for a TO-220
package with a 6030B heat sink.
Heat Sink Selection Example
A TO-220 package’s maximum dissipation is 2 Watts. The
maximum expected ambient temperature is 80°C. Find the
proper heat sink to keep the junction temperature below
125°C.
Another variable to consider is natural convection versus
forced convection air flow. Forced-air cooling by a small fan
can lower θCA (θCH + θHA) dramatically. Heat sink manufac-
turers provide thermal data for both of these cases. For
additional information on determining heat sink require-
ments, consult Application Bulletin AB-038.
Combining Equations 1 and 2 gives:
TJ = TA + PD(θJC + θCH + θHA
)
(3)
As mentioned earlier, once a heat sink has been selected, the
complete design should be tested under worst-case load and
signal conditions to ensure proper thermal protection.
TJ, TA, and PD are given. θJC is provided in the Specifica-
tions table, 3°C/W. θCH can be obtained from the heat sink
manufacturer. Its value depends on heat sink size, area, and
material used. Semiconductor package type, mounting screw
torque, insulating material used (if any), and thermal
joint compound used (if any) also affect θCH. A typical θCH
for a TO-220 mounted package is 1°C/W. Now we can solve
for θHA
:
(4)
TJ – TA
PD
θHA
=
– θ +θCH
(
JC
)
125°C – 80°C
θHA
=
– 3°C/W +1°C/W = 18.5°C/W
(
)
2W
DRV102
14
SBVS009B
www.ti.com
APPLICATION CIRCUITS
+5V
5kΩ
Flag
7
Can drive most types
of solenoid-actuated
valves and actuators
5
Thermal Shutdown
Over/Under Current
VS
VS
Pinch Valve
24kHz
Oscillator
Flexible Tube
Microprocessor
1
TTL Control Input
PWM
6
Plunger
On
Delay
2
Out
DRV102
Off
3
4
Gnd
Solenoid Coil
Duty Cycle
Adjust(1)
(10% to 90%)
Delay
Adjust
CD RPWM
NOTE: (1) Duty cycle can be programmed by
a resistor, analog voltage, or D/A converter.
Do not drive below 0.1V.
FIGURE 14. Fluid Flow Control System.
Brighter light results in
increased duty cycle
DRV102
5
DRV102
VS
1
5
Input
(On/Off)
VS
1
On/Off
6
Out
6
(1)
Coil
2
3
4
Out
Delay
Adjust
Lamp
2
3
4
Delay
Adjust
100Ω
Duty Cycle Adjust
Cadmium Sulfide
Optical Detector
(Clairex CL70SHL
or CLSP5M)
Aimed at
ambient
light
4-20mA
187Ω
λ
Twisted Pair
10kΩ
NOTE: (1) Rectifier diode required for inductive
loads to conduct load current during the off cycle.
FIGURE 16. 4-20mA Input to PWM Output.
FIGURE 15. Instrument Light Dimmer Circuit.
DRV102
SBVS009B
15
www.ti.com
Reduced mechanical actuation delay with high voltage pull-in followed by low duty cycle
DRV102
5
+40V (max for TPIC6273)
VS
1
On/Off
6
Out
3
4
2
RPWM
150kΩ
(25% Duty Cycle)
CD
0.047µF
Full power pulse width is control
plus interval set by CD.
74LS05
+5V
4
5
6
7
14
15
16
17
20
10
TI TPIC6273
(Octal Power Switch)
11
• • •
• • •
Control
2
3
8
9
12
13
18
19
TTL/CMOS Solenoid Selection Inputs
FIGURE 17. Improved Switching Time When Driving Multiple Loads.
DRV102
16
SBVS009B
www.ti.com
a)
VS
DRV102
5
1
2
On/Off
Higher temperature results
in lower duty cycle.
6
Delay
Adjust
Out
Heating
Element
3
4
Gnd
Thermistor
Duty
Cycle
Adjust
R1
R2
b)
VS
10µF
DRV102
5
1
2
On/Off
0.1µF
REF200
Delay
Adjust
6
7, 8
Out
100µA
100µA
Heating
Element
3
4
Gnd
1
2
2µF Film
0.1µF
VS
7
10MΩ
2
3
1kΩ
6
Duty Cycle
Adjust
OPA134
4
Temperature
Control
10kΩ
4.7V
or
Higher temperature results
in lower duty cycle.
Thermistor
5kΩ at +25°C
IN4148(1)
Integrator improves accuracy
NOTE: (1) Or any common silicon diode suited
to the mechanical mounting requirements.
20kΩ
FIGURE 18. (a) Constant Temperature Controller. (b) Improved Accuracy Constant Temperature Controller.
DRV102
SBVS009B
17
www.ti.com
DRV102
5
+12V
1
Input
(On/Off)
dc Tachometer
Coupled to Motor
6
Out
3
4
2
M
T
Delay
Adjust
R1
R2
Speed Control(1)
NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.
FIGURE 19. Constant Speed Motor Control.
5
6
+40V
Open circuit will
provide 3.4V
“on” signal
DRV102
1
2
3
4
M
40kΩ
Speed Control Input
Delay Adjust
0V to +10V
+15V
0.5µF
1kΩ
+15V
22kΩ
470kΩ
1nF
100kΩ
Frequency In
VOUT
One-Shot
47kΩ
10kΩ
2N2222
AC
Tachometer
T
VFC32
Coupled to Motor
5nF
NP0
–15V
FIGURE 20. DC Motor Speed Control Using AC Tachometer.
DRV102
18
SBVS009B
www.ti.com
VZ
+24V
DRV102
2kΩ
5
VS
5.1V
Zener
25kΩ
100kΩ
0.1µF
1
On
6
1kΩ
Off
VZ
Current Set
Out
2
3
4
Load
Duty Cycle
Adjust
Delay
Adjust
OPA237
100kΩ
0.1µF
RSHUNT
0.1Ω
5kΩ
0.6V gives ~ 90% Duty Cycle
3.7V gives ~ 10% Duty Cycle
FIGURE 21. Constant Current Output Drive.
Only one DRV102 is
turned on at sequence time.
5
5
6
VS
VS
Phase 2
Stepper
Logic In
Phase 3
Stepper
Logic In
DRV102
DRV102
6
Motor
5
6
VS
Phase 1
Stepper
Logic In
DRV102
FIGURE 22. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.
DRV102
VS = +8V to +60V
5
VS
R1
1
R2
6
Out
3
4
2
Select R1 and R2 to divide
down VS to 5.5V max.
For example: with VS = 60V
Delay Adjust
C1
20µF
R3
4.87kΩ
R1 = 11kΩ, R2 = 1kΩ
Duty Cycle Adjust
after soft start
R4
4.87kΩ
1kΩ
1kΩ + 11kΩ
+
VIN
=
• 60V = 5V
4.3V
DIN5229
Sets start-up
duty cycle
FIGURE 23. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.
DRV102
SBVS009B
19
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
1
Front Page
Updated front page appearance.
5/09
B
12
Package Mounting
Changed Figure 10 to show TI package designator.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DRV102
20
SBVS009B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2013
PACKAGING INFORMATION
Orderable Device
DRV102F
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
OBSOLETE DDPAK/
TO-263
KTW
7
7
7
7
7
7
TBD
Call TI
CU SN
CU SN
CU SN
CU SN
CU SN
Call TI
DRV102F/500
DRV102FKTWT
DRV102FKTWTG3
DRV102T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTW
KTW
KTW
KVT
KVT
500
50
50
50
50
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-3-245C-168 HR
Level-3-245C-168 HR
N / A for Pkg Type
N / A for Pkg Type
DRV102F
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
DRV102F
DRV102F
DRV102T
DRV102T
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
TO-220
Green (RoHS
& no Sb/Br)
DRV102TG3
TO-220
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV102F/500
DDPAK/
TO-263
KTW
KTW
7
7
500
50
330.0
24.4
10.95 16.5
5.15
16.0
24.0
Q2
DRV102FKTWT
DDPAK/
TO-263
330.0
24.4
10.6 15.6
4.9
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV102F/500
DDPAK/TO-263
DDPAK/TO-263
KTW
KTW
7
7
500
50
346.0
367.0
346.0
367.0
41.0
45.0
DRV102FKTWT
Pack Materials-Page 2
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.304 (7,72)
0.296 (7,52)
0.300 (7,62)
0.252 (6,40)
0.410 (10,41)
0.385 (9,78)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
H
0.0625 (1,587)
0.0585 (1,485)
0.055 (1,40)
0.045 (1,14)
0.064 (1,63)
0.056 (1,42)
0.187 (4,75)
0.179 (4,55)
0.370 (9,40)
0.330 (8,38)
0.605 (15,37)
0.595 (15,11)
H
A
0.012 (0,305)
0.000 (0,00)
C
0.104 (2,64)
0.096 (2,44)
H
0.019 (0,48)
0.017 (0,43)
0.050 (1,27)
0.026 (0,66)
C
0.014 (0,36)
0.034 (0,86)
0.022 (0,57)
0°~3°
C
F
0.010 (0,25)
M
B
A M
C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
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