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DRV10983-Q1

SLVSD14A –JUNE 2017–REVISED JUNE 2020

DRV10983-Q1 Automotive, Three-Phase, Sensorless BLDC Motor Driver

1 Features

–

Thermal shutdown protection

•

Thermally enhanced package

1

•

Qualified for automotive applications

AEC-Q100 qualified with the following results:

2 Applications

–

Device temperature grade 1: –40°C to 125°C

ambient operating temperature range

•

Small automotive pumps and fans

Seat ventilation fans

–

Device HBM ESD classification level 1C

Device CDM ESD classification level C4A

Motorcycle fuel pumps

HEV battery cooling fans

•

Operation voltage range:

–

Motor operation, 6.2 V to 28 V

3 Description

Register setting preserved, 4.5 V to 45 V

The DRV10983-Q1 device is a 3-phase sensorless

motor driver with integrated power MOSFETs, which

can provide continuous drive current up to 2 A. The

device is specifically designed for cost-sensitive, low-

noise, low-external-component-count fan and pump

applications.

•

Supports load dump voltage up to 45 V

Total driver H + L r_DS(on)

–

250 mΩ at T_A= 25°C

325 mΩ at T_A= 125°C

•

Drive current: 2-A continuous winding current (3-A

Peak)

The DRV10983-Q1 device preserves register setting

down to 4.5 V and delivers current to the motor with

supply voltage as low as 6.2 V. If the power supply

voltage is higher than 28 V, the device stops driving

the motor and protects the DRV10983-Q1 circuitry.

This function is able to handle a load dump condition

up to 45 V.

Configurable output PWM slew rate and frequency

for EMI management

Sensorless proprietary Back Electromotive Force

(BEMF) control scheme (no need of hall sensors)

•

Continuous sinusoidal 180° commutation

TI provides DRV10983-Q1 tuning Guide for quick

setup and tuning of the device for optimal

performance.

Initial position-detect algorithm to avoid back spin

during start-up

•

No external sense resistor required

Flexible user interface options:

Device Options:

•

DRV10983Q: Sleep Version

DRV10983SQ: Standby Version

–

I²C interface: access registers for command

and feedback

(1)

Device Information

–

Dedicated SPEED pin: accepts either analog

or PWM input

PART NUMBER

DRV10983-Q1

PACKAGE

BODY SIZE (NOM)

HTSSOP (24)

7.80 mm × 6.40 mm

–

Dedicated FG pin: provides TACH feedback

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Spin-up profile can be customized with

EEPROM

–

Forward-reverse control with DIR pin

Application Schematic

•

Integrated buck converter to efficiently provide 5‑V

and 3.3-V LDOs for internal and external circuits

VCC

0.1 µF

1

2

3

4

5

6

7

8

9

VCP

VCC 24

VCC 23

10 µF

CPP

Supply current 8.5 mA with standby version

(DRV10983SQ)

10 nF

CPN

W

V

22

21

20

19

18

17

10 µF

5 V

SW

47 µH

SWGND

VREG

V1P8

GND

V3P3

Supply current of 48 μA with sleep version

(DRV10983Q)

M

V

1 µF

U

Protection features

1 µF

PGND 16

PGND 15

DIR 14

4.75 kW

–

Overcurrent protection (protection for phase-to-

phase, phase-to-GND and phase-to-v_CCshorts

10 SCL

11 SDA

12 FG

SPEED 13

–

Lock detection

Interface to

Microcontroller

Anti-Voltage Surge (AVS) protection

UVLO protection

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV10983-Q1

SLVSD14A –JUNE 2017–REVISED JUNE 2020

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 21

8.5 Register Maps......................................................... 47

Application and Implementation ........................ 64

9.1 Application Information............................................ 64

9.2 Typical Application ................................................. 64

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (Continued)........................................ 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 12

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 14

9

10 Power Supply Recommendations ..................... 67

11 Layout................................................................... 67

11.1 Layout Guidelines ................................................. 67

11.2 Layout Example .................................................... 67

12 Device and Documentation Support ................. 68

12.1 Trademarks........................................................... 68

12.2 Electrostatic Discharge Caution............................ 68

12.3 Receiving Notification of Documentation Updates 68

12.4 Community Resources.......................................... 68

12.5 Glossary................................................................ 68

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 68

4 Revision History

Changes from Original (June 2017) to Revision A

Page

•

Updated timing information for entering and exiting sleep mode and standby mode ............................................................ 8

Added Analog and PWM mode timing diagrams.................................................................................................................. 10

Updated naming convention in Step-Down Regulator subsection ....................................................................................... 14

Changed the Conditions to Enter or Exit Sleep or Standby Condition table to reflect Electrical Characteristics

parameter names.................................................................................................................................................................. 18

•

Added Speed pin note to Table 1 ........................................................................................................................................ 19

Added subsection, Required Sequence to Enter Sleep Mode ............................................................................................. 19

Changed Figure 13 and Figure 14 ....................................................................................................................................... 21

Changed Table 4 ................................................................................................................................................................. 24

Updated Inductive AVS Function subsection ....................................................................................................................... 41

Changed eeWRnEn field description to properly reflect actual function .............................................................................. 55

Changed BEMF comparator hysteresis to reflect Electrical Characteristics specifications ................................................. 58

Changed Table 36 ............................................................................................................................................................... 65

Added EEprom note to Layout Guidelines ........................................................................................................................... 67

2

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5 Description (Continued)

The DRV10983-Q1 device uses a proprietary sensorless control scheme to provide continuous sinusoidal drive,

which significantly reduces the pure tone acoustics that typically occur as a result of commutation. The interface

to the device is designed to be simple and flexible. The motor can be controlled directly through PWM, analog, or

I²C inputs. Motor speed feedback is available through both the FG pin and the I²C interface simultaneously.

The DRV10983-Q1 device features an integrated buck regulator to step down the supply voltage efficiently to 5 V

for powering both internal and external circuits. The 3.3-V LDO also may be used to provide power for external

circuits. The device is available in either a sleep mode or a standby mode version to conserve power when the

motor is not running. The standby mode (8.5 mA) version (DRV10983SQ) leaves the regulator running and the

sleep mode (48 μA) version (DRV10983Q) shuts the regulator off. Use the standby mode version in applications

where the regulator is used to power an external microcontroller. Throughout this data sheet, the DRV10983-Q1

part number is used for both devices for example DRV10983Q (sleep version) and DRV10983SQ (standby

version), except for specific discussions of sleep vs standby functionality.

An I²C interface allows the user to reprogram specific motor parameters in registers and to program the

EEPROM to help optimize the performance for a given application. The DRV10983-Q1 device is available in a

thermally-efficient HTSSOP, 24-pin package with an exposed thermal pad. The operating ambient temperature is

specified from –40°C to 125°C.

6 Pin Configuration and Functions

PWP PowerPAD™ Package

24-Pin HTSSOP With Exposed Thermal Pad

Top View

VCP

CPP

1

24

23

22

21

20

19

18

17

16

15

14

13

VCC

W

2

CPN

3

SW

4

W

SWGND

VREG

V1P8

GND

V3P3

SCL

5

V

6

V

Thermal

Pad

7

U

8

U

9

PGND

DIR

SPEED

10

11

12

SDA

FG

Not to scale

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Pin Functions

TYPE

DESCRIPTION

(1)

N/AME

CPN

HTSSOP

3

2

P

Charge pump pin 1, use a ceramic capacitor between CPN and CPP

Charge pump pin 2, use a ceramic capacitor between CPN and CPP

CPP

Direction;

DIR

14

I

When low, phase driving sequence is U → V → W

When high, phase driving sequence is U → W → V

FG

12

8

O

P

I

FG signal output indicates speed of motor

Digital and analog ground

Power ground

I²C clock signal

I²C data signal

GND

PGND

SCL

SDA

SPEED

SW

15, 16

10

11

I/O

I

13

Speed control signal for PWM or analog input speed command

Step-down regulator switching node output

Step-down regulator ground

Motor U phase

4

O

P

O

SWGND

U

5

17, 18

19, 20

V

Motor V phase

Internal 1.8-V digital core voltage. V1P8 capacitor must connect to GND. This is an output, but is not

specified to drive external loads.

V1P8

V3P3

7

9

P

Internal 3.3-V supply voltage. V3P3 capacitor must connect to GND. This is an output and may drive

external loads not to exceed I_{V3P3_MAX}

.

V_CC

VCP

VREG

W

23, 24

P

O

Device power supply

1

6

Charge pump output, use a ceramic capacitor between VCP and V_CC

Step-down regulator output and feedback point

Motor W phase

21, 22

The exposed thermal pad must be electrically connected to the ground plane by soldering to the PCB

for proper operation, and connected to the bottom side of the PCB through vias for better thermal

spreading.

Thermal pad

(GND)

—

P

(1) I = Input, O = Output, I/O = Input/output, NC = No connect, P = Power

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range

(1)

MIN

–0.3

–1

MAX

UNIT

V_CC

28

V_CCduring load dump (V_CCslew rate < 1 V/µs)

45

SPEED

4

Input voltage⁽²⁾

V

PGND, SWGND

0.3

SCL, SDA

4

DIR

U, V, W

30

SW

–1

30

VREG

–0.3

–40

–55

7

FG

4

(2)

Output voltage

VCP

V_CC+ 6

30

V

CPN

CPP

V_CC+ 6

4

V3P3

V1P8

2.5

150

T_{J_MAX}

T_stg

Maximum junction temperature

Storage temperature

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the ground terminal (GND) unless otherwise noted.

7.2 ESD Ratings

VALUE

±2000

±750

UNIT

(1)

Human body model (HBM), per AEC Q100-002, all pins

Charged device model (CDM), per AEC Q100-011, all pins

Electrostatic

discharge

V_(ESD)

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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7.3 Recommended Operating Conditions

MIN

4.5

NOM

12

MAX

45

UNIT

V_CC, register contents preserved

Supply voltage

V

V_CC, motor operational

6.2

12

28

U, V, W

–0.7

–0.1

–0.7

29

SCL, SDA, FG, SPEED, DIR

3.3

3.6

PGND, GND, SWGND

Voltage range

0.1

V

VCP, CPP

V_CC+ 5

V_CC

100

5

CPN

SW

Step-down regulator output current (buck mode)

Step-down regulator output current (resistive mode)

Current range

mA

°C

V3P3 LDO output current (no load on VREG and V3P3 in

resitive mode)

5

T_A

Operating ambient temperature

–40

125

7.4 Thermal Information

DRV10983Q

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

24 PINS

36.1

17.4

14.8

0.4

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

14.5

1.1

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

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7.5 Electrical Characteristics

over operating voltage and ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT (DRV10983Q)

V_SPEED= 0 V; VCC = 12 V; T_A

25℃

=

48

54

I_VccSLEEP1

Sleep current

Active current

µA

81

V_SPEED= 0 V; VCC = 12 V; across

temperature

V_SPEED> 0 V; buck regulator with

inductor; no motor load

10

13

15

I_Vcc

mA

16

V_SPEED> 0 V; buck regulator with

resistor; no motor load

SUPPLY CURRENT (DRV10983SQ)

V_SPEED= 0 V; buck regulator with

inductor

8.5

11

10

13

14

I_VccSTBY

Standby current

Active current

mA

15

V_SPEED= 0 V; buck regulator with

resistor

V_SPEED> 0 V; buck regulator with

inductor; no motor load

15

I_Vcc

mA

16

V_SPEED> 0 V; buck regulator with

resistor; no motor load

UVLO

UVLO rising threshold

voltage

V_{UVLO_R}

5.8

5.6

6

5.8

6.2

6

V

UVLO falling threshold

voltage

V_{UVLO_F}

UVLO threshold voltage

hysteresis

V_{UVLO_HYS}

170

195

220

mV

V_{V1P8_UVLO_R}

V_{V1P8_UVLO_F}

V_{V3P3_UVLO_R}

V_{V3P3_UVLO_F}

V1P8 UVLO rising threshold

V1P8 UVLO falling threshold

V3P3 UVLO rising threshold

V3P3 UVLO falling threshold

1.5

1.4

2.7

2.5

4

1.6

1.55

2.85

2.7

1.7

1.65

2.95

2.8

V

V_{VREG_UVLO_R}VREG UVLO rising threshold

4.2

4.3

V_{VREG_UVLO_F}VREG UVLO falling

threshold

3.9

4.2

V

LDO OUTPUT

Buck regulator with inductor, 20-mA

load

V3P3

Output voltage

3.1

3.3

3.5

V

Buck regulator with resistor, no load

Only with inductor mode of buck

operation, with resistor mode no

load

I_{V3P3_MAX}

V1P8

Maximum load from V3P3

Output voltage

20

mA

V

No load

1.7

4.5

1.8

5

1.9

STEP-DOWN REGULATOR

L_SW= 47 µH, C_SW= 10 µF

I_load= 100 mA

V_REG

Regulator output voltage

5.5

V

R_SW= 39 Ω, C_SW= 10 µF

I_load= 5 mA

Maximum load from V_REGin

switching mode

I_{REG_MAX_L}

I_{REG_MAX_R}

L_SW= 47 µH, C_SW= 10 µF

100

5

mA

Maximum load from V_REGin

linear mode

R_SW= 39 Ω, C_SW= 10 µF

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Electrical Characteristics (continued)

over operating voltage and ambient temperature range (unless otherwise noted)

PARAMETER

INTEGRATED MOSFET

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_A= 25˚C; V_(VCC)> 6.5 V; Io = 1 A

T_A= 125˚C; V_(VCC)> 6.5V; Io = 1 A

250

325

400

mΩ

550

r_DS(ON)

Series resistance (H + L)

SPEED – ANALOG MODE

V_{AN/A_FS}Analog full-speed voltage

V_{AN/A_ZS}

V_(V3P3)× 0.9

0

V_(V3P3)

100

V

Analog zero-speed voltage

mV

Sampling period for analog

voltage on SPEED pin

t_SAM

320

6.5

µs

V_{AN/A_RES}

Analog voltage resolution

mV

SPEED – PWM DIGITAL MODE

V_{DIG_IH}

V_{DIG_IL}

ƒ_PWM

PWM input high voltage

2.2

0.1

V

PWM input low voltage

PWM input frequency

0.6

100 kHz

STANDBY MODE (DRV10983SQ)

Analog voltage to enter

standby mode

V_{EN_SB}

SpdCtrlMd = 0 (analog mode)

100

700

mV

V

Analog voltage to exit

standby mode

V_{EX_SB}

0.17

1

SpdCtrlMd = 0 (analog mode)

V_SPEED> V_{EX_SB}

Time needed to exit from

t_{EX_SB_ANA}

ms

standby mode

SpdCtrlMd = 0 (analog mode)

V_SPEED> V_{EX_SB}; ISDen = 0;

BrkDoneThr[2:0] = 0

Time taken to drive motor

t_{EX_SB_DR_ANA}

350

2

ms

µs

after exiting standby mode

SpdCtrlMd = 1 (PWM mode)

V_SPEED> V_{DIG_IH}

Time needed to exit from

t_{EX_SB_PWM}

standby mode

SpdCtrlMd = 1 (PWM mode)

V_{SPEED_DUTY}> 0; ISDen = 0;

BrkDoneThr[2:0] = 0

Time taken to drive motor

t_{EX_SB_DR_PWM}

350

ms

after exiting standby mode

SpdCtrlMd = 0 (analog mode)

V_SPEED< V_{EN_SB}; AvSIndEn = 0

Time needed to enter

t_{EN_SB_ANA}

6

ms

standby mode

SpdCtrlMd = 1 (PMW mode)

V_SPEED< V_{DIG_IL;}AvSIndEn = 0

Time needed to enter

t_{EN_SB_PWM}

60

standby mode

8

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Electrical Characteristics (continued)

over operating voltage and ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SLEEP MODE (DRV10983Q)

Analog voltage to enter sleep

mode

V_{EN_SL}

SpdCtrlMd = 0 (analog mode)

100

mV

V

Analog voltage to exit sleep

mode

V_{EX_SL}

2.2

SpdCtrlMd = 0 (analog mode)

V_SPEED> V_{EX_SL}

Time needed to exit from

sleep mode

t_{EX_SL_ANA}

2

350

2

µs

SpdCtrlMd = 0 (analog mode)

V_SPEED> V_{EX_SL}; ISDen = 0;

BrkDoneThr[2:0] = 0

Time taken to drive motor

after exiting from sleep mode

t_{EX_SL_DR_ANA}

ms

µs

SpdCtrlMd = 1 (PWM mode)

V_SPEED> V_{DIG_IH}

Time needed to exit from

sleep mode

t_{EX_SL_PWM}

SpdCtrlMd = 1 (PWM mode)

V_SPEED> V_{DIG_IH}; ISDen = 0;

BrkDoneThr[2:0] = 0

Time taken to drive motor

after exiting from sleep mode

t_{EX_SL_DR_PWM}

350

ms

SpdCtrlMd = 0 (analog mode)

V_SPEED< V_{EN_SL}; AvSIndEn = 0

Time needed to enter sleep

mode

t_{EN_SL_ANA}

6

ms

kΩ

SpdCtrlMd = 1 (PMW mode)

V_SPEED< V_{DIG_IL}; AvSIndEn = 0

Time needed to enter sleep

mode

t_{EN_SL_PWM}

R_{PD_SPEED_SL}

60

Internal SPEED pin pull

down resistance to ground

V_SPEED= 0 (Sleep mode)

55

DIGITAL I/O (DIR INPUT, FG OUTPUT )

V_{DIR_H}

V_{DIR_L}

Input high

Input low

2.2

V

0.6

Output high voltage I_o= 5

mA

V_{FG_OH}

V_{FG_OL}

3.3

V

Output low voltage I_o= 5 mA

I²C SERIAL INTERFACE

V_{I2C_H}

V_{I2C_L}

Input high

2.2

0

V

Input low

I²C clock frequency

0.6

400 kHz

fI2C

LOCK DETECTION RELEASE TIME

t_{LOCK_OFF}

t_{LCK_ETR}

Lock release time

Lock enter time

5

s

0.3

OVERCURRENT PROTECTION

I_{OC_limit_HS}HS overcurrent protection

I_{OC_limit_LS}LS overcurrent protection

THERMAL SHUTDOWN

V_CC< 28.5 V

3.5

4.25

5.5

A

Junction temperature

shutdown threshold

T_SDN

150

165

180

°C

Junction temperature

shutdown hysteresis

T_{SDN_HYS}

T_WARN

15

20

25

°C

Junction temperature

warning threshold

115

125

140

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Electrical Characteristics (continued)

over operating voltage and ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PHASE DRIVER

PHslew = 0; measure 20% to 80%;

V_CC= 12 V

Phase slew rate switching

low to high

SL_{PH_LH0}

85

60

38

27

85

59

36

25

120

80

145 V/µs

100 V/µs

62 V/µs

44 V/µs

145 V/µs

100 V/µs

60 V/µs

45 V/µs

PHslew = 1; measure 20% to 80%;

V_CC= 12 V

Phase slew rate switching

low to high

SL_{PH_LH1}

SL_{PH_LH2}

SL_{PH_LH3}

SL_{PH_HL0}

SL_{PH_HL1}

SL_{PH_HL2}

SL_{PH_HL3}

PHslew = 2; measure 20% to 80%;

V_CC= 12 V

Phase slew rate switching

low to high

50

PHslew = 3; measure 20% to 80%;

V_CC= 12 V

Phase slew rate switching

low to high

35

PHslew = 0; measure 80% to 20%;

V_CC= 12 V

Phase slew rate switching

high to low

120

80

PHslew = 1; measure 80% to 20%;

V_CC= 12 V

Phase slew rate switching

high to low

PHslew = 2; measure 80% to 20%;

V_CC= 12 V

Phase slew rate switching

high to low

50

PHslew = 3; measure 80% to 20%;

V_CC= 12 V

Phase slew rate switching

high to low

35

BEMF

COMPARATOR

BEMF_HYS = 0

BEMF_HYS = 1

7

20

40

30

BEMF_HYS

BEMF comparator hysteresis

mV

51

17

LOAD DUMP PROTECTION

Load dump protection mode

entry on rising V_CCthreshold

V_{OV_R}

28.5

27.7

0.73

29.2

28.2

1

30

28.8

1.1

V

Load dump protection mode

exit on falling V_CCthreshold

V_{OV_F}

Load dump protection mode

hysteresis

V_{OV_HYS}

Speed Pin

V_{EX_SL}

V_{EN_SL}

t_{EX_SL_ANA}

t_{EN_SL_ANA}

V1P8

t_{EX_SL_DR_ANA}

Phase Pin

Motor Drive State

Figure 1. DRV10983Q Analog Mode Timing

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V_{DIG_IH}

V_{DIG_IL}

Speed Pin

t_{EX_SL_PWM}

t_{EN_SL_PWM}

V1P8

t_{EX_SL_DR_PWM}

Phase Pin

Motor Drive State

Figure 2. DRV10983Q PWM Mode Timing

Speed Pin

V_{EX_SB}

V_{EN_SB}

t_{EX_SB_ANA}

t_{EN_SB_ANA}

Internal

Signal

(Digital

Reset)

t_{EX_SB_DR_ANA}

Phase Pin

Motor Drive State

Figure 3. DRV10983SQ Analog Mode Timing

V_{DIG_IH}

V_{DIG_IL}

Speed Pin

t_{EX_SB_PWM}

t_{EN_SB_PWM}

Internal

Signal

(Digital

Reset)

t_{EX_SB_DR_PWM}

Phase Pin

Motor Drive State

Figure 4. DRV10983SQ PWM Mode Timing

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7.6 Typical Characteristics

15

5.2

5.1

5

I_VCC

12

9

6

4.9

4.8

3

0

5

10

15

Power Supply (V)

20

25

30

0

5

10

15

Power Supply (V)

20

25

30

D001

D002

Figure 5. Supply Current vs Power Supply Voltage

Figure 6. Step-Down Regulator Output vs Power Supply

Voltage

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8 Detailed Description

8.1 Overview

The DRV10983-Q1 device is a three-phase sensorless motor driver with integrated power MOSFETs that

provides drive-current capability up to 2 A continuously. The device is specifically designed for low-noise, low-

external-component-count motor-drive applications. The device is configurable through a simple I²C interface to

accommodate different motor parameters and spin-up profiles for different customer applications.

A 180° sensorless control scheme provides continuous sinusoidal output voltages to the motor phases to enable

ultra-quiet motor operation by keeping the electrically induced torque ripple small.

The DRV10983-Q1 device features extensive protection and fault-detection mechanisms to ensure reliable

operation. Voltage surge protection prevents the input V_CCcapacitor from overcharging, which is typical during

motor deceleration. The device provides overcurrent protection without the need for an external current-sense

resistor. Rotor-lock detection is available through several methods. These methods can be configured with

register settings to ensure reliable operation. The device provides additional protection for undervoltage lockout

(UVLO) and for thermal shutdown.

The commutation control algorithm continuously measures the motor phase current and periodically measures

the V_CCsupply voltage. The device uses this information for BEMF estimation, and the information is also

provided through the I²C register interface for debug and diagnostic use in the system, if desired.

A buck step-down regulator efficiently steps down the supply voltage. The output of this regulator provides power

for the internal circuits and can also be used to provide power for an external circuit such as a microcontroller. If

providing power for an external circuit is not necessary (and to reduce system cost), configure the buck step-

down regulator as a linear regulator by replacing the inductor with a resistor.

The DRV10983-Q1 device has a flexible interface, capable of supporting both analog and digital inputs. In

addition to the I²C interface, the device has FG, DIR, and SPEED pins. SPEED is the speed command input pin.

DIR is the direction control input pin. FG is the speed indicator output, which shows the frequency of the motor

commutation.

EEPROM is integrated in the DRV10983-Q1 device as memory for the motor parameter and operation settings.

EEPROM data transfers to the registers after power-on and exit from sleep mode.

The DRV10983-Q1 device can also operate in register mode. If the system includes a microcontroller

communicating through the I²C interface, the device can dynamically update the motor parameters and operation

settings by writing to the registers. In this configuration, the EEPROM data is bypassed by the register settings.

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8.2 Functional Block Diagram

SDA

I²C

Communication

Register

EEPROM

SCL

VCC

VCP

CPP

CPN

SW

Charge

Pump

5-V Step-Down

Regulator

VREG

SWGND

V3P3

3.3-V LDO

1.8-V LDO

FG

V_CC

V1P8

GND

VCP

Oscillator

Band Gap

U

Pre-

Driver

U

V

Logic

Core

V / I

Sensor

ADC

W

VCP

PWM and Analog

Speed Control

SPEED

DIR

V

Pre-

Driver

Lock

Overcurrent

Thermal

UVLO

VCP

W

Pre-

Driver

GND

PGND

8.3 Feature Description

8.3.1 Regulators

8.3.1.1 Step-Down Regulator

The DRV10983-Q1 device includes a step-down hysteretic voltage regulator that can be operated as either a

switching buck regulator using an external inductor or as a linear regulator using an external resistor. The best

efficiency is achieved when the step-down regulator is in buck mode (see Figure 7). The regulator output voltage

is 5 V. When the regulated voltage drops by the hysteresis level, the high-side FET turns on to raise the

regulated voltage back to the target of 5 V. The switching frequency of the hysteretic regulator is not constant

and changes with load.

If the step-down regulator is configured in buck mode, see I_{REG_MAX_L}in Electrical Characteristics to determine

the amount of current provided for external load. If the step-down regulator is configured in linear mode, see

I_{REG_MAX_R}in Electrical Characteristics to determine the amount of current provided for external load. Active

current I_CCis higher in buck mode compared to linear mode.

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Feature Description (continued)

IC

VREG

V_CC

47 µH

39 Ω

SW

5 V

10 µF

Load

SWGND

Buck Regulator with External Inductor

Buck Regulator with External Resistor

Figure 7. Step-Down Regulator Configurations

8.3.1.2 3.3-V and 1.8-V LDO

The DRV10983-Q1 device includes a 3.3-V LDO and a 1.8-V LDO. The 3.3-V LDO is powered by Vreg and 1.8-

V LDO is powered by 3.3-V LDO. The 1.8-V LDO is for internal circuits only. The 3.3-V LDO is mainly for internal

circuits, but can also drive external loads not to exceed I_{V3P3_MAX}. For example, it can work as a pullup voltage

for the FG, DIR, SDA, and SCL interface.

Both the V1P8 and V3P3 capacitors must be connected to GND.

8.3.2 Protection Circuits

8.3.2.1 Thermal Shutdown

The DRV10983-Q1 device has a built-in thermal shutdown function, which shuts down the device when the

junction temperature is more than T_SDN˚C and recovers operating conditions when the junction temperature falls

to T_SDN– T_{SDN_HYS}˚C.

The OverTemp status bit (address 0x00, bit 15) is set during thermal shutdown. In addition to the thermal

shutdown function there is a warning bit that is set whenever the device exceeds T_WARNand is indicated by the

TempWarning bit of the FaultReg register (address 0x00, bit 14).

8.3.2.2 Undervoltage Lockout (UVLO)

The DRV10983-Q1 device has a built-in UVLO function block. The device is locked out when V_CCis below

V_{UVLO_F}and is unlocked when V_CCis above V_{UVLO_R}. The hysteresis of the UVLO threshold is V_{UVLO_HYS}. In

addition to the main supply, the step-down regulator, charge pump, and 3.3-V LDO all have undervoltage lockout

monitors.

8.3.2.3 Overcurrent Protection

The overcurrent protection function acts to protect the device if the current, as measured from the FETs, exceeds

the I_OC-limitthreshold. It protects the device in the event of a short-circuit condition on the motor phases. This

includes phase shorts to GND, phase shorts to phase, or phase shorts to V_CC. The DRV10983-Q1 device places

the output drivers into a high-impedance state until the lock time t_{LOCK_OFF}has expired. The OverCurr status bit

of the FaultReg register (address 0x00, bit 11) is set.

The DRV10983-Q1 device also provides acceleration current-limit and lock-detection current-limit functions to

protect the device and motor (see Current Limit and Lock Detect and Fault Handling ).

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Feature Description (continued)

8.3.2.4 Lock

When the motor is blocked or stopped by an external force, lock protection is triggered, and the device stops

driving the motor immediately. After the lock release time t_{LOCK_OFF}, the DRV10983-Q1 device resumes driving

the motor again. If the lock condition is still present, it enters the next lock protection cycle, and repeats until the

lock condition is removed. With this lock protection, the motor and device do not overheat or become damaged

due to the motor being locked (see Lock Detect and Fault Handling ).

During a lock condition the Status register indicates which of the locks has occurred.

8.3.3 Motor Speed Control

The DRV10983-Q1 device offers four methods for indirectly controlling the speed of the motor by adjusting the

output voltage amplitude. This can be accomplished by varying the supply voltage (V_CC) or by controlling the

speed command. The speed command can be controlled in one of three ways. The user can set the speed

command by adjusting either the PWM input (PWM in) or the analog input (Analog) or by writing the speed

command directly through the I²C serial port (I²C). The speed command is used to determine the PWM duty

cycle output (PWM_DCO) (see Figure 9).

The input PWM input (PWM in) can have a minimum duty cycle limit applied. DutyCycleLimit[1:0], accessible

through the I²C interface, allows the user to configure the minimum duty cycle behavior. This behavior is

illustrated in Figure 8.

DutyCycleLimit[1:0], Reg0x95

Output Duty

Cycle (%)

Output Duty

Cycle (%)

10 - linear down to 5%, then holds at 5% until

duty command is 1.5 %; 100 % for duty command

below 1.5 %.

00 - linear down to 5%, then holds at 5% until

duty command is 1.5 %; 0 % for duty command

below 1.5 %.

11 - linear down to 10%, then holds at 10% until

duty command is 1.5 %; 100 % for duty command

below 1.5 %.

01 - linear down to 10%, then holds at 10% until

duty command is 1.5 %; 0 % for duty command

below 1.5 %.

100

10

5

10

5

0

Input Duty Cycle

0

Input Duty Cycle (%)

0 1.5

5

10

0 1.5

5

10

Figure 8. Duty Cycle Profile

The speed command may not always be equal to the PWM_DCO because the DRV10983-Q1 device has the

AVS function (see Anti Voltage Suppression Function), the acceleration current-limit function (see Acceleration

Current Limit), and the closed-loop accelerate function (see Closed-Loop Accelerate) to optimize the control

performance. These functions can limit the PWM_DCO, which affects the output amplitude (see Figure 9).

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Feature Description (continued)

PWM Duty

ADC

PWM In

AVS,

Acceleration Current Limit

Closed Loop Accelerate

SPEED Pin

Analog

Speed

Command

I²C

PWM_

DCO

Output

Amplitude

V_CC

X

Motor

Figure 9. Multiplexing the Speed Command to the Output Amplitude Applied to the Motor

The output voltage amplitude applied to the motor is developed through sine wave modulation so that the phase-

to-phase voltage is sinusoidal.

When any phase is measured with respect to ground, the waveform is sinusoidally coupled with third-order

harmonics. This encoding technique permits one phase to be held at ground while the other two phases are

pulse-width modulated. Figure 10 and Figure 11 show the sinusoidal encoding technique used in the DRV10983-

Q1 device.

PWM Output

Average Value

Figure 10. PWM Output and the Average Value

U-V

U

V-W

W-U

V

W

Sinusoidal voltage from phase to phase

Sinusoidal voltage with third-order harmonics

from phase to GND

Figure 11. Representing Sinusoidal Voltages With Third-Order Harmonic Output

The output amplitude is determined by the magnitude of V_CCand the PWM duty cycle output (PWM_DCO). The

PWM_DCO represents the peak duty cycle that is applied in one electrical cycle. The maximum amplitude is

reached when PWM_DCO is at 100%. The peak output amplitude is V_CC. When the PWM_DCO is at 50%, the

peak amplitude is V_CC/ 2 (see Figure 12).

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Feature Description (continued)

V_CC

100% PWM DCO

50% PWM DC0

V_CC/ 2

Figure 12. Output Voltage Amplitude Adjustment

Motor speed is controlled indirectly by controlling the output amplitude, which is achieved by either controlling

V_CC, or controlling the PWM_DCO. The DRV10983-Q1 device provides different options for the user to control

the PWM_DCO:

•

Analog input (SPEED pin)

PWM encoded digital input (SPEED pin)

I²C serial interface.

See the Closed Loop section for more information.

8.3.4 Load Dump Handling

The recommended operation voltage of the DRV10983-Q1 device is from 6.2 V to 28 V. The device is able to

drive the motor within this V_CCrange.

In the load dump condition, V_CCcan rise up to 45 V. Once the DRV10983-Q1 device detects that V_CCis higher

than V_{OV_R}, it stops driving the motor and protects its own circuitry. When V_CCdrops below V_{OV_F}, the

DRV10983-Q1 device continues to operate the motor based on the user’s command.

8.3.5 Sleep or Standby Condition

The DRV10983-Q1 device is available in either a sleep mode (DRV10983Q) or standby mode version

(DRV10983SQ). The DRV10983-Q1 device enters either sleep or standby to conserve energy. When the device

enters either sleep or standby, the device stops driving the motor. The step-down regulator is disabled in the

sleep mode version to conserve more energy. The I²C interface is disabled and any register data not stored in

EEPROM is reset for the sleep mode version. The step-down regulator remains active in the standby mode

version. The register data is maintained, and the I²C interface remains active for standby mode version.

For different speed command modes, shows the timing and command to enter the sleep or standby condition.

Table 1. Conditions to Enter or Exit Sleep or Standby Condition

SPEED COMMAND

MODE

ENTER STANDBY

CONDITION

ENTER SLEEP

CONDITION

EXIT FROM STANDBY

CONDITION

EXIT FROM SLEEP

CONDITION

SPEED pin voltage <

V_{EN_SB}for t_{EN_SB_ANA}

SPEED pin voltage <

V_{EN_SL}for t_{EN_SL_ANA}

SPEED pin voltage >

V_{EX_SB}for t_{EX_ SB_ANA}

SPEED pin voltage >

V_{EX_SL}for t_{EX_SL_ANA}

Analog

PWM

SPEED pin low (V <

V_{DIG_IL}) for t_{EN_SB_PWM}

SPEED pin low (V <

V_{DIG_IL}) for t_{EN_SL_PWM}

SPEED pin high (V >

V_{DIG_IH}) for t_{EX_SB_PWM}

SPEED pin high (V >

V_{DIG_IH}) for t_{EX_SL_PWM}

SPEED pin high (V >

V_{DIG_IH}) for t_{EX_SL_PWM}

(PWM mode) or SPEED

pin voltage > V_{EX_SL}for

t_{EX_SL_ANA}(Analog mode)

SpdCtrl[8:0] is

programmed as 0 for

t_{EN_SB_PWM}

See Required Sequence to

Enter Sleep Mode

SpdCtrl[8:0] is programmed

as non-zero for t_{EX_SB_PWM}

I²C

Changed Table 4

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Speed pin in DRV10983SQ (Standby version) and DRV10983Q (sleep version) should be in known state (pulled

high or low) when the speed is controlled via I²C.

Note that when using the analog speed command, a higher voltage is required to exit from the sleep condition

than from the standby condition. The I²C speed command cannot take the device out of the sleep condition

because I²C communication is disabled during the sleep condition.

Table 2. Minimum PWM Duty Cycle Requirement for Different PWM Frequency to Exit Sleep Condition

INPUT PWM FREQUENCY (kHz)

PWM DUTY CYCLE (%)

0.1 to 0.5

0.5 to 1

1 to 50

50 to 100

100

14

11

9

4

3.5

8.3.5.1 Required Sequence to Enter Sleep Mode

In I²C speed command mode, either of two sequence options can be used to enter sleep mode.

8.3.5.1.1 Option 1

1. Provide a non-zero value to the speed control register. For example, write 100 to register 0x30,

speedCtrl[8:0].

2. Set the I²C OverRide bit to 1. That is, write 1 to register 0x30, speedCtrl[15].

3. In analog mode, be sure SPEED pin voltage is less than V_{EN_SL}for t_{EN_SL_ANA}. In PWM mode, make sure

SPEED pin is low (V < V_{DIG_IL}) for t_{EN_SL_PWM}

.

4. Provide the value of zero to the speed control register to enter sleep mode. That is, write 0 to register 0x30,

speedCtrl[8:0].

8.3.5.1.2 Option 2

1. Set the motor disable bit to 1. That is, write 1 to register 0x60, EECtrl[15].

2. Set the I²C OverRide bit to 1. That is, write 1 to register 0x30, speedCtrl[15].

3. Set the motor disable bit to 0. That is, write 0 to register 0x60, EECtrl[15].

4. Provide the value of zero to the speed control register to enter sleep mode. That is, write 0 to register 0x30,

speedCtrl[8:0].

8.3.6 EEPROM Access

The DRV10983-Q1 device has 112 bits (7 registers with 16-bit width) of EEPROM data, which are used to

program the motor parameters as described in the I²C Serial Interface.

The procedure for programming the EEPROM is as follows. TI recommends to perform the EEPROM

programming without the motor spinning, cycle the power after the EEPROM write, and read back the EEPROM

to verify the programming is successful.

1. Power up with any voltage within operating voltage range (6.2 V to 28 V)

2. (DRV10983Q only) Exit from sleep condition

3. Wait 10 ms

4. Write register 0x60 to set MTR_DIS = 1; this disables the motor driver.

5. Write register 0x31 with 0x0000 to clear the EEPROM access code

6. Write register 0x31 with 0xC0DE to enable access to EEPROM

7. Read register 0x32 for eeReadyStatus = 1

8. Case-A: Mass Write

A. Write all individual shadow registers

a. Write register 0x90 (CONFIG1) with CONFIG1 data

b. ...

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c. Write register 0x96 (CONFIG7) with CONFIG7 data

B. Write the following to register 0x35

a. ShadowRegEn = 0

b. eeRefresh = 0

c. eeWRnEn = 1

d. EEPROM Access Mode = 10

C. Wait for register 0x32 eeReadyStatus = 1 – EEPROM is now updated with the contents of the shadow

registers.

9. Case-B: Mass Read

A. Write the following to register 0x35

a. ShadowRegEn = 0

b. eeRefresh = 0

c. eeWRnEn = 0

d. eeAccMode = 10

B. Internally, the device starts reading the EEPROM and storing it in the shadow registers.

C. Wait for register 0x32 eeReadyStatus = 1 – shadow registers now contain the EEPROM values

10. Write register 0x60 to set MTR_DIS = 0; this re-enables the motor driver

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8.4 Device Functional Modes

This section includes the logic required to be able to reliably start and drive the motor. It describes the processes

used in the logic core and provides the information needed to configure the parameters effectively to work over a

wide range of applications.

8.4.1 Motor Parameters

See the DRV10983-Q1 Tuning Guide for the motor parameter measurement.

The motor phase resistance and BEMF constants are two important parameters used to characterize a BLDC

motor. The DRV10983-Q1 device requires these parameters to be configured in the register. The motor phase

resistance is programmed by writing the values for Rm[6:0] (combination of RMShift[2:0] and RMValue[3:0]) in

the Config1 register. The BEMF constant is programmed by writing the values for Kt[6:0] (combination of

KTShift[2:0] and KTValue[3:0]) in the Config2 register.

8.4.1.1 Motor Phase Resistance

For a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the

center tap, R_{PH_CT}(denoted as R_{PH_CT}in Figure 13).

Phase U

R_{PH_CT}

Center

Tap

Phase V

Phase W

Figure 13. Wye-Connected Motor Phase Resistance

For a delta-connected motor, the motor phase resistance refers to the equivalent phase to center tap in the wye

configuration. In Figure 14, it is denoted as R_Y. R_{PH_CT}= R_Y.

For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent R_{PH_CT}is

to measure the resistance between two phase terminals (R_{PH_PH}), and then divide this value by two, R_{PH_CT}= ½

R_{PH_PH}

.

Phase U

R_Y

R

PH_PH

R_Y

Center

Tap

Phase V

R

Phase W

PH_PH

Figure 14. Delta-Connected Motor and the Equivalent Wye Connections

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Device Functional Modes (continued)

The motor phase resistance (R_{PH_CT}) must be converted to a 7-bit digital register value Rm[6:0] to program the

motor phase resistance value. The digital register value can be determined as follows:

1. Convert the motor phase resistance (R_{PH_CT}) to a digital value where the LSB is weighted to represent 9.67

mΩ: Rmdig = R_{PH_CT}/ 0.00967.

2. Encode the digital value such that Rmdig = RMValue[3:0] << RMShift[2:0].

The maximum resistor value, R_{PH_CT}, that can be programmed for the DRV10983-Q1 device is 18.5 Ω, which

represents Rmdig = 1920 and an encoded Rm[6:0] value of 0x7Fh. The minimum resistor the DRV10983-Q1

device supports is 0.029 Ω, R_{PH_CT}, which represents Rmdig = 3.

For convenience, the encoded value for Rm[6:0] can also be obtained from Table 3.

Table 3. Motor Phase Resistance Look-Up Table

RM[6:0] {RMShift[2:0],

RMValue[3:0]}

RM[6:0] {RMShift[2:0],

RMValue[3:0]}

RM[6:0] {RMShift[2:0],

RMValue[3:0]}

R_{PH_CT}(Ω)

BINARY

000 0000

000 0001

000 0010

000 0011

000 0100

000 0101

000 0110

000 0111

000 1000

000 1001

000 1010

000 1011

000 1100

000 1101

000 1110

000 1111

001 1000

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

HEX

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

BINARY

0101000

010 1001

010 1010

010 1011

010 1100

010 1101

010 1110

010 1111

011 1000

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

100 1000

100 1001

100 1010

100 1011

100 1100

100 1101

100 1110

100 1111

HEX

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

BINARY

1011000

101 1001

101 1010

101 1011

101 1100

101 1101

101 1110

101 1111

110 1000

110 1001

110 1010

110 1011

110 1100

110 1101

110 1110

110 1111

111 1000

111 1001

111 1010

111 1011

111 1100

111 1101

111 1110

111 1111

HEX

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0

0.3104

0.3492

0.388

2.4832

2.7936

3.104

0.0097

0.0194

0.0291

0.0388

0.0485

0.0582

0.0679

0.0776

0.0873

0.097

0.4268

0.4656

0.5044

0.5432

0.582

3.4144

3.7248

4.0352

4.3456

4.656

0.6208

0.6984

0.776

4.9664

5.5872

6.208

0.1067

0.1164

0.1261

0.1358

0.1455

0.1552

0.1746

0.194

0.8536

0.9312

1.0088

1.0864

1.164

6.8288

7.4496

8.0704

8.6912

9.312

1.2416

1.3968

1.552

9.9328

11.1744

12.416

13.6576

14.8992

16.1408

17.3824

18.624

0.2134

0.2328

0.2522

0.2716

0.291

1.7072

1.8624

2.0176

2.1728

2.328

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8.4.1.2 BEMF Constant

The BEMF constant, Kt[6:0] describes the phase-to-phase BEMF voltage of the motor as a function of the motor

velocity.

Figure 15 shows the measurement technique for this constant as used in the DRV10983-Q1 device.

PhU

Rm

E_p

Lm

T_e

E_pE_p

=

Eu

Kt =

Ev

1

f_e

Ew

t_e

Lm

Rm

PhV

PhW

Figure 15. Kt_PHDefinition

With the motor coasting, use an oscilloscope to capture the differential voltage waveform between any two

phases. Derive the BEMF constant used by the DRV10983-Q1 device as shown in Equation 1.

Kt_PH= E_p× t_e

where

•

E_pis ½ the peak-to-peak amplitude of the measured voltage

t_eis the electrical period

(1)

The measured BEMF constant (Kt_PH) must be converted to a 7-bit digital register value Kt[6:0] (combination of

KtShift[2:0] and KtValue[3:0]) to program the BEMF constant value. The digital register value can be determined

as follows:

1. Convert the measured Kt_PHto a weighted digital value: Kt_{ph_dig}= 1090 × Kt_PH

2. Encode the digital value such that Kt_{ph_dig}= KtValue[3:0] << KtShift[2:0].

The maximum Kt_PHthat can be programmed is 1760 mV/Hz. This represents a digital value of 1920 and an

encoded Kt[6:0] value of 0x7Fh. The minimum Kt_PHthat can be programmed is 0.92 mV/Hz, which represents a

digital value of 1 and an encoded Kt[6:0] value of 0x01h.

For convenience, the encoded value of Kt[6:0] may also be obtained from Table 4.

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Table 4. BEMF Constant Look-Up Table

Kt[6:0] {KtShift[2:0],

Kt [6:0] {KtShift[2:0],

KtValue[3:0]}

Kt_PH

(mV/Hz)

Kt_PH

(mV/Hz)

Kt_PH

(mV/Hz)

KtValue[3:0]}

BINARY

000 0000

000 0001

000 0010

000 0011

000 0100

000 0101

000 0110

000 0111

000 1000

000 1001

000 1010

000 1011

000 1100

000 1101

000 1110

000 1111

001 1000

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

HEX

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

BINARY

010 1000

010 1001

010 1010

010 1011

010 1100

010 1101

010 1110

010 1111

011 1000

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

100 1000

100 1001

100 1010

100 1011

100 1100

100 1101

100 1110

100 1111

HEX

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

BINARY

101 1000

101 1001

101 1010

101 1011

101 1100

101 1101

101 1110

101 1111

110 1000

110 1001

110 1010

110 1011

110 1100

110 1101

110 1110

110 1111

111 1000

111 1001

111 1010

111 1011

111 1100

111 1101

111 1110

111 1111

HEX

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0

29.44

33.12

36.8

235.52

264.96

294.4

0.92

1.84

2.76

3.68

4.6

40.48

44.16

47.84

51.52

55.2

323.84

353.28

382.72

412.16

441.6

5.52

6.44

7.36

8.28

9.2

58.88

66.24

73.6

471.04

529.92

588.8

10.12

11.04

11.96

12.88

13.8

14.72

16.56

18.4

20.24

22.08

23.92

25.76

27.6

80.96

88.32

95.68

103.04

110.4

117.76

132.48

147.2

161.92

176.64

191.36

206.08

220.8

647.68

706.56

765.44

824.32

883.2

942.08

1059.84

1177.6

1295.36

1413.12

1530.88

1648.64

1766.4

8.4.2 Starting the Motor Under Different Initial Conditions

The motor can be in one of three states when the DRV10983-Q1 device attempts to begin the start-up process.

The motor may be stationary, or spinning in the forward or reverse directions. The DRV10983-Q1 device

includes a number of features to allow for reliable motor start under all of these conditions. Figure 16 shows the

motor start-up flow for each of the three initial motor states.

8.4.2.1 Case 1 – Motor is Stationary

If the motor is stationary, the commutation logic must be initialized to be in phase with the position of the motor.

The DRV10983-Q1 device provides for two options to initialize the commutation logic to the motor position. Initial

position detect (IPD) determines the position of the motor based on the deterministic inductance variation, which

is often present in BLDC motors. The align-and-go technique forces the motor into alignment by applying a

voltage across a particular motor phase to force the motor to rotate in alignment with this phase.

8.4.2.2 Case 2 – Motor is Spinning in the Forward Direction

If the motor is spinning forward with enough velocity, the DRV10983-Q1 device may be configured to go directly

into closed loop. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time

for this initial condition.

8.4.2.3 Case 3 – Motor is Spinning in the Reverse Direction

If the motor is spinning in the reverse direction, the DRV10983-Q1 device provides several methods to convert it

back to the forward direction.

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One method, reverse drive, allows the motor to be driven so that it accelerates through zero velocity. The motor

achieves the shortest possible spin-up time in systems where the motor is spinning in the reverse direction.

If this feature is not selected, then the DRV10983-Q1 device may be configured either to wait for the motor to

stop spinning or to brake the motor. After the motor has stopped spinning, the motor start-up sequence proceeds

as it would for a motor which is stationary.

Take care when using the reverse-drive or brake feature to ensure that the current is limited to an acceptable

level and that the supply voltage does not surge as a result of energy being returned to the power supply.

IPD

Stationary

Align and Go

Spinning forward

Spinning reversely

Direct closed loop

Wait

Brake

Reverse drive

Figure 16. Start the Motor Under Different Initial Conditions

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8.4.3 Motor Start Sequence

Figure 17 shows the motor-start sequence implemented in the DRV10983-Q1 device.

Power on

DIR pin

change

N

ISDen

Y

ISD

Speed <

ISDThr

Y

N

Forward

N

Y

Speed >

RvsDrThr

Y

N

BrkEn

Y

N

Brake

N

RvsDrEn

Y

IPDEn

Y

Time >

BrkDoneThr

N

Y

N

Align

IPD

RvsDr

Accelerate

Speed >

Op2CIsThr

N

Y

ClosedLoop

Figure 17. Motor Starting-Up Flow

Power-On State This is the initial power-on state of the motor start sequencer (MSS). The MSS starts in this

state on initial power-up or whenever the DRV10983-Q1 device comes out of either standby or

sleep mode.

ISDen Judgment After power-on, the DRV10983-Q1 MSS enters the ISDen judgment where it checks to see if

the initial speed detect (ISD) function is enabled (ISDen = 1). If ISD is disabled, the MSS proceeds

directly to the BrkEn Judgment. If ISD is enabled, the motor start sequence advances to the ISD

state.

ISD State

The MSS determines the initial condition of the motor (see Initial Speed Detect).

Speed<ISDThr Judgment If the motor speed is lower than the threshold defined by ISDThr[1:0], then the motor

is considered to be stationary and the MSS proceeds to the BrkEn judgment. If the speed is greater

than the threshold defined by ISDThr[1:0], the start sequence proceeds to the Forward judgment.

Forward Judgment The MSS determines whether the motor is spinning in the forward or the reverse direction.

If the motor is spinning in the forward direction, the DRV10983-Q1 device executes the

resynchronization (see Motor Resynchronization) process by transitioning directly into the

ClosedLoop state. If the motor is spinning in the reverse direction, the MSS proceeds to the

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Speed>RvsDrThr.

Speed>RvsDrThr Judgment The motor start sequencer checks to see if the reverse speed is greater than the

threshold defined by RvsDrThr[1:0]. If it is, then the MSS returns to the ISD state to allow the motor

to decelerate. This prevents the DRV10983-Q1 device from attempting to reverse drive or brake a

motor that is spinning too quickly. If the reverse speed of the motor is less than the threshold

defined by RvsDrThr[1:0], then the MSS advances to the RvsDrEn judgment.

RvsDrEn Judgment The MSS checks to see if the reverse drive function is enabled (RvsDrEn = 1). If it is, the

MSS transitions into the RvsDr state. If the reverse drive function is not enabled, the MSS

advances to the BrkEn judgment.

RvsDr State The DRV10983-Q1 device drives the motor in the forward direction to force it to rapidly decelerate

(see Reverse Drive). When it reaches zero velocity, the MSS transitions to the Accelerate state.

BrkEn Judgment The MSS checks to determine whether the brake function is enabled (BrkDoneThr[2:0] ≠ 000).

If the brake function is enabled, the MSS advances to the brake state.

Brake State The device performs the brake function (see Motor Brake).

Time>BrkDoneThr Judgment The MSS applies brake for a time configured by BRKDoneThr[2:0]. After brake

state, the MSS advances to the IPDEn judgment.

IPDEn Judgment The MSS checks to see if IPD has been enabled (IPDCurrThr[3:0] ≠ 0000). If the IPD is

enabled, the MSS transitions to the IPD state. Otherwise, it transitions to the align state.

Align State The DRV10983-Q1 device performs the align function (see Align). After the align completes, the

MSS transitions to the Accelerate state.

IPD State

The DRV10983-Q1 device performs the IPD function. The IPD function is described in Initial

Position Detect (IPD). After the IPD completes, the MSS transitions to the accelerate state.

Accelerate State The DRV10983-Q1 device accelerates the motor according to the settings of StAccel and

StAccel2. After applying the accelerate settings, the MSS advances to the Speed>Op2ClsThr

judgment.

Speed>Op2ClsThr Judgment The motor accelerates until the drive rate exceeds the threshold configured by

the Op2ClsThr[4:0] settings. When this threshold is reached, the DRV10983-Q1 device enters into

the ClosedLoop state.

ClosedLoop State In this state, the DRV10983-Q1 device drives the motor based on feedback from the

commutation control algorithm.

DIR Pin Change Judgment If the DIR pin is changed during any of above states, DRV10983-Q1 device stops

driving the motor and restarts from the beginning.

8.4.3.1 Initial Speed Detect

The ISD function is used to identify the initial condition of the motor. If the function is disabled, the DRV10983-Q1

device does not perform the initial speed detect function and treats the motor as if it is stationary.

Phase-to-phase comparators are used to detect the zero crossings of the motor’s BEMF voltage while it is

coasting (motor phase outputs are in the high-impedance state). Figure 18 shows the configuration of the

comparators.

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degrees

60

V

+

U

W

Figure 18. Initial Speed Detect Function

If the UW comparator output is lagging the UV comparator by 60°, the motor is spinning forward. If the UW

comparator output is leading the UV comparator by 60°, the motor is spinning in reverse.

The motor speed is determined by measuring the time between two rising edges of either of the comparators.

If neither of the comparator outputs toggles for a given amount of time, the condition is defined as stationary. The

amount of time can be programmed by setting the register bits ISDThr[1:0].

8.4.3.2 Motor Resynchronization

The resynchronize function works when the ISD function is enabled and determines that the initial state of the

motor is spinning in the forward direction. The speed and position information measured during ISD are used to

initialize the drive state of the DRV10983-Q1 device, which can transition directly into the closed-loop running

state without needing to stop the motor.

8.4.3.3 Reverse Drive

The ISD function measures the initial speed and the initial position; the DRV10983-Q1 reverse drive function acts

to reverse accelerate the motor through zero speed and to continue accelerating until the closed loop threshold is

reached (see Figure 19). If the reverse speed is greater than the threshold configured in RvsDrThr[1:0], then the

DRV10983-Q1 device waits until the motor coasts to a speed that is less than the threshold before driving the

motor to reverse accelerate.

Speed

Closed loop

Op2ClsThr

Open loop

Time

RevDrThr

Reverse Drive

Coasting

Figure 19. Reverse Drive Function

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Reverse drive is suitable for applications where the load condition is light at low speed and relatively constant

and where the reverse speed is low (that is, a fan motor with little friction). For other load conditions, the motor

brake function provides a method for helping force a motor which is spinning in the reverse direction to stop

spinning before a normal start-up sequence.

8.4.3.4 Motor Brake

The motor brake function can be used to stop the spinning motor before attempting to start the motor. The brake

is applied by turning on all three of the low-side driver FETs.

Brake is enabled by configuring a non-zero BrkDoneThr[2:0]. Brake is applied for a time configured by

BrkDoneThr[2:0] (forward or reverse). After the motor is stopped, the motor position is unknown. To proceed with

restarting in the correct direction, the IPD or align-and-go algorithm must be implemented. The motor start

sequence is the same as it would be for a motor starting in the stationary condition.

The motor brake function can be disabled. The motor skips the brake state and attempts to spin the motor as if it

were stationary. If this happens while the motor is spinning in either direction, the start-up sequence may not be

successful.

8.4.3.5 Motor Initialization

8.4.3.5.1 Align

The DRV10983-Q1 device aligns a motor by injecting dc current through a particular phase pattern which is

current flowing into phase V, flowing out from phase W for a certain time (configured by AlignTime[2:0]). The

current magnitude is determined by OpenLCurr[1:0]. The motor should be aligned at the known position.

The time of align affects the start-up timing (see Start-Up Timing). A bigger-inertia motor requires longer align

time.

8.4.3.5.2 Initial Position Detect (IPD)

The inductive sense method is used to determine the initial position of the motor when IPD is enabled. IPD is

enabled by selecting IPDCurrThr[3:0] to any value other than 0000.

IPD can be used in applications where reverse rotation of the motor is unacceptable. Because IPD is not

required to wait for the motor to align with the commutation, it can allow for a faster motor start sequence. IPD

works well when the inductance of the motor varies as a function of position. Because it works by pulsing current

to the motor, it can generate acoustics which must be taken into account when determining the best start method

for a particular application.

8.4.3.5.2.1 IPD Operation

The IPD operates by sequentially applying voltage across two of the three motor phases according to the

following sequence: VW WV UV VU WU UW (see Figure 20). When the current reaches the threshold configured

in IPDCurrThr[3:0], the voltage across the motor is stopped. The DRV10983-Q1 device measures the time it

takes from when the voltage is applied until the current threshold is reached. The time varies as a function of the

inductance in the motor windings. The state with the shortest time represents the state with the minimum

inductance. The minimum inductance is because of the alignment of the north pole of the motor with this

particular driving state.

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U

V

N

IPDclk

Clock

S

W

Drive

V W

W V

U V

V U

W U

U W

IPDCurrThr

Current

Search the Minimum Time

Permanent

Magnet Position

Saturation Position of the

Magnetic Field

Smallest

Inductance

Minimum

Time

Figure 20. IPD Function

8.4.3.5.2.2 IPD Release Mode

Two options are available for stopping the voltage applied to the motor when the current threshold is reached. If

IPDRlsMd = 0, the recirculate mode is selected. The low-side (S6) MOSFET remains on to allow the current to

recirculate between the MOSFET (S6) and body diode (S2) (see Figure 21). If IPDRlsMd = 1, the high-

impedance (Hi-Z) mode is selected. Both the high-side (S1) and low-side (S6) MOSFETs are turned off and the

current flies back across the body diodes into the power supply (see Figure 22).

In the high-impedance state, the phase current has a faster settle-down time, but that could result in a surge on

V_CC. Manage this with appropriate selection of either a clamp circuit or by providing sufficient capacitance

between V_CCand GND. If the voltage surge cannot be contained and if it is unacceptable for the application, then

select the recirculate mode. When selecting the recirculate mode, select the IPDClk[1:0] bits to give the current in

the motor windings enough time to decay to 0.

S1

S3

S5

S1

S3

S5

M

U1

S2

S4

S6

S4

S6

Driving

Brake (Recirculate)

Figure 21. IPD Release Mode 0

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S1

S3

S4

S5

S6

S1

S3

S4

S5

S6

M

U1

S2

Driving

Hi-Z (Tri-State)

Figure 22. IPD Release Mode 1

8.4.3.5.2.3 IPD Advance Angle

After the initial position is detected, the DRV10983-Q1 device begins driving the motor at an angle specified by

IPDAdvcAgl[1:0].

Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by 90°

results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the rotor.

Select the IPDAdvcAgl[1:0] to allow for smooth acceleration in the application (see Figure 23).

Motor spinning direction

U

V

N

S

W

U

V

U

V

U

V

U

V

N

S

W

30˘ advance

60˘ advance

90˘ advance

120˘ advance

Figure 23. IPD Advance Angle

8.4.3.5.3 Motor Start

After it is determined that the motor is stationary and after completing the motor initialization with either align or

IPD, the DRV10983-Q1 device begins to accelerate the motor. This acceleration is accomplished by applying a

voltage determined by the open-loop current setting (OpenLCurr[1:0]) to the appropriate drive state and by

increasing the rate of commutation without regard to the real position of the motor (referred to as open-loop

operation). The function of the open-loop operation is to drive the motor to a minimum speed so that the motor

generates sufficient BEMF to allow the commutation control logic to accurately drive the motor.

Table 5 lists the configuration options that can be set in register to optimize the initial motor acceleration stage

for different applications.

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Table 5. Configuration Options for Controlling Open-Loop Motor Start

CONFIGURATION

BITS

DESCRIPTION

REG. NAME

MIN. VALUE

MAX. VALUE

Open- to closed-loop threshold

Align time

CONFIG4

Op2ClsThr[4:0]

AlignTime[2:0]

StAccel[2:0]

0.8 Hz

40 ms

204.8 Hz

5.3 s

First-order accelerate

Second-order accelerate

Open-loop current setting

Align current setting

0.019 Hz/s

0.0026 Hz/s²

200 mA

76 Hz/s

57 Hz/s²

1.6 A

StAccel2[2:0]

CONFIG3

OpenLCurr[1:0]

OpLCurrRt[2:0]

150 mA

1.2 A

Open-loop current ramping

0.023 V_CC/s

6 V_CC/s

8.4.3.6 Start-Up Timing

Start-up timing is determined by the align and accelerate time. The align time can be set by AlignTime[2:0]. The

accelerate time is defined by the open-to-closed loop threshold Op2ClsThr[4:0] along with the first-order

StAccel[2:0](A1) and second-order StAccel2[2:0](A2) acceleration coefficients. Figure 24 shows the motor start-

up process.

Speed

Speed =

Close loop

A1 ´ t + 0.5 A2 ´ t²

Op2ClsThr

AlignTime

Accelerate Time is determined by

Op2ClsThr and A1, A2.

Time

Accelerate Time

Figure 24. Motor Start-Up Process

Select the first-order and second-order acceleration coefficients to allow the motor to reliably accelerate from

zero velocity up to the closed-loop threshold in the shortest time possible. Using a slow acceleration coefficient

during the first order accelerate stage can help improve reliability in applications where it is difficult to accurately

initialize the motor with either align or IPD.

Select the open-to-closed loop threshold to allow the motor to accelerate to a speed that generates sufficient

BEMF for closed-loop control. This is determined by the velocity constant of the motor based on the relationship

described in Equation 2.

BEMF = Kt_PH× speed (Hz)

(2)

8.4.4 Align Current

During the align state, the measured align current is dependent on actual motor phase resistance and r_DS(on)of

the internal FETs. The relationship between measured align current and configured align current is derived from

actual motor phase resistance, configured motor phase resistance and r_DS(on)

.

é

ê

ë

ù

R_m

AlignCurrent _Measured = AlignCurrent _Configured´

ú

R

+ r

ê

ú

^DS(on)û

motor

where

•

AlignCurrent_Measured is the actual align current measured during the align state

AlignCurrent_Configured is the align current configured by OpenLCurr[1:0]

R_motoris the actual motor phase resistance

r_DS(on)is the resistance between the drain and source of the FETs during the on-state

R_mis configured by Rm[6:0]

(3)

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8.4.5 Start-Up Current Setting

The start-up current setting is to control the peak start-up during open loop. During open-loop operation, it is

desirable to control the magnitude of drive current applied to the motor. This is helpful in controlling and

optimizing the rate of acceleration. The limit takes effect during reverse drive, align, and acceleration.

The start current is set by programming the OpenLCurr[1:0] bits. The current should be selected to allow the

motor to reliably accelerate to the handoff threshold. Heavier loads may require a higher current setting, but it

should be noted that the rate of acceleration is limited by the acceleration rate (StAccel[2:0], StAccel2[2:0]). If the

motor is started with more current than necessary to reliably reach the handoff threshold, it results in higher

power consumption.

The start current is controlled based on the relationship shown in Equation 4 and Figure 25. The duty cycle

applied to the motor is derived from the calculated value for U_Limitand the magnitude of the supply voltage, V_CC

as well as the drive state of the motor.

,

U_Limit= I_Limitì Rm + Speed Hz ì Kt

(

)

where

•

I_Limitis configured by OpenLCurr[1:0]

Rm is configured by Rm[6:0]

Speed is variable based motor’s open loop acceleration profile

Kt is configured by Kt[6:0]

(4)

Rm

BEMF = Kt × speed

M

V_U= BEMF + I× Rm

Figure 25. Motor Start-Up Current

8.4.5.1 Start-Up Current Ramp-Up

A fast change in the applied drive current may result in a sudden change in the driving torque. In some

applications, this could result in acoustic noise. To avoid this, the DRV10983-Q1 device allows the option of

limiting the rate at which the current is applied to the motor. OpLCurrRt[2:0] sets the maximum voltage ramp-up

rate that is applied to the motor. The waveforms in Figure 26 show how this feature can be used to gradually

ramp the current applied to the motor.

Start driving with fast current ramp

Start driving with slow current ramp

Figure 26. Motor Start-Up Current Ramp

8.4.6 Closed Loop

In closed loop operation, the DRV10983-Q1 device continuously samples the current in the U phase of the motor

and uses this information to estimate the BEMF voltage that is present. The drive state of the motor is controlled

based on the estimated BEMF voltage.

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8.4.6.1 Half-Cycle Control and Full-Cycle Control

The estimated BEMF used to control the drive state of the motor has two zero-crosses every electrical cycle. The

DRV10983-Q1 device can be configured to update the drive state either once every electrical cycle or twice for

every electrical cycle. When AdjMode is programmed to 1, half-cycle adjustment is applied. The control logic is

triggered at both the rising edge and falling edge. When AdjMode is programmed to 0, full-cycle adjustment is

applied. The control logic is triggered only at the rising edge (see Figure 27).

Half-cycle adjustment provides a faster response when compared with full-cycle adjustment. Use half-cycle

adjustment whenever the application requires operation over large dynamic loading conditions. Use the full-cycle

adjustment for low-current (<1 A) applications because it offers more tolerance for current-measurement offset

errors.

Zero cross signal

Estimated Position

Real Driving Voltage

Real Position

Ideal Driving Voltage

Estimated Position

Real Driving Voltage

Real Position

Ideal Driving Voltage

Adjustment (full cycle)

Adjustment (half cycle)

Figure 27. Closed-Loop Control Commutation-Adjustment Mode

8.4.6.2 Analog-Mode Speed Control

The SPEED input pin can be configured to operate as an analog input (SpdCtrlMd = 0).

When configured for analog mode, the voltage range on the SPEED pin can be varied from 0 to V3P3. If

SPEED > V_{ANA_FS}, the speed command is maximum. If V_{ANA_ZS}≤ SPEED < V_{ANA_FS}the speed command

changes linearly according to the magnitude of the voltage applied at the SPEED pin. If SPEED < V_{ANA_ZS}the

speed command is to stop the motor. Figure 28 shows the speed command when operating in analog mode.

Speed

Command

Maximum

Speed

Command

Analog Input

V_ANA-ZS

V_ANA-FS

Figure 28. Analog-Mode Speed Command

8.4.6.3 Digital PWM-Input-Mode Speed Control

If SpdCtrlMd = 1, the SPEED input pin is configured to operate as a PWM-encoded digital input. The PWM duty

cycle applied to the SPEED pin can be varied from 0 to 100%. The speed command is proportional to the PWM

input duty cycle. The speed command stops the motor when the PWM input keeps at 0 for t_{EN_SL_SB}(see

Figure 29).

The frequency of the PWM input signal applied to the SPEED pin is defined as f_PWM. This is the frequency the

device can accept to control motor speed. It does not correspond to the PWM output frequency that is applied to

the motor phase. The PWM output frequency can be configured to be either 25 kHz when the PWMFreq bit is set

to 0 or to 50 kHz when PWMFreq bit is set to 1.

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Speed

Command

Maximum

Speed

Command

PWM duty

0

100%

Figure 29. PWM-Mode Speed Command

8.4.6.4 I²C-Mode Speed Control

The DRV10983-Q1 device can also command the speed through the I²C serial interface. To enable this feature,

the OverRide bit is set to 1. When the DRV10983-Q1 device is configured to operate in I²C mode, it ignores the

signal applied to the SPEED pin.

The speed command can be set by writing the SpdCtrl[8:0] bits. The 9-bit SpdCtrl [8:0] located in the SpeedCtrl

registers is used to set the peak amplitude voltage applied to the motor. The maximum speed command is set

when SpdCtrl [8:0] is set to 0x1FF (511).

8.4.6.5 Closed-Loop Accelerate

To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the

DRV10983-Q1 device provides the option of limiting the maximum rate at which the speed command changes.

ClsLpAccel[2:0] can be programmed to set the maximum rate at which the speed command changes (shown in

Figure 30).

y%

Speed command

input

x%

y%

Speed command

after closed loop

accelerate buffer

x%

Closed loop

accelerate settings

Figure 30. Closed Loop Accelerate

8.4.6.6 Control Coefficient

The DRV10983-Q1 device continuously measures the motor current and uses this information to control the drive

state of the motor when operating in closed-loop mode. In applications where noise makes it difficult to control

the commutation optimally, the CtrlCoef[1:0] can be used to attenuate the feedback used for closed-loop control.

The loop is less reactive to the noise on the feedback and provides for a smoother output.

8.4.6.7 Commutation Control Advance Angle

To achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor phase

current is aligned with the motor BEMF voltage.

To align the motor phase current with the motor BEMF voltage, consider the inductive effect of the motor. The

voltage applied to the motor should be applied in advance of the motor BEMF voltage (see Figure 31). The

DRV10983-Q1 device provides configuration bits for controlling the time (t_adv) between the driving voltage and

BEMF.

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For motors with salient pole structures, aligning the motor BEMF voltage with the motor current may not achieve

the best efficiency. In these applications, the timing advance should be adjusted accordingly. Accomplish this by

operating the system at constant speed and load conditions and by adjusting t_advuntil the minimum current is

achieved.

Phase

Voltage

Phase

BEMF

Phase

Current

t_adv

Figure 31. Advance Time (t_adv) Definition

The DRV10983-Q1 device has two options for adjusting the motor commutate advance time. When

CommAdvMode = 0, mode 0 is selected. When CommAdvMode = 1, mode 1 is selected.

Mode 0: t_advis maintained to be a fixed time relative to the estimated BEMF zero cross as determined by

Equation 5.

t_adv= t_SETTING

(5)

Mode 1: t_advis maintained to be a variable time relative to the estimated BEMF zero cross as determined by

Equation 6.

t_adv= t_SETTING× (U - BEMF) / U.

where

•

U is the phase voltage amplitude

BEMF is phase BEMF amplitude

(6)

t_SETTING(in µs) is determined by the configuration of the TCtrlAdvShift [2:0] and TCtrlAdvValue [3:0] bits as

defined in Equation 7. For convenience, the available t_SETTINGvalues are provided in Table 6.

t_SETTING= 2.5 µs × [TCtrlAdvValue[3:0]] << TCtrlAdvShift[2:0]

(7)

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Table 6. Configuring Commutation Advance Timing by Adjusting t_SETTING

TCtrlAdv [6:0]

{TCtrlAdvShift[2:0],

TCtrlAdvValue[3:0]}

{TCtrlAdvShift[2:0],

TCtrlAdvValue[3:0]}

{TCtrlAdvShift[2:0],

TCtrlAdvValue[3:0]}

t_SETTING(µs)

Binary

Hex

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Binary

Hex

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

Binary

Hex

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

000 0000

000 0001

000 0010

000 0011

000 0100

000 0101

000 0110

000 0111

000 1000

000 1001

000 1010

000 1011

000 1100

000 1101

000 1110

000 1111

001 1000

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

0.0

2.5

5

010 1000

010 1001

010 1010

010 1011

010 1100

010 1101

010 1110

010 1111

011 1000

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

100 1000

100 1001

100 1010

100 1011

100 1100

100 1101

100 1110

100 1111

80

101 1000

101 1001

101 1010

101 1011

101 1100

101 1101

101 1110

101 1111

110 1000

110 1001

110 1010

110 1011

110 1100

110 1101

110 1110

110 1111

111 1000

111 1001

111 1010

111 1011

111 1100

111 1101

111 1110

111 1111

640

720

90

100

110

120

130

140

150

160

170

200

220

240

260

280

300

320

360

400

440

480

520

560

600

800

7.5

10

880

960

12.5

15

1040

1120

1200

1280

1440

1600

1760

1920

2080

2240

2400

2560

2880

3200

3520

3840

4160

4480

4800

17.5

20

22.5

25

27.5

30

32.5

35

37.5

40

45

50

55

60

65

70

75

8.4.7 Current Limit

The DRV10983-Q1 device has several current-limit modes to help ensure optimal control of the motor and to

ensure safe operation. The various current-limit modes are listed in Table 7. Acceleration current limit is used to

provide a means of controlling the amount of current delivered to the motor. This is useful when the system

needs to limit the amount of current pulled from the power supply during motor start-up. The lock-detection

current limit is a configurable threshold that can be used to limit the current applied to the motor. Overcurrent

protection is used to protect the device; therefore, it cannot be disabled or configured to a different threshold.

The current-limit modes are described in the following sections.

Table 7. DRV10983-Q1 Current-Limit Modes

CURRENT LIMIT MODE

Acceleration current limit

Lock-detection current limit

Overcurrent Protection

SITUATION

Motor start

ACTION

FAULT DIAGNOSIS

No fault

Limit the output voltage amplitude

Motor locked

Short circuit

Stop driving the motor and enter the lock state

Mechanical rotation error

Circuit connection

8.4.7.1 Acceleration Current Limit

The acceleration current limit limits the voltage applied to the motor to prevent the current from exceeding the

programmed threshold. The acceleration current limit threshold is configured by writing the SWiLimitThr[3:0] bits

to select I_LIMIT. The acceleration current limit does not use a direct measurement of current. It uses the

programmed motor phase resistance, R_{PH_CT}, and programmed BEMF constant, Kt, to limit the voltage applied to

the motor, U, as shown in Figure 32 and Equation 8.

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When the acceleration current limit is active, it does not stop the motor from spinning nor does it trigger a fault.

The functionality of the acceleration current limit is only available in closed-loop control.

Rm

I_LIMIT

BEMF = Kt ´ Speed

M

V_{U_LIMIT}

Figure 32. Acceleration Current Limit

U_LIMIT= I_LIMIT× R_{PH_CT}+ Speed × Kt

(8)

8.4.8 Lock Detect and Fault Handling

The DRV10983-Q1 device provides several options for determining if the motor becomes locked as a result of

some external torque. Five lock-detect schemes work together to ensure the lock condition is detected quickly

and reliably. Figure 33 shows the logic which integrates the various lock-detect schemes. When a lock condition

is detected, the DRV10983-Q1 device takes action to prevent continuously driving the motor in order to prevent

damage to the system or the motor.

In addition to detecting if there is a locked motor condition, the DRV10983-Q1 device also identifies and takes

action if there is no motor connected to the system.

Each of the five lock-detect schemes and the no-motor detection can be disabled by respective register bits

LockEn[5:0].

When a lock condition is detected, the FaultReg register provides an indication of which of the six different

conditions was detected on Lock5 to Lock0. These bits are reset when the motor restarts. The bits in the

FaultReg register are set even if the lock detect scheme is disabled.

The DRV10983-Q1 device reacts to either locked-rotor or no-motor-connected conditions by putting the output

drivers into a high-impedance state. To prevent the energy in the motor from pumping the supply voltage, the

DRV10983-Q1 device incorporates an anti-voltage-surge (AVS) process whenever the output stages transition

into the high-impedance state. The AVS function is described in Anti Voltage Suppression Function. After

entering the high-impedance state as a result of a fault condition, the system tries to restart after t_{LOCK_OFF}

.

LockEn(0, 1, 2, 3, 4, 5)

Lock-Detection Current Limit

Speed Abnormal

BEMF Abnormal

Hi-Z

OR

and Restart

Logic

No-Motor Fault

Open-Loop Stuck

Closed-Loop Stuck

Reset

Register:

FaultCode[5:0]

Set

Figure 33. Lock Detect and Fault Diagnose

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8.4.8.1 Lock0: Lock-Detection Current Limit Triggered

The lock-detection current-limit function provides a configurable threshold for limiting the current to prevent

damage to the system. This is often tripped in the event of a sudden locked-rotor condition. The DRV10983-Q1

device continuously monitors the current in the low-side drivers as shown in Figure 34. If the current goes higher

than the threshold configured by the HWiLimitThr[2:0] bits, then the DRV10983-Q1 device stops driving the

motor by placing the output phases into a high-impedance state. The Lock0 bit is set and a lock condition is

reported. It retries after t_{LOCK_OFF}

.

Set the lock-detection current limit to a higher value than the acceleration current limit.

+

DigitalCore

–

DAC

Figure 34. Lock-Detection Current Limit

8.4.8.2 Lock1: Abnormal Speed

If the motor is operating normally, the motor BEMF should always be less than the output amplitude. The

DRV10983-Q1 device uses two methods of monitoring the BEMF in the system. The U phase current is

monitored to maintain an estimate of BEMF based on the setting for Rm[6:0] {RmShift[2:0],RmValue[3:0]}. In

addition, the BEMF is estimated based on the operation speed of the motor and the setting for Kt[6:0]

{KtShift[2:0],KtValue[3:0]}. Figure 35 shows the method for using this information to detect a lock condition. If the

motor BEMF is much higher than the output amplitude for a certain period of time, t_{LCK_ETR}, it means the

estimated speed is wrong, and the motor has gotten out of phase.

Rm

BEMF1 = V_U– I× Rm

BEMF2 =Kt × Speed

I

M

V_U

Lock Detected If BEMF2 > V_U

Figure 35. Lock Detection 1

8.4.8.3 Lock2: Abnormal Kt

For any given motor, the integrated value of BEMF during half of an electrical cycle is constant. The value is

determined by the BEMF constant (Kt_PH) (see Figure 36). The BEMF constant is the same regardless of whether

the motor is running fast or slow. This constant value is continuously monitored by calculation and used as a

criterion to determine the motor lock condition, and is referred to as Ktc.

Based on the Kt_PHvalue programmed, create a range from Kt_low to Kt_high. If Ktc goes beyond the range for a

certain period of time, t_{LCK_ETR}, lock is detected. Kt_low and Kt_high are determined by KtLckThr[1:0] (see

Figure 37).

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Figure 36. BEMF Integration

Kt_high

Ktc

Kt

Kt_low

Lock detect

Figure 37. Abnormal-Kt Lock Detect

8.4.8.4 Lock3 (Fault3): No-Motor Fault

The phase U current is checked after transitioning from open loop to closed loop. If phase U current is not

greater than 140 mA then the motor is not connected as shown in Figure 38. This condition is treated and

reported as a fault.

DRV10983-Q1

M

Figure 38. No Motor Error

8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock

Lock4 is used to detect locked-motor conditions while the motor start sequence is in open loop.

For a successful startup, motor speed should be equal to the open-to-closed-loop handoff threshold when the

motor is transitioning into closed loop. However, if the motor is locked, the motor speed is not able to match the

open-loop drive rate.

If the motor BEMF is not detected for one electrical cycle after the open-loop drive rate exceeds the threshold,

then the open loop was unsuccessful as a result of a locked-rotor condition.

8.4.8.6 Lock5: Closed Loop Motor Stuck Lock

If the motor suddenly becomes locked, motor speed and Ktc are not able to be refreshed because the BEMF

zero cross of the motor may not appear after the lock. In this condition, lock can also be detected by the

following scheme: if the current commutation period is 2× longer than the previous period.

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8.4.9 Anti Voltage Suppression Function

When a motor is driven, energy is transferred from the power supply into the motor. Some of this energy is

stored in the form of inductive energy or as mechanical energy. The DRV10983-Q1 device includes circuits to

prevent this energy from being returned to the power supply, which could result in pumping up the V_CCvoltage.

This function is referred to as the AVS and acts to protect the DRV10983-Q1 device as well as other circuits that

share the same V_CCconnection. Two forms of AVS protection are used to prevent both the mechanical energy

and the inductive energy from being returned to the supply. Each of these modes can be independently disabled

through the register configuration bits AVSMEn and AVSIndEn.

8.4.9.1 Mechanical AVS Function

If the speed command suddenly drops such that the BEMF voltage generated by the motor is greater than the

voltage that is applied to the motor, then the mechanical energy of the motor is returned to the power supply and

the V_CCvoltage surges. The mechanical AVS function works to prevent this from happening. The DRV10983-Q1

device buffers the speed command value and limits the resulting output voltage, U_MIN, so that it is not less than

the BEMF voltage of the motor. The BEMF voltage in the mechanical AVS function is determined using the

programmed value for the motor Kt (Kt[6:0]) along with the speed. Figure 39 shows the criteria used by the

mechanical AVS function.

Rm

I_MIN= 0

BEMF

M

V_U

V_{U_MIN}= BEMF + I_MIN´ Rm = BEMF

Figure 39. Mechanical AVS

The mechanical AVS function can operate in one of two modes, which can be configured by the register bit

AVSMMd:

AVSMMd = 0 – AVS mode is always active to prevent the applied voltage from being less than the BEMF

voltage.

AVSMMd = 1 – AVS mode becomes active when V_CCreaches 24 V. The motor acts as a generator and returns

energy into the power supply until V_CCreaches 24 V. This mode can be used to enable faster deceleration of the

motor in applications where returning energy to the power supply is allowed.

8.4.9.2 Inductive AVS Function

When the DRV10983-Q1 device transitions from driving the motor into a high-impedance state, the inductive

current in the motor windings continues to flow and the energy returns to the power supply through the intrinsic

body diodes in the FET output stage (see Figure 40).

S1

S3

S4

S5

S6

S1

S3

S4

S5

S6

M

V_CC

S2

V_CC

S2

Driving State

High-Impedance State

Figure 40. Inductive-Mode Voltage Surge

To prevent the inductive energy from being returned to the power supply, the DRV10983-Q1 system transitions

from driving to a high-impedance state by first turning OFF the active high-side drivers, and turning ON all low-

side drivers. The DRV10983-Q1 device monitors phase current after entering the BRAKE state and transitions

into the high-impedance state when the amplitude of the phase current is less than BrkCurThrSel for a fixed

period of time (BrkDoneThr[2:0])(see Figure 41).

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S1

S3

S5

S6

S1

S3

S4

S5

S6

M

V_CC

S2

V_CC

S2

S4

Driving

AVS State

Figure 41. Inductive AVS

In this example, current is applied to the motor through the high-side driver on phase U (S1) and returned

through the low-side driver on phase W (S6). The high-side driver on phase U is turned off and after a period of

time (to allow the inductive energy in the resulting LR circuit to decay) the low-side driver on phase W is turned

off. If BrkDoneThr[2:0] = 000, no brake will be applied and the device will not protect from inductive energy even

with the inductive AVS feature enabled.

8.4.10 PWM Output

The DRV10983-Q1 device has 32 options for PWM dead time. These options can be used to configure the time

between one of the bridge FETs turning off and the complementary FET turning on. Deadtime[4:0] can be used

to configure dead times between 40 and 1280 ns. Take care that the dead time is long enough to prevent the

bridge FETs from shooting through.

The DRV10983-Q1 device offers two options for PWM switching frequency. When the configuration bit PWMFreq

is set to 0, the output PWM frequency is 25 kHz, and when PWMFreq is set to 1, the output PWM frequency is

50 kHz.

8.4.11 FG Customized Configuration

The DRV10983-Q1 device provides information about the motor speed through the frequency generate (FG) pin.

FG also provides information about the driving state of the DRV10983-Q1 device.

8.4.11.1 FG Output Frequency

The FG output frequency can be configured by FGcycle[3:0]. The default FG toggles once every electrical cycle

(FGcycle = 0000). Many applications configure the FG output so that it provides two pulses for every mechanical

rotation of the motor. The configuration bits provided in the DRV10983-Q1 device can accomplish this for 2-pole,

4-pole, 6-pole, and 8-pole motors up to 32-pole motors. This is illustrated in Figure 42 for 2, 4, 6, and 8-pole

motors.

Figure 42 shows the DRV10983-Q1 device has been configured to provide FG pulses once every electrical cycle

(4 poles), twice every three electrical cycles (6 poles), once every two electrical cycles (8 poles), and once every

three electrical cycles (12 poles).

Note that when it is set to two FG pulses every three electrical cycles, the FG output is not 50% duty cycle. Motor

speed is able to be measured by monitoring the rising edge of the FG output.

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Motor phase

driving voltage

FGCycle = 0000

2 pole

FGCycle = 0001

4 pole

FGCycle = 0010

6 pole

FGCycle = 0011

8 pole

Figure 42. FG Frequency Divider

8.4.11.2 FG Open Loop and Lock Behavior

Note that the FG output reflects the driving state of the motor. During normal closed-loop behavior, the driving

state and the actual state of the motor are synchronized. During open-loop acceleration, however, this may not

reflect the actual motor speed. During a locked-motor condition, the FG output is driven high.

The DRV10983-Q1 device provides three options for controlling the FG output during open loop, as shown in

Figure 43. The selection of these options is determined by the FGOLSel[1:0] setting.

•

Option0: Open-loop, FG output based on driving frequency

Option1: Open-loop, no FG output (keep high)

Option2: FG output based on driving frequency at the first power-on startup, and no FG output (keep high) for

any subsequent restarts

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Open loop

Closed loop

Motor phase

driving voltage

FGOLset= 00

FGOLset =01

Open loop

Closed loop

Open loop

Closed loop

Motor phase

driving voltage

FGOLset =10

Start-up after power-on or wake

up from sleep/standby mode

Rest of the startups

Figure 43. FG Behavior During Open Loop

8.4.12 Diagnostics and Visibility

The DRV10983-Q1 device offers extensive visibility into the motor system operation conditions stored in internal

registers. This information can be monitored through the I²C interface. Information can be monitored relating to

the device status, motor speed, supply voltage, speed command, motor phase-voltage amplitude, fault status,

and others. The data is updated on the fly.

8.4.12.1 Motor-Status Readback

The motor FaultReg register provides information on overtemperature (OverTemp), overcurrent (OverCurr), and

locked rotor (Lock0–Lock5).

8.4.12.2 Motor-Speed Readback

The motor operation speed is automatically updated in register MotorSpeed while the motor is spinning. The

value is determined by the period for calculated BEMF zero crossings on phase U. The electrical speed of the

motor is denoted as Velocity (Hz) and is calculated as shown in Equation 9.

Velocity (Hz) = {MotorSpeed} / 10

As an example consider the following:

MotorSpeed = 0x01FF;

(9)

Velocity = 512 (0x01FF) / 10 = 51 Hz

ecycles 1 mechcycle

second

minute

51

ì

ì 60

= 1530 RPM

second

2

ecycle

For a 4-pole motor, this translates to:

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8.4.12.3 Motor Electrical-Period Readback

The motor-operation electrical period is automatically updated in register MotorPeriod while the motor is spinning.

The electrical period is measured as the time between calculated BEMF zero crossings for phase U. The

electrical period of the motor is denoted as t_{ELE_PERIOD}(µs) and is calculated as shown in Equation 10.

t_{ELE_PERIOD}(µs) = {MotorPeriod} × 10

As an example consider the following:

MotorPeriod = 0x01FF;

(10)

(11)

t_{ELE_PERIOD}= 512 (0x01FF) × 10 = 5120 µs

The motor electrical period and motor speed satisfies the condition of Equation 11.

t_{ELE_PERIOD}(s) × Velocity (Hz) = 1

8.4.12.4 BEMF Constant Read Back

For any given motor, the integrated value of BEMF during half of an electronic cycle is a constant, Ktc (see

Lock2: Abnormal Kt ).

The integration of the motor BEMF is processed periodically (updated every electrical cycle) while the motor is

spinning. The result is stored in register MotorKt.

The relationship is shown in .

Ktc (V/Hz) = {MotorKt} / 2 / 1090

(12)

8.4.12.5 Motor Estimated Position by IPD

After inductive sense is executed, the rotor position is detected within 60 electrical degrees of resolution. The

position is stored in register IPDPosition.

The value stored in IPDPosition corresponds to one of the six motor positions plus the IPD advance angle as

shown in Table 8. For more information about IPD, see Initial Position Detect (IPD).

Table 8. IPD Position Read Back

S

U

V

U

V

U

V

U

V

U

V

U

V

N

S

W

Rotor position (°)

Data1

0

60

43

60

44

120

85

180

128

120

85

240

171

300

213

IPD advance angle

Data2

30

22

90

63

Register data

(Data1 + Data2) mod (256)

8.4.12.6 Supply-Voltage Readback

The power supply is monitored periodically during motor operation. This information is available in register

SupplyVoltage. The power supply voltage is recorded as shown in Equation 13.

V_POWERSUPPLY(V) = Supply Voltage × 30 V / 256

(13)

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8.4.12.7 Speed-Command Readback

The DRV10983-Q1 device converts the various types of speed command into a speed command value

(SpeedCmd) as shown in Figure 44. By reading SpeedCmd, the user can observe PWM input duty (PWM digital

mode), analog voltage (analog mode), or I²C data (I²C mode). This value is calculated as shown in Equation 14.

Equation 14 shows how the speed command as a percentage can be calculated and set in SpeedCmd.

Duty_SPEED(%) = SpeedCmd × 100 / 255

where

•

Duty_SPEED= Speed command as a percentage

SpeedCmd = Register value

(14)

8.4.12.8 Speed-Command Buffer Readback

If acceleration current limit and AVS are enabled, the PWM duty cycle output (read back at spdCmdBuffer) may

not always match the input command (read back at SpeedCmd) shown in Figure 44. See Anti Voltage

Suppression Function and Current Limit.

By reading the value of spdCmdBuffer, the user can observe buffered speed command (output PWM duty cycle)

to the motor.

Equation 15 shows how the buffered speed is calculated.

Duty_OUTPUT(%) = spdCmdBuffer × 100 / 255

where

•

Duty_OUTPUT= The maximum duty cycle of the output PWM, which represents the output amplitude in

percentage.

•

spdCmdBuffer = Register value

(15)

PWM in

Analog

PWM duty

ADC

AVS,

Acceleration Current Limit

Closed Loop Accelerate

Speed

Command

I²C

SpeedCmd

PWM_DCO

spdCmdBuffer

Figure 44. SpeedCmd and spdCmdBuffer Registers

8.4.12.9 Fault Diagnostics

See Lock Detect and Fault Handling.

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8.5 Register Maps

8.5.1 I²C Serial Interface

The DRV10983-Q1 device provides an I²C slave interface with slave address 101 0010. TI recommends a pullup

resistor of 4.7 kΩ to 3.3 V for I²C interface ports SCL and SDA. The protocol for the I²C interface is given in

Figure 45.

I2C Write

Start

7 bit Slave Add

R/W=0 ACK 8 bit Reg Add

ACK 8 bit Data ACK 8 bit Data ACK

Stop

Internal Reg

write happens

I2C Read

Start

7 bit Slave Add

R/W=0 ACK 8 bit Reg Add

ACK

Start

7 bit Slave Add

R/W=1 8 bit Data ACK 8 bit Data ACK

Stop

Data from Reg is

loaded to the buffer

Figure 45. I²C Protocol

Seven read/write registers (0x30:0x36) are used to set motor speed and control device registers and EEPROM.

Device operation status can be read back through nine read-only registers (0x0:0x08). Another seven EEPROM

registers (0x90:0x96) can be accessed to program motor parameters and optimize the spin-up profile for the

application.

8.5.2 Register Map

REGISTER

NAME

D15

D7

D14

D6

D13

D5

D12

D4

D11

D3

D10

D2

D9

D1

D8

D0

ADDR.

(1)(2)

FaultReg

0x00

OverTemp TempWarni

ng

VCC_OV

VREG_OC

OverCurr

CP_UVLO VREG_UVL VCC_UVLO

O

V3P3_UVL

O

Reserved

Lock5

Lock4

Lock3

Lock2

Lock1

Lock0

(1)

MotorSpeed

MotorPeriod

0x01

0x02

0x03

0x04

MotorSpeed[15:0]

MotorPeriod[15:0]

MotorKt[15:0]

(1)

MotorKt

(1)

MotorCurrent

Reserved

MotorCurrent[10:8]

MotorCurrent[7:0]

IPDPosition[7:0]

SupplyVoltage[7:0]

SpeedCmd[7:0]

IPDPosition /

SupplyVoltage

0x05

0x06

0x07

0x08

0x30

(1)

SpeedCmd /

spdCmdBuffer⁽¹⁾

spdCmdBuffer[7:0]

(1)

AnalogInLvl

Reserved

commandSenseAdc[9:8]

commandSenseAdc[7:0]

DieID[7:0]

Device ID /

(1)

Revision ID

RevisionID[7:0]

Reserved

(3)

SpeedCtrl

OverRide

SpeedCtrl[8

]

SpeedCtrl[7:0]

EEPROM

Programming1

0x31

ENPROGKEY[15:0]

(3)

(1) Read only

(2) Fault Register requires 0xFF to be written to the register to clear the bits.

(3) R/W

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Register Maps (continued)

REGISTER

NAME

D15

D7

D14

D6

D13

D5

D12

D4

D11

D3

D10

D2

D9

D1

D8

D0

ADDR.

EEPROM

Programming2

0x32

Reserved

(3)

eeReadySt

atus

EEPROM

Programming3

0x33

Reserved

eeIndAddress[7:0]

eeIndWData[15:0]

EEPROM

Programming4

0x34

0x35

(3)

EEPROM

Programming5

Reserved

ShadowRe

Reserved

eeWRnEn

eeRefresh

gEn

Reserved

eeAccMode[1:0]

EEPROM

Programming6

0x36

0x60

eeIndRData[15:0]

(3)

EECTRL

MTR_DIS

Reserved

(4)

CONFIG1

CONFIG2

CONFIG3

0x90

0x91

0x92

0x93

0x94

SSMConfig[1:0]

FGOLSel[1:0]

FGCycle[3:0]

ClkCycleAdj

ust

RMShift[2:0]

RMValue[3:0]

(4)

Reserved

KtShift[2:0]

KtValue[3:0]

CommAdv

Mode

TCtrlAdvShift[2:0]

TCtrlAdvValue[3:0]

ISDThr[1:0]

BrkCurrThr BEMF_HYS

Sel

ISDEn

RvsDrEn

RvsDrThr[1:0]

OpenLCurr[1:0]

OpLCurrRt[2:0]

StAccel2[2:0]

BrkDoneThr[2:0]

StAccel[2:0]

CONFIG4⁽⁴⁾

Reserved AccelRange

Sel

Op2ClsThr[4:0]

AlignTime[2:0]

LockEn1

(4)

CONFIG5

OTWarning_ILimit[1:0]

LockEn5

LockEn4

LockEn3

LockEn2

LockEn0

SwILimit[3:0]

HwILimit[2:0]

AVSMEn

IPDasHwILi

mit

(4)

CONFIG6

0x95

0x96

SpdCtlrMd

CLoopDis

PWMFreq

KtLckThr[1:0]

ClsLpAccel[2:0]

AvSIndEn

AVSMMd

IPDRIsMd

DutyCycleLimit[1:0]

IPDCurrThr[3:0]

SlewRate[1:0]

IPDClk[1:0]

(4)

CONFIG7

IPDAdvcAg[1:0]

Reserved CtrlCoef[1:0]

DeadTime[4:0]

(4) EEPROM

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Table 9. Default EEPROM

Values

ADDRESS

DEFAULT

VALUE

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x1048

0x2F3B

0x0050

0x1B8A

0x3FAF

0x3C43

0x016A

8.5.3 Register Descriptions

Table 10. Access Type Codes

ACCESS TYPE

CODE

DESCRIPTION

READ TYPE

R

Read

Write

WRITE TYPE

W

W1C

W

Write

1C

1 to clear

RESET OR DEFAULT VALUE

-n

Value after reset or the default

value

8.5.3.1 FaultReg Register (address = 0x00) [reset = 0x00]

Figure 46. FaultReg Register

15

14

13

12

11

10

9

8

OverTemp

R/W1C-0

TempWarning

R//W1C-0

VCC_OV

R/W1C-0

VREG_OC

R/W1C-0

OverCurr

R/W1C-0

CP_UVLO

R/W1C-0

VREG_UVLO

R/W1C-0

VCC_UVLO

R/W1C-0

7

6

5

4

3

2

1

0

V3P3_UVLO

R/W1C-0

Reserved

R/W1C-0

Lock5

Lock4

Lock3

Lock2

Lock1

Lock0

R/W1C-0

Table 11. FaultReg Register Field Descriptions

Bit

Field

OverTemp

Type

Reset

Description

Bit to indicate device temperature is over the limit.

15

R//W1C

0

14

13

12

TempWarning

VCC_OV

R/W1C

0

Bit to indicate device temperature is over the warning limit.

Bit to indicate the supply voltage is above the upper limit.

VREG_OC

Bit to indicate that the step-down regulator is in an overcurrent

condition.

11

10

OverCurr

R/W1C

0

Bit to indicate that an overcurrent event happened.

CP_UVLO

Bit to indicate that the charge pump is in an undervoltage fault

condition.

9

8

7

6

VREG_UVLO

VCC_UVLO

V3P3_UVLO

Reserved

R/W1C

0

Bit to indicate that the step-down regulator (VREG) is in an

undervoltage fault condition.

Bit to indicate that the supply (V_CC) is in an undervoltage fault

condition.

Bit to indicate that the 3.3 V LDO regulator is in an undervoltage

fault condition.

Do not access this bit.

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Table 11. FaultReg Register Field Descriptions (continued)

Bit

5

Field

Type

Reset

Description

Lock5

Lock4

Lock3

Lock2

Lock1

Lock0

R/W1C

0

Stuck in closed loop fault

Stuck in open loop fault

No motor fault

4

3

2

Kt abnormal fault

1

Speed abnormal fault

Hardware current-limit fault

0

8.5.3.2 MotorSpeed Register (address = 0x01) [reset = 0x00]

Figure 47. MotorSpeed Register

15

14

13

12

11

10

9

8

MotorSpeed[15] MotorSpeed[14] MotorSpeed[13] MotorSpeed[12] MotorSpeed[11] MotorSpeed[10] MotorSpeed[9] MotorSpeed[8]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

R-0

0

MotorSpeed[7] MotorSpeed[6] MotorSpeed[5] MotorSpeed[4] MotorSpeed[3] MotorSpeed[2] MotorSpeed[1] MotorSpeed[0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Table 12. MotorSpeed Register Field Descriptions

Bit

15:0

Field

MotorSpeed[15:0]

Type

Reset

Description

R

0x00

16-bit value indicating the motor speed.

Motor speed in Hz = MotorSpeed[15:0] / 10

8.5.3.3 MotorPeriod Register (address = 0x02) [reset = 0x00]

Figure 48. MotorPeriod Register

15

14

13

12

11

10

9

8

MotorPeriod[15] MotorPeriod[14] MotorPeriod[13] MotorPeriod[12] MotorPeriod[11] MotorPeriod[10] MotorPeriod[9] MotorPeriod[8]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

R-0

0

MotorPeriod[7] MotorPeriod[6] MotorPeriod[5] MotorPeriod[4] MotorPeriod[3] MotorPeriod[2] MotorPeriod[1] MotorPeriod[0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Table 13. MotorPeriod Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

MotorPeriod[15:0]

R

0x00

16-bit value indicating the motor period.

Motor period = MotorPeriod[15:0] × 10 = period in μs

50

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8.5.3.4 MotorKt Register (address = 0x03) [reset = 0x00]

Figure 49. MotorKt Register

15

MotorKt[15]

R-0

14

MotorKt[14]

R-0

13

MotorKt[13]

R-0

12

MotorKt[12]

R-0

11

MotorKt[11]

R-0

10

MotorKt[10]

R-0

9

8

MotorKt[9]

R-0

MotorKt[8]

R-0

7

6

5

4

3

2

1

0

MotorKt[7]

R-0

MotorKt[6]

R-0

MotorKt[5]

R-0

MotorKt[4]

R-0

MotorKt[3]

R-0

MotorKt[2]

R-0

MotorKt[1]

R-0

MotorKt[0]

R-0

Table 14. MotorKt Register Field Descriptions

Bit

Field

MotorKt[15:0]

Type

Reset

Description

15:0

R

0x00

16-bit value indicating the motor measured velocity constant.

Ktc (V/Hz) = {MotorKt[15:0]} / 2 / 1090

8.5.3.5 MotorCurrent Register (address = 0x04) [reset = 0x00]

Figure 50. MotorCurrent Register

15

14

13

12

11

10

9

8

Reserved

MotorCurrent[1 MotorCurrent[9] MotorCurrent[8]

0]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

R-0

0

MotorCurrent[7] MotorCurrent[6] MotorCurrent[5] MotorCurrent[4] MotorCurrent[3] MotorCurrent[2] MotorCurrent[1] MotorCurrent[0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Table 15. MotorCurrent Register Field Descriptions

Bit

Field

Type

R

Reset

0

Description

15:11

10:0

Reserved

Do not access these bits.

MotorCurrent[10:0]

R

0x00

11-bit value indicating the motor peak current.

if MotorCurrent[10:0] >=1023

Current (A) = 3 × (MotorCurrent[10:0] – 1023) / 512

Else

Current (A) = 3 × (MotorCurrent[10:0]) / 512

8.5.3.6 IPDPosition–SupplyVoltage Register (address = 0x05) [reset = 0x00]

Figure 51. IPDPosition–SupplyVoltage Register

15

14

13

12

11

10

9

8

IPDPosition [7] IPDPosition [6] IPDPosition [5] IPDPosition [4] IPDPosition [3] IPDPosition [2] IPDPosition [1] IPDPosition [0]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

R-0

0

SupplyVoltage[ SupplyVoltage[ SupplyVoltage[ SupplyVoltage[ SupplyVoltage[ SupplyVoltage[ SupplyVoltage[ SupplyVoltage[

7]

6]

5]

4]

3]

2]

1]

0]

R-0

Table 16. IPDPosition–SupplyVoltage Register Field Descriptions

Bit

15:8

Field

Type

Reset

Description

IPDPosition [7:0]

R

0x0

8-bit value indicating the estimated motor position during IPD

plus the IPD advance angle (see Table 8)

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Table 16. IPDPosition–SupplyVoltage Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7:0

SupplyVoltage[7:0]

R

0x0

8-bit value indicating the supply voltage

V_POWERSUPPLY(V) = SupplyVoltage[7:0] × 30 V / 255

For example, SupplyVoltage[7:0] = 0x67,

V_POWERSUPPLY(V) = 0x67 (102) × 30 / 255 = 12 V

8.5.3.7 SpeedCmd–spdCmdBuffer Register (address = 0x06) [reset = 0x00]

Figure 52. SpeedCmd–spdCmdBuffer Register

15

SpeedCmd[7]

R-0

14

SpeedCmd[6]

R-0

13

SpeedCmd[5]

R-0

12

SpeedCmd[4]

R-0

11

SpeedCmd[3]

R-0

10

SpeedCmd[2]

R-0

9

8

SpeedCmd[1]

R-0

SpeedCmd[0]

R-0

7

6

5

4

3

2

1

0

spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[

7]

6]

5]

4]

3]

2]

1]

0]

R-0

Table 17. SpeedCmd–spdCmdBuffer Register Field Descriptions

Bit

Field

Type

Reset

Description

15:8

SpeedCmd[7:0]

R

0x0

8-bit value indicating the speed command based on analog or

PWMin or I²C.

FF indicates 100% speed command.

7:0

spdCmdBuffer[7:0]

R

0x0

8-bit value indicating the speed command after buffer output.

FF indicates 100% speed command.

8.5.3.8 AnalogInLvl Register (address = 0x07) [reset = 0x00]

Figure 53. AnalogInLvl Register

15

14

13

12

Reserved

11

Reserved

10

9

8

Reserved

commandSnsA commandSnsA

DC[9]

DCt[8]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

0

commandSnsA commandSnsA commandSnsA commandSnsA commandSnsA commandSnsA commandSnsA commandSnsA

DC[7]

DC[6]

DC[5]

DC[4]

DC[3]

DC[2]

DC[1]

DC[0]

R-0

Table 18. AnalogInLvl Register Field Descriptions

Bit

Field

Type

R

Reset

0

Description

15:10

9:0

Reserved

Do not access these bits.

commandSnsADC[9:0]

R

0x00

10-bit value indicating the analog speed input converted to a

digital word.

AnalogSPEED (V) = AnalogInLvl × V3P3 / 1024

8.5.3.9 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]

Figure 54. DeviceID–RevisionID Register

15

DieID[7]

R-0

14

DieID[6]

R-0

13

DieID[5]

R-0

12

DieID[4]

R-0

11

DieID[3]

R-0

10

DieID[2]

R-0

9

8

DieID[1]

R-0

DieID[0]

R-0

7

6

5

4

3

2

1

0

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RevisionID[7]

R-0

RevisionID[6]

R-0

RevisionID[5]

R-0

RevisionID[4]

R-0

RevisionID[3]

R-0

RevisionID[2]

R-0

RevisionID[1]

R-0

RevisionID[0]

R-0

Table 19. DeviceID–RevisionID Register Field Descriptions

Bit

15:10

9:0

Field

Type

R

Reset

0

Description

DieID[7:0]

8-bit unique device identification.

RevisionID[7:0]

R

0x00

8-bit revision ID for the device

0000 0000 → REV A

0000 0001 → REV B

...

8.5.3.10 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]

Figure 55. DeviceID–RevisionID Register

15

DieID[7]

R-0

14

DieID[6]

R-0

13

DieID[5]

R-0

12

DieID[4]

R-0

11

DieID[3]

R-0

10

DieID[2]

R-0

9

8

DieID[1]

R-0

DieID[0]

R-0

7

6

5

4

3

2

1

0

RevisionID[7]

R-0

RevisionID[6]

R-0

RevisionID[5]

R-0

RevisionID[4]

R-0

RevisionID[3]

R-0

RevisionID[2]

R-0

RevisionID[1]

R-0

RevisionID[0]

R-0

Table 20. DeviceID–RevisionID Register Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

0x0

Description

DieID[7:0]

8-bit unique device identification.

RevisionID[7:0]

R

0x0

8-bit revision ID for the device

0000 0000 → REV A

0000 0001 → REV B

...

8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F)

Registers 0x09 through 0x2F are not used.

8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00]

Figure 56. SpeedCtrl Register

15

14

Reserved

R-0

13

Reserved

R-0

12

Reserved

R-0

11

Reserved

R-0

10

Reserved

R-0

9

8

OverRide

R/W-0

Reserved

R-0

SpeedCtrl[8]

R/W-0

7

6

5

4

3

2

1

0

SpeedCtrl[7]

R/W-0

SpeedCtrl[6]

R/W-0

SpeedCtrl[5]

R/W-0

SpeedCtrl[4]

R/W-0

SpeedCtr[3]

R/W-0

SpeedCtrl[2]

R/W-0

SpeedCtrl[1]

R/W-0

SpeedCtrl[0]

R/W-0

Table 21. SpeedCtrl Register Field Descriptions

Bit

Field

OverRide

Type

Reset

Description

15

R/W

0

Used to control the SpdCtrl[8:0] bits. If OverRide = 1, the user

can write the speed command directly through I²C.

14:9

8:0

Reserved

R

0x0

Do not access this bit.

SpeedCtrl[8:0]

R/W

0x00

9-bit value used for the motor speed. If OverRide = 1, speed

command can be written by the user through I²C.

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8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00]

Figure 57. EEPROM Programming1 Register

15

14

13

12

11

10

9

8

ENPROGKEY

[15]

ENPROGKEY

[14]

ENPROGKEY

[13]

ENPROGKEY

[12]

ENPROGKEY

[11]

ENPROGKEY

[10]

ENPROGKEY

[9]

ENPROGKEY

[9]

R/W-0

7

R/W-0

6

R/W-0

5

R/W-0

4

R/W-0

3

R/W-0

2

R/W-0

1

R/W-0

0

ENPROGKEY

[7]

ENPROGKEY

[6]

ENPROGKEY

[5]

ENPROGKEY

[4]

ENPROGKEY

[3]

ENPROGKEY

[2]

ENPROGKEY

[1]

ENPROGKEY

[0]

R/W-0

Table 22. EEPROM Programming1 Register Field Descriptions

Bit

Field

ENPROGKEY[15:0]

Type

Reset

Description

15:0

R/W

0x00

EEPROM access key

0xCODE → access key for customer space; registers 0x90 to

0x96

8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00]

Figure 58. EEPROM Programming2 Register

15

Reserved

R-0

14

Reserved

R-0

13

Reserved

R-0

12

Reserved

R-0

11

Reserved

R-0

10

Reserved

R-0

9

8

Reserved

R-0

Reserved

R-0

7

6

5

4

3

2

1

0

eeReadyStatus

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Table 23. EEPROM Programming2 Register Field Descriptions

Bit

15:1

0

Field

Type

R

Reset

0x00

0

Description

Reserved

eeReadyStatus

Do not access these bits.

R

EEPROM status bit.

0: EEPROM not ready for read/write access

1: EEPROM ready for read/write access

8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00]

Figure 59. EEPROM Programming3 Register

15

Reserved

R-0

14

Reserved

R-0

13

Reserved

R-0

12

Reserved

R-0

11

Reserved

R-0

10

Reserved

R-0

9

8

Reserved

R-0

Reserved

R-0

7

6

5

4

3

2

1

0

eeIndAddress

[7]

eeIndAddress

[6]

eeIndAddress

[5]

eeIndAddress

[4]

eeIndAddress

[3]

eeIndAddress

[2]

eeIndAddress

[1]

eeIndAddress

[0]

R-0

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Table 24. EEPROM Programming3 Register Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

0x0

Description

Reserved

Do not access these bits.

eeIndAddress[7:0]

R

0x0

EEPROM individual access address.

Contents of this register define the address of EEPROM for the

individual access operation. For example, for writing/reading

CONFIG1 in individual access mode happens if eeIndAddress =

0x90.

8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]

Figure 60. EEPROM Programming4 Register

15

14

13

12

11

10

9

8

eeIndWData

[15]

eeIndWData

[14]

eeIndWData

[13]

eeIndWData

[12]

eeIndWData

[11]

eeIndWData

[10]

eeIndWData[9] eeIndWData[8]

R/W-0

7

R/W-0

6

R/W-0

5

R/W-0

4

R/W-0

3

R/W-0

2

R/W-0

1

R/W-0

0

eeIndWData[7] eeIndWData[6] eeIndWData[5] eeIndWData[4] eeIndWData[3] eeIndWData[2] eeIndWData[1] eeIndWData[0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Table 25. EEPROM Programming4 Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

eeIndWData[15:0]

R/W

0x00

EEPROM individual access write data

Contents of this register are used to write to EEPROM data of

the registers specified by eeIndAddress.

8.5.3.17 EEPROM Programming5 Register (address = 0x35) [reset = 0x00]

Figure 61. EEPROM Programming5 Register

15

Reserved

R-0

14

Reserved

R-0

13

Reserved

R-0

12

11

Reserved

R-0

10

Reserved

R-0

9

8

ShadowRegEn

R/W-0

Reserved

R-0

0

7

6

5

4

3

2

1

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

eeWRnEn

R/W-0

eeAccMode[1] eeAccMode[0]

R/W-0 R/W-0

Table 26. EEPROM Programming5 Register Field Descriptions

Bit

15:13

12

Field

Type

R

Reset

000

0

Description

Reserved

ShadowRegEn

Do not access these bits.

R/W

Enable shadow register.

0 : Shadow register is not used.

1 : Shadow register values are used for device operation

(EEPROM contents are ignored). I²C read returns the contents

of the shadow registers.

11:9

8

Reserved

eeRefresh

R

000

0

Do not access these bits.

R/W

EEPROM refresh

0 : normal operation

1 : Sync shadow registers with contents of EEPROM.

7:3

2

Reserved

eeWRnEn

R

0x0

0

Do not access these bits.

R/W

EEPROM Write/Read enable

0 : EEPROM read enable

1 : EEPROM write enable.

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Table 26. EEPROM Programming5 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1:0

eeAccMode[1:0]

R/W

00

EEPROM access mode

00 : EEPROM access disabled

01 : EEPROM individual access enabled

10 : EEPROM mass access enabled

11 : Do not access these bits.

8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00]

Figure 62. EEPROM Programming6 Register

15

14

13

12

11

10

9

8

eeIndRData[15] eeIndRData[14] eeIndRData[13] eeIndRData[12] eeIndRData[11] eeIndRData[10] eeIndRData[9] eeIndRData[8]

R-0

7

R-0

6

R-0

5

R-0

4

R-0

3

R-0

2

R-0

1

R-0

0

eeIndRData[7] eeIndRData[6] eeIndRData[5] eeIndRData[4] eeIndRData[3] eeIndRData[2] eeIndRData[1] eeIndRData[0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Table 27. EEPROM Programming6 Register Field Descriptions

Bit

15:0

Field

eeIndRData[15:0]

Type

Reset

Description

R

0x00

EEPROM Individual Access Read Data

Contents of this register reflect the value of EEPROM location

accessed through the individual read.

8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F)

Registers 0x37 through 0x5F are not used.

8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00]

Figure 63. EECTRL Register

15

MTR_DIS

W-0

14

Reserved

R-0

13

Reserved

R-0

12

Reserved

R-0

11

Reserved

R-0

10

Reserved

R-0

9

8

Reserved

R-0

Reserved

R-0

7

6

5

4

3

2

1

0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Reserved

R-0

Table 28. EECTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15

MTR_DIS

W

0

Control to disable motor without going to sleep. For use during

EEPROM programming. This bit is write-only (cannot be read).

0: Motor control is enabled.

1: Motor control is disabled.

14:0

Reserved

R

0x00

Do not access these bits.

8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F)

Registers 0x61 through 0x8F are not used.

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8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00]

Figure 64. CONFIG1 Register

15

14

13

12

11

10

9

8

SSMConfig[1]

R/W-0

SSMConfig[0]

R/W-0

FGOLSel[1]

R/W-0

FGOLSel[0]

R/W-0

FGCycle[3]

R/W-0

FGCycle[2]

R/W-0

FGCycle[1]

R/W-0

FGCycle[0]

R/W-0

7

6

5

4

3

2

1

0

ClkCycleAdjust

R/W-0

RMShift[2]

R/W-0

RMShift[1]

R/W-0

RMShift[0]

R/W-0

RMValue[3]

R/W-0

RMValue[2]

R/W-0

RMValue[1]

R/W-0

RMValue[0]

R/W-0

Table 29. CONFIG1 Register Field Descriptions

Bit

Field

SSMConfig[1:0]

Type

Reset

Description

15:14

R/W

00

Spread spectrum modulation control

00: No spread spectrum

01: ±5% dithering

1:0: ±10% dithering

11: ±15% dithering

13:12

11:8

FGOLSel[1:0]

FGCycle[3:0]

R/W

00

FG open-loop output select

00: FG outputs in both open loop and closed loop

01: FG outputs only in closed loop after approximately 280ms of

delay

10: FG outputs closed loop and the first open loop

11: Reserved

0x0

FG motor pole option

n: FG output is electrical speed / (n + 1)

0: FG / 1 (2 pole)

1: FG / 2 (4 pole)

2: FG / 3 (6 pole)

3: FG / 4 (8 pole)

...

15: FG / 16 (32 pole)

7

ClkCycleAdjust

RMShift[2:0]

R/W

0

0: Full-cycle adjust

1: Half-cycle adjust

6:4

000

Number of shift bits to determine the motor phase resistance.

R_{PH_CT}= RmValue << RmShift

R_{PH_CT}' = (bin) {RPhase / 0.009615}

After calculating R_{PH_CT}' value, split the value with shift number

and significant number according the length of the R_{PH_CT}

'

value.

If the length of R_{PH_CT}' is within 4 bits; RmValue[3:0] = R_{PH_CT}';

RmShift[2:0] = 000

If the length of R_{PH_CT}' is 5 bits; RmValue[3:0] = R_{PH_CT}'[4:1];

RmShift[2:0] = 001

and so on.

3:0

RMValue[3:0]

R/W

0x0

Significant portion of the motor resistor, used in conjunction with

RmShift[2:0]

8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00]

Figure 65. CONFIG2 Register

15

Reserved

R-0

14

13

12

11

10

9

8

KtShift[2]

R/W-0

KtShift[1]

R/W-0

KtShift[0]

R/W-0

KtValue[3]

R/W-0

KtValue[2]

R/W-0

KtValue[1]

R/W-0

KtValue[0]

R/W-0

7

6

5

4

3

2

1

0

CommAdvMod TCtrlAdvShift[2] TCtrlAdvShift[1] TCtrlAdvShift[0]

e

R/W-0

R-0

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Table 30. CONFIG2 Register Field Descriptions

Bit

15

Field

Type

R

Reset

0

Description

Reserved

KtShift[2:0]

Do not access this bit

14:12

R/W

000

Number of shift bits to determine the motor BEMF constant.

Kt = KtValue << KtShift

11:8

7

KtValue[3:0]

R/W

0x0

0

CommAdvMode

Commutation advance mode

0: Voltage advance is maintained at a fixed time⁽¹⁾relative to the

estimated BEMF.

1: Voltage advance is maintained at a variable time relative to

the estimated BEMF based on: t_adv= t_setting× (U-BEMF) / U

6:4

3:0

TCtrlAdvShift[2:0]

TCtrlAdvValue[3:0]

R/W

000

0x0

Number of shift bits to determine the commutation advance

timing

t_adv= TCtrlAdvValue << TCtrlAdvShift

Commutation advance value.

(1) EEPROM

8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00]

Figure 66. CONFIG3 Register

15

14

13

12

11

10

9

8

ISDThr[1]

R/W-0

ISDThr[0]

R/W-0

BrkCurThrSel

R/W-0

BEMF_HYS

R/W-0

ISDEn

R/W-0

RvsDrEn

R/W-0

RvsDrThr[1]

R/W-0

RvsDrThr[0]

R/W-0

7

6

5

4

3

2

1

0

OpenLCurr[1]

R/W-0

OpenLCurr[0]

R/W-0

OpLCurrRt[2]

R/W-0

OpLCurrRt[1]

R/W-0

OpLCurrRt[0]

R/W-0

BrkDoneThr[2] BrkDoneThr[1] BrkDoneThr[0]

R/W-0 R/W-0 R/W-0

Table 31. CONFIG3 Register Field Descriptions

Bit

Field

ISDThr[1:0]

Type

Reset

Description

15:14

R/W

00

ISD stationary judgment threshold

00: 6 Hz (80 ms, no zero cross)

01: 3 Hz (160 ms, no zero cross)

10: 1.6 Hz (320 ms, no zero cross)

11: 0.8 Hz (640 ms, no zero cross)

13

BrkCurThrSel

R/W

0

Brake current-level-threshold selection.

0: 24 mA

1: 48 mA

12

11

10

9:8

BEMF_HYS

ISDEn

R/W

0

0: Low hysteresis for BEMF comparator (approximately 20 mV)

1: High hysteresis for BEMF comparator (approximately 40 mV)

0

0: Initial speed detect (ISD) disabled

1: ISD enabled

RvsDrEn

0

0: Reverse drive disabled

1: Reverse drive enabled

RvsDrThr[1:0]

00

The threshold where device starts to process revers drive

(RvsDr) or brake.

00: 6.3 Hz

01: 13 Hz

10: 26 Hz

11: 51 Hz

58

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Table 31. CONFIG3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7:6

OpenLCurr[1:0]

R/W

00

Open-loop current setting.

00: 0.2 A

01: 0.4 A

10: 0.8 A

11: 1.6 A

Align current setting.

00: 0.15 A

01: 0.3 A

10: 0.6 A

11: 1.2 A

5:3

OpLCurrRt[2:0]

R/W

000

Open-loop current ramp-up setting.

000: 6 V_CC/s

001: 3 V_CC/s

010: 1.5 V_CC/s

011: 0.7 V_CC/s

100: 0.34 V_CC/s

101: 0.16 V_CC/s

110: 0.07 V_CC/s

111: 0.023 V_CC/s

2:0

BrkDoneThr[2:0]

R/W

000

Braking mode setting.

000: No brake (BrkEn = 0)

001: 2.7 s

010: 1.3 s

011: 0.67 s

100: 0.33 s

101: 0.16 s

110: 0.08 s

111: 0.04 s

8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00]

Figure 67. CONFIG4 Register

15

Reserved

R-0

14

13

12

11

10

9

8

AccelRangeSel

R/W-0

StAccel2[2]

R/W-0

StAccel2[1]

R/W-0

StAccel2[0]

R/W-0

StAccel[2]

R/W-0

StAccel[1]

R/W-0

StAccel[0]

R/W-0

7

6

5

4

3

2

1

0

Op2ClsThr[4]

R/W-0

Op2ClsThr[3]

R/W-0

Op2ClsThr[2]

R/W-0

Op2ClsThr[1]

R/W-0

Op2ClsThr[0]

R/W-0

AlignTime[2]

R/W-0

AlignTime[1]

R/W-0

AlignTime[0]

R/W-0

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Table 32. CONFIG4 Register Field Descriptions

Bit

15

14

Field

Type

R

Reset

Description

Reserved

AccelRangeSel

0

Do not access this bit

R/W

Acceleration range selection

0: Fast

1: Slow

13:11

StAccel2[2:0]

R/W

000

Open-loop start-up acceleration (second-order)

AccelRangeSel = 0; 000: 57 Hz/s²

AccelRangeSel = 0; 001 = 29 Hz/s²

AccelRangeSel = 0; 010 = 14 Hz/s²

AccelRangeSel = 0; 011 = 6.9 Hz/s²

AccelRangeSel = 0; 100 = 3.3 Hz/s²

AccelRangeSel = 0; 101 = 1.6 Hz/s²

AccelRangeSel = 0; 110 = 0.66 Hz/s²

AccelRangeSel = 0; 111 = 0 Hz/s²

AccelRangeSel = 1; 000 = 0.22 Hz/s²

AccelRangeSel = 1; 001 = 0.11 Hz/s²

AccelRangeSel = 1; 010 = 0.055 Hz/s²

AccelRangeSel = 1; 011 = 0.027 Hz/s²

AccelRangeSel = 1; 100 = 0.013 Hz/s²

AccelRangeSel = 1; 101 = 0.0063 Hz/s²

AccelRangeSel = 1; 110 = 0.0026 Hz/s²

AccelRangeSel = 1; 111 = 0 Hz/s²

10:8

StAccel[2:0]

R/W

0

Open-loop start-up acceleration (first-order)

AccelRangeSel = 0; 000 = 76 Hz/s

AccelRangeSel = 0; 001 = 38 Hz/s

AccelRangeSel = 0; 010 = 19 Hz/s

AccelRangeSel = 0; 011 = 9.2 Hz/s

AccelRangeSel = 0; 100 = 4.5 Hz/s

AccelRangeSel = 0; 101 = 2.1 Hz/s

AccelRangeSel = 0; 110 = 0.9 Hz/s

AccelRangeSel = 0; 111 = 0.3 Hz/s

AccelRangeSel = 1; 000 = 4.8 Hz/s

AccelRangeSel = 1; 001 = 2.4 Hz/s

AccelRangeSel = 1; 010 = 1.2 Hz/s

AccelRangeSel = 1; 011 = 0.58 Hz/s

AccelRangeSel = 1; 100 = 0.28 Hz/s

AccelRangeSel = 1; 101 = 0.13 Hz/s

AccelRangeSel = 1; 110 = 0.056 Hz/s

AccelRangeSel = 1; 111 = 0.019 Hz/s

7:3

Op2ClsThr[4:0]

R/W

0

Open- to closed-loop threshold

0 xxxx = Range 0: n × 0.8 Hz

0 0000 = N/A

0 0001 = 0.8 Hz

0 0111 = 5.6 Hz

0 1111 = 12 Hz

1 xxxx = Range 1: 12.8 × (n-16)+11.9 Hz

1 0000 = 11.9 Hz

1 0001 = 24.7 Hz

...

1 0111 = 101.5 Hz

1 1111 = 203.9 Hz

2:0

AlignTime[2:0]

R/W

0

Align time.

000 = 5.3 s

001 = 2.7 s

010 = 1.3 s

011 = 0.67 s

100 = 0.33 s

101 = 0.16 s

110 = 0.08 s

111 = 0.04 s

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8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00]

Figure 68. CONFIG5 Register

15

14

13

12

11

10

9

8

OTWarning

Limit[1]

OTWarning

Limit[0]

LockEn5

LockEn4

LockEn3

LockEn2

LockEn1

LockEn0

R/W-0

7

R/W-0

6

R/W-0

5

R/W-0

4

R/W-0

3

R/W-0

2

R/W-0

1

R/W-0

0

SWiLimitThr [3] SWiLimitThr [2] SWiLimitThr [1] SWiLimitThr [0] HWiLimitThr [2] HWiLimitThr [1] HWiLimitThr [0] IPDasHwILimit

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Table 33. CONFIG5 Register Field Descriptions

Bit

15:14

Field

OTWarningLimit[1:0]

Type

Reset

Description

R/W

00

Overtemperature warning current limit

00: No temperature-based current-limit function, uses

SWILimitThr

01: Limit current to 1 A when overtemperature warning reached

10: Limit current to 1.6 A when overtemperature warning

reached

11: Limit current to 2 A when overtemperature warning reached

13

LockEn5

R/W

0

Stuck in closed loop (no zero cross detected). Enabled when

high

12

11

10

9

LockEn4

R/W

0

Open loop stuck (no zero cross detected). Enabled when high

No motor fault. Enabled when high

LockEn3

0

LockEn2

0

Abnormal Kt. Enabled when high

LockEn1

0

Abnormal speed. Enabled when high

8

LockEn0

0

Lock-detection current limit. Enabled when high.

7:4

SWiLimitThr[3:0]

0x0

Acceleration current limit threshold

0000: No acceleration current limit

0001: 0.2-A current limit

0010 to 1111: n × 0.2 A current limit

3:1

HWiLimitThr[2:0]

R/W

000

HWILimitThr: Current limit for lock detection

If IPDasHwILimit = 0 then

x00: 2.5 A

x01: 1.9 A

x10: 1.5 A

x11: 0.9 A

If IPDasHwILimit = 1 then

000: 0.4 A

001: 0.8 A

010: 1.2 A

011: 1.6 A

100: 2 A

101: 2.4 A

110: 2.8 A

111: 3.2 A

0

IPDasHwILimit

R/W

0

0: Range1 of current limit for lock detection

1: Range2 of current limit for lock detection

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8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00]

Figure 69. CONFIG6 Register

15

14

13

12

11

10

9

8

SpdCtrlMd

R/W-0

PWMFreq

R/W-0

KtLckThr[1]

R/W-0

KtLckThr[0]

R/W-0

AVSIndEn

R/W-0

AVSMEn

R/W-0

AVSMMd

R/W-0

IPDRlsMd

R/W-0

7

6

5

4

3

2

1

0

CLoopDis

ClsLpAccel[2]

ClsLpAccel[1]

ClsLpAccel[0] DutyCycleLimit[ DutyCycleLimit[

SlewRate[1]

SlewRate[0]

1]

0]

R/W-0

Table 34. CONFIG6 Register Field Descriptions

Bit

Field

SpdCtrlMd

Type

Reset

Description

15

R/W

0

Speed input mode

0: Analog input expected at SPEED pin

1: PWM input expected at SPEED pin

14

PWMFreq

R/W

0

PWM Frequency Control

0: PWM frequency = 25 kHz

1: PWM frequency = 50 kHz

13:12

KtLckThr[1:0]

Abnormal Kt lock detect threshold

00: Kt_high = 3/2Kt. Kt_low = 3/4Kt

01: Kt_high = 2Kt. Kt_low = 3/4Kt

10: Kt_high = 3/2Kt. Kt_low = 1/2Kt

11: Kt_high = 2Kt. Kt_low = 1/2Kt

11

10

9

AVSIndEn

AVSMEn

AVSMMd

R/W

0

Inductive AVS enable. Enabled when high

Mechanical AVS enable. Enabled when high

Mechanical AVS mode

0: AVS to V_CC

1: AVS to 24 V

8

IPDRlsMd

R/W

0

IPD release mode

0: Brake when inductive release

1: Hi-z when inductive release

7

CLoopDis

R/W

0

0: Transfer to closed loop at Op2ClsThr speed

1: No transfer to closed loop. Keep in open loop

6:4

ClsLpAccel[2:0]

Closed-loop accelerate

000: Immediate change

001: 48 V_CC/s

010: 48 V_CC/s

011: 0.77 V_CC/s

100: 0.37 V_CC/s

101: 0.19 V_CC/s

110: 0.091 V_CC/s

111: 0.045 V_CC/s

3:2

DutyCycleLimit[1:0]

R/W

0

Minimum duty-cycle limit

00: Linear down to 5%, then holds at 5% until duty command is

1.5 %; 0 % for duty command below 1.5 %.

01: Linear down to 10%, then holds at 10% until duty command

is 1.5 %; 0 % for duty command below 1.5 %.

10: Linear down to 5%, then holds at 5% until duty command is

1.5 %; 100 % for duty command below 1.5 %.

11: Linear down to 10%, then holds at 10% until duty command

is 1.5 %; 100 % for duty command below 1.5 %.

1:0

SlewRate[1:0]

R/W

0

Slew-rate control for phase node

00: Typical slew rate for V_CCat 12 V = 35 V/μs

01: Typical slew rate for V_CCat 12 V = 50 V/μs

10: Typical slew rate for V_CCat 12 V = 80 V/μs

11: Typical slew rate for V_CCat 12 V = 120 V/μs

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8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00]

Figure 70. CONFIG7 Register

15

14

13

12

11

10

9

8

IPDAdvcAg[1]

R/W-0

IPDAdvcAg[0]

R/W-0

IPDCurrThr[3]

R/W-0

IPDCurrThr[2]

R/W-0

IPDCurrThr[1]

R/W-0

IPDCurrThr[0]

R/W-0

IPDClk[1]

R/W-0

IPDClk[0]

R/W-0

7

6

5

4

3

2

1

0

Reserved

R-0

CtrlCoef[1]

R/W-0

CtrlCoef[0]

R/W-0

DeadTime[4]

R/W-0

DeadTime[3]

R/W-0

DeadTime[2]

R/W-0

DeadTime[1]

R/W-0

DeadTime[0]

R/W-0

Table 35. CONFIG7 Register Field Descriptions

Bit

Field

IPDAdvcAg[1:0]

Type

Reset

Description

15:14

R/W

00

Advance angle after inductive sense.

00: 30 degrees

01: 60 degrees

10: 90 degrees

11: 120 degrees

13:10

9:8

IPDCurrThr[3:0]

IPDClk[1:0]

R/W

0x0

00

IPD (inductive sense) current threshold

0000: No IPD function. Align and go

0001: 0.4-A current threshold.

0010 to 1111: 0.2 A × (n + 1) current threshold.

Inductive sense clock

00: IPD clock 12 Hz; IPD measurement resolution = 2.56 µs

01: IPD clock = 24 Hz; IPD measurement resolution = 1.28 µs

10: IPD clock = 47 Hz; IPD measurement resolution = 0.64 µs

11: IPD clock = 95 Hz; IPD measurement resolution = 0.32 µs

7

Reserved

R

0

Do not access this bit.

6:5

CtrlCoef[1:0]

R/W

00

SCORE control constant

00: 0.25

01: 0.5

10: 0.75

11: 1

4:0

DeadTime[4:0]

R/W

0x0

Driver dead time

(n + 1) × 40 ns

40 ns to 1.204 μs

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DRV10983-Q1 device is used in sensorless 3-phase BLDC motor control. The driver provides a high-

performance, high-reliability, flexible, and simple solution for appliance fan, pump, and HVAC applications. The

following design shows a common application of the DRV10983-Q1 device.

9.2 Typical Application

VCC

0.1 µF

1

2

3

4

5

6

7

8

9

VCP

VCC 24

VCC 23

10 µF

CPP

10 nF

CPN

W

V

22

21

20

19

18

17

10 µF

5 V

SW

47 µH

SWGND

VREG

V1P8

GND

V3P3

M

V

1 µF

U

1 µF

PGND 16

PGND 15

DIR 14

4.75 kW

10 SCL

11 SDA

12 FG

SPEED 13

Interface to

Microcontroller

Figure 71. Typical Application Schematic

9.2.1 Design Requirements

Table 36 provides design input parameters and motor parameters for system design.

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Typical Application (continued)

Table 36. Recommended Application Range

MIN

6.2

TYP

MAX UNIT

28

1.8 V/Hz

Motor voltage

12

V

BEMF constant

Phase to phase, measured while motor is coasting

Measured ph-ph

0.001

0.6

Phase-Phase resistance

Phase-Phase inductance

38

Ω

Measured ph-ph

0.7

mH

Operating closed loop

speed

Electrical frequency

1

1000

Hz

Operating current

PGND, GND

0.1

2

3

A

Absolute maximum current During start-up or locked condition

Table 37. External Components

COMPONENT

C_VCC

PIN 1

V_CC

PIN 2

GND

V_CC

RECOMMENDED

10-µF ceramic capacitor rated for V_CC

0.1-µF ceramic capacitor rated for 10 V

10-nF ceramic capacitor rated for V_CC× 2

C_VCP

VCP

CPP

SW

C_CP

CPN

L_SW-VREG

VREG

47-µH ferrite inductor with 1.15-A current rating, 1.15-A saturation current, and DC resistance <

1-Ω (buck mode)

R_SW-VREG

C_VREG

C_V1P8

C_V3P3

R_SCL

SW

VREG

GND

V3P3

39-Ω series resistor rated for ¼ W (linear mode)

10-µF ceramic capacitor rated for 10 V

1-µF ceramic capacitor rated for 5 V

4.75-kΩ pullup to V3P3

VREG

V1P8

V3P3

SCL

SDA

FG

R_SDA

4.75-kΩ pullup to V3P3

R_FG

4.75-kΩ pullup to V3P3

9.2.2 Detailed Design Procedure

1. See the Design Requirements section and make sure your system meets the recommended application

range.

2. See the DRV10983-Q1 Tuning Guide and measure the motor parameters.

3. See the DRV10983-Q1 Tuning Guide. Configure the parameters using the DRV10983-Q1 GUI, and optimize

the motor operation. The Tuning Guide takes the user through all the configurations step by step, including:

start-up operation, closed-loop operation, current control, initial positioning, lock detection, and anti-voltage

surge.

4. Build your hardware based on Layout Guidelines .

5. Connect the device into a system and validate your system solution.

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9.2.3 Application Curves

FG

Phase

current

Phase

voltage

Figure 72. DRV10983-Q1 Start-Up Waveform

Figure 73. DRV10983-Q1 Operation Current Waveform

66

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10 Power Supply Recommendations

The DRV10983-Q1 device is designed to operate from an input voltage supply, V_CC, in a range between 8 V and

28 V. The user must place a 10-µF ceramic capacitor rated for V_CCas close as possible to the V_CCand GND

pins.

If the power supply ripple is more than 200 mV, in addition to the local decoupling capacitors, a bulk capacitance

is required and must be sized according to the application requirements. If the bulk capacitance is implemented

in the application, the user can reduce the value of the local ceramic capacitor to 1 µF.

11 Layout

11.1 Layout Guidelines

•

Place the V_CC, GND, U, V, and W pins with thick traces because high current passes through these traces.

Place the 10-µF capacitor between V_CCand GND, and as close to the V_CCand GND pins as possible.

Place the capacitor between CPP and CPN, and as close to the CPP and CPN pins as possible.

Connect the GND, PGND, and SWGND under the thermal pad.

Keep the thermal pad connection as large as possible, on both the bottom side and top sides. It should be

one piece of copper without any gaps.

•

If EEPROM is programmed, it is okay to leave SCL and SDA floating.

11.2 Layout Example

C_VCC(10 µF)

C_VCP(0.1 µF)

V_CC

W

VCP

CPP

C_CP(10 nF)

CPN

L_{SW_VREG}(47 µH)

SW

W

C_VRE(10 µF)

G

SWGND

VREG

V

V1P8

GND

V3P3

U

C_V1P8(1 µF)

C_V3P3(1 µF)

U

PGND

DIR

SPEED

R_SCL(4.75 kW)

SCL

R_SDA(4.75 kW)

SDA

R_FG(4.75 kW)

FG

Figure 74. Layout Diagram

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12 Device and Documentation Support

12.1 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated devices. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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PACKAGE MATERIALS INFORMATION

www.ti.com

26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DRV10983QPWPRQ1 HTSSOP PWP

DRV10983SQPWPRQ1 HTSSOP PWP

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DRV10983QPWPRQ1

DRV10983SQPWPRQ1

HTSSOP

PWP

24

2000

350.0

43.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

PWP 24

4.4 x 7.6, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224742/B

www.ti.com

PACKAGE OUTLINE

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

22X 0.65

PLANE

24

1

2X

7.9

7.7

7.15

NOTE 3

12

B

13

0.30

24X

4.5

4.3

0.19

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 2.08 MAX

NOTE 5

4X 0.3 MAX

13

4X 0.1 MAX

NOTE 5

12

0.25

GAGE PLANE

1.2 MAX

5.26

5.11

25

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

1

24

3.20

3.05

4225860/A 04/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(3.2)

METAL COVERED

BY SOLDER MASK

SYMM

24X (1.5)

1

24

24X (0.45)

SEE DETAILS

(R0.05) TYP

(5.26)

22X (0.65)

SYMM

25

(7.8)

NOTE 9

(1.2) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

13

12

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4225860/A 04/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0024J

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.2)

BASED ON

0.125 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

24X (1.5)

1

24

24X (0.45)

(R0.05) TYP

22X (0.65)

SYMM

(5.26)

25

BASED ON

0.125 THICK

STENCIL

12

13

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.58 X 5.88

3.20 X 5.26 (SHOWN)

2.92 X 4.80

0.125

0.15

0.175

2.70 X 4.45

4225860/A 04/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV10983-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 12V 电池、3.5A 峰值无传感器正弦控制三相 BLDC 电机驱动器电池电机驱动传感器驱动器
文件：	总77页 (文件大小：2502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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