DRV2510QPWPRQ1 [TI]
适用于螺线管且具有集成诊断和负载突降保护功能的汽车类 3A 触觉驱动器 | PWP | 16 | -40 to 125;
| 型号： | DRV2510QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于螺线管且具有集成诊断和负载突降保护功能的汽车类 3A 触觉驱动器 | PWP | 16 | -40 to 125 驱动 驱动器 |
| 文件： | 总33页 (文件大小：3125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
DRV2510-Q1 适用于螺线管和音圈且集成诊断功能的 3A 汽车类触觉驱动
器评
1 特性
3 说明
1
•
•
•
•
•
•
宽工作电压范围 (5V - 18V)
DRV2510-Q1 器件是一款专为感性负载（例如，螺线
管和音圈）而设计的大电流触觉驱动器。
集成负载突降保护 (40V)
大电流驱动（峰值电流达 3A）
低 RDS(on)，完整 H 桥输出
集成诊断
输出级含一个完整 H 桥，能够提供 3A 峰值电流。
DRV2510-Q1 器件提供欠压闭锁、过流保护和过热保
护等多种保护功能。
集成故障保护
–
–
–
–
–
40V 负载突降保护，符合 ISO-7637-2 标准
DRV2510-Q1 器件符合汽车类产品标准。集成的突降
保护可降低外部电压钳位组件的成本和尺寸，板载负载
诊断会通过数字接口报告致动器状态。
短路保护
过热保护
过压和欠压保护
故障报告
器件信息(1)
器件型号
封装
封装尺寸（标称值）
•
•
•
•
•
模拟输入
I2C 通信
DRV2510-Q1
HTSSOP (16)
5.00 mm x 4.40 mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
专用中断引脚
符合汽车级 (Q100) 标准
环境温度范围：–40ºC 至 125ºC
简化电路原理图
VDD
BSTP
OUT+
2 应用
•
电磁致动器驱动器
–
–
音圈
螺线管
•
•
机械按钮替代产品
汽车类触觉 应用
EN
STDBY
–
–
–
–
–
信息娱乐
中央控制台
方向盘
INTZ
SDA
SCL
Solenoid/
Voice-Coil
M
车门板
座椅
IN+
IN-
OUTœ
REG
GND
BSTN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS919
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
目录
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 11
7.6 Register Map........................................................... 15
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 器件支持 ............................................................... 23
11.2 商标....................................................................... 23
11.3 静电放电警告......................................................... 23
11.4 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2016) to Revision A
Page
•
发布为量产数据。................................................................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
5 Pin Configuration and Functions
TWP
HTSSOP 16-Pin With Thermal Pad
Top View
GND
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VDD
REG
SDA
SCL
INTZ
BSTP
OUT+
OUT-
BSTN
GND
IN+
IN-
STDBY
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
NO.
1, 9, 16
2
P
I
Ground.
EN
Device enable pin.
Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1
µF X7R ceramic decoupling capacitor and the MODE resistor divider.
REG
3
P
I2C data.
SDA
4
5
I
I
I2C clock.
SCL
IN+
6
I
Positive differential input.
IN-
7
I
Negative differential input.
STDBY
BSTN
OUT-
OUT+
BSTP
8
I
Standby pin.
10
11
12
13
P
O
O
P
Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUT-.
Negative output.
Positive output.
Boot strap for positive output, connect to 220 nF X5R, or better ceramic cap to OUT+.
General fault reporting. Open drain.
INTZ = High, normal operation
INTZ = Low, fault condition
INTZ
14
15
O
VDD
P
Power supply.
Thermal Pad
G
Connect to GND for best system performance. If not connected to GND, leave floating.
Copyright © 2016, Texas Instruments Incorporated
3
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–1
MAX
30
40
15
5
UNIT
V
VDD DC supply voltage range
Supply voltage
Input voltage, VI
Current
VDD pulsed supply voltage range. t < 400 ms exposure
VDD supply voltage ramp rate
SCL, SDA, EN
V/ms
V
–0.3
–0.3
–4
IN+, IN-, STDBY
6.5
4
DC current on VDD, GND, OUT+, OUT-
Maximum current in all input pins
Maximum sink current for open-drain pins
A
–1
1
mA
7
Operating free-air temperature, TA
Storage temperature range, Tstg
–40
–55
125
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±3500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
NOM
MAX
UNIT
V
VDD
VIH
VIL
Supply voltage. VDD.
18
High-level input voltage. SDA, SCL, STDBY, EN.
Low-level input voltage. SDA, SCL, STDBY, EN
Low-level output voltage
2.1
V
0.7
0.4
V
VOL
VOH
IIH
V
High-level output voltage
2.4
V
High-level input current. SDA, SCL, STDBY, EN
Minimum load Impedance
50
µA
Ω
RL
1.5
CB
Load capacitance for each bus line (SDA/SCL)
400
pF
6.4 Thermal Information
DRV2510-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
{16} PINS
39.4
24.9
20
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
19.8
2
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
6.5 Electrical Characteristics
TA = 25°C, AVCC = VDD = 12 V, RL = 5 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output offset voltage (measured
differentially)
| VOS
IVDD
|
VI = 0 V, Gain = 20 dB
No load or filter
–25
25
mV
mA
µA
Quiescent supply current
16
5
Quiescent supply current in shutdown
mode
IVDD(SD)
No load or filter
20
IVDD(STD
BY)
Quiescent supply current in standby mode No load or filter
7
mA
Drain-source on-state resistance,
TJ = 25°C
rDS(on)
180
mΩ
measured pin to pin
19
25
31
35
6.4
20
26
21
27
33
37
7.4
dB
dB
G
Gain
P(o) = 1 W
32
36
VREG
VO
Regulator voltage
6.9
20
V
V
Output voltage (measured differentially)
Power supply ripple rejection
Input common-mode min
PSRR
VICMIN
VDD = 12 V + 1 Vrms at 1 kHz
75
dB
V
0.3
4.4
VICMAX Input common-mode max
f = 1 kHz, 100 mVrms referenced to GND. Gain =
20 dB
CMRR Common-mode rejection ratio
63
dB
400
500
10
Oscillator frequency
fOSC
kHz
(with PWM duty cycle < 96%)
Output resistance in shutdown
MΩ
Resistance to detect a short from OUT
pin(s) to VDD or GND
200
Ω
Open-circuit detection threshold
Short-circuit detection threshold
Power-on threshold
75
95
1.2
4.1
150
15
120
1.5
Ω
Ω
V
0.9
Thermal trip point
°C
°C
A
Thermal hysteresis
Over-current trip point
Over-voltage trip point
Over-voltage hysteresis
Under-voltage trip point
Under-voltage hysteresis
3.5
21
V
0.6
4
V
V
0.25
V
6.6 Timing Requirements
TA = 25 °C, VDD = 3.6 V (unless otherwise noted)
MIN
NOM
MAX
400
UNIT
ƒ(SCL)
tw(H)
tw(L)
Frequency at the SCL pin with no wait states
kHz
µs
µs
ns
ns
µs
µs
µs
µs
Pulse duration, SCL high
0.6
1.3
100
300
1.3
0.6
0.6
0.6
Pulse duration, SCL low
tsu(1)
th(1)
Setup time, SDA to SCL
Hold time, SCL to SDA
t(BUF)
tsu(2)
th(2)
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
tsu(3)
Copyright © 2016, Texas Instruments Incorporated
5
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
t
t
w(L)
w(H)
{/[
t
su(1)
t
h(1)
{5!
Figure 1. SCL and SDA Timing
{/[
t
t
t
su(3)
h(2)
su(2)
t
(BUF)
{5!
{tart /ondition
{top /ondition
Figure 2. Timing for Start and Stop Conditions
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
229
47
MAX UNIT
Turn-on time from shutdown to
waveform
ton-sd
EN = Low to High, STBY = Low
EN = High to Low
ms
µs
µs
tOFF-sd
ton-stdby
Turn-off time
Turn-on time from standby to
waveform
EN = High, STBY = High to Low
32
6.8 Typical Characteristics
24.0
20.0
16.0
12.0
8.0
10
9
8
7
6
4.0
5
0.0
4
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
VDD − Supply Voltage (V)
VDD − Supply Voltage (V)
图 3. Shutdown Current vs VDD Voltage
图 4. Standby Current vs VDD Voltage
6
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
7 Detailed Description
7.1 Overview
The DRV2510-Q1 device is a high current haptic driver specifically designed for inductive loads, such as
solenoids and voice coils.
The output stage consists of a full H-bridge capable of delivering 3 A of peak current.
The design uses an ultra-efficient switching output technology developed by Texas Instruments, but with features
added for the automotive industry. The DRV2510-Q1 device provides protection functions such as undervoltage
lockout, over-current protection and over-temperature protection. This technology allows for reduced power
consumption, reduced heat, and reduced peak currents in the electrical system.
The DRV2510-Q1 device is automotive qualified. The integrated load-dump protection reduces external voltage
clamp cost and size, and the onboard load diagnostics report the status of the actuator through the digital
interface.
7.2 Functional Block Diagram
REG
VDD
BSTP
OUT+
Reg
VDD
Digital Core
EN
STDBY
SDA
POR
Control
Gate
Drive
Reg
Map
SCL
I2C
INTZ
Solenoid/
Voice-Coil
M
Interrupt
Control
VDD
Load
Diagnostics
OT
Thermal
Protection
OUTœ
Gate
Drive
VDD
VDD
OVV
Critical
Condition
Control
OSC
UVLO
OC
BSTN
Over-Current
Protection
PWM
Logic
Freq_Sel
IN+
IN-
Gain
Control
GND
版权 © 2016, Texas Instruments Incorporated
7
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
7.3 Feature Description
7.3.1 Analog Input and Configurable Pre-amplifier
The DRV2510-Q1 device features a differential input stage that cancels common-mode noise that appears on
the inputs. The DRV2510-Q1 device also features four gain settings that are configurable via I2C. Please see the
Programming Sections for register locations.
表 1. Gain Configuration Table
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
60 kΩ
30 kΩ
15 kΩ
9 kΩ
7.3.2 Pulse-Width Modulator (PWM)
The DRV2510-Q1 device features BD modulation scheme with high bandwidth, low noise, low distortion, and
excellent stability.
The BD modulation scheme allows for smaller ripple currents through the load. Each output switches from 0 V to
the supply voltage. With no input, the OUT+ and OUT- pins are in phase with each other so that there is little or
no current in the load. For positive differential inputs, the duty cycle of OUT+ is greater than 50% and the duty
cycle of OUT- is lower than 50% for a positive differential output voltage. The opposite is true for negative
differential inputs. The voltage accross the load sits at 0 V throughout most of the switching period, reducing the
switching current, which reduces the I2R losses in the load.
8
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
No Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
Positive Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
Negative Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
图 5. BD Mode Modulation
7.3.3 Designed for low EMI
The DRV2510-Q1 device design has minimal parasitic inductances due to the short leads on the package. This
dramatically reduces EMI that results from current passing from the die to the system PCB. The design
incorporates circuitry that optimizes output transitions that causes EMI. Follow the recommended design
requirements in the Design Requirements section.
7.3.4 Device Protection Systems
The DRV2510-Q1 device features a complete set of protection circuits carefully designed to protect the device
against permanent failures due to shorts, over-temperature, over-voltage, and under-voltage scenarios. The INTZ
pin signals if an error is detected.
Additionally, the DRV2510-Q1 device is not damaged by adjacent pin to pin shorts.
版权 © 2016, Texas Instruments Incorporated
9
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
表 2. Fault Reporting Table
FAULT
TRIGGERING CONDITION
INTZ
ACTION
output in high impedance.
I2 updated.
Over-current
Output short or short to VDD or GND
pulled low
output in high impedance.
Recovery is automatic
once the temperature
returns to a safe level.
Over-temperature
Tj > 150 ºC
pulled low
output in high impedance.
I2 reset.
Under-voltage
Over-voltage
VDD < 4 V
pulled low
pulled low
output in high impedance.
I2 updated.
VDD > 21 V
7.3.4.1 Diagnostics
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output
connections. The device supports the following diagnostics:
•
•
•
•
Short to GND
Short to VDD
Short across load
Open load
The device reports the presence of any of the short or open conditions to the system via I2C register read.
1. Load Diagnostics—The load diagnostic function runs on de-assertion of EN or when the device is in a fault
state (dc detect, overcurrent, overvoltage, undervoltage, and overtemperature). During this test, the outputs
are in a Hi-Z state. The device determines whether the output is a short to GND, short to VDD, open load, or
shorted load. The load diagnostic biases the output, which therefore requires limiting the capacitance value
for proper functioning. The load diagnostic test takes approximately 229 ms to run. Note that the check
phase repeats up to five times if a fault is present or a large capacitor to GND is present on the output. On
detection of an open load, the output still operates. On detection of any other fault condition, the output goes
into a Hi-Z state, and the device checks the load continuously until removal of the fault condition. After
detection of a normal output condition, the output starts. The load diagnostics run after every other
overvoltage (OV) event. The load diagnostic for open load only has I2C reporting. All other faults have I2C
and INTZ pin assertion.
The device performs load diagnostic tests as shown in 图 6.
图 7 illustrates how the diagnostics determine the load based on output conditions.
Discharge
(75 ms)
Ramp Up
(52 ms)
Check
(50 ms)
Ramp Down
(52 ms)
图 6. Load Diagnostics Sequence of Events
10
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
Output Conditions
Open Load
Load Diagnostics
Open Load Detected
OL Max
OL Min
SL Max
SL Min
Normal or Open Load
May Be Detected
Open Load (OL)
Detection Threshold
Normal
Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Detected
Shorted
Load
图 7. Load Diagnostic Reporting Thresholds
2. Faults During Load Diagnostics—If the device detects a fault (overtemperature, overvoltage, undervoltage)
during the load diagnostics test, the device exits the load diagnostics, which may result in a small transient
on the output.
7.4 Device Functional Modes
The DRV2510-Q1 device has multiple power states to optimize power consumption.
7.4.1 Operation in Shutdown Mode
The NRST pin of the DRV2510-Q1 device puts the device in a shutdown mode. When NRST is asserted (logic
low), all internal blocks of the device are off to achieve ultra low power. I2C is not operational in this mode and
the output is in Hi-Z state.
7.4.2 Operation in Standby Mode
The STDBY pin of the DRV2510-Q1 device puts the device in a standby mode. When STDBY is asserted (logic
high), some internal blocks of the device are off to achieve low power while preserving the ability to wake up
quickly to achieve low latency waveform playback.
7.4.3 Operation in Active Mode
The DRV2510-Q1 device is in active mode when it has a valid supply, and it is not in either shutdown or standby
modes. In this mode the DRV2510-Q1 device is fully on and reproducing at the output the input times the gain.
7.5 Programming
7.5.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with
the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the
SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period. 图 8 shows a typical sequence. The master device generates the 7-bit
版权 © 2016, Texas Instruments Incorporated
11
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
Programming (接下页)
slave address and the read-write (R/W) bit to start communication with a slave device. The master device then
waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock
period to indicate acknowledgment. When the acknowledgment occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible
devices share the same signals through a bidirectional bus using a wired-AND connection.
The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word
transfers, the master generates a stop condition to release the bus. 图 8 shows a generic data-transfer
sequence.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull-up resistors
between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2510-
Q1 supply voltage, VDD
.
注
The DRV2510-Q1 slave address is 0x6C (7-bit), or 1101100 in binary.
8-bit register data for address
8-bit register data for address
7-bit slave address
A
8-bit register address (N)
A
A
A
R/W
(N)
(N)
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
{tart
{top
图 8. Typical I2C Sequence
The DRV2510-Q1 device operates as an I2C-slave 1.8-V logic thresholds, but can operate up to the VDD voltage.
The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5
(8-bit) for reading.
7.5.2 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.
During multiple-byte read operations, the DRV2510-Q1 device responds with data one byte at a time and begins
at the signed register. The device responds as long as the master device continues to respond with
acknowledges.
The DRV2510-Q1 supports sequential I2C addressing. For write transactions, a sequential I2C write transaction
has taken place if a register is issued followed by data for that register as well as the remaining registers that
follow. For I2C sequential-write transactions, the register issued then serves as the starting point and the amount
of data transmitted subsequently before a stop or start is transmitted determines how many registers are written.
7.5.3 Single-Byte Write
As shown in 图 9, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read-write bit. The read-write bit determines the direction of the data
transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I2C device
address and the read-write bit, the DRV2510-Q1 responds with an acknowledge bit. Next, the master transmits
the register byte corresponding to the DRV2510-Q1 internal-memory address that is accessed. After receiving
the register byte, the device responds again with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single-byte data-write transfer.
12
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
Programming (接下页)
!cknowledge
!cknowledge
!cknowledge
!7 !6 !ꢀ
!6 !ꢀ !4 !3 !2 !1 !0
í
!/Y
!4 !3 !2 !0 !1 !/Y 57 56 5ꢀ 54 53 52 51 50 !/Y
2
{top
condition
{ubaddress
5ata byte
{tart
condition
I C device address
and R/W bit
图 9. Single-Byte Write Transfer
7.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DRV2510-Q1 device as shown in 图 10. After receiving each data
byte, the DRV2510-Q1 device responds with an acknowledge bit.
!cknowledge
!cknowledge
!cknowledge
!cknowledge
!cknowledge
!1
!0
!1
!0
í
!/Y !7 !6
!1
!0 !/Y 57 56
51 50 !/Y 57
50 !/Y 57
50 !/Y
{top
condition
2
{tart
condition
{ubaddress
Cirst data byte
htꢀer data bytes
[ast data byte
I C device address
and R/W bit
图 10. Multiple-Byte Write Transfer
7.5.5 Single-Byte Read
图 11 shows that a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read-write bit. For the data-read transfer, both a write followed by a
read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be
read. As a result, the read-write bit is set to 0.
After receiving the DRV2510-Q1 address and the read-write bit, the DRV2510-Q1 device responds with an
acknowledge bit. The master then sends the internal memory address byte, after which the device issues an
acknowledge bit. The master device transmits another start condition followed by the DRV2510-Q1 address and
the read-write bit again. On this occasion, the read-write bit is set to 1, indicating a read transfer. Next, the
DRV2510-Q1 device transmits the data byte from the memory address that is read. After receiving the data byte,
the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data
read transfer. See the note in the General I2C Operation section.
!cknowledge
!cknowledge
!cknowledge
!cknowledge
!/Y
!/Y
!/Y
!6
!5
!1
!0
í
!7
!6
!1
!0
!6
!5
!0
ꢁ
ꢀ7
ꢀ0 !/Y
2
2
{tart
/ondition
{ubaddress
ꢁepeat start
condition
ꢀata .yte
{top
/ondition
I C device address and
R/W bit
I C device address and
R/W bit
图 11. Single-Byte Read Transfer
7.5.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the DRV2510-Q1 device to the master device as shown in 图 12. With the exception of the
last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Copyright © 2016, Texas Instruments Incorporated
13
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
Programming (接下页)
!cknowledge
!cknowledge
!cknowledge
!cknowledge
ꢂ0 !/Y ꢂ7
!cknowledge
ꢂ0 !/Y ꢂ7
!cknowledge
!6
!0
!/Y !7 !6
!1 !0 !/Y
!6 !5
!0
!/Y ꢂ7
ꢂ0 !/Y
í
ꢀ
2
2
{top
condition
ꢀepeat start
condition
{tart
condition
{ubaddress
Cirst data byte
htꢁer data byte
[ast data byte
I C device address
and R/W bit
I C device address
and R/W bit
图 12. Multiple-Byte Read Transfer
14
Copyright © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
7.6 Register Map
Table 3. Register Map Overview
REG
DEFAULT
NO.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x00
0x01
0x00
0x00
Reserved
LOAD_DIAG
Reserved
OVER_TEMP
DEV_ACTIVE
Reserved
STDBY
OVER_VOLT
UNDER_VOLT
FAULT
OVER_CURR
LOAD_SHORT
Reserved
Reserved
LOAD_SHORT_
GND
LOAD_SHORT_
VDD
0x02
0x03
0x00
0x00
DIAG_ACTIVE
LOAD_OPEN
GAIN[1:0]
FREQ_SEL
7.6.1 Address: 0x00
Figure 13. 0x00
7
6
5
4
3
2
1
0
Reserved
LOAD_DIAG[0]
RO-0
Reserved
Table 4. Address: 0x00
BIT
7-3
2
FIELD
TYPE DEFAULT DESCRIPTION
Reserved
LOAD_DIAG
RO
0
Shows the status of the load diagnostics.
0
1
An open or short has not been detected.
An open or short was detected.
1-0
Reserved
7.6.2 Address: 0x01
Figure 14. 0x01
7
6
5
4
3
2
1
Reserved
0
OVER_TEMP[0
]
Reserved
OVER_VOLT[0] UNDER_VOLT[ OVER_CURR[0
0]
]
RO-0
RO-0
RO-0
RO-0
Table 5. Address: 0x01
BIT
FIELD
TYPE DEFAULT DESCRIPTION
7
OVER_TEMP
RO
0
Shows the current statuts of the thermal protection
0
1
Temperature is below the over-temperature threshold.
Temperature is above the over-temperature threshold.
6
5
Reserved
OVER_VOLT
RO
RO
RO
0
0
0
Shows the status of the over-voltage protection.
0
1
VDD voltage is below the over-voltage threshold.
VDD voltage is above the over-voltage threshold.
4
3
UNDER_VOLT
OVER_CURR
Reserved
Shows the status of the under-voltage protection.
0
1
VDD voltage is above the under-voltage threshold.
VDD voltage is below the under-voltage threshold.
Shows the status of the over-current protection.
0
1
An over-current event has not occured.
Device shutdown due to over-current.
2-0
Copyright © 2016, Texas Instruments Incorporated
15
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
7.6.3 Address: 0x02
Figure 15. 0x02
7
6
5
4
3
2
1
0
DEV_ACTIVE[0
]
STDBY[0]
DIAG_ACTIVE[
0]
FAULT[0]
LOAD_SHORT[ LOAD_OPEN[0 LOAD_SHORT LOAD_SHORT
0]
]
_GND[0]
_VDD[0]
RO-0
RO-0
RO-0
RO-0
RO-0
RO-0
RO-0
RO-0
Table 6. Address: 0x02
BIT
FIELD
TYPE DEFAULT DESCRIPTION
7
DEV_ACTIVE
RO
RO
RO
RO
0
0
0
0
Shows the device status (active or shutdown).
0
1
Device is shutdown.
Device is active.
6
5
4
STDBY
Shows the device standby status.
0
1
Device is not on standby.
Device is on standby.
DIAG_ACTIVE
FAULT
Shows the status of the diagnositcs engine.
0
1
Not performing load diagnostics.
Performing load diagnostics.
Shows if a fault has occured on the system. Either over-voltage, under-voltage, over-current,
over-temperature.
0
1
No fault has occured.
A fault has occured.
3
2
1
0
LOAD_SHORT
RO
RO
RO
RO
0
0
0
0
Shows whether the output is shorted.
0
1
OUT+ is not shorted to OUT-.
OUT+ is shorted to OUT-.
LOAD_OPEN
Shows whether the output has a proper load connected.
0
1
A proper load is connected between OUT+ and OUT-.
There is an open connection between OUT+ and OUT-.
LOAD_SHORT_GND
LOAD_SHORT_VDD
Shows whether the output is shorted to GND.
0
1
Output is not shorted to GND.
Either OUT+ or OUT- is shorted to GND.
Shows whether the output is shorted to VDD.
0
1
Output is not shorted to VDD.
Either OUT+ or OUT- is shorted to VDD.
16
Copyright © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
7.6.4 Address: 0x03
Figure 16. 0x03
7
6
5
4
3
2
1
0
GAIN[1:0]
Reserved
FREQ_SEL[0]
R/W-0
R/W-0
R/W-0
Table 7. Address: 0x03
BIT
FIELD
TYPE DEFAULT DESCRIPTION
R/W 0 Sets the gain of the driver.
7-6
GAIN[1:0]
0
1
2
3
20 dB.
26 dB.
32 dB.
36 dB.
5-1
0
Reserved
FREQ_SEL
R/W
0
Sets the output frequency.
0
1
400 kHz.
500 kHz.
版权 © 2016, Texas Instruments Incorporated
17
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV2510-Q1 device is a high-efficiency driver for inductive loads, such as solenoids and voice-coils. The
typical use of the device is on haptic applications where short, strong waveforms are desired to create a haptic
event that will be coming from the application processor.
8.2 Typical Applications
8.2.1 Single-Ended Source
To use the DRV2510-Q1 with a single-ended source, apply either a voltage divider to bias INB to 3 V, tie to GND
or use a 0.1-μF cap from INB to GND to have the device self bias. Apply the single-ended signal to the INA pin.
C2
VDD
BSTP
OUT+
C1
Optional
L1
Application
Processor
R
R
R
(PU) (PU) (PU)
EN
GPIO
STDBY
C7
GPIO
GPIO
SDA
SCL
R1
INTZ
SDA
SCL
C4
C5
Solenoid/
Voice-Coil
M
IN+
IN-
PWM+
LPF
R2
L2
OUTœ
C9
REG
GND
C8
C6
C3
BSTN
Optional
图 17. Typical Application Schematic
8.2.1.1 Design Requirements
For most applications the following component values found in 表 8 below can be used.
18
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
Typical Applications (接下页)
表 8. Component Requirements Table
COMPONENT
C1
DESCRIPTION
SPECIFICATION
Capacitance
TYPICAL VALUE
Supply capacitor
Boost capacitor
22 µF, 10 µF, and 0.1 µF
C2/C3
C4/C5
C6
Capacitance
Capacitance
Capacitance
Capacitance
Resistance
Resistance
0.22 µF
470 pF
1 µF
Output snubber capacitor
Regulator capacitor
Input decoupling capacitor
Output snubber resistor
Pull-up resistor
C9
0.1 µF
3.3 Ω
R1/R2
R(PU)
100 kΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Optional Components
Note that in the diagrams, there are a few optional external components. These optional external components
may be needed in the application to meet EMI/EMC standards and specifications by filters necessary frequency
spectrums.
8.2.1.2.2 Capacitor Selection
A bulk bypass capacitor should be mounted between VBAT and GND. The capacitance needs to be >22 uF with
a X5R or better rating on the power pins to GND. Also include two ceramic capacitors in the ranges of 220 pF to
1 uF and 100 nF to 1 uF. The bootstrap capacitors, BSTA and BSTB, should be 220-nF ceramic capacitors of
quality X5R or better rated for at least the maximum rating of the pin.
8.2.1.2.3 Solenoid Selection
The DRV2510-Q1 solenoid driver can accommodate a variety of solenoids. Solenoids should have an equivalent
resistance of 1.6 Ω or greater. Solenoids with lower resistances are prone to driving high currents. A maximum
peak current of 3-A should not be exceeded.
8.2.1.2.4 Output Filter Considerations
The output filter is optional and is mainly for limiting peak currents. A second-order Butterworth low-pass filter
with the cut-off frequency set to a few kilohertz should be sufficient. See 公式 2, 公式 3, and 公式 4 for example
filter design.
1
H(s) =
s2 + 2s +1
(1)
2 ´RL
Lx
=
2wo
(2)
2
2´ CF =
RL
2´
´ w0
2
(3)
(4)
w0 = 2p´ ƒ
8.2.1.3 Application Curves
These application curves were taken using an HA200 solenoid with a 100-g mass, and the acceleration was
measured using the DRV-AAC16-EVM accelerometer. The following scales apply to the graphs:
•
•
•
Output Differential Voltage scale is shown on the plots at 5-V/div
Acceleration scale is 5.85-G/div
Current scale is 2-A/div
版权 © 2016, Texas Instruments Incorporated
19
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
Acceleration
Input
Acceleration
Current
[OUT+] − [OUT−]
[OUT+] − [OUT−]
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
图 18. Voltage and Acceleration vs Time (Input Square
图 19. Voltage and Acceleration vs Time (Square Wave)
Wave)
Acceleration
Current
Acceleration
Current
[OUT+] − [OUT−]
[OUT+] − [OUT−]
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
图 20. Voltage and Acceleration vs Time (Ramp Wave)
图 21. Voltage and Acceleration vs Time (1/2 Sine Wave)
8.2.1.4 Differential Input Diagram
To use the DRV2510-Q1 with a differential input source, apply both inputs differentially from a control source
(GPIO, DAC, etc...).
20
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
C2
VDD
BSTP
OUT+
C1
Optional
L1
Application
Processor
R
R
R
(PU) (PU) (PU)
EN
GPIO
GPIO
GPIO
SDA
STDBY
C7
R1
INTZ
SDA
SCL
C4
Solenoid/
M
Voice-Coil
SCL
C5
IN+
IN-
PWM+
PWM-
LPF
R2
L2
LPF
OUTœ
REG
GND
C8
C6
C3
BSTN
Optional
图 22. Typical Application Schematic
版权 © 2016, Texas Instruments Incorporated
21
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
9 Power Supply Recommendations
The DRV2510-Q1 device operates from 5 V - 18 V and this supply should be able to handle high surge currents
in order to meet the high currrent draws for haptics effects. Additionally the DRV2510-Q1 should have 22-µF, 10-
µF and 0.1-µF ceramic capacitors near the VDD pin for additional decoupling from trace routing.
10 Layout
10.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The DRV2510-Q1 device has a
thermal pad down, and good thermal conduction and dissipation require adequate copper area. Layout also
affects EMC performance. It is best practice to use the same/similiar layout as shown below in the
DRV2510Q1EVM.
10.2 Layout Example
图 23. DRV2510-Q1 EVM
22
版权 © 2016, Texas Instruments Incorporated
DRV2510-Q1
www.ti.com.cn
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 商标
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016, Texas Instruments Incorporated
23
DRV2510-Q1
ZHCSFB0A –JUNE 2016–REVISED JUNE 2016
www.ti.com.cn
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2016, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV2510QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV2510
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV2510QPWPRQ1
HTSSOP PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DRV2510QPWPRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X 0.15 MAX
NOTE 5
2X 0.95 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.0
2.4
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.0
2.4
4218971/A 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
SYMM
(3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218971/A 01/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3)
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.35 X 3.35
3 X 3 (SHOWN)
2.74 X 2.74
0.125
0.15
0.175
2.54 X 2.54
4218971/A 01/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
DRV2603
Haptic Driver with Auto Resonance Tracking for Linear Resonance Actuators (LRA) and Optimized Drive for Eccentric Rotating Mass Actuators (ERM)
TI
DRV2603RUNR
Haptic Driver with Auto Resonance Tracking for Linear Resonance Actuators (LRA) and Optimized Drive for Eccentric Rotating Mass Actuators (ERM)
TI
DRV2603RUNT
Haptic Driver with Auto Resonance Tracking for Linear Resonance Actuators (LRA) and Optimized Drive for Eccentric Rotating Mass Actuators (ERM)
TI
©2020 ICPDF网 联系我们和版权申明