DRV2511QDAPRQ1 [TI]
适用于螺线管且具有集成故障保护功能的汽车类 8A 触觉驱动器 | DAP | 32 | -40 to 125;
| 型号： | DRV2511QDAPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于螺线管且具有集成故障保护功能的汽车类 8A 触觉驱动器 | DAP | 32 | -40 to 125 驱动 驱动器 |
| 文件： | 总27页 (文件大小：3178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
DRV2511-Q1 适用于螺线管和音圈的 8A 汽车类触觉驱动器
1 特性
3 说明
1
•
宽工作电压范围 (4.5V - 26V)
能够处理 30V 电压
DRV2511-Q1 器件是一款专为感性负载（例如，螺线
管和音圈）而设计的大电流触觉驱动器。
•
•
•
•
大电流驱动（峰值电流达 8A）
低 RDS(on)，完整 H 桥输出
集成故障保护
输出级含一个完整 H 桥，能够提供 8A 峰值电流。
DRV2511-Q1 器件提供欠压闭锁、过流保护和过热保
护等多种保护功能。
–
–
–
–
短路保护
过热保护
DRV2511-Q1 器件符合汽车类产品标准。
过压和欠压保护
故障报告
器件信息(1)
器件型号
封装
封装尺寸（标称值）
•
•
•
模拟输入
DRV2511-Q1
HTSSOP (32)
11 mm x 6.20 mm
专用中断引脚
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
具有符合 AEC-Q100 标准的下列结果：
–
–
–
器件温度 1 级：-40°C 至 125°C
的环境运行温度范围
简化电路原理图
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
PVDD
AVDD
BSTP
器件组件充电模式 (CDM) ESD 分类等级 C4B
2 应用
•
电磁致动器驱动器
OUT+
–
–
音圈
EN
螺线管
STDBY
•
•
机械按钮替代产品
汽车类触觉 应用
INTZ
FS2
FS1
FS0
IN+
Solenoid/
Voice-Coil
M
–
–
–
–
–
信息娱乐
中央控制台
方向盘
车门板
IN-
座椅
OUT
GAIN
REG
BSTN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS916
DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
Power Supply Recommendations...................... 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 器件和文档支持 ..................................................... 17
11.1 器件支持 ............................................................... 17
11.2 商标....................................................................... 17
11.3 静电放电警告......................................................... 17
11.4 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 18
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2016) to Revision A
Page
•
发布为量产数据。................................................................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
5 Pin Configuration and Functions
DAP Package
32-Pin HTSSOP
Top View
GND
EN
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDD
2
PVDD
BSTP
OUT+
GND
INTZ
IN+
3
4
IN-
5
REG
REG
GAIN
GND
GND
GND
STDBY
FS2
6
OUT+
BSTP
GND
7
8
9
BSTN
OUT-
GND
10
11
12
13
14
15
16
OUT-
BSTN
PVDD
PVDD
AVDD
FS1
FS0
N/C
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
EN
NO.
1, 9, 10, 11,
22, 25, 28
P
I
Ground.
2
Device enable pin.
General fault reporting. Open drain.
INTZ = High, normal operation
INTZ = Low, fault condition
INTZ
3
O
IN+
IN-
4
5
I
I
Positive differential input.
Negative differential input.
Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a
1 µF X7R ceramic decoupling capacitor and the MODE resistor divider.
REG
6, 7
P
GAIN
STDBY
FS2
8
I
I
Selects Gain.
12
Standby pin.
13
14
I
Output switching frequency selection.
FS1
I
Output switching frequency selection.
FS0
15
I
Output switching frequency selection.
N/C
16
N/C
P
P
P
O
P
Pin should be left floating.
AVDD
PVDD
BSTN
OUT-
BSTP
17
Analog Supply, can be connected to VBAT for single power supply operation.
Power supply.
18, 19, 31, 32
20, 24
21, 23
26, 30
Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUT-.
Negative output.
Boot strap for positive output, connect to 220 nF X5R, or better ceramic cap to OUT+.
Copyright © 2016, Texas Instruments Incorporated
3
DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
OUT+
27, 29
O
G
Positive output.
Connect to GND for best system performance. If not connected to GND, leave floating.
Thermal Pad or
PowerPAD™
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–8
MAX
UNIT
Supply voltage
Input voltage, VI
Current
PVDD, AVDD
30
V
IN+, IN-
6.3
VREG + 0.3
PVDD + 0.3
8
GAIN
V
EN
DC current on PVDD, GND, OUT+, OUT-
A
Operating free-air temperature, TA
Storage temperature range, Tstg
–40
–50
125
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–2000
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
–450
450
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
2
NOM
MAX
UNIT
VDD
VIH
Supply voltage. PVDD, AVDD.
26
V
V
V
V
High-level input voltage. STDBY, EN, FS0, FS1, FS2.
Low-level input voltage. STDBY, EN, FS0, FS1, FS2.
Low-level output voltage. INTZ, RPULL-UP = 100 kΩ, PVDD = 26 V.
VIL
0.8
0.8
VOL
High-level input current. STDBY, EN, FS0, FS1, FS2. (VI = 2 V,
PVDD = 26 V).
IIH
50
µA
RL
Lo
Minimum load Impedance.
Output-filter Inductance.
1.65
Ω
1
µH
6.4 Thermal Information
DRV2511-Q1
DAP
THERMAL METRIC(1)
UNIT
32 PINS
32.4
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
Thermal Information (continued)
DRV2511-Q1
THERMAL METRIC(1)
DAP
32 PINS
17.3
0.4
UNIT
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
17.2
1
RθJC(bot)
Copyright © 2016, Texas Instruments Incorporated
5
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ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
TA = 25°C, AVCC = PVDD = 12 V, RL = 5 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
20
Output offset voltage (measured
differentially)
| VOS
IVDD
|
VI = 0 V, Gain = 36 dB
No load or filter
15
mV
mA
µA
Quiescent supply current
Quiescent supply current in shutdown
mode
IVDD(SD)
No load or filter
35
IVDD(STD
BY)
Quiescent supply current in standby mode No load or filter
11
60
mA
Drain-source on-state resistance,
TJ = 25°C
rDS(on)
mΩ
measured pin to pin
R1 = open, R2 = 20 kΩ
19
25
31
35
6.4
20
26
21
27
33
37
7.4
dB
dB
R1 = 100 kΩ, R2 = 20 kΩ
R1 = 100 kΩ, R2 = 39 kΩ
R1 = 75 kΩ, R2 = 47 kΩ
G
Gain
32
36
VREG
BW
Regulator voltage
6.9
60
V
kHz
V
Full Power Bandwidth
VO
Output voltage (measured differentially)
Power supply ripple rejection
Measured at PVDD = 26V
50
PSRR
200 mVpp ripple at 1 kHz, Gain = 20 dB
–70
–56
400
500
600
1000
1200
4.1
28
dB
dB
CMRR Common-mode rejection ratio
FS2 = 0, FS1 = 0, FS0 = 0
FS2 = 0, FS1 = 0, FS0 = 1
FS2 = 0, FS1 = 1, FS0 = 0
FS2 = 0, FS1 = 1, FS0 = 1
FS2 = 1, FS1 = 0, FS0 = 0
376
470
424
530
Oscillator frequency
fOSC
564
636 kHz
(with PWM duty cycle < 96%)
940
1060
1278
V
1128
Power-on threshold
Power-off threshold
Thermal trip point
V
150
15
°C
°C
A
Thermal hysteresis
Over-current trip point
Over-voltage trip point
13
28
V
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
5
MAX
UNIT
ms
µs
Turn-on time from shutdown to
waveform
ton-sd
EN = Low to High, STBY = Low
EN = High to Low
tOFF-sd
ton-stdby
Turn-off time
Turn-on time from standby to
waveform
EN = High, STBY = High to Low
6
µs
6
版权 © 2016, Texas Instruments Incorporated
DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
6.7 Typical Characteristics
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
28.00
26.00
24.00
22.00
20.00
18.00
16.00
14.00
12.00
4
6
8
10
12
14
16
18
20
22
24
26
4
6
8
10
12
14
16
18
20
22
24
26
VDD − Supply Voltage (V)
VDD − Supply Voltage (V)
图 1. Shutdown Current vs VDD Voltage
图 2. Standby Current vs VDD Voltage
版权 © 2016, Texas Instruments Incorporated
7
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ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DRV2511-Q1 device is a high current haptic driver specifically designed for inductive loads, such as
solenoids and voice coils.
The output stage consists of a full H-bridge capable of delivering 8 A of peak current.
The design uses an ultra-efficient switching output technology developed by Texas Instruments, but with features
added for the automotive industry. The DRV2511-Q1 device provides protection functions such as undervoltage
lockout, over-current protection and over-temperature protection. This technology allows for reduced power
consumption, reduced heat, and reduced peak currents in the electrical system.
The DRV2511-Q1 device is automotive qualified.
7.2 Functional Block Diagram
REG
PVDD
AVDD
BSTP
OUT+
Reg
PVDD
Digital Core
EN
STDBY
INTZ
POR
Control
Gate
Drive
Interrupt
Control
Solenoid/
Voice-Coil
M
OT
Thermal
Protection
PVDD
VDD
VDD
OVV
Critical
Condition
Control
Critical_Event
OUTœ
Gate
Drive
UVLO
OC
OSC
Over-Current
Protection
BSTN
FS2
FS1
FS0
PWM
Logic
IN+
IN-
GAIN
Gain
Control
GND
8
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DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
7.3 Feature Description
7.3.1 Analog Input and Configurable Pre-amplifier
The DRV2511-Q1 device features a differential input stage that cancels common-mode noise that appears on
the inputs. The DRV2511-Q1 device also features four gain settings that are configurable via external resistors.
表 1. Gain Configuration Table
GAIN
20 dB
26 dB
32 dB
36 dB
R1
R2
INPUT IMPEDANCE
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
open
60 kΩ
30 kΩ
15 kΩ
9 kΩ
100 kΩ
100 kΩ
75 kΩ
REG
GAIN
GND
R2
R1
图 3. Gain Configuration
7.3.2 Pulse-Width Modulator (PWM)
The DRV2511-Q1 device features BD modulation scheme with high bandwidth, low noise, low distortion, and
excellent stability.
The BD modulation scheme allows for smaller ripple currents through the load. Each output switches from 0 V to
the supply voltage. With no input, the OUT+ and OUT- pins are in phase with each other so that there is little or
no current in the load. For positive differential inputs, the duty cycle of OUT+ is greater than 50% and the duty
cycle of OUT- is lower than 50% for a positive differential output voltage. The opposite is true for negative
differential inputs. The voltage accross the load sits at 0 V throughout most of the switching period, reducing the
switching current, which reduces the I2R losses in the load.
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DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
No Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
Positive Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
Negative Output
OUT+
OUT-
OUT+ - OUT- 0 V
Solenoid Current 0 A
图 4. BD Mode Modulation
7.3.3 Designed for low EMI
The DRV2511-Q1 device design has minimal parasitic inductances due to the short leads on the package. This
dramatically reduces EMI that results from current passing from the die to the system PCB. The design
incorporates circuitry that optimizes output transitions that causes EMI. Follow the recommended design
requirements in the Design Requirements section.
7.3.4 Device Protection Systems
The DRV2511-Q1 device features a complete set of protection circuits carefully designed to protect the device
against permanent failures due to shorts, over-temperature, over-voltage, and under-voltage scenarios. The INTZ
pin signals if an error is detected.
10
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DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
表 2. Fault Reporting Table
FAULT
TRIGGERING CONDITION
INTZ
ACTION
LATCH?
output in high
impedance
Over-current
Output short or short to PVDD or GND
Tj > 150 ºC
pulled low
Latched
output in high
impedance
Over-temperature
Under-voltage
Over-voltage
pulled low
Latched
output in high
impedance
PVDD < 4.5 V
-
-
Self-clearing
Self-clearing
output in high
impedance
PVDD > 27 V
When the "Latched" conditions happen, the device must be reset with the EN signal in order to clear the fault. If
automatic recovery from these conditions is desired, connect the INTZ pin directly to the EN pin. This allows the
INTZ pin function to automatically drive the EN pin low which clears the latched condition.
7.4 Device Functional Modes
The DRV2511-Q1 device has multiple power states to optimize power consumption.
7.4.1 Operation in Shutdown Mode
The NRST pin of the DRV2511-Q1 device puts the device in a shutdown mode. When NRST is asserted (logic
low), all internal blocks of the device are off to achieve ultra low power.
7.4.2 Operation in Standby Mode
The STDBY pin of the DRV2511-Q1 device puts the device in a standby mode. When STDBY is asserted (logic
high), some internal blocks of the device are off to achieve low power while preserving the ability to wake up
quickly to achieve low latency waveform playback.
7.4.3 Operation in Active Mode
The DRV2511-Q1 device is in active mode when it has a valid supply, and it is not in either shutdown or standby
modes. In this mode the DRV2511-Q1 device is fully on and reproducing at the output the input times the gain.
7.5 Programming
7.5.1 Gain
The DRV2511-Q1 device has a configurable gain that is controlled through external resistors. Please see the
Analog Input and Configurable Pre-amplifier section for more details.
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www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV2511-Q1 device is a high-efficiency driver for inductive loads, such as solenoids and voice-coils. The
typical use of the device is on haptic applications where short, strong waveforms are desired to create a haptic
event that will be coming from the application processor.
8.2 Typical Applications
8.2.1 Single-Ended Source
To use the DRV2511-Q1 with a single-ended source, apply either a voltage divider to bias INB to 3 V, tie to GND
or use a 0.1-μF cap from INB to GND to have the device self bias. Apply the single-ended signal to the INA pin.
PVDD
C2
AVDD
C1
BSTP
OUT+
Optional
L1
Application
Processor
R(PU)
EN
GPIO
STDBY
C7
GPIO
GPIO
GPIO
GPIO
GPIO
PWM+
R1
INTZ
FS2
FS1
FS0
IN+
C4
C5
Solenoid/
Voice-Coil
M
LPF
R2
IN-
L2
OUTœ
GAIN
REG
C9
C8
R(GAIN)
C6
C3
GND
BSTN
Optional
图 5. Typical Application Schematic
8.2.1.1 Design Requirements
For most applications the following component values found in 表 3 below can be used.
12
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DRV2511-Q1
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ZHCSFA9A –JUNE 2016–REVISED JULY 2016
Typical Applications (接下页)
表 3. Component Requirements Table
COMPONENT
DESCRIPTION
SPECIFICATION
TYPICAL VALUE
22 µF and 0.1 µF for
PVDD & AVDD
C1
Supply capacitor
Capacitance
C2/C3
C4/C5
C6
Boost capacitor
Output snubber capacitor
Regulator capacitor
Capacitance
Capacitance
Capacitance
Capacitance
Resistance
Resistance
0.22 µF
470 pF
1 µF
C9
Input decoupling capacitor
Output snubber resistor
Pull-up resistor
0.1 µF
3.3 Ω
R1/R2
R(PU)
100 kΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Optional Components
Note that in the diagrams, there are a few optional external components. These optional external components
may be needed in the application to meet EMI/EMC standards and specifications by filters necessary frequency
spectrums.
8.2.1.2.2 Capacitor Selection
A bulk bypass capacitor should be mounted between VBAT and GND. The capacitance needs to be >22 uF with
a X5R or better rating on the power pins to GND. Also include two ceramic capacitors in the ranges of 220 pF to
1 uF and 100 nF to 1 uF. The bootstrap capacitors, BSTA and BSTB, should be 220-nF ceramic capacitors of
quality X5R or better rated for at least the maximum rating of the pin.
8.2.1.2.3 Solenoid Selection
The DRV2511-Q1 solenoid driver can accommodate a variety of solenoids. Solenoids should have an equivalent
resistance of 1.6 Ω or greater. Solenoids with lower resistances are prone to driving high currents. A maximum
peak current of 8-A should not be exceeded. The DRV2511-Q1 will go into a shutdown mode to protect itself
from overcurrent.
8.2.1.2.4 Output Filter Considerations
The output filter is optional and is mainly for limiting peak currents. A second-order Butterworth low-pass filter
with the cut-off frequency set to a few kilohertz should be sufficient. See 公式 2, 公式 3, and 公式 4 for example
filter design.
1
H(s) =
s2 + 2s +1
(1)
2 ´RL
Lx
=
2wo
(2)
2
2´ CF =
RL
2´
´ w0
2
(3)
(4)
w0 = 2p´ ƒ
8.2.1.3 Application Curves
These application curves were taken using an HA200 solenoid with a 100-g mass, and the acceleration was
measured using the DRV-AAC16-EVM accelerometer. The following scales apply to the graphs:
•
•
•
Output Differential Voltage scale is shown on the plots at 5-V/div
Acceleration scale is 5.85-G/div
Current scale is 2-A/div
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Acceleration
Input
[OUT+] − [OUT−]
Acceleration
Current
[OUT+] − [OUT−]
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
图 6. Voltage and Acceleration vs Time (Input Square
图 7. Voltage and Acceleration vs Time (Square Wave)
Wave)
Acceleration
Current
Acceleration
Current
[OUT+] − [OUT−]
[OUT+] − [OUT−]
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
0
2m
4m
6m
8m 10m 12m 14m 16m 18m 20m
Time (s)
图 8. Voltage and Acceleration vs Time (Ramp Wave)
图 9. Voltage and Acceleration vs Time (1/2 Sine Wave)
8.2.1.4 Differential Input Diagram
To use the DRV2511-Q1 with a differential input source, apply both inputs differentially from a control source
(GPIO, DAC, etc...).
14
版权 © 2016, Texas Instruments Incorporated
DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
PVDD
AVDD
C2
BSTP
OUT+
C1
Optional
L1
Application
Processor
R(PU)
EN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PWM+
PWM-
STDBY
C7
R1
INTZ
FS2
FS1
FS0
IN+
C4
C5
Solenoid/
M
Voice-Coil
LPF
R2
IN-
L2
LPF
OUTœ
GAIN
REG
C8
C6
C3
R(GAIN)
GND
BSTN
Optional
图 10. Typical Application Schematic
版权 © 2016, Texas Instruments Incorporated
15
DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
9 Power Supply Recommendations
The DRV2511-Q1 device operates from 4.5 V - 26 V and this supply should be able to handle high surge
currents in order to meet the high currrent draws for haptics effects. Additionally the DRV2511-Q1 should have
22-µF and 0.1-µF ceramic capacitors near the PVDD & AVDD pins for additional decoupling from trace routing.
10 Layout
10.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The DRV2511-Q1 device has a
thermal pad down, and good thermal conduction and dissipation require adequate copper area. Layout also
affects EMC performance. It is best practice to use the same/similiar layout as shown below in the
DRV2511Q1EVM.
10.2 Layout Example
图 11. DRV2511-Q1 EVM
16
版权 © 2016, Texas Instruments Incorporated
DRV2511-Q1
www.ti.com.cn
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 商标
PowerPAD is a trademark of Texas Instruments.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016, Texas Instruments Incorporated
17
DRV2511-Q1
ZHCSFA9A –JUNE 2016–REVISED JULY 2016
www.ti.com.cn
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2016, Texas Instruments Incorporated
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都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV2511QDAPRQ1
ACTIVE
HTSSOP
DAP
32
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV2511Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV2511QDAPRQ1
HTSSOP
DAP
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DAP 32
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DRV2511QDAPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DAP 32
8.1 x 11, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225303/A
www.ti.com
PACKAGE OUTLINE
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
TYP
A
PIN 1 ID AREA
30X 0.65
32
1
11.1
10.9
NOTE 3
2X
9.75
16
B
17
0.30
32X
0.19
6.2
6.0
0.1 C
0.1
C A B
SEATING PLANE
(0.15) TYP
C
SEE DETAIL A
3.04
2.46
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.74
3.16
1.2 MAX
0.75
0.50
0.15
0.05
2X (0.6)
NOTE 5
0 - 8
2X (0.15)
NOTE 5
DETAIL A
TYPICAL
4223691/A 05/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(5.2)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.04)
32X (1.5)
SYMM
SEE DETAILS
1
32
32X (0.45)
30X (0.65)
(11)
NOTE 9
SYMM
(3.74)
(1.2 TYP)
(
0.2) TYP
VIA
(R0.05) TYP
16
17
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(1.3) TYP
(7.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223691/A 05/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAP0032C
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.04)
BASED ON
0.125 THICK
STENCIL
32X (1.5)
1
32
32X (0.45)
30X (0.65)
(3.74)
BASED ON
SYMM
0.125 THICK
STENCIL
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
16
METAL COVERED
BY SOLDER MASK
SYMM
(7.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.40 X 4.18
3.04 X 3.74 (SHOWN)
2.78 X 3.41
0.125
0.15
0.175
2.57 X 3.16
4223691/A 05/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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