DRV425RTJR [TI]
用于开环应用的全集成式磁通门磁传感器 | RTJ | 20 | -40 to 125;
| 型号： | DRV425RTJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于开环应用的全集成式磁通门磁传感器 | RTJ | 20 | -40 to 125 传感器 |
| 文件： | 总39页 (文件大小：1614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
DRV425 磁通门磁场传感器
1 特性
3 说明
1
•
高精度、集成磁通门传感器：
DRV425 专为单轴磁场感测 需要快速切换频率的应
用， 而设计，可实现电气隔离式高灵敏度精密直流和
交流磁场测量。该器件可提供独特且专有的集成磁通门
传感器 (IFG)。该传感器内置一个补偿线圈，支持
±2mT 的高精度感测范围，测量带宽最高可达 47kHz。
该传感器的低偏移、低漂移、低噪声特性与内部补偿线
圈的精确增益、低增益漂移和极低非线性度相结合，可
提供无与伦比的磁场测量精度。DRV425 输出与感测
到的场强成正比的模拟信号。
–
–
–
–
–
–
偏移：±8µT（最大值）
偏移漂移：±5nT/°C（典型值）
增益误差： 0.04%（典型值）
增益漂移：±7ppm/°C（典型值）
线性度：±0.1%
噪声：1.5nT/√Hz（典型值）
•
传感器范围：±2mT（最大值）
范围和增益可通过外部电阻进行调节
–
•
•
可选带宽：47kHz 或 32kHz
DRV425 提供了一组完整 采用，包括内部差分放大
器、片上精密基准以及诊断功能，能够最大限度地减少
组件数量并削减系统级成本。
精密基准：
–
精度：2%（最大值），漂移：50ppm/°C（最大
值）
DRV425 采用带有 PowerPAD™的耐热增强型、无磁
性、超薄四方扁平无引线 (WQFN) 封装来实现优化散
热，并且在 –40°C 至 +125°C 的扩展工业温度范围内
额定运行。
–
–
引脚可选电压：2.5V 或 1.65V
可选比例模式：VDD/2
•
•
诊断 特性: 超限和错误标志
电源电压范围：3.0V 至 5.5V
器件信息 (1)
2 应用
部件号
DRV425
封装
WQFN (20)
封装尺寸（标称值）
•
•
•
•
•
•
•
•
线性位置感测
4.00mm x 4.00mm
母线电流感测
走线电流感测
通用磁场传感器
过流检测
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
电机可靠性诊断
频率和电压逆变器
太阳能逆变器
简化电路原理图
RSHUNT
COMP1
DRV425
COMP2
DRV2
DRV1 AINP
AINN
Shunt
Sense
Amplifier
Differential
Driver
Fluxgate
Sensor
and
Integrator
Compensation
Coil
VOUT
REFIN
ADC
Fluxgate Sensor Front-End
Device Control and Diagnostic
Reference
REFOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS729
DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 23
8
9
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Applications ................................................ 24
Power-Supply Recommendations...................... 29
9.1 Power-Supply Decoupling....................................... 29
9.2 Power-On Start-Up and Brownout .......................... 29
9.3 Power Dissipation ................................................... 29
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 文档支持 ............................................................... 32
11.2 社区资源................................................................ 32
11.3 商标....................................................................... 32
11.4 静电放电警告......................................................... 32
11.5 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (October 2015) to Revision A
Page
•
•
•
已修复损坏的链接................................................................................................................................................................... 1
已添加最后四个 应用 要点的措辞 .......................................................................................................................................... 1
Changed device name in 图 63 ........................................................................................................................................... 21
2
Copyright © 2015–2016, Texas Instruments Incorporated
DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
5 Pin Configuration and Functions
RTJ Package
20-Pin WQFN
Top View
BSEL
RSEL1
1
2
3
4
5
15
14
13
12
11
OR
AINN
AINP
DRV1
DRV2
RSEL0
(Thermal Pad)
REFOUT
REFIN
Pin Functions
PIN
NAME
AINN
NO.
I/O
I
DESCRIPTION
14
Inverting input of the shunt-sense amplifier
Noninverting input of the shunt-sense amplifier
Filter bandwidth select input
AINP
13
I
BSEL
1
I
COMP1
COMP2
DRV1
16
I
Internal compensation coil input 1
17
I
Internal compensation coil input 2
12
O
O
O
—
O
—
I
Compensation coil driver output 1
DRV2
11
Compensation coil driver output 2
ERROR
GND
19
7, 10, 18, 20
15
Error flag: open-drain, active-low output
Ground reference
OR
Shunt-sense amplifier overrange indicator: open-drain, active-low output
Connect the thermal pad to GND
PowerPAD
REFIN
REFOUT
RSEL0
RSEL1
5
4
3
2
Common-mode reference input for the shunt-sense amplifier
Voltage reference output
O
I
Voltage reference mode selection input 0
Voltage reference mode selection input 1
I
Supply voltage, 3.0 V to 5.5 V. Decouple both pins using 1-µF ceramic capacitors placed as
close as possible to the device. See the Power-Supply Decoupling and Layout sections for
further details.
VDD
8, 9
6
—
O
VOUT
Shunt-sense amplifier output
Copyright © 2015–2016, Texas Instruments Incorporated
3
DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
6.5
UNIT
Supply voltage (VDD to GND)
Voltage
Input voltage, except AINP and AINN pins(2)
Shunt-sense amplifier inputs (AINP and AINN pins)(3)
GND – 0.5
GND – 6.0
–300
VDD + 0.5
VDD + 6.0
300
V
(4)
DRV1 and DRV2 pins (short-circuit current, IOS
)
Current
Shunt-sense amplifier input pins AINP and AINN
All remaining pins
–5
5
mA
°C
–25
25
Junction, TJ max
–50
150
Temperature
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited, except for the differential amplifier input pins.
(3) These inputs are not diode-clamped to the power-supply rails.
(4) Power-limited; observe maximum junction temperature.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
NOM
MAX
5.5
UNIT
VDD
TA
Supply voltage range (VDD to GND)
Specified ambient temperature range
5.0
V
–40
125
°C
6.4 Thermal Information
DRV425
THERMAL METRIC(1)
RTJ (WQFN)
UNIT
20 PINS
34.1
33.1
11
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
11
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015–2016, Texas Instruments Incorporated
DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
6.5 Electrical Characteristics
All minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA, unless otherwise
noted. Typical values are at VDD = 5.0 V.
PARAMETER
FLUXGATE SENSOR FRONT-END
Offset
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No magnetic field
–8
±2
±5
8
µT
Offset drift
No magnetic field
nT/°C
mA/mT
G
Gain
Current at DRV1 and DRV2 outputs
12.2
±0.04%
±7
Gain error
Gain drift
Best-fit line method
ppm/°C
Linearity error
Hysteresis
Noise
0.1%
1.4
Magnetic field sweep from –10 mT to 10 mT
f = 0.1 Hz to 10 Hz
µT
17
nTrms
nT/√Hz
mT
Noise density
Compensation range
f = 1 kHz
1.5
–2
2
Saturation trip level for the
ERROR pin(1)
Open-loop, uncompensated field
1.6
mT
µs
ERROR delay
Open-loop at B > 1.6 mT
BSEL = 0, RSHUNT = 22 Ω
BSEL = 1, RSHUNT = 22 Ω
VDD = 5 V
4 to 6
32
BW
IOS
Bandwidth
kHz
mA
47
250
150
Short-circuit current
VDD = 3.3 V
Common-mode output voltage at the
DRV1 and DRV2 pins
VREFOUT
100
V
Compensation coil resistance
Ω
SHUNT-SENSE AMPLIFIER
VOO
Output offset voltage
Output offset voltage drift
Common-mode rejection ratio, RTO(2) VCM = –1 V to VDD + 1 V, VREFIN = VDD / 2
VAINP = VAINN = VREFIN, VDD = 3.0 V
–0.075
–2
±0.01
±0.4
±50
±4
0.075
2
mV
µV/°C
µV/V
µV/V
V
CMRR
PSRRAMP
VICR
–250
–50
–1
250
Power-supply rejection ratio, RTO(2)
Common-mode input voltage range
Differential input impedance
Common-mode input impedance
Nominal gain
VDD = 3.0 V to 5.5 V, VCM = VREFIN
50
VDD + 1
23.5
60
zid
16.5
40
20
kΩ
zic
50
kΩ
Gnom
EG
VVOUT / (VAINP – VAINN
)
4
±0.02%
±1
V/V
Gain error
–0.3%
–5
0.3%
5
Gain error drift
ppm/°C
ppm
Linearity error
12
VDD = 5.5 V, IVOUT = 2.5 mA
VDD = 3.0 V, IVOUT = 2.5 mA
VDD = 5.5 V, IVOUT = –2.5 mA
VDD = 3.0 V, IVOUT = –2.5 mA
48
85
Voltage output swing from negative
rail (OR pin trip level)(1)
mV
56
100
VDD – 85
VDD – 48
VDD – 56
Voltage output swing from positive rail
(OR pin trip level)(1)
mV
µs
VDD – 100
Signal overrange indication delay
(OR pin)(1)
VIN = 1-V step
2.5 to 3.5
VOUT connected to GND
VOUT connected to VDD
–18
20
2
IOS
Short-circuit current
mA
BW–3dB
SR
Bandwidth
Slew rate
MHz
V/µs
6.5
0.9
8
Large signal
Settling time
ΔV = ± 2 V to 1%, no external filter
ΔV = ± 0.4 V to 0.01%
tsa
µs
Small signal
en
Output voltage noise density
f = 1 kHz, compensation loop disabled
Input voltage range at REFIN pin
170
nV/√Hz
VREFIN
Input voltage range at pin REFIN
GND
VDD
V
(1) See the Magnetic Field Range, Overrange Indicator, and Error Flag section for details on the behavior of the ERROR and OR outputs.
(2) Parameter value is referred-to-output (RTO).
Copyright © 2015–2016, Texas Instruments Incorporated
5
DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
www.ti.com.cn
Electrical Characteristics (continued)
All minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA, unless otherwise
noted. Typical values are at VDD = 5.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE
RSEL[1:0] = 00, no load
2.45
1.6
2.5
2.55
1.7
V
Reference output voltage at the
REFOUT pin
RSEL[1:0] = 01, no load
RSEL[1:0] = 1x, no load
1.65
VREFOUT
% of
VDD
45
50
55
Reference output voltage drift
Voltage divider gain error drift
Power-supply rejection ratio
RSEL[1:0] = 0x
RSEL[1:0] = 1x
RSEL[1:0] = 0x
–50
–50
±10
±10
±15
50 ppm/°C
50 ppm/°C
PSRRREF
–300
300
µV/V
RSEL[1:0] = 0x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C
0.15
0.3
0.35
0.8
ΔVO(ΔIO)
Load regulation
mV/mA
RSEL[1:0] = 1x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C
REFOUT connected to VDD
REFOUT connected to GND
20
mA
mA
IOS
Short-circuit current
–18
DIGITAL INPUTS/OUTPUTS (CMOS)
IIL
Input leakage current
0.01
µA
V
VIH
VIL
VOH
VOL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
TA = –40°C to +125°C
TA = –40°C to +125°C
Open-drain output
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
V
Set by external pullup resistor
0.3
V
4-mA sink current
V
POWER SUPPLY
IDRV1/2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V,
TA = –40°C to +125°C
6
8
IQ
Quiescent current
mA
V
IDRV1/2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V,
TA = –40°C to +125°C
7
10
VPOR
Power-on reset threshold
2.4
6
版权 © 2015–2016, Texas Instruments Incorporated
DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
6.6 Typical Characteristics
at VDD = 5 V and TA = 25°C (unless otherwise noted)
50
40
30
20
10
0
50
40
30
20
10
0
D001
D002
Offset (mT)
Offset (mT)
VDD = 5 V
VDD = 3.3 V
图 1. Fluxgate Sensor Front-End Offset Histogram
图 2. Fluxgate Sensor Front-End Offset Histogram
4
3
4
3
Device 1
Device 2
Device 3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Supply Voltage (V)
D003
D004
图 3. Fluxgate Sensor Front-End Offset vs
图 4. Fluxgate Sensor Front-End Offset vs
Supply Voltage
Temperature
100
80
60
40
20
0
50
40
30
20
10
0
D046
D005
Offset Drift (nT/èC)
Gain (mA/mT)
VDD = 5 V
图 5. Fluxgate Sensor Front-End Offset Drift Histogram
图 6. Fluxgate Sensor Front-End Gain Histogram
版权 © 2015–2016, Texas Instruments Incorporated
7
DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
www.ti.com.cn
Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
12.35
12.35
12.3
Device 1
Device 2
Device 3
12.3
12.25
12.2
12.25
12.2
12.15
12.1
12.15
12.1
12.05
12.05
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Supply Voltage (V)
D008
D009
图 7. Fluxgate Sensor Front-End Gain vs
图 8. Fluxgate Sensor Front-End Gain vs Temperature
Supply Voltage
50
40
30
20
10
0
0.2
0.175
0.15
0.125
0.1
0.075
0.05
0.025
0
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
D057
D010
Linearity (%)
VDD = 5 V
图 9. Fluxgate Sensor Front-End Linearity Histogram
图 10. Fluxgate Sensor Front-End Linearity vs
Supply Voltage
100
10
1
0.2
0.175
0.15
0.125
0.1
Device 1
Device 2
Device 3
0.075
0.05
0.025
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Noise Frequency (kHz)
D006
D011
图 12. Fluxgate Sensor Front-End Noise Density vs Noise
图 11. Fluxgate Sensor Front-End Linearity vs Temperature
Frequency
8
版权 © 2015–2016, Texas Instruments Incorporated
DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
D007
D013
Saturation Trip Level (mT)
Saturation Trip Level (mT)
VDD = 5 V
VDD = 3.3 V
图 13. Fluxgate Sensor Saturation (ERROR Pin)
图 14. Fluxgate Sensor Saturation (ERROR Pin)
Trip Level Histogram
Trip Level Histogram
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
60
50
40
30
20
10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D052
D053
Compensation Coil Resistance (W)
图 16. Compensation Coil Resistance Histogram
图 15. Fluxgate Sensor Saturation (ERROR Pin) Trip Level
vs Temperature
150
140
130
120
110
100
90
70
60
50
40
30
20
10
0
80
70
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D054
D015
Output Offset (mV)
VDD = 5 V
图 18. Shunt-Sense Amplifier Output Offset Histogram
图 17. Compensation Coil Resistance vs Temperature
版权 © 2015–2016, Texas Instruments Incorporated
9
DRV425
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
www.ti.com.cn
Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
70
75
50
60
50
40
30
20
10
0
25
0
-25
-50
-75
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
D0165
D018
Output Offset (mV)
VDD = 3.3 V
图 20. Shunt-Sense Amplifier Output Offset vs
图 19. Shunt-Sense Amplifier Output Offset Histogram
Supply Voltage
75
50
40
30
20
10
0
Device 1
Device 2
Device 3
50
25
0
-25
-50
-75
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D019
Common-Mode Rejection Ratio (mV/V)
D017
图 21. Shunt-Sense Amplifier Output Offset vs Temperature
图 22. Shunt-Sense Amplifier CMRR Histogram
100
70
60
50
40
30
20
10
0
80
60
40
20
0
0.01
0.1
1
10
100
1000
D021
Input Signal Frequency (kHz)
Power-Supply Rejection Ratio (mV/V)
D020
图 23. Shunt-Sense Amplifier CMRR vs
图 24. Shunt-Sense Amplifier PSRR Histogram
Input Signal Frequency
10
版权 © 2015–2016, Texas Instruments Incorporated
DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
0.01
0.1
1
10
100
1000
D023
Ripple Frequency (kHz)
AINP Input Impedance (kW)
D022
图 26. Shunt-Sense Amplifier AINP Input Impedance
图 25. Shunt-Sense Amplifier PSRR vs
Histogram
Ripple Frequency
50
51
50.8
50.6
50.4
50.2
50
40
30
20
10
0
49.8
49.6
49.4
49.2
49
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D025
D024
AINN Input Impedance (kW)
图 27. Shunt-Sense Amplifier AINP Input Impedance
图 28. Shunt-Sense Amplifier AINN Input Impedance
vs Temperature
Histogram
100
80
60
40
20
0
11
10.8
10.6
10.4
10.2
10
9.8
9.6
9.4
9.2
9
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D027
D026
Gain Error (%)
Including IFG, VDD = 5 V
图 29. Shunt-Sense Amplifier AINN Input Impedance
图 30. Shunt-Sense Amplifier Gain Error Histogram
vs Temperature
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Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
100
0.3
0.25
0.2
80
60
40
20
0
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D028
D055
Gain Error (%)
Including IFG, VDD = 3.3 V
图 32. Shunt-Sense Amplifier Gain Error vs
图 31. Shunt-Sense Amplifier Gain Error Histogram
Temperature
20
15
10
5
40
35
30
25
20
15
10
5
0
0.01
0
3
0.1
1
10
100
1000
10000
3.5
4
4.5
5
5.5
Input Signal Frequency (kHz)
Supply Voltage (V)
D029
D030
图 33. Shunt-Sense Amplifier Gain vs
图 34. Shunt-Sense Amplifier Linearity Error vs
Input Signal Frequency
Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
VDD = 5.5 V
VDD = 3.0 V
0
1
2
3
4
5
6
7
8
9
10
3
3.5
4
4.5
5
5.5
Output Current (mA)
Supply Voltage (V)
D031
D056
图 35. OR Pin Trip Level vs Output Current
图 36. OR Pin Trip Level vs Supply Voltage
12
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Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
0.5
4
3.75
3.5
3.25
3
VDD = 5.5 V
VDD = 3.0 V
0.4
0.3
0.2
0.1
0
2.75
2.5
2.25
2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D032
D033
图 37. OR Pin Trip Level vs Temperature
图 38. OR Pin Trip Delay vs Temperature
40
30
40
30
VOUT to GND
VOUT to VDD
VOUT to GND
VOUT to VDD
20
20
10
10
0
0
-10
-20
-30
-40
-10
-20
-30
-40
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Supply Voltage (V)
D035
D034
图 39. Shunt-Sense Amplifier Output Short-Circuit Current
图 40. Shunt-Sense Amplifier Output Short-Circuit Current
vs Supply Voltage
vs Temperature
0.25
0.2
0.25
VVOUT
VAINP - VAINN
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.05
-0.1
-0.15
-0.2
-0.25
VVOUT
VAINP - VAINN
-0.2
-0.25
-2.5
0
2.5
5
7.5
10
12.5
15
17.5
-2.5
0
2.5
5
7.5
10
12.5
15
17.5
Time (ms)
Time (ms)
D012
D049
Rising edge
Falling edge
图 41. Shunt-Sense Amplifier Small-Signal
图 42. Shunt-Sense Amplifier Small-Signal
Settling Time
Settling Time
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Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
1.25
1
1.25
VVOUT
VAINP - VAINN
1
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-0.25
-0.5
-0.75
-1
VVOUT
VAINP - VAINN
-1
-1.25
-1.25
-0.5
0
0.5
1
1.5
2
2.5
-0.5
0
0.5
1
1.5
2
2.5
Time (ms)
Time (ms)
D050
D051
Rising edge
Falling edge
图 43. Shunt-Sense Amplifier Large-Signal
图 44. Shunt-Sense Amplifier Large-Signal
Settling Time
Settling Time
5
4
5
4
VAINP - VAINN
VVOUT
VAINP - VAINN
VVOUT
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
-0.1 -0.075 -0.05 -0.025
0
0.025 0.05 0.075 0.1
-0.1 -0.075 -0.05 -0.025
0
0.025 0.05 0.075 0.1
Time (ms)
Time (ms)
D036
D037
VDD = 5 V
VDD = 3.3 V
图 45. Shunt-Sense Amplifier Overload Recovery Response
图 46. Shunt-Sense Amplifier Overload Recovery Response
10000
70
60
50
40
30
20
10
0
1000
100
10
10
100
1000
10000
100000
Noise Frequency (Hz)
D039
Reference Voltge (V)
D038
VREFOUT = 2.5 V
图 48. Reference Voltage Histogram
图 47. Shunt-Sense Amplifier Output Voltage Noise Density
vs Noise Frequency
14
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Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
3
2.8
2.6
2.4
2.2
2
70
RSEL[1:0] = 00
RSEL[1:0] = 01
60
50
40
30
20
10
0
1.8
1.6
1.4
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
D042
D058
Reference Voltage (V)
VREFOUT = 1.65 V
图 50. Reference Voltage vs Supply Voltage
图 49. Reference Voltage Histogram
2.55
3
2.8
2.6
2.4
2.2
2
Device 1
Device 2
Device 3
RSEL[1:0] = 00
RESL[1:0] = 01
RSEL[1:0] = 1x
2.54
2.53
2.52
2.51
2.5
2.49
2.48
2.47
2.46
2.45
1.8
1.6
1.4
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
Referene Current (mA)
D040
D043
图 51. Reference Voltage vs Temperature
图 52. Reference Voltage vs Reference Output Current
30
25
20
15
10
5
50
40
30
20
10
0
0
D041
Reference Voltage Drift (ppm/èC)
D044
Power-Supply Rejection Ratio (mV/V)
图 53. Reference Voltage Drift Histogram
图 54. Reference Voltage PSRR Histogram
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Typical Characteristics (接下页)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
100
30
25
20
15
10
5
REFOUT to GND
REFOUT to VDD
80
60
40
20
0
0
-5
-10
-15
-20
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D045
D060
Load Regulation (mV/mA)
图 56. Reference Short-Circuit Current vs Temperature
图 55. Reference Voltage Load Regulation Histogram
10
10
VDD = 3.3 V
VDD = 5 V
9.5
9
9
8.5
8
8
7.5
7
7
6.5
6
6
5.5
5
5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
D048
D061
图 58. Quiescent Current vs Temperature
图 57. Quiescent Current vs Supply Voltage
40
35
30
25
20
15
10
5
2.55
2.45
2.35
2.25
VDD = 3.3 V
VDD = 5 V
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Magnetic Field (mT)
D014
D047
图 59. Supply Current vs Magnetic Field
图 60. Power-On Reset Threshold vs Temperature
16
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ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
7 Detailed Description
7.1 Overview
Magnetic sensors are used in a broad range of applications (such as position, indirect ac and dc current, or
torque measurement). Hall-effect sensors are most common in magnetic field sensing, but their offset, noise,
gain variation, and nonlinearity limit the achievable resolution and accuracy of the system. Fluxgate sensors offer
significantly higher sensitivity, lower drift, lower noise, and high linearity and enable up to 1000-times better
accuracy of the measurement.
As shown in the Functional Block Diagram section, the DRV425 consists of a magnetic fluxgate sensor with the
necessary sensor conditioning and compensation coil to internally close the control loop. The fluxgate sensor is
repeatedly driven in and out of saturation and supports hysteresis-free operation with excellent accuracy. The
internal compensation coil assures stable gain and high linearity.
The magnetic field (B) is detected by the internal fluxgate sensor in the DRV425. The device integrates the
sensor output to assure high-loop gain. The integrator output connects to the built-in differential driver that drives
an opposing compensation current through the internal compensation coil. The compensation coil generates an
opposite magnetic field that brings the original magnetic field at the sensor back to zero.
The compensation current is proportional to the external magnetic field and its value is 12.2 mA/mT. This
compensation current generates a voltage drop across an external shunt resistor, RSHUNT. An integrated
difference amplifier with a fixed gain of 4 V/V measures this voltage and generates an output voltage that is
referenced to REFIN and is proportional to the magnetic field. The value of the output voltage at the VOUT pin
(VVOUT) is calculated using 公式 1:
VVOUT [V] = B × G × RSHUNT × GAMP = B [mT] × 12.2 mA/mT × RSHUNT [Ω] × 4 [V/V]
(1)
7.2 Functional Block Diagram
RSHUNT
COMP1
COMP2
DRV2
DRV1
AINP
AINN
Fluxgate Sensor Front-End
Shunt
Sense
Amplifier
Compensation
Coil
Integrator
Fluxgate
Sensor
Differential
Driver
VOUT
REFIN
Voltage Reference
RSEL0 RSEL1
REFOUT
Device Control
DRV425
OR ERROR BSEL
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7.3 Feature Description
7.3.1 Fluxgate Sensor Front-End
The following sections describe the functional blocks and features of the integrated fluxgate sensor front-end.
7.3.1.1 Fluxgate Sensor
The fluxgate sensor of the DRV425 is uniquely suited for high-performance magnetic-field sensors because of
the high sensitivity, low noise, and low offset of the sensor. The fluxgate principle relies on repeatedly driving the
sensor in and out of saturation; therefore, the sensor is free of any significant magnetic hysteresis. The feedback
loop accurately drives a compensation current through the integrated compensation coil and drives the magnetic
field at the sensor back to zero. This approach supports excellent gain stability and high linearity of the
measurement.
The DRV425 package is free of any ferromagnetic materials in order to prevent magnetization by external fields
and to obtain accurate and hysteresis-free operation. Select non-magnetizable materials for the printed circuit
board (PCB) and passive components in the direct vicinity of the DRV425; see the Layout Guidelines section for
more details.
The orientation and the sensitivity axis of the fluxgate sensor is indicated by a dashed line on the top of the
package, as shown in 图 61. 图 61 also shows the location of the sensor inside the package.
Sensitivity Axis Indication
(Top View)
Sensor Location
(Top View)
Sensor Location
(Side View)
>
0.4 mm ± 0.025 mm
Top
DRV425
TI Date
Code
Bottom
图 61. Magnetic Sensitivity Direction of the Integrated Fluxgate Sensor
The sensitivity of the fluxgate sensor is a vector function of its sensitivity axis and the magnetic field orientation.
图 62 shows the output of the DRV425 in dependency of the orientation of the device to a constant magnetic
field.
2.65
2.6
2.55
2.5
2.45
2.4
2.35
0
30 60 90 120 150 180 210 240 270 300 330 360
Angle (è)
D063
图 62. DRV425 Output vs Magnetic Field Orientation
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Feature Description (接下页)
7.3.1.2 Bandwidth
The small-signal bandwidth of the DRV425 is determined by the behavior of the compensation loop versus
frequency. The implemented integrator limits the bandwidth of the loop to provide stable response. Use the
digital input pin BSEL to select the bandwidth. For a shunt resistor of 22 Ω and BSEL = 0, the bandwidth is
32 kHz; for BSEL = 1, the bandwidth is 47 kHz.
Bandwidth can be reduced by increasing the value of the shunt resistor because the shunt resistor and the
compensation coil resistance form a voltage divider. The reduced bandwidth (BW) can be calculated using 公式
2:
RCOIL + 22 W
RCOIL + RSHUNT
122 W
100 W + RSHUNT
BW =
ìBW22 W
=
ìBW22 W
where
•
•
•
RCOIL = internal compensation coil resistance (100 Ω),
RSHUNT = external shunt resistance, and
BW22Ω = sensor bandwidth with RSHUNT = 22 Ω (depending on the BSEL setting)
(2)
The bandwidth for a given shunt resistor value can also be calculated using the DRV425 System Parameter
Calculator, SLOC331. For large magnetic fields (B > 500 μT), the effective bandwidth of the sensor is limited by
fluxgate saturation effects. For a magnetic signal with a 2-mT amplitude, the large-signal bandwidth is 10 kHz
with BSEL = 0 or 15 kHz with BSEL = 1.
Although the analog output responds slowly to large fields, a magnetic field with a magnitude of 1.6 mT (or
higher) beyond the measurement range of the DRV425 triggers the ERROR pin within 4 µs to 6 µs. See the
Magnetic Field Range, Overrange Indicator, and Error Flag section for more details.
7.3.1.3 Differential Driver for the Internal Compensation Coil
The differential compensation coil driver provides the current for the internal compensation coil at the DRV1 and
DRV2 pins. The driver is capable of sourcing up to ±250 mA with a 5-V supply or up to ±150 mA in 3.3-V mode.
The current capability is not internally limited. The actual value of the compensation coil current depends on the
magnetic field strength and is limited by the sum of the resistance of the internal compensation coil and the
external shunt resistor value. The internal compensation coil resistance depends on temperature (see 图 17) and
must be taken into account when dimensioning the system. Select the value of the shunt resistor to avoid OR pin
trip levels in normal operation.
The common-mode voltage of the compensation coil driver outputs is set by the RSEL pins (see the Voltage
Reference section). Thus, the common-mode voltage of the shunt-sense amplifier is matched if the internal
reference is used.
Consider the polarity of the compensation coil connection to the output of the compensation coil driver. If the
polarity is incorrect, then the driver output drives to the power-supply rails, even at low primary-current levels. In
this case, interchange the connection of the DRV1 and DRV2 pins to the compensation coil.
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Feature Description (接下页)
7.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
The measurement range of the DRV425 is determined by the amount of current driven into the compensation coil
and the output voltage range of the shunt-sense amplifier. The maximum compensation current is limited by the
supply voltage and the series resistance of the compensation coil and the shunt.
The magnetic field range is adjusted with the external shunt resistor. The DRV425 System Parameter Calculator,
SLOC331 provides the maximum shunt resistor values depending on the supply voltage (VDD) and the selected
reference voltage (VREFIN) for various magnetic field ranges.
For proper operation at a maximum field (BMAX), choose a shunt resistor (RSHUNT) using 公式 3
min VDD - V
,V
- 0.085 V
(
)
(
)
REFIN
REFIN
RSHUNT
Ç
BMAX ì12.2 A/Tì 4 V/V
where
•
•
•
VDD = minimum supply voltage of the DRV425 (V),
VREFIN = common-mode voltage of the shunt-sense amplifier (V), and
BMAX = desired magnetic field range (T)
(3)
Alternatively, to adjust the output voltage of the DRV425 for a desired maximum voltage (VVOUTMAX), use 公式 4:
VVOUTMAX - VREFIN
RSHUNT
Ç
BMAX ì12.2 A/Tì 4 V/V
where
•
•
VVOUTMAX = desired maximum output voltage at VOUT pin (V), and
BMAX = desired magnetic field range (T)
(4)
To avoid railing of the compensation coil driver, assure that 公式 5 is fulfilled:
BMAX ì(RCOIL + RSHUNT )ì12.2A / T
+ 0.1V Ç min VDD - V
,V
REFIN
(
)
REFIN
2
where
•
•
•
•
BMAX = desired magnetic field range (T),
RCOIL = compensation coil resistance (Ω),
VDD = minimum supply voltage of the DRV425 (V), and
VREFIN = selected internal reference voltage value (V)
(5)
The DRV425 System Parameter Calculator, SLOC331 is designed to assist with selecting the system
parameters.
The DRV425 offers two diagnostic output pins to detect large fields that exceed the measurement range of the
sensor: the overrange indicator (OR) and the ERROR flag.
In normal operation, the DRV425 sensor feedback loop compensates the magnetic field inside the fluxgate to
zero. Therefore, a large field inside the fluxgate indicates that the feedback loop is not properly working and the
sensor output is invalid. To detect this condition, the ERROR pin is pulled low if the internal field exceeds
1.6 mT. The ERROR output is suppressed for 4 µs to 6 µs to prevent an undesired reaction to transients or
noise. For static and slowly varying ambient fields, the ERROR pin triggers when the ambient field exceeds the
sensor measurement range by more than 1.6 mT. For dynamic magnetic fields that exceed the sensor bandwidth
as specified in the Specifications section, the feedback loop response is too slow to accurately compensate the
internal field to zero. Therefore, high-frequency fields can trigger the ERROR pin, even if the ambient field does
not exceed the measurement range by 1.6 mT.
In addition, the low-active overrange pin (OR) indicates railing of the output of the shunt-sense amplifier. The OR
output is suppressed for 2.5 µs to 3.5 µs to prevent an undesired reaction to transients or noise. The OR pin trip
level refers to the output voltage value of the shunt-sense amplifier as specified in the Specifications section. Use
公式 3 and 公式 4 to adjust the OR pin behavior to the specific system-level requirements.
Both the ERROR and OR pins are open-drain outputs that require an external pullup resistor. Connect both pins
together with a single pullup resistor to provide a single diagnostic flag, if desired.
20
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Feature Description (接下页)
Based on the DRV425 System Parameter Calculator, SLOC331, for a design for a ±2-mT magnetic field input
range with a supply of 5 V (±5%), a shunt resistor value of 22 Ω is selected and 图 63 shows the status of the
diagnostic flags in the resulting three operation ranges.
Sensor Saturation: B > 3.6 mT
(OR = 0, ERROR = 0)
4
Magnetic Overrange: 2 mT < B ≤ 3.6 mT
3
2
(OR = 0, ERROR = 1)
1
Designated Operating Range: -2 mT ≤ B ≤ 2 mT
0
(OR = 1, ERROR = 1)
-1
-2
-3
-4
Magnetic Overrange: -3.6 mT ≤ B < -2 mT
(OR = 0, ERROR = 1)
Sensor Saturation: B < -3.6 mT
(OR = 0, ERROR = 0)
图 63. Magnetic Field Range of the DRV425 (VDD = 5 V and RSHUNT = 22 Ω)
With the proper RSHUNT value, the differential amplifier output rails and activates the overrange flag (OR = 0)
when the magnetic field exceeds the designated operating range. For fields that exceed the measurement range
of the DRV425 by ≥ 1.6 mT, the fluxgate is permanently saturated and the ERROR pin is pulled low. In this
condition, the fluxgate sensor does not provide a valid output value and, therefore, the output VOUT of the
DRV425 must be ignored. In applications where the ERROR pin cannot be separately monitored, combining the
VOUT and ERROR outputs is recommended (as shown in 图 64) to indicate a magnetic field outside of the
sensor range by pulling the output of the DRV425 to ground.
5 V
1 kW
DRV2
VOUT
RSHUNT
DRV1
AINP
REFIN
Device REFOUT
OR
AINN
COMP1
COMP2
ERROR
5 V
1 µF
1 µF
图 64. Field Overrange Detection Using a Combined VOUT and ERROR Pin
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Feature Description (接下页)
7.3.2 Shunt-Sense Amplifier
The compensation coil current creates a voltage drop across the external shunt resistor, RSHUNT. The internal
differential amplifier senses this voltage drop. This differential amplifier offers wide bandwidth and a high slew
rate. Excellent dc stability and accuracy result from a chopping technique. The voltage gain is 4 V/V, set by
precisely-matched and thermally-stable internal resistors.
Both the AINN and AINP differential amplifier inputs are connected to the external shunt resistor. This shunt
resistor, in series with the internal 10-kΩ input resistors of the shunt sense amplifier, causes an additional gain
error. Therefore, for best common-mode rejection performance, place a dummy shunt resistor (R5) with a value
higher than the shunt resistor in series with the REFIN pin to restore the matching of both resistor dividers, as
shown in 图 65.
Device
DRV2
DRV1
R1
R2
10 kꢀ
40 kꢀ
AINP
_
Optional
RF
500 ꢀ
VOUT
REFIN
RSHUNT
Shunt-Sense
Amplifier
ADC
CF
10 nF
+
R4
40 kꢀ
R3
10 kꢀ
AINN
REFIN (Compensated)
R5
(Dummy Shunt)
ICOMP1
ICOMP2
图 65. Internal Difference Amplifier with an Example of a Decoupling Filter
For an overall gain of 4 V/V, calculate the value of R5 using 公式 6:
R2
R1
R4 + R5
4 =
=
RSHUNT + R3
where:
•
•
R2 / R1 = R4 / R3 = 4,
R5 = RSHUNT × 4
(6)
If the input signal is large, the amplifier output drives close to the supply rails. The amplifier output is able to drive
the input of a successive approximation register (SAR) analog-to-digital converter (ADC). For best performance,
add an RC low-pass filter stage between the shunt-sense amplifier output and the ADC input. This filter limits the
noise bandwidth and decouples the high-frequency sampling noise of the ADC input from the amplifier output.
For filter resistor RF and filter capacitor CF values, see the specific converter recommendations in the respective
product data sheet.
The shunt-sense amplifier output drives 100 pF directly and shows a 50% overshoot with a 1-nF capacitance.
Filter resistor RF extends the capacitive load range. Note that with an RF of only 20 Ω, the load capacitor must be
either less than 1 nF or more than 33 nF to avoid overshoot; with an RF of 50 Ω, this transient area is avoided.
22
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Feature Description (接下页)
Reference input REFIN is the common-mode voltage node for the output signal VOUT. Use the internal voltage
reference of the DRV425 by connecting the REFIN pin to the reference output REFOUT. To avoid mismatch
errors, use the same reference voltage for REFIN and the ADC. Alternatively, use an ADC with a pseudo-
differential input, with the positive input of the ADC connected to VOUT and the negative input connected to
REFIN of the DRV425.
7.3.3 Voltage Reference
The internal precision voltage reference circuit offers low-drift performance at the REFOUT output pin and is
used for internal biasing. The reference output is intended to be the common-mode voltage of the output (the
VOUT pin) to provide a bipolar signal swing. This low-impedance output tolerates sink and source currents of
±5 mA. However, fast load transients can generate ringing on this line. A small series resistor of a few ohms
improves the response, particularly for capacitive loads equal to or greater than 1 μF.
Adjust the value of the voltage reference output to the power supply of the DRV425 using mode selection pins
RSEL0 and RSEL1, as shown in 表 1.
表 1. Reference Output Voltage Selection
MODE
RSEL1
RSEL0
DESCRIPTION
Use with a sensor module supply of 5 V
VREFOUT = 2.5 V
VREFOUT = 1.65 V
Ratiometric output
0
0
1
0
1
x
Use with a sensor module supply of 3.3 V
Provides an output centered on VDD / 2
In ratiometric output mode, an internal resistor divider divides the power-supply voltage by a factor of two.
7.3.4 Low-Power Operation of the DRV425
In applications with low-bandwidth or low sample-rate requirements, the average power dissipation of the
DRV425 can be significantly reduced by powering the device down between measurements. The DRV425
requires 300 μs to fully settle the analog output VOUT, as shown in 图 66. To minimize power dissipation, the
device can be powered down immediately after acquiring the sample by the ADC.
startup
VDD
VOUT
Settling time:
300 µs
图 66. Settling Time of the DRV425 Output VOUT
7.4 Device Functional Modes
The DRV425 is operational when the power supply VDD is applied, as specified in the Specifications section.
The DRV425 has no additional functional modes.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV425 is a high-sensitivity and high-performance magnetic-field sensor. The analog output of the DRV425
can be processed by a 12- to 16-bit analog to digital converter (ADC). The following sections show examples of
DRV425-based applications.
8.2 Typical Applications
8.2.1 Linear Position Sensing
The high sensitivity of the fluxgate sensor, combined with the high linearity of the compensation loop and low
noise of the DRV425, make the device suitable for high-performance linear-position sense applications. A typical
schematic of such a 5-V application using an internal 2.5-V reference is shown in 图 67.
5 V
MCU
DRV2
VOUT
RSHUNT
DRV1
AINP
REFIN
Device REFOUT
OR
ADC
AINN
COMP1
COMP2
GPIO0
GPIO1
ERROR
10 kW
10 kW
5 V
1 µF
1 µF
图 67. Simplified Schematic of a DRV425-Based Linear-Position Sensing Application
8.2.1.1 Design Requirements
For the example shown in 图 67, use the parameters listed in 表 2 as a starting point of the design.
表 2. Design Parameters
DESIGN PARAMETER
Magnetic field range
EXAMPLE VALUE
VDD = 5 V: ±2 mT (max)
VDD = 3.3 V: ±1.3 mT (max)
Supply voltage, VDD
3.0 V to 5.5 V
Range: GND to VDD
If an internal reference is used: 2.5 V, 1.65 V, or VDD / 2
Reference voltage, VREFIN
Depends on the desired magnetic field range, reference, and supply voltage; see the
DRV425 System Parameter Calculator, SLOC331 for details.
Shunt resistor, RSHUNT
24
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8.2.1.2 Detailed Design Procedure
Use the following procedure to design a solution for a linear-position sensor based on the DRV425:
•
•
Select the proper supply voltage VDD to support the desired magnetic field range (see 表 2 for reference).
Select the proper reference voltage VREFIN to support the desired magnetic field range and to match the input
voltage specifications of the desired ADC.
•
•
•
Use the DRV425 System Parameter Calculator, SLOC331 (RangeCalculator tab) to select the proper shunt
resistor value of RSHUNT
.
The sensitivity drift performance of a DRV425-based linear position sensor is dominated by the temperature
coefficient of the external shunt resistor. Select a low-drift shunt resistor for best sensor performance.
Use the DRV425 System Parameter Calculator, SLOC331 (Problems Detected Table in DRV425 System
Parameters tab) to verify the system response.
The amplitude of the magnetic field is a function of distance to and the shape of the magnet, as shown in 图 69.
If the magnetic field to be measured exceeds 3.6 mT, see the datasheet of the magnet to calculate the
appropriate minimum distance to the DRV425 to avoid saturating the fluxgate sensor.
The high sensitivity of the DRV425 may require shielding of the sensing area to avoid influence of undesired
magnetic field sources (such as the earth magnetic field). Alternatively, an additional DRV425 can be used to
perform difference measurement to cancel the influence of a static magnetic field source, as shown in 图 68. 图
70 shows the differential voltage generated by two DRV425 devices in such a circuit.
DRV425-1
DRV425-2
Direction of Linear
Movement
>
>
REFOUT
REFIN
VOUT
REFOUT
REFIN
VOUT
ADC
图 68. Differential Linear-Position Sensing Using Two DRV425 Devices
8.2.1.3 Application Curves
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
50 100 150 200 250 300 350 400 450 500
Distance (mm)
0
20
40
60
80 100 120 140 160 180 200
Distance (mm)
D064
D065
图 69. Analog Output Voltage of the DRV425 vs Distance to
图 70. Difference Between Two DRV425 Outputs vs
the Magnet
Distance to the Magnet
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ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
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8.2.2 Current Sensing in Busbars
In existing applications that use busbars for power distribution, closed-loop current modules are usually used to
accurately measure and control the current. These modules are usually bulky because of the required large
magnetic core. Additionally, because the compensation current generated inside the module is proportional to the
usually high busbar current, the power dissipation of this solution is usually as high as several watts.
图 71 shows an alternative approach with two DRV425 devices. If a hole is drilled in the middle of the busbar, the
current is split in two equal parts that generate magnetic field gradients with opposite directions inside the hole.
These magnetic fields are termed BR and BL in 图 72. The opposite fields cancel each other out in the middle of
the hole. The high sensitivity and linearity of two DRV425 devices positioned at the same distance from the
middle of the hole allow the small opposite fields to be sensed and the current measured with high-accuracy
levels. The differential measurement rejects outside fields that generate a common-mode error that is subtracted
at the output.
Busbar
(Top View)
I/2
Hole
DRV425-1
I
I
DRV425-2
PCB
I/2
图 71. DRV425-Based Busbar Current Sensing
I
Axis of
cross-section
I/2
I/2
Cross-section
PCB
DRV425 - 1
BR
I/2
I/2
Y-Axis
BL
DRV425 - 2
图 72. Magnetic Field Distribution Inside a Busbar Hole
26
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DRV425
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ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
8.2.2.1 Design Requirements
In order to measure the field gradient in the busbar, two DRV425 sensors are placed inside the hole at a well-
defined distance by mounting them on opposite sides of a PCB that is inserted in the hole. The measurement
range and resolution of this solution depends on the following factors:
•
•
•
Busbar geometry: a wider busbar means a larger measurement range and lower resolution.
Size of the hole: a larger diameter means a larger measurement range and lower resolution.
Distance between the two DRV425 sensors: a smaller distance increases the measurement range and
resolution.
Each of these factors can be optimized to create the desired measurement range for a particular application.
Measurement ranges of ±250 A to ±1500 A are achievable with this approach. Larger currents are supported
with large busbar structures and minimized distance between the two DRV425 sensors. Use the parameters
listed in 表 3 as a starting point of the design.
表 3. Design Parameters
DESIGN PARAMETER
Current range
EXAMPLE VALUE
Up to ±1500 A
3.0 V to 5.5 V
VDD / 2
Supply voltage, VDD
Reference voltage, VREFIN
8.2.2.2 Detailed Design Procedure
图 73 shows the schematic diagram of a differential gradient field measurement circuit.
VDD
DRV2
DRV1
AINP
AINN
COMP1
COMP2
DRV2
DRV1
AINP
AINN
COMP1
COMP2
VOUT
REFIN
REFOUT
OR
VCM
VOUT
REFIN
REFOUT
OR
VDIFF
U1
DRV425
U2
DRV425
ERROR
ERROR
VDD
1 µF
1 µF
1 µF
1 µF
VDD
R1
R2
5.1 W
5.1 W
VDD
R3
10 W
1 µF
U3
10 kW
10 kW
OPA320
+
VREF
œ
图 73. Schematic of a DRV425-Based Busbar Current-Sensing Circuit
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ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
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In 图 73, the feedback loops of both DRV425 sensors are combined to directly produce a differential output VDIFF
that is proportional to the sensed magnetic field difference inside the busbar hole. Both compensation coils are
connected in series and are driven from a single side of the compensation coil driver (the DRV1 pins of each
DRV425). Therefore, both driver stages ensure that a current proportional to the magnetic fields BR and BL is
driven through the respective compensation coil. The difference in current through both compensation coils, and
thus the difference field between the sensors, flows through resistor R3 and is sensed by the shunt-sense
amplifier of U2. The current proportional to the common-mode field inside the busbar hole flows through R1 and
R2 and is sensed by the shunt-sense amplifier of U1.
Use the output VCM to verify that the sensors are correctly positioned in the busbar hole with the following steps:
1. Measure VCM with no current flow through the busbar and the PCB in the middle of the busbar hole. This
value is the offset voltage VOFFSET. The value of VOFFSET only depends on stray fields and varies little with the
absolute position of the sensors.
2. Apply current through the busbar and move the PCB along the y-axis in the busbar hole, as shown in 图 72.
The PCB is in the center of the hole if VCM = VOFFSET
.
The sensitivity drift performance of the circuit shown in 图 73 is dominated by the temperature coefficient of the
external resistors R1, R2, and R3. Select low-drift resistors for best sensor performance. For overall system error
calculation, also consider the affect of thermal expansion on the PCB and busbar.
The internal voltage reference of the DRV425 cannot be used in this application because of its limited driver
capability. The OPA320 (U3) is a low-noise operational amplifier with a short-circuit current capability of ±65 mA
and is used to support the required compensation current.
The advantage of this solution is its simplicity: the currents are subtracted by the two DRV425 devices without
additional components. The series connection of the compensation coils halves the voltage swing and reduces
the measurement range of the sensors also by 50%. If a larger sensing range is required, operate the two
sensors independently and use a differential amplifier or ADC to subtract both voltage outputs (VOUT).
Use the ERROR outputs for fast overcurrent detection on the system level.
8.2.2.3 Application Curves
图 74 and 图 75 show the measurement results on a 16-mm wide and 6-mm thick copper busbar with a 12-mm
hole diameter using the circuit shown in 图 73. The two DRV425 devices are placed at a distance of 1 mm from
each other on opposite sides of the PCB. The measurement range is ±500 A; measurement results are limited by
test setup. Independent operation of the two DRV425 sensors increases the measurement range to ±1000 A with
the same busbar geometry.
400
350
300
250
200
150
100
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0
20
40
60
80 100 120 140 160 180 200
Busbar Current (A)
0
20
40
60
80 100 120 140 160 180 200
Busbar Current (A)
D066
D067
图 74. Analog Output Voltage vs
图 75. Linearity Error vs Busbar Current
Busbar Current
28
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DRV425
www.ti.com.cn
ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
9 Power-Supply Recommendations
9.1 Power-Supply Decoupling
Decouple both VDD pins of the DRV425 with 1-µF, X7R-type ceramic capacitors to the adjacent GND pin as
illustrated in 图 76. For best performance, place both decoupling capacitors as close to the related power-supply
pins as possible. Connect these capacitors to the power-supply source in a way that allows the current to flow
through the pads of the decoupling capacitors.
9.2 Power-On Start-Up and Brownout
Power-on is detected when the supply voltage exceeds 2.4 V at the VDD pin. At this point, the DRV425 initiates
the following start-up sequence:
1. Digital logic starts up and waits for 26 μs for the supply to settle.
2. The fluxgate sensor powers up.
3. The compensation loop is active 70 μs after the supply voltage exceeds 2.4 V.
During this startup sequence, the DRV1 and DRV2 outputs are pulled low to prevent undesired signals on the
compensation coil and the ERROR pin is asserted low.
The DRV425 tests for low supply voltages with a brownout voltage level of 2.4 V. Use a power-supply source
capable of supporting large current pulses driven by the DRV425, and low-ESR bypass capacitors for a stable
supply voltage in the system. A supply drop below 2.4 V that lasts longer than 20 μs generates a power-on reset;
the device ignores shorter voltage drops. A voltage drop on the VDD pin to below 1.8 V immediately initiates a
power-on reset. After the power supply returns to 2.4 V, the device initiates a start-up cycle.
9.3 Power Dissipation
The thermally-enhanced, PowerPAD, WQFN package reduces the thermal impedance from junction to case.
This package has a downset lead frame that the die is mounted to. The lead frame has an exposed thermal pad
(PowerPAD) on the underside of the package, and provides a good thermal path for heat dissipation.
The power dissipation on both linear outputs DRV1 and DRV2 is calculated with 公式 7:
PD(DRV) = IDRV × (VDRV – VSUPPLY
)
where
•
•
•
IDRV = supply current as shown in 图 59,
VDRV = voltage potential on the DRV1 or DRV2 output pin, and
VSUPPLY = voltage potential closer to VDRV: VDD or GND
(7)
9.3.1 Thermal Pad
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences the overall heat dissipation. Technical details are described in application report
PowerPad Thermally Enhanced Package, SLMA002, available for download at www.ti.com.
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10 Layout
10.1 Layout Guidelines
The unique, integrated fluxgate of the DRV425 has a very high sensitivity to enable designing a closed-loop
magnetic-field sensor with best-in-class precision and linearity. Observe proper PCB layout techniques because
any current-conducting wire in the direct vicinity of the DRV425 generates a magnetic field that can distort
measurements. Common passive components and some PCB plating materials contain ferromagnetic materials
that are magnetizable. For best performance, use the following layout guidelines:
•
Route current-conducting wires in pairs: route a wire with an incoming supply current next to, or on top of, its
return current path. The opposite magnetic field polarity of these connections cancel each other. To facilitate
this layout approach, the DRV425 positive and negative supply pins are located next to each other.
•
•
•
Route the compensation coil connections close to each other as a pair to reduce coupling effects.
Minimize the length of the compensation coil connections between the DRV1/2 and COMP1/2 pins.
Route currents parallel to the fluxgate sensor sensitivity axis as illustrated in 图 76. As a result, magnetic
fields are perpendicular to the fluxgate sensitivity and have limited affect.
•
•
Vertical current flow (for example, through vias) generates a field in the fluxgate-sensitive direction. Minimize
the number of vias in the vicinity of the DRV425.
Use nonmagnetic passive components (for example, decoupling capacitors and the shunt resistor) to prevent
magnetizing effects near the DRV425.
•
•
Do not use PCB trace finishes with nickel-gold plating because of the potential for magnetization.
Connect all GND pins to a local ground plane.
Ferrite beads in series to the power-supply connection reduce interaction with other circuits powered from the
same supply voltage source. However, to prevent influence of the magnetic fields if ferrite beads are used, do
not place them next to the DRV425.
The reference output (the REFOUT pin) refers to GND. Use a low-impedance and star-type connection to reduce
the driver current and the fluxgate sensor current modulating the voltage drop on the ground track. The REFOUT
and VOUT outputs are able to drive some capacitive load, but avoid large direct capacitive loading because of
increased internal pulse currents. Given the wide bandwidth of the shunt-sense amplifier, isolate large capacitive
loads with a small series resistor.
Solder the exposed PowerPAD on the bottom of the package to the ground layer because the PowerPAD is
internally connected to the substrate that must be connected to the most-negative potential.
图 76 illustrates a generic layout example that highlights the placement of components that are critical to the
DRV425 performance. For specific layout examples, see the DRV425EVM Users Guide, SLOU410.
30
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DRV425
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ZHCSE99A –OCTOBER 2015–REVISED MARCH 2016
10.2 Layout Example
Fluxgate sensor sensitivity axis
Keep this area free of components
creating magnetic fields.
To MCU
To MCU
BSEL
RSEL1
RSEL0
REFOUT
REFIN
OR
AINN
AINP
DRV1
DRV2
RSHUNT
1206
LEGEND
To ADC
Top Layer:
Copper Pour and Traces
Via to Ground Plane
Via to Supply Plane
图 76. Generic Layout Example (Top View)
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
《OPA320 数据表》，SBOS513
《DRV425EVM 用户指南》，SLOU410
《DRV425 系统参数计算器》，SLOC331
《PowerPAD 耐热增强型封装》，SLMA002
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV425RTJR
DRV425RTJT
ACTIVE
QFN
QFN
RTJ
20
20
3000 RoHS & Green
250 RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
----->
DRV425
ACTIVE
RTJ
Call TI
----->
DRV425
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RTJ 20
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224842/A
www.ti.com
MECHANICAL DATA
RTJ (S-PWQFN-ꢀ20)
ꢁLASꢂIC ꢃUAD ꢄLAꢂPACK NO-ꢅEAꢆ
3,85
ꢃ
5
ꢀ1
ꢀ
ꢀ
10
I
16
I
I
4ꢀ5
-ꢄ-ꢄ
3:85
�
Pin 1 Index Area
Top ꢀnd Bꢁtꢂom
ꢁ
5
0,20 Nominꢀl
Leꢀd Fraꢆꢇ
ꢀ
0ꢅ80
ꢂ
�
ꢁ
0ꢅ70
-_ꢀꢁ
_L d
ꢈ
jꢁꢂ ꢃꢄIꢅ Seꢀting Plꢀne
ꢍ0ꢅ0
ꢉ ꢋꢌ ꢎ ꢎꢏꢐꢎcꢑꢒ-f
- f
�ꢀ
ꢊ
ꢊ
o,o5
Seating Heighꢂ
ꢀ
0,00
I
6
1"+ꢀꢁ7
SIZE JD SHAPE
-ꢀꢁ-ꢀꢁ+ꢀꢁ-ꢀꢁ-
SꢀOWN ON
S
ARATE SHEET
r
ꢀ
10
L ꢀ
0,50
-ꢂ
15
1
ꢀ1
0,3ꢀ
0,18
ꢓ
20X
ꢔ
Cꢕꢖ
0,10 @
0,0 ꢗ@ C
Bottom View
4205505/ꢆ 07/1ꢃ
NOTES:
A. All linear dimensꢀons are ꢀn miꢁꢁꢀmeters. Dꢀmeꢂsioꢂꢀꢂg and toꢁeranciꢂg per ASME Y14.5-ꢃ994.
Bꢄ ꢅhꢀs drawing ꢀs subject to change without noticeꢄ
C. QFN (Quad ꢆꢁatpack No-Lead) package coꢂfꢀguratioꢂ.
D. ꢅhe package thermaꢁ pad must be soldered to the board for thermal and mechaꢂꢀcaꢁ perꢇormance.
E. See the additional fꢀgure in the Product Data Sheet ꢇor details regardꢀꢂg the exposed thermaꢁ pad features and dimensꢀons.
�
Check thermal pad mechanical drawiꢂg ꢀn the product datasheet ꢇor nomꢀnaꢁ ꢁead ꢁeꢂgth dimeꢂsionsꢄ
ꢀTꢁS
INSꢀUMEꢁTꢂ
ꢃ.ti.com
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