DRV5023AJEDBZTQ1 [TI]
汽车类 2.7V 至 38V 霍尔效应单极开关 | DBZ | 3 | -40 to 150;
| 型号： | DRV5023AJEDBZTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2.7V 至 38V 霍尔效应单极开关 | DBZ | 3 | -40 to 150 开关 |
| 文件： | 总33页 (文件大小：1649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
DRV5023-Q1 汽车数字开关霍尔效应传感器
1 特性
2 应用
1
•
•
数字单极性开关霍尔传感器
符合汽车类应用的 AEC-Q100 标准
•
•
•
•
•
对接检测
门开关检测
接近感测
阀定位
–
1 级：TA = –40 至 125°C（Q，请参见器件命名
规则）
–
0 级：TA = –40 至 150°C（E，请参见器件命名
规则）
脉冲计数
3 说明
•
•
反向输出选项 (FI)
出色的温度稳定性
DRV5023-Q1 器件是一款斩波稳定霍尔效应传感器，
能够在整个温度范围内提供具有出色灵敏度稳定性和集
成保护 特性的磁场感测解决方案。
–
温度范围内的灵敏度为 ±10%
•
多个灵敏度选项 (BOP/BRP)：
–
–
–
3.5/2 mT（FA、FI，请参见器件命名规则）
6.9 / 3.2 mT（AJ，请参见器件命名规则）
14.5/6 mT（BI，请参见器件命名规则）
当施加的磁通量密度超过 BOP 阈值时，DRV5023-Q1
开漏输出将会转低。输出将保持低电平，直到磁通量密
度降至 BRP 以下之后变为高阻抗。输出灌电流能力为
30mA。反向极性保护高达 -22V 的宽工作电压范围
（2.7 至 38V）使得此器件广泛适用于各种汽车 应
用。
•
支持宽电压范围
–
–
2.7V 至 38V
无需外部稳压器
•
•
•
开漏输出（30mA 灌电流）
35µs 快速上电时间
小型封装尺寸
该器件提供针对反向电源情况、负载突降以及输出短路
或过流故障的内部保护功能。
器件信息(1)
–
表面贴装 3 引脚小外形尺寸晶体管 (SOT)-23
(DBZ)
器件型号
封装
SOT-23 (3)
TO-92 (3)
封装尺寸（标称值）
2.92mm × 1.30mm
4.00mm × 3.15mm
–
2.92mm × 2.37mm
插入式 3 引脚 TO-92 (LPG)
4.00mm × 3.15mm
保护 特性
DRV5023-Q1
–
–
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
•
–
–
–
–
–
反向电源保护（高达 -22V）
支持高达 40V 抛负载
输出短路保护
输出电流限制
电池输出短路保护
输出状态
OUT
Bhys
B (mT)
BRP
BOF
BOP
FA, AJ, and BI Versions
OUT
Bhys
B (mT)
BRP
BOF
BOP
FI Version
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS163
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
器件封装
2
版权 © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
目录
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics.......................................... 7
6.7 Magnetic Characteristics........................................... 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 器件支持................................................................ 21
11.2 文档支持................................................................ 22
11.3 接收文档更新通知 ................................................. 22
11.4 社区资源................................................................ 22
11.5 商标....................................................................... 22
11.6 静电放电警告......................................................... 22
11.7 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (September 2016) to Revision G
Page
•
•
Added the output jitter parameter to the Switching Characteristics table............................................................................... 7
Added the Output Jitter Characteristic section..................................................................................................................... 16
Changes from Revision E (August 2016) to Revision F
Page
•
Made changes to the Power-on time in the Electrical Characteristics table ......................................................................... 7
Changes from Revision D (May 2016) to Revision E
Page
•
•
•
Clarified the output description for the FI device version in the Device Output section ...................................................... 11
Added the Layout section .................................................................................................................................................... 20
已添加 接收文档更新通知 部分............................................................................................................................................. 22
Changes from Revision C (February 2016) to Revision D
Page
•
Revised preliminary limits for the FA version ......................................................................................................................... 7
Changes from Revision B (December 2015) to Revision C
Page
•
•
已添加 FA 和 FI 器件选项....................................................................................................................................................... 1
Added the typical bandwidth value to the Magnetic Characteristics table ............................................................................ 7
版权 © 2014–2017, Texas Instruments Incorporated
3
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
Changes from Revision A (May 2015) to Revision B
Page
•
•
•
•
•
已更正 SOT-23 封装体尺寸并将 SIP 封装名称更正为 TO-92 ................................................................................................ 1
Added BMAX to Absolute Maximum Ratings ........................................................................................................................... 6
Removed table notes regarding testing for the operating junction temperature in Absolute Maximum Ratings .................. 6
已更新封装卷带选项 M 和空白.............................................................................................................................................. 21
已添加 社区资源 .................................................................................................................................................................. 22
Changes from Original (December 2014) to Revision A
Page
•
已将器件状态更新为量产数据 ................................................................................................................................................ 1
4
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
5 Pin Configuration and Functions
For additional configuration information, see 器件标记 and 机械、封装和可订购信息.
DBZ Package
3-Pin SOT-23
Top View
LPG Package
3-Pin TO-92
Top View
OUT
2
3
1
2
3
GND
1
V
CC
VCC
OUT
GND
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
OUT
DBZ
LPG
3
2
2
3
GND
Ground pin
Output
Hall sensor open-drain output. The open drain requires a resistor pullup.
2.7 to 38 V power supply. Bypass this pin to the GND pin with a 0.01-μF (minimum)
VCC
1
1
Power
ceramic capacitor rated for VCC
.
Copyright © 2014–2017, Texas Instruments Incorporated
5
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
–22(2)
40
V
Power supply voltage
Output pin voltage
Voltage ramp rate (VCC), VCC < 5 V
Voltage ramp rate (VCC), VCC > 5 V
Unlimited
V/µs
0
–0.5
0
2
40
V
Output pin reverse current during reverse supply condition
Magnetic flux density, BMAX
100
mA
Unlimited
Q, see 图 26
E, see 图 26
–40
–40
–65
150
175
150
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Ensured by design. Only tested to –20 V.
6.2 ESD Ratings
VALUE
±2500
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX
UNIT
V
VCC
VO
Power supply voltage
2.7
0
38
38
30
Output pin voltage (OUT)
Output pin current sink (OUT)(1)
V
ISINK
0
mA
Q, see 图 26
E, see 图 26
–40 125
–40 150
Operating ambient
temperature
TA
°C
(1) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV5023-Q1
DBZ (SOT-23) LPG (TO-92)
THERMAL METRIC(1)
UNIT
3 PINS
333.2
99.9
3 PINS
180
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
98.6
66.9
154.9
40
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.9
ψJB
65.2
154.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VCC
)
VCC
VCC operating voltage
2.7
38
V
VCC = 2.7 to 38 V, TA = 25°C
VCC = 2.7 to 38 V, TA = TA, MAX
AJ, BI versions
2.7
3
ICC
Operating supply current
Power-on time
mA
(1)
3.5
50
70
35
35
ton
µs
FA, FI versions
OPEN DRAIN OUTPUT (OUT)
VCC = 3.3 V, IO = 10 mA, TA = 25°C
VCC = 3.3 V, IO = 10 mA, TA = 125°C
Output Hi-Z
22
36
rDS(on)
Ilkg(off)
FET on-resistance
Ω
50
1
Off-state leakage current
µA
PROTECTION CIRCUITS
VCCR Reverse supply voltage
IOCP Overcurrent protection level
–22
15
V
OUT shorted VCC
30
45
mA
(1) TA, MAX is 125°C for Q Grade 1 devices and 150°C for E Grade 0 devices (see 图 26)
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN DRAIN OUTPUT (OUT)
td
tr
tf
Output delay time
B = BRP – 10 mT to BOP + 10 mT in 1 µs
R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V
R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V
13
200
31
25
µs
ns
ns
Output rise time (10% to 90%)
Output fall time (90% to 10%)
Measured from 20 000 cycles of B increasing
at a rate of 50 mT/ms (see Figure 19)
tj
Output jitter
±8.5
µs
6.7 Magnetic Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT(1)
ƒBW
DRV5023FA, DRV5023FI: 3.5 / 2 mT
Bandwidth(2)
20
30
kHz
BOP
BRP
Bhys
BO
Operate point (see Figure 12 and Figure 13)
Release point (see Figure 12 and Figure 13)
1.8
0.5
3.5
2
6.8
4.2
mT
mT
mT
mT
Hysteresis; Bhys= (BOP – BRP
)
1.5
2.8
Magnetic offset, BO = (BOP + BRP) / 2
DRV5023AJ: 6.9 / 3.2 mT
BOP
BRP
Bhys
BO
Operate point (see Figure 12 and Figure 13)
Release point (see Figure 12 and Figure 13)
Hysteresis; Bhys= (BOP – BRP
Magnetic offset, BO = (BOP + BRP) / 2
3
1
6.9
3.2
3.7
5
12
5
mT
mT
mT
mT
)
DRV5023BI: 14.5 / 6 mT
BOP
BRP
Bhys
BO
Operate point (see Figure 12 and Figure 13)
6
3
14.5
6
24
9
mT
mT
mT
mT
Release point (see Figure 12 and Figure 13)
(3)
Hysteresis; Bhys = (BOP – BRP
)
8.5
10.3
Magnetic offset, BO = (BOP + BRP) / 2
(1) 1 mT = 10 Gauss
(2) Bandwidth describes the fastest changing magnetic field that can be detected and translated to the output.
(3) |BOP| is always greater than |BRP|.
Copyright © 2014–2017, Texas Instruments Incorporated
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DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
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6.8 Typical Characteristics
TA > 125°C data is valid for Grade 0 devices only (E, see 图 26)
3.5
3.5
3
TA = œ40°C
TA = 25°C
TA = 75°C
TA = 125°C
TA = 150°C
VCC = 3.3 V
VCC = 13.2 V
VCC = 38 V
3
2.5
2
2.5
2
0
10
20
30
40
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Ambient Temperature (°C)
D009
D010
Figure 1. ICC vs VCC
Figure 2. ICC vs Temperature
16
14
12
10
8
16
14
12
10
8
DRV5023AJ
DRV5023BI
DRV5023AJ
DRV5023BI
6
6
4
4
0
10
20
30
40
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Ambient Temperature (°C)
D001
D002
TA = 25°C
VCC = 3.3 V
Figure 3. BOP vs VCC
Figure 4. BOP vs Temperature
6.5
6
7
6
5
4
3
2
5.5
5
4.5
4
DRV5023BI
DRV5023AJ
DRV5023AJ
DRV5023BI
3.5
3
2.5
2
0
10
20
30
40
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Ambient Temperature (°C)
D003
D004
TA = 25°C
VCC = 3.3 V
Figure 5. BRP vs VCC
Figure 6. BRP vs Temperature
8
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
Typical Characteristics (continued)
TA > 125°C data is valid for Grade 0 devices only (E, see 图 26)
9
10
8
DRV5023AJ
DRV5023BI
8
7
6
DRV5023AJ
6
DRV5023BI
5
4
3
2
4
2
0
10
20
30
40
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Ambient Temperature (°C)
D007
D008
TA = 25°C
VCC = 3.3 V
Figure 7. Hysteresis vs VCC
Figure 8. Hysteresis vs Temperature
11
11
10
9
10
9
8
8
DRV5023AJ
DRV5023BI
DRV5023AJ
DRV5023BI
7
7
6
6
5
5
4
4
0
4
8
12
16
20
24
28
32
36
40
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Ambient Temperature (°C)
D005
D006
TA = 25°C
VCC = 3.3 V
Figure 9. Offset vs VCC
Figure 10. Offset vs Temperature
Copyright © 2014–2017, Texas Instruments Incorporated
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DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DRV5023-Q1 device is a chopper-stabilized Hall sensor with a digital output for magnetic sensing
applications. The DRV5023-Q1 device can be powered with a supply voltage between 2.7 and 38 V, and will
survive –22 V reverse-battery conditions. The DRV5023-Q1 device does not operate when –22 to 2.4 V is
applied to the VCC pin (with respect to GND pin). In addition, the device can withstand supply voltages up to 40 V
for transient durations.
The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic
field. A north pole near the marked side of the package is a negative magnetic field. The output state is
dependent on the magnetic field perpendicular to the package.
For the FA, AJ, and BI device versions, a strong south pole near the marked side of the package causes the
output to pull low, and the absence of a field makes the output high-impedance. The FI version has an inverted
output response, where a strong south pole causes the output to be high-impedance, and the absence of a field
makes the output pull low. Hysteresis is included in between the operate point and the release point to prevent
toggling near the magnetic threshold.
An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to VCC, or to a different
voltage supply. This allows for easier interfacing with controller circuits.
7.2 Functional Block Diagram
2.7 V to 38 V
C1
V
CC
Regulated Supply
R1
Temperature
Compensation
Bias
OUT
C2
OCP
(Optional)
+
Gate
Drive
Hall Element
œ
Reference
GND
10
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
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ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
7.3 Feature Description
7.3.1 Field Direction Definition
A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 11.
SOT-23 (DBZ)
TO-92 (LPG)
B > 0 mT
B < 0 mT
B > 0 mT
B < 0 mT
N
S
S
N
N
S
S
N
1
2
3
1
2
3
(Bottom view)
N = North pole, S = South pole
Figure 11. Field Direction Definition
7.3.2 Device Output
If the device is powered on with a magnetic field strength between BRP and BOP, then the device output is
indeterminate and can either be Hi-Z or Low. For the FA, AJ, and BI device versions, if the field strength is
greater than BOP, then the output is pulled low; if the field strength is less than BRP, then the output is released.
For the FI device version, if the field strength is greater than BOP, then the output is Hi-Z; if the field strength is
less than BRP, then the output is pulled Low.
OUT
Bhys
B (mT)
BRP
BOF
BOP
Figure 12. Output State of FA, AJ, BI Versions
OUT
Bhys
B (mT)
BRP
BOF
BOP
Figure 13. Output State of FI Version
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Feature Description (continued)
7.3.3 Power-On Time
After applying VCC to the DRV5023-Q1 device, ton must elapse before the OUT pin is valid. During the power-up
sequence, the output is Hi-Z. A pulse as shown in Figure 14 and Figure 15 occurs at the end of ton. This pulse
can allow the host processor to determine when the DRV5023-Q1 output is valid after startup. In Case 1
(Figure 14) and Case 2 (Figure 15), the output is defined assuming a constant magnetic field B > BOP and B <
BRP
.
VCC
B (mT)
OUT
t (s)
t (s)
t (s)
BOP
BRP
Valid Output
ton
Figure 14. Case 1: Power On When B > BOP
VCC
B (mT)
OUT
t (s)
t (s)
t (s)
BOP
BRP
Valid Output
ton
Figure 15. Case 2: Power On When B < BRP
12
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DRV5023-Q1
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ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
Feature Description (continued)
If the device is powered on with the magnetic field strength BRP < B < BOP, then the device output is
indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until
ton has elapsed. At the end of ton, a pulse is given on the OUT pin to indicate that ton has elapsed. After ton, if the
magnetic field changes such that BOP < B, the output is released. Case 3 (Figure 16) and Case 4 (Figure 17)
show examples of this behavior.
V
CC
t (s)
t (s)
t (s)
B (mT)
B
B
OP
RP
OUT
Valid Output
t
t
d
on
Figure 16. Case 3: Power On When BRP < B < BOP, Followed by B > BOP
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Feature Description (continued)
VCC
t (s)
B (mT)
BOP
BRP
t (s)
OUT
Valid Output
t (s)
ton
td
Figure 17. Case 4: Power On When BRP < B < BOP, Followed by B < BRP
14
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DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
Feature Description (continued)
7.3.4 Output Stage
The DRV5023-Q1 output stage uses an open-drain NMOS, and it is rated to sink up to 30 mA of current. For
proper operation, calculate the value of the pullup resistor R1 using Equation 1.
V
ref max
Vref min
Ç R1Ç
30 mA
100 µA
(1)
The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current
is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching.
In addition, ensure that the value of R1 > 500 Ω to ensure the output driver can pull the OUT pin close to GND.
NOTE
Vref is not restricted to VCC. The allowable voltage range of this pin is specified in the
Absolute Maximum Ratings.
Vref
R1
OUT
ISINK
C2
OCP
Gate
Drive
GND
Figure 18.
Select a value for C2 based on the system bandwidth specifications as shown in Equation 2.
1
2 ì ƒBW (Hz) <
2p ì R1ì C2
(2)
Most applications do not require this C2 filtering capacitor.
Copyright © 2014–2017, Texas Instruments Incorporated
15
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
7.3.5 Protection Circuits
The DRV5023-Q1 device is fully protected against overcurrent and reverse-supply conditions.
7.3.5.1 Overcurrent Protection (OCP)
An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During
this clamping, the rDS(on) of the output FET is increased from the nominal value.
7.3.5.2 Load Dump Protection
The DRV5023-Q1 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand
VCC = 40 V. No current-limiting series resistor is required for this protection.
7.3.5.3 Reverse Supply Protection
The DRV5023-Q1 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).
NOTE
In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings
specified in the Absolute Maximum Ratings.
Table 1.
FAULT
FET overload (OCP)
Load dump
CONDITION
ISINK ≥ IOCP
DEVICE
Operating
Operating
Disabled
DESCRIPTION
RECOVERY
Output current is clamped to IOCP
Device will operate for a transient duration
Device will survive this condition
IO < IOCP
38 V < VCC < 40 V
–22 V < VCC < 0 V
VCC ≤ 38 V
Reverse supply
VCC ≥ 2.7 V
7.3.5.4 Output Jitter Characteristic
The DRV5023-Q1 propagation delay is not fully consistent. If a periodic magnetic field is applied, the device
introduces a small amount of jitter on the output. The tj parameter describes this characteristic and Figure 19
shows the test waveform.
B
Cycle 1
Cycle 2
Cycle 3
BOP
time
Figure 19. Test Waveform for tj
7.4 Device Functional Modes
The DRV5023-Q1 device is active only when VCC is between 2.7 and 38 V.
When a reverse supply condition exists, the device is inactive.
16
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV5023-Q1 device is used in magnetic-field sensing applications.
8.2 Typical Applications
8.2.1 Standard Circuit
C2
680 pF
(Optional)
OUT
2
R1
10 kΩ
3
V
CC
V
CC
1
C1
0.01 µF
(minimum)
Figure 20. Typical Application Circuit
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
VCC
EXAMPLE VALUE
3.2 to 3.4 V
10 kHz
System bandwidth
ƒBW
8.2.1.2 Detailed Design Procedure
Table 3. External Components
COMPONENT
PIN 1
VCC
PIN 2
GND
RECOMMENDED
C1
C2
R1
A 0.01-µF (minimum) ceramic capacitor rated for VCC
Optional: Place a ceramic capacitor to GND
Requires a resistor pullup
OUT
OUT
GND
REF(1)
(1) REF is not a pin on the DRV5023-Q1 device, but a REF supply-voltage pullup is required for the OUT pin; the OUT pin may be pulled
up to VCC
.
Copyright © 2014–2017, Texas Instruments Incorporated
17
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
8.2.1.2.1 Configuration Example
In a 3.3-V system, 3.2 V ≤ Vref ≤ 3.4 V. Use Equation 3 to calculate the allowable range for R1.
V
ref max
Vref min
Ç R1Ç
30 mA
100 µA
(3)
For this design example, use Equation 4 to calculate the allowable range of R1.
3.4 V
3.2 V
Ç R1Ç
30 mA
100 µA
(4)
(5)
Therefore:
113 Ω ≤ R1 ≤ 32 kΩ
After finding the allowable range of R1 (Equation 5), select a value between 500 Ω and 32 kΩ for R1.
Assuming a system bandwidth of 10 kHz, use Equation 6 to calculate the value of C2.
1
2 ì ƒBW (Hz) <
2p ì R1ì C2
(6)
(7)
For this design example, use Equation 7 to calculate the value of C2.
1
2 ì 10 kHz <
2p ì R1ì C2
An R1 value of 10 kΩ and a C2 value less than 820 pF satisfy the requirement for a 10-kHz system bandwidth.
A selection of R1 = 10 kΩ and C2 = 680 pF would cause a low-pass filter with a corner frequency of 23.4 kHz.
8.2.1.3 Application Curves
OUT
OUT
R1 = 10-kΩ pullup
C2 = 680 pF
R1 = 10-kΩ pullup
No C2
Figure 22. 10-kHz Switching Magnetic Field
Figure 21. 10-kHz Switching Magnetic Field
0
-2
-4
-6
-8
-10
-12
-14
100
1000
10000
100000
Frequency (Hz)
D011
R1 = 10-kΩ pullup
C2 = 680 pF
Figure 23. Low-Pass Filtering
18
Copyright © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
8.2.2 Alternative Two-Wire Application
For systems that require minimal wire count, the device output can be connected to VCC through a resistor, and
the total supplied current can be sensed near the controller.
R1
+
œ
OUT
VCC
2
1
C1
3
GND
Controller
Current
sense
Figure 24. 2-Wire Application
Current can be sensed using a shunt resistor or other circuitry.
8.2.2.1 Design Requirements
Table 4 lists the related design parameters.
Table 4. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
VCC
EXAMPLE VALUE
12 V
OUT resistor
R1
1 kΩ
Bypass capacitor
Current when B < BRP
Current when B > BOP
C1
0.1 µF
IRELEASE
IOPERATE
About 3 mA
About 15 mA
8.2.2.2 Detailed Design Procedure
When the open-drain output of the device is high-impedance, current through the path equals the ICC of the
device (approximately 3 mA).
When the output pulls low, a parallel current path is added, equal to VCC / (R1 + rDS(on)). Using 12 V and 1 kΩ,
the parallel current is approximately 12 mA, making the total current approximately 15 mA.
The local bypass capacitor C1 should be at least 0.1 µF, and a larger value if there is high inductance in the
power line interconnect.
9 Power Supply Recommendations
The DRV5023-Q1 device is designed to operate from an input voltage supply (VM) range between 2.7 and 38 V.
A 0.01-µF (minimum) ceramic capacitor rated for VCC must be placed as close to the DRV5023-Q1 device as
possible.
Copyright © 2014–2017, Texas Instruments Incorporated
19
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The bypass capacitor should be placed near the DRV5023-Q1 device for efficient power delivery with minimal
inductance. The external pullup resistor should be placed near the microcontroller input to provide the most
stable voltage at the input; alternatively, an integrated pullup resistor within the GPIO of the microcontroller can
be used.
Generally, using PCB copper planes underneath the DRV5023-Q1 device has no effect on magnetic flux, and
does not interfere with device performance. This is because copper is not a ferromagnetic material. However, If
nearby system components contain iron or nickel, they may redirect magnetic flux in unpredictable ways.
10.2 Layout Example
VCC
OUT
GND
Figure 25. DRV5023-Q1 Layout Example
20
版权 © 2014–2017, Texas Instruments Incorporated
DRV5023-Q1
www.ti.com.cn
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
图 26 显示了读取 DRV5023-Q1 器件完整器件名称的图例。
DRV5023
(AJ)
(Q)
(DBZ)
(R)
(Q1)
Prefix
AEC-Q100
DRV5023: Digital switch Hall sensor
Q1: Automotive qualification
Blank: Non-auto
BOP/BRP
FA: 3.5/2 mT
Tape and Reel
R: 3000 pcs/reel
T: 250 pcs/reel
M: 3000 pcs/box (ammo)
Blank: 1000 pcs/bag (bulk
FI: 3.5/2 mT, inverter
AJ: 6.9/3.2 mT
BI: 14.5/6 mT
Package
DBZ: 3-pin SOT-23
LPG: 3-pin TO-92
Temperature Range
Q: œ40 to 125°C
E: œ40 to 150°C
图 26. 器件命名规则
11.1.2 器件标记
Marked Side Front
Marked Side
3
1
2
3
1
2
Marked Side
1
2
3
(Bottom view)
图 27. SOT-23 (DBZ) 封装
图 28. TO-92 (LPG) 封装
表示霍尔效应传感器（未按比例显示）。霍尔元件置于封装中央位置，容差为 ±100μm。在 DBZ 封装中，霍尔元件
与封装底部的距离为 0.7mm ± 50μm；在 LPG 封装中，霍尔元件与封装底部的距离为 0.987mm ± 50μm。
版权 © 2014–2017, Texas Instruments Incorporated
21
DRV5023-Q1
ZHCSEF4G –DECEMBER 2014–REVISED MARCH 2017
www.ti.com.cn
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《了解和应用霍尔效应传感器产品数据表》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
22
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV5023AJEDBZRQ1
DRV5023AJEDBZTQ1
DRV5023AJELPGMQ1
DRV5023AJELPGQ1
DRV5023AJQDBZRQ1
DRV5023AJQDBZTQ1
DRV5023AJQLPGMQ1
DRV5023AJQLPGQ1
DRV5023BIEDBZRQ1
DRV5023BIEDBZTQ1
DRV5023BIELPGMQ1
DRV5023BIELPGQ1
DRV5023BIQDBZRQ1
DRV5023BIQDBZTQ1
DRV5023BIQLPGMQ1
DRV5023BIQLPGQ1
DRV5023FAEDBZRQ1
DRV5023FIEDBZRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
TO-92
DBZ
DBZ
LPG
LPG
DBZ
DBZ
LPG
LPG
DBZ
DBZ
LPG
LPG
DBZ
DBZ
LPG
LPG
DBZ
DBZ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 150
-40 to 150
+PJAJ
NIPDAUAG
SN
+PJAJ
+PJAJ
+PJAJ
+PKAJ
+PKAJ
+PKAJ
+PKAJ
+PJBI
+PJBI
+PJBI
+PJBI
+PKBI
+PKBI
+PKBI
+PKBI
+PJFA
+PJFI
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
TO-92
SN
SOT-23
SOT-23
TO-92
NIPDAUAG
NIPDAUAG
SN
250
RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
TO-92
SN
SOT-23
SOT-23
TO-92
NIPDAUAG
NIPDAUAG
SN
250
RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
TO-92
SN
SOT-23
SOT-23
TO-92
NIPDAUAG
NIPDAUAG
SN
250
RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
TO-92
SN
SOT-23
SOT-23
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV5023AJEDBZRQ1 SOT-23
DRV5023AJEDBZTQ1 SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3
3
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.15
3.15
3.15
3.15
3.15
3.15
3.15
3.15
3.15
3.15
2.77
2.77
2.77
2.77
2.77
2.77
2.77
2.77
2.77
2.77
1.22
1.22
1.22
1.22
1.22
1.22
1.22
1.22
1.22
1.22
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
DRV5023AJQDBZRQ1 SOT-23
DRV5023AJQDBZTQ1 SOT-23
3000
250
DRV5023BIEDBZRQ1
DRV5023BIEDBZTQ1
DRV5023BIQDBZRQ1
DRV5023BIQDBZTQ1
SOT-23
SOT-23
SOT-23
SOT-23
3000
250
3000
250
DRV5023FAEDBZRQ1 SOT-23
DRV5023FIEDBZRQ1 SOT-23
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV5023AJEDBZRQ1
DRV5023AJEDBZTQ1
DRV5023AJQDBZRQ1
DRV5023AJQDBZTQ1
DRV5023BIEDBZRQ1
DRV5023BIEDBZTQ1
DRV5023BIQDBZRQ1
DRV5023BIQDBZTQ1
DRV5023FAEDBZRQ1
DRV5023FIEDBZRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3
3
3000
250
202.0
202.0
202.0
202.0
202.0
202.0
202.0
202.0
202.0
202.0
201.0
201.0
201.0
201.0
201.0
201.0
201.0
201.0
201.0
201.0
28.0
28.0
28.0
28.0
28.0
28.0
28.0
28.0
28.0
28.0
3000
250
3000
250
3000
250
3000
3000
Pack Materials-Page 2
PACKAGE OUTLINE
LPG0003A
TO-92 - 5.05 mm max height
S
C
A
L
E
1
.
3
0
0
TRANSISTOR OUTLINE
4.1
3.9
3.25
3.05
0.55
0.40
3X
5.05
MAX
3
1
3X (0.8)
3X
15.5
15.1
0.48
0.35
0.51
0.36
3X
3X
2X 1.27 0.05
2.64
2.44
2.68
2.28
1.62
1.42
2X (45 )
1
3
2
0.86
0.66
(0.5425)
4221343/C 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
FULL R
TYP
0.05 MAX
ALL AROUND
TYP
(1.07)
METAL
TYP
3X ( 0.75) VIA
2X
METAL
(1.7)
2X (1.7)
2X
SOLDER MASK
OPENING
2
3
1
2X (1.07)
(R0.05) TYP
(1.27)
SOLDER MASK
OPENING
(2.54)
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE:20X
4221343/C 01/2018
www.ti.com
TAPE SPECIFICATIONS
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0
1
13.0
12.4
0
1
1 MAX
21
18
2.5 MIN
6.5
5.5
9.5
8.5
0.25
0.15
19.0
17.5
3.8-4.2 TYP
0.45
0.35
6.55
6.15
12.9
12.5
4221343/C 01/2018
www.ti.com
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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