DRV612 [TI]
2-Vrms DirectPath? Line Driver With Programmable-Fixed Gain; 2 Vrms的的DirectPath ™线路驱动器，具有可编程固定增益
| 型号： | DRV612 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-Vrms DirectPath? Line Driver With Programmable-Fixed Gain |
| 文件： | 总23页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV612
www.ti.com
SLOS690B –DECEMBER 2010–REVISED APRIL 2011
2-Vrms DirectPath™ Line Driver With Programmable-Fixed Gain
Check for Samples: DRV612
1
FEATURES
DESCRIPTION
The DRV612 is a single-ended, 2-Vrms stereo line
driver designed to reduce component count, board
space and cost. It is ideal for single-supply
electronics where size and cost are critical design
parameters.
2
•
DirectPath™
–
–
–
Eliminates Pops/Clicks
Eliminates Output DC-Blocking Capacitors
3-V to 3.6-V Supply Voltage
•
Low Noise and THD
The DRV612 does not require a power supply greater
than 3.3 V to generate its 5.6-VPP output, nor does it
require a split-rail power supply.
–
–
SNR > 105 dB at –1× Gain
Typical Vn < 12 μVms 20 Hz–20 kHz
at –1× Gain
Designed using TI’s patented DirectPath technology,
which integrates a charge pump to generate a
negative supply rail that provides a clean, pop-free
ground-biased output. The DRV612 is capable of
–
THD+N < 0.003% at 10-kΩ Load
and –1× Gain
•
•
•
2-Vrms Output Voltage Into 600-Ω Load
driving
2 Vms into a 600-Ω load. DirectPath
technology also allows the removal of the costly
output dc-blocking capacitors.
Single-Ended Input and Output
Programmable Gain Select Reduces
Component Count
The device has fixed-gain single-ended inputs with a
gain-select pin. Using a single resistor on this pin, the
designer can choose from 13 internal programmable
gain settings to match the line driver with the codec
output level. It also reduces the component count and
board space.
–
13× Gain Values
•
•
•
Active Mute With More Than 80 dB Attenuation
Short Circuit and Thermal Protection
±8-kV HBM ESD-Protected Outputs
Line outputs have ±8 kV HBM ESD protection,
APPLICATIONS
enabling
a simple ESD protection circuit. The
DRV612 has built-in active mute control with more
that 80 dB attenuation for pop-free mute on/off
control.
•
•
•
•
PDP / LCD TV
DVD Players
Mini/Micro Combo Systems
Soundcards
The DRV612 is available in a 14-pin TSSOP and
16-pin QFN. For
a
footprint-compatible stereo
headphone driver, see TPA6139A2 (SLOS700).
LEFT
-
DAC
+
Programmable
Gain
Line Driver
DRV612
SOC
DAC
-1x to -10x
RIGHT
-
+
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DirectPath is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
DRV612
SLOS690B –DECEMBER 2010–REVISED APRIL 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The DRV612 is available in package:
•
14-pin TSSOP package (PW) or 16-pin QFN package (RGT)
PW PACKAGE
TSSOP
(TOP VIEW)
RGT PACKAGE
QFN
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
-IN_L
-IN_R
OUT_L
GND
OUT_R
GAIN
1
2
3
4
12
11
10
9
OUT_L
OUT_R
GAIN
GND
GND
MUTE
GND
VDD
CP
MUTE
VSS
GND
VDD
CN
NC
NC
8
PIN FUNCTIONS
PIN
FUNCTION(1) DESCRIPTION
NAME
PW NO.
RGT NO.
-IN_L
OUT_L
GND
MUTE
VSS
CN
1
2
16
I
O
P
Negative input, left channel
1
Output, left channel
Ground
3, 11
4
2, 3, 10
4
I
MUTE, active low
5
5
O
I/O
Change Pump negative supply voltage
6
6
Charge Pump flying capacitor negative connection
No internal connection
NC
7, 8
9
7. 14, 15
CP
8
9
I/O
P
Charge Pump flying capacitor positive connection
Supply voltage, connect to positive supply
VDD
10
Gain set programming pin; connect a resistor to ground.
See Table 1 for recommended resistor values
GAIN
12
11
I
OUT_R
13
14
12
13
O
I
Output, right channel
Negative input, right channel
Connect to ground
-IN_R
Thermal Pad
n/a
Thermal Pad
P
(1) I = input, O = output, P = power
2
Copyright © 2010–2011, Texas Instruments Incorporated
DRV612
www.ti.com
SLOS690B –DECEMBER 2010–REVISED APRIL 2011
SYSTEM BLOCK DIAGRAM
Current
Limit
Left
GAIN
Control
De Pop
Current
Limit
Right
Thermal
Limit
Power
Management
Charge Pump
ORDERING INFORMATION(1)
PACKAGE
TA
DESCRIPTION
14-pin TSSOP
16-pin QFN
DRV612PW
–40°C to 85°C
DRV612RGT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
THERMAL INFORMATION
DRV612
DRV612
THERMAL METRIC(1)
UNITS
RGT (16-Pin)
PW (14-Pin)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52
71
130
49
θJCtop
θJB
26
63
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.0
26
3.6
62
ψJB
θJCbot
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
MAX
4
VDD to GND
Voltage range
Temperature
VI , Input voltage
VSS – 0.3
–0.3
VDD + 0.3
VDD + 0.3
150
V
MUTE to GND
Maximum operating junction temperature range, TJ
Storage temperature
–40
°C
–65
150
OUT_L, OUT_R
All other pins
8
2
Electrostatic discharge (HBM) QSS
009-105 (JESD22-A114A)
kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
MIN NOM
MAX
UNIT
V
VDD
RL
Supply voltage
DC supply voltage
3.0
600
38
3.3
10k
40
3.6
Ω
VIL
VIH
TA
Low-level input voltage
High-level input voltage
Free-air temperature
MUTE
MUTE
43
66
85
%VDD
%VDD
°C
57
60
–0
25
4
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
ELECTRICAL CHARACTERISTICS
VDD = 3.3V, RLD = 5 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
80
MAX
UNIT
mV
dB
V
|VOS
|
Output offset voltage
VDD = 3.3 V, input ac-coupled
1
PSRR
VOH
Power-supply rejection ratio
High-level output voltage
Low-level output voltage
VDD, undervoltage detection
70
VDD = 3.3 V
VDD = 3.3 V
3.1
VOL
–3.05
V
Vuvp_on
2.8
V
Vuvp_hysteresis VDD, undervoltage detection, hysteresis
200
350
mV
kHz
µA
µA
mA
mA
°C
FCP
|IIH
Charge-pump switching frequency
High-level input current, MUTE
Low-level input current, MUTE
Supply current, no load
|
VDD = 3.3 V, VIH = VDD
VDD = 3.3 V, VIL = 0 V
VDD, MUTE = 3.3 V
1
1
|IIL|
I(VDD)
18
18
Supply current, MUTED
VDD = 3.3 V, MUTE = GND
TSD
Thermal shutdown
150
15
Thermal shutdown hysteresis
°C
ELECTRICAL CHARACTERISTICS, LINE DRIVER
VDD = 3.3 V, RLOAD = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 µF, 1× gain select (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1% THD+N, f = 1 kHz, 10 -kΩ load
f = 1 kHz, 10-kΩ load, VO = 2 Vrms
A-weighted, AES17 filter, 2 Vrms ref
A-weighted, AES17 filter, 2 Vrms ref
A-weighted, AES17 filter
MIN
TYP MAX
UNIT
VO
Output voltage, outputs in phase
Total harmonic distortion plus noise
Signal-to-noise ratio
2.2
Vrms
THD+N
SNR
DNR
Vn
0.007%
105
105
12
dB
dB
μV
Ω
Dynamic range
Noise voltage
Zo
Output impedance when muted
MUTE = GND
0.07
1
Input-to-output attenuation when
muted
1 Vrms, 1-kHz input
80
dB
Slew rate
4.5
8
V/μs
MHz
dB
GBW
Unity-gain bandwidth
Crosstalk – Line L-R and R-L
Current limit
10-kΩ load, VO = 2 Vrms
–91
25
Ilimit
VDD = 3.3 V
mA
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
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PROGRAMMABLE GAIN SETTINGS(1)(2)
VDD = 3.3 V, Rload = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, 1× gain select, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R_Tol
Gain programming resistor tolerance
Gain matching
2%
ΔAV
Between left and right channels
0.25
0.1
dB
dB
Gain step tolerance
Gain resistor 2% tolerance
249k or higher
82k5
A
–2
–1
51k1
34k8
27k4
20k5
–1.5
–2.3
–2.5
–3
Gain steps
V/V
15k4
11k5
–3.5
–4
9k09
–5
7k50
6k19
5k11
4k22
–5.6
–6.4
–8.3
–10
Gain resistor 2% tolerance
249k or higher
82k5
51k1
34k8
27k4
20k5
15k4
11k5
9k09
7k50
6k19
5k11
A
37
55
44
33
31
28
24
22
18
17
15
12
10
Input impedance
kΩ
4k22
(1) If the GAIN pin is left floating, an internal pullup sets the gain to –2×.
(2) Gain setting is latched during power up.
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
TYPICAL CHARACTERISTICS, LINE DRIVER
VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, Gain = -2V/V (unless otherwise noted)
THD+N vs OUTPUT VOLTAGE
THD+N vs OUTPUT VOLTAGE
3.3 V, 10 kΩ, 1 kHz
3.3 V, 600 Ω load, 1 kHz
10
5
10
5
1
1
0.5
0.5
0.1
0.1
0.01
0.01
0.005
0.005
0.001
0.001
40m
100m 200m
500m
1
2
4
40m
100m 200m
500m
1
2
4
V
- Output Voltage - Vrms
V
- Output Voltage - Vrms
O
O
Figure 1.
Figure 2.
THD+N vs FREQUENCY
CHANNEL SEPARATION
3.3 V, 10 kΩ load, 2 Vrms
3.3 V, 5 kΩ load, 2 Vrms, Blue L to R, Red R to L
10
5
+0
3.3 V, 5 kW, 2Vrms
-10
-20
-30
-40
1
0.5
0.1
-50
-60
-70
0.01
Left to Right
Right to Left
-80
-90
0.005
0.001
-100
20
50 100 200
V
500 1k 2k
5k
- Output Voltage - Vrms
20k
20
50 100 200
500 1k 2k
f - Frequency - Hz
5k 10k20k
O
Blue: 10-µF ceramic ac-coupling capacitor.
Red: 10-µF electrolytic ac-coupling capacitor
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS, LINE DRIVER (continued)
VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, Gain = -2V/V (unless otherwise noted)
Gain vs Frequency
For the Different Gain Settings
Mute to Play
+22
+20
+18
+16
+14
+12
+10
+8
+6
+4
+2
-0
-2
20 50 100 200 500 1k 2k 5k 10k 20k 50k 200k
f - Frequency - Hz
Figure 5.
Figure 6.
Play to Mute
Figure 7.
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
APPLICATION INFORMATION
LINE DRIVER AMPLIFIERS
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 8 illustrates
the conventional line-driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click
and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can
reduce the fidelity of the audio output signal.
9-12V
Conventional solution
VDD
+
Mute Circuit
Co
+
Output
VDD/2
+
OPAMP
-
GND
MUTE
3.3V
DRV612 Solution
DirectPath
VDD
-
Output
GND
DRV612
VSS
MUTE
Figure 8. Conventional and DirectPath Line Driver
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail.
Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
Combining this with the built-in click- and pop-reduction circuit, the DirectPath amplifier requires no output
dc-blocking capacitors.
The bottom block diagram and waveform of Figure 8 illustrate the ground-referenced line-driver architecture. This
is the architecture of the DRV612.
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COMPONENT SELECTION
Charge Pump Flying Capacitor and VSS Capacitor
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The VSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical.
Decoupling Capacitors
The DRV612 is a DirectPath line-driver amplifier that requires adequate power-supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV612 is important for the performance of the amplifier. For filtering lower-frequency
noise signals, a 10-μF or greater capacitor placed near the audio power amplifier also helps, but it is not required
in most applications because of the high PSRR of this device.
Gain-Setting
The gain setting is programmed with the GAIN pin. Gain setting is latched durning power on. Table 1 lists the
gain settings.
NOTE: If gain pin is left unconnected (open) default gain of –2× is selected.
Table 1. Gain Settings
Gain_set RESISTOR
GAIN
–2×
GAIN (dB)
6
INPUT RESISTANCE
37 kΩ
249 kΩ(1)
82k5
51k1
34k8
27k4
20k5
15k4
11k5
9k09
7k5
–1×
0.0
55 kΩ
–1.5×
–2.3×
–2.5×
–3×
3.5
44 kΩ
7.2
33 kΩ
8
31 kΩ
9.5
28 kΩ
–3.5×
–4.0×
–5×
10.9
12
24 kΩ
22 kΩ
14
18 kΩ
–5.6×
–6.4×
–8.3×
–10×
15
17 kΩ
6k19
5k11
4k22
16.1
18.4
20
15 kΩ
12 kΩ
10 kΩ
(1) or higher
Internal Undervoltage Detection
The DRV612 contains an internal precision band-gap reference voltage and a comparator used to monitor the
supply voltage, VDD. The internal VDD monitor is set at 2.8 V with 200-mV hysteresis.
1.25 V
Bandgap
AMP Enable
VDD
Comparator
Internal VDD
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV612. These capacitors block the dc portion of the audio source and allow the DRV612 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the dc gain to 1, limiting the
dc-offset voltage at the output.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 2. Then the frequency and/or capacitance can be determined when one of the
two values is given.
1
1
fc
+
C
+
or
IN
IN
2p R
C
2p fc
R
IN IN
IN IN
(1)
For a fixed cutoff frequency of 2 Hz, the size of the input capacitance is shown in Table 2 with the capacitors
rounded up to nearest E6 values. For 20-Hz cutoff, simply divide the capacitor values with 10; e.g., for 1× gain,
150 nF is needed.
Table 2. Input Capacitor for Different Gain and Cutoff
Gain_set
RESISTOR
Gain
(dB)
INPUT
RESISTANCE
2 Hz
Cutoff
GAIN
249 kΩ
82k5
51k1
34k8
27k4
20k5
15k4
11k5
9k09
7k5
–2 ×
–1 ×
6
0.0
3.5
7.2
8
37 kΩ
55 kΩ
44 kΩ
33 kΩ
31 kΩ
28 kΩ
24 kΩ
22 kΩ
18 kΩ
17 kΩ
15 kΩ
12 kΩ
10 kΩ
2.2 µF
1.5 µF
2.2 µF
3.3 µF
3.3 µF
3.3 µF
3.3 µF
4.7 µF
4.7 µF
4.7 µF
6.8 µF
6.8 µF
10 µF
–1.5×
–2.3×
–2.5×
–3×
9.5
10.9
12
–3.5×
–4×
–5×
14
–5.6×
–6.4×
–8.3×
–10×
15
6k19
5k11
4k22
16.1
18.4
20
Pop-Free Power Up
Pop-free power up is ensured by keeping the MUTE pin low during power-supply ramp-up and -down. The pins
should be kept low until the input ac-coupling capacitors are fully charged before asserting the MUTE pin high,
this way proper pre-charge of the ac-coupling is performed and pop-less power up is achieved. Figure 9
illustrates the preferred sequence.
Supply
MUTE
_
Supply ramp
Time for ac -coupling
capasitors to charge
Figure 9. Power-Up/Down Sequence
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CAPACITIVE LOAD
The DRV612 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ω or larger for the line driver output.
LAYOUT RECOMMENDATIONS
A proposed layout for the DRV612 can be seen in the DRV612EVM User's Guide (SLOU248), and the Gerber
files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/DRV612evm.html. To access this
information, open the DRV612 product folder and look in the Tools and Software folder.
Ground traces are recommended to be routed as a star ground to minimize hum interference. VDD, VSS
decoupling capacitors and the charge-pump capacitors should be connected with short traces.
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SLOS690B –DECEMBER 2010–REVISED APRIL 2011
FOOTPRINT COMPATIBLE WITH TPA6139A2
The DRV612 stereo line driver is pin compatible with the headphone amplifier TPA6139A2. Therefore, a single
PCB layout can be used with stuffing options for different board configurations.
1
14
1
14
APPLICATION CIRCUIT
2
1
2
1
U11
IN_LEFT
OUT_LEFT
MUTE
IN_RIGHT
1
2
3
4
5
6
7
14
13
12
11
10
9
C11 2.2 mF
C12 2.2 mF
-IN_L
OUT_L
GND
MUTE
VSS
-IN_R
OUT_R
GAIN
GND
VDD
CP
OUT_RIGHT
1
2
R11 49 kW
1
2
1
2
1 mF
C15
C13 1 mF
CN
GND
8
+3.3 V
NC
NC
GND
2
1
1 mF
C14
2
1
2
1
IN_LEFT
IN_RIGHT
2.2 mF
C21
C22
2.2 mF
U21
1
12
11
10
9
OUT_LEFT
MUTE
OUT_RIGHT
OUT_L
OUT_R
GAIN
GND
2
3
4
GND
GND
MUTE
DRV612RGT
GND
VDD
GND
+3.3 V
R21
49 kW
C25
1 mF
C23
1 mF
2
C24
1
GND
GND
1 mF
GND
Figure 10. Single-Ended Input and Output, Gain Set to –1.5×
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REVISION HISTORY
Changes from Original (December 2010) to Revision A
Page
•
•
•
•
Added the QFN pinout drawing ............................................................................................................................................ 2
Added the QFN device To the PIN FUNCTIONS table ........................................................................................................ 2
Changed the Abs Max Storage Temp From: MIN = -40 To: MIN = -65 ............................................................................... 4
Changed the Gain resistor 2% tolerance values in the Programmable Gain Settings table For Gain Steps and Input
Impedance ............................................................................................................................................................................ 6
•
Changed Note 1 of the PROGRAMMABLE GAIN SETTINGS table From: If pin 12, GAIN, is left floating To: If the
GAIN pin is left floating ......................................................................................................................................................... 6
•
•
•
•
Changed From: CPUMP = C(VSS) = 10 µF To: CPUMP = C(VSS) = 1 µF in the Typical Characteristics condition text ................ 7
Changed the Gain_set RESISTOR values in Table 1 ........................................................................................................ 10
Changed the Gain_set RESISTOR values in Table 2 ........................................................................................................ 11
Removed references to DRV614 from the FOOTPRINT COMPATIBLE WITH TPA6139A2 secton ................................. 13
Changes from Revision A (February 2011) to Revision B
Page
•
•
Deleted the Product Preview note from the RGT package .................................................................................................. 3
Changed RIN = 10 kΩ, Rfb = 20 kΩ To Gain = -2V/V in the Typical Characteristics condition text ...................................... 7
14
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Product Folder Link(s) :DRV612
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV612PW
DRV612PWR
DRV612RGTR
DRV612RGTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
QFN
PW
PW
14
14
16
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
RGT
RGT
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV612PWR
DRV612RGTR
DRV612RGTT
TSSOP
QFN
PW
RGT
RGT
14
16
16
2000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
6.9
3.3
3.3
5.6
3.3
3.3
1.6
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q2
Q2
QFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV612PWR
DRV612RGTR
DRV612RGTT
TSSOP
QFN
PW
RGT
RGT
14
16
16
2000
3000
250
346.0
346.0
210.0
346.0
346.0
185.0
29.0
29.0
35.0
QFN
Pack Materials-Page 2
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