DRV8212PDSG [TI]
DRV8212P 11-V H-Bridge Motor Driver with PWM Interface and Low-Power Sleep Mode;
| 型号： | DRV8212PDSG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8212P 11-V H-Bridge Motor Driver with PWM Interface and Low-Power Sleep Mode |
| 文件： | 总34页 (文件大小：2835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8212P
SLVSFZ0A – JUNE 2021 – REVISED JULY 2021
DRV8212P 11-V H-Bridge Motor Driver with PWM Interface and Low-Power Sleep
Mode
1 Features
3 Description
•
N-channel H-bridge motor driver
The DRV8212P is an integrated motor driver with
four N-channel power FETs, charge pump regulator,
and protection circuitry. The tripler charge pump
architecture allows the device to operate down to 1.65
V to accommodate 1.8-V supply rails and low-battery
conditions. The charge pump integrates all capacitors
to reduce the overall solution size of the motor driver
on a PCB and allows for 100% duty cycle operation.
– MOSFET on-resistance: HS + LS 280 mΩ
– Drives one bidirectional brushed DC motor
– One single- or dual-coil latching relay
1.65-V to 11-V operating supply voltage range
High output current capability: 4-A peak
Standard PWM Interface (IN1/IN2)
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Ultra low-power sleep mode
– <84.5 nA @ VVM = 5 V, VVCC = 3.3 V, TJ = 25°C
– Pin-to-pin with DRV8837 & DRV8837C
Protection features
– Undervoltage lockout (UVLO)
– Overcurrent protection (OCP)
•
•
•
•
•
The DRV8212P supports an industry standard PWM
(IN1/IN2) control interface. The nSLEEP pin controls
a low-power sleep mode which achieves ultra-low
quiescent current draw by disabling the internal
circuitry.
•
•
The device can supply up to 4-A peak output current.
It operates with a supply voltage from 1.65 V to 5.5 V.
– Thermal shutdown (TSD)
Family of devices. See Section 5 for details.
– DRV8210: 1.65-11 V, 1 Ω, multiple interfaces
– DRV8210P: Sleep pin, PWM interface
– DRV8212: 1.65-11 V, 280 mΩ, multiple
interfaces
The driver offers robust internal protection features
include supply undervoltage lockout (UVLO), output
overcurrent (OCP), and device overtemperature
(TSD).
– DRV8212P: Sleep pin, PWM interface
– DRV8220: 4.5-18 V, 1 Ω, multiple interfaces
The DRV8212P is part of a family of devices which
come in pin-to-pin scalable RDS(on) and supply voltage
options to support various loads and supply rails
with minimal design changes. See Section 5 for
information on the devices in this family. View our full
portfolio of brushed motor drivers on ti.com.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Brushed DC motor, solenoid, & relay driving
Water, gas, & electricity meters
IP network camera IR cut filter
Video doorbell
Machine vision camera
Electronic smart lock
Electronic and robotic toys
Blood pressure monitors
Infusion pumps
Device Information
PART NUMBER (1)
PACKAGE
BODY SIZE (NOM)
DRV8212PDSG
WSON (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Electric toothbrush
Beauty & grooming
1.65 to 5.5 V
VCC
0 to 11 V
VM
DRV821xP
nSLEEP
Control Inputs
H-Bridge
Motor Driver
Protecꢀon
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8212P
SLVSFZ0A – JUNE 2021 – REVISED JULY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
9.3 Current Capability and Thermal Performance.......... 20
10 Power Supply Recommendations..............................25
10.1 Bulk Capacitance....................................................25
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Documentation Support.......................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks.............................................................27
12.5 Electrostatic Discharge Caution..............................27
12.6 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (July 2021)
Page
•
Updated HBM to 2000 V from 1500 V.................................................................................................................5
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5 Device Comparison
Table 5-1. Device Comparison Table
Supply voltage
Sleep mode
Pin-to-pin
devices
Device name
(V)
RDS(on) (mΩ)
IOCP (A)
Interface options
Packages
entry
950 (DRL),
1050 (DSG)
DRV8210
DRV8212
DRV8220
DRV8210P
1.65 to 11
1.65 to 11
4.5 to 18
1.65 to 11
1.76
4
Autosleep,
VCC
DRV8210,
DRV8212,
DRV8220
SOT563
(DRL), WSON
(DSG)
PWM, PH/EN, Half
Bridge
280
1000
1050
Autosleep,
nSLEEP pin
1.76
1.76
DRV8837,
DRV8837C,
DRV8210P,
DRV8212P
WSON (DSG)
WSON (DSG)
PWM
nSLEEP pin
DRV8212P
1.65 to 11
280
4
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6 Pin Configuration and Functions
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
nSLEEP
IN1
Thermal
Pad
IN2
Figure 6-1. DRV8212P DSG Package 8-Pin WSON Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
IN1
NO.
4
PWR Device ground. Connect to system ground.
6
I
I
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
IN2
5
Sleep mode input. Set this pin to logic high to enable the device. Set this pin to logic low to go to
low-power sleep mode. Internal pulldown resistor.
nSLEEP
7
I
OUT1
OUT2
2
3
O
O
H-bridge output. Connect to the motor or other load.
H-bridge output. Connect to the motor or other load.
Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient
bulk capacitance rated for VM.
VM
1
PWR
VCC
PAD
8
PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC.
Thermal pad. Connect to system ground.
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Power supply pin voltage
Logic power supply pin voltage
Power supply transient voltage ramp
Logic pin voltage
VM
-0.5
12
V
V
VCC
-0.5
5.75
VM, VCC
INx, nSLEEP
OUTx
0
2
V/µs
V
-0.5
5.75
Output pin voltage
-VSD
VVM+VSD
V
Output current(1)
OUTx
Internally Limited
Internally Limited
A
Ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
–40
–40
–65
125
150
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
discharge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±
2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500
V may actually have higher performance.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
0
NOM
MAX UNIT
VVM
VVCC
VIN
Motor power supply voltage
Logic power supply voltage
Logic pin voltage
VM
11
5.5
5.5
100
4
V
V
VCC
1.65
0
INx, nSLEEP
INx,
V
fPWM
PWM frequency
0
kHz
A
(1)
IOUT
TA
Peak output current
OUTx
0
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
TJ
(1) Power dissipation and thermal limits must be observed.
7.4 Thermal Information
DRV8212P
DSG (WSON)
8 PINS
77.9
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
97.3
42.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.9
ΨJB
42.4
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DRV8212P
DSG (WSON)
8 PINS
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
21.1
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 11 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).
Typical values are at TJ = 27°C, VVCC = 3.3 V, and VVM = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (VM, VCC)
IVM
VM active mode current
VM sleep mode current
VCC active mode current
VCC sleep mode current
Turnon time
nSLEEP = 3.3 V, IN1 = 0 V, IN2 = 3.3 V
Sleep mode, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C
nSLEEP = 3.3 V, IN1 = 0 V, IN2 = 3.3 V
Sleep mode, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C
Sleep mode to active mode delay
6
1
11 mA
IVMQ
IVCC
82
nA
0.21
11 mA
IVCCQ
tWAKE
tSLEEP
2.5
nA
μs
μs
100
Turnoff time
Active mode to sleep mode delay
2
LOGIC-LEVEL INPUTS (INx, nSLEEP)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Input pulldown resistance
0
1.45
49
0.4
5.5
V
V
VIH
VHYS
IIL
mV
µA
µA
kΩ
VI = 0 V
VI = 3.3 V
To GND
-1
1
IIH
20
50
RPD
100
DRIVER OUTPUTS (OUTx)
RDS(on)_HS
RDS(on)_LS
VSD
High-side MOSFET on resistance
IO = 0.2 A
140
140
1
mΩ
mΩ
V
Low-side MOSFET on resistance
Body diode forward voltage
Output rise time
IO = –0.2 A
IO = –1.5 A
tRISE
VOUTx rising from 10% to 90% of VVM
VOUTx falling from 90% to 10% of VVM
Input crosses 0.8 V to VOUTx = 0.1×VVM, IO = 1 A
Internal dead time
150
150
135
500
ns
ns
ns
ns
tFALL
Output fall time
tPD
Input to output propagation delay
Output dead time
tDEAD
PROTECTION CIRCUITS
Supply rising
1.65
V
V
VCC supply undervoltage lockout
VUVLO,VCC
(UVLO)
VUVLO_HYS Supply UVLO hysteresis
tUVLO Supply undervoltage deglitch time
IOCP
Supply falling
1.30
4
Rising to falling threshold
VVCC falling to OUTx disabled
80
mV
µs
A
3.8
Overcurrent protection trip point
Overcurrent protection deglitch time
Overcurrent protection retry time
Thermal shutdown temperature
Thermal shutdown hysteresis
tOCP
4.2
1.7
µs
ms
°C
°C
tRETRY
TTSD
THYS
153
193
22
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7.6 Typical Characteristics
1400
2000
1800
1600
1400
1200
1000
800
TJ = -40°C
VVM = 0 V
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
1200
1000
800
600
400
200
0
600
400
200
0
-200
-200
0
2
4
6
8
10
12
-40 -20
0
20
40
60
80 100 120 140 160
VM Supply Voltage (V)
Junction Temperature (°C)
A. VVCC = 3.3 V
A. VVCC = 3.3 V
Figure 7-1. Sleep Current (IVMQ) vs. Supply Voltage
(VVM
Figure 7-2. Sleep Current (IVMQ) vs. Junction
Temperature (TJ)
)
110
140
120
100
80
VVCC = 1.65 V
VVCC = 3.3 V
VVCC = 4.2 V
VVCC = 5.5 V
TJ = 27°C
TJ = -40°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
100
90
80
70
60
50
40
30
20
10
0
60
40
20
0
-10
-20
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
JunctionTemperature (°C)
VCC Supply Voltage (V)
A. VVM = 5 V
A. VVM = 5 V
Figure 7-4. Sleep Current (IVCCQ) vs. Junction
Temperature (TJ)
Figure 7-3. Sleep Current (IVCCQ) vs. Supply
Voltage (VVCC
)
8
9
8
7
6
5
6
4
4
3
VVM = 0 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
2
2
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0
1
0
-2
-1
0
2
4
6
8
10
12
-40 -20
0
20
40
60
80 100 120 140 160
VM Supply Voltage (V)
Junction Temperature (°C)
A. VVCC = 3.3 V
A. VVCC = 3.3 V
Figure 7-5. Active Current (IVM) vs. Supply Voltage
(VVM
Figure 7-6. Active Current (IVM) vs. Junction
Temperature (TJ)
)
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8
7.5
7
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
7
6
5
4
3
2
1
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VVCC = 1.65 V
VVCC = 3.3 V
VVCC = 4.2 V
VVCC = 5.5 V
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40 -20
A. VVM = 5 V
0
20
40
60
80 100 120 140 160
VCC Supply Voltage (V)
Junction Temperature (°C)
A. VVM = 5 V
Figure 7-7. Active Current (IVCC) vs. Supply Voltage
(VVCC
Figure 7-8. Active Current (IVCC) vs. Junction
Temperature (TJ)
)
270
250
230
210
190
170
150
130
110
90
200
190
180
170
160
150
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 0 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
140
130
120
110
100
VVM = 8 V
VVM = 11 V
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Junction Temperature (°C)
Supply Voltage, VVM = VVCC (V)
A. VVCC = 3.3 V
A. VVM = VVCC
Figure 7-10. High-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-9. High-Side RDS(on) vs. Supply Voltage
300
210
200
190
180
170
160
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
280
260
TJ = 150°C
240
220
200
180
160
140
120
100
150
VVM = 0 V
140
130
120
110
100
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
VVM = 8 V
VVM = 11 V
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Junction Temperature (°C)
Supply Voltage, VVM = VVCC (V)
A. VVCC = 3.3 V
A. VVM = VVCC
Figure 7-12. Low-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-11. Low-Side RDS(on) vs. Supply Voltage
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8 Detailed Description
8.1 Overview
DRV8212P is an integrated H-bridge driver controlled by a standard PWM (IN1/IN2) interface. The H-bridge can
drive loads like brushed DC motors and bistable relays bidirectionally. To reduce area and external components
on a printed circuit board, the device integrates a charge pump regulator and its capacitors. With separate motor
(VM) and logic (VCC) supplies, the VM voltage can drop to 0 V without significant impact to RDS(on) and without
triggering UVLO as long as the VCC supply is stable. The nSLEEP pin disables the device and puts it in a
low-power sleep mode. The package PCB footprint is compatible with the DRV8837 and DRV8837C.
The integrated protection features protect the device in the case of a system fault. These include undervoltage
lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD).
8.2 Functional Block Diagram
VM
VM
VM
Power
Charge
Pump
Gate
Drive
OUT1
VCC
Logic
nSLEEP
VM
BDC
Core Logic
Gate
Drive
IN1
IN2
OUT2
Control
Inputs
Overcurrent
Undervoltage
Thermal
GND
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8.3 Feature Description
8.3.1 External Components
Table 8-1 lists the recommended external components for the device.
Table 8-1. Recommended external components
COMPONENT
CVM1
PIN 1
PIN 2
GND
GND
RECOMMENDED
0.1-µF, low ESR ceramic capacitor, VM-rated.
Section 10.1, VM-rated.
VM
CVM2
VM
0.1-µF, low ESR ceramic capacitor, VCC-rated.
Only needed for DSG package variant.
CVCC
VCC
GND
8.3.2 Control Modes
The DRV8212P supports a standard PWM (IN1/IN2) interface. The inputs can accept DC or pulse-width
modulated (PWM) voltage signals with duty cycles from 0% to 100%. By default, the INx pins have internal
pulldown resistors to ensure the outputs are Hi-Z if no inputs are present. The following section shows the truth
table for the PWM interface. Additionally, the DRV8210P automatically handles the dead-time generation when
switching between the high-side and low-side MOSFET of a half-bridge. Figure 8-1 describes the naming and
configuration for the various H-bridge states described in the following sections.
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
OUT1
OUT2
OUT1
OUT2
2
3
2
3
Forward
Reverse
Figure 8-1. H-bridge states
8.3.2.1 PWM Control
The DRV8212P implements the same interface as the DRV8837/C devices for pin-to-pin replacement. The
nSLEEP pin controls sleep mode. Table 8-2 shows the truth table for the PWM interface.
Table 8-2. PWM control
nSLEEP
IN1
X
IN2
X
OUT1
Hi-Z
Hi-Z
L
OUT2
Hi-Z
Hi-Z
H
DESCRIPTION
Low-power sleep mode
Coast (H-bridge Hi-Z)
0
1
1
1
0
0
0
1
Reverse (OUT2 → OUT1)
Forward (OUT1 → OUT2)
1
0
H
L
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Table 8-2. PWM control (continued)
nSLEEP
IN1
IN2
OUT1
OUT2
DESCRIPTION
1
1
1
L
L
Brake (low-side slow decay)
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8.3.3 Protection Circuits
The DRV8212P is fully protected against supply undervoltage, output overcurrent, and device overtemperature
events.
8.3.3.1 Supply Undervoltage Lockout (UVLO)
If at any time the VCC supply voltage falls below the undervoltage lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge will be disabled. The charge pump and device logic are also disabled in this condition.
Normal operation resumes when VCC rises above the VUVLO threshold. The VM pin does not have UVLO and
may drop to 0 V as long as the VCC rail is stable. Table 8-3 summarizes the conditions when the device enters
UVLO.
Table 8-3. UVLO response conditions
VVM
VVCC
Device response
UVLO
0 V to VMMAX
0 V to VMMAX
<1.65 V
>1.65 V
Normal operation
8.3.3.2 OUTx Overcurrent Protection (OCP)
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short
circuit events. If the output current exceeds the overcurrent threshold, IOCP, for longer than the overcurrent
deglitch time, tOCP, all MOSFETs in the H-bridge will be disabled. After tRETRY, the MOSFETs are re-enabled
according to the state of the IN1 and IN2 pins. If the overcurrent condition is still present, the cycle repeats;
otherwise normal device operation resumes.
8.3.3.3 Thermal Shutdown (TSD)
If the die temperature exceeds the overtemperature limit TTSD, all MOSFETs in the H-bridge will be disabled.
Normal operation will resume when the overtemperature condition is removed and the die temperature drops
below the TTSD threshold.
8.3.4 Pin Diagrams
8.3.4.1 Logic-Level Inputs
Figure 8-2 shows the input structure for the logic-level input pins nSLEEP, IN1, and IN2.
100 kꢀ
Figure 8-2. Logic-level input
8.4 Device Functional Modes
The DRV8212P has several different modes of operation depending on the system inputs and conditions.
8.4.1 Active Mode
In active mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive
inputs. The device leaves active mode when entering low-power sleep mode or fault mode. When leaving sleep
mode, nSLEEP must be held high for longer than the duration of tWAKE to enable the device.
8.4.2 Low-Power Sleep Mode
The DRV8212P supports a low-power sleep mode to reduce current consumption from VM and VCC when the
driver is not active. In low-power sleep mode, the device draws minimal current denoted by IVCCQ and IVMQ
.
When the nSLEEP pin is logic low, the device is in sleep mode. The nSLEEP pin has an internal pulldown
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resistor to put the device into sleep mode if the nSLEEP pin is floating. The device returns to active mode when
the nSLEEP pin is logic high.
8.4.3 Fault Mode
The DRV8212P enters fault mode when encountering a fault. This protects the device and the output load.
Device behavior in fault mode depends on the fault condition, as described in Section 8.3.3. The device leaves
the fault mode and re-enters active mode once the recovery condition is met. Table 8-4 summarizes the fault
conditions, response, and recovery.
Table 8-4. Fault condition summary
FAULT
CONDITION
H-BRIDGE
RECOVERY
Undervoltage Lockout
(UVLO)
VCC < VUVLO,VCC falling
Disabled
VCC > VUVLO,VCC rising
Overcurrent (OCP)
IOUT > IOCP
TJ > TTSD
Disabled
Disabled
tRETRY
Thermal Shutdown (TSD)
TJ < TTSD – THYS
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The application examples in this section highlight how to use the DRV8212P.
9.2 Typical Application
9.2.1 Full-Bridge Driving
A typical application for the DRV8212P is driving a brushed DC motor or single-coil bistable latching relay
bidriectionally (in forward and reverse) using the outputs as a full-bridge, or H-bridge, configuration. Figure 9-1
shows an example schematic for driving a motor, and Figure 9-2 shows an example schematic for driving a
latching relay.
VM
VM
VCC
VCC
VCC
0.1 …F
VCC
CBulk
0.1 …F
CBulk
Controller
0.1 …F
1
2
3
4
8
7
6
5
DRV821xPDSG
VM
VCC
nSLEEP
IN1
0.1 …F
Controller
1
2
3
4
8
7
6
5
DRV821xPDSG
OUT1
OUT2
GND
O
VM
VCC
nSLEEP
IN1
Thermal
Pad
PWM
PWM
OUT1
OUT2
GND
O
Single-
coil
relay
Thermal
Pad
BDC
IN2
PWM
PWM
IN2
Figure 9-2. PWM interface relay-driving application
Figure 9-1. PWM interface motor-driving
application
9.2.1.1 Design Requirements
Table 9-1 lists the required parameters for a typical usage case.
Table 9-1. System design requirements
DESIGN PARAMETER
Motor supply voltage
Logic supply voltage
Target motor RMS current
Target relay current
REFERENCE
EXAMPLE VALUE
11 V
VM
VCC
Imotor
Irelay
3.3 V
300 mA
50 mA
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Supply Voltage
The appropriate supply voltage depends on the ratings of the load (motor, solenoid, relay, etc.). In the case of a
brushed DC motor, the supply voltage will impact the desired RPM. A higher voltage spins a brushed dc motor
faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of
current change through the inductive windings of a motor, solenoid, or relay.
9.2.1.2.2 Control Interface
Section 8.3.2.1 describes the PWM control interface. The DRV8212P is pin-to-pin compatible with the DRV8837
and DRV8837C PCB footprints. Figure 9-3 and Figure 9-4 show waveform examples of driving a motor with the
PWM interface. Figure 9-5 and Figure 9-6 show waveform examples of driving a single-coil relay with the PWM
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interface. The relay can be driven between the forward/reverse states and the brake/coast states as shown in
the figures.
9.2.1.2.3 Low-Power Operation
Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting
all inputs as a logic low to minimize system power.
9.2.1.3 Application Curves
A. Channel 1 = IN1
Channel 4 = OUT2
Channel 2 = IN2 Channel 3 = OUT1
A. Channel 1 = IN1 Channel 2 = Motor Channel 3 = OUT1
Current
Channel 4 = OUT2
Figure 9-3. PWM driving for a motor with 50% duty
cycle, INx and OUTx voltages
Figure 9-4. PWM driving for a motor with 50% duty
cycle, signals and motor current
A. Channel 1 = IN1
Channel 4 = VOUT2 Channel 6 = Relay Channel 7 = Relay
Switch Coil Current
Channel 2 = IN2 Channel 3 = VOUT1
A. Channel 1 = IN1
Channel 4 = VOUT2 Channel 6 = Relay Channel 7 = Relay
Switch Coil Current
Channel 2 = IN2 Channel 3 = VOUT1
Figure 9-5. PWM driving for a single-coil latching
relay with driving profile FORWARD → COAST →
REVERSE → COAST
Figure 9-6. PWM driving for a single-coil latching
relay with driving profile FORWARD → BRAKE →
REVERSE → BRAKE
9.2.2 Dual-Coil Relay Driving
The PWM interface may also be used to drive a dual-coil latching relay. Figure 9-7 shows an example
schematic.
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VM
VCC
VCC
CBulk
0.1 …F
Controller
0.1 …F
1
2
3
4
8
7
6
5
DRV821xPDSG
VM
VCC
nSLEEP
IN1
OUT1
OUT2
GND
O
Thermal
Pad
PWM
PWM
VM
Dual-
coil
relay
IN2
Figure 9-7. Dual-coil relay driving
9.2.2.1 Design Requirements
Table 9-2 provides example requirements for a dual-coil relay application.
Table 9-2. System design requirements
DESIGN PARAMETER
Motor supply voltage
Logic supply voltage
Relay current
REFERENCE
EXAMPLE VALUE
VM
6 V
VCC
3.3 V
IOUT1, IOUT2
500 mA pulse for 100 ms
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Supply Voltage
The appropriate supply voltage depends on the ratings of the load.
9.2.2.2.2 Control Interface
The PWM interface can be used to drive dual-coil relays. Section 8.3.2.1 describes the PWM control interface.
Figure 9-8 and Figure 9-9 show a schematic and timing diagram for driving a dual-coil relay with the PWM
interface.
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VM
VM
Sleep
mode
Sleep
mode
Sleep
mode
Drive Coil1
Drive Coil2
IN1
IN2
Coil1
IOUT1
Coil2
VM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VOUT1
VOUT1
VOUT2
IOUT2
GND
VM
Dual-coil
relay
VOUT2
GND
IOUT1
IOUT2
Figure 9-8. Schematic of dual-coil relay driven by
the OUTx H-bridge
Figure 9-9. Timing diagram for driving a dual-coil
relay with PWM interface
Table 9-3 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and
output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will
go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true
when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so
extra external diodes are not needed. Figure 9-10 shows oscilloscope traces for this application.
Table 9-3. PWM control table for dual-coil relay driving
IN1
0
IN2
OUT1
Hi-Z
L
OUT2
Hi-Z
H
DESCRIPTION
Outputs disabled (H-Bridge Hi-Z)
Drive Coil1
0
0
1
1
0
H
L
Drive Coil2
Drive Coil1 and Coil2 (invalid state for a
dual-coil latching relay)
1
1
L
L
9.2.2.2.3 Low-Power Operation
Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting
all inputs as a logic low to minimize system power.
To minimize leakage current into the OUTx pins (especially in battery-powered applications), connect the load
from OUTx to GND. As shown in the previous section, connecting the load from OUTx to VM is also possible,
but there may be some small leakage current into OUTx when it is disabled.
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9.2.2.3 Application Curves
A.
Channel 1 = IN1
Channel 4 = VOUT2
Channel 2 = IN2
Channel 3 = VOUT1
Channel 7 = Relay Coil1 Current
Channel 6 = Relay Switch
Channel 8 = Relay Coil2 Current
Figure 9-10. PWM driving for dual-coil relay
9.2.3 Current Sense
A small shunt resistor on the GND pin can provide current sense information back to the microcontroller ADC.
The microcontroller can use this information to detect motor load conditions, such as stall. shows an example
schematic using the DRL package. If better current sensing dynamic range is needed, an amplifier can be added
as shown in Figure 9-11.
The DSG thermal pad may be connected to the board ground net or the GND pin/sense signal net.
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VM
VCC
0.1 …F
VCC
CBulk
0.1 …F
Controller
1
2
3
4
8
7
6
5
DRV821xPDSG
VM
VCC
nSLEEP
IN1
OUT1
OUT2
GND
O
Thermal
Pad
BDC
PWM
PWM
IN2
TLV905I
+
ADC
œ
RSENSE
CFILTER
R2
R1
Figure 9-11. Current sense amplifier example
9.2.3.1 Design Requirements
Table 9-4 provides example requirements for a current sensing application.
Table 9-4. System design requirements
DESIGN PARAMETER
Motor supply voltage
REFERENCE
EXAMPLE VALUE
VM
6 V
3.3 V
Logic supply voltage
VCC
Maximum voltage across RSENSE
Motor RMS current
VSENSE
150 mV
500 mA
1 A
IOUT1, IOUT2
IOUT1,stall, IOUT2,stall
Motor stall current
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Shunt Resistor Sizing
The Absolute Maximum Ratings for the INx pins set the maximum voltage across the shunt resistor. If the signal
on the INx pin is low, referenced at the board ground, then the INx pins are at a negative voltage with respect
to the GND pin voltage. This sets the maximum sense voltage/GND pin voltage to 0.5 V. Figure 9-12 shows the
relative pin voltages.
IN1
VIN2 = 0 V
IN2
+
VGND,pin = -0.5 V
-
GND
+
VSENSE = 0.5 V
-
RSENSE
VGND,board = 0 V
Figure 9-12. Pin voltages with respect to board ground using current sense resistor
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This example uses 150 mV for the maximum VSENSE, which is less than 0.5 V and provides some margin for
safety or error. The maximum current through the motor will be the stall current, which is 1 A for this example.
With this information, the sense resistance RSENSE can be calculated from the equation below.
RSENSE = VSENSE / ISTALL = 0.15 / 1 = 0.15 Ω
(1)
Because the device GND pin voltage will vary with current through the sense resistor, the designers must
also ensure that the logic pins meet VIL and VIH parameters,and the supply remains above VUVLO for proper
operation.
9.3 Current Capability and Thermal Performance
The output current and power dissipation capabilities of the driver depends heavily on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
9.3.1 Power Dissipation and Output Current Capability
Total power dissipation for the device consists of three main components: quiescent supply current dissipation
(PVM and PVCC), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction)
losses (PRDS). While other factors may contribute additional power losses, they are typically insignificant
compared to the three main items.
PTOT = PVM + PVCC + PSW + PRDS
(2)
PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current
specification. PVCC can be calculated from the nominal logic supply voltage (VVCC) and the IVCC active mode
current specification. When VVCC < VVM, the DRV8212 draws active current from the VM pin rather than the VCC
pin. During this operating condition, IVCC is typically less than 500 nA.
PVM = VVM x IVM
(3)
(4)
(5)
(6)
PVM = 30 mW = 5 V x 6 mA
PVCC = VVCC x IVCC
PVCC = 0.693 mW = 3.3 V x 0.21 mA
PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IRMS), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL
(7)
(8)
PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM
PSW_FALL = 0.5 x VM x IRMS x tFALL x fPWM
PSW_RISE = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz
PSW_FALL = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz
PSW = 7.5 mW = 3.75 mW + 3.75 mW
(9)
(10)
(11)
(12)
PRDS can be calculated from the device RDS(on) and average output current (IRMS).
PRDS = IRMS 2 x (RDS(ON)_HS + RDS(ON)_LS
)
(13)
RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85
°C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows
this derating factor. Alternatively, the Section 7.6 section shows curves that plot how RDS(on) changes with
temperature.
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PRDS = 420 mW = (1 A)2 x (140 mΩ x 1.5 + 140 mΩ x 1.5)
(14)
Based on the example calculations above, the expressions below calculate the total expected power dissipation
for the device.
PTOT = PVM + PVCC + PSW + PRDS
(15)
(16)
PTOT = 458 mW = 30 mW + 0.693 mW + 7.5 mW + 420 mW
The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking
around the device. Section 9.3.2 describes this dependence in greater detail.
TJ = (PTOT x RθJA) + TA
(17)
(18)
TJ = 121°C = (0.458 W x 77.9 °C/W) + 85°C
The device junction temperature should remain below its absolute maximum rating for all system operating
conditions. The calculations in this section provide reasonable estimates for junction temperature. However,
other methods based on temperature measurements taken during system operation are more realistic and
reliable. Additional information on motor driver current ratings and power dissipation can be found in Section
9.3.2 and Section 12.1.1.
9.3.2 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria:
•
2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only
present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
– Top layer: DRV8212P WSON package footprint and copper plane heatsink. Top layer copper area is
varied in simulation.
– Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8212P.
Bottom layer copper area varies with top copper area.
•
4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner
planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm
diameter, 0.025 mm Cu plating).
– Top layer: DRV8212P WSON package footprint and copper plane heatsink. Top layer copper area is
varied in simulation.
– Mid layer 1: GND plane thermally connected to DRV8212P thermal pad through vias. The area of the
ground plane is 74.2 mm x 74.2 mm.
– Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
– Bottom layer: signal layer with small copper pad underneath DRV8212P and thermally connected through
via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the
package (2 mm x 2 mm). Bottom pad size remains constant as top copper plane is varied.
Figure 9-13 shows an example of the simulated board for the HTSSOP package. Table 9-5 shows the
dimensions of the board that were varied for each simulation.
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A
A
Figure 9-13. WSON PCB model top layer
Table 9-5. Dimension A for 16-pin PWP package
Cu area (mm2)
Dimension A (mm)
2
4
15.11
20.98
29.27
40.99
8
16
9.3.2.1 Steady-State Thermal Performance
"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long
period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter)
change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more
layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the
PCB layout.
38
4 layer, 1 oz
4 layer, 2 oz
2 layer, 1 oz
2 layer, 2 oz
36
34
32
30
28
2
4
6
8
10
12
14
16
Top layer copper area (cm2)
Figure 9-14. WSON, PCB junction-to-ambient
thermal resistance vs copper area
Figure 9-15. WSON, junction-to-board
characterization parameter vs copper area
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9.3.2.2 Transient Thermal Performance
The motor driver may experience different transient driving conditions that cause large currents to flow for a
short duration of time. These may include
•
•
Motor start-up when the rotor is initially stationary.
Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent
protection triggers.
•
Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance in
addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the
junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for
1-oz and 2-oz copper layouts for the WSON package. These graphs indicate better thermal performance with
short current pulses. For short periods of drive time, the device die size and package dominates the thermal
performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both
graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of
the drive pulse duration increases. Long pulses can be considered steady-state performance.
Figure 9-16. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts
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Figure 9-17. WSON package junction-to-ambient thermal impedance for 2-oz copper layouts
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10 Power Supply Recommendations
10.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local bulk capacitance needed depends on a variety of factors, including:
•
•
•
•
•
The highest current required by the motor or load
The capacitance of the power supply and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple of the system
The motor braking method (if applicable)
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended minimum value, but system level testing is required to
determine the appropriately sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VBB
+
Motor
Driver
+
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. System Supply Parasitics Example
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11 Layout
11.1 Layout Guidelines
Since the DRV8212P device has integrated power MOSFETs capable of driving high current, careful attention
should be paid to the layout design and external component placement. Some design and layout guidelines
are provided below. For more information on layout recommendations, please see the application note Best
Practices for Board Layout of Motor Drivers.
•
•
•
•
Low ESR ceramic capacitors should be utilized for the VM-to-GND and VCC-to-GND bypass capacitors. X5R
and X7R types are recommended.
The VM and VCC power supply capacitors should be placed as close to the device as possible to minimize
the loop inductance.
The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as
close as possible to the device to minimize the loop inductance.
VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground.
Thick metal routing should be utilized for these traces as is feasible.
•
•
GND should connect directly on the PCB ground plane.
The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
•
11.2 Layout Example
CBULK
0.1 …F
0.1 …F
VM
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
nSLEEP
IN1
VCC
MOT+
MOT-
Thermal
Pad
IN2
Figure 11-1. Simplified Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, Calculating Motor Driver Power Dissipation application report
Texas Instruments, PowerPAD™ Made Easy application report application report
Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, Understanding Motor Driver Current Ratings application report
Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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Product Folder Links: DRV8212P
DRV8212P
SLVSFZ0A – JUNE 2021 – REVISED JULY 2021
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8212PDSGR
ACTIVE
WSON
DSG
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
212P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2021, Texas Instruments Incorporated
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