DRV8212_V03 [TI]
DRV8212 11-V H-Bridge Motor Driver with PWM, PH/EN, and Half-Bridge Control Interfaces and Low-Power Sleep Mode;
| 型号： | DRV8212_V03 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8212 11-V H-Bridge Motor Driver with PWM, PH/EN, and Half-Bridge Control Interfaces and Low-Power Sleep Mode |
| 文件： | 总49页 (文件大小：4282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8212
SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
DRV8212 11-V H-Bridge Motor Driver with PWM, PH/EN, and Half-Bridge Control
Interfaces and Low-Power Sleep Mode
1 Features
3 Description
•
N-channel H-bridge motor driver
The DRV8212 is an integrated motor driver with
four N-channel power FETs, charge pump regulator,
and protection circuitry. The tripler charge pump
architecture allows the device to operate down to 1.65
V to accommodate 1.8-V supply rails and low-battery
conditions. The charge pump integrates all capacitors
to reduce the overall solution size of the motor driver
on a PCB and allows for 100% duty cycle operation.
– MOSFET on-resistance: HS + LS 280 mΩ
– Drives one bidirectional brushed DC motor
– Two unidirectional brushed DC motors
– One single- or dual-coil latching relay
– Push-pull and bistable solenoids
– Other resistive, inductive, or LED loads
1.65-V to 11-V operating supply voltage range
High output current capability:
– Full-bridge: 4-A peak
– Half-bridge: 4-A peak per output
– Parallel half-bridge: 8-A peak
Multiple interfaces for flexibility and reduced GPIO
Standard PWM Interface (IN1/IN2)
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Ultra low-power sleep mode
– <84.5 nA @ VVM = 5 V, VVCC = 3.3 V, TJ = 25°C
– Timed autosleep mode to reduce GPIO
Protection features
– Undervoltage lockout (UVLO)
– Overcurrent protection (OCP)
– Thermal shutdown (TSD)
Family of devices. See Device Comparison for
details.
– DRV8210: 1.65-11 V, 1 Ω, multiple interfaces
– DRV8210P: Sleep pin, PWM interface
– DRV8212: 1.65-11 V, 280 mΩ, multiple
interfaces
– DRV8212P: Sleep pin, PWM interface
– DRV8220: 4.5-18 V, 1 Ω, multiple interfaces
•
•
The DRV8212 supports multiple control interface
modes including: PWM (IN1/IN2), phase/enable (PH/
EN), independent half-bridge, and parallel half-bridge.
Each interface supports a low-power sleep mode to
achieve ultra-low quiescent current draw by shutting
down most of the internal circuitry.
•
•
•
•
The device can supply up to 4-A peak output current.
It operates with a supply voltage from 1.65 V to 5.5 V.
The driver offers robust internal protection features
include supply undervoltage lockout (UVLO), output
overcurrent (OCP), and device overtemperature
(TSD).
•
•
The DRV8212 is part of a family of devices which
come in pin-to-pin scalable RDS(on) and supply voltage
options to support various loads and supply rails with
minimal design changes. See Device Comparison for
information on the devices in this family. View our full
portfolio of brushed motor drivers on ti.com.
Device Information
PART NUMBER (1)
DRV8212DSG
PACKAGE
WSON (8)
SOT563 (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
1.20 mm × 1.60 mm
2 Applications
DRV8212DRL
•
•
•
•
•
•
•
•
•
•
•
Brushed DC motor, solenoid, & relay driving
Water, gas, & electricity meters
IP network camera IR cut filter
Video doorbell
Machine vision camera
Electronic smart lock
Electronic and robotic toys
Blood pressure monitors
Infusion pumps
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1.65 to 5.5 V
VCC
0 to 11 V
VM
DRV821x
MODE
Control Inputs
H-Bridge
Motor Driver
Electric toothbrush
Beauty & grooming
Protecꢀon
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8212
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SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics DSG Package ....................... 7
7.7 Typical Characteristics DRL Package ......................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
9.3 Current Capability and Thermal Performance.......... 28
10 Power Supply Recommendations..............................35
10.1 Bulk Capacitance....................................................35
11 Layout...........................................................................36
11.1 Layout Guidelines................................................... 36
11.2 Layout Example...................................................... 36
12 Device and Documentation Support..........................38
12.1 Documentation Support.......................................... 38
12.2 Receiving Notification of Documentation Updates..38
12.3 Support Resources................................................. 38
12.4 Trademarks.............................................................38
12.5 Electrostatic Discharge Caution..............................38
12.6 Glossary..................................................................38
13 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (July 2021)
Page
•
Updated HBM to 2000 V from 1500 V.................................................................................................................5
Changes from Revision A (July 2021) to Revision B (August 2021)
Page
•
Updated Device Status to Production Data........................................................................................................ 1
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5 Device Comparison
Table 5-1. Device Comparison Table
Supply voltage
Sleep mode
entry
Pin-to-pin
devices
Device name
(V)
RDS(on) (mΩ)
IOCP (A)
Interface options
Packages
950 (DRL),
1050 (DSG)
DRV8210
DRV8212
DRV8220
DRV8210P
1.65 to 11
1.65 to 11
4.5 to 18
1.65 to 11
1.76
4
Autosleep,
VCC
DRV8210,
DRV8212,
DRV8220
SOT563
(DRL), WSON
(DSG)
PWM, PH/EN, Half
Bridge
280
1000
1050
Autosleep,
nSLEEP pin
1.76
1.76
DRV8837,
DRV8837C,
DRV8210P,
DRV8212P
WSON (DSG)
WSON (DSG)
PWM
nSLEEP pin
DRV8212P
1.65 to 11
280
4
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6 Pin Configuration and Functions
IN1
IN2
1
2
3
6
5
4
OUT1
VM
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
MODE
IN1/PH
IN2/EN
GND
OUT2
Thermal
Pad
Figure 6-1. DRV8212 DRL Package 6-Pin SOT Top
View
Figure 6-2. DRV8212 DSG Package 8-Pin WSON
Top View
Table 6-1. Pin Functions
PIN
DRL
3
TYPE
DESCRIPTION
NAME
GND
DSG
4
PWR Device ground. Connect to system ground.
IN1
1
—
6
I
I
I
I
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
H-bridge control input. See Section 8.3.2. Internal pulldown resistor.
IN1/PH
IN2
—
2
—
5
IN2/EN
—
H-bridge control input mode. See Section 8.3.2. Tri-level input referenced to VCC pin
voltage.
MODE
—
7
I
OUT1
OUT2
6
4
2
3
O
O
H-bridge output. Connect to the motor or other load.
H-bridge output. Connect to the motor or other load.
Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well
as sufficient bulk capacitance rated for VM.
VM
5
1
PWR
Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for
VCC.
VCC
PAD
—
—
8
PWR
—
—
Thermal pad. Connect to system ground.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Power supply pin voltage
Logic power supply pin voltage, DSG
Power supply transient voltage ramp
Logic pin voltage
VM
-0.5
12
V
V
VCC
-0.5
5.75
VM, VCC
INx, IN1/PH, IN2/EN
MODE
0
2
5.75
V/µs
V
-0.5
Tri-level pin voltage
-0.5
VVCC+0.3
VVM+VSD
Internally Limited
125
Output pin voltage
OUTx
-VSD
V
Output current(1)
OUTx
Internally Limited
A
Ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
–40
–40
–65
°C
°C
°C
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
discharge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±
2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500
V may actually have higher performance.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
1.65
0
NOM
MAX UNIT
VVM
VVM
VVCC
VIN
Motor power supply voltage, DRL
Motor power supply voltage, DSG
Logic power supply voltage, DSG
Logic pin voltage
VM
11
11
V
V
VM
VCC
1.65
0
5.5
5.5
100
4
V
INx, IN1/PH, IN2/EN, MODE
INx, IN1/PH, IN2/EN
OUTx
V
fPWM
PWM frequency
0
kHz
A
(1)
IOUT
TA
Peak output current
0
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
TJ
(1) Power dissipation and thermal limits must be observed.
7.4 Thermal Information
DRV8212
DRL (SOT563)
6 PINS
DRV8212
DSG (WSON)
8 PINS
77.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
138.5
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.4
97.3
25.8
42.6
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UNIT
SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
DRV8212
DRL (SOT563)
6 PINS
DRV8212
DSG (WSON)
8 PINS
4.9
THERMAL METRIC(1)
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
°C/W
°C/W
ΨJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.6
42.4
RθJC(bot)
21.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
DRL: 1.65 V ≤ VVM ≤ 11 V, DSG: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 11 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).
Typical values are at TJ = 27°C, VVCC = 3.3 V, and VVM = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY, DRL (VM)
IVM
VM active mode current
VM sleep mode current
Turnon time
IN1 = 0 V, IN2 = 3.3 V
6
5
11 mA
INx = 0 V, after waiting tsleep, VVM = 5 V,
TJ = 27°C
IVMQ
tWAKE
80
nA
μs
Sleep mode to active mode delay
100
tAUTOSLEEP Autosleep turnoff time
Active mode to autosleep mode delay
0.9
2.6 ms
POWER SUPPLIES, DSG (VM, VCC)
IVM
VM active mode current
VM sleep mode current
VM sleep mode current
VCC active mode current
VCC sleep mode current
VCC sleep mode current
Turnon time
IN1 = 0 V, IN2 = 3.3 V
6
1
11 mA
IVMQ
Sleep mode, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C
INx = 0 V, VVM = 5 V, VVCC < 0.35 V, TJ = 27°C
IN1 = 0 V, IN2 = 3.3 V
82
89
nA
nA
IVMQ_UV
IVCC
2
0.21
11 mA
IVCCQ
IVCCQ_UV
tWAKE
Sleep mode, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C
INx = 0 V, VVM = 5 V, VVCC < 0.35 V, TJ = 27°C
Sleep mode to active mode delay
2.5
nA
nA
μs
35
100
tAUTOSLEEP Autosleep turnoff time
Active mode to autosleep mode delay
0.9
2.6 ms
LOGIC-LEVEL INPUTS (INx, IN1/PH, IN2/EN)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Input pulldown resistance
0
1.45
49
0.4
5.5
V
V
VIH
VHYS
IIL
mV
µA
µA
kΩ
VI = 0 V
VI = 3.3 V
To GND
-1
1
IIH
20
50
RPD
100
TRI-LEVEL INPUTS (MODE)
0.22 ×
VVCC
VTIL
VTIZ
VTIH
Tri-level input logic low voltage
0
V
V
V
0.60 ×
VVCC
0.675 ×
VVCC
Tri-level input Hi-Z voltage
0.75 ×
VVCC
Tri-level input logic high voltage
5.5
to GND, sleep mode
to GND, active mode
to VCC
1
130
75
MΩ
kΩ
kΩ
RTPD
RTPU
Tri-level pulldown resistance
Tri-level pullup resistance
DRIVER OUTPUTS (OUTx)
RDS(on)_HS
RDS(on)_LS
VSD
High-side MOSFET on resistance
IO = 0.2 A
IO = –0.2 A
IO = –1.5 A
140
140
1
mΩ
mΩ
V
Low-side MOSFET on resistance
Body diode forward voltage
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DRL: 1.65 V ≤ VVM ≤ 11 V, DSG: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 11 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).
Typical values are at TJ = 27°C, VVCC = 3.3 V, and VVM = 5 V.
PARAMETER
TEST CONDITIONS
VOUTx rising from 10% to 90% of VVM
VOUTx falling from 90% to 10% of VVM
Input crosses 0.8 V to VOUTx = 0.1×VVM, IO = 1 A
Internal dead time
MIN
TYP
150
150
135
500
186
-3
MAX UNIT
tRISE
tFALL
tPD
Output rise time
ns
ns
ns
ns
μA
nA
Output fall time
Input to output propagation delay
Output dead time
tDEAD
OUTx is Hi-Z, RL = 20 Ω to VM
IOUT
Leakage current into OUTx
OUTx is Hi-Z, RL = 20 Ω to GND
PROTECTION CIRCUITS
Supply rising
1.65
1.65
V
V
VM supply undervoltage lockout
(UVLO), DRL
VUVLO,VM
Supply falling
1.30
1.30
Supply rising
V
VCC supply undervoltage lockout
(UVLO), DSG
VUVLO,VCC
Supply falling
V
VUVLO_HYS Supply UVLO hysteresis
Rising to falling threshold
80
mV
VVM falling (DRL) or VVCC falling (DSG) to OUTx
disabled
tUVLO
Supply undervoltage deglitch time
3.8
µs
IOCP
Overcurrent protection trip point
Overcurrent protection deglitch time
Overcurrent protection retry time
Thermal shutdown temperature
Thermal shutdown hysteresis
4
A
tOCP
4.2
1.7
µs
ms
°C
°C
tRETRY
TTSD
THYS
153
193
22
7.6 Typical Characteristics DSG Package
1400
2000
1800
1600
1400
1200
1000
800
TJ = -40°C
VVM = 0 V
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
1200
1000
800
600
400
200
0
600
400
200
0
-200
-200
0
2
4
6
8
10
12
-40 -20
0
20
40
60
80 100 120 140 160
VM Supply Voltage (V)
Junction Temperature (°C)
A. VVCC = 3.3 V
A. VVCC = 3.3 V
Figure 7-1. Sleep Current (IVMQ) vs. Supply Voltage
(VVM
Figure 7-2. Sleep Current (IVMQ) vs. Junction
Temperature (TJ)
)
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110
100
90
80
70
60
50
40
30
20
10
0
140
VVCC = 1.65 V
VVCC = 3.3 V
VVCC = 4.2 V
VVCC = 5.5 V
TJ = 27°C
TJ = -40°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
120
100
80
60
40
20
0
-10
-20
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
JunctionTemperature (°C)
VCC Supply Voltage (V)
A. VVM = 5 V
A. VVM = 5 V
Figure 7-4. Sleep Current (IVCCQ) vs. Junction
Temperature (TJ)
Figure 7-3. Sleep Current (IVCCQ) vs. Supply
Voltage (VVCC
)
8
9
8
7
6
5
6
4
4
3
VVM = 0 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
2
2
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0
1
0
-2
-1
0
2
4
6
8
10
12
-40 -20
0
20
40
60
80 100 120 140 160
VM Supply Voltage (V)
Junction Temperature (°C)
A. VVCC = 3.3 V
A. VVCC = 3.3 V
Figure 7-5. Active Current (IVM) vs. Supply Voltage
(VVM
Figure 7-6. Active Current (IVM) vs. Junction
Temperature (TJ)
)
8
7
6
5
4
3
2
1
0
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVCC = 1.65 V
VVCC = 3.3 V
VVCC = 4.2 V
VVCC = 5.5 V
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40 -20
A. VVM = 5 V
0
20
40
60
80 100 120 140 160
VCC Supply Voltage (V)
Junction Temperature (°C)
A. VVM = 5 V
Figure 7-7. Active Current (IVCC) vs. Supply Voltage
(VVCC
Figure 7-8. Active Current (IVCC) vs. Junction
Temperature (TJ)
)
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60
55
50
45
40
35
30
25
20
15
10
5
2000
1800
1600
1400
1200
1000
800
VVM = 0 V
VVM = 0 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 5 V
VVM = 8 V
VVM = 11 V
600
400
0
200
-5
-10
0
-40 -20
0
20
40
60
80 100 120 140 160
-200
Junction Temperature (°C)
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
A. VVCC < 0.35 V
A. VVCC < 0.35 V
Figure 7-10. VCC supply current when VCC is low
(IVCCQ_UV) vs. Junction Temperature (TJ)
Figure 7-9. VM supply current when VCC is low
(IVMQ_UV) vs. Junction Temperature (TJ)
270
200
190
180
170
160
150
TJ = -40°C
250
230
210
190
170
150
130
110
90
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 0 V
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
140
130
120
110
100
VVM = 8 V
VVM = 11 V
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Junction Temperature (°C)
Supply Voltage, VVM = VVCC (V)
A. VVCC = 3.3 V
A. VVM = VVCC
Figure 7-12. High-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-11. High-Side RDS(on) vs. Supply Voltage
300
210
200
190
180
170
160
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
280
260
TJ = 150°C
240
220
200
180
160
140
120
100
150
VVM = 0 V
140
130
120
110
100
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
VVM = 8 V
VVM = 11 V
-40 -20
0
20
40
60
80 100 120 140 160
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Junction Temperature (°C)
Supply Voltage, VVM = VVCC (V)
A. VVCC = 3.3 V
A. VVM = VVCC
Figure 7-14. Low-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-13. Low-Side RDS(on) vs. Supply Voltage
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50
0
-50
-100
-150
-200
-250
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0
2
4
6
8
10
12
VM Supply Voltage (V)
A. VVCC = 3.3 V
A. VVCC = 3.3 V
Figure 7-16. High-Z Leakage Current into OUTx
(IOUT) with OUTx connected to VM vs. Supply
Figure 7-15. High-Z Leakage Current into OUTx
(IOUT) with OUTx connected to GND vs. Supply
Voltage (VVM
)
Voltage (VVM
)
7.7 Typical Characteristics DRL Package
Figure 7-18. Sleep Current (IVMQ) vs. Junction
Temperature (TJ)
Figure 7-17. Sleep Current (IVMQ) vs. Supply
Voltage (VVM
)
Figure 7-20. Active Current (IVM) vs. Junction
Temperature (TJ)
Figure 7-19. Active Current (IVM) vs. Supply Voltage
(VVM
)
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240
220
200
180
160
140
120
190
180
170
160
150
140
130
120
110
100
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
VVM = 8 V
VVM = 11 V
100
1.5
-40 -20
0
20
40
60
80 100 120 140 160
2
2.5
3
3.5
4
4.5
5
5.5
Junction Temperature (°C)
VM Supply Voltage (V)
Figure 7-22. High-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-21. High-Side RDS(on) vs. Supply Voltage
Figure 7-24. Low-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-23. Low-Side RDS(on) vs. Supply Voltage
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8 Detailed Description
8.1 Overview
DRV8212 is an integrated H-bridge driver with multiple control interface options: PWM (IN1/IN2) interface (DRL
and DSG packages), PH/EN (DSG only), or half-bridge interface (DSG only). To reduce area and external
components on a printed circuit board, the device integrates a charge pump regulator and its capacitors. In the
DSG package, the separate motor (VM) and logic (VCC) supplies allow the motor supply voltage to drop to 0 V
without significant impact to RDS(on) and without triggering UVLO as long as the VCC supply is stable. A timed
auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically
putting the device into a low-power sleep mode when the inputs remain inactive for 1-2 ms.
The PWM interface is a standard 2-pin (IN1/IN2) motor drive interface. The PH/EN interface allows bi-directional
PWM control using only one PWM resource from the controller. PWM and PH/EN interfaces can drive loads like
brushed DC motors and bistable relays bidirectionally. Independent half-bridge mode allows for full control over
each half-bridge. The half-bridges can independently control two loads with each channel acting as a high-side
or low-side driver with half of the RDS(on) of full-bridge driving. Alternatively, half-bridge mode also allows the
inputs and outputs to be connected together, or "paralleled," to drive a single load as a high-side or low-side
driver with one-forth the RDS(on) of full-bridge driving.
The integrated protection features protect the device in the case of a system fault. These include undervoltage
lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD).
8.2 Functional Block Diagram
VM
VM
VM
VM
Power
Power
Charge
Pump
VM
Charge
Pump
Gate
Drive
OUT1
Gate
Drive
OUT1
VM
VCC
Logic
Logic
VVCC
BDC
BDC
VM
VM
MODE
IN1/EN
IN2/PH
Core Logic
Core Logic
IN1
IN2
Gate
Drive
Gate
Drive
OUT2
OUT2
Control
Inputs
Control
Inputs
Overcurrent
Undervoltage
Thermal
Overcurrent
Undervoltage
Thermal
GND
GND
Figure 8-2. PWM interface variant in DRL package
Figure 8-1. Multiple interface variant in DSG
package
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8.3 Feature Description
8.3.1 External Components
Table 8-1 lists the recommended external components for the device.
Table 8-1. Recommended external components
COMPONENT
CVM1
PIN 1
PIN 2
GND
GND
RECOMMENDED
0.1-µF, low ESR ceramic capacitor, VM-rated.
Section 10.1, VM-rated.
VM
CVM2
VM
0.1-µF, low ESR ceramic capacitor, VCC-rated.
Only needed for DSG package variant.
CVCC
VCC
GND
8.3.2 Control Modes
The DRV8212 provides three modes to support different control schemes with the PH/IN1 and EN/IN2 pins. The
MODE pin (DSG package variant only) selects the control interface mode by setting it either logic low, logic high,
or Hi-Z as shown in Table 8-2. The MODE pin does not latch its state, so it may be changed during operation.
The DRL package variant only supports the PWM interface (see Table 8-3).
Table 8-2. MODE pin functions for DSG variant
MODE STATE
MODE = Logic Low
MODE = Logic High
MODE = Hi-Z
CONTROL MODE
PWM
PH/EN
Half-Bridge
The inputs can accept DC or pulse-width modulated (PWM) voltage signals with duty cycles from 0% to 100%.
By default, the INx, PH/IN1, and EN/IN2 pins have internal pulldown resistors to ensure the outputs are Hi-Z if no
inputs are present (the only exception is half-bridge mode, where OUTx = L if INx is floating).
The following sections show the truth tables for each control mode. Additionally, the DRV8212 automatically
handles the dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.
Figure 8-3 describes the naming and configuration for the various H-bridge states described in the following
sections.
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
OUT1
OUT2
OUT1
OUT2
2
3
2
3
Forward
Reverse
Figure 8-3. H-bridge states
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8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
The PWM interface (IN1/IN2) controls the OUTx pins according to the logic table in Table 8-3. In the DSG
package, setting the MODE pin logic low selects PWM mode. The coast/Hi-Z state doubles as an automatic
sleep mode. After staying in the coast/Hi-Z state for tSLEEP, the device will automatically go into low-power sleep
mode (autosleep). The PWM mode is the only interface mode available in the DRL package.
Table 8-3. PWM control mode with automatic sleep
IN1
IN2
OUT1
OUT2
DESCRIPTION
Coast (H-bridge Hi-Z)/
0
0
Hi-Z
Hi-Z
low-power automatic sleep mode
Reverse (OUT2 → OUT1)
Forward (OUT1 → OUT2)
Brake (low-side slow decay)
0
1
1
1
0
1
L
H
L
H
L
L
8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
When the MODE pin is logic high on power up, the device selects "phase-enable" mode (PH/EN). PH/EN mode
allows for the H-bridge to be controlled with a speed and direction type of interface. Table 8-4 shows the truth
table for PH/EN mode. When the EN pin is low, the device enters brake mode. This allows the controller to use a
single PWM generator peripheral on the EN pin while a standard GPIO pin controls directions using the PH pin.
However, if the EN pin remains low for longer than tSLEEP, the device goes into low-power sleep mode and the
outputs are disabled.
Table 8-4. PH/EN control mode
EN
PH
OUT1
OUT2
DESCRIPTION
Brake (low-side slow decay) for tSLEEP, then
auto-sleep mode (H-bridge Hi-Z)
0
X
L → Hi-Z
L → Hi-Z
1
1
0
1
L
H
L
Reverse (OUT2 → OUT1)
Forward (OUT1 → OUT2)
H
8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
When the MODE pin is floating (Hi-Z), the DSG variant selects the half-bridge control mode. This mode allows
for each half-bridge to be directly controlled in order to support high-side slow decay (or brake), driving two
independent loads, or paralleling the outputs for higher current capability for a single load. Table 8-5 shows the
truth table for independent half-bridge mode.If the MODE pin is connected to a GPIO pin from a microcontroller,
the microcontroller can achieve the Hi-Z state by setting the GPIO pin as an input. When using half-bridge mode,
the device can go into sleep mode by bringing the MODE, IN1, and IN2 pins logic low. The GPIO controlling the
MODE pin will need to be reconfigured as an output set to logic low. Alternatively, the VCC pin can be supplied
from a GPIO and used to put the device to sleep in some cases. See Section 8.4.2 for more details.
Table 8-5. Half-bridge control mode
VCC
MODE
IN1
IN2
OUT1
OUT2
DESCRIPTION
0 V
X
X
X
Hi-Z
Hi-Z
Low-power sleep mode
H-bridge disable/low-
power automatic sleep
mode
1.65-5.5 V
0
0
0
Hi-Z
Hi-Z
1.65-5.5 V
1.65-5.5 V
1.65-5.5 V
1.65-5.5 V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
X
X
0
1
L
H
X
X
X
X
L
OUT1 low-side On
OUT1 high-side On
OUT2 low-side On
OUT2 high-side On
X
X
H
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8.3.3 Protection Circuits
The DRV8212 is fully protected against supply undervoltage, output overcurrent, and device overtemperature
events.
8.3.3.1 Supply Undervoltage Lockout (UVLO)
If at any time the supply voltage falls below the undervoltage lockout threshold voltage, all MOSFETs in the
H-bridge will be disabled. The charge pump and device logic are disabled in this condition. When powered by
split supplies (DSG package only), the UVLO triggers when the VCC pin voltage drops below VUVLO,VCC falling
threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DRL
package only), the UVLO triggers when the VM pin voltage drops below VUVLO,VM falling threshold. Normal
operation resumes when the supply voltage rises above the VUVLO rising threshold. Table 8-6 summarizes the
conditions when the device enters UVLO.
Table 8-6. UVLO response conditions
Package variant
VVM
VVCC
<1.65 V
>1.65 V
N/A
Device response
UVLO
0 V to VVM_MAX
0 V to VVM_MAX
<1.65 V
DSG
Normal operation
UVLO
DRL
1.65 V to VVM_MAX
N/A
Normal operation
8.3.3.2 OUTx Overcurrent Protection (OCP)
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short
circuit events. If the output current exceeds the overcurrent threshold, IOCP, for longer than the overcurrent
deglitch time, tOCP, all MOSFETs in the H-bridge will be disabled. After tRETRY, the MOSFETs are re-enabled
according to the state of the PH/IN1 and EN/IN2 pins. If the overcurrent condition is still present, the cycle
repeats; otherwise normal device operation resumes.
In half-bridge control mode, the OCP behavior is slightly modified. If an overcurrent event is detected, only
the corresponding half-bridge will be disabled. The other half-bridge will continue normal operation. This allows
for the device to manage independent fault events when driving independent loads. If an overcurrent event is
detected in both half-bridges, both half-bridges will be disabled. Both half-bridges share the same overcurrent
retry timer. If an overcurrent event occurs first in OUT1, that output will disable for the duration of tRETRY. If OUT2
experiences an overcurrent event after OUT1, but before tRETRY has expired, then both OUTx pins will remain
disabled for a full duration of tRETRY
.
8.3.3.3 Thermal Shutdown (TSD)
If the die temperature exceeds the overtemperature limit TTSD, all MOSFETs in the H-bridge will be disabled.
Normal operation will resume when the overtemperature condition is removed and the die temperature drops
below the TTSD threshold.
8.3.4 Pin Diagrams
8.3.4.1 Logic-Level Inputs
Figure 8-4 shows the input structure for the logic-level input pins IN1, IN2, PH/IN1, and EN/IN2.
100 kꢀ
Figure 8-4. Logic-level input
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8.3.4.2 Tri-Level Input
Figure 8-5 shows the input structure for the tri-level input pin, MODE.
VVCC
+
75 kꢀ
œ
+
130 kꢀ
œ
Figure 8-5. MODE tri-level input
8.4 Device Functional Modes
The DRV8212 has several different modes of operation depending on the system inputs and conditions.
8.4.1 Active Mode
In active mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive
inputs. The device leaves active mode when entering low-power sleep mode or fault mode. When waking from
autosleep, the INx pins (DRL package or DSG package when MODE = 0) or EN pin (DSG package when MODE
= 1) must be held high for the duration of tWAKE to enable the device. After the tWAKE time has elapsed, the
device is awake, and the INx pins or EN pin may receive a PWM signal.
When VVCC < VVM, the DRV8212 draws active current from the VM pin rather than the VCC pin. During this
operating condition, IVCC is typically less than 500 nA(see Figure 7-5 and Figure 7-7).
8.4.2 Low-Power Sleep Mode
The DRV8212 supports a low-power sleep mode to reduce current consumption from VM and VCC when the
driver is not active. There are two ways to enter low-power sleep mode: autosleep and using the VCC pin. In
autosleep mode, the device draws minimal current denoted by IVCCQ and IVMQ. Both DSG and DRL packages
support autosleep. In VCC sleep mode, the device draws minimal current denoted by IVMQ_UV and IVCCQ_UV
.
Only the DSG package can go into low-power mode using the VCC pin. Table 8-7 describes how to enter
low-power sleep mode.
Table 8-7. Sleep mode summary
Variant
Input pin state
OUT1
OUT2
Description
DRL
IN1 = IN2 = 0
Hi-Z
Hi-Z
Autosleep for PWM or half-bridge interface: Upon entering this
state, the outputs are disabled. The device remains in Active
Mode for tSLEEP, then goes into low-power mode.
MODE = 0, IN1 = IN2 = 0
MODE = 1, EN = 0
Hi-Z
Hi-Z
Autosleep for PH/EN interface: Upon entering this state, both
outputs go into brake mode by turning the low-side FETs on. The
device remains in this state for tSLEEP, then goes into low-power
mode. Once in low-power mode, the outputs are disabled.
L → Hi-Z
L → Hi-Z
DSG
VCC supply as sleep pin: The VCC pin can be supplied from
a GPIO pin and used to put the device to sleep. By bringing the
GPIO pin low, the device enters low-power mode by using UVLO.
To wake up the device, set the GPIO pin high (VCC > VUVLO),
then set EN = 1 if MODE = 1, or set/toggle either INx input to 1 if
MODE = Hi-Z or 1. See Section 9.2.2.2.3 for more information on
using the VCC pin for sleep.
VCC = 0 V
Hi-Z
Hi-Z
The device returns to active mode when the input pins move to a state other than the ones in Table 8-7. To wake
up the device from autosleep mode, the INx pins or EN pin (depending on MODE state and package variant)
must be asserted high for longer than tWAKE before receiving PWM input signals.
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To wake up the device from VCC sleep mode, the VCC pin voltage must be greater than VUVLO,VCC. Once the
VCC pin has a valid voltage, either or both INx pins must be asserted high for longer than tWAKE to fully wake up
the device. To protect the microcontroller GPIO pin from excess current due to the decoupling capacitor charging
current, a resistor may need to be added between the GPIO and the decoupling capacitor on the VCC pin. See
Section 9.2.2.2.3 for more information on designing this limiting resistor.
To ensure lowest supply current draw, TI recommends setting all input pins to logic low to eliminate current draw
through the pulldown resistors in sleep mode. If the MODE pin is set to Hi-Z or logic low, it will not draw current
in sleep mode. However, the MODE pin will draw some current in sleep mode when it is logic high.
8.4.3 Fault Mode
The DRV8212 enters a fault mode when a fault is encountered. This protects the device and the output load.
The device behavior in the fault mode is described in Section 8.3.3 and depends on the fault condition. The
device leaves the fault mode and re-enters the active mode once the recovery condition is met. Table 8-8
summarizes the fault conditions, response, and recovery.
Table 8-8. Fault condition summary
FAULT
CONDITION
H-BRIDGE
RECOVERY
Undervoltage Lockout
(UVLO), DSG
VCC < VUVLO,VCC falling
Disabled
VCC > VUVLO,VCC rising
Undervoltage Lockout
(UVLO), DRL
VM < VUVLO,VM falling
Disabled
VM > VUVLO,VM rising
Overcurrent (OCP)
IOUT > IOCP
TJ > TTSD
Disabled
Disabled
tRETRY
Thermal Shutdown (TSD)
TJ < TTSD – THYS
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8212 can be used in a variety of applications that require either a half-bridge or H-bridge power stage
configuration. Common application examples include brushed DC motors, solenoids, bistable latching relays,
and actuators. These devices can also drive many common passive loads such as LEDs, resistive elements,
relays, etc. This section highligts some application examples for the DRV8212.
9.2 Typical Application
9.2.1 Full-Bridge Driving
A typical application for the DRV8212 is to drive a brushed DC motor or single-coil latching relay bidriectionally
(in forward and reverse) using the outputs as a full-bridge, or H-bridge, configuration. Figure 9-1 and Figure 9-2
show examples for each package variant driving a motor with the PWM interface. Figure 9-3 shows an example
of driving a single-coil latching relay with the PWM interface. Figure 9-4 shows an example of driving a motor
with the PH/EN interface.
VM
VCC
VM
0.1 …F
VCC
Controller
CBulk
1
2
3
16
15
14
0.1 …F
PWM
IN1
VM
OUT1
OUT2
DRV82xxDRL
VCC
Controller
1
2
3
4
8
7
6
5
DRV821xDSG
VM
VCC
MODE
IN1
PWM
IN2
0.1 …F
OUT1
OUT2
GND
Thermal
Pad
GND
BDC
PWM
PWM
BDC
IN2
Figure 9-1. PWM interface motor-driving
application for DRL package
Figure 9-2. PWM interface motor-driving
application for DSG package
VM
VM
VCC
0.1 …F
VCC
VCC
CBulk
CBulk
Controller
0.1 …F
1
2
3
4
8
7
6
5
DRV821xDSG
VM
VCC
MODE
IN1
VCC
Controller
1
2
3
4
8
7
6
5
0.1 …F
DRV821xDSG
OUT1
OUT2
GND
VM
VCC
MODE
PH
Thermal
Pad
0.1 …F
PWM
PWM
OUT1
OUT2
GND
Single-
coil
relay
Thermal
Pad
BDC
IN2
PWM
PWM
EN
Figure 9-3. PWM interface single-coil latching relay
application
Figure 9-4. PH/EN interface motor-driving
application for DSG package
9.2.1.1 Design Requirements
Table 9-1 lists the required parameters for a typical usage case.
Table 9-1. System design requirements
DESIGN PARAMETER
Motor supply voltage
Logic supply voltage
REFERENCE
EXAMPLE VALUE
VM
11 V
VCC
3.3 V
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Table 9-1. System design requirements (continued)
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
300 mA
Target motor RMS current
Target relay current
Imotor
Irelay
50 mA
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Supply Voltage
The appropriate supply voltage depends on the ratings of the load (motor, solenoid, relay, etc.). In the case of a
brushed DC motor, the supply voltage will impact the desired RPM. A higher voltage spins a brushed dc motor
faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of
current change through the inductive windings of a motor, solenoid, or relay.
9.2.1.2.2 Control Interface
Section 8.3.2.1 describes the PWM control interface depending on selected package. TI recommends
connecting the the MODE pin directly to the GND net as shown in Figure 9-2. However, if other interface states
are required in the application, the MODE pin may be connected to a GPIO pin to select the other interface
options during operation. The autosleep feature allows for bidirectional control of the motor and low-power mode
using only two pins. This eliminates the need for another GPIO to control a sleep pin. Figure 9-5 and Figure 9-6
show waveform examples of driving a motor with the PWM interface.
Figure 9-7 and Figure 9-8 show waveform examples of driving a single coil relay with the PWM interface. The
relay can be driven between the forward/reverse states and the brake/coast states as shown in the figures.
Section 8.3.2.2 describes the PH/EN control interface. Connecting the MODE pin to the microcontroller supply
selects the PH/EN interface. PH/EN mode helps to reduce the number of microcontroller PWM generators
needed for motor driving by toggling only the EN pin. The PH pin controls the direction of motor driving with this
interface. The device will enter sleep mode if EN is held low for longer than tSLEEP
.
9.2.1.2.3 Low-Power Operation
Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting
all inputs as a logic low to minimize system power.
9.2.1.3 Application Curves
A.
Channel 1 = IN1
Channel 2 = IN2 Channel 3 = OUT1 A.
Channel 1 = IN1 Channel 2 = Motor Channel 3 = OUT1
Channel 4 = OUT2
Current
Channel 4 = OUT2
Figure 9-5. PWM driving for a motor with 50% duty
cycle, INx and OUTx voltages
Figure 9-6. PWM driving for a motor with 50% duty
cycle, signals and motor current
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A.
Channel 1 = IN1
Channel 4 = VOUT2 Channel 6 = Relay Channel 7 = Relay
Switch Coil Current
Channel 2 = IN2 Channel 3 = VOUT1 A.
Channel 1 = IN1
Channel 2 = IN2 Channel 3 = VOUT1
Channel 4 = VOUT2 Channel 6 = Relay Channel 7 = Relay
Switch Coil Current
Figure 9-7. PWM driving for a single-coil latching
relay with driving profile FORWARD → COAST →
REVERSE → COAST
Figure 9-8. PWM driving for a single-coil latching
relay with driving profile FORWARD → BRAKE →
REVERSE → BRAKE
9.2.2 Half-Bridge Driving
The DRV8212 can be configured to half-bridge mode by leaving the MODE pin floating. In this mode, the device
outputs can be used as low-side or high-side drivers. This allows the device to drive various loads such as one
or two motors unidirectionally (only in one direction), solenoids, valves, and relays. Figure 9-9 shows the device
used as a low-side driver on OUT1 and high-side driver on OUT2. Both loads may also be driven from the
high-side or from the low-side. By tying the INx pins together and OUTx pins together, as shown in Figure 9-10
and Figure 9-11, the device can drive a single load with half of the RDS(on). This can accommodate larger current
requirements. This configuration is called "parallel half-bridge mode."
In half-bridge mode, the other FETs and body diodes in the half-bridge will recirculate freewheeling current
during the off-time of the PWM duty cycle, so extra external diodes are not needed.
VM
VM
VMCU
0.1 …F
0.1 μF
VMCU
CBulk
CBulk
Controller
O
RLimit
1
2
3
4
8
7
DRV821xDSG
VM
VCC
MODE
IN1
Controller
O
VM
RLimit
1
2
3
4
8
7
0.1 …F
DRV821xDSG
VM
VCC
MODE
IN1
OUT1
OUT2
GND
X
Thermal
Pad
BDC
6
0.1 μF
OUT1
OUT2
GND
Valve
Pump
PWM
X
Thermal
Pad
6
5
PWM
PWM
IN2
5
IN2
Figure 9-10. Half-bridge mode used as a high-side
driver with outputs paralleled
Figure 9-9. Half-bridge mode used as a high-side
and low-side driver for two loads
VM
VMCU
0.1 …F
CBulk
Controller
O
RLimit
1
8
DRV821xDSG
VM
VCC
MODE
IN1
VM
2
3
4
7
0.1 …F
OUT1
OUT2
GND
X
Thermal
Pad
BDC
6
5
PWM
IN2
Figure 9-11. Half-bridge mode used as a low-side driver with outputs paralleled
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9.2.2.1 Design Requirements
Table 9-2 lists the required parameters for the use case shown in Figure 9-9.
Table 9-2. System design requirements
DESIGN PARAMETER
Load supply voltage
REFERENCE
VM
EXAMPLE VALUE
6 V
Logic supply voltage
Maximum valve current
Maximum pump current
VMCU
3.3 V
IOUT1
100 mA pulse for 100 ms
600 mA, RMS
IOUT2
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Supply Voltage
The appropriate supply voltage depends on the ratings of the load.
9.2.2.2.2 Control Interface
Section 8.3.2.3 describes the half-bridge control interface for the DSG package.
9.2.2.2.3 Low-Power Operation
Bringing VCC to 0 V puts the DRV8212 to sleep in half-bridge mode. Section 8.4.2 describes how to enter
low-power sleep mode in detail. When entering sleep mode, TI recommends setting all inputs as a logic low to
minimize system power. To wake up the DRV8212 in half-bridge mode, bring VCC high, then set IN1 or IN2
high for longer than tWAKE before returning low or sending a PWM signal. Figure 9-19 and Figure 9-20 show this
wakeup procedure.
Because of the decoupling capacitor on the VCC pin, TI recommends adding a resistor between the GPIO pin
of the controller and the VCC pin as shown in Figure 9-9, Figure 9-10, and Figure 9-11. The purpose of this
resistor is to protect the GPIO pin from large currents from the capacitor when switching the GPIO pin. However,
this resistor must be sized appropriately to allow the operating current, IVCC, to flow into the VCC pin. Table 9-3
shows the design considerations for the RLIMIT resistor. VOL is the GPIO voltage when logic low, VOH is the GPIO
voltage when logic high, and IOL is the maximum current that the GPIO can sink. The controller datasheet should
specify VOL, VOH and IOL for the GPIO pin.
Table 9-3. GPIO pin current limiting resistor design requirements
Design consideration
Equation
Example
Minimum resistance needed to protect GPIO
pin. Here, VCap is the voltage on the capacitor
when the GPIO pin switches from high to
low. To simplify calculation and assume a
worst-case condition, VCap is assumed to be
equivalent to the controller supply voltage,
VMCU. See Figure 9-12 for example circuit.
RLimit ≥ (VCap - VOL) / IOL
RLimit ≥ (3.3 V - 0.3 V) / 50 mA = 60 Ω
Keep the VCC pin voltage high enough so
device does not go into undervoltage lockout.
See Figure 9-13 for example circuit.
VOH - (IVCC × RLimit) = VVCC ≥ 1.65 V
3.0 V - (11 mA × 60 Ω) = 2.34 V ≥ 1.65 V
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VMCU = 3.3 V
VMCU = 3.3 V
IOL = 50 mA
IVCC = 11 mA
RLimit
Controller
Controller
DRV8212DSG
DRV8212DSG
8
8
VCC
O
VCC
O
RLimit
+
+
+
+
VOL = 0.3 V
0.1 μF
VOH = 3.0 V
VCap = 3.3 V
VCap = 2.34 V
0.1 μF
-
-
-
-
Figure 9-12. GPIO current when switching output
from logic high to logic low
Figure 9-13. GPIO current with logic high output
when VVCC > VVM
In cases where the specified GPIO current is too small, there are a few other options to put the device to sleep.
One option is to parallel multiple GPIO to supply the appropriate current. A second option is to set MODE =
IN1 = IN2 = 0 to put the device into the autosleep state. This will require the GPIO pin that controls MODE
to be configured as an input during operation and an output low during sleep. A third option is to place a
GPIO-controlled transistor between the supply and the VCC pin as shown in Figure 9-14.
VMCU = 3.3 V
Controller
DRV821xDSG
8
O
VCC
10 kꢀ
0.1 …F
Figure 9-14. GPIO with transistor
To minimize leakage current into the OUTx pins (especially in battery-powered applications), connect the load
from OUTx to GND. As mentioned earlier, connecting the load from OUTx to VM is also possible, but there
may be some small leakage current into OUTx when it is disabled. No leakage current is expected if loads are
connected in H-bridge configuration.
9.2.2.3 Application Curves
The figures below show waveform examples of high-side and low-side driving in half-bridge mode. Figure 9-15
and Figure 9-16 show example waveforms of driving a motor unidirectionally using high-side and low-side
driving. Figure 9-17 and Figure 9-18 show example waveforms of driving a solenoid using high-side and low-side
driving. Figure 9-19 and Figure 9-20 show examples of driving a motor using high-side and low-side driving
when the OUTx pins are paralleled together to create a single half bridge.
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A.
Channel 1 = IN2 Channel 2 = VOUT2 Channel 4 = Motor A.
Channel 1 = IN2 Channel 2 = VOUT2 Channel 4 = Motor
Current
Current
Figure 9-15. Driving a motor in half-bridge mode
with 50% duty cycle using the high-side FET
Figure 9-16. Driving a motor in half-bridge mode
with 50% duty cycle using the low-side FET
A.
Channel 1 = IN1 Channel 2 = VOUT1
Channel 4 = A.
Solenoid Current
Channel 1 = IN1 Channel 2 = VOUT1
Channel 4 =
Solenoid Current
Figure 9-17. Driving a solenoid in half-bridge mode Figure 9-18. Driving a solenoid in half-bridge mode
using the high-side FET
using the low-side FET
A.
Channel 1 = IN1, Channel 2 = VVCC Channel 3 = VOUT A.
Channel 1 = IN1, Channel 5 = VVCC Channel 6 = VOUT
IN2 (paralleled)
Channel 8 = Motor
Current
(OUT1/2 paralleled)
IN2 (paralleled)
Channel 8 = Motor
Current
(OUT1/2 paralleled)
Figure 9-19. Driving a motor in parallel half-bridge Figure 9-20. Driving a motor in parallel half-bridge
mode using the high-side FETs mode using the low-side FETs
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9.2.3 Dual-Coil Relay Driving
The PWM interface may also be used to drive a dual-coil latching relay. The figures in this section show example
schematics.
VM
VCC
VM
VMCU
Controller
CBulk
Controller
1
2
3
16
15
14
RLimit
0.1 μF
1
2
3
4
8
7
6
5
0.1 …F
DRV821xDSG
PWM
IN1
VM
OUT1
OUT2
O
DRV821xDRL
VM
VCC
MODE
IN1
0.1 μF
OUT1
OUT2
GND
PWM
IN2
Thermal
Pad
PWM
PWM
GND
VM
VM
Dual-
coil
relay
Dual-
coil
relay
IN2
Figure 9-22. Dual-coil relay driving, DRL package
Figure 9-21. Dual-coil relay driving, DSG package
9.2.3.1 Design Requirements
Table 9-4 provides example requirements for a dual-coil relay application.
Table 9-4. System design requirements
DESIGN PARAMETER
Motor supply voltage
Logic supply voltage
Relay current
REFERENCE
EXAMPLE VALUE
VM
6 V
3.3 V
VCC
IOUT1, IOUT2
500 mA pulse for 100 ms
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Supply Voltage
The appropriate supply voltage depends on the ratings of the load.
9.2.3.2.2 Control Interface
The PWM interface can be used to drive dual-coil relays. Section 8.3.2.1 describes the PWM control interface.
Figure 9-23 and Figure 9-24 show a schematic and timing diagram for driving a dual-coil relay with the PWM
interface.
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VM
VM
Sleep
mode
Sleep
mode
Sleep
mode
Drive Coil1
Drive Coil2
IN1
IN2
Coil1
IOUT1
Coil2
VM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VOUT1
VOUT1
VOUT2
IOUT2
GND
VM
Dual-coil
relay
VOUT2
GND
IOUT1
IOUT2
Figure 9-23. Schematic of dual-coil relay driven by
the OUTx H-bridge
Figure 9-24. Timing diagram for driving a dual-coil
relay with PWM interface
Table 9-5 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and
output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will
go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true
when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so
extra external diodes are not needed. Figure 9-25 shows oscilloscope traces for this application.
Table 9-5. PWM control table for dual-coil relay driving
IN1
0
IN2
OUT1
Hi-Z
L
OUT2
Hi-Z
H
DESCRIPTION
Outputs disabled (H-Bridge Hi-Z)
Drive Coil1
0
0
1
1
0
H
L
Drive Coil2
Drive Coil1 and Coil2 (invalid state for a
dual-coil latching relay)
1
1
L
L
9.2.3.2.3 Low-Power Operation
Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting
all inputs as a logic low to minimize system power.
To minimize leakage current into the OUTx pins (especially in battery-powered applications), connect the load
from OUTx to GND. As shown in the previous section, connecting the load from OUTx to VM is also possible,
but there may be some small leakage current into OUTx when it is disabled.
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9.2.3.3 Application Curves
A.
Channel 1 = IN1
Channel 4 = VOUT2
Channel 2 = IN2
Channel 3 = VOUT1
Channel 6 = Relay Switch
Channel 7 = Relay Coil1 Current
Channel 8 = Relay Coil2 Current
Figure 9-25. PWM driving for dual-coil relay
9.2.4 Current Sense
A small shunt resistor on the GND pin can provide current sense information back to the microcontroller ADC.
The microcontroller can use this information to detect motor load conditions, such as stall. Figure 9-26 shows an
example schematic using the DRL package. If better current sensing dynamic range is needed, an amplifier can
be added as shown in Figure 9-27.
The DSG thermal pad may be connected to the board ground net or the GND pin/sense signal net.
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VCC
VM
Controller
1
2
3
16
0.1 …F
PWM
IN1
VM
OUT1
OUT2
DRV821xDRL
15
14
PWM
ADC
IN2
RFILTER
CFILTER
GND
BDC
RSENSE
Figure 9-26. Shunt resistor on GND pin of the DRL package variant
VM
VCC
0.1 …F
VCC
CBulk
Controller
0.1 …F
1
2
3
4
8
7
6
5
DRV821x
VM
VCC
MODE
IN1
OUT1
OUT2
GND
Thermal
Pad
BDC
PWM
IN2
PWM
TLV905I
+
ADC
œ
RSENSE
CFILTER
R2
R1
Figure 9-27. Current sense amplifier examplein the DSG package variant
9.2.4.1 Design Requirements
Table 9-6 provides example requirements for a current sensing application.
Table 9-6. System design requirements
DESIGN PARAMETER
Motor supply voltage
REFERENCE
VM
EXAMPLE VALUE
6 V
3.3 V
Logic supply voltage
VCC
Maximum voltage across RSENSE
Motor RMS current
VSENSE
150 mV
500 mA
1 A
IOUT1, IOUT2
IOUT1,stall, IOUT2,stall
Motor stall current
9.2.4.2 Detailed Design Procedure
9.2.4.2.1 Shunt Resistor Sizing
The Absolute Maximum Ratings for the INx pins set the maximum voltage across the shunt resistor. If the signal
on the INx pin is low, referenced at the board ground, then the INx pins are at a negative voltage with respect
to the GND pin voltage. This sets the maximum sense voltage/GND pin voltage to 0.5 V. Figure 9-28 shows the
relative pin voltages.
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IN1
IN2
VIN2 = 0 V
+
VGND,pin = -0.5 V
-
GND
+
VSENSE = 0.5 V
-
RSENSE
VGND,board = 0 V
Figure 9-28. Pin voltages with respect to board ground using current sense resistor
This example uses 150 mV for the maximum VSENSE, which is less than 0.5 V and provides some margin for
safety or error. The maximum current through the motor will be the stall current, which is 1 A for this example.
With this information, the sense resistance RSENSE can be calculated from the equation below.
RSENSE = VSENSE / ISTALL = 0.15 / 1 = 0.15 Ω
(1)
Because the device GND pin voltage will vary with current through the sense resistor, the designers must also
ensure that the logic pins meet VIL and VIH parameters,the MODE pin meets the VTIL, VTIZ, and VTIH parameters,
and the supply remains above VUVLO for proper operation.
9.2.4.2.2 RC Filter
The RC filter shown in Figure 9-26 is used to filter noise and transients from the sense signal. TI recommends
RFILTER = 1 kΩ and CFILTER = 100 nF. Different values can be chosen depending on the specific system
conditions.
9.3 Current Capability and Thermal Performance
The output current and power dissipation capabilities of the driver depends heavily on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
9.3.1 Power Dissipation and Output Current Capability
Total power dissipation for the device consists of three main components: quiescent supply current dissipation
(PVM and PVCC), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction)
losses (PRDS). While other factors may contribute additional power losses, they are typically insignificant
compared to the three main items.
PTOT = PVM + PVCC + PSW + PRDS
(2)
PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current
specification. PVCC can be calculated from the nominal logic supply voltage (VVCC) and the IVCC active mode
current specification. When VVCC < VVM, the DRV8212 draws active current from the VM pin rather than the VCC
pin. During this operating condition, IVCC is typically less than 500 nA.
PVM = VVM x IVM
(3)
(4)
(5)
(6)
PVM = 30 mW = 5 V x 6 mA
PVCC = VVCC x IVCC
PVCC = 0.693 mW = 3.3 V x 0.21 mA
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PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IRMS), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL
(7)
(8)
PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM
PSW_FALL = 0.5 x VM x IRMS x tFALL x fPWM
PSW_RISE = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz
PSW_FALL = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz
PSW = 7.5 mW = 3.75 mW + 3.75 mW
(9)
(10)
(11)
(12)
PRDS can be calculated from the device RDS(on) and average output current (IRMS).
PRDS = IRMS 2 x (RDS(ON)_HS + RDS(ON)_LS
)
(13)
RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85
°C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows
this derating factor. Alternatively, the Section 7.6 section shows curves that plot how RDS(on) changes with
temperature.
PRDS = 105 mW = (0.5 A)2 x (140 mΩ x 1.5 + 140 mΩ x 1.5)
(14)
Based on the example calculations above, the expressions below calculate the total expected power dissipation
for the device.
PTOT = PVM + PVCC + PSW + PRDS
(15)
(16)
PTOT = 143 mW = 30 mW + 0.693 mW + 7.5 mW + 105 mW
The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking
around the device. Section 9.3.2 describes this dependence in greater detail.
TJ = (PTOT x RθJA) + TA
(17)
(18)
TJ = 96°C = (0.458 W x 77.9 °C/W) + 85°C
The device junction temperature should remain below its absolute maximum rating for all system operating
conditions. The calculations in this section provide reasonable estimates for junction temperature. However,
other methods based on temperature measurements taken during system operation are more realistic and
reliable. Additional information on motor driver current ratings and power dissipation can be found in Section
9.3.2 and Section 12.1.1.
9.3.2 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria:
WSON (DSG package)
•
2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only
present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
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– Top layer: DRV8212 WSON package footprint and copper plane heatsink. Top layer copper area is varied
in simulation.
– Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8212. Bottom
layer copper area varies with top copper area.
•
4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner
planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm
diameter, 0.025 mm Cu plating).
– Top layer: DRV8212 WSON package footprint and copper plane heatsink. Top layer copper area is varied
in simulation.
– Mid layer 1: GND plane thermally connected to DRV8212 thermal pad through vias. The area of the
ground plane is 74.2 mm x 74.2 mm.
– Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
– Bottom layer: signal layer with small copper pad underneath DRV8212 and thermally connected through
via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the
package (2 mm x 2 mm). Bottom pad size remains constant as top copper plane is varied.
Figure 9-29 shows an example of the simulated board for the HTSSOP package. Table 9-7 shows the
dimensions of the board that were varied for each simulation.
A
A
Figure 9-29. WSON PCB model top layer
Table 9-7. Dimension A for 16-pin PWP package
Cu area (mm2)
Dimension A (mm)
2
4
15.11
20.98
29.27
40.99
8
16
SOT (DRL package)
•
2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only
present under the package footprint (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
– Top layer: DRV8212 SOT package footprint and copper plane heatsink. Top layer copper area is varied in
simulation.
– Bottom layer: ground plane thermally connected through vias under the DRV8212DRL package footprint.
Bottom layer copper area varies with top copper area.
•
4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner
planes are kept at 1-oz. Thermal vias are only present under the DRV8212DRL package footprint (2 vias,
1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
– Top layer: DRV8212 SOT package footprint and copper plane heatsink. Top layer copper area is varied in
simulation.
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– Mid layer 1: GND plane thermally connected under DRV8212DRL package footprint through vias. The
area of the ground plane is 74.2 mm x 74.2 mm.
– Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
– Bottom layer: signal layer with small copper pad underneath DRV8212DRL and thermally connected
through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as
the package (1.2 mm x 1.6 mm). Bottom pad size remains constant as top copper plane is varied.
Figure 9-30 shows an example of the simulated board for the HTSSOP package. Table 9-8 shows the
dimensions of the board that were varied for each simulation.
A
IN1
IN2
1
2
3
6
5
4
OUT1
VM
Via
Via
GND
OUT2
A
Figure 9-30. SOT PCB model top layer
Table 9-8. Dimension A for 16-pin PWP package
Cu area (mm2)
Dimension A (mm)
2
4
15.11
20.98
29.27
40.99
8
16
9.3.2.1 Steady-State Thermal Performance
"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long
period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter)
change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more
layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the
PCB layout.
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38
36
34
32
30
28
4 layer, 1 oz
4 layer, 2 oz
2 layer, 1 oz
2 layer, 2 oz
2
4
6
8
10
12
14
16
Top layer copper area (cm2)
Figure 9-31. WSON, PCB junction-to-ambient
thermal resistance vs copper area
Figure 9-32. WSON, junction-to-board
characterization parameter vs copper area
Figure 9-34. SOT, junction-to-board
characterization parameter vs copper area
Figure 9-33. SOT, PCB junction-to-ambient thermal
resistance vs copper area
9.3.2.2 Transient Thermal Performance
The motor driver may experience different transient driving conditions that cause large currents to flow for a
short duration of time. These may include
•
•
Motor start-up when the rotor is initially stationary.
Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent
protection triggers.
•
Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance in
addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the
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junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances
for 1-oz and 2-oz copper layouts for the WSON and SOT packages. These graphs indicate better thermal
performance with short current pulses. For short periods of drive time, the device die size and package
dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on
thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and
copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state
performance.
Figure 9-35. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts
Figure 9-36. WSON package junction-to-ambient thermal impedance for 2-oz copper layouts
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Figure 9-37. SOT package junction-to-ambient thermal impedance for 1-oz copper layouts
200
100
80
70
60
50
40
30
2 cm2, 2-layer
4 cm2, 2-layer
8 cm2, 2-layer
16 cm2, 2-layer
2 cm2, 4-layer
4 cm2, 4-layer
8 cm2, 4-layer
16 cm2, 4-layer
20
10
0.01
0.020.03 0.05
0.1
0.2 0.3 0.5 0.7
1
2
3
4 5 6 78 10
20 30 4050 70 100
200 300 500
1000
Pulse duration (s)
Figure 9-38. SOT package junction-to-ambient thermal impedance for 2-oz copper layouts
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10 Power Supply Recommendations
10.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local bulk capacitance needed depends on a variety of factors, including:
•
•
•
•
•
The highest current required by the motor or load
The capacitance of the power supply and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple of the system
The motor braking method (if applicable)
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended minimum value, but system level testing is required to
determine the appropriately sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VBB
+
Motor
Driver
+
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. System Supply Parasitics Example
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: DRV8212
DRV8212
www.ti.com
SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
11 Layout
11.1 Layout Guidelines
Since the DRV8212 device has integrated power MOSFETs capable of driving high current, careful attention
should be paid to the layout design and external component placement. Some design and layout guidelines
are provided below. For more information on layout recommendations, please see the application note Best
Practices for Board Layout of Motor Drivers.
•
•
•
•
Low ESR ceramic capacitors should be utilized for the VM-to-GND and VCC-to-GND bypass capacitors. X5R
and X7R types are recommended.
The VM and VCC power supply capacitors should be placed as close to the device as possible to minimize
the loop inductance.
The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as
close as possible to the device to minimize the loop inductance.
VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground.
Thick metal routing should be utilized for these traces as is feasible.
•
•
GND should connect directly on the PCB ground plane.
The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
•
11.2 Layout Example
CBULK
VM
MOT+
MOT-
IN1
IN2
1
2
3
6
5
4
OUT1
VM
GND
OUT2
0.1 …F
Figure 11-1. Simplified Layout Example of DRL Package without Vias
Copyright © 2021 Texas Instruments Incorporated
36
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SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
MOT+
IN1
IN2
1
2
3
6
5
4
OUT1
VM
Vias to bo om
layer trace
GND
OUT2
MOT-
VM
0.1 μF
CBULK
Figure 11-2. Simplified Layout Example of DRL Package with Larger Copper Area for Better Thermal
Dissipation
CBULK
0.1 …F
0.1 …F
VM
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
MODE
IN1
VCC
MOT+
MOT-
Thermal
Pad
IN2
Figure 11-3. Simplified Layout Example for DSG package
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: DRV8212
DRV8212
www.ti.com
SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, Calculating Motor Driver Power Dissipation application report
Texas Instruments, PowerPAD™ Made Easy application report application report
Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, Understanding Motor Driver Current Ratings application report
Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
38
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SLVSFY9B – JUNE 2021 – REVISED AUGUST 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DRV8212
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8212DRLR
DRV8212DSGR
ACTIVE
ACTIVE
SOT-5X3
WSON
DRL
DSG
6
8
4000 RoHS & Green
3000 RoHS & Green
Call TI
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
8212
212
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/B 12/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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