DRV8231_V01 [TI]
DRV8231 3.7-A Brushed DC Motor Driver with Integrated Current Regulation;
| 型号： | DRV8231_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8231 3.7-A Brushed DC Motor Driver with Integrated Current Regulation |
| 文件： | 总39页 (文件大小：3536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8231
SLVSFZ7 – NOVEMBER 2021
DRV8231 3.7-A Brushed DC Motor Driver with Integrated Current Regulation
1 Features
3 Description
•
•
•
N-channel H-bridge brushed DC motor driver
4.5-V to 33-V operating supply voltage range
Pin-to-pin, RDS(on), voltage, and current sense/
regulation variants (external shunt resistor and
integrated current mirror)
The DRV8231 device is an integrated motor driver
with N-channel H-bridge, charge pump, current
regulation, and protection circuitry. The charge
pump improves efficiency by supporting N-channel
MOSFET half bridges and 100% duty cycle driving.
– DRV8870: 6.5-V to 45-V, 565-mΩ, shunt
– DRV8251: 4.5-V to 48-V, 450-mΩ, shunt
– DRV8251A: 4.5-V to 48-V, 450-mΩ, mirror
– DRV8231: 4.5-V to 33-V, 600-mΩ, shunt
– DRV8231A: 4.5-V to 33-V, 600-mΩ, mirror
High output current capability: 3.7-A Peak
PWM control interface
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Integrated current regulation
Low-power sleep mode
– <1-µA at VVM = 24-V, TJ = 25°C
Small package and footprint
– 8-Pin WSON with PowerPAD™, 2.0 × 2.0 mm
– 8-Pin HSOP with PowerPAD™, 4.9 × 6.0 mm
Integrated protection features
– VM undervoltage lockout (UVLO)
– Auto-retry overcurrent protection (OCP)
– Thermal shutdown (TSD)
The DRV8231 implements a current regulation feature
by comparing the analog input VREF and the voltage
across a current-sense shunt resistor on the ISEN
pin. The ability to limit current can significantly
reduce large currents during motor startup and stall
conditions.
•
•
•
•
•
A low-power sleep mode achieves ultra-low quiescent
current draw by shutting down most of the internal
circuitry. Internal protection features include supply
undervoltage lockout, output overcurrent, and device
overtemperature.
•
•
The DRV8231 is part of a family of devices which
come in pin-to-pin, scalable RDS(on) and supply
voltage options to support various loads and supply
rails with minimal design changes. See Section 5 for
information on the devices in this family. View the full
portfolio of brushed motor drivers on ti.com.
Device Information (1)
2 Applications
PART NUMBER
PACKAGE
HSOP (8)
WSON (8)
BODY SIZE (NOM)
4.90 mm × 6.00 mm
2.00 mm × 2.00 mm
•
•
•
•
•
•
•
•
•
•
•
Printers
Vacuum robot
Washer and dryer
Coffee machine
POS printer
Electricity meter
ATMs (Automated Teller Machines)
Ventilators
Surgical equipment
Electronic hospital bed and bed control
Fitness machine
DRV8231
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4.5 to 33 V
DRV8231
IN1
H-Bridge
Motor Driver
IN2
Fault
Protec on
VREF
Current
Regula on
RSENSE
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8231
SLVSFZ7 – NOVEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
7.7 Timing Diagrams.........................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 External Components................................................. 9
8.4 Feature Description...................................................10
8.5 Device Functional Modes..........................................14
8.6 Pin Diagrams............................................................ 15
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
9.3 Current Capability and Thermal Performance.......... 24
10 Power Supply Recommendations..............................30
10.1 Bulk Capacitance....................................................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................33
12.1 Documentation Support.......................................... 33
12.2 Receiving Notification of Documentation Updates..33
12.3 Community Resources............................................33
12.4 Trademarks.............................................................33
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2021
*
Initial Release
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5 Device Comparison
Table 5-1. Device Comparison Table
Device
name
Supply
voltage (V)
RDS(on)
(mΩ)
Current
regulation
Current-sense
feedback
Overcurrent
protection response
Pin-to-pin
devices
Package
DRV8870
DRV8251
6.5 to 45
4.5 to 48
565
450
Automatic Retry
Latched Disable
HSOP (4.9x6)
HSOP (4.9x6)
DRV8870,
DRV8251,
DRV8231
External Shunt
Resistor
External
Amplifier
HSOP (4.9x6)
WSON (2x2)
DRV8231
DRV8251A
DRV8231A
4.5 to 33
4.5 to 48
4.5 to 33
600
450
600
Automatic Retry
Automatic Retry
Automatic Retry
HSOP (4.9x6)
DRV8251A,
DRV8231A
Internal current mirror (IPROPI)
HSOP (4.9x6)
WSON (2x2)
6 Pin Configuration and Functions
GND
IN2
1
2
3
4
8
7
6
5
OUT2
ISEN
OUT1
VM
GND
IN2
1
2
3
4
8
7
OUT2
ISEN
OUT1
VM
Thermal
Pad
Thermal
Pad
IN1
6
5
IN1
VREF
VREF
Figure 6-1. DDA Package 8-Pin HSOP Top View
Figure 6-2. DSG Package 8-Pin HSOP Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
IN1
NO.
1
PWR
Logic ground. Connect to board ground
3
I
I
Logic inputs. Controls the H-bridge output. Has internal pulldowns. See Table 8-2.
Logic inputs. Controls the H-bridge output. Has internal pulldowns. See Table 8-2.
IN2
2
High-current ground path. If using current regulation, connect ISEN to a resistor (low-value,
high-power-rating) to ground. If not using current regulation, connect ISEN directly to ground.
ISEN
7
PWR
OUT1
OUT2
6
8
O
O
H-bridge output. Connect directly to the motor or other inductive load.
H-bridge output. Connect directly to the motor or other inductive load.
4.5-V to 48-V power supply. Connect a 0.1-µF bypass capacitor to ground, as well as
sufficient bulk capacitance, rated for the VM voltage.
VM
5
4
PWR
Analog input. Apply a voltage between 0 to 5 V. For information on current regulation, see
the Section 8.4.2 section.
VREF
PAD
I
Thermal pad. Connect to board ground. For good thermal dissipation, use large ground
planes on multiple layers, and multiple nearby vias connecting those planes.
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
0
MAX UNIT
Power supply pin voltage
Power supply transient voltage ramp
Logic pin voltage
VM
35
V
V/µs
V
VM
2
INx
-0.3
-0.3
-0.7
-0.5
7
Reference input pin voltage
Output pin voltage
VREF
OUTx
ISEN
6
VM + 0.7
1
V
V
Current sense input pin voltage
V
Internally
Limited
Internally
Limited
Output current
OUTx
A
Junction temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
Junction temperature, TA
–40
–40
–65
125
150
150
°C
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±
2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500
V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
4.5
0
NOM
MAX UNIT
VVM
Power supply voltage
Reference voltage
VM
33
5
V
V
VVREF
VIN
VREF
INx
Logic input voltage
0
5.5
200
3.7
150
V
fPWM
PWM frequency
INx
0
kHz
A
(1)
IOUT
TJ
Peak output current
Operating junction temperature
OUTx
0
–40
°C
(1) Power dissipation and thermal limits must be observed
7.4 Thermal Information
DRV8231
DRV8231
THERMAL METRIC(1)
DDA (HSOP)
8 PINS
42.8
DSG (WSON)
8 PINS
66.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
57.6
77.8
RθJB
ΨJT
Junction-to-board thermal resistance
16.8
32.8
Junction-to-top characterization parameter
5.4
2.2
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DRV8231
DDA (HSOP)
8 PINS
DRV8231
THERMAL METRIC(1)
DSG (WSON)
8 PINS
32.7
UNIT
ΨJB
Junction-to-board characterization parameter
16.8
°C/W
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
6.2
12.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
4.5 V ≤ VVM ≤ 33 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 25 °C and VVM = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY (VM)
IVMQ
IVM
tWAKE
tSLEEP
VM sleep mode current
VM active mode current
Turnon time
VVM = 24 V, IN1 = IN2 = 0, TJ = 25°C
VVM = 24 V, IN1 = IN2 = 1
1
4
µA
mA
µs
3
Control signal to active mode
Control signal to sleep mode
250
1.5
Turnoff time
0.8
ms
LOGIC-LEVEL INPUTS (INx)
VIL
Input logic low voltage
0.5
V
V
VIH
VHYS
IIL
Input logic high voltage
Input hysteresis
1.5
-1
200
mV
µA
µA
kΩ
Input logic low current
Input logic high current
Input pulldown resistance
VIN = 0 V
VIN = 3.3 V
To GND
1
IIH
33
100
RPD
100
DRIVER OUTPUTS (OUTx)
RDS(on)_HS
RDS(on)_LS
VSD
High-side MOSFET on resistance
VVM = 24 V, I = 1 A, fPWM = 25 kHz
VVM = 24 V, I = 1 A, fPWM = 25 kHz
IOUT = 1 A
300
300
0.8
mΩ
mΩ
V
Low-side MOSFET on resistance
Body diode forward voltage
Output rise time
tRISE
VVM = 24 V, OUTx rising from 10% to 90%
VVM = 24 V, OUTx falling from 90% to 10%
INx to OUTx
220
220
0.7
ns
ns
µs
ns
tFALL
Output fall time
tPD
Input to output propagation delay
Output dead time
1
tDEAD
200
SHUNT CURRENT SENSE AND REGULATION (ISEN, VREF)
AV
ISEN gain
VREF = 2.5 V
9.6
10
25
2
10.4
V/V
µs
tOFF
tBLANK
Current regulation off time
Current regulation blanking time
µs
PROTECTION CIRCUITS
Supply rising
4.15
4.05
4.3
4.2
100
10
4.45
4.35
V
V
VUVLO
Supply undervoltage lockout (UVLO)
Supply falling
VUVLO_HYS Supply UVLO hysteresis
Rising to falling threshold
mV
µs
A
tUVLO
IOCP
Supply undervoltage deglitch time
Overcurrent protection trip point
3.7
Overcurrent protection trip point on
ISEN pin
VOCP_ISEN
0.7
V
tOCP
Overcurrent protection deglitch time
Overcurrent protection retry time
Thermal shutdown temperature
Thermal shutdown hysteresis
1.5
3
µs
ms
°C
°C
tRETRY
TTSD
THYS
150
175
40
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7.6 Typical Characteristics
0.75
0.7
0.75
0.6
0.45
0.3
0.15
0
0.65
0.6
0.55
0.5
VVM = 4.5 V
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0.45
0.4
VVM = 6.5 V
VVM = 12 V
VVM = 24 V
VVM = 33 V
0.35
-40 -20
0
20
40
60
80 100 120 140 160
3
6
9
12
15
18
21
24
27
30
33
Junction Temperature (°C)
VM Supply Voltage (V)
Figure 7-2. Sleep Current (IVMQ) vs. Junction
Temperature (TJ)
Figure 7-1. Sleep Current (IVMQ) vs. Supply Voltage
(VVM
)
2.2
2.15
2.1
2.3
2.2
2.1
2
2.05
2
1.9
1.95
1.9
1.8
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 4.5 V
VVM = 6.5 V
VVM = 12 V
VVM = 24 V
VVM = 33 V
1.7
1.85
1.8
1.6
1.5
3
6
9
12
15
18
21
24
27
30
33
-40 -20
0
20
40
60
80 100 120 140 160
VM Supply Voltage (V)
Junction Temperature (°C)
Figure 7-3. Active Current (IVM) vs. Supply Voltage
(VVM
Figure 7-4. Active Current (IVM) vs. Junction
Temperature (TJ)
)
600
560
520
480
440
400
360
320
280
240
200
440
420
400
380
360
340
320
300
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 4.5 V
VVM = 6.5 V
VVM = 12 V
VVM = 24 V
VVM = 33 V
280
260
240
220
-40 -20
0
20
40
60
80 100 120 140 160
3
6
9
12
15
18
21
24
27
30
33
Junction Temperature (°C)
VM Supply Voltage (V)
Figure 7-6. High-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-5. High-Side RDS(on) vs. VM Supply Voltage
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600
560
520
480
440
400
360
320
280
240
440
420
400
380
360
340
320
300
280
260
240
220
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 4.5 V
VVM = 6.5 V
VVM = 12 V
VVM = 24 V
VVM = 33 V
200
3
-40 -20
0
20
40
60
80 100 120 140 160
6
9
12
15
18
21
24
27
30
33
Junction Temperature (°C)
VM Supply Voltage (V)
Figure 7-8. Low-Side RDS(on) vs. Junction
Temperature (TJ)
Figure 7-7. Low-Side RDS(on) vs. VM Supply Voltage
10
9.75
9.5
9.25
9
8.75
8.5
8.25
8
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
7.75
7.5
7.25
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VREF Pin Voltage (V)
VVM = 24 V
Figure 7-9. Current Regulation Gain (AV) vs. Reference Voltage (VREF)
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7.7 Timing Diagrams
IN1 (V)
tPD
IN2 (V)
tPD
tPD
OUT1 (V)
Z
Z
Z
tPD
Z
OUT2 (V)
90%
90%
OUTx (V)
10%
10%
tRISE
tFALL
Figure 7-10. Input-to-Output Timing
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8 Detailed Description
8.1 Overview
The DRV8231 is an 8-pin device for driving brushed DC motors from a 4.5-V to 33-V supply rail. Two logic inputs
control the H-bridge driver, which consists of four N-channel MOSFETs that have a typical RDS(on) of 600 mΩ
(including one high-side and one low-side FET). A single power input, VM, serves as both device power and the
motor winding bias voltage. The integrated charge pump of the device boosts VM internally and fully enhances
the high-side FETs. Motor speed can be controlled with pulse-width modulation at frequencies between 0 to 200
kHz. The device enters a low-power sleep mode by bringing both inputs low.
The DRV8231 also integrates current regulation using an external shunt resistor on the ISEN pin. This allows the
device to limit the output current with a fixed off-time PWM chopping scheme to limit inrush and stall currents.
The current regulation level can be configured during motor operation through the VREF pin to limit the load
current accordingly to the system demands.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD).
8.2 Functional Block Diagram
VCP
VM
Power
VM
VM VCP
bulk
0.1µF
OUT2
Charge
Pump
Gate
Drive
OCP
Logic
GND
Core Logic
BDC
VCP
VM
IN2
IN1
Overcurrent
Undervoltage
Thermal
OUT1
Gate
Drive
Control
Inputs
OCP
ISEN
x
+
-
10
RSENSE
VREF
8.3 External Components
Table 8-1 lists the recommended external components for the device.
Table 8-1. Recommended external components
COMPONENT
PIN 1
PIN 2
GND
GND
RECOMMENDED
CVM1
VM
0.1-µF, low ESR ceramic capacitor, VM-rated.
Section 10.1, VM-rated.
CVM2
VM
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8.4 Feature Description
8.4.1 Bridge Control
The DRV8231 output consists of four N-channel MOSFETs that are designed to drive high current. These
outputs are controlled by the two logic inputs IN1 and IN2 as listed in Table 8-2.
Table 8-2. H-Bridge Control
IN1
0
IN2
0
OUT1
OUT2
DESCRIPTION
Coast; H-bridge disabled to High-Z (sleep entered after 1 ms)
Reverse (Current OUT2 → OUT1)
High-Z
High-Z
0
1
L
H
L
H
L
L
1
0
Forward (Current OUT1 → OUT2)
1
1
Brake; low-side slow decay
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM, switching between driving and braking typically works best. For
example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period,
and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current
decay is also available. Figure 8-1 shows how the motor current flows through the H-bridge. The input pins can
be powered before VM is applied.
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
OUT1
OUT2
OUT1
OUT2
2
3
2
3
FORWARD
REVERSE
Figure 8-1. H-Bridge Current Paths
When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically
inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the
output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the
pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above
VM. This diode is the body diode of the high-side or low-side FET.
The propagation delay time (tPD) is measured as the time between an input edge to output change. This time
accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents
noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn
on or turn off times (tRISE and tFALL).
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Figure 8-2 below shows the timing of the inputs and outputs of the motor driver.
IN1 (V)
IN2 (V)
OUT1 (V)
tPD
tRISE
tDEAD
tPD
tFALL
tDEAD
OUT2 (V)
tPD
tFALL
tDEAD
tPD
tRISE
tDEAD
Figure 8-2. H-Bridge Current Paths
8.4.2 Current Regulation
The DRV8231 device limits the output current based on the analog input, VREF, and the resistance of an
external sense resistor on the ISEN pin, RSENSE, according to Equation 1:
VREF
VREF
=
10 × R
I
=
(1)
TRIP
A
× R
V
SENSE
SENSE
By using current regulation, the device input pins can be set for 100% duty cycle, while the device switches
the outputs to keep the motor current at the ITRIP level. For example, if VREF = 3.3 V and a RSENSE = 0.15 Ω,
the DRV8231 limits motor current to 2.2 A during high torque conditions. For guidelines on selecting a sense
resistor, see the Section 9.2.1.2.3 section.
When ITRIP is reached, the device enforces slow current decay by enabling both low-side FETs, and it does this
for a time of tOFF
.
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ITRIP
tBLANK
tDRIVE
tOFF
Figure 8-3. Current-Regulation Time Periods
After tOFF elapses, the output is re-enabled according to the two inputs, INx. The drive time (tDRIVE) until reaching
another ITRIP event heavily depends on the VM voltage, the back-EMF of the motor, and the inductance of the
motor.
If current regulation is not required, the ISEN pin should be directly connected to the PCB ground plane. The
VREF voltage must still be 0.3 V to 5 V, and larger voltages provide greater noise margin. This provides
the highest-possible peak current which is up to IOCP,min for a few hundred milliseconds (depending on PCB
characteristics and the ambient temperature). If current exceeds IOCP,min, the device may enter the fault mode
due to overcurrent protection (OCP) or overtemperature shutdown (TSD).
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8.4.3 Protection Circuits
The DRV8231 device is fully protected against VM undervoltage, overcurrent, and overtemperature events.
8.4.3.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally.
If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will
disable. The driver re-enables after the OCP retry period (tRETRY) has passed. If the fault condition is still
present, the cycle repeats as shown in Figure 8-4.
Overshoot due to OCP
)
deglitch time (tOCP
IOCP
Motor
Current
Time
tOCP
tRETRY
Figure 8-4. OCP Operation
Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short
to ground, supply, or across the motor winding will all result in an overcurrent shutdown. The ISEN pin also
integrates a separate overcurrent trip threshold specified by VOCP_ISEN for additional protection when the VM
voltage is low or the RSENSE resistance on the ISEN pin is high.
8.4.3.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled. After the die temperature has
fallen to a safe level, operation automatically resumes.
8.4.3.3 VM Undervoltage Lockout (UVLO)
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, the output FETS are disabled, and all internal logic is reset. Operation continues when the
VVM voltage rises above the UVLO rising threshold as shown in Figure 8-5.
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
Device enabled,
active mode
Device status
Device enabled, active mode
Device disabled, fault mode
Time
Figure 8-5. VM UVLO Operation
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8.5 Device Functional Modes
Table 8-3 summarizes the DRV8231 functional modes described in this section.
Table 8-3. Modes of Operation
MODE
Active Mode
CONDITION
H-BRIDGE
Operating
Disabled
Disabled
INTERNAL CIRCUITS
IN1 or IN2 = logic high
IN1 = IN2 = logic low
Any fault condition met
Operating
Disabled
Low-Power Sleep Mode
Fault Mode
See Table 8-4
8.5.1 Active Mode
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the INx pins are in a state
other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the H-bridge,
charge pump, and internal logic are active and the device is ready to receive inputs.
8.5.2 Low-Power Sleep Mode
When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8231 device enters a low-power sleep mode.
In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ). If
the device is powered up while all inputs are low, it immediately enters sleep mode. After any of the input pins
are set high for longer than the duration of tWAKE, the device becomes fully operational. Figure 8-6 shows an
example timing diagram for entering and leaving sleep mode.
Sleep
Mode
Active Mode
Wakeup
Active Mode
IN1
IN2
tSLEEP
tWAKE
OUT1
OUT2
Hi-Z
Hi-Z
Figure 8-6. Sleep Mode Entry and Wakeup Timing Diagram
8.5.3 Fault Mode
The DRV8231 device enters a fault mode when a fault is encountered. This is utilized to protect the device
and the output load. The device behavior in the fault mode is described in Table 8-4 and depends on the fault
condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is met.
Table 8-4. Fault Conditions Summary
FAULT
CONDITION
VM < VUVLO,falling
IOUT > IOCP
H-BRIDGE
Disabled
Disabled
Disabled
INTERNAL CIRCUITS
RECOVERY
VM > VUVLO,rising
IOUT < IOCP
VM undervoltage (UVLO)
Overcurrent (OCP)
Disabled
Operating
Thermal Shutdown (TSD)
TJ > TTSD
Operating
TJ < TTSD – THYS
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8.6 Pin Diagrams
8.6.1 Logic-Level Inputs
100 kꢀ
Figure 8-7. Logic-level input
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8231 device is typically used to drive one brushed DC motor.
9.2 Typical Application
9.2.1 Brush DC Motor
GND
IN2
OUT2
ISEN
OUT1
VM
3.3 V
0.2 Ω
BDC
Controller
DRV8231
IN1
3.3 V
VREF
PPAD
+
œ
4.5 to 33 V
Power Supply
0.1 µF
47 µF
Figure 9-1. Typical Connections
9.2.1.1 Design Requirements
The table below lists the design parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Motor voltage
VVM
12 V
0.8 A
2.1 A
2.1 A
1.9 A
4 V
Average motor current
Motor inrush (startup) current
Motor stall current
IAVG
IINRUSH
ISTALL
Motor current trip point
VREF voltage
ITRIP
VREF
RSENSE
fPWM
Sense resistance
0.2 Ω
20 kHz
PWM frequency
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Motor Voltage
The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
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9.2.1.2.2 Motor Current
Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at
motor startup is sometimes called inrush current. The current regulation feature in the DRV8231 can help to limit
these large currents. Figure 9-4 and Figure 9-5 show examples of limiting inrush current.
Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup
time.
9.2.1.2.3 Sense Resistor
For optimal performance, the sense resistor must have the following characteristics:
•
•
•
•
Surface-mount
Low inductance
Rated for high enough power
Placed closely to the motor driver
The power dissipated by the sense resistor equals (IAVG)2 × R. For example, if peak motor current is 3 A,
average motor current is 1.5 A, and a 0.2-Ω sense resistor is used, the resistor dissipates 1.5 A2 × 0.2 Ω = 0.45
W. The power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, the system
designer should add margin. Measuring the actual sense resistor temperature in a final system is always best.
Because power resistors are larger and more expensive than standard resistors, using multiple standard
resistors in parallel, between the sense node and ground, is common and distributes the current and heat
dissipation.
9.2.1.3 Application Curves
Stall Current
Inrush Current
Inrush Current
Motor Stall Occurs
Motor Stall Occurs
Stall Current
Average Running Current
Average Running Current
Ch 1 (Yellow) = IN1 Signal
Ch 3 (Blue) = OUT1 Voltage
Ch 2 (Magenta) = IN2 Signal
Ch 7 (Red) = Motor Current
Ch 1 (Yellow) = IN1 Signal
Ch 2 (Magenta) = IN2 Signal
Ch 4 (Green) = OUT2 Voltage Ch 7 (Red) = Motor Current
Figure 9-2. Motor startup at 100% duty cycle
Figure 9-3. Motor startup at 50% duty cycle
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Current Regula on Threshold (ITRIP
)
Current Regula on Threshold (ITRIP
)
Inrush Current
Inrush Current
Motor Stall Occurs
Motor Stall Occurs
Stall Current
Stall Current
Average Running Current
Average Running Current
Ch 1 (Yellow) = IN1 Signal
Ch 3 (Blue) = OUT1 Voltage
Ch 2 (Magenta) = IN2 Signal
Ch 7 (Red) = Motor Current
Ch 1 (Yellow) = IN1 Signal
Ch 2 (Magenta) = IN2 Signal
Ch 4 (Green) = OUT2 Voltage Ch 7 (Red) = Motor Current
Figure 9-4. Motor startup at 100% duty cycle with
current regulation
Figure 9-5. Motor startup at 50% duty cycle with
current regulation
9.2.2 Stall Detection
Some applications require stall detection to notify the microcontroller of a locked rotor condition. A stall could
be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a
constrained travel path. By using current-sense amplifier (CSA) to amplify the voltage on the ISEN pin of the
DRV8231, the system can implement a simple stall detection scheme. Figure 9-6 shows an example schematic
implementation.
VCC
VM = 14.4 V
IN1
IN2
OUT1
PWM
PWM
M
MCU
DRV8231/51
VREF =
5 V
OUT2
ISEN
TLV6001
+
ADC
VSENSE,CSA
RSENSE
150 m
–
4.02 k
1 k
Figure 9-6. Stall Detection Circuit
The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions
as shown in Figure 9-7. To implement stall detection, the microcontroller reads the voltage from CSA using an
analog-to-digital converter (ADC) and compares it to a stall threshold set in firmware. Alternatively, a comparator
peripheral may be used to set this threshold as well.
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Motor driver
disabled
Stall
detected
Motor Start
IN1
IN2
Motor
current
OUTx
disabled
OUTx
disabled
Inrush
current
Average running
current
Stall
Current
Stall threshold
in rmware
VSENSE,CSA
STALL
tINRUSH
tSTALL
Figure 9-7. Motor Current Profile with STALL Signal
9.2.2.1 Design Requirements
The table below lists the design parameters.
Table 9-2. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Motor voltage
VREF voltage
VM
14.4 V
3.3 V
VREF
ISEN resistance
RSENSE
ISTALL
150 mΩ
1.5 A
Stall current
Stall detection threshold
Inrush current ignore time
Stall detection time
ISTALL,TH
tINRUSH
tSTALL
1 A
80 ms
80 ms
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Stall Detection Timing
The microcontroller needs to decide whether or not the VSENSE,CSA signal indicates a motor stall. Large inrush
current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current
drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The
inrush current should not be mistaken for a stall condition. One way to do this is for the microcontroller to
ignore the VSENSE,CSA signal above the firmware stall threshold for the duration of the inrush current, tINRUSH
,
at startup. The tINRUSH timing should be determined experimentally because it depends on motor parameters,
supply voltage, and mechanical load response times.
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When a stall condition occurs, the motor current will increase from the average running current level because
the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in
case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque
condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before
the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be
desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a
shorter tSTALL time in the microcontroller.
Figure 9-7 illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform.
9.2.2.2.2 Stall Threshold Selection
The stall detection threshold in firmware should be chosen at a current level between the maximum stall current
and the average running current of the motor as shown in Figure 9-7.
9.2.2.3 Application Curves
Inrush Current
Average Running Current
Motor Stall Occurs
Stall Current
MCU Detects Stall
Ch 1 (Yellow) = CSA Output Voltage
Ch 3 (Blue) = Stall Detection Indication
Ch 2 (Magenta) = IN1 Signal
Ch 4 (Green) = Motor Current
Figure 9-8. Example Waveform of Stall Detection
9.2.3 Relay Driving
The PWM interface may also be used to drive single- and dual-coil latching relays, as shown in the figures
below.
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VCC
DRV8251/31
Controller
GND
IN2
OUT2
ISEN
OUT1
VM
Single-
coil
relay
1
2
3
4
8
7
6
5
PWM
PWM
Thermal
Pad
IN1
VM
VCC
VREF
CBulk
0.1 μF
Figure 9-9. Single-Coil Relay Driving
VCC
DRV8251/31
VM
Dual-
coil
relay
Controller
GND
IN2
OUT2
ISEN
OUT1
VM
1
2
3
4
8
7
6
5
PWM
PWM
Thermal
Pad
IN1
VM
VCC
VREF
CBulk
0.1 μF
Figure 9-10. Dual-Coil Relay Driving
9.2.3.1 Design Requirements
Table 9-3 provides example requirements for a single- or dual-coil relay application. Current regulation may also
be configured to ensure the relay current is within the relay specification. This is important if the VM supply
voltage is higher than the voltage rating of the relay.
Table 9-3. System design requirements
DESIGN PARAMETER
Motor supply voltage
REFERENCE
EXAMPLE VALUE
12 V
VM
Microcontroller supply voltage
Single coil relay current
Dual coil relay current
VCC
3.3 V
IRelay
500 mA pulse for 200 ms
100 mA pulse for 200 ms
IOUT1, IOUT2
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Control Interface for Single-Coil Relays
The PWM interface can be used to drive single-coil relays. To actuate the relay, the driver needs to drive current
with either the forward or reverse states in the PWM table. After driving the relay, the outputs can be disabled
(IN1=IN2=0) to put the driver to sleep and save energy. Alternatively, the outputs can be put into brake mode
briefly after actuation to avoid back EMF effects from the relay or causing current to flow back from the relay into
the VM supply node.
9.2.3.2.2 Control Interface for Dual-Coil Relays
A dual coil relay only require two low-side drivers if the center tap is connected to VM. The body diodes of
the unused FETs act as freewheeling diodes, so additional freewheeling diodes are not needed when driving a
dual-coil relay with the DRV8231. The PWM interface can be used to control the dual-coil relay. The following
figures show the schematic and timing diagram for driving dual-coil relays.
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VM
VM
Sleep
mode
Sleep
mode
Sleep
mode
Drive Coil1
Drive Coil2
IN1
IN2
Coil1
IOUT1
Coil2
VM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VOUT1
VOUT2
VOUT2
VOUT1
IOUT2
GND
VM
Dual-coil
relay
GND
IOUT1
IOUT2
Figure 9-11. Schematic of dual-coil relay driven by
the OUTx H-bridge
Figure 9-12. Timing diagram for driving a dual-coil
relay with PWM interface
Table 9-4 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and
output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will
go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true
when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so
extra external diodes are not needed. Figure 9-15 shows oscilloscope traces for this application.
Table 9-4. PWM control table for dual-coil relay driving
IN1
0
IN2
OUT1
Hi-Z
L
OUT2
Hi-Z
H
DESCRIPTION
Outputs disabled (H-Bridge Hi-Z)
Drive Coil1
0
0
1
1
0
H
L
Drive Coil2
Drive Coil1 and Coil2 (invalid state for a
dual-coil latching relay)
1
1
L
L
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9.2.3.3 Application Curves
A.
Ch 1 = IN1
Ch 2 = IN2
Ch 6 = Relay
Switch
Ch 3 = VOUT1 A.
Ch 7 = Relay Coil
Current
Ch 1 = IN1
Ch 2 = IN2
Ch 3 = VOUT1
Ch 7 = Relay Coil
Current
Ch 4 = VOUT2
Ch 4 = VOUT2
Ch 6 = Relay
Switch
Figure 9-13. PWM driving for a single-coil latching Figure 9-14. PWM driving for a single-coil latching
relay with driving profile FORWARD → COAST →
REVERSE → COAST
relay with driving profile FORWARD → BRAKE →
REVERSE → BRAKE
A.
Ch 1 = IN1
Ch 4 = VOUT2
Ch 2 = IN2
Ch 3 = VOUT1
Ch 6 = Relay Switch
Ch 7 = Relay Coil1 Current
Ch 8 = Relay Coil2 Current
Figure 9-15. PWM driving for dual-coil relay
9.2.4 Multi-Sourcing with Standard Motor Driver Pinout
The DRV8870, DRV8251, and DRV8231 devices come in an industry standard package footprint in the DDA
package. When the system needs current sensing, a current-sense amplifier may be used across the RSENSE
resistor to provide an amplifed signal back to an microcontroller ADC as shown in Figure 9-16. To reduce the
size of the system bill of materials and cost, the IPROPI function in DRV8231A/51A can replace the current
sense amplifer. During the board design process, both solutions, IPROPI and industry standard shunt devices,
can be accomodated in the same board layout by placing and not placing (DNP) components as shown in Figure
9-17. This allows the system to be flexible for lowest cost with the DRV8231A/51A or for use with second-source
devices with the same pinout as DRV8870, DRV8231, and DRV8251.
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0
To ADC
DNP
0
GND
1
2
3
4
8
7
6
5
OUT2
ISEN
IN1
IN2
DRV8870,
DRV8231,
DRV8251
Rsense
0.5
OUT1
Sense
Amp
VREF
VM
Figure 9-16. Standard Pinout with Current Sense Amplifier
DNP
To ADC
0
IPROPI
1
2
3
4
8
7
6
5
OUT2
GND
Ripropi
1.5 k
IN1
IN2
DRV8231A,
DRV8251A
0
OUT1
VM
Sense
Amp DNP
VREF
Figure 9-17. DRV8231A/51A Device Using IPROPI to Integrate The Current Sense Function into The
Motor Driver
9.3 Current Capability and Thermal Performance
The output current and power dissipation capabilities of the driver depends heavily on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
9.3.1 Power Dissipation and Output Current Capability
Total power dissipation for the device consists of three main components: quiescent supply current dissipation
(PVM), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction) losses (PRDS).
While other factors may contribute additional power losses, they are typically insignificant compared to the three
main items.
PTOT = PVM + PSW + PRDS
PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current
specification.
PVM = VVM x IVM
(2)
(3)
PVM = 96 mW = 24 V x 4 mA
PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IAVG), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL
(4)
(5)
(6)
(7)
PSW_RISE = 0.5 x VM x IAVG x tRISE x fPWM
PSW_FALL = 0.5 x VM x IAVG x tFALL x fPWM
PSW_RISE = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz
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PSW_FALL = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz
(8)
(9)
PSW = 53 mW = 26.4 mW + 26.4 mW
PRDS can be calculated from the device RDS(on) and average output current (IAVG).
PRDS = IAVG 2 x (RDS(ON)_HS + RDS(ON)_LS
)
(10)
RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85
°C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows this
derating factor. Alternatively, Section 7.6 shows curves that plot how RDS(on) changes with temperature.
PRDS = 225 mW = (0.5 A)2 x (300 mΩ x 1.5 + 300 mΩ x 1.5)
(11)
Based on the example calculations above, the expressions below calculate the total expected power dissipation
for the device.
PTOT = PVM + PSW + PRDS
PTOT = 374 mW = 96 mW + 53 mW + 225 mW
(12)
The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking
around the device. Section 9.3.2 describes this dependence in greater detail.
TJ = (PTOT x RθJA) + TA
(13)
(14)
TJ = 100 °C = (0.374 W x 40.4 °C/W) + 85°C
The device junction temperature should remain below its absolute maximum rating for all system operating
conditions. The calculations in this section provide reasonable estimates for junction temperature. However,
other methods based on temperature measurements taken during system operation are more realistic and
reliable. Additional information on motor driver current ratings and power dissipation can be found in Section
9.3.2 and Section 12.1.1.
9.3.2 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria.
HSOP (DDA package)
Table 9-5. Simulation PCB Stackup Summary for HSOP package
Layer
2-layer
4-layer
Top Layer
HSOP footprint with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally
connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from HSOP thermal
pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground N/A
plane
1-oz copper thickness, 74.2 mm x 74.2 mm copper
area, thermally connected to HSOP thermal pad
through vias.
Layer 3, internal supply
plane
N/A
1-oz copper thickness, 74.2 mm x 74.2 mm copper
area, not connected to other layers.
Bottom Layer
Ground plane with 1- or 2-oz copper thickness. See
1- or 2-oz copper thickness. Copper area fixed at 4.90
Table 9-6 for copper area varied in simulation. Thermally mm × 6.00 mm in simulation. Thermally connected to
connected to HSOP thermal pad through vias. HSOP thermal pad through vias.
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Figure 9-18 shows an example of the simulated board for the HSOP package. Table 9-6 shows the dimensions
of the board that were varied for each simulation.
Figure 9-18. HSOP PCB model top layer
Table 9-6. Dimension A for 8-pin HSOP (DDA) package
Cu area (cm2)
Dimension A (mm)
0.069
Package thermal pad dimensions
2
4
16.40
22.32
30.64
42.38
8
16
WSON (DSG package)
Table 9-7. Simulation PCB Stackup Summary for WSON package
Layer
2-layer
4-layer
Top Layer
WSON footprint with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally
connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from WSON thermal
pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground N/A
plane
1-oz copper thickness, 74.2 mm x 74.2 mm copper
area, thermally connected to HSOP thermal pad
through vias.
Layer 3, internal supply
plane
N/A
1-oz copper thickness, 74.2 mm x 74.2 mm copper
area, not connected to other layers.
Bottom Layer
Ground plane with 1- or 2-oz copper thickness. See
1- or 2-oz copper thickness. Copper area fixed at 2.00
Table 9-8 for copper area varied in simulation. Thermally mm × 2.00 mm in simulation. Thermally connected to
connected to WSON thermal pad through vias. WSON thermal pad through vias.
Figure 9-19 shows an example of the simulated board for the WSON package. Table 9-8 shows the dimensions
of the board that were varied for each simulation.
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Figure 9-19. WSON PCB model top layer
Table 9-8. Dimension A for 8-pin WSON package
Cu area (mm2)
Dimension A (mm)
0.015
Package thermal pad dimensions
2
4
15.11
20.98
29.27
40.99
8
16
9.3.2.1 Steady-State Thermal Performance
"Steady-state" conditions assume that the motor driver operates with a constant average current over a long
period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter)
change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more
layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the
PCB layout.
200
180
160
140
120
100
80
50
45
40
35
30
25
20
15
10
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
60
40
20
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Top layer copper area (cm2)
Top layer copper area (cm2)
Figure 9-20. HSOP, PCB junction-to-ambient
thermal resistance vs copper area
Figure 9-21. HSOP, junction-to-board
characterization parameter vs copper area
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275
250
225
200
175
150
125
100
75
80
75
70
65
60
55
50
45
40
35
30
25
20
15
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
50
25
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Top layer copper area (cm2)
Top layer copper area (cm2)
Figure 9-22. WSON, PCB junction-to-ambient
thermal resistance vs copper area
Figure 9-23. WSON, junction-to-board
characterization parameter vs copper area
9.3.2.2 Transient Thermal Performance
The motor driver may experience different transient driving conditions that cause large currents to flow for a
short duration of time. These may include
•
•
Motor start-up when the rotor is initially stationary.
Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent
protection triggers.
•
Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance in
addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the
junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances
for 1-oz and 2-oz copper layouts for the HSOP and WSON packages. These graphs indicate better thermal
performance with short current pulses. For short periods of drive time, the device die size and package
dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on
thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and
copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state
performance.
200
100
70
50
40
30
20
10
7
0.069 cm2, 2 layer
2 cm2, 2 layer
5
4
3
4 cm2, 2 layer
8 cm2, 2 layer
0.069 cm2, 4 layer
2 cm2, 4 layer
2
4 cm2, 4 layer
8 cm2, 4 layer
1
0.001 0.002 0.005 0.01 0.02
0.05 0.1
0.2 0.3 0.50.7 1
2
3
4 5 67810
20 30 50 70100 200300 500 1000
Pulse duration (s)
Figure 9-24. HSOP package junction-to-ambient thermal impedance for 1-oz copper layouts
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200
100
70
50
40
30
20
10
7
0.69 cm2, 2 layer
2 cm2, 2 layer
4 cm2, 2 layer
8 cm2, 2 layer
0.69 cm2, 4 layer
2 cm2, 4 layer
4 cm2, 4 layer
8 cm2, 4 layer
5
4
3
2
1
0.001 0.002 0.005 0.01 0.02
0.05 0.1
0.2 0.3 0.50.7 1
2
3
4 5 67810
20 30 50 70100 200300 500 1000
Pulse Duration (s)
Figure 9-25. HSOP package junction-to-ambient thermal impedance for 2-oz copper layouts
300
200
100
70
50
40
30
20
0.015 cm2, 2 layer
10
7
2 cm2, 2 layer
4 cm2, 2 layer
8 cm2, 2 layer
5
4
0.015 cm2, 4 layer
2 cm2, 4 layer
4 cm2, 4 layer
8 cm2, 4 layer
3
2
0.001 0.002 0.005 0.01 0.02
0.05 0.1
0.2 0.3 0.50.7 1
2
3
4 5 67810
20 30 50 70100 200300 500 1000
Pulse duration (s)
Figure 9-26. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts
300
200
100
70
50
40
30
20
0.015 cm2, 2 layer
10
7
2 cm2, 2 layer
4 cm2, 2 layer
8 cm2, 2 layer
5
4
0.015 cm2, 4 layer
2 cm2, 4 layer
4 cm2, 4 layer
8 cm2, 4 layer
3
2
0.001 0.002 0.005 0.01 0.02
0.05 0.1
0.2 0.3 0.50.7 1
2
3
4 5 67810
20 30 50 70100 200300 500 1000
Pulse duration (s)
Figure 9-27. WSON package junction-to-ambient thermal impedance for 2-oz copper layouts
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10 Power Supply Recommendations
10.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The capacitance of the power supply and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VBB
+
Motor
Driver
+
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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11 Layout
11.1 Layout Guidelines
Since the DRV8231 integrates power MOSFETs capable of driving high current, careful attention should be paid
to the layout design and external component placement. Some design and layout guidelines are provided below.
•
•
•
•
•
Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are
recommended.
The VM power supply capacitors should be placed as close to the device as possible to minimize the loop
inductance.
The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as
close as possible to the device to minimize the loop inductance.
VM, OUT1, OUT2, and PGND carry the high current from the power supply to the outputs and back to
ground. Thick metal routing should be utilized for these traces as is feasible.
The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
•
•
A recommended land pattern for the thermal vias is provided in the package drawing section.
The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
11.2 Layout Example
GND
IN2
1
2
3
4
8
7
6
5
OUT2
ISEN
OUT1
VM
Thermal
Pad
IN1
VREF
+
Figure 11-1. Layout Recommendation for DSG package
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GND
IN2
1
2
3
4
8
7
6
5
OUT2
ISEN
OUT1
VM
Thermal
Pad
IN1
VREF
+
Figure 11-2. Layout Recommendation
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
Texas Instruments, Calculating Motor Driver Power Dissipation application report
Texas Instruments, Current Recirculation and Decay Modes application report
Texas Instruments, PowerPAD™ Made Easy application report
Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, Understanding Motor Driver Current Ratings application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
PowerPAD™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8231DSGR
ACTIVE
WSON
DSG
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
31
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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