DRV8245SQRXZRQ1_技术文档

DRV8245-Q1

SLVSFJ1A – NOVEMBER 2021 – REVISED DECEMBER 2021

DRV8245-Q1 Automotive H-Bridge Driver with Integrated Current Sense and

Diagnostics

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications:

– Temperature grade 1: –40°C to +125°C, T_A

Functional Safety-Capable

– Documentation available to aid functional safety

system design

4.5-V to 35-V (40-V abs. max) operating range

VQFN-HR package: R_{ON_LS}+ R_{ON_HS}: 32 mΩ

HTSSOP package: R_{ON_LS}+ R_{ON_HS}: 40 mΩ

I_OUTMax = 32 A

PWM frequency operation up to 25 KHz with

automatic dead time assertion

Configurable slew rate and spread spectrum

clocking for low electromagnetic interference (EMI)

Integrated current sense (eliminates shunt resistor)

Proportional load current output on IPROPI pin

Configurable current regulation

Protection and diagnostic features with

configurable fault reaction (latched or retry)

– Load diagnostics in both the off-state and on-

state to detect open load and short circuit

– Voltage monitoring on supply (VM)

– Over current protection

The DRV824x-Q1 family of devices is a fully

integrated H-bridge driver intended for a wide

range of automotive applications. The device can

be configured as a single full-bridge driver or as

two independent half-bridge drivers. Designed in a

BiCMOS high power process technology node, this

monolithic family of devices in a power package

offer excellent power handling and thermal capability

while providing compact package size, ease of layout,

EMI control, accurate current sense, robustness, and

diagnostic capability. This family also has identical

pin function with scalable R_ON(current capability) to

support different loads.

•

The devices integrate a N-channel H-bridge, charge

pump regulator, high-side current sensing and

regulation, current proportional output, and protection

circuitry. A low-power sleep mode is provided to

achieve low quiescent current. The devices offer

voltage monitoring and load diagnostics as well

as protection features against over current and

over temperature. Fault conditions are indicated on

nFAULT pin. The devices are available in three

variants - hardwired interface: HW (H) and two SPI

interface variants: SPI(P) and SPI(S), with SPI (P)

for externally supplied logic supply and SPI (S) for

internally generated logic supply. The SPI interface

variants offer more flexibility in device configuration

and fault observability.

– Over temperature protection

– Fault indication on nFAULT pin

Supports 3.3-V, 5-V logic inputs

Low sleep current - 1μA typical at 25°C

3 variants - HW (H), SPI (S) or SPI (P)

Configurable control modes:

•

– Single full bridge using PWM or PH/EN mode

– Two half-bridges using Independent mode

Device family comparison table

Device Information⁽¹⁾

PART NUMBER

DRV8245-Q1

PACKAGE

VQFN-HR (16)

HTSSOP (28)

BODY SIZE (nominal)

3.5 mm X 5.5 mm

4.4 mm X 9.7 mm

•

2 Applications

DRV8245-Q1⁽²⁾

•

Automotive brushed DC motors, Solenoids

Door modules , wiper modules , trunk and seat

modules

(1) For all available packages, see the orderable addendum at

the end of the data sheet

(2) Device available for preview only.

•

Body control module (BCM)

E-Shifter

Steering systems

Gas engine systems

On board charger

4.5 - 35 V

nSLEEP

DRV824X-Q1

Driver Control

nFAULT

Full Bridge

Driver

SPI (SPI variant)

CONFIG pins

(HW variant)

Diagnos cs

Current Sense

IPROPI

ADC

Current Regula on

Built-in Protec on

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

DRV8245-Q1

SLVSFJ1A – NOVEMBER 2021 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................6

6.1 HW Variant..................................................................6

6.2 SPI Variant..................................................................9

7 Specifications................................................................ 12

7.1 Absolute Maximum Ratings...................................... 12

7.2 ESD Ratings............................................................. 12

7.3 Recommended Operating Conditions.......................13

7.4 Thermal Information..................................................13

7.5 Electrical Characteristics...........................................13

7.6 SPI Timing Requirements......................................... 20

7.7 Switching Waveforms................................................22

7.8 Typical Characteristics..............................................28

8 Detailed Description......................................................30

8.1 Overview...................................................................30

8.2 Functional Block Diagram.........................................31

8.3 Feature Description...................................................34

8.4 Device Functional States.......................................... 48

8.5 Programming - SPI Variant Only...............................50

8.6 Register Map - SPI Variant Only...............................55

9 Application and Implementation..................................62

9.1 Application Information............................................. 62

9.2 Typical Application.................................................... 63

10 Power Supply Recommendations..............................67

10.1 Bulk Capacitance Sizing......................................... 67

11 Layout...........................................................................68

11.1 Layout Guidelines................................................... 68

11.2 Layout Example...................................................... 68

12 Device and Documentation Support..........................69

12.1 Documentation Support.......................................... 69

12.2 Receiving Notification of Documentation Updates..69

12.3 Community Resources............................................69

12.4 Trademarks.............................................................69

13 Mechanical, Packaging, and Orderable

Information.................................................................... 69

13.1 Tape and Reel Information......................................73

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (November 2021) to Revision A (December 2021)

Page

•

Updated device status to Mixed Production....................................................................................................... 1

2

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5 Device Comparison

Table 5-1 summarizes the R_ONand package differences between devices in the DRV824X-Q1 family.

Table 5-1. Device Comparison

PART NUMBER⁽²⁾

DRV8243-Q1

DRV8244-Q1

DRV8245-Q1

DRV8245-Q1⁽³⁾

(LS + HS) R_ON

84 mΩ

I_OUTMAX

PACKAGE

VQFN-HR (14)

HVSSOP (28)

VQFN-HR (16)

HVSSOP (28)

VQFN-HR (16)

HTSSOP (28)

BODY SIZE (nominal)

3 mm X 4.5 mm

3 mm X 7.3 mm

3 mm X 6 mm

Variants

12 A

HW (H), SPI (S)

98 mΩ

12 A

HW (H), SPI (S), SPI (P)

HW (H), SPI (S)⁽¹⁾

47 mΩ

21 A

60 mΩ

21 A

3 mm X 7.3 mm

3.5 mm X 5.5 mm

4.4 mm X 9.7 mm

HW (H), SPI (S), SPI (P)

HW (H)⁽¹⁾, SPI (S)

32 mΩ

32 A

40 mΩ

32 A

HW (H), SPI (S), SPI (P)

(1) DRV8245HRXZQ1 and DRV8244SRYJQ1 exceptions:

a. Off-state diagnostics (OLP) - This feature is NOT available for use in DRV8244SRYJQ1 (SPI(S) variant in VQFN-HR (16)

package) and DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) - recommend to disable OLP in application.

b. Slew rate setting (SR = 3'b000, 3'b001, 3'b010) for DRV8244SRYJQ1 (SPI(S) variant in VQFN-HR (16) package) and LVL2 for

DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) is NOT available in Independent mode operation using low-side

recirculation (low-side load) - recommend to use other settings for slew rate control.

(2) This is the product datasheet for the DRV8245-Q1. Please reference other device variant data sheets for additional information.

(3) Device available for preview only.

Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV824X-

Q1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback,

redundant driver shutoff, improved Pin FMEA and additional features.

In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant. The SPI (P) variant supports

an external, low voltage 5 V supply to the device through the VDD pin for the device logic, whereas in the SPI

(S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant

avoids device brown out (reset of device) during VM under voltage transients.

Table 5-2. SPI Variant vs HW Variant Comparison

FUNCTION

HW (H) Variant

SPI (S) Variant

SPI (P) Variant

Individual pin "and/or" register bit with pin status indication (Refer

Bridge control

Pin only

Register Pin control)

Sleep function

Available through nSLEEP pin

Not available

External logic supply to the device

Not supported

Supported through VDD pin

Reset pulse on nSLEEP

Clear fault command

Slew rate

SPI CLR_FAULT command

6 levels

8 levels

Fixed at the highest

setting

Over current protection (OCP)

3 choices for thresholds, 4 choices for filter time

5 levels with disable &

fixed TOFF time

ITRIP regulation

7 levels with disable & indication, with programmable TOFF time

Supported

Individual fault reaction configuration

between retry or latched behavior

Not supported, either all

latched or all retry

Detailed fault logging and device status

feedback

Not supported, nFAULT

pin monitoring necessary

Supported, nFAULT pin monitoring optional

VM over voltage

Fixed

4 threshold choices

Supported for high-side loads

Supported

On-state (Active) diagnostics

Spread spectrum clocking (SSC)

Additional driver states in PWM mode

Not supported

Supported

Hi-Z for individual half-bridge in

Independent mode

Not supported

Supported (SPI register only)

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Note

There are some functional improvements as well as parametric corrections between the pre-

production samples and final production devices. These differences are summarized in the feature

changes table and errata table. The sample types can be differentiated visually by their package

symbolization. Pre-production samples are pre-fixed with a "P" on the package symbolization.

Additionally, for the SPI variant, it is possible to electrically differentiate between the samples by

reading the DEVICE_ID register byte (refer to Table 5-5).

Table 5-3 summarizes the feature changes between the pre-production samples and final production devices.

Table 5-3. Feature Changes Between Pre-Production and Production Samples

Feature

Pre-Production Samples

Final Product

Parallel mode removed. Use the DRV814X equivalent

device for this.

Parallel Mode

Parallel mode available

DRV824X: SR = ~[1.6 12* 18* 23 28 33 38 43] V/usec DRV824X: SR = ~[1.2 4* 6.7* 11.4 17 22 32 41] V/usec

Slew Rate

HW only 6 choices only for high-side recirculation

*Additional settings in SPI variant only

for high-side recirculation

*Additional settings in SPI variant only

OCP limit in DRV8243

Set at 9 A min

Increased to 12 A

VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65* 1.41* 1.18] V

*Additional settings in SPI only

ITRIP regulation levels VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65] V

DRVOFF_SEL, EN_IN1_SEL, PH_IN2_SEL

When SPI_IN is unlocked, the input pins, DRVOFF,

SPI variants only - Reg / EN_IN1 and PH_IN2, become don’t care and the

introduced to configure the logical combination

(AND/OR) of each of the three input pins (DRVOFF,

EN/IN1, PH/IN2) with their register bit counterparts,

when SPI_IN is unlocked. (Refer Register Pin control)

Pin control

output is controlled by their equivalent register bits

only.

[IN1 IN2] = [H H] => HiZ, [L L] => Brake. This

eliminates risk for direction reversal for a short to GND

or Open in PWM mode.

PWM truth table

[IN1 IN2] = [L L] => HiZ, [H H] => Brake

Changes allow for efficient diagnostic monitoring, in

addition to support extended configurability

1. STATUS2 byte added for DRVOFF_STAT and

ACTIVE bit indication

SPI variants only -

Register map expansion

2. OLP_CMP moved to STATUS2 with a redundant

ACTIVE bit replacing OLP_CMP in the STATUS1

3. CONFIG4 byte added to accommodate

configurability for OCP control and output control

through input pins & their equivalent register bits

As listed in the register map section

1. SPI variant - Feature enabled by default

2. HW variant - Feature always enabled

1. SPI variant - Feature disabled by default

2. HW variant - Feature always disabled

Spread spectrum clocking

Added 2 bits of OCP_SEL to lower OCP threshold and

2 bits of OCP_TSEL to change the OCP filter time.

Over current protection Fixed thresholds

Additional SPI (P) variant – nSLEEP/VIO pin function

changed to external VDD input as logic supply

SPI (P) variant

Not available

Thresholds swapped in half-bridge operation to enable

differentiation between short and open for a half-bridge

use case during off-state diagnostics (OLP)

Can't differentiate between open and short for a half-

bridge use case during off-state diagnostics (OLP)

OLP CMP reference

Processes write commands for

Improved feature to process write commands for

1. length = 16 SCLKs for regular SPI frame or

1. length ≥ 16 SCLKs for regular SPI frame or

SPI variant only – Frame

length error

2. length ≥ 16 + “N” x 16 SCLKs for daisy chain SPI 2. length = 16 + “N” x 16 SCLKs for daisy chain SPI

frame, where N = number of peripherals

Only shorter lengths are rejected with SPI_ERR

All other lengths are rejected with SPI_ERR

4

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Table 5-4. Errata Fixes Between Pre-Production and Production Samples

Errata

Pre-Production Samples

Final Product

HW (H) variant only - Mean shift in

determining the resistance to GND at the

CONFIG pins

Fixed the mean shift to ensure 10% resistor

(datasheet target) is OK for use on the

CONFIG pins as per datasheet

Recommend to use 1% resistor on the

CONFIG pins to ensure expected behavior

Digital input pin - hysteresis is lower than

expected

Hysteresis measured: [Min/ Typ/ Max] = [30/ Fixed to meet datasheet target of: [Min/ Typ/

60/ 90] mV

Max] = [70/ 100/ 150] mV

ITRIP regulation accuracy – lower than

expected

VTRIP threshold comparison could be ~ +/-

12%

Fixed to meet datasheet target of < +/- 10%

Over current protection threshold mean shift

of high-side FET for DRV8245 closer to the

lower threshold

Fixed the mean value so that min OCP is

always > 32 A(datasheet target)

OCP of HSx FET could be as low as 28 A

Table 5-5. Differentiating Between Pre-Production and Production Samples

Pre-Production Samples

Final Product

Device

Package Symbolization

DEVICE_ID Register

Not applicable

0 x 30

Package Symbolization

DEVICE_ID Register

Not applicable

0 x 32

DRV8243H-Q1

DRV8244H-Q1

DRV8245H-Q1

DRV8243S-Q1

DRV8244S-Q1

DRV8245S-Q1

DRV8243P-Q1

DRV8244P-Q1

DRV8245P-Q1

P8243X

P8244X

P8245X

P8243X

P8244X

P8245X

8243H

8244H

8245H

8243S

8244S

8245S

8243P

8244P

8245P

0 x 40

0 x 42

0 x 50

0 x 52

Not available

0 x 36

Not available

0 x 46

0 x 56

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6 Pin Configuration and Functions

6.1 HW Variant

6.1.1 HTSSOP (28) Package

1

2

3

4

5

SR

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITRIP

MODE

nFAULT

IPROPI

nSLEEP

VM

DIAG

PH/IN2

EN/IN1

DRVOFF

VM

6

VM

7

VM

8

9

OUT1

OUT2

10

11

12

13

14

OUT1

GND

OUT2

GND

Figure not drawn to scale

Figure 6-1. DRV8245H-Q1 HW Variant in HTSSOP (28) Package

Table 6-1. Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NO.

NAME

Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device

Configuration section.

1

SR

I

Device configuration pin for load type indication and fault reaction configuration. For details,

refer to DIAG in the Device Configuration section.

2

DIAG

3

4

5

PH/IN2

EN/IN1

I

Controller input pin for bridge operation. For details, see the Bridge Control section.

Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.

DRVOFF

Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins

(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic

capacitor and a bulk capacitor.

6, 7, 8, 21,

22, 23

VM

P

Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of

OUT1 pins (3 total) to support device current capability.

9, 10, 11

OUT1

GND

P

12, 13, 14,

15, 16, 17

Ground pin. Must combine with the rest of GND pins (6 total) to support device current

capability.

G

Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of

OUT2 pins (3 total) to support device current capability.

18, 19, 20

OUT2

nSLEEP

IPROPI

P

I

24

25

Controller input pin for SLEEP . For details, see the Bridge Control section.

Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration

section.

I/O

Fault indication to the controller. For details, refer to nFAULT in the Device Configuration

section.

26

nFAULT

OD

6

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Table 6-1. Pin Functions (continued)

TYPE ⁽¹⁾

DESCRIPTION

NO.

NAME

27

MODE

I

Device configuration pin for MODE. For details, refer to the Device Configuration section.

Device configuration pin for ITRIP level for high-side current limiting. For details, refer to

ITRIP in the Device Configuration section.

28

ITRIP

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

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6.1.2 VQFN-HR(16) Package

nFAULT

1

2

3

12 PH/IN2

12

11

nFAULT

IPROPI

nSLEEP

VM

PH/IN2

EN/IN1

2

3

IPROPI

11

EN/IN1

TOP VIEW

nSLEEP

DRVOFF 10

BOTTOM VIEW

DRVOFF

10

4

VM

4

VM

OUT2

GND

OUT2

5

6

9

8

OUT1

9

8

5

6

OUT1

OUT2

GND

7

GND

GND GND GND GND

Figure not drawn to scale

GND GND GND GND

Figure 6-2. DRV8245H -Q1 HW Variant in VQFN-HR(16) Package

Table 6-2. Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NO.

NAME

Fault indication to the controller. For details, refer to nFAULT in the Device Configuration

section.

1

nFAULT

OD

Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration

section.

2

3

4

IPROPI

nSLEEP

VM

I/O

I

Controller input pin for SLEEP . For details, see the Bridge Control section.

Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF

ceramic capacitor and a bulk capacitor.

P

Half-bridge output 2. Connect this pin to the motor or load. Must combine with the other

OUT2 pin to support device current capability.

5, 6

OUT2

P

7

8, 9

10

11

GND

OUT1

G

P

I

Ground pin

Half-bridge output 1. Connect this pin to the motor or load.

Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.

Controller input pin for bridge operation. For details, see the Bridge Control section.

DRVOFF

EN/IN1

PH/IN2

I

12

I

Device configuration pin for load type indication and fault reaction configuration. For details,

refer to DIAG in the Device Configuration section.

13

14

DIAG

SR

I

Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device

Configuration section.

Device configuration pin for ITRIP level for high-side current limiting. For details, refer to

ITRIP in the Device Configuration section.

15

16

ITRIP

I

MODE

Device configuration pin for MODE. For details, refer to the Device Configuration section.

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

8

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6.2 SPI Variant

6.2.1 HTSSOP (28) Package

1

SCLK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SCLK

nSCS

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SDI

2

3

4

5

nSCS

SDO

nFAULT

IPROPI

VDD

VM

3

nFAULT

IPROPI

nSLEEP

VM

PH/IN2

EN/IN1

DRVOFF

VM

4

EN/IN1

5

DRVOFF

VM

6

VM

7

VM

8

9

OUT1

OUT2

10

11

12

13

14

OUT1

11

OUT1

GND

OUT2

GND

OUT2

GND

12

GND

13

GND

14

Figure not drawn to scale

SPI (S) variant

SPI (P) variant

Figure 6-3. DRV8245S-Q1 SPI Variant in HTSSOP (28) Package

Table 6-3. Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NO.

1

NAME

SCLK

I

SPI - Serial Clock input.

2

nSCS

SPI - Chip Select. An active low on this pin enables the serial interface communication.

Controller input pin for bridge operation. For details, see the Bridge Control section.

Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.

3

PH/IN2

EN/IN1

DRVOFF

4

5

Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins

(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic

capacitor and a bulk capacitor.

6, 7, 8, 21,

22, 23

VM

P

Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of

OUT1 pins (3 total) to support device current capability.

9, 10, 11

OUT1

GND

P

G

P

12, 13, 14,

15, 16, 17

Ground pin. Must combine with the rest of GND pins (6 total) to support device current

capability.

Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of

OUT2 pins (3 total) to support device current capability.

18, 19, 20

OUT2

SPI (S) variant: Controller input pin for SLEEP. For details, see the Bridge Control section.

Also VIO logic level for SDO.

nSLEEP

VDD

I

24

P

SPI (P) variant: Logic power supply to the device.

Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration

section.

25

26

IPROPI

I/O

Fault indication to the controller. For details, refer to nFAULT in the Device Configuration

section.

nFAULT

OD

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Table 6-3. Pin Functions (continued)

TYPE ⁽¹⁾

DESCRIPTION

NO.

27

NAME

SDO

SDI

PP

I

SPI - Serial Data Output. Data is updated at the rising edge of SCLK.

SPI - Serial Data Input. Data is captured at the falling edge of SCLK.

28

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

10

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6.2.2 VQFN-HR (16) Package

PH/IN2

1

2

1

2

3

12

11

10

nFAULT

IPROPI

nFAULT

IPROPI

11 EN/IN1

EN/IN1

TOP VIEW

3

BOTTOM VIEW

nSLEEP

VM

10

DRVOFF

VM

nSLEEP

VM

4

VM

OUT1

OUT2

GND

OUT2

GND

5

6

9

8

OUT1

9

8

5

6

GND

7

GND

GND GND GND GND

Figure not drawn to scale

GND GND GND GND

Figure 6-4. DRV8245S-Q1 SPI Variant in VQFN-HR (16) Package

Table 6-4. Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NO.

NAME

Fault indication to the controller. For details, refer to nFAULT in the Device Configuration

section.

1

2

3

4

nFAULT

OD

I/O

I

Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration

section.

IPROPI

nSLEEP

VM

Controller input pin for SLEEP. For details, see the Bridge Control section. Also VIO logic

level for SDO.

Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF

ceramic capacitor and a bulk capacitor.

P

Half-bridge output 2. Connect this pin to the motor or load. Must combine with the other

OUT2 pin to support device current capability.

5, 6

7

OUT2

GND

P

G

P

Ground pin

Half-bridge output 1. Connect this pin to the motor or load. Must combine with the other

OUT1 pin to maximize device current capability.

8, 9

OUT1

10

11

12

13

14

15

16

DRVOFF

EN/IN1

PH/IN2

nSCS

SCLK

SDI

I

Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.

Controller input pin for bridge operation. For details, see the Bridge Control section.

SPI - Chip Select. An active low on this pin enables the serial interface communication.

SPI - Serial Clock input.

I

SPI - Serial Data Input. Data is captured at the falling edge of SCLK.

SPI - Serial Data Output. Data is updated at the rising edge of SCLK.

SDO

PP

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

Power supply pin voltage

VM

–0.3

40

2

Power supply transient voltage ramp

V/µs

V

Output pin voltage

OUT1, OUT2

-0.9

V_VM+ 0.9

Output pin current

Internally limited⁽²⁾

A

Driver disable pin voltage

Logic I/O voltage

DRVOFF

–0.3

40

V

EN/IN1, PH/EN2, nFAULT

MODE, ITRIP, SR, DIAG

IPROPI

5.75

V

HW variant - Configuration pins voltage

Analog feedback pin voltage

V

Sleep pin voltage (Not applicable for SPI (P)

variant)

nSLEEP

–0.3

40

V

SPI I/O voltage - SPI variant

SPI (P) variant - Logic supply

SDI, SDO, nSCS, SCLK

VDD

–0.3

-0.3

5.75

V

SPI (P) variant - Logic supply transient voltage

ramp

VDD

5

V/µs

Ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

–40

–65

125

150

°C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Limited by the over current and over temperature protection functions of the device

7.2 ESD Ratings

VALUE

±4000

±2000

±750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

VM, OUT1, OUT2, GND

All other pins

Electrostatic

discharge

V_(ESD)

V

Corner pins

Charged device model (CDM), per AEC Q100-011

CDM ESD Classification Level C4B

Other pins

±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)

MIN

4.5

MAX

35⁽¹⁾

5.5

UNIT

V

V_VM

Power supply voltage

VM

V_VDD

SPI (P) variant - Logic supply voltage

VDD

4.5

V

EN/IN1, PH/EN2, nSLEEP, DRVOFF,

nFAULT

V_LOGIC

Logic pin voltage

0

5.5

V

f_PWM

PWM frequency

EN/IN1, PH/EN2

MODE, ITRIP, SR, DIAG

IPROPI

0

25

5.5

KHz

V

V_CONFIG

V_IPROPI

HW variant - Configuration pin voltage

Analog feedback voltage

V

V_nSLEEP

0.5

+

SPI (S) variant - SPI pin voltage

SDI, SDO, nSCS, SCLK

0

V

V_{SPI_IOS}

SPI (P) variant - SPI pin voltage

Operating ambient temperature

Operating junction temperature

0

V_VDD+ 0.5

125

V

T_A

T_J

–40

°C

150

(1) The over current protection function does not support direct output (OUT1, OUT2) shorts less than 1 μH above 28 V.

7.4 Thermal Information

Refer Transient thermal impedance table for application related use case.

THERMAL METRIC⁽¹⁾

HTSSOP package VQFN-HR package

UNIT

°C/W

R_θJA

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

27.7

13.8

7.1

41.3

14.4

5.5

Ψ_JT

0.6

0.3

Ψ_JB

7.1

5.4

R_θJC(bot)

0.9

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

4.5 V (falling) ≤ V_VM≤ 35 V, -40°C ≤ T_J≤ 150°C (unless otherwise noted)

For SPI (P) variant only: 4.5 V ≤ V_VDD≤ 5.5 V (unless otherwise noted)

7.5.1 Power Supply & Initialization

Refer wake up transient waveforms

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply pin voltage during reverse

current

V_{VM_REV}

I_VM= - 5 A, device in unpowered state

0.7

V

V_VM= 13.5 V, V_nSLEEP= 0 V or V_VDD

POR_{VDD_FALL}, T_A= 25°C

<

1

µA

I_VMQ

VM current in SLEEP state

V_VM= 13.5 V, V_nSLEEP= 0 V or V_VDD

POR_{VDD_FALL}, T_A= 125°C

<

13

I_VMS

I_VDD

VM current in STANDBY state

VDD current in ACTIVE state

V_VM= 13.5 V

3

5

mA

SPI (P) variant

10

Reset signal on nSLEEP pin for HW (H)

variant

t_RESET

t_SLEEP

RESET pulse filter time

5

20

µs

Sleep signal on nSLEEP pin for HW (H)

variant

SLEEP command filter time

40

120

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UNIT

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PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Sleep signal on nSLEEP pin for SPI (S)

variant

t_{SLEEP_SPI}SLEEP command filter time

5

20

µs

Wake-up signal on nSLEEP pin for HW

(H) and SPI (S) variants

t_WAKEUP

Wake-up command filter time

10

µs

Time for communication to be available Wake-up signal on nSLEEP pin or

t_COM

after wake-up or power-up through VM

or VDD supply pin

power cycle - V_VM> VM_{POR_RISE}or

V_VDD> VDD_{POR_RISE}

400

1

Time for driver ready to be driven after

Wake-up signal on nSLEEP pin or

wake-up through nSLEEP pin or power- power cycle - V_VM> VM_{POR_RISE}or

up through VM or VDD supply pin V_VDD> VDD_{POR_RISE}

t_READY

ms

7.5.2 Logic I/Os

PARAMETER

TEST CONDITIONS

MIN

TYP

200

100

MAX

UNIT

V

V_{IL_nSLEEP}Input logic low voltage

V_{IH_nSLEEP}Input logic high voltage

nSLEEP pin

0.65

1.55

V

V_{IHYS_nSLEE}

Input hysteresis

nSLEEP pin

mV

P

V_IL

V_IH

Input logic low voltage

Input logic high voltage

Input hysteresis

DRVOFF, EN/IN1, PH/IN2 pins

0.7

V

1.5

V_IHYS

mV

Internal pull-down resistance on nSLEEP

to GND

R_{PD_nSLEEP}

Measured at min VIL level

Measured at min VIH level

Measured at max VIL level

V_nFAULT= 0.3 V

100

200

5

400

550

500

KΩ

mA

Internal pull-up resistance to VDD

(reverse current blocked) on DRVOFF

R_PU

Internal pull-down resistance to GND on

EN/IN1 and PH/IN2

R_PD

Sink current to GND on nFAULT pin

when asserted low

I_{nFAULT_PD}

7.5.3 SPI I/Os

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal pull-up resistance to VDD

(reverse current blocked) on nSCS

R_{PU_nSCS}

R_{PD_SPI}

Measured at min VIH level

200

500

KΩ

Internal pull-down resistance to GND on

SDI, SCLK

Measured at max VIL level

150

1.5

500

0.7

KΩ

V_IL

V_IH

Input logic low voltage

Input logic high voltage

Input hysteresis

SDI, SCLK, nSCS pins

0.5 mA sink into SDO

V

V_IHYS

100

mV

V

V_{OL_SDO}Output logic low voltage

0.4

0.5 mA source from SDO, V_nSLEEP= 5

V, V_VM> 7 V

4.1

2.7

4.5

V

Output logic high voltage for SPI (S)

variant

0.5 mA source from SDO, V_nSLEEP

3.3 V, V_VM> 5 V

=

V_{OH_SDO}

Output logic high voltage for SPI (P)

variant

0.5 mA source from SDO, V_VDD= 5 V

No current from SDO, V_nSLEEP= 5 V,

V_VM> 7 V

5.5

3.8

Output logic high voltage at no load on

SDO, valid only for SPI (S) variant

V_{OH_SDO_NL}

No current from SDO, V_nSLEEP= 3.3 V,

V_VM> 5 V

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7.5.4 Configuration Pins - HW Variant Only

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

6 level setting for ITRIP, SR and DIAG

Connect to GND

R_LVL1OF6

R_LVL2OF6

R_LVL3OF6

R_LVL4OF6

R_LVL5OF6

R_LVL6OF6

Level 1 of 6

Level 2 of 6

Level 3 of 6

Level 4 of 6

Level 5 of 6

Level 6 of 6

10

9

Ω

+/- 10% resistor to GND

Hi-Z (no connect)

7.4

19.8

42.3

90

8.2

22

KΩ

24.2

51.7

110

47

100

250

3 level setting for MODE

Connect to GND

R_LVL1OF3

R_LVL2OF3

R_LVL3OF3

Level 1 of 3

Level 2 of 3

Level 3 of 3

10

9

Ω

+/- 10% resistor to GND

Hi-Z (no connect)

7.4

8.2

KΩ

100

7.5.5 Power FET Parameters

Measured at V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

38

UNIT

mΩ

I_OUT= 6 A, T_J= 25°C

I_OUT= 6 A, T_J= 150°C

I_OUT= 6 A, T_J= 25°C

I_OUT= 6 A, T_J= 150°C

I_OUT= 6 A, T_J= 25°C

I_OUT= 6 A, T_J= 150°C

I_OUT= 6 A, T_J= 25°C

I_OUT= 6 A, T_J= 150°C

20

High-side FET on resistance, HTSSOP

package

R_{HS_ON}

16

20

16

High-side FET on resistance, VQFN-HR

package

30.4

38

Low-side FET on resistance, HTSSOP

package

R_{LS_ON}

Low-side FET on resistance, VQFN-HR

package

30.4

1.5

Low-side & High-side FET source-drain

voltage when body diode is forward

biased

V_SD

I_OUT= +/- 6 A (both directions)

V_OUTx= V_VM= 13.5 V

0.4

1

0.9

V

OUT resistance to GND in SLEEP or

STANDBY state

R_Hi-Z

10

KΩ

7.5.6 Switching Parameters with High-Side Recirculation

Load = 1.5mH / 4.7 Ohm, V_VM= 13.5 V, refer high-side recirculation waveform

PARAMETER

TEST CONDITIONS

MIN

TYP

1.5

5

MAX

UNIT

V/µs

SR = 3'b000 or LVL2

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

SR = 3'b011 or LVL3

SR = 3'b100 or LVL4

SR = 3'b101 or LVL1

SR = 3'b110 or LVL6

SR = 3'b111 or LVL5

9.8

14

20

26

38

50

SR_LSOFFOutput voltage rise time, 10% - 90%

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PARAMETER

TEST CONDITIONS

SR = 3'b000 or LVL2

MIN

TYP

1.1

0.9

0.8

0.7

0.6

0.5

0.9

1.5

5

MAX

UNIT

µs

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

SR = 3'b011 or LVL3

µs

Propagation time during output voltage

t_{PD_LSOFF}

rise

µs

SR = 3'b100 & 3'b101 or LVL4 & LVL1

SR = 3'b110 & 3'b111 or LVL6 & LVL5

All SRs

µs

t_{DEAD_LSOFF}Dead time during output voltage rise

µs

SR = 3'b000 or LVL2

V/µs

µs

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

SR = 3'b011 or LVL3

9.8

14

SR_LSON

Output voltage fall time, 90% - 10%

SR = 3'b100 or LVL4

20

SR = 3'b101 or LVL1

26

SR = 3'b110 or LVL6

38

SR = 3'b111 or LVL5

50

SR = 3'b000 or LVL2

0.2

0.4

0.3

0.2

1.5

0.6

0.85

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

SR = 3'b011 or LVL3

µs

Propagation time during output voltage

fall

t_{PD_LSON}

µs

SR = 3'b100 or 3'b101 or LVL4 or LVL1

SR = 3'b110 or 3'b111 or LVL6 or LVL5

SR = 3'b000 or LVL2

µs

t_{DEAD_LSON}Dead time during output voltage fall

SR = 3'b001 or 3'b010 (SPI only)

All other SRs

µs

Output voltage rise and fall slew rate

Match_SRLS

matching

All SRs

-20

+20

%

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7.5.7 Switching Parameters with Low-Side Recirculation

Load = 1.5 mH / 4.7 Ohm, V_VM= 13.5 V, refer low-side recirculation waveform

Note

Slew rate setting (LVL2) for DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) is NOT

available for use - recommend to use other settings for slew rate control

PARAMETER

TEST CONDITIONS

MIN

TYP

10

MAX

UNIT

V/µs

µs

SR_HSON

Output voltage rise time, 10% - 90%

All SRs

SR = 3'b000 or LVL2

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

SR = 3'b011 or LVL3

All other SRs

4.2

2

µs

Propagation time during output voltage

rise

t_{PD_HSON}

1.5

1.2

0.9

1.5

1

µs

SR = 3'b000 or LVL2

SR = 3'b001 (SPI only)

SR = 3'b010 (SPI only)

All other SRs

µs

t_{DEAD_HSON}Dead time during output voltage rise

0.8

0.5

µs

SR = 3'b000 or 3'b001 or 3'b010 or

LVL2

42

V/µs

SR = 3'b011 or LVL3

SR = 3'b100 or LVL4

SR = 3'b101 or LVL1

SR = 3'b110 or LVL6

SR = 3'b111 or LVL5

15

20

26

37

48

V/µs

SR_HSOFFOutput voltage fall time, 90% - 10%

Propagation time during output voltage

fall

t_{PD_HSOFF}

All SRs

0.25

0.2

µs

t_{DEAD_HSOFF}Dead time during output voltage fall

Current regulation blanking time after

t_BLANK

OUT slewing for current sense output to All SRs

settle (Valid for only for LS recirculation)

3.4

µs

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7.5.8 IPROPI & ITRIP Regulation

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current scaling factor, HTSSOP package

6150

A/A

A_IPROPI

Current scaling factor, VQFN-HR

package

6400

A/A

I_OUT> 2 A, measured up to 10.9 A

I_OUT= 0.5 A to 2 A

-5

+5

%

A_{I_ERR}

Current scaling factor

-20

-50

+20

+50

I_OUT= 0.2 A to 0.5 A

Current matching between the two half-

bridges

A_{I_ERR_M}

Offset_IPROPI

BW_IPROPI

I_OUT> 2 A

-2

+2

15

%

µA

Offset current on IPROPI at no load

current

I_OUT= 0 A

Bandwidth of the IPROPI internal sense

circuit

No external capacitor on IPROPI.

400

KHz

V_{IPROPI_LIM}Internal clamping voltage on IPROPI

5

5.5

1.3

V

ITRIP = 3'b001 or LVL2

ITRIP = 3'b010 (SPI only)

ITRIP = 3'b011 (SPI only)

ITRIP = 3'b100 or LVL3

ITRIP = 3'b101 or LVL4

ITRIP = 3'b110 or LVL5

ITRIP = 3'b111 or LVL6

TOFF = 2'b00 (SPI only)

1.06

1.27

1.49

1.78

2.08

2.38

2.67

16

1.18

1.41

1.65

1.98

2.31

2.64

2.97

20

1.55

1.82

2.18

2.54

2.9

V

Voltage limit on V_IPROPIto trigger TOFF

V_{ITRIP_LVL}

V

cycle for ITRIP regulation

V

3.27

25

V

µs

TOFF = 2'b01 (SPI). Only choice for

HW

24

30

36

µs

t_OFF

ITRIP regulation - off time

TOFF = 2'b10 (SPI only)

TOFF = 2'b11 (SPI only)

33

41

40

50

48

61

µs

7.5.9 Over Current Protection (OCP)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OCP_SEL = 2'b00 (SPI), Only choice

for HW

32

64

A

Over current protection threshold on the

I_{OCP_HS}

high side

OCP_SEL = 2'b10 (SPI only)

OCP_SEL = 2'b01 (SPI only)

24

16

49

34

A

OCP_SEL = 2'b00 (SPI), Only choice

for HW

32

64

A

Over current protection threshold on the

I_{OCP_LS}

low side

OCP_SEL = 2'b10 (SPI only)

OCP_SEL = 2'b01 (SPI only)

24

16

49

34

A

TOCP_SEL = 2'b00 (SPI), Only choice

for HW

Over current protection deglitch time

4.5

6

7.3

µs

Over current protection deglitch time

TOCP_SEL = 2'b01 (SPI only)

TOCP_SEL = 2'b10 (SPI only)

TOCP_SEL = 2'b11 (SPI only)

2.2

1.1

3

4.1

2.3

0.4

µs

t_OCP

1.5

0.2

0.15

7.5.10 Over Temperature Protection (TSD)

PARAMETER

TEST CONDITIONS

MIN

TYP

170

30

MAX

UNIT

°C

T_TSD

T_HYS

t_TSD

Thermal shutdown temperature

Thermal shutdown hysteresis

Thermal shutdown deglitch time

155

185

°C

10

12

19

µs

18

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7.5.11 Voltage Monitoring

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VMOV_SEL = 2'b00 (SPI), Only choice

in HW variant

33.6

37

V

V_VMOV

VM over voltage threshold while rising

VMOV_SEL = 2'b01 (SPI only)

VMOV_SEL = 2'b10 (SPI only)

28

18

31

21

V

V_{VMOV_HYS}VM over voltage hysteresis

0.6

12

V

t_VMOV

VM over voltage deglitch time

10

19

µs

V

V_VMUV

VM under voltage threshold while falling

4.2

4.5

V_{VMUV_HYS}VM under voltage hysteresis

200

12

mV

µs

t_VMUV

VM under voltage deglitch time

10

19

VM voltage at which device goes into

POR

VM_{POR_FALL}

Applicable for HW & SPI (S) variant

Applicable for SPI (P) variant

3.6

V

VM voltage at which device comes out of

POR

VM_{POR_RISE}

3.9

3.5

3.8

VDD_{POR_FAL}VDD voltage at which device goes into

POR

L

VDD_{POR_RIS}VDD voltage at which device comes out

Applicable for SPI (P) variant

of POR

E

7.5.12 Load Monitoring

Note

The Off-state diagnostics (OLP) feature in DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16)

package) is NOT available for use - recommend to disable this feature (Set DIAG pin to LVL1 or

LVL5).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Off-state diagnostics (OLP)

Resistance on OUT to GND that will be

detected as short, All modes

R_{S_GND}

R_{S_VM}

1

KΩ

Resistance on OUT to VM that will be

detected as short , All modes

Resistance between OUTx that will be

detected as open, PH/EN or PWM mode

R_{OPEN_FB}

R_{OPEN_LS}

R_{OPEN_HS}

1.5

2

Resistance on OUT to GND that will be

detected as open , Independent mode

Valid for low-side load

Resistance on OUT to VM that will be

detected as open, Independent mode

Valid for high-side load, V_VM= 13.5 V

10

V_{OLP_REFH}OLP Comparator Reference High

V_{OLP_REFL}OLP Comparator Reference Low

2.65

2

V

Internal pull-up resistance on OUT to

VDD during OLP

R_{OLP_PU}

V_OUTx= V_{OLP_REFH}+ 0.1V

V_OUTx= V_{OLP_REFL}- 0.1V

1

KΩ

Internal pull-down resistance on OUT to

GND during OLP

R_{OLP_PD}

SPI variant only - On-state diagnostics (OLA)

Internal sink current on OUT to

I_{PD_OLA}

GND during dead-time in high-side

recirculation

3

8

mA

V

Comparator Reference with respect to

VM used for OLA

V_{OLA_REF}

0.25

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7.5.13 Fault Retry Setting

Refer to retry setting waveform

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RETRY

Automatic driver retry time

Fault reaction set to RETRY

4.1

5

6.1

ms

Fault free operation time to auto-clear

from over current event

t_CLEAR

Fault reaction set to RETRY

85

200

6.7

µs

Fault free operation time to auto-clear

from over temperature event

t_{CLEAR_TSD}

4.2

ms

7.5.14 Transient Thermal Impedance & Current Capability

Information based on thermal simulations

Table 7-1. Transient Thermal Impedance (R_θJA) and Current Capability - full-bridge

Current [A]⁽²⁾

R_θJA[°C/W]⁽¹⁾

PACKA

GE

PART NUMBER

without PWM⁽³⁾

with PWM⁽⁴⁾

0.1 sec

4.3

1 sec

9.2

10 sec

13.6

DC

30.3

29.1

0.1 sec

15.8

1 sec

10.8

11.0

10 sec

8.9

DC

5.9

5.4

10 sec

7.7

DC

4.8

4.5

VQFN-

HR

DRV8245-Q1

HTSSOP

3.3

7.1

12.2

16.1

8.4

7.4

(1) Based on thermal simulations using 40 mm x 40 mm x 1.6 mm 4 layer PCB – 2 oz Cu on top and bottom layers, 1 oz Cu on internal

planes with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 minimum mm via pitch.

(2) Estimated transient current capability at 85 °C ambient temperature for junction temperature rise up to 150°C

(3) Only conduction losses (I²R) considered

(4) Switching loss roughly estimated by the following equation:

P_SW= V_VMx I_Loadx f_PWMx V_VM/SR, where V_VM= 13.5 V, f_PWM= 20 KHz, SR = 23 V/µs

(1)

7.6 SPI Timing Requirements

MIN

NOM

MAX

UNIT

ns

t_SCLK

SCLK minimum period⁽¹⁾

SCLK minimum high time

SCLK minimum low time

SDO minimum high time

nSCS input setup time

nSCS input hold time

100

50

t_SCLKH

t_SCLKL

ns

50

ns

t_{HI_nSCS}

t_{SU_nSCS}

t_{H_nSCS}

t_{SU_SDI}

t_{H_SDI}

300

25

ns

25

ns

SDI input data setup time

SDI input data hold time

SDO enable delay time⁽¹⁾

SDO disable delay time⁽¹⁾

25

ns

25

ns

t_{EN_SDO}

t_{DIS_SDO}

35

ns

100

ns

(1) SPI (S) variant: SDO delay times are valid only with SDO external load of 5 pF. With a 20 pF load on SDO, there is an additional

delay on SDO, which results in a 25% increase in SCLK minimum time, limiting the SCLK to a maximum of 8 MHz. There is NO such

limitation for the SPI (P) variant.

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t_{HI_nSCS}

t_{H_nSCS}

t_{SU_nSCS}

nSCS

t_SCLK

SCLK

t_SCLKH

t_SCLKL

DON’T CARE

X

DON’T CARE

X

LSB

MSB

SDI

t_{SU_SDI}

t_{H_SDI}

t_{DIS_SDO}

HZI-Z

LSB

Z

HI-Z

SDO

MSB

t_{EN_SDO}

Write Command

executed by device

SDI capture point

SDO propogate point

Figure 7-1. SPI Peripheral-Mode Timing Definition

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7.7 Switching Waveforms

This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP

regulation.

7.7.1.1 High-Side Recirculation

LOAD

1, 2

LOAD

4, 5, 6

LOAD

3

7

8, 1

1

2

3

4

5

6

7

8

1

Isense OK

t_{DEAD_LSOFF}

t_{DEAD_LSON}

VM + VD(FET BODY DIODE)

VM

OUT1

OUT2

90%

~SR_HSOFF

t_{PD_LSON}

90%

~SR_HSON

Accuracy not

applicable

High side recircula on

Slew rate controlled by Low Side Driver (SR_LSON& SR_LSOFF

SR_LSON

SR_LSOFF

)

10%

GND

t_{PD_LSOFF}

“fPWM” @ duty cycle “D”

EN/IN1

PH/IN2

E.g. Full bridge in PH/EN mode, OUT1 is held high, while OUT2 is switching

Figure 7-2. Output Switching Transients for a H-Bridge with High-Side Recirculation

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LOAD

1, 2

LOAD

4, 5, 6

LOAD

3

7

8, 1

1

2

3

4

5

6

7

8

1

Isense NOT OK

t_{DEAD_LSOFF}

t_{DEAD_LSON}

VM + VD(FET BODY DIODE)

VM

90%

~SR_HSOFF

t_{PD_LSON}

90%

~SR_HSON

Accuracy not

applicable

High side recircula on

Slew rate controlled by Low Side Driver (SR_LSON& SR_LSOFF

)

SR_LSON

SR_LSOFF

10%

OUT1

IN1

GND

t_{PD_LSOFF}

“fPWM” @ duty cycle “1-D”

E.g. High side load in Independent mode, OUT1 is switching

Figure 7-3. Output Switching Transients for a Half-Bridge with High-Side Recirculation

7.7.1.2 Low-Side Recirculation

LOAD

4, 5, 6

LOAD

8, 1

1, 2

3

7

1

2

3

4

5

6

7

8

1

Isense OK

Isense NOT OK

VM

Isense OK

OUT1

90%

t_BLANK

t_{PD_HSOFF}

Low side recircula on

SR_HSOFF

SR_HSON

Slew rate controlled by High Side Driver (SR_HSON& SR_HSOFF

)

10%

~SR_LSOFF

~SR_LSON

Accuracy not applicable

GND

GND - VD(FET BODY DIODE)

t_{DEAD_HSOFF}

t_{DEAD_HSON}

t_{PD_HSON}

“fPWM” @ duty cycle “D”

IN1

E.g. Low side load in Independent mode, OUT1 is switching

Figure 7-4. Output Switching Transients for a half-bridge with Low-Side Recirculation

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7.7.2 Wake-up Transients

7.7.2.1 HW Variant

t_RESET

t_WAKEUP

t_READY

nSLEEP

t_COM

nFAULT

nSLEEP RESET

pulse ACK

Figure 7-5. Wake-up from SLEEP State to STANDBY State Transition for HW Variant

Hand shake between controller and device during wake-up as follows:

•

t0: Controller - nSLEEP asserted high to initiate device wake-up

t1: Device internal state - Wake-up command registered by device (end of Sleep state)

t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication

t3: Device internal state - Initialization complete

t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device wake-up

t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

t_READY

VM

V_{VMUV_HYST}

V_VMUV

VM_{POR_RISE}

VM_{POR_FALL}

Internal

nPOR

t_RESET

nSLEEP=

1'b1

t_COM

nFAULT

nSLEEP RESET

pulse ACK

Figure 7-6. Power-up to STANDBY State Transition for HW Variant

Hand shake between controller and device during power-up as follows:

•

t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)

t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage

t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication

t3: Device internal state - Initialization complete

t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device power-up

t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

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7.7.2.2 SPI Variant

CLR_FLT

cmd

t_WAKEUP

t_READY

nSLEEP

nFAULT

t_COM

CLR_FLT

cmd ACK

Figure 7-7. Wake-up from SLEEP State to STANDBY State Transition for SPI (S) Variant

Hand shake between controller and device during a wake-up transient as follows:

•

t0: Controller - nSLEEP asserted high to initiate device wake-up

t1: Device internal state - Wake-up command registered by device (end of Sleep state)

t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication

t3: Device internal state - Initialization complete

t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wake-up

t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

t_READY

VM

CLR_FLT

cmd

V_{VMUV_HYST}

V_VMUV

VM_{POR_RISE}

VM_{POR_FALL}

Internal

nPOR

nSLEEP=

1'b1

t_COM

nFAULT

CLR_FLT

cmd ACK

Figure 7-8. Power-up to STANDBY State Transition for SPI (S) Variant

Hand shake between controller and device during power-up as follows:

•

t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)

t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage

t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication

t3: Device internal state - Initialization complete

t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up

t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

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t_READY

VDD

CLR_FLT

cmd

VDD_{POR_RISE}

VDD_{POR_FALL}

Internal

nPOR

t_COM

nFAULT

CLR_FLT

cmd ACK

Figure 7-9. Power-up to STANDBY State Transition for SPI (P) Variant

Hand shake between controller and device during power-up as follows:

•

t0: Device internal state - POR asserted based on under voltage on VDD (external supply)

t1: Device internal state – POR de-asserted based on recovery of voltage on VDD (external supply)

t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication

t3: Device internal state - Initialization complete

t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up

t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

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7.7.3 Fault Reaction Transients

7.7.3.1 Retry setting

Valid for both SPI and HW variants

t_CLEAR

nFAULT

t_OCP

I_OCP

t_RETRY

I(VM)

I_VMQ

I_LOAD

External short to ground fault

Figure 7-10. Fault reaction with RETRY setting (shown for OCP occurrence on high-side when OUT is

shorted to ground)

Short occurrence and recovery scenario with RETRY setting:

•

t1: An external short occurs.

t2: OCP (Over Current Protection) fault confirmed after t_OCP, output disabled, nFAULT asserted low to

indicate fault.

•

t3: Device automatically attempts retry (auto retry) after t_RETRY. Each time output is briefly turned on to

confirm short occurrence and then immediately disabled after t_OCP. nFAULT remains asserted low through

out. Cycle repeats till driver is disabled by the user or external short is removed, as illustrated further. Note

that, in case of a TSD (Thermal Shut Down) event, automatic retry time depends on the cool off based on

thermal hysteresis.

•

t4: The external short is removed.

t5: Device attempts auto retry. But this time, no fault occurs and device continues to keep the output enabled.

t6: After a fault free operation for a period of t_CLEARis confirmed, nFAULT is de-asserted.

SPI variant only – Fault status remains latched till a CLR_FLT command is issued.

Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will

continue to be pulled up to V_{IPROPI_LIM}voltage to indicate this type of short, while the output is disabled. This

is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other

faults.

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7.7.3.2 Latch setting

Valid for both SPI and HW variants

CLR_FLT CMD (SPI) /

nSLEEP RESET PULSE (HW)

nFAULT

t_OCP

I_OCP

I(VM)

I_LOAD

I_VMQ

External short to ground fault

Figure 7-11. Fault reaction with Latch setting (shown for OCP occurrence on high-side when OUT is

shorted to ground)

Short occurrence and recovery scenario with LATCH setting:

•

t1: An external short occurs.

t2: OCP (Over Current Protection) fault confirmed after t_OCP, output disabled, nFAULT asserted low to

indicate fault.

•

t3: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT

is de-asserted and output is enabled. OCP fault is detected again and output is disabled with nFAULT

asserted low.

•

t4: The external short is removed.

t5: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT

is de-asserted and output is enabled. Normal operation resumes.

SPI variant only – Fault status remains latched till a CLR_FLT command is issued.

•

Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will

continue to be pulled up to V_{IPROPI_LIM}voltage to indicate this type of short, while the output is disabled. This

is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other

faults.

7.8 Typical Characteristics

17

16.5

16

6325

6320

6315

6310

6305

6300

6295

6290

6285

6280

6275

6270

6265

6260

6255

6250

LS1

LS2

HS1

HS2

15.5

15

14.5

14

13.5

13

12.5

12

-40 -20

0

20

40

60

80 100 120 140 160

-40 -30 -20 -10

0

10

20

30

40

50

60

Temperature [C]

Figure 7-13. A_IPROPIGain vs Temperature at V_VM

13.5 V

=

Figure 7-12. R_{HS_ON}& R_{LS_ON}for VQFN-HR(16) vs

Temperature at V_VM= 13.5 V

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50

46

44

42

40

38

36

34

32

30

28

26

24

22

45

40

35

30

25

OCP_SEL = 0

OCP_SEL = 2

OCP_SEL = 1

OCP_SEL = 0

OCP_SEL = 2

OCP_SEL = 1

20

40

60

80

100

120

140

160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature [C]

Figure 7-14. LS OCP Threshold vs Temperature at Figure 7-15. HS OCP Threshold vs Temperature at

V_VM= 13.5 V V_VM= 13.5 V

3.75

3.5

6.5

6

VM 5V

VM 13.5V

VM 25V

VM 35V

5.5

5

3.25

3

4.5

4

2.75

2.5

3.5

3

VM 5V

2.25

2

VM 13.5V

VM 25V

VM 35V

2.5

2

1.5

1

1.75

1.5

0.5

0

-40 -20

1.25

-40 -20

0

20

40

60

80 100 120 140 160

0

20

40

60

80 100 120 140 160

Temperature [C]

Figure 7-16. Current on VM in STANDBY state vs

Temperature

Figure 7-17. Current on VM in SLEEP state vs

Temperature

100

SR = 3'b000

SR = 3'b001

SR = 3'b000

SR = 3'b001

90

SR = 3'b010

80

SR = 3'b010

80

SR = 3'b011

SR = 3'b100

SR = 3'b101

SR = 3'b110

SR = 3'b111

SR = 3'b100

SR = 3'b101

SR = 3'b110

SR = 3'b111

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Input Duty Cycle [%] on EN/IN1 pin at 5 KHz PWM

Input Duty Cycle [%] on EN/IN1 pin at 20 KHz PWM

Figure 7-18. Measured Duty Cycle vs Input Duty

Figure 7-19. Measured Duty Cycle vs Input Duty

Cycle at PWM frequency of 5 KHz at V_VM= 13.5 V Cycle at PWM frequency of 20 KHz at V_VM= 13.5 V

for HS recirculation

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8 Detailed Description

8.1 Overview

The DRV824x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 35-V supporting a

wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge

output power stage that can be operated in different control modes set by the MODE function. This allows for

driving a single bidirectional brushed DC motor or two unidirectional brushed DC motors. The devices integrate

a charge pump regulator to support efficient high-side N-channel MOSFETs with 100% duty cycle operation.

The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC

voltage supply. The devices also provide a low power mode to minimize current draw during system inactivity.

The devices are available in two interface variants -

1. HW variant - Hardwired interface variant is available for easy device configuration. Due to the limited number

of available pins in the device, this variant offers fewer configuration and fault reporting capability compared

to the SPI variant.

2. SPI variant - A standard 4-wire serial peripheral interface (SPI) with daisy chain capability allows flexible

device configuration and detailed fault reporting to an external controller. The feature differences of the SPI

and HW variants can be found in the device comparison section. The SPI interface is available in two device

variant choices, as stated below:

a. SPI (S) variant - The power supply for the digital block is provided by an internal LDO regulator sourced

from VM supply. The nSLEEP pin is a high impedance input pin.

b. SPI (P) variant - This allows for an external supply input to the digital block of the device through a VDD

pin. The nSLEEP pin is replaced by this VDD supply pin. This prevents device reset (brown out) during a

VM under voltage condition.

The DRV824x family of devices provide a load current sense output using current mirrors on the high-side

power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the high-side

MOSFETs (current sourced out of the OUTx pin). This current can be converted to a proportional voltage using

an external resistor (R_IPROPI). Additionally, the devices also support a fixed off-time PWM chopping scheme for

limiting current to the load. The current regulation level can be configured through the ITRIP function.

A variety of protection features and diagnostic functions are integrated into the device. These include supply

voltage monitors (VMOV & VMUV), , off-state (Passive) diagnostics (OLP), on-state (Active) diagnostics (OLA) -

SPI variant only, overcurrent protection (OCP) for each power FET and over-temperature shutdown (TSD). Fault

conditions are indicated on the nFAULT pin. The SPI variant has additional communication protection features

such as frame errors and lock features for configuration register bits and driver control bits.

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8.2 Functional Block Diagram

8.2.1 HW Variant

High Side load to VM

(Independent mode)

Low Side load to GND

(Independent mode)

Full Bridge load

(PH/EN or PWM mode)

VM

PSM

Gate Driver

V_VCP

VCP

ISNS1

0.1 μF

Charge

Pump

HS

VDD

OUT1

GND

Internal

LDO & Bias

GND

V_DD

Supply

Monitors

LS

VDD

Oscillator

DRVOFF

nSLEEP

Thermal Shut Down (TSD)

Over Current Protection (OCP)

Off-state Diagnostics (OLP)

VM

Digital IOs

EN/IN1

PH/IN2

Gate Driver

ISNS2

V_VCP

HS

OUT2

V_DD

MODE

LS

ITRIP

SR

GND

Impedance

Estimator

R_nFAULT

nFAULT

IPROPI

DIAG

ISNS1

ISNS2

R_IPROPI

Figure 8-1. Functional Block Diagram - HW Variant

8.2.2 SPI Variant

There are two variants for the SPI interface - SPI (S) variant and SPI (P) variant as shown below.

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High Side load to VM

(Independent mode)

Low Side load to GND

(Independent mode)

Full Bridge load

(PH/EN or PWM mode)

VM

PSM

Gate Driver

VCP

ISNS1

V_VCP

0.1 μF

Charge

Pump

HS

VDD

OUT1

GND

Internal

LDO & Bias

GND

V_DD

Supply

Monitors

LS

VDD

Oscillator

DRVOFF

Thermal Shut Down (TSD)

Over Current Protection (OCP)

Load Diagnostics (OLP & OLA)

nSLEEP

EN/IN1

VM

Gate Driver

ISNS2

V_VCP

PH/IN2

HS

VDD

OUT2

V_DD

Digital IOs

nSCS

LS

GND

SDI

R_nFAULT

nFAULT

IPROPI

SCLK

SDO

ISNS1

ISNS2

R_IPROPI

Figure 8-2. Functional Block Diagram - SPI (S) Variant

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High Side load to VM

(Independent mode)

Low Side load to GND

(Independent mode)

Full Bridge load

(PH/EN or PWM mode)

VM

PSM

Gate Driver

VCP

ISNS1

V_VCP

0.1 μF

Charge

Pump

HS

VDD

OUT1

GND

Internal

LDO & Bias

GND

V_DD

Supply

Monitors

LS

VDD

Oscillator

DRVOFF

nSLEEP

Thermal Shut Down (TSD)

Over Current Protection (OCP)

Load Diagnostics (OLP & OLA)

VM

EN/IN1

PH/IN2

Gate Driver

ISNS2

V_VCP

HS

VDD

OUT2

V_DD

Digital IOs

nSCS

SDI

LS

GND

R_nFAULT

nFAULT

IPROPI

SCLK

SDO

ISNS1

ISNS2

R_IPROPI

Figure 8-3. Functional Block Diagram - SPI (P) Variant

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8.3 Feature Description

8.3.1 External Components

Section 8.3.1.1 and Section 8.3.1.2 contain the recommended external components for the device.

8.3.1.1 HW Variant

Table 8-1. External Components Table for HW Variant

Component

Recommendation

C_VM1

VM

0.1 µF, low ESR ceramic capacitor to GND rated for VM

Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the

section on bulk capacitor sizing.

C_VM2

VM

Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.

Pin can be shorted to GND if ITRIP and IPROPI function is not needed.

R_IPROPI

C_IPROPI

IPROPI

Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over

Current Protection (OCP) section.

R_nFAULT

R_MODE

R_SR

nFAULT

MODE

SR

Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply.

Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer MODE table.

Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer SR section.

Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer ITRIP table.

Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer DIAG section.

R_ITRIP

R_DIAG

ITRIP

DIAG

8.3.1.2 SPI Variant

Table 8-2. External Components Table for SPI Variant

Component

Recommendation

C_VM1

VM

0.1 µF, low ESR ceramic capacitor to GND rated for VM

Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the

section on bulk capacitor sizing.

C_VM2

VM

Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.

Pin can be shorted to GND if ITRIP and IPROPI function is not needed.

R_IPROPI

C_IPROPI

R_nFAULT

C_VDD

IPROPI

Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over

Current Protection (OCP) section.

Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply. If nFAULT signaling is not

used, this pin can be short to GND or left open.

nFAULT

VDD

0.1 µF, 6.3 V, low ESR ceramic capacitor to GND. This is applicable for the SPI (P) variant only.

8.3.2 Bridge Control

The DRV824x-Q1 family of devices provides three separate modes to support different control schemes with the

EN/IN1 and PH/IN2 pins. The control mode is selected through the MODE setting. MODE is a 3-level setting

based on the MODE pin for the HW variant or S_MODE bits in the CONFIG3 register for the SPI variant as

summarized in Table 8-3:

Table 8-3. Mode table

MODE pin

R_LVL1OF3

R_LVL2OF3

R_LVL3OF3

S_MODE bits

2'b00

Device Mode

Description

full-bridge mode where EN/IN1 is the PWM input,

PH/EN2 is the direction input

PH/EN mode

2'b01

Independent mode

PWM mode

Independent control for 2 half-bridges

full-bridge mode where EN/IN1 and PH/EN2 control

the PWM respectively depending on the direction

2'b10, 2b'11

In the HW variant, MODE pin is latched during device initialization following power-up or wake-up from sleep.

Update during operation is blocked.

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In the SPI variant of the device, the mode setting can be changed anytime the SPI communication is available by

writing to the S_MODE bits. This change is immediately reflected.

The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive

modes. The device input pins can be powered before VM is applied. By default, the nSLEEP and DRVOFF

pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are

present. Both the EN/IN1 and PH/IN2 pins also have internal pull down resistors. The sections below show the

truth table for each control mode.

The device automatically generates the optimal dead-time needed during transitioning between the high-side

and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage

feedback. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no

shoot-through current.

Note

1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to -

Register - Pin control.

2. For the SPI (P) variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin.

Internally, nSLEEP = 1, always. The control table is valid when VDD > VDD_PORlevel.

8.3.2.1 PH/EN mode

In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 is the PWM input and

PH/IN2 is the direction input. For load illustration, refer the Load Summary section.

Table 8-4. Control table - PH/EN mode

nSLEEP

DRVOFF

EN/IN1

PH/IN2

OUT1

OUT2

IPROPI

Device State

SLEEP

0

1

X

1

0

X

0

1

0

1

0

1

X

0

1

X

0

1

Hi-Z

No current

Hi-Z

STANDBY

Refer Off-state diagnostics table

No current

STANDBY

H

L⁽²⁾

H

ISNS1 or ISNS2⁽¹⁾

ISNS2

ACTIVE

L⁽²⁾

ISNS1

(1) Current sourcing out of the device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time

8.3.2.2 PWM mode

In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 provides the PWM input

in one direction, while PH/IN2 provides the PWM in the other direction. For load illustration, refer the Load

Summary section.

Table 8-5. Control table - PWM mode

nSLEEP

DRVOFF

EN/IN1

PH/IN2

OUT1

OUT2

IPROPI

No current

ISNS1 or ISNS2⁽¹⁾

ISNS2

Device State

SLEEP

0

1

X

1

0

X

0

1

0

1

0

1

X

0

1

0

1

0

Hi-Z

STANDBY

ACTIVE

Refer Off-state diagnostics table

H

L⁽²⁾

H

ACTIVE

L⁽²⁾

ISNS1

ACTIVE

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Table 8-5. Control table - PWM mode (continued)

nSLEEP

DRVOFF

EN/IN1

PH/IN2

OUT1

OUT2

IPROPI

Device State

STANDBY

1

0

1

Hi-Z

No current

(1) Current sourcing out of device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time

For the SPI variant, by setting the PWM_EXTEND bit in the CONFIG2 register, there are additional Hi-Z states

that are possible, when a forward ([EN/IN1 PH/IN2] = [1 0]) or reverse ([EN/IN1 PH/IN2] = [0 1]) command is

followed by a Hi-Z command ([EN/IN1 PH/IN2] = [1 1]). In this condition of Hi-Z (coasting), only the half-bridge

involved with the PWM is Hi-Z, while the HS FET on the other half-bridge is kept ON. The determination on

which half-bridge to Hi-Z is made based on the previous cycle. This is summarized in Table 8-6.

Table 8-6. PWM EXTEND table (PWM_EXTEND bit = 1'b1)

PREVIOUS STATE

CURRENT STATE

Device State Transition

OUT1

OUT2

Hi-Z

H

OUT1

Hi-Z

H

OUT2

Hi-Z

H

IPROPI

No current

ISNS2

Hi-Z

H

Remains in STANDBY, no change

ACTIVE to STANDBY

L

H

ACTIVE to STANDBY

H

L

Hi-Z

ISNS1

ACTIVE to STANDBY

Note

For the pre-production samples, the truth table is modified as shown in Table 8-7:

Table 8-7. Control Table Differences - PWM Mode in Pre-Production Samples

nSLEEP

DRVOFF

EN/IN1

PH/IN2

OUT1

OUT2

IPROPI

ISNS1 or ISNS2

No current

Device State

ACTIVE

1

0

1

0

1

0

H

Hi-Z

STANDBY

With this change, as an example, the PWM cycle for a forward → brake (HS recirculation) → forward, inputs will

be as follows:

•

Pre-production samples: [EN/IN1 PH/IN2] = [1 0] → [1 1] → [1 0]

Final product: [EN/IN1 PH/IN2] = [1 0] → [0 0] → [1 0]

8.3.2.3 Independent mode

In this mode, the two half-bridges are configured to be used as two independent half-bridges. The Table 8-8

shows the logic table for bridge control. For load illustration, refer the Load Summary section.

Table 8-8. Control table - Independent mode

nSLEEP

DRVOFF

EN/IN1

PH/IN2

OUT1

OUT2

IPROPI

No current

ISNS2⁽¹⁾

Device State

SLEEP

0

1

X

1

0

X

0

1

0

1

0

1

X

0

1

0

1

0

1

Hi-Z

STANDBY

ACTIVE

Refer Off-state diagnostics table

L

H⁽²⁾

ACTIVE

H⁽²⁾

L

ISNS1⁽¹⁾

ACTIVE

H⁽²⁾

ISNS1 + ISNS2⁽¹⁾

ACTIVE

For the SPI variant, it is possible to have independent Hi-Z control of both half-bridges through equivalent bits,

S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 8-9

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shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control

for details on the combined inputs shown in Table 8-9.

Table 8-9. Control table - Independent mode for SPI variant, when SPI_IN is unlocked

DRVOFF1 DRVOFF2 EN_IN1

combined combined combined combined

PH_IN2

nSLEEP

OUT1

OUT2

IPROPI

Device State

0

1

X

1

0

X

1

0

1

0

X

0

1

0

1

X

0

1

0

1

X

0

1

0

1

X

0

1

0

Hi-Z

No current

ISNS2⁽¹⁾

SLEEP

STANDBY

ACTIVE

Refer Off-state diagnostics table

Hi-Z

L

H⁽²⁾

Hi-Z

L

ACTIVE

No current

ISNS1⁽¹⁾

ACTIVE

H⁽²⁾

ACTIVE

L

No current

ISNS2⁽¹⁾

ACTIVE

L

H⁽²⁾

ACTIVE

H⁽²⁾

L

ISNS1⁽¹⁾

ACTIVE

ISNS1 +

ISNS2⁽¹⁾

1

0

1

H⁽²⁾

ACTIVE

(1) Current sourcing out of device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time

In this mode, the device behavior is as listed below:

•

Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for

high-side loads

•

The current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the

ITRIP current regulation feature as a combined current regulation, rather than as truly independent.

Slew rate configurability is limited for low-side recirculation (low-side loads)

Active state open load diagnostics (OLA) is possible only for high-side loads

For the HW variant, it is NOT possible to have independent Hi-Z control of each half-bridge. Asserting

DRVOFF pin high will Hi-Z both the half-bridges.

•

8.3.2.4 Register - Pin Control - SPI Variant Only

The SPI variant allows control of the bridge through the specific register bits, S_DRVOFF, S_DRVOFF2,

S_EN_IN1, S_PH_IN2 in the SPI_IN register, provided the SPI_IN register has been unlocked. The user

can unlock this register by writing the right combination to the SPI_IN_LOCK bits in the COMMAND register.

Additionally, the user can configure between an AND / OR logic combination of each of external input pin with

their equivalent register bit in the SPI_IN register. This logical configuration is done through the equivalent

selects bits in the CONFIG4 register:

•

DRVOFF_SEL, EN_IN1_SEL and PH_IN2_SEL

The control of the output is similar to the truth tables described in the section before, but with these logically

combined inputs. These combined inputs are listed as follows:

•

Combined input = Pin input OR equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b0

Combined input = Pin input AND equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b1

In Independent mode:

– DRVOFF2 combined = DRVOFF pin OR S_DRVOFF2 bit, if DRVOFF_SEL bit = 1'b0

– DRVOFF2 combined = DRVOFF pin AND S_DRVOFF2 bit, if DRVOFF_SELbit = 1'b1

Note that external nSLEEP pin is still needed for sleep function.

This logical combination offers more configurability to the user as shown in the table below.

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Table 8-10. Register - Pin Control Examples

CONFIG4: xxx_SEL

Bit

Example

PIN status

SPI_IN Bit Status

Comment

DRVOFF as

Either DRVOFF pin = 1 or S_DRVOFF bit = 1

will shutoff the output

DRVOFF_SEL = 1’b0

DRVOFF_SEL = 1’b1

DRVOFF active

S_DRVOFF active

S_DRVOFF = 1'b1

S_PH_IN2 active

redundant shutoff

Pin only control

Only DRVOFF pin function is available

PH_IN2_SEL bit =

1’b0

PH/IN2 - short to

GND or float

PH (direction) will be controlled by the

register bit alone

Register only control

Note

This logical combination is NOT supported in the pre-production samples. In this case, when the

SPI_IN register is unlocked, the output is controlled from the equivalent register bits and the input

pins are ignored. In other words, if SPI_IN unlocked, xxx_combined = S_xxx register bits, else

xxx_combined = Input pin.

8.3.3 Device Configuration

This section describes the various device configurations to enable the user to configure the device to suit their

use case.

8.3.3.1 Slew Rate (SR)

The SR pin (HW variant) or S_SR bits in the CONFIG3 register (SPI variant) determines the slew rate of

the driver. This enables the user to optimize the PWM switching losses while meeting the EM conformance

requirements. For the HW variant, SR is a 6-level setting as summarized in the table below. SPI variant has

additional 2 levels.

Table 8-11. SR Table

SR_LSOFF, SR_LSON[V/µsec]⁽¹⁾

SR Pin

R_LVL2OF6

S_SR Register Bits

3'b000

SR_HSOFF[V/µsec]⁽²⁾

SR_HSON[V/µsec]⁽²⁾

1.2

4

40⁽³⁾

10⁽³⁾

Not available

R_LVL3OF6

3'b001

40

10

3'b010

6.7

11.4

17

40

10

3'b011

15

10

R_LVL4OF6

3'b100

20

10

R_LVL1OF6

3'b101

22

26

10

R_LVL6OF6

3'b110

32

37

10

R_LVL5OF6

3'b111

41

48

10

(1) Applicable for high-side recirculation

(2) Applicable for low-side recirculation (only in the Independent mode operation using low-side load)

(3) Slew rate setting in the Independent mode operation using low-side recirculation (low-side load) for DRV8245HRXZQ1 (HW(H) variant

in VQFN-HR (16) package) is NOT available for use - recommend to use other settings for slew rate control

Note

The SPI variant also offers an optional spread spectrum clocking (SSC) feature that spreads the

internal oscillator frequency +/- 12% around its mean with a period triangular function of ~1.3 MHz to

reduce emissions at higher frequencies.

In the HW variant, the SR pin is latched during device initialization following power-up or wake-up from sleep.

Update during operation is blocked. Also there is no spread spectrum clocking (SSC) feature.

In the SPI variant, the slew rate setting can be changed at any time when SPI communication is available by

writing to the S_SR bits. This change is immediately reflected.

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Note

For the pre-production samples, the SR settings are as shown in Table 8-12 the table below. Also, in

the HW variant, SSC feature is always enabled.

Table 8-12. Pre-Production Samples - SR Table

SR Pin

R_LVL1OF6

S_SR Register Bits

SR_LSOFF, SR_LSON[V/µsec]⁽¹⁾

SR_HSOFF[V/µsec]⁽²⁾

SR_HSON[V/µsec]⁽²⁾

3'b000

23

1.6

33

38

43

28

18

12

23

1.6

33

38

43

28

18

12

8

1.6

8

R_LVL2OF6

3'b001

R_LVL3OF6

3'b010

R_LVL4OF6

3'b011

8

R_LVL5OF6

3'b100

8

R_LVL6OF6

3'101

8

Not available

3'b110

8

3'b111

8

8.3.3.2 IPROPI

The device integrates a current sensing feature with a proportional analog current output on the IPROPI pin that

can be used for load current regulation. This eliminates the need of an external sense resistor or sense circuitry

reducing system size, cost, and complexity.

The device senses the load current by using a shunt-less high-side current mirror topology. This way the device

can only sense an uni-directional high-side current from VM → OUTx → Load through the high-side FET when

it is fully turned ON (linear mode). The IPROPI pin outputs an analog current proportional to this sensed current

scaled by A_IPROPIas follows:

I_IPROPI= (I_HS1+ I_HS2) / A_IPROPI

The IPROPI pin must be connected to an external resistor (R_IPROPI) to ground in order to generate a proportional

voltage V_IPROPI. This allows for the load current to be measured as a voltage-drop across the R_IPROPIresistor

with an analog to digital converter (ADC). The R_IPROPIresistor can be sized based on the expected load current

in the application so that the full range of the controller ADC is utilized.

The current expressed on IPROPI is the sum of the currents flowing out of the OUTx pins from VM. This implies

that:

•

In full-bridge operation using PWM or PH/EN mode, the current expressed on IPROPI pin is always from one

of the half-bridges that is sourcing the current from VM to the load.

•

In independent mode, the current expressed on IPROPI pin could be from either half-bridges or both of them.

It is not possible to observe only one half-bridge current independently.

8.3.3.3 ITRIP Regulation

The device offers an optional internal load current regulation feature using fixed TOFF time method. This is done

by comparing the voltage on the IPROPI pin against a reference voltage determined by ITRIP setting. TOFF time

is fixed at 30 µsec for HW variant, while it is configurable between or 20 to 50 µsec for the SPI variant using

TOFF_SEL bits in the CONFIG3 register.

The ITRIP regulation, when enabled, comes into action only when the HS FET is enabled and current sensing is

possible. In this scenario, when the voltage on the IPROPI pin exceeds the reference voltage set by the ITRIP

setting, the internal current regulation loop forces the following action:

•

In PH/EN or PWM mode, OUT1 = H, OUT2 = H (high-side recirculation) for the fixed TOFF time

– Cycle skipping: Due to minimum duty cycle limitations (especially at low slew rate settings and high VM),

load current will contiue to increase even with ITRIP regulation. In order to prevent this current walk away,

a cycle skipping scheme is implemented, where, if IOUT sensed is still greater than ITRIP at the end of

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TOFF time, then the recirculation time is extended by an additional TOFF period. This recirculation time

addition will continue till IOUT sensed is less than ITRIP at the end of the TOFF period.

•

In Independent mode, If OUTx = H, then toggle OUTx = L for the fixed TOFF time, else no action on OUTx

Note

The user inputs always takes precedence over the internal control. That means that if the inputs

change during the TOFF time, the remainder of the TOFF time is ignored and the outputs will follow

the inputs as commanded.

ISNS

VM

IPROPI

R_IPROPI

High Side Current

Sense

V(IPROPI)

V(ITRIP)

OUTx

GND

ITRIP

R_ITRIP

Impedance Estimator

(HW variant)

DAC

SPI (SPI variant)

Digital Core

Figure 8-4. ITRIP Implementation

Current limit is set by the following equation:

ITRIP regulation level = V_ITRIP/ R_IPROPIX A_IPROPI

(2)

ITRIP regula on ac ve

I_TRIP

I_OUT

V_OUT1

V_OUT2

EN/IN1

t_OFF

PH/IN2

E.g. PH/EN mode

Figure 8-5. Fixed TOFF ITRIP Current Regulation

In Independent mode, since ITRIP regulation is based on summation of the two half-bridge currents on IPROPI

pin, it is not possible to have completely independent current regulation for the two half-bridges simultaneously.

The ITRIP comparator output (ITRIP_CMP) is ignored during output slewing to avoid false triggering of the

comparator output due to current spikes from the load capacitance. Additionally, in the event of transition from

low-side recirculation, an additional blanking time t_BLANKis needed for the sense loop to stabilize before the

ITRIP comparator output is valid.

ITRIP is a 6-level setting for the HW variant. The SPI variant offers two more settings. This is summarized in the

table below:

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Table 8-13. ITRIP Table

ITRIP Pin

R_LVL1OF6

S_ITRIP Register Bits

V_ITRIP[V]

3'b000

3'b001

3'b010

3'b011

3'b100

3'b101

3'b110

3'b111

Regulation Disabled

R_LVL2OF6

1.18

1.41

1.65

1.98

2.31

2.64

2.97

Not available

R_LVL3OF6

R_LVL4OF6

R_LVL5OF6

R_LVL6OF6

In the HW variant of the device, the ITRIP pin changes are transparent and changes are reflected immediately.

In the SPI variant of the device, the ITRIP setting can be changed at any time when SPI communication is

available by writing to the S_ITRIP bits. This change is immediately reflected in the device behavior.

SPI variant only - If the ITRIP regulation levels are reached, the ITRIP_CMP bit in the STATUS1 register is set.

There is no nFAULT pin indication. This bit can be cleared with a CLR_FLT command.

Note

For pre-production samples, the ITRIP settings are as shown in the table below.

Table 8-14. Pre-Production Samples - ITRIP Table

ITRIP Pin

R_LVL1OF6

R_LVL2OF6

R_LVL3OF6

R_LVL4OF6

R_LVL5OF6

R_LVL6OF6

S_ITRIP Register Bits

V_ITRIP[V]

3'b000

Regulation Disabled

3'b001

1.65

1.98

2.31

2.64

2.97

3'b010

3'b011

3'b100

3'b101, 3'b110, 3'b111

8.3.3.4 DIAG

Note

The Off-state diagnostics (OLP) feature in DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16)

package) is NOT available for use - recommend to disable this feature (Set DIAG pin to LVL1 or

LVL5).

The DIAG is a pin (HW variant) or register (SPI variant) setting that is used in both ACTIVE and STANDBY

operation of the device, as follows:

•

STANDBY state

– In PH/EN or PWM modes: Enable or disable Off-state diagnostics (OLP).

– Enable or disable Off-state diagnostics (OLP), as well as select the OLP combinations when enabled.

Refer to the tables in the Off-state diagnostics (OLP) section for details on this.

ACTIVE state

•

– Mask ITRIP regulation function if the load type is indicated as high-side load.

– SPI variant only - Mask active open load detection (OLA) if the load type is indicated as low-side. load

– HW variant only - Configure fault reaction between retry and latch settings

8.3.3.4.1 HW variant

For the HW variant, the DIAG pin is a 6-level setting. Depending on the mode, its configurations are

summarized in the table below.

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Table 8-15. DIAG table for the HW variant, PH/EN or PWM mode

STANDBY state

Off-state diagnostics

Disabled

ACTIVE state

Fault reaction

Retry

DIAG pin

R_LVL1OF6

All other levels

Enabled⁽¹⁾

Latch

Table 8-16. DIAG table for the HW variant, Independent mode

STANDBY state

Off-state diagnostics

Disabled

ACTIVE state

Fault reaction

Retry

DIAG pin

Load Configuration

Low-side load

High-side load

Low-side load

IPROPI / ITRIP

R_LVL1OF6

R_LVL2OF6

R_LVL3OF6

R_LVL4OF6

R_LVL5OF6

R_LVL6OF6

Available

Disabled

Available

Enabled⁽¹⁾

Latch

Enabled⁽¹⁾

Latch

Enabled⁽¹⁾

Retry

Disabled

Latch

Enabled⁽¹⁾

Retry

(1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details

Note

HW variant only - Option to disable off-state diagnostics for a high-side load use case is not

supported. In this case, setting DRVOFF pin high and IN pin low is only way to disable off-state

diagnostics.

In the HW variant, the DIAG pin is latched during device initialization following power-up or wake-up from sleep.

Update during operation is blocked.

8.3.3.4.2 SPI variant

For the SPI variant, S_DIAG is a 2-bit setting in the CONFIG2 register. Depending on the mode, its

configurations are summarized in the table below.

Table 8-17. DIAG table for the SPI variant, PH/EN or PWM mode

STANDBY state

Off-state diagnostics

Disabled

ACTIVE state

On-state diagnostics

Available

S_DIAG bits

2'b00

2'b01, 2'b10, 2'b11

Enabled⁽¹⁾

Available

Table 8-18. DIAG table for the SPI variant, Independent mode

STANDBY state

Off-state diagnostics

Disabled

ACTIVE state

On-state diagnostics

Disabled

S_DIAG bits

Load Configuration

Low-side load

IPROPI / ITRIP

Available

2'b00

2'b01

2'b10

2'b11

Enabled⁽¹⁾

Low-side load

Disabled

Available

Disabled

High-side load

Available

Disabled

Enabled⁽¹⁾

Available

Disabled

(1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details

In the SPI variant of the device, the settings can be changed anytime when SPI communication is available by

writing to the S_DIAG bits. This change is immediately reflected.

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8.3.4 Protection and Diagnostics

The driver is protected against over-current and over-temperature events to ensure device robustness.

Additionally, the device also offers load monitoring (on-state and off-state), over/ under voltage monitoring on

VM pin to signal any unexpected voltage conditions. Fault signaling is done through a low-side open drain

nFAULT pin which gets pulled to GND by I_{nFAULT_PD}current on detection of a fault condition. Transition to SLEEP

state automatically de-asserts nFAULT.

Note

In the SPI variant, nFAULT pin logic level is the inverted copy of the FAULT bit in the FAULT

SUMMARY register. Only exception is when off-state diagnostics are enabled and SPI_IN register

is locked (Refer OLP section) .

For the SPI variant, whenever nFAULT is asserted low, the device logs the fault into the FAULT SUMMARY and

STATUS registers. These registers can be cleared only by

•

CLR FLT command or

SLEEP command through the nSLEEP pin

It is possible to get all the useful diagnostic information for periodic software monitoring in a single 16 bit SPI

frame by:

•

Reading the STATUS1 register during ACTIVE state

Reading the STATUS2 register during STANDBY state

All the diagnosable fault events can be uniquely identified by reading the STATUS registers.

8.3.4.1 Over Current Protection (OCP)

•

Device state: ACTIVE

Mechanism & thresholds: An analog current limit circuit on each MOSFET limits the peak current out of the

device even in hard short circuit events. If the output current exceeds the overcurrent threshold, I_OCP, for

longer than t_OCP, then an over current fault is detected.

Action:

•

– nFAULT pin is asserted low

– Reaction is based on mode selection:

•

PH/EN or PWM mode - Both OUTx is Hi-Z

Independent mode - The affected half-bridge OUTx is Hi-Z

– For a short to GND fault (over current detected on the high-side FET), the IPROPI pin continues to be

pulled up to V_{IPROPI_LIM}even if the FET has been disabled. For the HW variant, this helps differentiate a

short to GND fault during ACTIVE state from other fault types, as the IPROPI pin is pulled high while the

nFAULT pin is asserted low.

•

Reaction configurable between latch setting and retry setting based on t_RETRYand t_CLEAR

User can add a small 6.3V capacitor in the range of 10 nF to 100 nF on the IPROPI pin to avoid a race

condition with ITRIP regulation in case of a load short condition when ITRIP regulation is enabled.

– In case of a load short where there is enough inductance in the short, ITRIP regulation could trigger ahead

of the OCP detection, resulting in the device missing the OCP detection. To ensure that OCP detection

wins this race condition, a small capacitor (10 nF - 100 nF) on the IPROPI pin is recommended. This

capacitance slows down the ITRIP regulation loop enough to allow the OCP detection circuit to work as

intended.

The SPI variant offers configurable I_OCPlevels and t_OCPfilter times. Refer CONFIG4 register for these settings.

8.3.4.2 Over Temperature Protection (TSD)

•

Device state: STANDBY, ACTIVE

Mechanism & thresholds: The device has several temperature sensors spread around the die. If any of the

sensors detect an over temperature event, set by T_TSDfor a time greater than t_TSD, then an over temperature

fault is detected.

Action:

•

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– nFAULT pin is asserted low

– Both OUTx is Hi-Z

– IPROPI pin is Hi-Z

•

Reaction configurable between latch setting and retry setting based on T_HYSand t_{CLEAR_TSD}

8.3.4.3 Off-State Diagnostics (OLP)

Note

This feature in DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) is NOT available for use

- recommend to keep this feature disabled (Set DIAG pin to LVL1 or LVL5).

The user can determine the impedance on the OUTx node using off-state diagnostics in the STANDBY state

when the power FETs are off. With this diagnostics, it is possible to detect the following fault conditions passively

in the STANDBY state:

•

Output short to VM or GND < 100 Ω

Open load > 1K Ω for full-bridge load or low-side load

Open load > 10K Ω for high-side load, VM = 13.5 V

Note

It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this

logically if an over current fault (OCP) occurs during ACTIVE operation, but OLP diagnotics do not

report any fault in the STANDBY state. Occurrence of both OCP in the ACTIVE state and OLP in the

STANDBY state would imply a terminal short (short on OUT node).

•

The user can configure the following combinations

– Internal pull up resistor (R_{OLP_PU}) on OUTx

– Internal pull down resistor (R_{OLP_PD}) on OUTx

– Comparator reference level

– Comparator input selection (OUT1 or OUT2)

•

This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the

SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.

HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT

pin.

SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in

STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also

available on the nFAULT pin when off-state diagnostics are enabled.

The user is expected to toggle through all the combinations and record the comparator output after its output

is settled.

•

Based on the input combinations and comparator output, the user can determine if there is a fault on the

output.

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Internal

5V

VM

R_{OLP_PU}

D1

OUT1

OUT2

Filter

R_{OLP_PD}

R_HIZ

D2

GND

Output on nFAULT pin / register^OLP_CMP

V_{OLP_REFH}

V_{OLP_REFL}

REF Voltage propor onal

to Internal 5V

PIN / register control

Figure 8-6. Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or

PWM modes is shown in Table 8-19.

Table 8-19. Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)

User Inputs

nSLEEP DRVOFF EN/IN1

OLP Set-Up

OUT2 CMP REF

OLP CMP Output

Output

GND

Open

PH/IN2

OUT1

Normal

VM Short

selected

Short

1

0

1

R_{OLP_PU}

R_{OLP_PD}

R_{OLP_PD}V_{OLP_REFH}

R_{OLP_PD}V_{OLP_REFL}

R_{OLP_PU}V_{OLP_REFL}

OUT1

OUT2

L

H

L

H

0

1

H

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent

mode is shown in Table 8-20.

Table 8-20. Off-State Diagnostics Table for Low-Side Load - Independent Mode

User Inputs

OLP Set-Up

OLP_CMP Output

DIAG

S_DIAG

bits

CMP

Output

nSLEEP DRVOFF EN/IN1

PH/IN2

OUT1

R_{OLP_PU}

R_{OLP_PD}

Hi-Z

OUT2

Hi-Z

Normal

Open

Short

REF

selected

LVL2,

LVL6

don't

care

V_{OLP_REF}

2'b01

2'b11

2'b01

2'b11

1

0

OUT1

OUT2

L

H

L

H

L

H

LVL3,

LVL4

don't

care

V_{OLP_REF}

Hi-Z

L

LVL2,

LVL6

V_{OLP_REF}

1

R_{OLP_PU}

H

LVL3,

LVL4

V_{OLP_REF}

Hi-Z

R_{OLP_PD}

L

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in

Independent mode is shown in Table 8-21.

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Table 8-21. Off-State Diagnostics Table for High-Side Load - Independent Mode

User Inputs

OLP Set-Up

OLP_CMP Output

DIAG

S_DIAG

bits

CMP

Output

nSLEEP DRVOFF EN/IN1

PH/IN2

OUT1

R_{OLP_PU}

R_{OLP_PD}

Hi-Z

OUT2

Hi-Z

Normal

Open

Short

REF

selected

LVL2,

LVL6

don't

care

V_{OLP_REF}

2'b01

2'b11

2'b01

2'b11

1

0

OUT1

OUT2

H

L

H

L

H

LVL3,

LVL4

don't

care

V_{OLP_REF}

Hi-Z

L

LVL2,

LVL6

V_{OLP_REF}

1

R_{OLP_PU}

H

LVL3,

LVL4

V_{OLP_REF}

Hi-Z

R_{OLP_PD}

L

Note

For the pre-production samples, it is NOT possible to differentiate between an open fault and a load

short in the Independent mode.

8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only

•

Device state: ACTIVE - high-side recirculation

Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state

during high-side recirculation. This includes high-side load connected directly to VM or through a high-side

FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into

VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on

OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike,

this load current needs to be higher than the pull down current (I_{PD_OLA}) on the output asserted by the FET

driver. Absence of this voltage spike for "3" consecutive re-circulation switching cycles indicates a loss of load

inductance or increase in load resistance and is detected as an OLA fault.

Action:

– nFAULT pin is asserted low

– Output - normal function maintained

– IPROPI pin - normal function maintained

Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically

cleared with the detection of "3" consecutive voltage spikes during re-circulation switching cycles.

•

This monitoring is optional and can be disabled.

Note

OLA is not supported for low-side loads (low-side recirculation).

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VM

OLA_VREF

OUTx_OLA_CMP

D1

OUTx

I_{PD_OLA}

D2

GND

Figure 8-7. On-State Diagnostics

8.3.4.5 VM Over Voltage Monitor

•

Device state: STANDBY, ACTIVE

Mechanism & thresholds: If the supply voltage on the VM pin exceeds the threshold, set by V_VMOVfor a time

greater than t_VMOV, then an VM over voltage fault is detected.

Action:

•

– nFAULT pin is asserted low

– Output - normal function maintained

– IPROPI pin - normal function maintained

•

Reaction configurable between retry and latch setting

In the SPI variant, this monitoring is optional and can be disabled. Also the thresholds are configurable. Refer

CONFIG1 register.

8.3.4.6 VM Under Voltage Monitor

•

Device state: STANDBY, ACTIVE

Mechanism & thresholds: If the supply voltage on the VM pin drops below the threshold, set by V_VMUVfor a

time greater than t_VMUV, then an VM under voltage fault is detected.

•

Action:

– nFAULT pin is asserted low

– Both OUTx is Hi-Z

– IPROPI pin is Hi-Z

•

HW and SPI (S) variant: Reaction fixed to retry setting

Only for SPI (P) variant: Reaction configurable between retry and latch setting

Note that retry time is only dependent on recovery of VM under voltage condition and is independent of

t_RETRY/ t_CLEARtimes

8.3.4.7 Power On Reset (POR)

•

Device state: ALL

Mechanism & thresholds: If logic supply drops below VDD_{POR_FALL}for a time greater than t_POR, then a power

on reset will occur that will hard reset the device.

•

Action:

– nFAULT pin is de-asserted

– Both OUTx is Hi-Z

– IPROPI pin is Hi-Z.

– When this supply recovers above the VDD_{POR_RISE}level, the device will go through a wake-up

initialization and nFAULT pin will be asserted low to notify the user on this reset (Refer Wake-up

transients).

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•

HW and SPI (S) variant: These thresholds translate to VM_{POR_FALL}and VM_{POR_RISE}as the logic supply is

internally derived from the VM supply

Only for SPI (P) variant: These thresholds directly map to the VDD pin voltage (VDD_{POR_FALL}and

VDD_{POR_RISE}

)

Fault reaction: Always retry, retry time depends on the external supply condition to initiate a device wake-up

8.3.4.8 Event Priority

In the ACTIVE state, in a scenario where two or more events occur simultaneously, the device assigns control of

the driver based on the following priority table.

Table 8-22. Event Priority Table

Event

Priority

User SLEEP command

1

2

3

4

5

6

7

8

9

User input: DRVOFF

Over temperature detection (TSD)

Over current detection (OCP)⁽¹⁾

VM under voltage detection (VMUV)

User input: EN/IN1 and/or PH/IN2

Internal PWM control from ITRIP regulation

VM over voltage detection (VMOV)⁽²⁾

On-state fault detection (OLA - SPI variant only)⁽²⁾

(1) If the device is waiting for an OCP event to be confirmed (waiting for t_OCP) when any of events with lower priority than OCP occur, then

the device may delay servicing the other events up to a maximum time of t_OCPto enable detection of the OCP event.

(2) Priority is "don't care" in this case as this fault event does not cause a change in OUTx

8.4 Device Functional States

The device has three functional states:

•

SLEEP

STANDBY

ACTIVE

SLEEP

nFAULT = H, No communica on

1

2

ACTIVE

Protec on Enabled

nFAULT = fault

signaling

Communica on

available

STANDBY

nFAULT = H

Communica on

available

INIT2

nFAULT = L

Communica on

enabled

6

7

INIT1

nFAULT = H

5

3

4

1. nSLEEP = 1 for t > t_WAKE

3. Power on reset

2. nSLEEP = 0 for t > t_SLEEP

4. End of t_COM

5. CLR_FLT or HW RESET pulse from from controller & End of t_READY

6. DRVOFF = 0 & [IN1/EN IN2/PH] != [1 1], if PWM mode

7. DRVOFF = 1 or [IN1/EN IN2/PH] = [1 1], if PWM mode

Note

For pre-production samples, [IN1/EN IN2/PH] = [0 0], if PWM mode

Figure 8-8. Illustrative State Diagram

These states are described in the following section.

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8.4.1 SLEEP State

This state occurs when nSLEEP pin is asserted low for a time > t_SLEEPor voltage on the VDD pin is <

VDD_{POR_FALL}

.

This is the deep sleep low power (I_SLEEP) state of the device where all functions except a wake-up command are

not serviced. The drivers are in Hi-Z. The internal power supply rails (5 V and others) are powered off. nFAULT

pin is de-asserted in this state. The device can enter this state from either the STANDBY or the ACTIVE state,

when the nSLEEP pin is asserted low for time longer than t_SLEEP(HW variant) or for t_{SLEEP_SPI}(SPI (S) variant).

8.4.2 STANDBY State

The device is in this state when nSLEEP pin is asserted high or the voltage on the VDD pin is > VDD_{POR_RISE}

with DRVOFF = 1'b0 for all modes and additionally, in PWM mode when both IN1/EN & IN2/PH are 1'b1 [Note:

1'b0 for pre-production samples]. In this state, the device is powered up (I_STANDBY), with the driver Hi-Z and

nFAULT de-asserted. The device is ready to transition to ACTIVE state or SLEEP state when commanded so.

Off-state diagnostics (OLP), if enabled, are done in this state.

8.4.3 Wake-up to STANDBY State

The device starts transition from SLEEP state to STANDBY state

•

if the nSLEEP pin goes high for a duration longer than t_WAKE, or

if VM supply > VM_{POR_RISE}or VDD supply > VDD_{POR_RISE}such that internal POR is released to indicate a

power-up.

The device goes through an initialization sequence to load its internal registers and wake-up all the blocks in the

following sequence:

•

At a certain time, t_COMfrom wake-up, the device is capable of communication. This is indicated by asserting

the nFAULT pin low.

•

This is followed by the time t_READY, when the device wake-up is complete.

At this point, once the device receives a nSLEEP reset pulse (HW variant) or a CLR FAULT command

through SPI (SPI variant) as an acknowledgment of the wake-up from the controller, the device enters the

STANDBY state. This is indicated by the de-assertion of the nFAULT pin. The driver is held in Hi-Z till this

point.

•

From here on, the device is ready to drive the bridge based on the truth tables for the specific mode

configured.

Refer to the wake-up transients waveforms for the illustration.

8.4.4 ACTIVE State

The device is fully functional in this state with the drivers controlled by other inputs as described in prior sections.

All protection features are fully functional with fault signaling on nFAULT pin. SPI communication is available.The

device can transition into this state only from the STANDBY state.

8.4.5 nSLEEP Reset Pulse (HW Variant Only)

This is a special communication signal from the controller to the device through the nSLEEP pin available only

for the HW variant. This is used to:

•

Acknowledge the nFAULT asserted during the SLEEP/ Power up transition to STANDBY state

Clear a latched fault when the fault reaction is configured to the LATCHED setting, without forcing the device

into SLEEP or affecting any of the other functions (Equivalent to the CLR_FAULT command in the SPI

variant)

This pulse on nSLEEP must be greater than the nSLEEP deglitch time of t_RESETtime, but shorter than t_SLEEP

time, as shown in case # 3, in Table 8-23 below.

Table 8-23. nSLEEP Timing (HW Variant Only)

Command Interpretation

Case #

Window Start Time

Window End Time

Clear Fault

Sleep

1

0

t_RESETmin

No

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Table 8-23. nSLEEP Timing (HW Variant Only) (continued)

Command Interpretation

Case #

Window Start Time

Window End Time

Clear Fault

Sleep

No

2

3

4

5

t_RESETmin

t_RESETmax

t_SLEEPmin

t_SLEEPmax

t_RESETmax

t_SLEEPmin

t_SLEEPmax

No limit

Interdeterminate

Yes

No

Interdeterminate

Yes

t

_SLEEPmax

t

_SLEEPmin

t_RESETmax

_RESETmin

t

Case 1

Case 2

Case 3

Case 4

Case 5

Window 5

Window 1

Window 2

Window 3

Window 4

me

Figure 8-9. nSLEEP Pulse Scenarios

8.5 Programming - SPI Variant Only

8.5.1 SPI Interface

The SPI variant has full-duplex, 4-wire synchronous communication that is used to set device configurations,

operating parameters, and read out diagnostic information from the device. The SPI operates in peripheral mode

and connects to a controller. The serial data input (SDI) word consists of a 16-bit word, with an 8-bit command

(A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of the FAULT_SUMMARY byte

(S1), followed by a report byte (R1). The report byte is either the register data being accessed by read command

or null for a write command. The data sequence between the MCU and the SPI peripheral driver is shown in

Figure 8-10.

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nSCS

A1

S1

D1

R1

SDI

SDO

Figure 8-10. SPI Data - Standard "16-bit" Frame

A valid frame must meet the following conditions:

•

SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

nSCS pin should be pulled high between words.

When nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed

in the Hi-Z state.

•

Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the

device on the subsequent falling edge of SCLK.

•

The most significant bit (MSB) is shifted in and out first.

A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chain

frame with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction.

Else, a frame error (SPI_ERR) is reported and the data is ignored if it is a WRITE operation.

8.5.2 Standard Frame

The SDI input data word is 2 bytes long and consists of the following format:

•

Command byte (first byte)

– MSB bit indicates frame type (bit B15 = 0 for standard frame).

– Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1)

– Followed by 6 address bits, A[5:0] (bits B13 through B8)

•

Data byte (second byte)

– Second byte indicates data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set

to null values, while for a write operation, these bits have the data value for the addressed register.

Table 8-24. SDI - Standard Frame Format

Command Byte

Data Byte

Bit

B15

0

B14

W0

B13

A5

B12

A4

B11

A3

B10

A2

B9

A1

B8

A0

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

Data

The SDO output data word is 2 bytes long and consists of the following format:

•

Status byte (first byte)

– 2 MSB bits are forced high (B15, B14 = 1)

– Following 6 bits are from the FAULT SUMMARY register (B13:B8)

Report byte (second byte)

•

– The second byte (B7:B0) is either the data currently in the register being read for a read operation (W0 =

1), or, existing data in the register being written to for a write command (W0 = 0)

Table 8-25. SDO - Standard Frame Format

Status Byte

Report Byte

B4 B3

Bit

B15

B14

B13

B12 B11

B10

B9

B8

B7

B6

B5

B2

B1

B0

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Table 8-25. SDO - Standard Frame Format (continued)

Status Byte

Report Byte

SPI_E

RR

Data

1

FAULT VMOV VMUV OCP

TSD

D7

D6

D5

D4 D3

D2

D1

D0

Note

For the pre-production samples, B8 in the above SDO format is OLA bit (not SPI_ERR as shown).

8.5.3 SPI Interface for Multiple Peripherals

Multiple devices can be connected to the controller with and without the daisy chain. For connecting a 'n' number

of devices to a controller without using a daisy chain, 'n' number of I/O resources from controller has to utilized

for nSCS pins as shown in Figure 8-11. Whereas, if the daisy chain configuration is used, then a single nSCS

line can be used for connecting multiple devices. Figure 8-12

DRV8x

SCLK

SDI

SCLK

SDI

Master Controller

SPI

Communication

SPI

Communication

SDO

nSCS

SDO

nSCS

CS1

MCLK

MO

CS

MCLK

MO

SPI

Communication

SPI

Communication

DRV8x

MI

SCLK

SDI

SCLK

SDI

CS2

SPI

SDO

nSCS

SDO

nSCS

Communication

Figure 8-11. SPI Operation Without Daisy Chain

Figure 8-12. SPI Operation With Daisy Chain

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8.5.3.1 Daisy Chain Frame for Multiple Peripherals

The device can be connected in a daisy chain configuration to save GPIO ports when multiple devices

are communicating to the same MCU. Figure 8-13 shows the topology with waveforms, where, number of

peripherals connected in a daisy chain "n" is set to 3. A maximum of up to 63 devices can be connected in this

manner.

SDO2

SDI3

SDO3

M-SDI

M-SDO

SDI1

SDO1

SDI2

M-SDO

SDI1

SDI2

SDO3

SDO2

SDO1

M-nSCS

M-SCLK

M-SDI

nSCS

SDI1

HDR1

HDR2

HDR1

S1

A3

A2

A1

A2

A3

D3

R1

R2

R3

D2

D3

R1

R2

D1

D2

D3

R1

SDO1

SDI2

S1

S2

S3

HDR2

HDR1

S1

A3

SDO2

SDI3

HDR2

HDR1

SDO3

S2

HDR2

All Address

Bytes Reach

Destination

All Address

Bytes Reach

Destination

Status

Response Here

Reads

Execute Here

Writes

Execute Here

Figure 8-13. Daisy Chain SPI Operation

The SDI sent by the controller in this case would be in the following format (see SDI1 in Figure 8-13 ):

•

2 bytes of header (HDR1, HDR2)

"n" bytes of command byte starting with furthest peripheral in the chain (for this example, this is A3, A2, A1)

"n" bytes of data byte starting with furthest peripheral in the chain (for this example, this is D3, D2, D1)

Total of 2 x "n" + 2 bytes

While the data is being transmitted through the chain, the controller receives it in the following format (see SDO3

in Figure 8-13):

•

3 bytes of status byte starting with furthest peripheral in the chain (for this example, this is S3, S2, S1)

2 bytes of header that were transmitted before (HDR1, HDR2)

3 bytes of report byte starting with furthest peripheral in the chain (for this example, this is R3, R2, R1)

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The Header bytes are special bytes asserted at the beginning of a daisy chain SPI communication. Header

bytes must start with 1 and 0 for the two leading bits.

The first header byte (HDR1) contains information of the total number of peripheral devices in the daisy chain.

N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 8-14. Up to

63 devices can be connected in series per daisy chain connection. Number of peripheral = 0 is not permitted and

will result in a SPI_ERR flag.

The second header byte (HDR2) contains a global CLR FAULT command that will clear the fault registers of

all the devices on the rising edge of the chip select (nSCS) signal. The 5 trailing bits of the HDR2 register are

marked as SPARE (don’t care bits). These can be used by the MCU to determine integrity of the daisy chain

connection.

1

0

N5

N4

N3

N2

N1

N0

HDR1

Number of Devices in the Chain (Up to 63 max)

CLR_FLT SPARE SPARE SPARE SPARE SPARE

Don’t Care

HDR2

1 = Global CLR_FAULT

0 = Don’t Care

Figure 8-14. Header bytes

In addition, the device recognizes bytes that start with 1 and 1 for the two leading bits as a "pass" byte. These

"pass" bytes are NOT processed by the device, but they are simply transmitted out on SDO in the following byte.

When data passes through a device, it determines the position of itself in the chain by counting the number of

Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in

the chain will receive two status bytes before receiving the two header bytes.

From the two status bytes it knows that its position is second in the chain, and from HDR2 byte it knows how

many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer

and bypasses the other bits. This protocol allows for faster communication without adding latency to the system

for up to 63 devices in the chain.

The command, data, status and report bytes remain the same as described in the standard frame format.

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8.6 Register Map - SPI Variant Only

This section describes the user configurable registers in the device.

Note

While the device allows register writes at any time SPI communication is available, it is recommended

to exercise caution while updating registers in the ACTIVE state while the load is being driven. This

is especially important for settings such as S_MODE and S_DIAG which control the critical device

configuration. In order to prevent accidental register writes, the device offers a locking mechanism

through the REG_LOCK bits in the COMMAND register to lock the contents of all configurable

registers. Best practice would be to write all the configurable registers during initialization and then

lock these settings. Run-time register writes for output control are handled by the SPI_IN register,

which offers its own separate locking mechanism through the SPI_IN_LOCK bits.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The DRV824x-Q1 family of devices can be used in a variety of applications that require either a half-bridge

or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids,

and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive

elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current

control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two

half-bridge drivers.

9.1.1 Load Summary

Table 9-1 summarizes the utility of the device features for different type of inductive loads.

Table 9-1. Load Summary Table

Configuration

Device Feature

LOAD TYPE

Recirculation

Path

Device

Slew Rate

Current sense ITRIP regulation

Bi-directional motor or

solenoid⁽¹⁾

DRV824x in PH/EN or PWM

mode

High-side

Low-side

High-side

Full range

Continuous

Useful

2 Uni-directional motors or

low-side solenoids (one side

connected to GND)

Individual load

regulation not

possible

DRV824x in Independent

mode ⁽²⁾

Limited⁽⁴⁾

Full range

Discontinuous⁽³⁾

,

2 High-side solenoids (one

side connected to VM)

DRV824x in Independent

mode ⁽²⁾

Not available, need external solution

(1) Solenoid - clamping or quick demagnetization possible, but clamping level will be VM dependent

(2) Independent Hi-Z only supported in the SPI variant

(3) Not sensed during recirculation and during OUTx voltage slew times including t_blank

(4) Rising edge slew rate capped at 8 V/µsec for higher settings

VM

nFAULT

IPROPI

to Controller ADC

SPI (Opt)

DRVOFF

Controller I/Os

(can be shared)

DRV824X

Applicable for

PWM or

PH/EN

mode

BDC

solenoid

nSLEEP

OUT1

EN/IN1

PH/IN2

LOAD

to Controller I/O

OUT2

GND

Figure 9-1. Illustration Showing a Full-Bridge Topology With DRV824X-Q1 in PWM or PH/EN Mode

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VM

nFAULT

to Controller ADC

IPROPI

SPI (Opt)

DRVOFF

Controller I/Os

(can be shared)

Summing current

Applicable for

DRV824X

BDC

solenoid

Independent

mode

nSLEEP

OUT1

LOAD

EN/IN1

PH/IN2

to Controller I/O

OUT2

LOAD

GND

Figure 9-2. Illustration Showing Half-Bridge Topology to Drive Two Low-side Loads Independently With

DRV824X-Q1 Device in INDEPENDENT Mode

VM

nFAULT

HS Switch for

clamping

(OPT)

IPROPI

Not useful

to Controller I/O

SPI (Opt)

DRVOFF

Controller I/Os

(can be shared)

DRV824X

Independent

mode

nSLEEP

OUT1

OUT2

solenoid

EN/IN1

PH/IN2

to Controller I/O

GND

Figure 9-3. Illustration Showing a Half-Bridge Topology to Drive Two High-side Loads Independently With

DRV824X-Q1 Device in INDEPENDENT Mode

9.2 Typical Application

The figures below show the typical application schematic for driving a brushed DC motor or any inductive load in

various modes. There are several optional connections shown in these schematics, which are listed as follows:

•

SPI (S) variant - the nSLEEP pin can be tied off high in the application if SLEEP function is not needed (not

relevant for the SPI (P) variant). For the HW variant, the nSLEEP pin control is needed to issue a reset pulse

during wake-up as well as to modify and latch any changes with MODE, DIAG, SR, and ITRIP.

SPI variant - the DRVOFF pin can be tied off low in the application if DRVOFF pin function is not needed.

SPI variant - EN/IN1 pin can be tied off low or left floating if register only control is needed.

SPI variant - the PH/IN2 pin can be tied off low or left floating if register only control is needed.

IPROPI pin monitoring is optional. Also IPROPI pin can be tied low if ITRIP feature & IPROPI function is not

needed.

•

SPI variant - the nFAULT pin monitoring is optional. All diagnostic information can be read from the STATUS

registers.

SPI variant - Inputs (SDI, nSCS, SCLK) are compatible with 3.3 V / 5 V levels.

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•

SPI variant - SDO tracks the nSLEEP pin voltage for the SPI (S) variant or VDD for SPI (P) variant. To

interface SDO on the SPI (P) variant with a 3.3 V level, a level shifter is recommended.

HW variant - Resistor on CONFIG pins is not needed for two selections - tie off to GND and Hi-Z.

9.2.1 HW Variant

V_CC

Reverse Supply

Protected Input

Reverse Supply

Protected Input

SSOP HW

24

5

6,7,8,21,22,23

24

5

6,7,8,21,22,23

I/O

nSLEEP

VM

I/O

nSLEEP

VM

C_VM2

I/O

DRVOFF

C_VM1

DRVOFF

EN/IN1

PH/IN2

IPROPI

C_VM1

4

3

4

EN/IN1

PH/IN2

IPROPI

nFAULT

MODE

DIAG

3

18,19,20

OUT2

LOAD

I/O

OUT2

25

26

27

2

Op onal (5)

25

Op onal (5)

R_IPROPI

ADC

I/O

ADC

I/O

R_IPROPI

V_CC

R_nFAULT

VM / GND

V_CC

R_nFAULT

26

27

nFAULT

MODE

9,10,11

LOAD

OUT1

GND

OUT1

GND

R_MODE

R_DIAG

R_ITRIP

R_SR

R_MODE

2

28

1

DIAG

ITRIP

SR

R_DIAG

R_ITRIP

R_SR

12,13,14,

15,16,17

12,13,14,

15,16,17

28

1

ITRIP

SR

HS/ LS load in Independent mode

FB with PH/EN or PWM mode

Figure 9-4. Typical Application Schematic - HW Variant in HTSSOP Package

V_CC

VQFN-HR HW

Reverse Supply

Protected Input

Reverse Supply

Protected Input

3

8

4

3

8

4

I/O

nSLEEP

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

MODE

DIAG

VM

I/O

nSLEEP

DRVOFF

EN/IN1

VM

C_VM2

C_VM1

9

I/O

5

10

2

5

10

2

OUT2

I/O

LOAD

OUT2

I/O

PH/IN2

Op onal (5)

R_IPROPI

Op onal (5)

ADC

I/O

ADC

I/O

IPROPI

V_CC

R_nFAULT

R_IPROPI

)

VM / GND

V_CC

R_nFAULT

1

nFAULT

MODE

DIAG

ITRIP

SR

14

11

13

12

7

6

14

11

13

12

7

6

OUT1

GND

LOAD

OUT1

GND

R_MODE

R_DIAG

R_ITRIP

R_SR

R_DIAG

R_ITRIP

R_SR

ITRIP

SR

HS/ LS load in Independent mode

FB with PH/EN or PWM mode

Figure 9-5. Typical Application Schematic - HW Variant in VQFN-HR Package

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9.2.2 SPI Variant

V_CC

Reverse Supply

Protected Input

Reverse Supply

Protected Input

SSOP SPI

24

5

6,7,8,21,22,23

Op onal (1)

Op onal (2)

Op onal (3)

Op onal (4)

Op onal (5)

24

5

6,7,8,21,22,23

Op onal (1)

I/O

nSLEEP

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

VM

I/O

nSLEEP

VM

C_VM2

Op onal (2)

Op onal (3)

Op onal (4)

Op onal (5)

C_VM2

I/O

C_VM1

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

C_VM1

4

I/O

3

18,19,20

OUT2

I/O

LOAD

OUT2

I/O

25

26

27

2

25

26

27

2

ADC

I/O

ADC

I/O

R_IPROPI

V_CC

R_nFAULT

R_IPROPI

VM / GND

V_CC

R_nFAULT

Op onal (6)

9,10,11

OUT1

GND

LOAD

OUT1

GND

S

P

I

nSCS

S

P

I

nSCS

12,13,14,

15,16,17

12,13,14,

15,16,17

28

1

28

1

SDI

SCLK

HS/ LS load in Independent mode

FB with PH/EN or PWM mode

Figure 9-6. Typical Application Schematic - SPI (S) Variant in HTSSOP Package

V_CC

Reverse Supply

Protected Input

Reverse Supply

Protected Input

SSOP SPI

24

6,7,8,21,22,23

24

5

6,7,8,21,22,23

Logic Supply

VDD

Logic Supply

Op onal (2)

VM

VDD

VM

5

4

C_VM2

Op onal (2)

C_VM2

I/O

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

C_VM1

I/O

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

C_VM1

Op onal (3)

Op onal (4)

Op onal (5)

4

Op onal (3)

Op onal (4)

Op onal (5)

3

18,19,20

OUT2

I/O

LOAD

OUT2

I/O

25

26

27

2

25

26

27

2

ADC

I/O

ADC

I/O

R_IPROPI

V_CC

R_nFAULT

R_IPROPI

VM / GND

V_CC

R_nFAULT

Op onal (6)

9,10,11

OUT1

GND

LOAD

OUT1

GND

S

P

I

nSCS

SDI

S

P

I

nSCS

SDI

12,13,14,

15,16,17

12,13,14,

15,16,17

28

1

28

1

SCLK

HS/ LS load in Independent mode

FB with PH/EN or PWM mode

Figure 9-7. Typical Application Schematic - SPI (P) Variant in HTSSOP Package

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V_CC

VQFN-HR SPI

Reverse Supply

Protected Input

Reverse Supply

Protected Input

3

10

11

12

2

4

Op onal (1)

Op onal (2)

Op onal (3)

Op onal (4)

Op onal (5)

3

10

11

12

2

4

Op onal (1)

Op onal (2)

Op onal (3)

Op onal (4)

Op onal (5)

I/O

nSLEEP

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

VM

I/O

nSLEEP

DRVOFF

EN/IN1

PH/IN2

IPROPI

nFAULT

SDO

VM

C_VM2

I/O

C_VM1

5,6

I/O

5,6

I/O

OUT2

LOAD

OUT2

I/O

ADC

I/O

ADC

I/O

R_IPROPI

V_CC

R_nFAULT

R_IPROPI

VM / GND

V_CC

R_nFAULT

1

Op onal (6)

16

13

15

14

8,9

7

16

13

15

14

8,9

7

OUT1

GND

LOAD

OUT1

GND

S

P

I

nSCS

S

P

I

nSCS

SDI

SCLK

HS/ LS load in Independent mode

FB with PH/EN or PWM mode

Figure 9-8. Typical Application Schematic - SPI (S) Variant in VQFN-HR Package

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10 Power Supply Recommendations

The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic

capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk

capacitor must be placed on the VM pin.

10.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk

capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors including:

•

The highest current required by the motor system.

The capacitance of the power supply and the ability of the power supply to source current.

The amount of parasitic inductance between the power supply and motor system.

The acceptable voltage ripple.

The type of motor used (brushed DC, brushless DC, and stepper).

The motor braking method.

The inductance between the power supply and motor drive system limits the rate that current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage

remains stable, and high current can be quickly supplied.

The data sheet provides a recommended value, but system-level testing is required to determine the appropriate

sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases

when the motor transfers energy to the supply.

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11 Layout

11.1 Layout Guidelines

Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values

of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace

or ground plane connection to the device GND pin.

Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed

such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as

possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk

capacitor to deliver high current.

For the SPI (P) device variant, VDD pin may be bypassed to ground using low-ESR ceramic 6.3 V bypass

capacitor with recommended values of 0.1 μF.

11.2 Layout Example

The following figure shows a layout example for a 4 cm X 4 cm x 1.6 mm, 4 layer PCB for a leaded package

device. The 4 layers uses 2 oz copper on top/ bottom signal layers and 1 oz copper on internal supply layers,

with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 mm minimum via pitch. The same layout can be

adopted for the non-leaded VQFN-HR package as well. The Section 7.5.14 for the 4 cm X 4 cm X 1.6 mm is

based on a similar layout.

Note: The layout example shown is for a full bridge topology using DRV824xQ1 device in SSOP package.

Figure 11-1. Layout example: 4cm x 4 cm x 1.6mm, 4 layer PCB

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Full Bridge Driver Junction Temperature Estimator (Excel-based worksheet)

Texas Instruments, Calculating Motor Driver Power Dissipation application report

Texas Instruments, Current Recirculation and Decay Modes application report

Texas Instruments, PowerPAD™ Made Easy application report

Texas Instruments, PowerPAD™ Thermally Enhanced Package application report

Texas Instruments, Understanding Motor Driver Current Ratings application report

Texas Instruments, Best Practices for Board Layout of Motor Drivers application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

12.4 Trademarks

All trademarks are the property of their respective owners.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and order-able information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

PowerPAD^TMTSSOP - 1.2 mm max height

PWP0028R

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

26X 0.65

28

1

2X

9.8

9.6

8.45

NOTE 3

14

15

0.30

0.19

28X

4.5

4.3

B

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 1.15 MAX

NOTE 5

14

15

2X 0.2 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

5.8

4.9

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

1

28

2.53

1.96

4226330/A 10/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may diﬀer or may not be present.

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EXAMPLE BOARD LAYOUT

PowerPAD^TMTSSOP - 1.2 mm max height

PWP0028R

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(2.53)

METAL COVERED

BY SOLDER MASK

SYMM

28X (1.5)

1

28X (0.45)

28

SEE DETAILS

(R0.05) TYP

(5.8)

26X (0.65)

SYMM

(0.6)

(9.7)

NOTE 9

(1.2) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

14

15

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4226330/A 10/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be ﬁlled, plugged

or tented.

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EXAMPLE STENCIL DESIGN

PowerPAD^TMTSSOP - 1.2 mm max height

PWP0028R

SMALL OUTLINE PACKAGE

(2.53)

BASED ON

0.125 THICK

STENCIL

28X (1.5)

METAL COVERED

BY SOLDER MASK

1

28X (0.45)

28

(R0.05) TYP

26X (0.65)

SYMM

(5.8)

BASED ON

0.125 THICK

STENCIL

15

14

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.83 X 6.48

2.53 X 5.80 (SHOWN)

2.31 X 5.29

0.125

0.15

0.175

2.14 X 4.90

4226330/A 10/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have diﬀerent recommendations for stencil design.

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Figure 13-1. PWP28R: HTSSOP(28) Package Drawing

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13.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

PDRV8245SPWPQ1

PDRV8245PPWPQ1

PDRV8245HPWPQ1

PDRV8245SRXZQ1

HTSSOP

VQFN-HR

PWP

RXZ

28

16

2500

5000

330

16.4

12.4

6.0

3.3.

10.2

3.3

1.8

1.1

12.0

8.0

16.0

12.0

Q1

Submit Document Feedback

73

Product Folder Links: DRV8245-Q1

DRV8245-Q1

SLVSFJ1A – NOVEMBER 2021 – REVISED DECEMBER 2021

www.ti.com

TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

HTSSOP

Package Drawing Pins

SPQ

2500

5000

Length (mm) Width (mm)

Height (mm)

PDRV8245SPWPQ1

PDRV8245PPWPQ1

PDRV8245HPWPQ1

PDRV8245SRXZQ1

PWP

RXZ

28

16

367

38

35

HTSSOP

VQFN-HR

74

Submit Document Feedback

Product Folder Links: DRV8245-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DRV8245HQRXZRQ1

VQFN-

HR

RXZ

16

3000

330.0

12.4

3.8

5.8

1.2

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN-HR RXZ 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

DRV8245HQRXZRQ1

3000

Pack Materials-Page 2

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RXZ0016A

A

3.6

3.4

B

PIN 1 INDEX AREA

5.6

5.4

0.100 MIN

(0.130)

SECTION A-A

TYPICAL

C

1 MAX

0.05

0.00

0.08 C

3.6

3.4

2X

(0.2) TYP

1.15

0.95

(0.15) TYP

8X (0.4) TYP

(0.16)

7

1.9

1

0.3

0.2

0.1

12X

C A B

8

0.05

C

0.2

0

1.725

1.525

PKG

4X

0.7

1.375

1.875

2.375

PIN1 ID

0.3

10X

0.2

0.1

C A B

0.05

C

12

1

13

16

0.55

0.35

(OPTIONAL)

10X

4226099/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RXZ0016A

10X (0.65)

10X (0.25)

16

(2.625)

(2.375)

1

11

(1.875)

(1.375)

8X (0.4) TYP

8X (0.25)

(R0.05) TYP

(0.7)

(0)

PKG

(0.2)

(1)

7

(0.35) TYP

6

(1.9)

(2.325)

(1.25)

SOLDER MASK

OPENING

4X

(0.25)

4X (1.825)

METAL UNDER

SOLDER MASK

2X (3.9)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226099/B 11/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RXZ0016A

4X (1.85)

16

10X (0.65)

(2.625)

1

(2.375)

(1.875)

(1.375)

11

10X (0.25)

(0.2)

8X (0.4) TYP

8X (0.25)

(R0.05) TYP

(0.7)

(0)

PKG

(0.2)

(1)

7

(0.35) TYP

6

(1.9)

(0.2)

(2.625)

4X (0.65)

4X

(0.25)

4X (1.825)

METAL UNDER

SOLDER MASK

2X (3.9)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 15X

PAD 4: 94%; PAD 7: 88%

4226099/B 11/2020

NOTES: (continued)

5.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

PWP 28

4.4 x 9.7, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224765/B

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8245SQRXZRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有集成电流检测和反馈功能的汽车类 40V、32A H 桥驱动器 \| RXZ \| 16 \| -40 to 125 驱动驱动器
文件：	总83页 (文件大小：4476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8245SQRXZRQ1 [TI]

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