DRV8300N [TI]
DRV8300: Three-Phase BLDC Gate Driver;
| 型号： | DRV8300N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8300: Three-Phase BLDC Gate Driver 栅 |
| 文件： | 总27页 (文件大小：1066K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8300
SLVSFG5 – SEPTEMBER 2020
DRV8300: Three-Phase BLDC Gate Driver
and GVDD for the low-side MOSFETs. The Gate
Drive architecture supports peak up to 750-mA source
and 1.5-A sink currents.
1 Features
•
Triple Half-Bridge Gate driver
– Drives 3 High-Side and 3 Low-Side N-Channel
MOSFETs (NMOS)
Integrated Bootstrap Diodes (DRV8300D devices)
Supports Inverting and Non-Inverting INLx inputs
Bootstrap gate drive architecture
– 750-mA source current
The phase pins SHx is able to tolerate the significant
negative voltage transients; while high side gate driver
supply BSTx and GHx is able to support to higher
positive voltage transients (115-V) abs max voltage
which improves robustness of the system. Small
propagation delay and delay matching specifications
minimize the dead-time requirement which further
improves efficiency. Undervoltage protection is
provided for both low and high side through GVDD
and BST undervoltage lockout.
•
•
•
– 1.5-A Sink current
•
•
•
Low leakage current on SHx pins (<55 µA)
Absolute maximum BSTx voltage upto 115-V
Supports negative Trasients upto -22-V on SHx
pins
Buit-in cross conduction prevention
Adjustable Deadtime through DT pin for QFN
package variants
Fixed Deadtime insertion of 200 nS for TSSOP
package variants
Supports 3.3-V, and 5-V logic inputs with 20-V Abs
Max
Device Information (1)
•
•
PART NUMBER
PACKAGE
BODY SIZE (NOM)
6.40 mm × 4.40 mm
6.40 mm × 4.40 mm
4.00 mm × 4.00 mm
6.40 mm × 4.40 mm
4.00 mm × 4.00 mm
6.40 mm × 4.40 mm
DRV8300DIPW
TSSOP (20)
DRV8300DPW (2)
DRV8300DRGE (2)
DRV8300NPW (2)
DRV8300NRGE (2)
DRV8300NIPW (2)
TSSOP (20)
VQFN (24)
TSSOP (20)
VQFN (24)
TSSOP (20)
•
•
•
•
4 nS typical propogation delay matching
Compact QFN and TSSOP packages and
footprints
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Device available for preview only
•
•
Efficient system design with Power Blocks
Integrated protection features
– BST undervoltage lockout (BSTUV)
– GVDD undervoltage (GVDDUV)
PVDD
GVDD
DBx
BSTA, BSTB, BSTC
GVDD
INHA
INHB
INHC
GHA, GHB, GHC
SHA, SHB, SHC
2 Applications
MCU
DRV8300D
•
•
•
•
•
•
•
E-Bikes, E-Scooters, and E-Mobility
Fans, Pumps, and Servo Drives
Brushless-DC (BLDC) Motor Modules and PMSM
Cordless Garden and Power Tools, Lawnmowers
Cordless Vacuum Cleaners
INLA
INLB
INLC
GLA, GLB. GLC
GND
Repeated for 3
phases
Simplified Schematic for DRV8300D
Drones, Robotics, and RC Toys
Industrial and Logistics Robots
GVDD
DBx
3 Description
PVDD
BSTA, BSTB, BSTC
DRV8300 family of devices provide three half-bridge
gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. The DRV8300D
generates the correct gate drive voltages using an
integrated bootstrap diode and external capacitor for
the high-side MOSFETs and GVDD for the low-side
MOSFETs. The DRV8300N generates the correct
gate drive voltages using an external bootstrap diode
and external capacitor for the high-side MOSFETs
GVDD
INHA
INHB
INHC
GHA, GHB, GHC
SHA, SHB, SHC
MCU
DRV8300N
INLA
INLB
INLC
GLA, GLB. GLC
GND
Repeated for 3
phases
Simplified Schematic for DRV8300N
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
DRV8300
SLVSFG5 – SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings Comm ...................................................6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
7.6 Timing Diagrams.........................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................15
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 Documentation Support.......................................... 22
12.3 Related Links.......................................................... 22
12.4 Receiving Notification of Documentation Updates..22
12.5 Support Resources................................................. 22
12.6 Trademarks.............................................................22
12.7 Electrostatic Discharge Caution..............................22
12.8 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2020
*
Initial Release
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SLVSFG5 – SEPTEMBER 2020
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5 Device Comparison Table
Integrated Bootstrap
Diode
GLx polarity with
respect to INLx Input
DEVICE
Package
Deadtime
DRV8300DI
20-Pin TSSOP
20-Pin TSSOP
24-Pin VQFN
20-Pin TSSOP
24-Pin VQFN
20-Pin TSSOP
Yes
Yes
Yes
No
Inverted
Non-Inverted
Fixed
Fixed
DRV8300D(1)
Non-Inverted or Inverted
Non-Inverted
Variable
Fixed
DRV8300N(1)
DRV8300NI(1)
No
Non-Inverted or Inverted
Inverted
Variable
Fixed
No
1. Device is available for preview only
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6 Pin Configuration and Functions
INLA
INLB
1
2
3
4
5
6
18 SHA
17
16
BSTB
GHB
DRV8300
INLC
GVDD
15 SHB
PowerPAD
14
MODE
GND
BSTC
13
GHC
Figure 6-1. DRV8300D, DRV8300N RGE Package 24-Pin VQFN With Exposed Thermal Pad Top View
Table 6-1. Pin Functions—24-Pin DRV8300 Devices
PIN
TYPE(1)
DESCRIPTION
NAME
BSTA
BSTB
BSTC
DT
NO.
20
17
14
21
19
16
13
11
10
9
O
O
O
I
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
Bootstrap output pin. Connect capacitor between BSTC and SHC
Deadtime input pin. Connect resistor to ground for variable deadtime, fixed deadtime when left it floating
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
GHA
GHB
GHC
GLA
O
O
O
O
O
O
I
GLB
GLC
INHA
INHB
INHC
INLA
INLB
INLC
22
23
24
1
I
I
I
2
I
3
I
Mode Input controls polarity of GLx compared to INLx inputs.
MODE
5
I
Mode pin floating: GLx output polarity same(Non-Inverted) as INLx input
Mode pin to GVDD: GLx output polarity inverted compared to INLx input
NC
7, 8
6
NC
No internal connection. This pin can be left floating or connected to system ground.
Device ground.
GND
SHA
SHB
SHC
PWR
18
15
12
I
I
I
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance
between the GVDD and GND pins.
GVDD
4
PWR
(1) PWR = power, I = input, O = output, NC = no connection
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1
2
3
4
5
6
INHA
20
19
18
17
16
15
14
13
12
11
BSTA
INHB
INHC
GHA
SHA
BSTB
GHB
INLA
INLB
INLC
GVDD
GND
GLC
DRV8300
SHB
BSTC
GHC
7
8
SHC
GLA
9
GLB
10
Figure 6-2. DRV8300D, DRV8300N, DRV8300DI, DRV8300NI PW Package 20-Pin TSSOP Top View
Table 6-2. Pin Functions—20-Pin DRV8300 Devices
PIN
TYPE1
DESCRIPTION
NAME
BSTA
BSTB
BSTC
GHA
GHB
GHC
GLA
NO.
20
17
14
19
16
13
11
10
9
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
O
Bootstrap output pin. Connect capacitor between BSTB and SHB
O
Bootstrap output pin. Connect capacitor between BSTC and SHC
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Device ground.
O
O
O
GLB
O
GLC
O
INHA
INHB
INHC
INLA
INLB
INLC
GND
SHA
1
I
2
I
3
I
4
I
5
I
6
I
8
PWR
18
15
12
I
I
I
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
SHC
Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance
between the GVDD and GND pins.
GVDD
7
PWR
1. PWR = power, I = input, O = output, NC = no connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-22
MAX UNIT
Gate driver regulator pin voltage
Bootstrap pin voltage
GVDD
21.5
115
V
V
BSTx
Bootstrap pin voltage
BSTx with respect to SHx
21.5
V
Logic pin voltage
INHx, INLx, MODE, DT
VGVDD+0.3
115
V
High-side gate drive pin voltage
High-side gate drive pin voltage
Low-side gate drive pin voltage
High-side source pin voltage
Ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
GHx
V
GHx with respect to SHx
-0.3
-0.3
-22
22
V
GLx
SHx
VGVDD+0.3
100
V
V
–40
–40
–65
125
°C
°C
°C
150
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings Comm
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
5
NOM
MAX UNIT
VGVDD
VSHx
Power supply voltage
GVDD
SHx
20
85
V
V
High-side source pin voltage
-2
Transient 2µs high-side source pin
voltage
VSHx
SHx
-22
85
V
VBST
VBST
VIN
Bootstrap pin voltage
Bootstrap pin voltage
Logic input voltage
PWM frequency
BSTx
5
5
0
0
105
20
V
V
BSTx with respect to SHx
INHx, INLx, MODE, DT
INHx, INLx
GVDD
200
V
fPWM
kHz
Slew rate on SHx pin (DRV8300D and
DRV8300DI)
VSHSL
VSHSL
CBOOT
2
50
1
V/ns
V/ns
µF
Slew rate on SHx pin (DRV8300N and
DRV8300NI)
Capacitor between BSTx and SHx
(DRV8300D and DRV8300DI)
(1)
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
(1) Current flowing through boot diode (DBOOT) needs to be limited for CBOOT > 1µF
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7.4 Thermal Information
DRV8300
PW (TSSOP)
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
51.2
UNIT
20 PINS
91.6
26.3
42.6
1.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
55.9
RθJB
ΨJT
ΨJB
Junction-to-board thermal resistance
28.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.0
42.1
N/A
28.3
RθJC(bot) Junction-to-case (bottom) thermal resistance
9.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
POWER SUPPLIES (GVDD, BSTx)
GVDD standby mode current
TEST CONDITIONS
MIN
TYP
MAX UNIT
INHx = INLX = 0; VBSTx = VGVDD
400
400
2
800
825
4
1400
1400
7
µA
µA
µA
µA
IGVDD
INHx = INLX = Switching @20kHz;
VBSTx = VGVDD; NO FETs connected
GVDD active mode current
ILBSx
Bootstrap pin leakage current
VBSTx = VSHx = 85V; VGVDD = 0V
INHx = Switching@20kHz
Bootstrap pin active mode transient
leakage current
ILBS_TRAN
30
105
220
Bootstrap pin active mode leakage static
current
ILBS_DC
IL
INHx = High
30
0
85
12
55
150
µA
µA
µA
INHx = INLX = 0; VBSTA,B,C = VSHA,B,C
85V; VGVDD = 0V
=
Leakage current
INHx = INLX = 0; VBSTx - VSHx = 12V;
VSHx = 0 to 85V
ILSHx
High-side source pin leakage current
30
80
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL
Input logic low voltage
Input logic high voltage
Input hysteresis
0.8
V
V
VIH
2.0
VHYS
100
0
mV
VPIN (Pin Voltage) = 0 V; INLx in non-
inverting mode
-1
5
1
30
µA
µA
µA
µA
IIL_INLx
INLx Input logic low current
INLx Input logic high current
VPIN (Pin Voltage) = 0 V; INLx in inverting
mode
20
20
VPIN (Pin Voltage) = 5 V; INLx in non-
inverting mode
5
30
IIH_INLx
VPIN (Pin Voltage) = 5 V; INLx in inverting
mode
0
0.5
1.5
IIL
INHx, MODE Input logic low current
INHx, MODE Input logic high current
INHx Input pulldown resistance
INLx Input pulldown resistance
INLx Input pullup resistance
VPIN (Pin Voltage) = 0 V;
VPIN (Pin Voltage) = 5 V;
To GND
-1
5
0
20
1
30
µA
µA
kΩ
kΩ
kΩ
kΩ
IIH
RPD_INHx
RPD_INLx
RPU_INLx
RPD_MODE
120
120
120
120
200
200
200
200
280
280
280
280
To GND, INLx in non-inverting mode
To INT_5V, INLx in inverting mode
To GND
MODE Input pulldown resistance
GATE DRIVERS (GHx, GLx, SHx, SLx)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
VGHx_LO
High-side gate drive low level voltage
0
0.15
0.35
V
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4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-side gate drive high level voltage
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
VGHx_HI
VGLx_LO
VGLx_HI
0.3
0.6
1.2
0.35
1.2
V
V
V
(VBSTx - VGHx
)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
Low-side gate drive low level voltage
0
0.15
0.6
Low-side gate drive high level voltage
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
0.3
(VGVDD - VGHx
)
IDRIVEP_HS
IDRIVEN_HS
IDRIVEP_LS
IDRIVEN_LS
High-side peak source gate current
High-side peak sink gate current
Low-side peak source gate current
Low-side peak sink gate current
GHx-SHx = 12V
GHx-SHx = 0V
GLx = 12V
400
850
400
850
750
1500
750
1200
2100
1200
2100
mA
mA
mA
mA
GLx = 0V
1500
INHx, INLx to GHx, GLx; VGVDD = VBSTx
- VSHx > 8V; SHx = 0V, No load on GHx
and GLx
tPD
Input to output propagation delay
70
0
125
4
180
25
ns
ns
GHx turning OFF to GLx turning ON,
GLx turning OFF to GHx turning ON;
VGVDD = VBSTx - VSHx > 8V; SHx = 0V,
No load on GHx and GLx
tPD_match
Matching propagation delay per phase
GHx/GLx turning ON to GHy/GLy turning
ON, GHx/GLx turning OFF to GHy/GLy
Matching propagation delay phase to
phase
tPD_match
0
4
25
ns
turning OFF; VGVDD = VBSTx - VSHx
>
8V; SHx = 0V, No load on GHx and GLx
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
-
-
tR_GLx
tR_GHx
tF_GLx
tF_GHx
GLx rise time (10% to 90%)
GHx rise time (10% to 90%)
GLx fall time (90% to 10%)
GHx fall time (90% to 10%)
10
10
5
24
24
12
12
50
50
30
30
ns
ns
ns
ns
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
-
CLOAD = 1000 pF; VGVDD = VBSTx
VSHx > 8V; SHx = 0V
-
5
DT pin floating
150
150
215
215
280
280
ns
ns
ns
ns
DT pin connected to GND
40 kΩ between DT pin and GND
400 kΩ between DT pin and GND
tDEAD
Gate drive dead time
150
200
260
1500
2000
2500
Minimum input pulse width on INHx,
INLx that changes the output on GHx,
GLx
tPW_MIN
40
70
150
ns
BOOTSTRAP DIODES (DRV8300D, DRV8300DI)
IBOOT = 100 µA
IBOOT = 100 mA
0.45
2
0.7
2.3
0.85
3.1
V
V
VBOOTD
Bootstrap diode forward voltage
Bootstarp dynamic resistance (ΔVBOOTD
/
RBOOTD
IBOOT = 100 mA and 80 mA
11
15
25
Ω
ΔIBOOT
)
PROTECTION CIRCUITS
Supply rising
Supply falling
4.45
4.2
4.6
4.7
4.4
V
V
Gate Driver Supply undervoltage lockout
(GVDDUV)
VGVDDUV
4.35
VGVDDUV_HY
Gate Driver Supply UV hysteresis
Rising to falling threshold
260
5
270
10
4.2
4
290
12.5
4.8
mV
µs
V
S
Gate Driver Supply undervoltage
deglitch time
tGVDDUV
Boot Strap undervoltage lockout (VBSTx
VSHx
-
-
Supply rising
Supply falling
3.6
3.5
)
VBSTUV
Boot Strap undervoltage lockout (VBSTx
VSHx
4.5
V
)
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4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
200
10
MAX UNIT
VBSTUV_HYS Bootstrap UV hysteresis
Rising to falling threshold
mV
tBSTUV
Bootstrap undervoltage deglitch time
6
22
µs
7.6 Timing Diagrams
INHx/INLx
GHx/GLx
50%
50%
tPD
tPD
Figure 7-1. Propagation Delay(tPD
)
INHx
INLx
GHx
GLx
tPD_match
tPD_match
Figure 7-2. Propagation Delay Match (tPD_match
)
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8 Detailed Description
8.1 Overview
The DRV8300 family of devices is a gate driver for three-phase motor drive applications. These devices
decrease system component count, saves PCB space and cost by integrating three independent half-bridge
gate drivers and optional bootstrap diodes.
DRV8300D device integrates bootstrap diode used along with boot capacitor to generate voltage to drive high
side N-channel MOSFET. External bootstrap diode along with capacitor is needed for DRV8300N devices.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive 750-mA
source, 1.5-A sink peak currents with total 30-mA average output current combined high and low side drivers. A
bootstrap capacitor and GVDD supply generates the voltage of the high-side gate drive. The GVDD supply
voltage is used to generate voltage for the low-side gate driver.
The DRV8300 family of devices are available in 0.5-mm pitch QFN and 0.65-mm pitch TSSOP surface-mount
packages. The QFN size is 4 × 4 mm (0.5-mm pin pitch) for the 24-pin package, and TSSOP size is 6.5 × 6.4
mm (0.65-mm pin pitch) for the 20-pin package.
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8.2 Functional Block Diagram
GVDD
CGVDD
PVDD
GVDD
HS
BSTA
GHA
SHA
CBSTA
RGHA
INHA
HS
INT_5V
GVDD
LS
INLA/INLA
RGLA
GLA
LS
MODE**
Gate Driver
GVDD
BSTB
GHB
SHB
PVDD
CBSTB
RGHB
HS
HS
INHB
INT_5V
Input logic
control
GVDD
LS
INLB/INLB
RGLB
GLB
LS
Shoot-
Through
Prevention
MODE**
Gate Driver
GVDD
PVDD
BSTC
GHC
SHC
CBSTC
RGHC
INHC
HS
HS
INT_5V
GVDD
LS
Gate Driver
INLC/INLC
RGLC
GLC
LS
MODE**
DT**
MODE**
GND
PowerPAD
** QFN-24 Package
Figure 8-1. Block Diagram for DRV8300D
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GVDD
GVDD
CGVDD
PVDD
BSTA
CBSTA
RGHA
INHA
GHA
SHA
HS
LS
HS
INT_5V
GVDD
LS
INLA/INLA
RGLA
GLA
MODE**
Gate Driver
BSTB
GHB
SHB
PVDD
CBSTB
RGHB
HS
HS
INHB
INT_5V
Input logic
control
GVDD
LS
INLB/INLB
RGLB
GLB
LS
Shoot-
Through
Prevention
MODE**
Gate Driver
PVDD
BSTC
GHC
SHC
CBSTC
RGHC
INHC
HS
HS
INT_5V
GVDD
LS
Gate Driver
INLC/INLC
RGLC
GLC
LS
MODE**
DT**
MODE**
GND
PowerPAD
** QFN-24 Package
Figure 8-2. Block Diagram for DRV8300N
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8.3 Feature Description
8.3.1 Three BLDC Gate Drivers
The DRV8300 integrates three half-bridge gate drivers, each capable of driving high-side and low-side N-
channel power MOSFETs. Input on GVDD provides the gate bias voltage for the low-side MOSFETs. The high
voltage is generated using bootstrap capacitor and GVDD supply. DRV8300 device integrates the bootstrap
diode. The half-bridge gate drivers can be used in combination to drive a three-phase motor or separately to
drive other types of loads.
8.3.1.1 Gate Drive Timings
8.3.1.1.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the input deglitcher delay and the delay through the analog gate
drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. The analog gate drivers have a small delay that contributes to the overall propagation delay of the
device.
8.3.1.1.2 Deadtime and Cross-Conduction Prevention
In the DRV8300, high- and low-side inputs operate independently, with an exception to prevent cross conduction
when high and low side are turned ON at same time. The DRV8300 turns OFF high- and low- side output to
prevent shoot through when high- and low-side inputs are logic high at same time.
The DRV8300 also provides deadtime insertion to prevents both external MOSFETs of each power-stage from
switching on at the same time. In devices with DT pin (QFN package device), deadtime can be linearily adjusted
between 200 nS to 2000 nS by connecting resistor between DT and ground. When DT pin left floating, fixed
deadtime of 200 nS (Typical value) is inserted. The value of resistor can be caculated using following equation.
&A=@PEIA (J5)
4&6(GÀ) =
5
In device without DT pin (TSSOP package device), fixed deadtime of 200 nS (Typical value) is inserted to
prevent high and low side gate output turning on at same time.
INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
Figure 8-3. Cross Conduction Prevention and Deadtime Insertion
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8.3.1.2 Mode (Inverting and non inverting INLx)
The DRV8300 has flexibility of accepting different kind of inputs on INLx. In devices with MODE pin (QFN
package device), the DRV8300 provides option of GLx output inverted or non-inverted compared to polarity of
signal on INLx pin. When MODE pin is left floating INLx is configured to be in non-inverting mode and GLx
output is in phase with INLx (see Figure 8-4), whereas when MODE pin is connected to GVDD, GLx output is out
of phase with inputs (see Figure 8-5). In devices without MODE pin (TSSOP package device), there are different
device option available for inverting and non inverting inputs (see Section 5)
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 8-4. Non-Inverted INLx inputs
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 8-5. Inverted INLx inputs
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8.3.2 Pin Diagrams
Figure 8-6 shows the input structure for the logic level pins INHx, INLx. INHx and INLx has passive pull down, so
when inputs are floating the output of gate driver will be pulled low. Figure 8-7 shows the input structure for the
logic level pin inverted INLx. INLx in inverted mode has passive pull up, so when inputs are floating the output of
gate driver will be pulled low.
INT_5V
INPUT
INPUT
200 kꢀ
Logic High
Logic Low
Logic High
Logic Low
INHx
INLx
INLx
200 kꢀ
Figure 8-7. Inverted INLx Logic-Level Input Pin
Structure
Figure 8-6. INHx and non-inverted INLx Logic-Level
Input Pin Structure
8.3.3 Gate Driver Protective Circuits
The DRV8300 is protected against BSTx undervoltage and GVDD undervoltage events.
Table 8-1. Fault Action and Response
FAULT
CONDITION
GATE DRIVER
RECOVERY
Automatic:
VBSTx > VBSTUV and low to high
PWM edge detected on INHx pin
VBSTx undervoltage
(BSTUV)
VBSTx < VBSTUV
GHx - Hi-Z
GVDD undervoltage
(GVDDUV)
Automatic:
VGVDD > VGVDDUV
VGVDD < VGVDDUV
Hi-Z
8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
The DRV8300 has separate voltage comparator to detect undervoltage condition for each phase. If at any time
the supply voltage on the BSTx pin falls lower than the VBSTUV threshold, high side external MOSFETs of that
particular phase is disabled by disabling (Hi-Z) GHx pin. Normal operation starts again when the BSTUV
condition clears and low to high PWM edge detected on INHx input on the same phase BSTUV was detected.
BSTUV protection ensures that high side gate driver are not switched when BSTx pin has lower value.
8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
If at any time the voltage on the GVDD pin falls lower than the VGVDDUV threshold voltage, all of the external
MOSFETs are disabled. Normal operation starts again GVDDUV condition clears. GVDDUV protection ensures
that gate driver are not switched when GVDD input is at lower value.
8.4 Device Functional Modes
Whenever the GVDD > VGVDDUVand VBSTX > VBSTUV the device is in operating (active) mode, in this condition
gate driver output GHx and GLX will follow respective inputs INHx and INLx.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8300 family of devices is primarily used in applications for three-phase brushless DC motor control. The
design procedures in the Section 9.2 section highlight how to use and configure the DRV8300.
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9.2 Typical Application
GVDD
GVDD
GND
CGVDD
PVDD
External
Supply
GND
BSTA
CBSTA
RGHA
GHA
SHA
RGLA
INHA
INLA
GLA
INHB
INLB
PWM
MCU
PVDD
BSTB
INHC
INLC
CBSTB
RGHB
GHB
SHB
RGLB
DRV8300D
GLB
PVDD
GVDD
BSTC
BSTC
CBSTC
RGHC
MODE**
GHC
SHC
GND or Floating
GHC
SHC
DT**
RGLC
GLC
** QFN-24 Package
GLC
INA+
INB+ INC+
R
R
INA-
INB-
INC-
R
N-
INx+
INx-
N-
N+
R
R
IN-
N+
œ
OUT
IN+
+
Reference
Voltage
V
REF
R
Current Sense Amplifier 1x or 3x
+
œ
Figure 9-1. Application Schematic
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9.2.1 Design Requirements
Table 9-1 lists the example design input parameters for system design.
Table 9-1. Design Parameters
EXAMPLE DESIGN PARAMETER
Gate Supply Voltage
Gate Charge
REFERENCE
VGVDD
QG
EXAMPLE VALUE
12 V
50 nC
Switching frequency
fSW
25 kHz
Slew Rate of MOSFET
tSLEW
100 nS
9.2.2 Detailed Design Procedure
Bootstrap Capacitor and GVDD Capacitpr Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 1 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F8$116&F8
$5678
(1)
=12V – 0.85V – 4.5V = 6.65V
where
•
•
•
VGVDD is the supply voltage of the gate drive
VBOOTD is the forward voltage drop of the bootstrap diode
VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and VDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value of 0.5 V.
The total charge needed per switching cycle can be estimated with Equation 2:
+.$5_64#05
3616 = 3) +
B
59
(2)
=50nC + 220uA/20kHz = 50nC + 11nC = 61nC
where
•
•
•
QG is the total MOSFET gate charge
ILBS_TRAN is the boostrap pin leakage current
fSW is the is the PWM frequency
The minimum bootstrap capacitor can then be estimated as below:
3
%
=
616W
$56_/+0
¿8
$56:
(3)
= 111nC / 4.5V = 24.7nF
The calculated value of minimum bootstrap capacitor is 24.7 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible. For this
application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R As a general rule
the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value (generally 10 times
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the bootstrap capacitor value). For this application choose a CVDD capacitor with the following specifications: 1
µF , 25 V, X7R CVDD capacitor is placed across GVDD and GND pin of the gate driver. The bootstrap and bias
capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a voltage rating at least
twice the maximum voltage that it will be exposed to. Choose this value because most ceramic capacitors lose
significant capacitance when biased. This value also improves the long term reliability of the system. The
capacitor should be rated for at least 2x the GVDD voltage, so 25V rated capacitors are recommended.
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10 Power Supply Recommendations
The DRV8300 is designed to operate from an input voltage supply (GVDD) range from 4.8 V to 20 V. A local
bypass capacitor should be placed between the GVDD and GND pins. This capacitor should be located as close
to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is recommended to
use two capacitors across GVDD and GND: a low capacitance ceramic surface-mount capacitor for high
frequency filtering placed very close to GVDD and GND pin, and another high capacitance value surfacemount
capacitor for device bias requirements. In a similar manner, the current pulses delivered by the GHx pins are
sourced from the BSTx pins. Therefore, capacitor across the BSTx to SHx is recommended, it should be high
enough capacitance value capacitor to deliver GHx pulses
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11 Layout
11.1 Layout Guidelines
•
Low ESR/ESL capacitors must be connected close to the device between GVDD and VSS pins and between
BSTx and SHx pins to support high peak currents drawn from GVDD and BSTx pins during the turn-on of the
external MOSFETs.
•
•
•
To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground.
In order to avoid large negative transients on the switch node (SHx) pin, the parasitic inductances between
the source of the high-side MOSFET and the source of the low-side MOSFET must be minimized.
In order to avoid unexpected transients, the parasitic inductance of the GHx, SHx, and GLx connections must
be minimized. Minimize the length and number of vias wherever possible. Minimum10 mil trace is
recommended.
•
•
Traces for GHx and SHx must be routed in parallel
Resistance between DT and GND must be place close to device
11.2 Layout Example
BSTx and SHx
cap close to
device
DT resistance
close to device
GVDD Cap close
to device
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
12.2 Documentation Support
12.2.1 Related Documentation
•
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
3000
3000
3000
3000
3000
1
(1)
(2)
(3)
(4/5)
(6)
DRV8300DIPWR
DRV8300DPWR
DRV8300DRGER
DRV8300NIPWR
DRV8300NPWR
DRV8300NRGER
PDRV8300DIPWR
PREVIEW
TSSOP
TSSOP
VQFN
PW
20
20
24
20
20
24
20
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8300DI
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
PW
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
8300D
8300D
8300NI
8300N
8300N
RGE
PW
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
RGE
PW
Green (RoHS
& no Sb/Br)
TSSOP
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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