DRV8304 [TI]
具有电流分流放大器的 40V（最大值）三相智能栅极驱动器;
| 型号： | DRV8304 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流分流放大器的 40V（最大值）三相智能栅极驱动器 放大器 栅极驱动 驱动器 |
| 文件： | 总66页 (文件大小：2660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
DRV8304 38V 三相智能栅极驱动器
1 特性
3 说明
1
•
6V 至 38V、三个半桥栅极驱动器，集成了 3 个电
流检测放大器 (CSA)
DRV8304 器件是一款集成式栅极驱动器，适用于需要
12V 和 24V 直流电源轨的三相无刷直流 (BLDC) 电机
应用 。这些 应用 包括 BLDC 电机的场定向控制
(FOC)、正弦电流控制和梯形电流控制。该器件集成了
三个电流检测放大器 (CSA)，可感测 BLDC 电机的相
电流，从而获得最佳的 FOC 和电流控制系统实现方
案。AUTOCAL 功能可以自动校准 CSA 失调误差，因
此可实现精确的电流检测。
–
–
–
–
40V 绝对最大额定值
针对 12V 和 24V 直流电源轨进行了全面优化
驱动高侧和低侧 N 沟道 MOSFET
支持 100% PWM 占空比
•
智能栅极驱动架构
–
通过可调压摆率控制实现更出色的 EMI 和 EMC
性能
该器件基于智能栅极驱动 (SGD) 架构，因此无需任何
外部栅极组件（电阻器和齐纳二极管），同时为外部
FET 提供全面保护。SGD 架构可优化死区时间以避免
出现任何击穿问题，在通过栅极压摆率控制技术降低电
磁干扰 (EMI) 方面带来了灵活性，并可通过 VGS 握手
和死区插入方法防止任何栅极短路问题。强下拉电流还
可防止任何 dv/dt 栅极导通。
–
通过 VGS 握手和最小死区时间插入方法避免击
穿
–
–
15mA 至 150mA 峰值拉电流
30mA 至 300mA 峰值灌电流
•
•
6x、3x、1x 和独立 PWM 模式
支持 120º 传感器式运行模式
集成栅极驱动器电源
–
该器件支持各种 PWM 控制模式（1x、3x、6x 和独立
模式），从而使用简单接口连接到可通过 30mA、3.3V
内部稳压器进行供电的控制电路。这些模式可根据具体
的电机控制要求减少控制器的输出外设数量，并提供控
制灵活性。该器件还具有 1x 模式，因此可通过使用内
部阻塞换向表对 BLDC 电机进行传感器式梯形控制。
该器件也可以配置为以独立模式驱动多个负载（如电磁
阀）。
–
–
高侧倍增电荷泵
低侧线性稳压器
•
集成三个分流放大器
–
–
可调增益（5、10、20、40 V/V）
双向或单向支持
•
•
•
•
•
SPI（预览）或硬件器件型号
支持 1.8V、3.3V 和 5V 逻辑输入
低功耗睡眠模式
3.3V、30mA 线性稳压器
集成式保护 特性
器件信息(1)
器件型号
DRV8304
封装
接口
–
–
–
–
–
–
–
VM 欠压闭锁 (UVLO)
硬件
SPI(2)
VQFN (40)
电荷泵欠压 (CPUV)
MOSFET VDS 过流保护 (OCP)
MOSFET 击穿保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) SPI 器件选择仅供预览。
栅极驱动器故障 (GDF)
热警告和热关断 (OTW/OTSD)
故障状态指示器 (nFAULT)
简化原理图
6 to 38 V
PWM
2 应用
DRV8304
Gate
Drive
ENABLE
3 Half Bridge
Smart Gate Driver
M
•
•
•
•
•
•
打印机
H/W
nFAULT
Current
Sense
BLDC 电机模块
白色家电
Sense Output
3x Shunt Amplifiers
Built-In Protection
CPAP、风扇和泵
无人机、机器人和遥控玩具
ATM 和点钞机
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
English Data Sheet: SLVSE39
DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
目录
7.6 Register Maps......................................................... 37
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 45
Power Supply Recommendations...................... 53
9.1 Bulk Capacitance Sizing ......................................... 53
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements.............................................. 10
6.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 35
7.5 Programming........................................................... 35
8
9
10 Layout................................................................... 54
10.1 Layout Guidelines ................................................. 54
10.2 Layout Example .................................................... 55
11 器件和文档支持 ..................................................... 56
11.1 器件支持................................................................ 56
11.2 文档支持................................................................ 56
11.3 接收文档更新通知 ................................................. 56
11.4 社区资源................................................................ 56
11.5 商标....................................................................... 57
11.6 静电放电警告......................................................... 57
11.7 术语表 ................................................................... 57
12 机械、封装和可订购信息....................................... 57
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2018) to Revision B
Page
•
已更改 将器件的 SPI 版本状态更改成了预览.......................................................................................................................... 1
Changes from Original (November 2017) to Revision A
Page
•
已更改 将数据表状态从预告信息 更改为生产数据 .................................................................................................................. 1
2
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
5 Pin Configuration and Functions
DRV8304H RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
DRV8304S (Preview) RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
ENABLE
GAIN
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
ENABLE
nSCS
SCLK
SDI
VCP
VDS
VCP
VM
IDRIVE
MODE
nFAULT
VREF
SOA
VM
VDRAIN
GHA
SHA
VDRAIN
GHA
SHA
SDO
Thermal
Pad
Thermal
Pad
nFAULT
VREF
SOA
GLA
GLA
SPA
SOB
SPA
SOB
SNA
SOC
SNA
SOC
Not to scale
Not to scale
Pin Functions
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8304H
DRV8304S
AGND
CAL
32
32
PWR Device analog ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and
perform offset calibration.
31
2
31
I
Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic
capacitor between the CPH and CPL pins.
CPH
CPL
2
1
PWR
PWR
Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic
capacitor between the CPH and CPL pins.
1
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic
DVDD
33
30
33
30
PWR capacitor between the DVDD and AGND pins. This regulator can source up to 30
mA externally.
Gate driver enable. When this pin is logic low the device enters a low power sleep
ENABLE
I
mode. An 5 to 32-µs low pulse can be used to reset fault conditions.
GAIN
GHA
GHB
GHC
GLA
GLB
GLC
29
6
—
6
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
O
O
O
O
O
O
15
16
8
15
16
8
13
18
13
18
Gate drive output current setting. This pin is a 7 level input pin set by an external
resistor.
IDRIVE
INHA
27
34
—
I
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHA).
34
(1) PWR = power, I = input, O = output, OD = open-drain
Copyright © 2017–2018, Texas Instruments Incorporated
3
DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
Pin Functions (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8304H
DRV8304S
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHB).
INHB
INHC
INLA
INLB
36
36
I
I
I
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHC).
38
35
37
38
35
37
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLA).
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLB).
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLC).
INLC
39
26
25
39
—
25
I
MODE
nFAULT
I
OD
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and
requires an external pullup resistor.
nSCS
—
29
40
Serial chip select. A logic low on this pin enables serial interface communication.
PGND
40
PWR Device power ground. Connect to system ground.
Serial clock input. Serial data is shifted out and captured on the corresponding
rising and falling edge on this pin.
SCLK
SDI
—
—
—
28
27
26
I
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin
requires an external pullup resistor.
SDO
OD
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
7
7
I
I
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
14
17
10
11
20
23
22
21
14
17
10
11
20
23
22
21
I
I
I
I
O
O
O
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
SPA
9
12
19
3
9
12
19
3
I
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
SPB
I
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
SPC
I
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor
between the VCP and VM pins.
VCP
PWR
High-side MOSFET drain sense input. Connect to the common point of the external
MOSFET drains.
VDRAIN
VDS
5
5
I
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external
resistor.
28
—
Gate driver power supply input. Connect to the bridge power supply. Connect a
VM
4
4
PWR X5R or X7R, 0.1-µF, VM-rated ceramic and greater than or equal to 10-uF local
capacitance between the VM and PGND pins.
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-μF,
6.3-V ceramic capacitor between the VREF and AGND pins.
VREF
24
24
PWR
4
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.5
–0.3
–0.3
–0.3
–0.3
MAX
40
UNIT
V
Power supply voltage (VM)
Voltage differential between any ground pin (AGND, DGND, PGND)
Internal logic regulator voltage (DVDD)
MOSFET voltage sense (VDRAIN)
0.5
V
3.8
V
40
V
Charge pump voltage (VCP, CPH)
VM + 13.5
VM
V
Charge pump negative switching pin voltage (CPL)
V
Digital pin voltage (SCLK, SDI, nSCS, ENABLE, VDS, IDRIVE, MODE, GAIN, CAL
INHX, INLX)
–0.3
5.75
V
Open drain output current range (nFAULT, SDO)
Continuous high-side gate pin voltage (GHX)
Pulsed 200 ns high-side gate pin voltage (GHX)
High-side gate voltage with respect to SHX (GHX)
Continuous phase node pin voltage (SHX)
Pulsed 200 ns phase node pin voltage (SHX)
Continuous low-side gate pin voltage (GLX)
Pulsed 200 ns low-side gate pin voltage (GLX)
Gate pin source current (GHX, GLX)
0
–2
5
mA
V
VCP + 0.5
VCP + 0.5
13.5
–5
V
–0.3
–2
V
VM + 2
VM + 2
13.5
V
–5
V
–1
V
–5
13.5
V
Internally limited
Internally limited
–1
A
Gate pin sink current (GHX, GLX)
A
Continuous shunt amplifier input pin voltage (SPX, SNX)
Pulsed 200 ns shunt amplifier input pin voltage (SPX, SNX)
Reference pin input voltage (VREF)
1
2
V
–2
–0.3
–0.3
0
V
5.75
VREF
5
V
Shunt amplifier output pin voltage range (SOX)
Shunt amplifier output pin current range (SOX)
Ambient temperature, TA
V
mA
°C
°C
°C
–40
–40
–65
125
150
150
Junction temperature, TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
6
MAX
38
UNIT
V
VVM
VI
Power supply voltage range
Logic level input voltage range
0
5.5
V
Copyright © 2017–2018, Texas Instruments Incorporated
5
DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
Recommended Operating Conditions (continued)
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
UNIT
kHz
mA
mA
mA
mA
V
(1)
fPWM
IGATE_HS
IGATE_LS
IDVDD
ISO
Applied PWM signal (INHX, INLX)
200
(1)
(1)
(1)
High-side average gate drive current (GHX)
Low-side average gate drive current (GLX)
DVDD external load current
15
15
30
Shunt amplifier output current loading (SOX)
Open drain pull up voltage (nFAULT, SDO)
Open drain output current (nFAULT, SDO)
Operating ambient temperature
0
0
5
VOD
5.5
5
IOD
0
mA
°C
TA
–40
125
(1) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8304
THERMAL METRIC(1)
RHA (VQFN)
32 PINS
35.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
22.6
14.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
14.9
RθJC(bot)
2.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (DVDD, VM)
IVM
VM operating supply current
ENABLE = 1; INHX = 0 V; INLX = 0 V
ENABLE = 0; VVM = 24 V; TA = 25°C
ENABLE = 0, VVM = 24 V, TA = 125°C
ENABLE = 0 V period to reset faults
ENABLE = 0 V to driver tri-stated
5
7
40
mA
µA
µA
µs
µs
ms
V
20
IVMQ
VM sleep mode supply current
(1)
100
40
tRST
Reset pulse time
Sleep time
15
tSLEEP
tWAKE
VDVDD
200
1
Wake-up time
VVM > VUVLO; ENABLE = 3.3 V to output transition
Internal logic regulator voltage IDVDD = 0 to 30 mA
2.9
3.3
3.6
CHARGE PUMP (CPH, CPL, VCP)
VM = 12 to 38 V; IVCP = 0 to 15 mA
VM = 10 V; IVCP = 0 to 10 mA
VM = 8 V; IVCP = 0 to 5 mA
7
6.5
5
10
7.5
6
11.5
9.5
V
V
V
V
VCP operating voltage with
respect to VM
VVCP
7.5
VM = 6 V; IVCP = 0 to 1 mA
3.8
4.3
6.5
LOGIC-LEVEL INPUTS (CAL, INHX, INLX, SCLK, SDI, nSCS)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
0
1.5
100
–1
0.8
5.5
V
V
mV
µA
µA
VPIN (Pin Voltage) = 0 V
VPIN (Pin Voltage) = 5 V
1
IIH
100
(1) Specified by design and characterization data
6
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Pulldown Resistance to AGND
(CAL, INHX, INLX, SCLK,
SDI, nSCS)
RPD
100
kΩ
LOGIC-LEVEL INPUTS (ENABLE)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
0
1.5
100
–10
-5
0.6
5.5
V
V
mV
µA
µA
VPIN (Pin Voltage) = 0 V
10
5
IIH
VPIN (Pin Voltage) = 5 V
FOUR-LEVEL INPUTS (GAIN, MODE)
VI1
VI2
VI3
VI4
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Tied to AGND
45 kΩ ± 5% to AGND
Hi-Z
0
1.2
2
V
V
V
V
Tied to DVDD
3.3
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
VI1
VI2
VI3
VI4
VI5
VI6
VI7
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Input mode 5 voltage
Input mode 6 voltage
Input mode 7 voltage
Tied to AGND
0
0.5
V
V
V
V
V
V
V
18 kΩ ± 5% to AGND
75 kΩ ± 5% to AGND
Hi-Z
1.1
1.65
2.2
75 kΩ ± 5% to DVDD
18 kΩ ± 5% to DVDD
Tied to DVDD
2.8
3.3
OPEN-DRAIN OUTPUTS (nFAULT, SDO)
VOL
IOZ
Output logic low voltage
Output logic high current
IOD = 2 mA
VOD = 5 V
0.1
1
V
–1
µA
GATE DRIVERS (GHX, GLX, SHX)
VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA
VVM = 10 V; IHS_GATE = 0 to 10 mA
VVM = 8 V; IHS_GATE = 0 to 5 mA
VVM = 6 V; IHS_GATE = 0 to 1 mA
VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA
VVM = 10 V; ILS_GATE = 0 to 10 mA
VVM = 8 V; ILS_GATE = 0 to 5 mA
VVM = 6 V; ILS_GATE = 0 to 1 mA
DEAD_TIME = 00b
7
6.5
5
10
7.5
11.5
8.5
7
High-side VGS gate drive
(gate-to-source)
(1)
VGHS
V
V
6
3.8
7.5
5.5
3.5
3
4.3
6.5
12.5
9.5
8.5
6.5
10
7.5
Low-side VGS gate drive (gate-
to-source)
(1)
VGSL
6
4.3
40
DEAD_TIME = 01b
120
200
400
120
500
1000
2000
4000
tDEAD
tDEAD
tDRIVE
Output dead time (SPI Device)
Output dead time (HW Device)
ns
ns
ns
DEAD_TIME = 10b
DEAD_TIME = 11b
TDRIVE = 00b
TDRIVE = 01b
TDRIVE = 10b
TDRIVE = 11b
Peak gate drive time (SPI
Device)
Peak gate drive time (HW
Device)
tDRIVE
4000
ns
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MAX UNIT
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDRIVEP_HS or IDRIVEP__LS = 000b
IDRIVEP_HS or IDRIVEP__LS = 001b
IDRIVEP_HS or IDRIVEP__LS = 010b
IDRIVEP_HS or IDRIVEP__LS = 011b
IDRIVEP_HS or IDRIVEP__LS = 100b
IDRIVEP_HS or IDRIVEP__LS = 101b
IDRIVEP_HS or IDRIVEP__LS = 110b
IDRIVEP_HS or IDRIVEP__LS = 111b
IDRIVE tied to AGND
MIN
TYP
15
15
45
Peak source gate current
(high-side and low-side) (SPI
Device)
60
IDRIVEP
IDRIVEP
IDRIVEN
IDRIVEN
mA
mA
mA
90
105
135
150
15
IDRIVE 18 kΩ (±5%) to AGND
IDRIVE 75 kΩ (±5%) to AGND
IDRIVE Hi-Z ( > 500 kΩ to AGND)
IDRIVE 75 kΩ (±5%) to DVDD
IDRIVE 18 kΩ (±5%) to DVDD
IDRIVE tied to DVDD
45
60
Peak source gate current
(high-side and low-side) (HW
Device)
90
105
135
150
30
IDRIVEN_HS or IDRIVEN_LS = 000b
IDRIVEN_HS or IDRIVEN_LS = 001b
IDRIVEN_HS or IDRIVEN_LS = 010b
IDRIVEN_HS or IDRIVEN_LS = 011b
IDRIVEN_HS or IDRIVEN_LS = 100b
IDRIVEN_HS or IDRIVEN_LS = 101b
IDRIVEN_HS or IDRIVEN_LS = 110b
IDRIVEN_HS or IDRIVEN_LS = 111b
IDRIVE tied to AGND
30
90
Peak sink gate current (high-
side and low-side) (SPI
Device)
120
180
210
270
300
30
IDRIVE 18 kΩ (±5%) to AGND
IDRIVE 75 kΩ (±5%) to AGND
IDRIVE Hi-Z ( > 500 kΩ to AGND)
IDRIVE 75 kΩ (±5%) to DVDD
IDRIVE 18 kΩ (±5%) to DVDD
IDRIVE tied to DVDD
90
120
180
210
270
300
15
Peak sink gate current (high-
side and low-side) (HW
Device)
mA
mA
Source current after tDRIVE
IHOLD
FET holding current
Sink current after tDRIVE
30
GLX pull-down current during GHX tDRIVE period or
vice-versa
ISTRONG
FET hold-off strong pulldown
300
mA
ROFF
tPD
FET gate hold-off resistor
Propagation delay
GHX to SHX and GLX to PGND
150
180
kΩ
INHX/INLX tansition to GHX/GLX transition
250
ns
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b, VREF = 3.3 to 5 V
4.85
9.7
5
10
20
40
5
5.15
10.3
20.6
41.2
5.15
10.3
20.6
41.2
CSA_GAIN = 01b, VREF = 3.3 to 5 V
CSA_GAIN = 10b, VREF = 3.3 to 5 V
CSA_GAIN = 11b, VREF = 3.3 to 5 V
Tied to AGND, VREF = 3.3 to 5 V
45 kΩ ± 5% to AGND, VREF = 3.3 to 5 V
Hi-Z, VREF = 3.3 to 5 V
GCSA
Amplifier gain (SPI Device)
Amplifier gain (HW Device)
V/V
19.4
38.8
4.85
9.7
10
20
40
GCSA
V/V
19.4
38.8
Tied to DVDD, VREF = 3.3 to 5 V
8
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8304
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STEP on SOX = 0.5 V; GCSA = 5 V/V, VREF = 3.3 to
5 V
260
STEP on SOX = 0.5 V; GCSA = 10 V/V, VREF = 3.3
to 5 V
400
700
(1)
tSET
Settling time to ±1%, 30 pF
Common-mode input range
ns
STEP on SOX = 0.5 V; GCSA = 20 V/V, VREF = 3.3
to 5 V
STEP on SOX = 0.5 V; GCSA = 40 V/V, VREF = 3.3
to 5 V
1550
(1)
VSP, COM
–0.5
–5
0.5
5
V
mV
mV
mV
mV
mV
mV
mV
mV
µV/°C
VSP = VSN = 0 V, GCSA = 5, VREF = 3.3 V ± 10%
VSP = VSN = 0 V, GCSA = 10, VREF = 3.3 V ± 10%
VSP = VSN = 0 V, GCSA = 20, VREF = 3.3 V ± 10%
VSP = VSN = 0 V, GCSA = 40, VREF = 3.3 V ± 10%
VSP = VSN = 0 V, GCSA = 5, VREF = 5 V ± 10%
VSP = VSN = 0 V, GCSA = 10, VREF = 5 V ± 10%
VSP = VSN = 0 V, GCSA = 20, VREF = 5 V ± 10%
VSP = VSN = 0 V, GCSA = 40, VREF = 5 V ± 10%
VSP = VSN = 0 V
–2.5
–1.5
–1.25
–7
2.5
1.5
1.25
7
VOFF
Input offset error
–3.5
–2.25
–1.5
3.5
2.25
1.5
(1)
VDRIFT
Drift offset
10
SOX output voltage linear
range
VVREF
–
(1)
VLINEAR
0.25
V
0.25
VVREF
–
VSP = VSN = 0 V, VREF_DIV = 0b
VSP = VSN = 0 V, VREF_DIV = 1b
VSP = VSN = 0 V
SOX output voltage bias (SPI
Device)
0.3
VBIAS
V
VVREF/2
SOX output voltage bias (HW
Device)
VBIAS
IBIAS
VVREF/2
V
SPX/SNX negative input bias
current
VSP = VSN = 0 V
VREF = 5.0 V
200
2
µA
VREFUV
IVREF
VREF undervoltage
VREF input current
2.6
1
V
mA
PROTECTION CIRCUITS
VM falling, UVLO report
VM rising, UVLO recovery
Rising to falling threshold
5.4
5.6
5.8
6
VUVLO
VM undervoltage lockout
VM undervoltage hysteresis
V
VUVLO_HYS
200
10
mV
µs
V
tUVLO_DEG
VM undervoltage deglitch time VM falling, UVLO report
(1)
VCPUV
Charge pump undervoltage
Gate drive clamping voltage
With respect to VM
Positive clamping voltage
Negative clamping voltage
VDS_LVL = 000b
VDS_LVL = 001b
VDS_LVL = 010b
VDS_LVL = 011b
VDS_LVL = 100b
VDS_LVL = 101b
VDS_LVL = 110b
VDS_LVL = 111b
2.4
10.5
15
VGS_CLAMP
V
–0.6
0.15
0.24
0.4
0.51
0.6
VDS overcurrent trip voltage
(SPI Device)
VDS_OCP
V
0.9
1.8
Disabled
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www.ti.com.cn
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDS tied to AGND
MIN
TYP
0.15
0.24
0.4
MAX UNIT
VDS 18 kΩ (±5%) to AGND
VDS 75 kΩ (±5%) to AGND
VDS Hi-Z ( > 500 kΩ to AGND)
VDS 75 kΩ (±5%) to DVDD
VDS 18 kΩ (±5%) to DVDD
VDS tied to DVDD
VDS overcurrent trip voltage
(HW Device)
VDS_OCP
0.6
V
0.9
1.8
Disabled
0.25
0.5
SEN_LVL = 00b
SEN_LVL = 01b
VSENSE overcurrent trip
voltage (SPI Device)
VSEN_OCP
V
SEN_LVL = 10b
0.75
1
SEN_LVL = 11b
VSENSE overcurrent trip
voltage (HW Device)
VSEN_OCP
tOCP_DEG
tRETRY
tRETRY
1
V
VDS and VSENSE overcurrent
deglitch time
4.5
µs
TRETRY = 0b
TRETRY = 1b
4
ms
µs
Overcurrent retry time (SPI
Device)
500
Overcurrent retry time (HW
Device)
4
140
170
20
ms
°C
°C
°C
(1)
TOTW
Thermal warning temperature Die temperature (Tj)
120
150
Thermal shutdown
Die temperature (Tj)
temperature
(1)
TOTSD
(1)
THYS
Thermal hysteresis
Die temperature (Tj)
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
SPI (nSCS, SCLK, SDI, SDO)
tREADY
tCLK
SPI ready after after enable
SCLK minimum period
VM > UVLO, ENABLE = 3.3 V
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
100
100
40
tCLKH
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
nSCS input setup time
tCLKL
tSU_SDI
tHD_SDI
tDLY_SDO
tSU_nSCS
tHD_nSCS
tHI_nSCS
tEN_nSCS
tDIS_nSCS
60
SCLK high to SDO valid
60
100
100
600
nSCS input hold time
nSCS minimum high time before active low
nSCS enable time
nSCS low to SDO out of high impedance
nSCS high to SDO high impedance
20
20
nSCS disable delay time
10
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
tHI_nSCS
tSU_nSCS
tHD_nSCS
tCLK
tCLKH
tCLKL
X
MSB
LSB
X
tSU_SDI tHD_SDI
Z
MSB
LSB
Z
tDIS_nSCS
tEN_nSCS tDLY_SDO
图 1. SPI Slave-Mode Timing Diagram
6.7 Typical Characteristics
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
VVM = 6 V
VVM = 12 V
VVM = 24 V
VVM = 38 V
TA = -40èC
1
0
TA = 25èC
TA = 125èC
0
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (èC)
D001
D002
图 2. Supply Current Over Supply Voltage
图 3. Supply Current Over Temperature
100
100
90
80
70
60
50
40
30
20
10
0
TA = -40èC
TA = 25èC
TA = 125èC
VVM = 6 V
VVM = 12 V
VVM = 24 V
VVM = 38 V
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (èC)
D003
D004
图 4. Sleep Current Over Supply Voltage
图 5. Sleep Current Over Temperature
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www.ti.com.cn
Typical Characteristics (接下页)
3.5
3.4
3.3
3.2
3.1
3
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.9
2.8
2.7
2.6
2.5
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
D005
D006
IDVDD = 0 mA
IDVDD = 30 mA
图 6. DVDD Voltage Over Supply Voltage
图 7. DVDD Voltage Over Supply Voltage
12
10
8
12
10
8
6
6
4
4
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
2
2
0
0
0
3
6
9
12
15
-40
-20
0
20
40
60
80
100 120 140
Load Current (mA)
Temperature (èC)
D007
D008
图 8. VCP Voltage Over Load
图 9. VCP Voltage Over Temperature
12
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
7 Detailed Description
7.1 Overview
The DRV8304 device is an integrated 6-V to 38-V gate driver for 3-phase motor-drive applications. The device
reduces system component count, cost, and complexity by integrating three independent half-bridge gate drivers,
charge pump, and linear regulator for the high-side and low-side gate-driver supply voltages. A standard serial
peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault
diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for
configuring the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 150-
mA source, 300-mA sink peak currents with a 15-mA average output current. The high-side gate-drive supply
voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVM + 10 V. The
low-side gate-drive supply voltage is generated using a linear regulator from the VM power supply that regulates
to 10 V. A smart gate-drive (SGD) architecture provides the ability to dynamically adjust the output gate-drive
current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This feature
allows for the removal of external gate-drive resistors and diodes reducing bill of materials (BOM) component
count, cost, and printed circuit board (PCB) area. The architecture also uses an internal state machine to protect
against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic
turnon of the external power MOSFET.
The DRV8304 device integrates three, bidirectional current-shunt amplifiers for monitoring the current level
through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier
can be adjusted through the SPI (DRV8304S) or hardware (DRV8304H) interface with the SPI providing
additional flexibility to adjust the output bias point.
In addition to the high level of device integration, the DRV8304 device provides a wide range of integrated
protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump
undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed
information available in the SPI registers on the SPI device version.
The DRV8304 device is available in 0.5-mm pin pitch, VQFN surface-mount packages. The VQFN package size
is 6 mm × 6 mm.
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DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
7.2 Functional Block Diagram
VM
+
1 …F
bulk
VM
VDRAIN
VM
Power
VCP
HS
1 …F
VCP
GHA
SHA
HS
LS
VCP
CPH
Charge
Pump
VGLS
LS
22 nF
CPL
GLA
30 mA
DVDD
AGND
3.3-V LDO
VGLS LDO
1 …F
Gate Driver
PGND
ENABLE
INHA
VM
VCP
GHB
SHB
HS
HS
INLA
INHB
INLB
Digital
Core
VGLS
LS
GLB
LS
Gate Driver
INHC
INLC
Control
Inputs
MODE
IDRIVE
VDS
VM
VCP
GHC
SHC
HS
HS
GAIN
CAL
VGLS
LS
GLC
LS
Gate Driver
Outputs
nFAULT
SPC
RSENSE
AV
VCC
SNC
SPB
VREF
0.1 µF
AV
RSENSE
SNB
SPA
SOC
SOB
SOA
Output Offset
Bias
AV
RSENSE
SNA
CAL
PPAD
图 10. Block Diagram for DRV8304H
14
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DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
Functional Block Diagram (接下页)
VM
+
1 …F
bulk
VM
VM
VDRAIN
VM
Power
VCP
HS
1 …F
VCP
CPH
GHA
SHA
HS
LS
VCP
Charge
Pump
VGLS
LS
22 nF
CPL
GLA
30 mA
DVDD
AGND
3.3-V LDO
VGLS LDO
1 …F
Gate Driver
PGND
ENABLE
INHA
VM
VCP
GHB
HS
HS
INLA
INHB
INLB
SHB
GLB
Digital
Core
VGLS
LS
LS
Control
Inputs
Gate Driver
INHC
INLC
VM
VCP
Outputs
GHC
nFAULT
SCLK
HS
HS
SHC
GLC
VGLS
LS
LS
SPI
SDI
Gate Driver
SDO
SPC
nSCS
RSENSE
AV
VCC
SNC
VREF
SPB
0.1 µF
AV
RSENSE
SNB
SOC
SOB
SOA
SPA
AV
RSENSE
Output Offset
Bias
SNA
CAL
PPAD
图 11. Block Diagram for DRV8304S
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DRV8304
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www.ti.com.cn
7.3 Feature Description
表 1 lists the recommended values of the external components for the gate driver.
表 1. DRV8304 Gate-Driver External Components
COMPONENTS
CVM1
PIN 1
VM
PIN 2
PGND
RECOMMENDED
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10 µF, VM-rated capacitor
CVM2
VM
PGND
CVCP
VCP
VM
X5R or X7R, 16-V, 1-µF capacitor
CSW
CPH
CPL
X5R or X7R, 22-nF, VM-rated capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
CDVDD
RnFAULT
RSDO
DVDD
VCC(1)
VCC(1)
IDRIVE
VDS
AGND
nFAULT
5.1-kΩ, Pullup resistor
SDO
5.1-kΩ, Pullup resistor, DRV8304 SPI device
DRV8304 hardware interface
RIDRIVE
RVDS
RMODE
RGAIN
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DGND
SNA and PGND
SNB and PGND
SNC and PGND
DRV8304 hardware interface
MODE
GAIN
VREF
SPA
DRV8304 hardware interface
DRV8304 hardware interface
CVREF
X5R or X7R, 0.1-µF, VREF-rated capacitor (Optional)
Sense shunt resistor based on current regulation limit
Sense shunt resistor based on current regulation limit
Sense shunt resistor based on current regulation limit
RASENSE
RBSENSE
RCSENSE
SPB
SPC
(1) The VCC pin is not a pin on the DRV8304 device, but a VCC supply voltage pullup is required for the open-drain output nFAULT and
SDO. These pins can also be pulled up to DVDD.
7.3.1 3-Phase Smart Gate Drivers
The DRV8304 device integrates three, half-bridge gate drivers, each capable of driving high-side and low-side N-
channel power MOSFETs. A doubler charge pump provides the proper gate-bias voltage to the high-side
MOSFET across a wide operating-voltage range in addition to providing 100% duty-cycle support. An internal
linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge gate drivers can be
used in combination to drive a 3-phase motor or separately to drive other types of loads.
The DRV8304 device implements a smart gate-drive architecture which allows the user to dynamically adjust the
gate drive current without requiring external gate current limiting resistors. Additionally, this architecture provides
a variety of protection features for the external MOSFETs including automatic dead-time insertion, parasitic dV/dt
gate turnon prevention, and gate-fault detection.
7.3.1.1 PWM Control Modes
The DRV8304 device provides four different PWM-control modes to support various commutation and control
methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during
operation of the power MOSFETs.
7.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in 表 2.
表 2. 6x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
SHx
Hi-Z
H
0
0
1
1
0
1
0
1
L
H
L
L
H
L
L
L
Hi-Z
16
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7.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in 表 3.
表 3. 3x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
SHx
Hi-Z
L
0
1
1
X
0
1
H
L
L
H
H
7.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV8304 device uses 6-step block commutation tables that are stored internally. This feature
allows for a 3-phase BLDC motor to be controlled using a single PWM sourced from a simple controller. The
PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode normally
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on the SPI device. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
表 4. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
INHC = 0
GATE-DRIVE OUTPUTS
PHASE B PHASE C
INHC = 1
PHASE A
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
GHB
GLB
GHC
GLC
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
!PWM
L
L
L
L
L
Stop
Align
L
H
L
H
Align
1
2
3
4
5
6
PWM
!PWM
L
L
H
H
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
!PWM
!PWM
L
L
L
H
L
L
L
L
H
PWM
PWM
L
!PWM
!PWM
L
L
H
L
L
L
H
PWM
!PWM
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DESCRIPTION
表 5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
INHC = 0
GATE-DRIVE OUTPUTS
PHASE B PHASE C
INHC = 1
PHASE A
STATE
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
L
GHB
GLB
L
GHC
GLC
L
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
L
Stop
Align
L
L
H
L
L
H
H
H
L
Align
1
2
3
4
5
6
L
PWM
L
L
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
L
L
L
L
L
L
H
H
L
L
L
PWM
PWM
L
L
L
H
H
L
L
L
PWM
L
L
图 12 and 图 13 show the different possible configurations in 1x PWM mode.
DRV8304
DRV8304
H
INHA
INLA
H
PWM
MCU_PWM
INHA
M
PWM
MCU_PWM
MCU_GPIO
M
STATE0
INLA
INHB
INLB
INHC
INLC
H
STATE0
STATE1
INHB
INLB
STATE1
STATE2
MCU_GPIO
MCU_GPIO
STATE2
DIR
INHC
INLC
DIR
MCU_GPIO
MCU_GPIO
MCU_GPIO
MCU_GPIO
nBRAKE
nBRAKE
图 13. 1x PWM—Hall Sensor
图 12. 1x PWM—Simple Controller
7.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the DRV8304 device to drive separate high-side and low-side loads with each half-
bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side
switches. In this mode, if the system is configured in a half-bridge configuration, simultaneously turning on both
the high-side and low-side MOSFETs causes shoot-through current in external MOSFETs and can cause them
to damage.
表 6. Independent PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
0
0
1
1
0
1
0
1
L
H
H
L
H
H
18
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DRV8304
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors if
both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible. In this
case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in 图 14.
Disable
+
V
DS œ
VM
VDRAIN
VCP
GHx
HS
INHx
INLx
Load
SHx
GLx
VGLS
LS
Load
Gate Driver
Disable
SPx
+
V
DSœ
图 14. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in 图 15 or 图 16. The unused gate driver and the corresponding
input can be left disconnected.
+
+
V
V
DS œ
DS œ
VM
VM
VDRAIN
VDRAIN
VCP
HS
VCP
HS
GHx
SHx
GHx
SHx
Load
INHx
INLx
INHx
INLx
VGLS
LS
VGLS
LS
GLx
SPx
GLx
SPx
Load
Gate Driver
Gate Driver
+
+
V
V
DS œ
DS œ
图 16. Single Low-Side Driver
图 15. Single High-Side Driver
7.3.1.2 Device Interface Modes
The DRV8304 device supports two different interface modes (SPI and hardware) to allow the end application to
design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different
versions to be pin-to-pin compatible. This allows for application designers to evaluate with one interface version
and potentially switch to another with minimal modifications to their design.
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7.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI device supports a serial communication bus that allows for an external controller to send and receive
data with the DRV8304 device. This bus allows for the external controller to configure device settings and read
detailed fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins.
•
The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on
SDI and SDO.
•
•
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
•
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV8304 device.
For more information on the SPI, see the SPI Communication section.
7.3.1.2.2 Hardware Interface
The hardware interface device converts the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This option allows for the application designer to configure the most commonly used device
settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This configuration
removes the requirement for a SPI bus from the external controller. General fault information can still be obtained
through the nFAULT pin.
•
•
•
•
The GAIN pin configures the current shunt-amplifier gain.
The IDRIVE pin configures the gate-drive current strength.
The MODE pin configures the PWM control mode.
The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
DVDD
RGAIN
DVDD
GAIN
SCLK
SDI
Hardware
Interface
SPI
DVDD
DVDD
IDRIVE
MODE
VDS
DVDD
VCC
RPU
SDO
nSCS
DVDD
RVDS
图 18. Hardware Interface
图 17. SPI
7.3.1.3 Gate Driver Voltage Supplies
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM
voltage supply input. The charge pump allows the gate driver to properly bias the high-side MOSFET gate with
respect to the source across a wide input supply-voltage range. The charge pump is regulated to maintain a fixed
output voltage of VVM + 10 V and supports an average output current of 15 mA. When VVM is less than 12 V, the
charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V when unloaded. The charge
pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The charge pump
requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the storage
capacitor. Additionally, a X5R or X7R, 22-nF, VM-rated ceramic capacitor is required between the CPH and CPL
pins to act as the flying capacitor.
20
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
VM
VM
1 …F
VCP
CPH
VM
Charge
Pump
22 nF
Control
CPL
图 19. Charge Pump Architecture
The low-side gate-drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The linear regulator allows the gate driver to properly bias the low-side MOSFET gate with respect to
ground. The linear regulator output is fixed at 10 V and supports an output current of 15 mA.
7.3.1.4 Smart Gate-Drive Architecture
The DRV8304 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-
side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. 图 20 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters of
the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
INLx
VM
GHx
SHx
Level
Shifters
150 kꢀ
Logic
VGLS
GLx
Level
Shifters
150 kꢀ
PGND
图 20. Gate Driver Block Diagram
7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics
in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are predominately
determined by the rate of gate charge (or gate current) delivered during the MOSFET Qgd or Miller charging
region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external
power MOSFETs.
IDRIVE allows the DRV8304 device to dynamically switch between gate drive currents either through a register
setting on the SPI device or the IDRIVE pin on hardware interface device. The SPI and hardware devices
provide 7 IDRIVE settings ranging from 15-mA to 150-mA source and 30-mA to 300-mA sink. The gate-drive
current setting is delivered to the gate during the turnon and turnoff of the external power MOSFET for the tDRIVE
duration. After the MOSFET turnon or turnoff, the gate driver switches to a smaller hold current (IHOLD) to improve
the gate driver efficiency. Additional details on the IDRIVE settings are described in the Register Maps section for
the SPI device and in the Pin Diagrams section for the hardware interface device.
7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead-time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is the period of
time between the switching of the external high-side and low-side MOSFETs to ensure that they do not cross
conduct and cause shoot-through. The DRV8304 device uses the VGS voltage monitors to measure the MOSFET
gate-to-source voltage and determine the proper time to switch instead of relying on a fixed time value. This
feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on the SPI device.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown happens for the tDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
22
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If,
at the end of the tDRIVE period, the VGS voltage has not reached the proper threshold, the gate driver reports a
fault. To ensure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Register Maps section for SPI device and in the Pin Diagrams section for hardware interface
device.
注
If the mode is set to independent PWM mode, then the IDRIVE current is automatically set
for the IHOLD period.
图 21 shows an example of the TDRIVE state machine in operation.
VINHx
tPD
tPD
VINLx
tDEAD
tDEAD
VGHx
IDRIVE
IHOLD
IHOLD
ISTRONG
ISTRONG
IGHx
IHOLD
IDRIVE
tDEAD
tDEAD
VGLx
IDRIVE
IHOLD
ISTRONG
ISTRONG
IGLx
IHOLD
IHOLD
IDRIVE
tDRIVE
tDRIVE
图 21. TDRIVE State Machine
7.3.1.4.3 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VGS,CLAMP voltage to help protect the external
high-side MOSFETs from gate overvoltage damage. The positive voltage clamp is realized using a series of
diodes. The negative voltage clamp uses the body diodes of the internal pulldown gate driver as shown in 图 22.
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DRV8304
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www.ti.com.cn
VGHS
VM
IREVERSE
GHx
VGS > VCLAMP
ICLAMP
SHx
Predriver
VGS negative
VGLS
GLx
RSENSE
PGND
图 22. Gate Drive Clamp
7.3.1.4.4 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time comprises three parts consisting of the digital input deglitcher delay, the digital propagation
delay, and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead-time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
In order for the output to change state during normal operation, one MOSFET must first be turned off. The
MOSFET gate is ramped down according to the IDRIVE setting, and the observed propagation delay ends when
the MOSFET gate falls below the threshold voltage.
7.3.1.4.5 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins and the low-side VDS
monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP
pins to the common ground point of the external half-bridges.
For the SPI device, the reference point of the low-side VDS monitor can be changed between the SPx and SNx
pins if desired with the LS_REF register setting.
24
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
The VVDS_OCP threshold is programmable from 0.15 V to 1.8 V. Additional information on the VDS monitor levels
are described in the Register Maps section for the SPI device and in the Pin Diagrams section hardware
interface device.
DRV8304
High-Side VDS OCP Monitor
VM
VDRAIN
+
œ
GHx
+
VDS,OCP
œ
SHx
Low-Side VDS OCP Monitor
GLx
+
œ
SPX
+
0
1
VDS,OCP
RSENSE
œ
SNX
LS_REF
(DRV8304S only)
图 23. DRV8304 VDS Monitors
7.3.1.4.6 VDRAIN Sense Pin
The DRV8304 device provides a separate sense pin for the common point of the high-side MOSFET drain. This
pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors (VDRAIN) and the power supply
(VM) to remain separate and prevent noise on the VDRAIN sense line. This separation also allows for a small
filter to be implemented on the gate driver supply (VM) or to insert a boost converter to support lower voltage
operation if desired. Care must still be taken when the filter or separate supply is designed because the VM
supply is still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH).
The VM supply must not drift to far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
7.3.2 DVDD Linear Voltage Regulator
A 3.3-V, 30-mA linear regulator is integrated into the DRV8304 device and is available for use by external
circuitry. This regulator can provide the supply voltage for a low-power microcontroller or other low-current
supporting circuitry. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or
X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 30
mA.
VM
+
œ
REF
3.3 V, 30 mA
maximum
DVDD
AGND
1 …F
图 24. DVDD Linear Regulator Block Diagram
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DRV8304
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www.ti.com.cn
Use 公式 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P = VVM - VDVDD ì I
DVDD
(1)
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in 公式 2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
7.3.3 Pin Diagrams
图 25 shows the input structure for the logic-level pins, INHx, INLx, CAL, nSCS, SCLK, and SDI. The input can
be driven with a voltage or external resistor.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
RPD
图 25. Logic-Level Input Pin Structure (INHx, INLx, CAL, nSCS, SCLK, and SDI)
图 26 shows the input structure for the logic-level ENABLE pin. The input can be driven with a voltage or external
resistor. The ENABLE pin is latched when the device is powered-up.
5 V
RPU2
Latch
VEXT
STATE
VIH
RESISTANCE
Tied to VEXT
Tied to AGND
INPUT
RPU1
Logic High
Logic Low
VIL
图 26. Logic-Level Input Pin Structure (ENABLE)
26
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DRV8304
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
图 27 shows the structure of the four-level input pins, MODE and GAIN, on the hardware interface device. The
input can be set with an external resistor. The MODE and GAIN pins are latched when the device is powered-up.
MODE
GAIN
DVDD
STATE
VI4
RESISTANCE
Tied to DVDD
DVDD
Independent
40 V/V
+
RPU
œ
Hi-Z (>500 kΩ to
1x PWM
3x PWM
6x PWM
20V/V
10 V/V
5 V/V
VI3
VI2
VI1
AGND)
+
RPD
47 kΩ ±5%
to AGND
œ
Tied to AGND
+
œ
图 27. Four-Level Input Pin Structure (MODE and GAIN)
图 28 shows the structure of the seven-level input pins, IDRIVE and VDS, on the hardware interface device. The
input can be set with an external resistor. The IDRIVE and VDS pins are latched when the device is powered-up.
IDRIVE
VDS
150/300 mA
Disabled
+
œ
STATE
VI7
RESISTANCE
Tied to DVDD
135/270 mA
105/210 mA
90/180 mA
60/120 mA
45/90 mA
1.8 V
0.9 V
0.6 V
0.4 V
0.24 V
0.15 V
+
DVDD
DVDD
œ
18 kꢀ ± 5%
to DVDD
VI6
VI5
VI4
VI3
VI2
VI1
+
75 kꢀ ± 5%
to DVDD
RPU
œ
Hi-Z (>500 kΩ
to AGND)
DVDD
+
RPD
75 kꢀ ± 5%
to AGND
œ
Latch
18 kΩ ±5%
to AGND
+
Tied to AGND
œ
+
œ
15/30 mA
图 28. Seven-Level Input Pin Structure (IDRIVE and VDS)
图 29 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function properly.
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DVDD
R
PU
STATE
No Fault
Fault
STATUS
OUTPUT
Active
Inactive
Active
Inactive
图 29. Open-Drain Output Pin Structure
7.3.4 Low-Side Current-Shunt Amplifiers
The DRV8304 device integrates three, high-performance low-side current-shunt amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such
as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin
(VREF).
7.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8304 outputs an analog voltage equal to the voltage across the SPx and SNx pins
multiplied by the gain setting (GCSA) as shown in 图 30. The gain setting is adjustable between four different
levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Use 公式 3 to calculate the current through the shunt resistor.
VVREF
- VSOx
2
I =
GCSA ì RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
V
CC
œ
R
SENSE
V
+
REF
0.1 …F
R2
R3
R4
R5
½
+
œ
图 30. Bidirectional Current-Sense Configuration
图 31 and 图 32 show the detail of the amplifier operational range. In bi-directional operation, the amplifier output
for 0-V input is set at VREF / 2. Any change in the differential input results in a corresponding change in the
output times the CSA_GAIN factor. The amplifier has a defined linear region in which it can maintain operation.
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
SO (V)
VREF
VREF / 2
VLINEAR
SP œ SN (V)
图 31. Bidirectional Current-Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP œ SN
œ0.3 V
œI × R
V
VREF
œ 0.25 V
V
SO(rangeœ)
V
SO(off)max
/ 2
V
,
OFF
0 V
V
VREF
V
DRIFT
V
SO(off)min
V
SO(range+)
I × R
0.3 V
0.25 V
0 V
图 32. Bidirectional Current Sense Regions
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7.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8304 SPI device, use the VREF_DIV bit to remove the VREF divider. In this case the shunt amplifier
operates unidirectionally and the SOx outputs an analog voltage equal to the voltage across the SPx and SNx
pins multiplied by the gain setting (GCSA). Use 公式 4 to calculate the current through the shunt resistor.
V
- 0.3 - V
SOX
(
)
(
)
VREF
I =
G
CSA ì RSENSE
(
)
(4)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
œ
R
SENSE
+
V
CC
R2
R3
R4
R5
0.3 V
V
REF
+
+
-
0.1 …F
œ
图 33. Unidirectional Current-Sense Configuration
图 34 and 图 35 show the detail of the amplifier operational range. In unidirectional operation, the amplifier output
for 0-V input is set at VREF – 0.3 V. In this operating mode the amplifier output only responds to a positive
current through the shunt resistor. The amplifier has a defined linear region in which it can maintain operation.
SO (V)
V
REF
V
œ 0.3 V
VREF
V
LINEAR
SP œ SN (V)
图 34. Unidirectional Current-Sense Output
30
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I
SP
SN
SO
SO
R
AV
V
REF
V
VREF
œ 0.25 V
V
SO(off)max
SP œ SN
V
,
OFF
0 V
V
œ 0.3 V
VREF
V
DRIFT
V
SO(off)min
V
SO(range)
I × R
0.3 V
0.25 V
0 V
图 35. Unidirectional Current-Sense Regions
7.3.4.3 Offset Calibration
The DRV8304 device provides an auto calibration feature to minimize the amplifier input offset on power up or
during an ENABLE reset pulse to account for temperature and device variation. Auto calibration is performed on
both the hardware and SPI device options. The auto calibration begins immediately after the VREF pin crosses
the minimum operational VREF voltage and completes in several µs (max 500 µs). During auto calibration, the
inputs to the amplifier are disconnected from SPX and SNX pin and shorted internally. After auto calibration the
amplifiers are ready for operation.
For the SPI device option, auto calibration can also be performed during run time by setting the AUTOCAL bit. If
the AUTOCAL bit is already set once, then the user must reset the bit and again set it to perform the auto-
calibration. The user must wait for at least 500 µs before another write to ensure a successful calibration. The
user is recommended not to sample CSA outputs during the AUTOCAL operation.
In addition to this, the device also supports an external calibration through the SPI registers (SPI_CAL) in SPI
device or through CAL pin in hardware device variant. When the calibration is enabled (CAL pin or SPI_CAL),
the inputs to the amplifier are shorted internally, and the amplifier voltage can be observed though SOX pin for
doing the external calibration. For the best results, perform offset calibration when the external MOSFETS are
not switching to reduce the potential noise impact to the amplifier. DC calibration can be done at any time, even
when the half-bridges are operating. 图 36 shows a diagram of the calibration mode
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R2
R3
R4
R5
R6
SOx
CAL
CAL
SPX
SNX
œ
R
SENSE
+
V
REF
CAL
CAL
R2
R3
R4
R5
1/2
+
œ
图 36. Amplifier Calibration Mode
7.3.5 Gate-Driver Protection Circuits
The DRV8304 device is fully protected against VM undervoltage, charge pump undervoltage, MOSFET VDS
overcurrent, gate driver shorts, and overtemperature events.
表 7. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
VM
undervoltage
(UVLO)
Automatic:
VVM > VUVLO
VVM < VUVLO
—
nFAULT
Hi-Z
Disabled
Charge pump
undervoltage
(CPUV)
DIS_CPUV = 0b
DIS_CPUV = 1b
nFAULT
None
Hi-Z
Active
Active
Automatic:
VVCP > VCPUV
VVCP < VCPUV
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
OCP_MODE = 01b
nFAULT
nFAULT
Hi-Z
Hi-Z
Active
Active
Retry:
tRETRY
VDS overcurrent
(VDS_OCP)
VDS > VVDS_OCP
OCP_MODE = 10b
OCP_MODE = 11b
nFAULT
None
Active
Active
Active
Active
No action
No action
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Retry:
tRETRY
VSENSE
overcurrent
(SEN_OCP)
OCP_MODE = 01b
OCP_MODE = 10b
nFAULT
nFAULT
None
Hi-Z
Active
Active
Active
VSP > VSEN_OCP
Active
Active
No action
No action
OCP_MODE = 11b or
DIS_SEN = 1b
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 0b
DIS_GDF = 1b
OTW_REP = 1b
OTW_REP = 0b
nFAULT
None
Hi-Z
Active
Active
Active
Active
Gate driver fault
(GDF)
Gate voltage stuck > tDRIVE
Active
Active
Active
No action
Automatic:
TJ < TOTW – THYS
Thermal
warning
(OTW)
nFAULT
None
TJ > TOTW
No action
Thermal
shutdown
(OTSD)
Automatic:
TJ < TOTSD – THYS
TJ > TOTSD
—
nFAULT
Hi-Z
Active
32
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7.3.5.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VUVLO threshold, all of the external MOSFETs
are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and VM_UVLO bits
are also latched high in the registers on the SPI device. Normal operation resumes (gate driver operation and the
nFAULT pin is released) when the VM undervoltage condition is removed. The VM_UVLO bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
7.3.5.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VCPUV threshold voltage of the charge
pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and CPUV bits
are also latched high in the registers on the SPI device. Normal operation resumes (gate-driver operation and the
nFAULT pin is released) when the VCP undervoltage condition is removed. The CPUV bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on the SPI
device disables this protection feature. On the hardware interface device, the CPUV protection is always
enabled.
7.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on)
.
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized and action is taken according to the OCP_MODE. On hardware interface
devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4.5 µs, and the OCP_MODE is
configured for 4-ms automatic retry. Moreover, the VDS_OCP can be disabled by tying the VDS pin to DVDD.
On SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, and the OCP_MODE bit can
operate in four different modes: VDS latched shutdown, VDS automatic retry, VDS report only, and VDS disabled.
7.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits remain latched until the tRETRY period expires.
7.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate normally. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
7.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SPX pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE bit. On the hardware interface device, the VSENSE threshold is fixed at 1 V, tOCP_DEG
is fixed at 4 µs, and the OCP_MODE bit for VSENSE is fixed for 4-ms automatic retry. On the SPI device, the
VSENSE threshold is set through the SEN_LVL SPI register and the OCP_MODE bit can operate in four different
modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and VSENSE disabled.
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7.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, SEN_OCP, and sense OCP bits remain latched until the tRETRY period expires.
7.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
7.3.5.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault might be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault might be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin is driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the gate-driver fault condition is removed and a clear fault
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On the SPI device, setting
the DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve a gate driver fault in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
7.3.5.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
the SPI device. The device performs no additional action and continues to function. When the die temperature
decreases below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can
also be configured to report on the nFAULT pin by setting the OTW_REP bit to 1b through the SPI registers.
7.3.5.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit remains latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
34
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7.4 Device Functional Modes
7.4.1 Gate Driver Functional Modes
7.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV8304 device. When the ENABLE pin is low, the device enters a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The tSLEEP time must
elapse after a falling edge on the ENABLE pin before the device enters sleep mode. The device comes out of
sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is
ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
注
During power up and power down of the device through the ENABLE pin, the nFAULT pin
is held low as the internal regulators enable or disable. After the regulators have enabled
or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin
is low does not exceed the tSLEEP or tWAKE time.
7.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device enters operating mode. The tWAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active and hardware inputs are latched.
注
If the ENABLE pin is left floating, the device will be in Operating Mode.
7.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV8304 device enters a partial shutdown state to help protect the
external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on the SPI device or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will begin the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
7.5 Programming
This section applies only to the DRV8304 SPI device.
7.5.1 SPI Communication
7.5.1.1 SPI
On the DRV8304 SPI device, an SPI bus is used to set device configurations, operating parameters, and read
out diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input
data (SDI) word consists of a 16-bit word, with a 5-bit command and 11 bits of data. The SPI output data (SDO)
word consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
•
•
•
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
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Programming (接下页)
placed in the Hi-Z state.
•
Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
•
•
•
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for the transaction to be valid.
If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
•
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data.
7.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
1 read or write bit, W (bit B15)
4 address bits, A (bits B14 through B11)
11 data bits, D (bits B11 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
表 8. SDI Input Data Word Format
R/W
B15
W0
ADDRESS
DATA
B5
B14
A3
B13
A2
B12
A1
B11
A0
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
D5
表 9. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
X
B14
X
B13
X
B12
X
B11
X
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
nSCS
SCLK
SDI
X
Z
MSB
LSB
X
SDO
MSB
LSB
Z
Capture
Point
Propagate
Point
图 37. SPI Slave Timing Diagram
36
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7.6 Register Maps
This section applies only to the DRV8304 SPI device.
注
Do not modify reserved registers or addresses not listed in the register map (表 10). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
表 10. DRV8304S Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
R
Address
0h
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
FAULT
SA_OC
Reserved
VDS_OCP
SB_OC
GDF
UVLO
OTSD
CPUV
VDS_HA
VGS_HA
VDS_LA
VGS_LA
1PWM_COM
VDS_HB
VGS_HB
1PWM_DIR
Reserved
Reserved
VDS_LB
VGS_LB
COAST
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
SC_OC
DIS_GDF
OTW
R
1h
DIS_CPUV
LOCK
OTW_REP
Reserved
Reserved
PWM_MODE
RW
RW
RW
RW
RW
RW
2h
IDRIVEP_HS
IDRIVEP_LS
OCP_ACT
DIS_SEN
IDRIVEN_HS
IDRIVEN_LS
VDS_LVL
3h
CBC
TDRIVE
DEAD_TIME
VREF_DIV LS_REF
4h
TRETRY
Reserved
OCP_MODE
CSA_GAIN
Reserved
5h
SPI_CAL
AUTOCAL
Reserved
SEN_LVL
6h
Reserved
7h
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7.6.1 Status Registers (DRV8304S Only)
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. 表 11 shows the codes that are used for
access types in this section.
表 11. Status Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 Fault Status Register 1 (Address = 0x00) [reset = 0x00]
The fault status register 1 is shown in 图 38 and described in 表 12.
Register access type: Read only
图 38. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
R-0b
VDS_OCP
R-0b
GDF
R-0b
UVLO
R-0b
OTSD
R-0b
VDS_HA
R-0b
VDS_LA
R-0b
VDS_HB
R-0b
VDS_LB
R-0b
VDS_HC
R-0b
VDS_LC
R-0b
表 12. Fault Status Register 1 Field Descriptions
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
Indicates VDS monitor overcurrent fault condition
Indicates gate drive fault condition
9
8
7
6
5
4
3
2
1
0
VDS_OCP
GDF
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
UVLO
Indicates undervoltage lockout fault condition
OTSD
Indicates overtemperature shutdown
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
Indicates VDS overcurrent fault on the A high-side MOSFET
Indicates VDS overcurrent fault on the A low-side MOSFET
Indicates VDS overcurrent fault on the B high-side MOSFET
Indicates VDS overcurrent fault on the B low-side MOSFET
Indicates VDS overcurrent fault on the C high-side MOSFET
Indicates VDS overcurrent fault on the C low-side MOSFET
38
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7.6.1.2 Fault Status Register 2 (Address = 0x01) [reset = 0x00]
The fault status register 2 is shown in 图 39 and described in 表 13.
Register access type: Read only
图 39. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
R-0b
SB_OC
R-0b
SC_OC
R-0b
OTW
R-0b
CPUV
R-0b
VGS_HA
R-0b
VGS_LA
R-0b
VGS_HB
R-0b
VGS_LB
R-0b
VGS_HC
R-0b
VGS_LC
R-0b
表 13. Fault Status Register 2 Field Descriptions
Bit
Field
Type
Default
Description
10
SA_OC
SB_OC
SC_OC
OTW
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8304S)
Indicates overcurrent on phase B sense amplifier (DRV8304S)
Indicates overcurrent on phase C sense amplifier (DRV8304S)
Indicates overtemperature warning
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
CPUV
Indicates charge pump undervoltage fault condition
Indicates gate drive fault on the A high-side MOSFET
Indicates gate drive fault on the A low-side MOSFET
Indicates gate drive fault on the B high-side MOSFET
Indicates gate drive fault on the B low-side MOSFET
Indicates gate drive fault on the C high-side MOSFET
Indicates gate drive fault on the C low-side MOSFET
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
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7.6.2 Control Registers (DRV8304S Only)
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. 表 14 shows the codes that are used for
access types in this section.
表 14. Control Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
The driver control register is shown in 图 40 and described in 表 15.
Register access type: Read/Write
图 40. Driver Control Register
10
9
8
7
6
5
4
3
2
1
0
DIS
_CPUV
DIS
_GDF
OTW
_REP
1PWM
_COM
1PWM
_DIR
CLR
_FLT
Reserved
R/W-0b
PWM_MODE
R/W-00b
COAST
R/W-0b
BRAKE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表 15. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
Reserved
R/W
0b
Reserved
9
DIS_CPUV
R/W
R/W
R/W
R/W
0b
0b = Charge-pump undervoltage lockout fault is enabled
1b = Charge-pump undervoltage lockout fault is disabled
8
DIS_GDF
0b
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
7
OTW_REP
PWM_MODE
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification (diode
freewheeling)
3
2
1
1PWM_DIR
COAST
R/W
R/W
R/W
0b
0b
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
Write a 1b to this bit to put all MOSFETs in the Hi-Z state
BRAKE
Write a 1b to this bit to turn on all three low-side MOSFETs in 1x
PWM mode.
This bit is ORed with the INLC (BRAKE) input.
0
CLR_FLT
R/W
0b
Write a 1b to this bit to clear latched fault bits.
This bit automatically resets after being written.
40
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7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
The gate drive HS register is shown in 图 41 and described in 表 16.
Register access type: Read/Write
图 41. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
0
LOCK
Reserved
R/W-0b
IDRIVEP_HS
R/W-111b
Reserved
R/W-0b
IDRIVEN_HS
R/W-111b
R/W-011b
表 16. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7
Reserved
R/W
R/W
0b
Reserved
6-4
IDRIVEP_HS
111b
000b = 15 mA
001b = 15 mA
010b = 45 mA
011b = 60 mA
100b = 90 mA
101b = 105 mA
110b = 135 mA
111b = 150 mA
3
Reserved
R/W
R/W
0b
Reserved
2-0
IDRIVEN_HS
111b
000b = 30 mA
001b = 30 mA
010b = 90 mA
011b = 120 mA
100b = 180 mA
101b = 210 mA
110b = 270 mA
111b = 300 mA
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7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
The gate drive LS register is shown in 图 42 and described in 表 17.
Register access type: Read/Write
图 42. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
0
CBC
TDRIVE
R/W-11b
Reserved
R/W-0b
IDRIVEP_LS
R/W-111b
Reserved
R/W-0b
IDRIVEN_LS
R/W-111b
R/W-1b
表 17. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
In retry OCP_MODE, for both VDS_OCP and SEN_OCP, the
fault is automatically cleared when a PWM input is given
9-8
TDRIVE
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
7
Reserved
R/W
R/W
0b
Reserved
6-4
IDRIVEP_LS
111b
000b = 15 mA
001b = 15 mA
010b = 45 mA
011b = 60 mA
100b = 90 mA
101b = 105 mA
110b = 135 mA
111b = 150 mA
3
Reserved
R/W
R/W
0b
Reserved
2-0
IDRIVEN_LS
111b
000b = 30 mA
001b = 30 mA
010b = 90 mA
011b = 120 mA
100b = 180 mA
101b = 210 mA
110b = 270 mA
111b = 300 mA
42
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7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
The OCP control register is shown in 图 43 and described in 表 18.
Register access type: Read/Write
图 43. OCP Control Register
10
9
8
7
6
5
4
3
2
1
0
TRETRY
R/W-0b
DEAD_TIME
R/W-01b
OCP_MODE
R/W-01b
OCP_ACT
R/W-0b
Reserved
R/W-00b
VDS_LVL
R/W-101b
表 18. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 4 ms
1b = VDS_OCP and SEN_OCP retry time is 50 µs
9-8
7-6
5
DEAD_TIME
R/W
R/W
R/W
01b
01b
0b
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
OCP_MODE
OCP_ACT
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
0b = All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
1b
= Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
4-3
2-0
Reserved
VDS_LVL
R/W
R/W
00b
Reserved
101b
000b = 0.15 V
001b = 0.24 V
010b = 0.40V
011b = 0.51 V
100b = 0.60 V
101b = 0.90 V
110b = 1.8 V
111b = VDS Disabled
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7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
The CSA control register is shown in 图 44 and described in 表 19.
Register access type: Read/Write
图 44. CSA Control Register
10
9
8
7
6
5
4
3
2
1
0
SEN_LVL
VREF
_DIV
LS
_REF
DIS
_SEN
SPI
_CAL
AUTO
CAL
Reserved
R/W-0b
CSA_GAIN
R/W-10b
Reserved
R/W-0b
R/W-1b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
表 19. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
10
Reserved
R/W
0b
Reserved
9
VREF_DIV
R/W
1b
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
8
LS_REF
R/W
0b
0b
= VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
R/W
10b
00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5
4
3
DIS_SEN
SPI_CAL
AUTOCAL
R/W
R/W
R/W
0b
0b
0b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
0b = Disable sense amplifier CAL function
1b = Enable sense amplifier CAL function
0b = AUTOCAL operation remains disabled in run mode
1b = Perform AUTOCAL operation
2
Reserved
SEN_LVL
R/W
R/W
0b
Reserved
1-0
11b
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
44
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8304 device is primarily used in 3-phase brushless DC motor control applications. The design
procedures in the Typical Application section highlight how to use and configure the DRV8304 device.
8.2 Typical Application
8.2.1 Primary Application
In this application the amplifiers are configured to sense bi-directional currents in each of the three half-bridge
legs.
Power and Charge Pump
VM
3.3 V, 30 mA
DVDD
AGND
VM
GND
1 µF
Three Phase Inverter
VM
GND
Gate Driver
VDD
GND
BLDC Motor
GHA
SHA
GLA
Power
GPIO
ENABLE
CAL
nFAULT
GP-O
GP-O
GP-I
GHB
SHB
GLB
PWM1, PWW2
PWM3, PWM4
PWM5, PWM6
INHA, INLA
INHB,INLB
INHC, INLC
PWM
Module
GHC
SHC
GLC
Smart Gate Drive
150 mA, 300 mA
(Fully Protected)
SCLK
SPI
SCLK
SDI
SDO
nSCS
MODE
IDRIVE
VDS
SDI
(DAC and External
Resistor for H/W I/F)
SDO
nSCS
GAIN
SOA
SOB
SOC
SPA, SNA
SPV, SNB
SPC, SNC
Analog to Digital
Converters
3x ADC
Microcontroller
DRV8304
图 45. Primary Application Schematic
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Typical Application (接下页)
8.2.1.1 Design Requirements
表 20 lists the example input parameters for the system design.
表 20. Design Parameters
EXAMPLE DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
REFERENCE
EXAMPLE VALUE
24 V
8 V to 38 V
VVM
MOSFET part number
CSD18514Q5A
29 nC (typical) at VVGS = 10 V
5 nC (typical)
100 to 300 ns
50 to 150 ns
45 kHz
MOSFET total gate charge
MOSFET gate to drain charge
Target output rise time
Target output fall time
Qg
Qgd
tr
tf
PWM frequency
ƒPWM
Imax
ISENSE
IRMS
PSENSE
TA
Maximum motor current
Winding sense current range
Motor RMS current
50 A
–20 A to +20 A
14.14 A
Sense resistor power rating
System ambient temperature
2 W
–20°C to +105°C
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External MOSFET Support
The DRV8304 MOSFET support is based on the charge-pump capacity and output PWM switching frequency.
For a quick calculation of MOSFET driving capacity, use 公式 5 and 公式 6 for three phase BLDC motor
applications.
Trapezoidal 120° Commutation:IVCP > Qg ׃PWM
Sinusoidal 180° Commutation:IVCP > 3 × Qg ׃PWM
(5)
where
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
IVCP is the charge pump capacity, which depends on the VM pin voltage.
The multiplier based on the commutation control method, may vary based on implementation.
(6)
8.2.1.2.1.1 Example
If a system at VVM = 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 45 kHz, then the charge
pump can support MOSFETs using trapezoidal commutation with a Qg < 333 nC, and MOSFETs with sinusoidal
commutation Qg < 111 nC. When the VM voltage (VVM) is 8 V, the maximum DRV8304 gate-drive voltage (VGSH
)
is 7.3 V. Therefore, at 7.3-V gate drive, the target FET (part number CSD18514Q5A) only has a gate charge of
approximately 22 nC. Therefore, with this FET, the system can have an adequate margin.
8.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
the SPI device through the SPI registers. On hardware interface devices, both source and sink settings are
selected simultaneously on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge (Qgd), desired rise time (tr), and a desired fall time (tf), use 公式
7 and 公式 8 to calculate the value of IDRIVEP and IDRIVEN (respectively).
46
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
Qgd
tr
IDRIVEP
>
(7)
(8)
Qgd
tf
IDRIVEN
>
8.2.1.2.2.1 Example
Use 公式 9 and 公式 10 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain charge of
5 nC and a rise time from 100 to 300 ns.
5 nC
IDRIVEP1
=
= 50 mA
100 ns
5 nC
(9)
IDRIVEP2
=
= 16.67 mA
300 ns
(10)
Select a value for IDRIVEP that is between 16.67 mA and 50 mA. For this example, the value of IDRIVEP was
selected as 45-mA source.
Use 公式 11 and 公式 12 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain charge of
5 nC and a fall time from 50 to 150 ns.
5 nC
IDRIVEN1
=
= 100 mA
50 ns
(11)
(12)
5 nC
IDRIVEN2
=
= 33.33 mA
150 ns
Select a value for IDRIVEN that is between 33.33 mA and 100 mA. For this example, the value of IDRIVEN was
selected as 90-mA sink.
8.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in 公式 13.
VDS_OCP > Imax ì RDS(on)max
(13)
8.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 50 A. According to the
CSD18514Q5A 40 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 4.9 mΩ. From these values, the approximate worst-
case value of RDS(on) is 1.8 × 4.9 mΩ = 8.82 mΩ.
Using 公式 13 with a value of 8.82 mΩ for RDS(on) and a worst-case motor current of 50 A, 公式 14 shows the
calculated the value of the VDS monitors.
VDS _ OCP > 50 A ì 8.82 mW
VDS _ OCP > 0.441 V
(14)
For this example, the value of VDS_OCP was selected as 0.51 V.
The deglitch time for the VDS overcurrent monitor is fixed at 4.5 µs.
8.2.1.2.4 Sense-Amplifier Bidirectional Configuration
The sense-amplifier gain and the sense-resistor value on the DRV8304 device are selected based on the target
current range, VREF voltage supply, sense-resistor power rating, and operating temperature range. In
bidirectional operation of the sense amplifier, the dynamic range at the output is approximately calculated as
shown in 公式 15.
VVREF
VO = V
- 0.25 V -
(
)
VREF
2
(15)
47
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Use 公式 16 to calculate the approximate value of the selected sense resistor with VO calculated using 公式 15.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
(16)
From 公式 15 and 公式 16, select a target gain setting based on the power rating of the target-sense resistor.
8.2.1.2.4.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from –20 to +20 A. The
linear range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range
of the sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
V = 3.3 V - 0.25 V -
= 1.4 V
(
)
O
2
(17)
(18)
(19)
1.4 V
AV ì 20 A
1.4 V
AV ì 20 A
R =
2 W > 14.142 ì R ç R < 10 mW
10 mW >
ç AV > 7
Therefore, the gain setting must be selected as 10 V/V or 20 V/V and the value of the sense resistor must be
less than 10 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 10 V/V. The value of the resistor and worst case current can be verified that R < 10 mΩ and Imax
=
20 A does not violate the differential range specification of the sense amplifier input (VSPxD).
I
SP
SO
R
AV
SN
SO
VREF
SP œ SN
VVREF œ 0.25 V
œ0.3 V
œI × R
VSO(rangeœ)
VSO(off)max
VVREF / 2
VSO(off)min
VOFF
VDRIFT
,
0 V
VSO(range+)
I × R
0.3 V
0.25 V
0 V
图 46. Sense Amplifier Configuration
48
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
8.2.1.3 Application Curves
图 47. IDRIVE Maximum Setting
图 48. IDRIVE Minimum Setting
图 49. Gate Drive 80% Duty Cycle
图 50. Gate Drive 20% Duty Cycle
图 51. Motor Operation at 80% PWM Duty
图 52. Motor Operation at 20% PWM Duty
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图 53. Motor Starting With PWM Duty Change
图 54. Motor Starting With Supply Voltage Change
图 55. Motor Performance at Speed Change
图 56. Motor Performance at Load Change
50
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
8.2.2 Alternative Application
In this application, a single-sense amplifier is used in unidirectional mode for a summing current-sense scheme
often used in trapezoidal or hall-based BLDC commutation control.
VM
Power and Charge Pump
3.3 V, 30 mA
DVDD
AGND
VM
GND
1 …F
Three Phase Inverter
VM
GND
Gate Driver
VDD
GND
BLDC Motor
GHA
SHA
GLA
Power
GPIO
GP-O
GP-O
GP-I
ENABLE
CAL
nFAULT
GHB
SHB
GLB
PWM1, PWW2
PWM3, PWM4
PWM5, PWM6
INHA, INLA
INHB,INLB
INHC, INLC
PWM
Module
GHC
SHC
GLC
Smart Gate Drive
150 mA, 300 mA
(Fully Protected)
SCLK
SPI
SCLK
SDI
SDO
nSCS
MODE
IDRIVE
VDS
Current Sense
SDI
(DAC and External
Resistor for H/W I/F)
SDO
nSCS
GAIN
Analog-to-Digital
Converters
SOA
SOB
SOC
SPA, SNA
SPV, SNB
SPC, SNC
1x ADC
CSA Output
Single Channel
Microcontroller
DRV8304
图 57. Alternative Application Schematic
8.2.2.1 Design Requirements
表 21 lists the example design input parameters for system design.
表 21. Design Parameters
EXAMPLE DESIGN PARAMETER
ADC reference voltage
Sensed current
REFERENCE
VVREF
EXAMPLE VALUE
3.3 V
0 to 20 A
14.14 A
ISENSE
IRMS
PSENSE
TA
Motor RMS current
Sense-resistor power rating
System ambient temperature
3 W
–20°C to +125°C
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Sense-Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on the SPI device by writing a 0b to
the VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use 公式 20 to calculate the approximate value of the dynamic range at the output.
V = V
- 0.25 V - 0.25 V = VVREF - 0.5 V
O
VREF
(20)
Use 公式 21 to calculate the approximate value of the selected sense resistor.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
where
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VO = VVREF - 0.5 V
•
(21)
From 公式 20 and 公式 21, select a target gain setting based on the power rating of a target sense resistor.
8.2.2.2.1.1 Example
In this system example, the value of VREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8304 device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO = 3.3 V - 0.5 V = 2.8 V
(22)
(23)
(24)
2.8 V
R =
3 W > 14.142 ì R ç R < 15 mW
AV ì 20 A
2.8 V
15 mW >
ç AV > 9.3
AV ì 20 A
Therefore, the gain setting must be selected as 10 V/V or 20 V/V and the value of the sense resistor must be
less than 15 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 15 mΩ and Imax
=
20 A does not violate the differential range specification of the sense amplifier input (VSPxD).
I
SP
SO
R
AV
SN
SO
V
REF
V
VREF
œ 0.25 V
V
SO(off)max
SP œ SN
V
,
OFF
0 V
V
œ 0.3 V
VREF
V
DRIFT
V
SO(off)min
V
SO(range)
I × R
0.3 V
0.25 V
0 V
图 58. Sense Amplifier Configuration
52
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ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
9 Power Supply Recommendations
The DRV8304 device is designed to operate from an input voltage supply (VM) range from 6 V to 38 V. A 0.1-µF
ceramic capacitor rated for VM must be placed as close to the device as possible. In addition, a bulk capacitor
must be included on the VM pin but can be shared with the bulk bypass capacitance for the external power
MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs and should be
sized according to the application requirements.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 59. Motor Drive Supply Parasitics Example
版权 © 2017–2018, Texas Instruments Incorporated
53
DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 22 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R
or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the
AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SNx pins directly to the PGND pin. Instead, use dedicated traces to
connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more
accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
54
版权 © 2017–2018, Texas Instruments Incorporated
DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
10.2 Layout Example
S
S
S
G
D
D
D
D
G
N
D
GND
D
D
D
D
G
S
S
S
GND
GND
31
20
19
18
17
16
15
14
13
12
11
CAL
AGND
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
32
D
D
D
D
G
S
S
S
33
DVDD
INHA
INLA
INHB
INLB
INHC
INLC
PGND
DVDD
INHA
INLA
INHB
INLB
INHC
INLC
34
35
36
37
38
39
40
DRV8304RH
A
Thermal Pad
S
S
S
G
D
D
D
D
GND
GND
S
S
S
G
D
D
D
D
GND
G
S
S
S
D
D
D
D
GND
图 60. Layout Example
版权 © 2017–2018, Texas Instruments Incorporated
55
DRV8304
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
请参阅以下 TI 设计以获取开发支持：
效率大于 95% 且适用于无刷直流伺服驱动器的 10.8V/30W 4.3cm2 功率级参考设计 TI 设计
11.1.1 器件命名规则
下图显示了说明完整器件名称的图例：
(4)
(RHA) (R)
(H)
DRV830
Prefix
Tape and Reel
DRV83 œ Brushless-DC three-phase
R œ Tape and Reel (higher SPQ)
T œ Small Tape and Reel
Package
RHA œ 6 × 6 × 0.9 mm QFN
Series
4 œ 40 V device
Interface
S œ SPI
H œ Hardware
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《AN-1149 开关电源布局指南》应用报告
德州仪器 (TI)，《BOOSTXL-DRV8304H EVM 用户指南》用户指南
德州仪器 (TI)，《BOOSTXL-DRV8304x EVM GUI 用户指南》用户指南
德州仪器 (TI)，《BOOSTXL-DRV8304x EVM 传感器式软件用户指南》用户指南
德州仪器 (TI)，《BOOSTXL-DRV8304x EVM 无传感器软件用户指南》用户指南
德州仪器 (TI)，《轻松实现无刷直流电机 - 传感器式电机控制》TI 技术手册
德州仪器 (TI)，《使用 TI 智能栅极驱动器轻松实现无刷直流 (BLDC) 电机的场定向控制 (FOC)》TI 技术手册
德州仪器 (TI)，《采用 BLDC 电机的高效真空吸尘器硬件设计注意事项》应用报告
德州仪器 (TI)，《采用 BLDC 电机的电动自行车硬件设计注意事项》应用报告
德州仪器 (TI)，《工业电机驱动解决方案指南》
德州仪器 (TI)，《开关电源布局指南》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术进行电机驱动保护》TI 技术手册
德州仪器 (TI)，《QFN/SON PCB 连接》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术缩减电机驱动 BOM 和 PCB 面积》TI 技术手册
德州仪器 (TI)，《采用 TI 智能栅极驱动技术降低 EMI 辐射发射》TI 技术手册
德州仪器 (TI)，《采用 MSP430™ 的传感器式三相 BLDC 电机控制》应用报告
德州仪器 (TI)，《TI 电机栅极驱动器的 IDRIVE 和 TDRIVE 认知》应用报告
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
56
版权 © 2017–2018, Texas Instruments Incorporated
DRV8304
www.ti.com.cn
ZHCSI91B –NOVEMBER 2017–REVISED JULY 2018
社区资源 (接下页)
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
设计支持
11.5 商标
NexFET, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
57
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8304HRHAR
DRV8304HRHAT
DRV8304SRHAR
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
DRV8304H
Samples
Samples
Samples
NIPDAU
NIPDAU
DRV8304H
DRV8304S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8304HRHAR
DRV8304HRHAT
DRV8304SRHAR
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
2500
250
330.0
180.0
330.0
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8304HRHAR
DRV8304HRHAT
DRV8304SRHAR
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
2500
250
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040E
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.15
5.85
A
B
PIN 1 INDEX AREA
6.15
5.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
3.52 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
11
20
10
21
SYMM
41
2X 4.5
2.62 0.1
30
36X 0.5
1
0.30
0.18
40X
31
40
PIN 1 ID
0.1
C A B
0.5
0.3
0.05
40X
4219054/A 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.52)
SYMM
SEE SOLDER MASK
DETAIL
31
40
40X (0.6)
40X (0.24)
1
30
36X (0.5)
(2.62)
41
SYMM
(5.8)
(1.06)
(
0.2) TYP
VIA
(R0.05) TYP
21
10
11
20
(0.6)
TYP
(0.91)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219054/A 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2)
31
40
40X (0.6)
30
40X (0.24)
1
36X (0.5)
(0.675)
(5.8)
41
SYMM
6X (1.15)
(R0.05) TYP
21
10
20
11
SYMM
6X (1)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219054/A 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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