DRV8316C_技术文档

DRV8316C

ZHCSR87 –DECEMBER 2022

DRV8316C 三相集成式FET 电机驱动器

1 特性

3 说明

• 的三相BLDC 电机驱动器

DRV8316C 集成了三个 H 桥，具有40V 的绝对最大电

压和 95mΩ 的超低 R_DS(ON)（高侧 + 低侧），可为

12V/24V 无刷直流电机提供高功率驱动能力。

DRV8316C 提供集成电流检测功能，无需再使用外部

检测电阻。DRV8316C 集成了电源管理电路，包括可

用于为外部电路供电的电压可调节降压稳压器

（3.3V/5V，200mA）和LDO (3.3V/30mA)。

– 逐周期电流限制，可限制相位电流

– 支持高达200kHz 的PWM 频率

– 主动消磁支持减少功率损耗

• 4.5V 至35V 工作电压（绝对最大值40V）

• 高输出电流能力：8A 峰值

• 低MOSFET 导通状态电阻

– T_A= 25°C 时，R_DS(ON)(HS + LS) 为95 mΩ

• 低功耗睡眠模式

DRV8316C 提供了可配置的 6x 或 3x PWM 控制方

案，可用于使用外部微控制器实施有传感器或无传感器

磁场定向控制 (FOC) 、正弦控制或梯形控制。

DRV8316C 能够驱动高达 200kHz 的 PWM 频率。

DRV8316C 可通过 SPI (DRV8316CR) 或引脚

(DRV8316CT) 进行高度配置。PWM 模式、压摆率、

OCP 电平、电流检测增益是部分可配置的特性。

– 1.5 µA（V_VM= 24V，T_A= 25°C）

• 多种控制接口选项

– 6x PWM 控制接口

– 3x PWM 控制接口

– 具有逐周期电流限制的6x PWM 控制接口

– 具有逐周期电流限制的3x PWM 控制接口

• 不需要外部电流感测电阻器，内置电流感测功能

• 灵活的器件配置选项

DRV8316C 集成了多种保护特性，包括电源欠压锁定

(UVLO)、过压保护 (OVP)、电荷泵欠压 (CPUV)、过

流保护 (OCP) 、过热警告 (OTW) 和过热关断

(OTSD)，目的是在出现故障事件时保护器件、电机和

系统。故障状态通过nFAULT 引脚指示。

– DRV8316CR：用于器件配置和故障状态的5

MHz 16 位SPI 接口

– DRV8316CT：基于硬件引脚的配置

• 支持1.8V、3.3V 和5V 逻辑输入

• 内置3.3V (5%)、30mA LDO 稳压器

• 内置3.3V/5V、200mA 降压稳压器

• 内置3.3V、30mA LDO

有关器件使用的设计考虑因素和建议，请参考

Application Information。

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

7.00mm x 5.00mm

• 延迟补偿减少占空比失真

• 整套集成保护特性

DRV8316CR

DRV8316CT

VQFN (40)

– 电源欠压锁定(UVLO)

– 电荷泵欠压(CPUV)

– 过流保护(OCP)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 热警告和热关断(OTW/OTSD)

– 故障条件指示引脚(nFAULT)

– 可选择通过SPI 接口进行故障诊断

LDO out

3.3-V, up to 30-mA

4.5V to 35V (40V abs max)

Buck out

3.3 or 5.0 V, up to 200mA

6x / 3x PWM

PWM input

MCU

DRV8316C

A

B

C

nSLEEP

Charge Pump

2 应用

DRVOFF

Built-in Protec on

• CPAP 呼吸机

• 无刷直流(BLDC) 电机模块

• 打印机

• 云台相机

• HVAC 电机

• 小型家用电器

• 办公自动化设备

• 工厂自动化和机器人

CSA out

nFAULT

Buck/LDO Regulator

Integrated Current Sensing

8-A peak output current,

typically 12-V/24-V,

<80W motors

SPI

Only on SPI

variant

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSH07

DRV8316C

ZHCSR87 –DECEMBER 2022

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Table of Contents

8.5 SPI Communication.................................................. 55

8.6 Register Map.............................................................58

9 Application and Implementation..................................70

9.1 Application Information............................................. 70

9.2 Typical Applications.................................................. 71

10 Power Supply Recommendations..............................83

10.1 Bulk Capacitance....................................................83

11 Layout...........................................................................84

11.1 Layout Guidelines................................................... 84

11.2 Layout Example...................................................... 85

11.3 Thermal Considerations..........................................86

12 Device and Documentation Support..........................87

12.1 Documentation Support.......................................... 87

12.2 支持资源..................................................................87

12.3 Trademarks.............................................................87

12.4 Electrostatic Discharge Caution..............................87

12.5 术语表..................................................................... 87

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table ..............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................7

7.6 SPI Timing Requirements......................................... 14

7.7 SPI Slave Mode Timings...........................................15

7.8 Typical Characteristics..............................................15

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................54

Information.................................................................... 87

4 Revision History

DATE

REVISION

NOTES

December 2022

*

Initial release.

2

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5 Device Comparison Table

DEVICE

PACKAGES

INTERFACE

SPI

BUCK REGULATOR

DRV8316CR

40-pin VQFN (7x5 mm)

Yes

DRV8316CT

Hardware (Pin)

表5-1. DRV8316CR (SPI variant) vs. DRV8316CT (Hardware variant) configuration comparison

Parameters

DRV8316CR (SPI variant)

PWM_MODE (4 settings)

SLEW (4 settings)

DRV8316CT (Hardware variant)

MODE pin (4 settings)

SLEW pin (4 settings)

GAIN pin (4 settings)

Push-Pull mode

PWM mode

Slew rate

CSA gain

CSA_GAIN (4 settings)

SDO_MODE (2 settings)

DRV_OFF (2 settings)

OCP_LVL (2 settings)

OCP_MODE (4 settings)

OCP_RETRY (2 settings)

OVP_EN (2 settings)

SDO pin configuration

DRVOFF pin configuration

OCP level

Enabled

OCP/SR pin (2 settings)

Latched fault

OCP mode

OCP retry time

N/A since OCP mode is latched fault

Enabled

Overvoltage protection (OVP)

OVP threshold

OVP_SEL (2 settings)

34-V

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6 Pin Configuration and Functions

32

31

30

29

28

27

26

25

24

23

22

21

INLC

NC

AGND

FB_BK

GND_BK

SW_BK

CPL

1

2

32

31

30

29

28

27

26

25

24

23

22

21

INLC

NC

AGND

FB_BK

GND_BK

SW_BK

CPL

1

2

INHC

3

INLB

3

INLB

4

INHB

4

INHB

5

INLA

5

INLA

6

INHA

6

INHA

Thermal Pad

CPH

7

AGND

AVDD

NC

CPH

7

AGND

AVDD

VSEL_BK

nSLEEP

nFAULT

DRVOFF

CP

8

CP

8

VM

9

VM

9

VM

10

11

12

nSLEEP

nFAULT

DRVOFF

VM

10

11

12

VM

PGND

图6-1. DRV8316CR 40-Pin VQFN With Exposed

图6-2. DRV8316CT 40-Pin VQFN With Exposed

Thermal Pad Top View

表6-1. Pin Functions

40-pin Package

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8316CR

DRV8316CT

AGND

2, 26

GND

Device analog ground. Refer 节11.1 for connections recommendation.

3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic

AVDD

CP

25

8

PWR O capacitor between the AVDD and AGND pins. This regulator can source up to

30 mA externally.

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor

8

PWR O

between the CP and VM pins.

CPH

CPL

7

6

7

6

PWR

Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic

capacitor between the CPH and CPL pins. TI recommends a capacitor voltage

rating at least twice the normal operating voltage of the device.

When this pin is pulled high the six MOSFETs in the power stage are turned

OFF making all outputs Hi-Z.

DRVOFF

FB_BK

21

3

21

3

I

Feedback for buck regulator. Connect to buck regulator output after the

inductor/resistor.

PWR I

GAIN

36

4

I

Amplifier gain setting. The pin is a 4-level input pin set by an external resistor.

—

GND_BK

4

GND

Buck regulator ground. Refer 节11.1 for connections recommendation.

High-side driver control input for OUTA. This pin controls the output of the

high-side MOSFET.

INHA

INHB

INHC

INLA

27

29

31

28

27

29

31

28

I

High-side driver control input for OUTB. This pin controls the output of the

high-side MOSFET.

High-side driver control input for OUTC. This pin controls the output of the

high-side MOSFET.

Low-side driver control input for OUTA. This pin controls the output of the low-

side MOSFET.

4

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表6-1. Pin Functions (continued)

40-pin Package

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8316CR

DRV8316CT

Low-side driver control input for OUTB. This pin controls the output of the low-

side MOSFET.

INLB

INLC

30

32

30

I

Low-side driver control input for OUTC. This pin controls the output of the low-

side MOSFET.

32

PWM input mode setting. This pin is a 4-level input pin set by an external

resistor.

MODE

NC

33

1

I

—

1, 24

No connection, open

—

Fault indicator. Pulled logic-low with fault condition; Open-drain output requires

an external pull-up resistor to 1.8 V to 5.0 V. If external supply is used to pull

up nFAULT, ensure that it is pulled to >2.2 V on power up or the device will

enter test mode

nFAULT

22

O

Serial chip select. A logic low on this pin enables serial interface

communication.

nSCS

36

23

—

I

—

23

35

Driver nSLEEP. When this pin is logic low, the device goes into a low-power

sleep mode. A 20 to 40-µs low pulse can be used to reset fault conditions

without entering sleep mode.

nSLEEP

OCP/SR

OCP level and Synchronous Rectification (Active Demagnetization) setting.

This pin is a 4-level input pin set by an external resistor.

OUTA

OUTB

OUTC

PGND

13, 14

16, 17

13, 14

16, 17

PWR O Half bridge output A

PWR O Half bridge output B

PWR O Half bridge output C

19, 20

12, 15, 18

GND

I

Device power ground. Refer 节11.1 for connections recommendation.

Serial clock input. Serial data is shifted out and captured on the corresponding

rising and falling edge on this pin (SPI devices).

SCLK

SDI

35

34

33

—

34

40

39

Serial data input. Data is captured on the falling edge of the SCLK pin (SPI

devices).

I

Serial data output. Data is shifted out on the rising edge of the SCLK pin. This

pin requires an external pullup resistor (SPI devices).

SDO

SLEW

SOA

SOB

O

I

Slew rate control setting. This pin is a 4-level input pin set by an external

resistor.

—

40

39

Current sense amplifier output. Supports capacitive load or low pass filter

(resistor in series and capacitor to GND)

O

Current sense amplifier output. Supports capacitive load or low pass filter

(resistor in series and capacitor to GND)

Current sense amplifier output. Supports capacitive load or low pass filter

(resistor in series and capacitor to GND)

SOC

38

5

38

5

SW_BK

PWR O Buck switch node. Connect this pin to an inductor or resistor.

Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1-

µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI

PWR I

VM

9, 10, 11

24

recommends a capacitor voltage rating at least twice the normal operating

voltage of the device.

Buck output voltage setting. This pin is a 4-level input pin set by an external

resistor.

VSEL_BK

I

—

VREF in PWM Mode 1 and Mode 3: Current sense amplifier power supply

input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor

VREF/ILIM

37

PWR/I

GND

between the VREF and AGND pins.

ILIM in PWM Mode 2 and Mode 4: Sets the threshold for phase current used

in cycle by cycle current limit.

Thermal

pad

Must be connected to analog ground.

(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

Power supply pin voltage (VM)

40

4

V

V/µs

V

–0.3

Power supply voltage ramp (VM)

Voltage difference between ground pins (GND_BK, PGND, AGND)

Charge pump voltage (CPH, CP)

0.3

–0.3

–1

V_M+ 6

V_M+ 0.3

5.75

V

Charge pump negative switching pin voltage (CPL)

Switching regulator pin voltage (FB_BK)

Switching node pin voltage (SW_BK)

Analog regulator pin voltage (AVDD)

Logic pin input voltage (DRVOFF, INHx, INLx, nSCS, nSLEEP, SCLK, SDI)

Logic pin output voltage (nFAULT, SDO)

Output pin voltage (OUTA, OUTB, OUTC)

Ambient temperature, T_A

V

V_M+ 0.3

4

V

5.75

V

5.75

V

V_M+ 1

125

V

°C

–40

–65

Junction temperature, T_J

150

Storage tempertaure, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_VM

f_PWM

I_OUT

Power supply voltage

V_VM

4.5

24

35

200

8

V

kHz

A

Output PWM frequency

Peak output winding current

OUTA, OUTB, OUTC

(1)

DRVOFF, INHx, INLx, nSCS, nSLEEP,

SCLK, SDI

V_IN

Logic input voltage

5.5

V

–0.1

V_OD

Open drain pullup voltage

Push-pull voltage

nFAULT, SDO

SDO

5.5

V

–0.1

V_SDO

I_OD

V_VREF

T_A

2.2

Open drain output current

Voltage reference pin voltage

Operating ambient temperature

Operating Junction temperature

nFAULT, SDO

VREF

5

mA

V

2.8

–40

AVDD

125

150

°C

T_J

(1) Power dissipation and thermal limits must be observed

6

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7.4 Thermal Information

DRV8316CR,

DRV8316CT

VQFN (RGF)

40 Pins

25.7

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

15.2

7.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

7.2

Ψ_JB

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES

V_VM> 6 V, nSLEEP = 0, T_A= 25 °C

nSLEEP = 0

1.5

2.5

5

µA

I_VMQ

VM sleep mode current

nSLEEP = 1, INHx = INLx = 0, SPI =

'OFF', BUCK_DIS = 1;

4

10 mA

VM standby mode current

(Buck regulator disabled)

I_VMS

V_VM> 6 V, nSLEEP = 1, INHx = INLx =

0, SPI = 'OFF', T_A= 25 °C, BUCK_DIS =

1;

5

6

mA

V_VM> 6 V, nSLEEP = 1, INHx = INLx =

0, SPI = 'OFF', I_BK= 0, T_A= 25

°C, BUCK_DIS = 0;

5

VM standby mode current

(Buck regulator enabled)

I_VMS

nSLEEP = 1, INHx = INLx = 0, SPI =

'OFF', I_BK= 0, BUCK_DIS = 0;

6

10

18

11

17

10 mA

13 mA

21 mA

16 mA

25 mA

V_VM> 6 V, nSLEEP = 1, f_PWM= 25 kHz,

T_A= 25 °C, BUCK_DIS = 1

V_VM> 6 V, nSLEEP = 1, f_PWM= 200 kHz,

T_A= 25 °C, BUCK_DIS = 1

VM operating mode current

(Buck regulator disabled)

I_VM

nSLEEP =1, f_PWM= 25 kHz, BUCK_DIS

= 1

nSLEEP =1, f_PWM= 200 kHz,

BUCK_DIS = 1

V_VM> 6 V, nSLEEP = 1, f_PWM= 25 kHz,

T_A= 25 °C, BUCK_DIS =

0; BUCK_PS_DIS = 0

11

19

13 mA

22 mA

V_VM> 6 V, nSLEEP = 1, f_PWM= 200 kHz,

T_A= 25 °C, BUCK_DIS =

VM operating mode current

(Buck regulator enabled)

I_VM

0; BUCK_PS_DIS = 0

nSLEEP =1, f_PWM= 25 kHz, BUCK_DIS

= 0; BUCK_PS_DIS = 0

12

18

17 mA

27 mA

nSLEEP =1, f_PWM= 200 kHz,

BUCK_DIS = 0; BUCK_PS_DIS = 0

0 mA ≤I_AVDD≤30 mA; BUCK_PS_DIS

= 0

V_AVDD

Analog regulator voltage

3.1

3.6

3.3

3.465

V

I_AVDD

V_VCP

External analog regulator load

Charge pump regulator voltage

30 mA

VCP with respect to VM

4.7

5.25

V

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_CP

Charge pump switching frequency

400

kHz

V_VM> V_UVLO, nSLEEP = 1 to outputs

ready and nFAULT released

t_WAKE

Wakeup time

1

ms

t_SLEEP

t_RST

Sleep Pulse time

Reset Pulse time

nSLEEP = 0 period to enter sleep mode

nSLEEP = 0 period to reset faults

120

20

µs

40

BUCK REGULATOR

V_VM> 6 V, 0 mA ≤I_BK≤200 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

5.0

4.0

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤I_BK≤200 mA,

BUCK_SEL = 01b

Buck regulator average voltage

V_VM> 6 V, 0 mA ≤I_BK≤200 mA,

BUCK_SEL = 10b

V_BK

(L_BK= 47 µH, C_BK= 22 µF)

(SPI Device)

V_VM> 6.7 V, 0 mA ≤I_BK≤200 mA,

BUCK_SEL = 11b

5.7

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤I_BK≤200 mA

V_VM–

V

I_BK*(R_LBK

+

2)⁽¹⁾

V_VM> 6 V, 0 mA ≤I_BK≤50 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤I_BK≤50 mA,

BUCK_SEL = 01b

5.0

4.0

Buck regulator average voltage

(L_BK= 22 µH, C_BK= 22 µF)

(SPI Device)

V_VM> 6 V, 0 mA ≤I_BK≤50 mA,

BUCK_SEL = 10b

V_VM> 6.7 V, 0 mA ≤I_BK≤50 mA,

BUCK_SEL = 11b

5.7

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤I_BK≤50 mA

V_VM–

V

I_BK*(R_LBK

+

2) ⁽¹⁾

V_VM> 6 V, 0 mA ≤I_BK≤40 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤I_BK≤40 mA,

BUCK_SEL = 01b

5.0

4.0

5.7

Buck regulator average voltage

(R_BK= 22 Ω, C_BK= 22 µF)

(SPI Device)

V_VM> 6 V, 0 mA ≤I_BK≤40 mA,

BUCK_SEL = 10b

V_VM> 6.7 V, 0 mA ≤I_BK≤40 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤I_BK≤40 mA

V_VM–

I_BK*(R_BK+2

)

V

V_VM> 6 V, 0 mA ≤I_BK≤200 mA,

VSEL_BK pin tied to AGND

3.1

4.6

3.3

5.0

3.5

5.4

V

V_VM> 6 V, 0 mA ≤I_BK≤200

mA, VSEL_BK pin to Hi-Z

V_VM> 6 V, 0 mA ≤I_BK≤200

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(L_BK= 47 µH, C_BK= 22 µF)

(HW Device)

3.7

5.2

4.0

4.3

6.2

V

V_BK

V_VM> 6.7 V, 0 mA ≤I_BK≤200 mA,

VSEL_BK pin tied to AVDD

5.7

V_VM–

V_VM< 6.0 V, 0 mA ≤I_BK≤200 mA

I_BK*(R_LBK

+

2)⁽¹⁾

8

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VM> 6 V, 0 mA ≤I_BK≤50 mA,

VSEL_BK pin tied to AGND

3.1

3.3

3.5

5.4

V

V_VM> 6 V, 0 mA ≤I_BK≤50

mA, VSEL_BK pin to Hi-Z

4.6

3.7

5.2

5.0

4.0

V_VM> 6 V, 0 mA ≤I_BK≤50

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(L_BK= 22 µH, C_BK= 22 µF)

(HW Device)

4.3

6.2

V

V_BK

V_VM> 6.7 V, 0 mA ≤I_BK≤50 mA,

VSEL_BK pin tied to AVDD

5.7

V_VM–

V_VM< 6.0 V, 0 mA ≤I_BK≤50 mA

I_BK*(R_LBK

+

2)⁽¹⁾

V_VM> 6 V, 0 mA ≤I_BK≤40 mA,

VSEL_BK pin tied to AGND

3.1

4.6

3.3

3.5

5.4

V

V_VM> 6 V, 0 mA ≤I_BK≤40

mA, VSEL_BK pin to Hi-Z

5.0

4.0

5.7

V_VM> 6 V, 0 mA ≤I_BK≤40

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(R_BK= 22 Ω, C_BK= 22 µF)

(HW Device)

3.7

5.2

4.3

6.2

V

V_BK

V_VM> 6.7 V, 0 mA ≤I_BK≤40 mA,

VSEL_BK pin tied to AVDD

V_VM–

I_BK*(R_BK+2

)

V_VM< 6.0 V, 0 mA ≤I_BK≤40 mA

V_VM> 6 V, 0 mA ≤I_BK≤200 mA, Buck

regulator with inductor, L_BK= 47 uH, C_BK

= 22 µF

100 mV

–100

V_VM> 6 V, 0 mA ≤I_BK≤50 mA, Buck

regulator with inductor, L_BK= 22 uH, C_BK

= 22 µF

V_{BK_RIP}

Buck regulator ripple voltage

V_VM> 6 V, 0 mA ≤I_BK≤50 mA, Buck

regulator with resistor; R_BK= 22 Ω, C_BK

= 22 µF

100 mV

200 mA

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 1b

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

200 –

I_AVDD

mA

L_BK= 22 uH, C_BK

22 µF, BUCK_PS_DIS = 1b

=

50 mA

I_BK

External buck regulator load

L_BK= 22 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

50 –

I_AVDD

mA

R_BK= 22 Ω, C_BK

=

40 mA

22 µF, BUCK_PS_DIS = 1b

R_BK= 22 Ω, C_BK= 22 µF,

BUCK_PS_DIS = 0b

40 –

I_AVDD

mA

Regulation Mode

Linear Mode

20

535 kHz

f_{SW_BK}

Buck regulator switching frequency

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

V_BKrising, BUCK_SEL = 00b

V_BKfalling, BUCK_SEL = 00b

V_BKrising, BUCK_SEL = 01b

V_BKfalling, BUCK_SEL = 01b

V_BKrising, BUCK_SEL = 10b

V_BKfalling, BUCK_SEL = 10b

V_BKrising, BUCK_SEL = 11b

V_BKfalling, BUCK_SEL = 11b

V_BKrising, VSEL_BK pin tied to AGND

V_BKfalling, VSEL_BK pin tied to AGND

MIN

2.7

2.5

4.2

4.0

2.7

2.5

4.2

4

TYP

2.8

2.6

4.4

4.2

2.8

2.6

4.4

4.2

2.8

2.6

MAX UNIT

2.9

2.7

V

4.55

4.35

2.9

Buck regulator undervoltage lockout

(SPI Device)

V_{BK_UV}

2.7

4.55

4.35

2.9

2.7

2.5

2.7

V_BKrising, VSEL_BK pin to 47 kΩ+/-

5% tied to AVDD

4.3

4.1

4.4

4.2

4.5

4.3

V

V_BKfalling, VSEL_BK pin to 47 kΩ+/-

5% tied to AVDD

Buck regulator undervoltage lockout

(HW Device)

V_{BK_UV}

V_BKrising, VSEL_BK pin to Hi-Z

2.7

2.5

4.2

4.0

2.8

2.6

4.4

4.2

2.9

2.7

V

V_BKfalling, VSEL_BK pin to Hi-Z

V_BKrising, VSEL_BK pin tied to AVDD

V_BKfalling, VSEL_BK pin tied to AVDD

4.55

4.35

Buck regulator undervoltage lockout

hysteresis

V_{BK_UV_HYS}

Rising to falling threshold

90

200

320 mV

BUCK_CL = 0b

BUCK_CL = 1b

360

80

600

150

900 mA

250 mA

Buck regulator Current limit threshold

(SPI Device)

I_{BK_CL}

Buck regulator Current limit threshold

(HW Device)

I_{BK_CL}

360

600

900 mA

Buck regulator Overcurrent protection

trip point

I_{BK_OCP}

2

3

1

4

A

t_{BK_RETRY}

Overcurrent protection retry time

0.7

1.3 ms

LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP, SCLK, SDI)

V_IL

Input logic low voltage

0

1.5

1.6

180

95

0.6

5.5

V

Other Pins

V_IH

Input logic high voltage

nSLEEP

Other PIns

300

250

420 mV

V_HYS

I_IL

Input logic hysteresis

Input logic low current

Input logic high current

nSLEEP

V_PIN(Pin Voltage) = 0 V

nSLEEP, V_PIN(Pin Voltage) = 5 V

Other pins, V_PIN(Pin Voltage) = 5 V

nSLEEP

1

30

µA

kΩ

pF

–1

10

I_IH

30

75

150

70

200

100

30

300

130

R_PD

C_ID

Input pulldown resistance

Input capacitance

Other pins

LOGIC-LEVEL INPUTS (nSCS)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

Input logic high current

Input pullup resistance

Input capacitance

0

1.5

0.6

5.5

V

V_IH

V_HYS

I_IL

180

300

420 mV

V_PIN(Pin Voltage) = 0 V

V_PIN(Pin Voltage) = 5 V

75

25

µA

I_IH

–1

R_PU

C_ID

80

100

30

130

kΩ

pF

10

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FOUR-LEVEL INPUTS (GAIN, MODE, SLEW, VSEL_BK)

0.2*AVD

V_L1

V_L2

V_L3

V_L4

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Tied to AGND

0

V

D

0.27*AV

DD

0.545*AV

DD

Hi-Z

0.5*AVDD

0.606*AV 0.757*AVD 0.909*AV

47 kΩ+/- 5% tied to AVDD

Tied to AVDD

DD

D

DD

0.945*AV

DD

AVDD

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

70

100

130

kΩ

Input pulldown resistance

FOUR-LEVEL INPUTS (OCP/SR)

0.09*AV

DD

V_L1

V_L2

V_L3

V_L4

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Tied to AGND

22 kΩ ± 5% to AGND

Hi-Z

0

V

0.12*AV

DD

0.2*AVD

D

0.15*AVDD

0.5*AVDD

0.45*AV

DD

0.55*AV

DD

0.94*AV

DD

Tied to AVDD

AVDD

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

80

100

120

kΩ

Input pulldown resistance

OPEN-DRAIN OUTPUTS (nFAULT)

V_OL

I_OH

Output logic low voltage

Output logic high current

Output capacitance

I_OD= 5 mA

V_OD= 5 V

0.4

1

V

µA

pF

–1

C_OD

30

PUSH-PULL OUTPUTS (SDO)

V_OL

V_OH

I_OL

Output logic low voltage

I_OP= 5 mA

V_OP= 0 V

V_OP= 5 V

0

2.2

–1

0.4

5.5

1

V

Output logic high voltage

V

Output logic low leakage current

Output logic high leakage current

Output capacitance

µA

pF

I_OH

1

C_OD

30

DRIVER OUTPUTS

V_VM> 6 V, I_OUT= 1 A, T_A= 25°C

V_VM< 6 V, I_OUT= 1 A, T_A= 25°C

V_VM> 6 V, I_OUT= 1 A, T_J= 150 °C

V_VM< 6 V, I_OUT= 1 A, T_J= 150 °C

95

105

140

145

120

130

185

190

mΩ

Total MOSFET on resistance (High-side

+ Low-side)

R_DS(ON)

V_VM= 24 V, SLEW = 00b or SLEW pin

tied to AGND

14

30

25

50

45 V/µs

80 V/µs

185 V/µs

280 V/µs

V_VM= 24 V, SLEW = 01b or SLEW pin to

Hi-Z

Phase pin slew rate switching low to high

(Rising from 20 % to 80 %)

SR

V_VM= 24 V, SLEW = 10b or SLEW pin to

47 kΩ+/- 5% to AVDD

80

125

200

V_VM= 24 V, SLEW = 11b or SLEW pin

tied to AVDD

130

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VM= 24 V, SLEW = 00b or SLEW pin

tied to AGND

14

25

45 V/µs

V_VM= 24 V, SLEW = 01b or SLEW pin to

Hi-Z

30

80

50

125

200

80 V/µs

185 V/µs

280 V/µs

Phase pin slew rate switching high to low

(Falling from 80 % to 20 %)

SR

V_VM= 24 V, SLEW = 10b or SLEW pin to

47 kΩ+/- 5% to AVDD

V_VM= 24 V, SLEW = 11b or SLEW pin

tied to AVDD

110

Leakage current on OUTx

V_OUTx= V_VM, nSLEEP = 1

V_OUTx= 0 V, nSLEEP = 1

5

1

mA

µA

I_LEAK

V_VM= 24 V, SR = 25 V/µs, HS driver

OFF to LS driver ON and LS driver OFF

to HS driver ON

1800

1100

650

3400

1550

1000

750

ns

V_VM= 24 V, SR = 50 V/µs, HS driver

OFF to LS driver ON and LS driver OFF

to HS driver ON

Output dead time (high to low / low to

high)

t_DEAD

V_VM= 24 V, SR = 125 V/µs, HS driver

OFF to LS driver ON and LS driver OFF

to HS driver ON

V_VM= 24 V, SR = 200 V/µs, HS driver

OFF to LS driver ON and LS driver OFF

to HS driver ON

500

V_VM= 24 V, INHx/INLx = 1 to OUTx

transition, SR = 25 V/µs

2000

1200

800

4550

2150

1350

1050

ns

V_VM= 24 V, INHx/INLx = 1 to OUTx

transition, SR = 50V/µs

Propagation delay (high-side / low-side

ON/OFF)

t_PD

V_VM= 24 V, INHx/INLx = 1 to OUTx

transition, SR = 125 V/µs

V_VM= 24 V, INHx/INLx = 1 to OUTx

transition, SR = 200 V/µs

650

ns

t_{MIN_PULSE}

Minimum output pulse width

SR = 200 V/µs

600

CURRENT SENSE AMPLIFIER

CSA_GAIN = 00b

0.15

0.3

0.6

1.2

0.15

0.3

0.6

1.2

V/A

%

CSA_GAIN = 01b

G_CSA

Current sense gain (SPI Device)

CSA_GAIN = 10b

CSA_GAIN = 11b

GAIN pin tied to AGND

GAIN pin to Hi-Z

G_CSA

Current sense gain (HW Device)

GAIN pin to 47 kΩ ± 5% to AVDD

GAIN pin tied to AVDD

T_A= 25°C, 0A ≤I_PHASE≤4A

T_A= 25°C, 4A < I_PHASE≤6A

TJ = 0°C to 125°C, 0A ≤I_PHASE≤4A

T_J= 0°C to 125°C, 4A < I_PHASE≤6A

0A ≤I_PHASE≤4A

G_{CSA_ERR}

Current sense gain error

2

4.2

4

–4.5

-3.5

-5

%

-3.5

-5

6

%

4.5

6.5

3

%

-6

%

4A < I_PHASE≤6A

T_A= 25°C

%

–3

–5

Current sense gain error matching

between phases A, B and C

I_MATCH

5

%

V_VREF

–

V_LINEAR

SOX output voltage linear range

0.25

V

0.25

12

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

Phase current = 0 A, G_CSA= 0.15 V/A

Phase current = 0 A, G_CSA= 0.3 V/A

Phase current = 0 A, G_CSA= 0.6 V/A

Phase current = 0 A, G_CSA= 1.2 V/A

Step on SOX = 1.2 V, G_CSA= 0.15 V/A

Step on SOX = 1.2 V, G_CSA= 0.3 V/A

Step on SOX = 1.2 V, G_CSA= 0.6 V/A

Step on SOX = 1.2 V, G_CSA= 1.2 V/A

Phase current = 0 A

MIN

–50

TYP

MAX UNIT

50 mA

I_OFFSET

Current sense offset low side current in

1

μs

µA/℃

µA

t_SET

Settling time to ±1%, 30 pF

1

V_DRIFT

I_VREF

Drift offset

160

50

80

56

22

–160

VREF input current

VREF = 3.0 V

AVDD to SOx, DC

55

39

5

dB

PSRR

Power Supply Rejection Ratio

AVDD to SOx, 10 kHz

dB

AVDD to SOx, 500 kHz

dB

PULSE-BY-PULSE CURRENT LIMIT

AVDD/2

–0.4

Voltage on VLIM pin for cycle by cycle

current limit

V_LIM

AVDD/2

V

A

Current limit corresponding to VLIM pin

voltage range

I_LIMIT

0

8

I_{LIM_AC}

t_BLANK

Current limit accuracy

10

%

–10

Cycle by cycle current limit blank time

5

µs

PROTECTION CIRCUITS

VM rising

VM falling

4.3

4.1

4.4

4.2

4.5

4.3

V

V_UVLOSupply undervoltage lockout (UVLO)

V_{UVLO_HYS}Supply undervoltage lockout hysteresis Rising to falling threshold

140

200

350 mV

Supply undervoltage lockout deglitch

time

t_UVLO

3

32.5

31.8

20

5

34

33

22

21

7

35

µs

V

Supply rising, OVP_EN = 1, OVP_SEL =

0

Supply falling, OVP_EN = 1, OVP_SEL

= 0

34.3

23

V

Supply overvoltage protection (OVP)

(SPI Device)

V_OVP

Supply rising, OVP_EN = 1, OVP_SEL =

1

V

Supply falling, OVP_EN = 1, OVP_SEL

= 1

19

22

V

Supply overvoltage protection hysteresis Rising to falling threshold, OVP_SEL = 1

(OVP)

Rising to falling threshold, OVP_SEL = 0

(SPI Device)

0.9

0.7

1

1.1

0.9

V

V_{OVP_HYS}

0.8

Supply overvoltage protection deglitch

time

t_OVP

2.5

5

7

µs

Supply rising

2.3

2.2

75

2.5

2.4

2.7

2.6

V

Charge pump undervoltage lockout

(above VM)

V_CPUV

Supply falling

V_{CPUV_HYS}Charge pump UVLO hysteresis

Rising to falling threshold

Supply rising

100

2.85

2.65

140 mV

2.7

2.5

3

V

V_{AVDD_UV}

Analog regulator undervoltage lockout

Supply falling

2.8

V_{AVDD_}

Analog regulator undervoltage lockout

hysteresis

Rising to falling threshold

180

200

240 mV

UV_HYS

I_OCP

Overcurrent protection trip point

OCP_LVL = 0b or OCP pin tied to AGND

OCP_LVL = 1b or OCP pin tied to AVDD

10

15

16

24

22

30

A

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

0.06

0.2

0.6

1

TYP

MAX UNIT

OCP_DEG = 00b

0.3

0.7

1.2

1.8

2.5

µs

OCP_DEG = 01b

OCP_DEG = 10b

OCP_DEG = 11b

0.6

Overcurrent protection deglitch time

(SPI Device)

1.25

1.6

t_OCP

Overcurrent protection deglitch time

(HW Device)

0.06

0.3

0.6

6

µs

OCP_RETRY = 0

OCP_RETRY = 1

4

5

ms

Overcurrent protection retry time

(SPI Device)

t_RETRY

425

500

575 ms

Overcurrent protection retry time

(HW Device)

t_RETRY

4

5

6

ms

T_OTW

Thermal warning temperature

Thermal warning hysteresis

Die temperature (T_J)

135

15

145

20

155

25

°C

T_{OTW_HYS}

T_TSD

T_{TSD_HYS}

T_{TSD_FET}

Thermal shutdown temperature

Thermal shutdown hysteresis

Thermal shutdown temperature (FET)

170

15

180

20

190

25

165

175

185

T_{TSD_FET_HY}

Thermal shutdown hysteresis (FET)

Die temperature (T_J)

20

25

30

°C

S

(1) R_LBKis resistance of inductor L_BK

7.6 SPI Timing Requirements

MIN

NOM

MAX UNIT

t_READY

SPI ready after power up

nSCS minimum high time

nSCS input setup time

nSCS input hold time

1

ms

ns

t_{HI_nSCS}

t_{SU_nSCS}

t_{HD_nSCS}

t_SCLK

300

25

SCLK minimum period

SCLK minimum high time

SCLK minimum low time

SDI input data setup time

SDI input data hold time

SDO output data delay time

SDO enable delay time

SDO disable delay time

100

50

t_SCLKH

t_SCLKL

50

t_{SU_SDI}

t_{HD_SDI}

t_{DLY_SDO}

t_{EN_SDO}

t_{DIS_SDO}

25

50

14

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7.7 SPI Slave Mode Timings

t_{HD_nSCS}

t_{HI_nSCS}

t_{SU_nSCS}

t_SCLK

t_SCLKH

t_SCLKL

X

MSB

LSB

X

t_{DIS_SDO}

t_{DLY_SDO}

t_{SU_SDI}

t_{HD_SDI}

Z

MSB

LSB

Z

t_{EN_SDO}

图7-1. SPI Secondary Mode Timings

7.8 Typical Characteristics

17

16

15

160

150

140

130

F_PWM= 200 kHz

14

13

12

11

10

9

120

T_J= -40 C

110

100

90

T_J= 25 C

T_J= 150 C

80

F_PWM= 25 kHz

70

8

60

7

-40 -20

0

20

40

60

80 100 120 140

6

9

12

15

18

21

24

27

30

33

36

Junction Temperature (C)

Supply Voltage (V)

图7-3. R_DS(ON)(high and low side combined) for

图7-2. Supply current over supply voltage

MOSFETs over temperature

100

5.75

5.5

T_J= -40 C

97.5

T_J= 25 C

T_J= -150 C

5.25

5

95

92.5

90

4.75

BUCK_SEL = 00b

BUCK_SEL = 01b

BUCK_SEL = 10b

BUCK_SEL = 11b

4.5

87.5

85

4.25

4

82.5

80

3.75

3.5

3.25

3

77.5

75

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Buck Output Load Current (A)

4

8

12

16

20

24

28

32

36

Supply Voltage (V)

图7-5. Buck regulator output voltage over load

图7-4. Buck regulator efficiency over supply

current

voltage

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8 Detailed Description

8.1 Overview

The DRV8316C device is an integrated 95-mΩ (high-side + low-side MOSFET's on-state resistance) driver for

3-phase motor-drive applications. The device reduces system component count, cost, and complexity by

integrating three half-bridge MOSFETs, gate drivers, charge pump, current sense amplifiers, linear regulator and

buck regulator for external loads. A standard serial peripheral interface (SPI) provides a simple method for

configuring the various device settings and reading fault diagnostic information through an external

microcontroller. Alternatively, a hardware interface (pin) variant allows for configuring the most commonly used

settings through fixed external resistors.

The architecture uses an internal state machine to protect against short-circuit events and dv/dt parasitic turn-on

of the internal power MOSFETs.

The DRV8316C device integrates three, bidirectional current-sense amplifiers for monitoring the current level

through each of the half-bridges using a built-in current sense. The gain setting of the amplifier can be adjusted

through the SPI or hardware interface.

In addition to the high level of device integration, DRV8316C provides a wide range of integrated protection

features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout

(CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck regulator UVLO and

overtemperature warning and shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with

detailed information available in the SPI registers on the SPI variant.

The DRV8316CT and DRV8316CR device are available in 0.5-mm pin pitch, VQFN surface-mount packages.

The VQFN package size is 7 mm × 5 mm.

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8.2 Functional Block Diagram

V_VM

+

C_VM1

C_CP

VM

C_VM2

C_FLY

CPL

CP

CPH

To AVDD and

Buck Regulator

Replace Resistor (R_BK

)

with Inductor (L_BK) for

larger external load

or to reduce power

dissipaꢀon

Charge Pump

Regulators

I/O Control

Ext.

Load

Protection

AVDD

AGND

nSLEEP

V_VM

V_{FB_BK}

/

C_AVDD1

AVDD Linear Regulator

Overcurrent

Protection

DRVOFF

INHA

L_BK

Ext.

Load

SW_BK

Thermal Warning

Thermal Shutdown

C_BK

R_BK

V_VM

GND_BK

Buck Regulator

INLA

FB_BK

Input

INHB

Control

INLB

Predriver Stage

VCP

Power Stage

VM

INHC

HS Pre-

driver

INLC

VDD

OUTA

VLS

R_nFAULT

LS Pre-

driver

Digital Control

Output

Current

Sense for

Phase - A

nFAULT

PGND

ISEN_A

Predriver Stage

VCP

Power Stage

VM

Interface

SCLK

HS Pre-

driver

SPI

OUTB

SDI

Current Limit

AVDD

VLS

SOA

SOB

LS Pre-

driver

SDO

Current

Sense for

Phase - B

AVDD

PGND

SOC

nSCS

+

-

ILIM

ISEN_B

Predriver Stage

VCP

Power Stage

VM

VREF/

ILIM

Current Sense Amplifiers

HS Pre-

driver

C_VREF

ISEN_A

ISEN_B

ISEN_C

A_V

OUTC

SOC

SOB

SOA

VLS

A_V

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

PGND

TPAD

图8-1. DRV8316CR Block Diagram

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V_VM

+

C_VM1

C_CP

VM

C_VM2

C_FLY

CPL

CP

CPH

To AVDD and

Buck Regulator

Replace Resistor (R_BK

)

with Inductor (L_BK) for

larger external load

or to reduce power

dissipaꢀon

Charge Pump

Regulators

I/O Control

Ext.

Load

Protection

AVDD

AGND

nSLEEP

DRVOFF

V_VM

V_{FB_BK}

/

C_AVDD1

AVDD Linear Regulator

Overcurrent

Protection

L_BK

Ext.

Load

SW_BK

Thermal Warning

Thermal Shutdown

C_BK

R_BK

GND_BK

V_VM

INHA

INLA

INHB

INLB

INHC

Buck Regulator

FB_BK

Predriver Stage

VCP

Power Stage

VM

HS Pre-

driver

Input

Control

OUTA

INLC

VLS

LS Pre-

driver

Digital Control

Current

Sense for

Phase - A

MODE

SLEW

PGND

ISEN_A

Predriver Stage

VCP

Power Stage

VM

OCP/SR

GAIN

HS Pre-

driver

VSEL_BK

OUTB

Current Limit

VLS

SOA

SOB

VDD

LS Pre-

driver

R_nFAULT

Current

Sense for

Phase - B

Output

PGND

nFAULT

SOC

+

-

ILIM

ISEN_B

Predriver Stage

VCP

Power Stage

VM

VREF/

ILIM

Current Sense Amplifiers

HS Pre-

driver

C_VREF

ISEN_A

ISEN_B

ISEN_C

A_V

OUTC

SOC

SOB

SOA

VLS

A_V

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

PGND

TPAD

图8-2. DRV8316CT Block Diagram

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8.3 Feature Description

表8-1 lists the recommended values of the external components for the driver.

表8-1. DRV8316C External Components

COMPONENTS

PIN 1

PIN 2

RECOMMENDED

X5R or X7R, 0.1-µF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the device

C_VM1

VM

PGND

≥10-µF, TI recommends a capacitor voltage rating at

least twice the normal operating voltage of the device

C_VM2

C_CP

VM

CP

PGND

VM

X5R or X7R, 16-V, 1-µF

X5R or X7R, 47-nF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage

C_FLY

CPH

CPL

X5R or X7R, 1-µF, ≥6.3-V. In order for AVDD to

accurately regulate output voltage, capacitor should

have effective capacitance between 0.7-µF to 1.3-µF

at 3.3-V across operating temperature.

C_AVDD

AVDD

AGND

C_BK

L_BK

FB_BK

SW_BK

VCC

GND_BK

FB_BK

X5R or X7R, 22-µF, ≥10-V

Output inductor

R_nFAULT

R_MODE

R_SLEW

R_OCP

nFAULT

5.1-kΩ, Pullup resistor

MODE

SLEW

AGND or AVDD

AGND

DRV8316CT hardware interface

X5R or X7R, 0.1-µF, VREF-rated capacitor (Optional)

OCP

R_GAIN

GAIN

R_{VSEL_BK}

C_VREF

VSEL_BK

VREF/ILIM

备注

TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into

internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on

power up or the device will enter internal test mode.

8.3.1 Output Stage

The DRV8316C device consists of an integrated 95-mΩ (combined high-side and low-side FET's on-state

resistance) NMOS FETs connected in a three-phase H-bridge configuration. A doubler charge pump provides

the proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to

providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side

MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the motor-

supply voltage.

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8.3.2 Control Modes

The DRV8316C family of devices provides four different control modes to support various commutation and

control methods. 表8-2 shows the various modes of the DRV8316C device.

表8-2. PWM Control Modes

MODE Pin (Hardware

Variant)

PWM_MODE Bits (SPI

Variant)

VREF/ILIM pin

configuration

MODE

CSA output (SOx)

SOx available

6x Mode

Connected to AGND

Hi-Z

PWM_MODE = 00b

PWM_MODE = 01b

VREF: Reference for CSA

ILIM: Threshold for cycle

by cycle current limit

6x Mode with Current Limit

3x Mode

SOx not available

Connected to AVDD with

R_MODE

PWM_MODE = 10b

PWM_MODE = 11b

VREF: Reference for CSA

SOx available

ILIM: Threshold for cycle

by cycle current limit

3x Mode with Current Limit

Connected to AVDD

SOx not available

备注

Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during

operation of the power MOSFETs. Set all INHx and INLx pins to logic low before changing the MODE

pin or PWM_MODE register.

8.3.2.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The

corresponding INHx and INLx signals control the output state as listed in 表8-3.

表8-3. 6x PWM Mode Truth Table

INLx

INHx

PHASEx

0

1

0

1

0

1

Hi-Z

H

L

Hi-Z

图8-3 shows the application diagram of DRV8316C configured in 6x PWM mode.

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VM

OUTA

nSLEEP

INHA

INLA

INHB

VM

Controller

INLB

INHC

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

MODE

GND

OUTC

GND

图8-3. 6x PWM Mode

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8.3.2.2 3x PWM Mode (PWM_MODE = 10b or MODE Pin is Connected to AVDD with R_MODE

)

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx

pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.

The corresponding INHx and INLx signals control the output state as listed in 表8-4.

表8-4. 3x PWM Mode Truth Table

INLx

INHx

PHASEx

0

1

X

0

1

Hi-Z

L

H

图8-4 shows the application diagram of DRV8316C configured in 3x PWM mode.

VM

OUTA

nSLEEP

INHA

VM

INHB

INHC

Controller

INLA

INLB

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

AVDD

OUTC

R_MODE

GND

图8-4. 3x PWM Mode

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8.3.2.3 Current Limit Mode (PWM_MODE = 01b / 11b or MODE Pin is Hi-Z or Connected to AVDD)

图 8-5 and 图 8-6 show the application diagram of DRV8316C configured in current limit mode. A current limit

comparator is used for the current limiting - comparator input is generated with the three current sense

amplifiers' outputs.

VM

OUTA

nSLEEP

Current

Sense

ISEN_A

INHA

VM

INLA

INHB

Controller

INLB

INHC

OUTB

Gate

Drive

and

Logic

Current

Sense

OCP

BLDC

Motor

ISEN_B

INLC

VM

MODE

Hi-Z

OUTC

Current

Sense

ISEN_C

GND

Current Limit

SOA

SOB

ILIM

SOC

-

+

PWM Current Limit

图8-5. 6x PWM Mode with Current Limit

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VM

OUTA

nSLEEP

Current

Sense

ISEN_A

INHA

INHB

INHC

VM

Controller

INLA

INLB

OUTB

Gate

Drive

and

Logic

Current

Sense

OCP

BLDC

Motor

ISEN_B

INLC

VM

AVDD

MODE

AVDD

OUTC

Current

Sense

ISEN_C

GND

Current Limit

SOA

SOB

ILIM

SOC

-

+

PWM Current Limit

图8-6. 3x PWM Mode with Current Limit

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8.3.3 Device Interface Modes

DRV8316C supports two different interface modes (SPI and hardware) to provide either flexibility or simplicity to

users. The two interface modes share the same pins (except pins 24, 33-36) allowing the different versions to be

largely pin-to-pin compatible. This compatibility allows application designers to evaluate with one interface

variant and switch to another with minimal modifications to their design.

8.3.3.1 Serial Peripheral Interface (SPI)

The SPI variant supports a serial communication bus that allows an external microcontroller to send and receive

data with DRV8316C. This allows the external microcontroller to configure device settings and read detailed fault

information. The SPI interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on

the SDI and SDO pins.

• The SDI pin is the data input.

• The SDO pin is the data output. The SDO pin can be configured to either open-drain or push-pull through

SDO_MODE.

• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

DRV8316C.

For more information on the SPI, see the 节8.5 section.

8.3.3.2 Hardware Interface

Hardware variant uses four resistor-configurable inputs (in the place of SPI pins) which are GAIN, SLEW,

MODE, and OCP.

This variant allows the application designer to configure the critical device settings by tying each pin to logic high

or logic low or leave it floating or pull-up to logic high with a suitable resistor. This eliminates the requirement for

an SPI bus from the external microcontroller to configure DRV8316C. General fault information can still be

obtained through the nFAULT pin.

• The GAIN pin configures the gain of the current sense amplifier.

• The SLEW pin configures the slew rate of the output voltage.

• The MODE pin configures the PWM control mode.

• The OCP/SR pin is used to configures the OCP level and active demagnetization modes.

• The VSEL_BK pin is used to configure the buck regulator voltage.

For more information on the hardware interface, see the 节8.3.10 section.

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AVDD

R_SLEW

AVDD

SLEW

SCLK

AVDD

MODE

SPI

Interface

SDI

AVDD

VCC

Hardware

Interface

R_PU

OCP/SR

GAIN

SDO

AVDD

nSCS

图8-8. DRV8316CT Hardware Interface

图8-7. DRV8316CR SPI Interface

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8.3.4 Step-Down Mixed-Mode Buck Regulator

The DRV8316CR and DRV8316CT have an integrated mixed-mode buck regulator to supply regulated 3.3-V or

5.0-V power for an external controller or system voltage rail. Additionally, the buck output can also be configured

to 4.0-V or 5.7-V for supporting the extra headroom for external LDO for generating a 3.3-V or 5.0-V supplies.

The output voltage of the buck is set by the VSEL_BK pin in the DRV8316CT device (hardware variant) and

BUCK_SEL bits in the DRV8316CR device (SPI variant).

The buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device

improves performance during line and load transients by implementing a pulse-frequency current-mode control

scheme which requires less output capacitance and simplifies frequency compensation design.

To disable the buck regulator, set the BUCK_DIS bit to 1b in DRV8316CR (SPI variant). The buck regulator

cannot be disabled in DRV8316CT (hardware variant).

备注

If the buck regulator is unused, the buck pins SW_BK, GND_BK, and FB_BK cannot be left floating or

connected to ground. The buck regulator components L_BK/R_BKand C_BKmust be connected in

hardware.

表8-5. Recommended settings for Buck Regulator

Buck Mode

Buck output voltage Max output current Max output current Buck current limit

AVDD power

sequencing

from AVDD (I_AVDD

)

from Buck (I_BK)

3.3-V or 4.0-V

5.0-V or 5.7-V

3.3-V or 4.0-V

5.0-V or 5.7-V

3.3-V or 4.0-V

30 mA

200 mA

600 mA (BUCK_CL = Not supported

Inductor - 47 μH

Inductor - 22 μH

Resistor - 22 μH

0b)

(BUCK_PS_DIS = 1)

30 mA

200 mA - I_AVDD

50 mA

600 mA (BUCK_CL = Supported

0b)

(BUCK_PS_DIS = 0)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1)

50 mA - I_AVDD

40 mA

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1)

40 mA - I_AVDD

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0)

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8.3.4.1 Buck in Inductor Mode

The buck regulator in DRV8316C device is primarily designed to support low inductance of 47 µH and 22 µH

inductors. The 47 µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas

the 22 µH inductor limits the load current to 50 mA.

图8-9 shows the connection of buck regulator in inductor mode.

VM

SW_BK

Ext. Load

V_BK

Control

L_BK

C_BK

GND_BK

FB_BK

图8-9. Buck (Inductor Mode)

8.3.4.2 Buck in Resistor mode

If the external load requirements is less than 40 mA, the inductor can be replaced with a resistor. In resistor

mode the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.

图8-10 shows the connection of buck regulator in resistor mode.

VM

SW_BK

Ext. Load

V_BK

Control

R_BK

C_BK

GND_BK

FB_BK

图8-10. Buck (Resistor Mode)

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8.3.4.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to fed to external LDO to generate standard 3.3 V or

5.0 V output rail with higher accuracies. The buck output voltage should be configured to 4 V or 5.5 V to provide

for a extra headroom to support the external LDO for generating 3.3 V or 5 V rail as shown in 图8-11.

This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out

voltage.

VM

V_LDO

(3.3V / 5V)

V_BK

SW_BK

(4V / 5.7V)

V_IN

V_LDO

Ext. Load

C_LDO

Control

L_BK

3.3V / 5V

LDO

C_BK

GND_BK

FB_BK

GND

External LDO

GND

图8-11. Buck Regulator with External LDO

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8.3.4.4 AVDD Power Sequencing on Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce power

dissipation internally. The power sequencing mode allows on-the-fly changeover of LDO power supply from DC

mains (VM) to buck output (VBK) as shown in 图 8-12. This sequencing can be configured through the

BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5.0 V or 5.7 V.

VM

SW_BK

Ext. Load

V_BK

Control

L_BK

C_BK

GND_BK

FB_BK

BUCK_PS_DIS

V_BK

VM

REF

+

–

AVDD

AGND

External Load

C_AVDD

图8-12. AVDD Power Sequencing on mixed mode Buck Regulator

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8.3.4.5 Mixed mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.

The output voltage of the buck regulator is compared with the internal reference voltage (V_{BK_REF}) which is

internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer

voltage control loop. Depending on the comparator output going high (V_BK< V_{BK_REF}) or low (V_BK> V_{BK_REF}),

the high-side power FET of the buck turns on and turna off respectively. An independent current control loop

monitors the current in high-side power FET (I_BK) and turns off the high-side FET when the current becomes

higher than the buck current limit (I_{BK_CL}). This implements a current limit control for the buck regulator. 图 8-13

shows the architecture of the buck and various control/protection loops.

SW_BK

I_BK

Ext. Load

V_BK

VM

L_BK

PWM Control

and Driver

C_BK

GND_BK

I_BK

+

Current Limit

OC Protection

UV Protection

_

I_{BK_CL}

I_BK

+

_

I_{BK_OCP}

FB_BK

V_BK

+

_

V_{BK_UVLO}

VM

V_BK

+

_

Voltage Control

V_{BK_REF}

Buck

Reference

Voltage

BUCK_SEL

Buck Control

Generator

图8-13. Buck Operation and Control Loops

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8.3.5 AVDD Linear Voltage Regulator

A 3.3-V linear regulator is integrated into the DRV8316C family of devices and is available for use by external

circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the device and additionally,

this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting low current

(up to 30 mA). The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-

µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3 V.

FB_BK

BUCK_PS_DIS

V_BK

VM

REF

+

–

AVDD

AGND

External Load

C_AVDD

图8-14. AVDD Linear Regulator Block Diagram

Use 方程式 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply

(BUCK_PS_DIS = 1b)

2 = (8_8/F 8_#8&&) × +_#8&&

(1)

For example, at a V_VMof 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in 方程式2.

P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

(2)

Use 方程式 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as

supply (BUCK_PS_DIS = 0b)

P =

V

− V

× I

AVDD

(3)

FB_BK

AVDD

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8.3.6 Charge Pump

Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM

power supply to enhance the high-side FETs fully. The DRV8316C integrates a charge-pump circuit that

generates a voltage above the VM supply for this purpose.

The charge pump requires two external capacitors for operation. See 图 8-1, 图 8-2, 节 6 and 节 8.3 for details

on these capacitors (value, connection, and so forth).

The charge pump shuts down when nSLEEP is low.

VM

C_CP

CP

CPH

VM

Charge

Pump

Control

C_FLY

CPL

图8-15. DRV8316C Charge Pump

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8.3.7 Slew Rate Control

An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew rate

control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration

of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are

predominantly determined by the rate of gate charge to internal MOSFETs as shown in 图8-16.

VM

VCP (Internal)

Slew Rate

Control

OUTx

VCP (Internal)

Slew Rate

Control

GND

图8-16. Slew Rate Circuit Implementation

The slew rate can be adjusted by the SLEW pin in hardware variant or by using the SLEW bits in SPI variant.

Four slew rate settings are available : 25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the

rise time and fall time of the voltage on OUTx pin as shown in 图8-17.

V_OUTx

VM

80%

20%

0

Time

t_fall

t_rise

图8-17. Slew Rate Timings

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8.3.8 Cross Conduction (Dead Time)

The device is fully protected against any cross conduction of MOSFETs - during the switching of high-side and

low-side MOSFETs, DRV8316C avoids shoot-through events by inserting a dead time (t_dead). This is

implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring

that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side MOSFET of

same half-bridge (or vice-versa) as shown in 图8-18 and 图8-19.

VM

HS Gate

Control

+

VGS_HS

–

OUTx

LS Gate

Control

+

GND

VGS_LS

–

图8-18. Cross Conduction Protection

VGS_HS

10%

t_DEAD

VGS_LS

10%

Time

图8-19. Dead Time

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8.3.9 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to change in gate driver

voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator

delay.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate

drivers. To support multiple control modes, a small digital delay is added as the input command propagates

through the device.

INHx/INLx

INLx : 0

1

OUTx High

OUTx Low

OUTx High

OUTx Low

80%

t_PD

20%

INHx : 0

1

OUTx

Time

图8-20. Propagation Delay

8.3.9.1 Driver Delay Compensation

DRV8316C monitors the propagation delay internally and adds a variable delay on top of it to provide fixed delay

as shown in 图 8-21 and 图 8-22. Delay compensation feature reduces uncertainty caused in timing of current

measurement and also reduces duty cycle distortion caused due to propagation delay.

The fixed delay is summation of propagation delay (t_PD) caused to internal driver delay and variable delay (t_VAR

)

added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer

表8-6 for recommendation on configuration for DLY_TARGET for different slew rate settings.

Delay compensation is only available in SPI variant DRV8316C and can be enabled by configuring DLYCMP_EN

and DLY_TARGET. It is disabled in hardware variant DRV8316C.

INLx

INHx

1V

OUTx

Time

t_VAR

t_PD

t_VAR

t_PD

DLY_TARGET

图8-22. Delay Compensation with current flowing

图8-21. Delay Compensation with current flowing

into the phase

out of phase

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表8-6. Delay Target Recommendation

SLEW RATE

200 V/μs

125 V/μs

50 V/μs

DLY_TARGET

DLY_TARGET = 0x5 (1.2 μs)

DLY_TARGET = 0x8 (1.8 μs)

DLY_TARGET = 0xB (2.4 μs)

DLY_TARGET = 0xF (3.2 μs)

25 V/μs

8.3.10 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

8.3.10.1 Logic Level Input Pin (Internal Pulldown)

图 8-23 shows the input structure for the logic level pins, DRVOFF, INHx, INLx, nSLEEP, SCLK and SDI. The

input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep mode to

reduce leakage current through internal pull-down resistors.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

Logic High

Logic Low

V_IL

R_PD

ESD

图8-23. Logic-Level Input Pin Structure

8.3.10.2 Logic Level Input Pin (Internal Pullup)

图8-24 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or external

resistor.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

R_PU

Logic High

Logic Low

V_IL

ESD

图8-24. Logic nSCC

8.3.10.3 Open Drain Pin

图 8-25 shows the structure of the open-drain output pin, nFAULT and SDO in open drain mode. The open-drain

output requires an external pullup resistor to function properly.

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AVDD

STATE

No Fault

Fault

STATUS

Pulled-Up

R_PU

OUTPUT

Inactive

Active

Pulled-Down

ESD

图8-25. Open Drain

8.3.10.4 Push Pull Pin

图8-26 shows the structure of SDO in push-pull mode.

AVDD

STATE

V_OH

STATUS

Pulled-Up

OUTPUT

V_OL

Pulled-Down

ESD

Logic High

Logic Low

图8-26. Push Pull

8.3.10.5 Four Level Input Pin

图 8-27 shows the structure of the four level input pins, GAIN, MODE, SLEW, OCP/SR and VSEL_BK on

hardware interface devices. The input can be set with an external resistor.

CONTROL

AVDD

STATE

V_L1

RESISTANCE

Tied to AGND

Setting-1

Setting-2

Setting-3

Setting-4

+

R_PU

œ

Hi-Z (>2000 kΩ to

AGND)

V_L2

V_L3

V_L4

+

R_PD

47 kΩ ±5%

to AVDD

œ

Tied to AVDD

+

œ

图8-27. Four Level Input Pin Structure

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8.3.11 Current Sense Amplifiers

The DRV8316C integrates three, high-performance low-side current sense amplifiers for current measurements

using built-in current sensing. Low-side current measurements are commonly used to implement overcurrent

protection, external torque control, or brushless-DC commutation with an external controller. The three amplifiers

can be used to sense the current in each of the half-bridge legs (when the low-side FET of the corresponding

phase is conducting current). The current sense amplifiers include features such as programmable gain and

external reference (which is provided on the voltage reference pin, VREF).

8.3.11.1 Current Sense Amplifier Operation

The SOx pin on the DRV8316C outputs an analog voltage proportional to current flowing in the low side FETs

multiplied by the gain setting (G_CSA). The gain setting is adjustable between four different levels which can be

set by the GAIN pin (in hardware device variant) or the GAIN bits (in SPI device variant).

图 8-28 shows the internal architecture of the current sense amplifiers. The current sense is implemented with

the sense FET on each low-side FET of the DRV8316C device. This current information is fed to the internal I/V

converter, which generates the CSA output voltage on the SOX pin based on the voltage on VREF pin and the

Gain setting. The CSA output voltage can be calculated as :

8

^4'(W

51: = @

A ± )#+0 × +_176:

2

(4)

VM

VREF

OUTX

Sense

FET

GAIN

I/V Converter

PGND

SOX

图8-28. Integrated Current Sense Amplifier

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图 8-29 and 图 8-30 show the detail of the amplifier operational range. In bi-directional operation, the amplifier

output for 0-V input is set at VREF / 2. Any change in the differential input results in a corresponding change in

the output times the CSA_GAIN factor. The amplifier has a defined region in which it can maintain a linear

operation.

SOX

V_REF

(V_REF– 0.25) V

I_OUTx

V

SOX(range+)

V

SOX(off)max

V_REF/2

V

, V

OFF DRIFT

0-A

V

SOX(off)min

V

SOX(range-)

-I_OUTx

0.25-V

0-V

图8-29. Bi-directional Current Sense Linear Region

SOX (V)

V_REF

(V_REF- 0.25)

V_REF/ 2

V_LINEAR

0.25-V

0-V

I_OUTx(A) (Current flowing out of OUTx)

图8-30. IOUTx to CSA Transfer Function

备注

The current sense amplifier supports only capacitive load at output. TI recommends connecting low

pass filter with resistor and capacitor on output of current sense amplifier.

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8.3.12 Active Demagnetization

DRV8316C family of devices has smart rectification features (active demagnetization) which decreases power

losses in the device by reducing diode conduction losses. When this feature is enabled, the device automatically

turns ON the corresponding MOSFET whenever it detects diode conduction. This feature can be configured with

the OCP/SR pins in hardware variants. In SPI device variants this can be configured through EN_ASR and

EN_AAR bits. The smart rectification is classified into two categories of automatic synchronous rectification

(ASR) mode and automatic asynchronous rectification (AAR) mode which are described in sections below.

备注

In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active

demagnetization.

The DRV8316C device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the

negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET

output with the supply voltage (VM) threshold, whereas the AD_LS comparator compares with the ground (0-V)

threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS

comparator trips. This comparator provides a reference point for the operation of active demagnetization feature.

VM

AD_HS

Comparator

+

-

Sense

FET

(To Digital)

OUTX

VM

+

-

Sense

FET

AD_LS

Comparator

0V (GND)

PGND

VREF

I/V Converter

SOX

GAIN

图8-31. Active Demagnetization Operation

表8-7 shows the configuration of ASR and AAR mode in the DRV8316C device.

表8-7. OCP/SR Configuration

MODE Type

OCP/SR Pin (DRV8316CT)

SR Bits (DRV8316CR)

OCP Setting

ASR and AAR Mode

Mode 1

Connected to AGND

EN_ASR = 0, EN_AAR = 0

16 A

ASR and AAR Disabled

Connected to AGND with

R_MODE1

Mode 2

EN_ASR = 0, EN_AAR = 0

24 A

ASR and AAR Disabled

Mode 3

Mode 4

Hi-Z

EN_ASR = 1, EN_AAR = 1

16 A

24 A

ASR and AAR Enabled

Connected to AVDD

8.3.12.1 Automatic Synchronous Rectification Mode (ASR Mode)

The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation

and ASR during PWM mode.

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8.3.12.1.1 Automatic Synchronous Rectification in Commutation

图 8-32 shows the operation of active demagnetization during the BLDC motor commutation. As shown in 图

8-32 (a), the current is flowing from HA to LC in one commutation state. During the commutation changeover as

shown in 图 8-32 (b), the HC switch is turned on, whereas the commutation current (due to motor inductance) in

OUTA flows through the body diode of LA. This incorporates a higher diode loss depending on the commutation

current. This commutation loss is reduced by turning on the LA for the commutation time as shown in 图8-32 (c).

Similarly the operation of high-side FET is realized in 图8-32 (d), (e) and (f).

VM

HB

HC

HA

HB

HC

HA

OUTA

OUTB

OUTC

LA

LB

LC

LA

LB

LC

(a) Current flowing from HA to LC

VM

(d) Current flowing from HC to LA

VM

Decay Current

HB

HC

HB

OUTA

LB

HC

HA

OUTA

OUTB

LA

LB

LC

LA

LC

(e) Decay current with AD disabled

VM

(b) Decay current with AD disabled

VM

Decay Current

HB

HC

HB

OUTA

LB

HC

HA

OUTA

OUTB

LA

LB

LC

LA

LC

(c) Decay current with AD enabled

(f) Decay current with AD enabled

图8-32. ASR in BLDC Motor Commutation

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图 8-33 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode in

BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a

single commutation cycle.

图 8-33 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with margin

time (t_margin) and ASR mode early stop due to active demag. comparator threshold and delays.

Current Limit

Phase ”A‘

Current

LA

HA

HA, LB

HB, LC

HB, LA

HC, LA

HC, LB

HA, LC

(a) Commutation current of Phase —A“

t_margin

t_dead

HA Conducts

LA Body Diode

Conducts

HA Body Diode

Conducts

Phase ”A‘

Current

LA Conducts

t_dead

HC, LA

HC, LB

HA, LC

HB, LC

(b) Zoomed waveform of Active Demagnetization

图8-33. Current Waveforms for ASR in BLDC Motor Commutation

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8.3.12.1.2 Automatic Synchronous Rectification in PWM Mode

图 8-34 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on the high-

side FET, whereas the low-side FET is always off. During the PWM off time, current decays from the low-side

FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET during the

low-side diode conduction.

PWM_HS

(Applied)

&t

PWM_LS

(Applied)

&t

PWM_HS

(Actual)

&t

PWM_LS

(Actual)

&t

I_a

&t

ASR Mode Disabled

ASR Mode Enabled

图8-34. ASR in PWM Mode

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8.3.12.2 Automatic Asynchronous Rectification Mode (AAR Mode)

图 8-35 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a synchronous

rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower inductance

motors, the current can decay to zero and becomes negative since low side FET is in on-state. This creates a

negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the decay is

monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves the

negative current building in the BLDC motor which results in better noise performance and better thermal

management.

PWM_HS

(Applied)

&t

PWM_LS

(Applied)

&t

PWM_HS

(Actual)

&t

PWM_LS

(Actual)

&t

I_a

&t

AAR Mode Disabled

AAR Mode Enabled

图8-35. AAR in PWM Mode

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8.3.13 Cycle-by-Cycle Current Limit

The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the I_LIMITcurrent.

This feature restricts motor current to less than the I_LIMIT

.

The current-limit circuitry utilizes the current sense amplifier output of the three phases compared with the

voltage at ILIM pin. 图8-36 shows the implementation of current limit circuitry. As shown in this figure, the output

of current sense amplifiers is combined with star connected resistive network. This measured voltage V_MEASis

compared with the external reference voltage e V_ILIMpin to realize the current limit implementation. The relation

between current sensed on OUTX pin and V_MEASthreshold is given as:

8

^#8&&W

: ;

¤

A F k +_176#+ +_176$+ +_176%× )#+0 3o

8_/'#5= @

2

(5)

where

• AVDD is 3.3-V LDO output

• OUTX is current flowing into the low-side MOSFET

• GAIN is the CSA_GAIN setting

The I_LIMITthreshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.4) V. AVDD/2 is

minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum

threshold of 8 A can be configured by applying (AVDD/2 - 0.4) V on ILIM pin.

VM

AVDD

I/V Converter

SOA

OUTA

Sense

FET

GAIN

PGND

SOB

To PWM

V_MEAS

V_ILIM

Controller

-

+

ILIM

SOC

图8-36. Current Limit Implementation

When then the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle as

shown in 图8-37. The low-side FETs can operate in brake mode or high-Z mode by configuring the ILIM_RECIR

bit in the SPI device variant.

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PWM

OUTx

I_LIMIT

Bridge Operating in

Brake Mode

I_BRIDGE

Time

图8-37. Cycle-by-Cycle Current-Limit Operation

图 8-38 shows the operation of driver in brake mode, where the current recirculates through low-side FETs while

the high-side FETs are disabled.

图8-39 shows the operation of driver in hi-Z mode, where the current recirculates through the body diodes of the

low-side FETs while the high-side FETs are disabled.

VM

HB

HC

HA

HB

HC

HA

X

OUTA

OUTB

OUTC

LA

LB

LC

LA

LB LC

X X X

图8-38. Brake State

图8-39. Coast State

备注

The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking

time to prevent false trips of the current-limit circuit.

备注

During the brake operation, a high-current can flow through the low-side FETs which can eventually

trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct

and pump brake energy to the VM supply rail.

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8.3.13.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input

In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To

overcome this problem, DRV8316C has built in internal PWM clock which is used to turn high-side FET back on

once it is disabled after exceeding I_LIMITthreshold. In SPI variant DRV8316C, this internal PWM clock can be

configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant DRV8316C PWM internal

clock is set to 20 kHz. 图8-40 shows operation with 100 % duty cycle.

PWM

Internal

PWM

OUTx

ILIMIT

Bridge Operating in

Brake Mode

Time

图8-40. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle

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8.3.14 Protections

The DRV8316C family of devices is protected against VM undervoltage, charge pump undervoltage, and

overcurrent events. 表8-8 summarizes various faults details.

表8-8. Fault Action and Response (SPI Devices)

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

Automatic:

V_VM> V_{UVLO_R}

CLR_FLT, nSLEEP Reset Pulse (NPOR

bit)

VM undervoltage

(NPOR)

V_VM< V_UVLO

Hi-Z

Disabled

—

Automatic:

V_AVDD> V_{AVDD_UV_R}

CLR_FLT, nSLEEP Reset Pulse (NPOR

bit)

AVDD undervoltage

(NPOR)

V_AVDD< V_{AVDD_UV}

V_{FB_BK}< V_{BK_UV}

V_CP< V_CPUV

Hi-Z

Active

Hi-Z

Disabled

Active

—

Automatic:

V_{FB_BK}> V_{BUCK_UV_R}

CLR_FLT, nSLEEP Reset Pulse

(BUCK_UV bit)

Buck undervoltage

(BUCK_UV)

nFAULT

Automatic:

V_VCP> V_CPUV

CLR_FLT, nSLEEP Reset Pulse

(VCP_UV bit)

Charge pump

undervoltage

(VCP_UV)

Active

OVP_EN = 0b

OVP_EN = 1b

None

Active

Hi-Z

Active

No action (OVP Disabled)

OverVoltage

Protection

(OVP)

Automatic:

V_VM< V_OVP

CLR_FLT, nSLEEP Reset Pulse (OVP bit)

V_VM> V_OVP

FAULT

Latched:

CLR_FLT, nSLEEP Reset Pulse (OCP

bits)

OCP_MODE = 00b

OCP_MODE = 01b

nFAULT

Hi-Z

Active

Retry:

t_RETRY

Overcurrent

Protection

(OCP)

I_PHASE> I_OCP

Automatic:

CLR_FLT, nSLEEP Reset Pulse (OCP

bits)

OCP_MODE = 10b

OCP_MODE = 11b

—

nFAULT

None

Active

No action

Buck Overcurrent

Protection

(BUCK_OCP)

Retry:

t_RETRY

I_BK> I_{BK_OC}

nFAULT

Automatic:

CLR_FLT, nSLEEP Reset Pulse

(SPI_FLT bit)

SPI_FLT_REP = 0b

SPI_FLT_REP = 1b

nFAULT

Active

SPI Error

(SPI_FLT)

SCLK fault and ADDR

fault

None

nFAULT

None

Active

Hi-Z

Active

No action

OTP Error

(OTP_ERR)

Latched:

OTP reading is erroneous

T_J> T_OTW

—

Power Cycle, nSLEEP Reset Pulse

OTW_REP = 0b

Active

No action

Thermal warning

(OTW)

Automatic:

T_J< T_OTW–T_{OTW_HYS}

CLR_FLT, nSLEEP Pulse (OTW bit)

OTW_REP = 1b

nFAULT

Active

Hi-Z

Active

Automatic:

T_J< T_TSD–T_{TSD_HYS}

Thermal shutdown

(OTSD)

T_J> T_TSD

—

Automatic:

T_J< T_{TSD_FET}–T_{TSD_FET_HYS}

CLR_FLT, nSLEEP Pulse (OTS bit)

Thermal shutdown

(OTSD_FET)

T_J> T_{TSD_FET}

Hi-Z

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8.3.14.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the V_UVLOthreshold (VM UVLO falling

threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in 图

8-41. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The NPOR

bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR bit

remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST).

V_UVLO(max) rising

V_UVLO(min) rising

V_UVLO(max) falling

V_UVLO(min) falling

V_VM

DEVICE ON

DEVICE OFF

DEVICE ON

Time

图8-41. VM Supply Undervoltage Lockout

8.3.14.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the V_{AVDD_UV}threshold, all of the integrated FETs, driver

charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the

AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)

register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the

CLR_FLT bit or an nSLEEP pin reset pulse (t_RST).

8.3.14.3 BUCK Undervoltage Lockout (BUCK_UV)

If at any time the voltage on VFB_BK pin falls lower than the V_{BK_UV}threshold, the integrated FETs of the buck

regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally.

The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register

is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices.

Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK

undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or

an nSLEEP pin reset pulse (t_RST).

8.3.14.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the V_CPUVthreshold voltage of the

charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV

bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the

nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared

through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST). The CPUV protection is always enabled in both

hardware and SPI device varaints.

8.3.14.5 Overvoltage Protection (OVP)

If at any time input supply voltage on the VM pins rises higher lower than the V_OVPthreshold voltage, all of the

integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high

in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)

when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin

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reset pulse (t_RST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. The OVP

threshold is programmable on the SPI variant and can be set to 22-V or 34-V based on the OVP_SEL bit. In

hardware variant, the OVP protection is always enabled and set to a 34-V threshold.

V_VM

V_OVP(max) rising

V_OVP(min) rising

V_OVP(max) falling

V_OVP(min) falling

DEVICE ON

DEVICE OFF

DEVICE ON

nFAULT

Time

图8-42. Over Voltage Protection

8.3.14.6 Overcurrent Protection (OCP)

A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a

FET exceeds the I_OCPthreshold for longer than the t_OCPdeglitch time, an OCP event is recognized and action is

done according to the OCP_MODE bit. On hardware interface devices, the I_OCPthreshold is set via OCP/SR pin,

the t_{OCP_DEG}is fixed at 0.6-µs, and the OCP_MODE bit is configured for latched shutdown. On SPI devices, the

I_OCPthreshold is set through the OCP_LVL SPI register, the t_{OCP_DEG}is set through the OCP_DEG SPI register,

and the OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP automatic retry, OCP

report only, and OCP disabled.

8.3.14.6.1 OCP Latched Shutdown (OCP_MODE = 00b)

After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,

and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver

operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued

either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

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Peak Current due

to deglitch time

I_OCP

I_OUTx

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Clear Fault

Time

图8-43. Overcurrent Protection - Latched Shutdown Mode

8.3.14.6.2 OCP Automatic Retry (OCP_MODE = 01b)

After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,

and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again

automatically (driver operation and the nFAULT pin is released) after the t_RETRYtime elapses. After the t_RETRY

time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is

issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_RETRY

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Time

图8-44. Overcurrent Protection - Automatic Retry Mode

8.3.14.6.3 OCP Report Only (OCP_MODE = 10b)

No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the

nFAULT pin low and latching the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. The

DRV8316C continues to operate as usual. The external controller manages the overcurrent condition by acting

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appropriately. The reporting clears (nFAULT pin is released) when the OCP condition clears and a clear faults

command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

8.3.14.6.4 OCP Disabled (OCP_MODE = 11b)

No action occurs after a OCP event in this mode.

8.3.14.7 Buck Overcurrent Protection

A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the

current across the buck regulator FET exceeds the I_{BK_OCP}threshold for longer than the t_{BK_OCP}deglitch time,

an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after a

buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low. The

FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again

automatically (driver operation and the nFAULT pin is released) after the t_{BK_RETRY}time elapses. The FAULT,

BK_FLT, and BUCK_OCP bits stay latched until the t_RETRYperiod expires.

8.3.14.8 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OT bit in the IC status (IC_STAT)

register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by

setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device

performs no additional action and continues to function. In this case, the nFAULT pin releases when the die

temperature decreases below the hysteresis point of the thermal warning (T_{OTW_HYS}). The OTW bit remains set

until cleared through the CLR_FLT bit or an nSLEEP reset pulse (t_RST) and the die temperature is lower than

thermal warning trip (T_OTW).

备注

Over temperature warning is not reported on nFAULT pin by default.

8.3.14.9 Thermal Shutdown (OTS)

DRV8316C has 2 die temperature sensor for thermal shutdown, one of them near FETs and other one in other

part of die.

8.3.14.9.1 OTS FET

If the die temperature near FET exceeds the trip point of the thermal shutdown limit (T_{TSD_FET}), all the FETs are

disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in

the IC status (IC_STAT) register and OTS bit in the status register is set. Normal operation starts again (driver

operation and the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays

latched high indicating that a thermal event occurred until a clear fault command is issued either through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST). This protection feature cannot be disabled.

8.3.14.9.2 OTS (Non FET)

If the die temperature in the device exceeds the trip point of the thermal shutdown limit (T_TSD), all the FETs are

disabled, the buck regulator disabled, the charge pump is shut down, and the nFAULT pin is driven low. In

addition, the FAULT and OT bit in the IC status (IC_STAT) register and OTS bit in the status register is set.

Normal operation starts again (driver operation and the nFAULT pin is released) when the overtemperature

condition clears. The OTS bit stays latched high indicating that a thermal event occurred until a clear fault

command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST). This protection feature

cannot be disabled.

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8.4 Device Functional Modes

8.4.1 Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of the DRV8316C family of devices. When the nSLEEP pin is low, the

device goes to a low-power sleep mode. In sleep mode, all FETs are disabled, current sense amplifiers are

disabled, buck regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled,

and the SPI bus is disabled. The t_SLEEPtime must elapse after a falling edge on the nSLEEP pin before the

device goes to sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high.

The t_WAKEtime must elapse before the device is ready for inputs.

In sleep mode and when V_VM< V_UVLO, all MOSFETs are disabled.

备注

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low

as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the

t_SLEEPor t_WAKEtime.

备注

TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into

internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2 V on

power up or the device will enter internal test mode.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the V_VMvoltage is greater than the V_UVLOvoltage, the device goes to

operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the charge

pump, AVDD regulator, buck regulator, and SPI bus are active.

8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)

In the case of device latched faults, the DRV8316C family of devices goes to a partial shutdown state to help

protect the power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT bit

to 1b in the SPI variant or issuing a reset pulse to the nSLEEP pin on either variant. The nSLEEP reset pulse

(t_RST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should fall

within the t_RSTtime window or else the device will start the complete shutdown sequence (low power sleep

mode). The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.

8.4.2 DRVOFF functionality

DRV8316C has capability to disable predriver and MOSFETs bypassing the digital through DRVOFF pin. When

DRVOFF pin is pulled high, all six MOSFETs are disabled. If nSLEEP is high when the DRVOFF pin is high, the

charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults such as OCP

will be inactive. DRVOFF pin independently disables MOSFETs which will stop motor commutation irrespective

of status of INHx and INLx input pins.

备注

Since DRVOFF pin independently disables MOSFET, it can trigger fault condition resulting in nFAULT

getting pulled low.

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8.5 SPI Communication

8.5.1 Programming

On DRV8316C SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out

diagnostic information. The SPI operates in secondary mode and connects to a controller. The SPI input data

(SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit

word, with a 8 bits of status information (STAT register) and 8-bit register data.

A valid frame must meet the following conditions:

• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

• The nSCS pin should be pulled high for at least 400 ns between words.

• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is

placed in the Hi-Z state.

• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK

pin.

• The most significant bit (MSB) is shifted in and out first.

• A full 16 SCLK cycles must occur for transaction to be valid.

• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word

is ignored.

• For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 8-bit status data.

The SPI registers are reset to the default settings on power up and when the device is enters sleep mode

8.5.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

• 1 read or write bit, W (bit B15)

• 6 address bits, A (bits B14 through B9)

• Parity bit, P (bit B8). Parity bit is set such that the SDI input data word has even number of 1s and 0s

• 8 data bits, D (bits B7 through B0)

The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the

register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read.

nSCS

A1

S1

D1

R1

SDI

SDO

图8-45.

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Master Controller

Device

MCLK

MO

MI

SCLK

SDI

SPI

Communication

SDO

SPI

Communication

nSCS

CS

图8-46.

表8-9. SDI Input Data Word Format

R/W

ADDRESS

Parity

DATA

B15

W0

B14

A5

B13

A4

B12

A3

B11

A2

B10

A1

B9

A0

B8

P

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

表8-10. SDO Output Data Word Format

STATUS

DATA

B15

S7

B14

S6

B13

S5

B12

S4

B11

S3

B10

S2

B9

S1

B8

S0

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

nSCS

SCLK

SDI

X

Z

MSB

LSB

X

Z

SDO

Capture

Point

Propagate

Point

图8-47. SPI Secondary Timing Diagram

SPI Error Handling

SPI Frame Error (SPI_SCLK_FLT: If the nSCS gets deasserted before the end of 16-bit frame, SPI frame error

is detected and SPI_SCLK_FLT bit is set in STAT2. The SPI_SCLK_FLT status bit is latched and can be cleared

when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse

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SPI Address Error (SPI_ADDR_FLT): If an invalid address is provided in the ADDR field of the input SPI data

on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any address

that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC. The

SPI_ADDR_FLT status bit is latched and can be cleared when a clear faults command is issued either through

the CLR_FLT bit or an nSLEEP reset pulse

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8.6 Register Map

8.6.1 STATUS Registers

表8-11 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in 表

8-11 should be considered as reserved locations and the register contents should not be modified.

表8-11. STATUS Registers

Offset Acronym

Register Name

IC Status Register

Status Register 1

Status Register 2

Section

节8.6.1.1

节8.6.1.2

节8.6.1.3

0h

1h

2h

IC Status Register

Status Register 1

Status Register 2

Complex bit access types are encoded to fit into small table cells. 表 8-12 shows the codes that are used for

access types in this section.

表8-12. STATUS Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Reset or Default Value

-n

Value after reset or the default

value

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8.6.1.1 IC Status Register (Offset = 0h) [Reset = 00h]

IC Status Register is shown in 图8-48 and described in 表8-13.

Return to the 表8-11.

图8-48. IC Status Register

7

6

5

4

3

2

1

0

BK_FLT

R-0h

SPI_FLT

R-0h

OCP

R-0h

NPOR

R-0h

OVP

R-0h

OT

FAULT

R-0h

表8-13. IC Status Register Field Descriptions

Bit

Field

Type

Reset

Description

6

5

4

3

2

1

0

BK_FLT

SPI_FLT

OCP

R

0h

Buck Fault Bit

0h = No buck regulator fault condition is detected

1h = Buck regulator fault condition is detected

R

0h

SPI Fault Bit

0h = No SPI fault condition is detected

1h = SPI Fault condition is detected

Over Current Protection Status Bit

0h = No overcurrent condition is detected

1h = Overcurrent condition is detected

NPOR

OVP

Supply Power On Reset Bit

0h = Power on reset condition is detected on VM

1h = No power-on-reset condition is detected on VM

Supply Overvoltage Protection Status Bit

0h = No overvoltage condition is detected on VM

1h = Overvoltage condition is detected on VM

OT

Overtemperature Fault Status Bit

0h = No overtemperature warning / shutdown is detected

1h = Overtemperature warning / shutdown is detected

FAULT

Device Fault Bit

0h = No fault condition is detected

1h = Fault condition is detected

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8.6.1.2 Status Register 1 (Offset = 1h) [Reset = 00h]

Status Register 1 is shown in 图8-49 and described in 表8-14.

Return to the 表8-11.

图8-49. Status Register 1

7

6

5

4

3

2

1

0

OTW

R-0h

OTS

R-0h

OCP_HC

R-0h

OCL_LC

R-0h

OCP_HB

R-0h

OCP_LB

R-0h

OCP_HA

R-0h

OCP_LA

R-0h

表8-14. Status Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

7

OTW

R

0h

Overtemperature Warning Status Bit

0h = No overtemperature warning is detected

1h = Overtemperature warning is detected

6

5

4

3

2

1

0

OTS

R

0h

Overtemperature Shutdown Status Bit

0h = No overtemperature shutdown is detected

1h = Overtemperature shutdown is detected

OCP_HC

OCL_LC

OCP_HB

OCP_LB

OCP_HA

OCP_LA

Overcurrent Status on High-side switch of OUTC

0h = No overcurrent detected on high-side switch of OUTC

1h = Overcurrent detected on high-side switch of OUTC

Overcurrent Status on Low-side switch of OUTC

0h = No overcurrent detected on low-side switch of OUTC

1h = Overcurrent detected on low-side switch of OUTC

Overcurrent Status on High-side switch of OUTB

0h = No overcurrent detected on high-side switch of OUTB

1h = Overcurrent detected on high-side switch of OUTB

Overcurrent Status on Low-side switch of OUTB

0h = No overcurrent detected on low-side switch of OUTB

1h = Overcurrent detected on low-side switch of OUTB

Overcurrent Status on High-side switch of OUTA

0h = No overcurrent detected on high-side switch of OUTA

1h = Overcurrent detected on high-side switch of OUTA

Overcurrent Status on Low-side switch of OUTA

0h = No overcurrent detected on low-side switch of OUTA

1h = Overcurrent detected on low-side switch of OUTA

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8.6.1.3 Status Register 2 (Offset = 2h) [Reset = 00h]

Status Register 2 is shown in 图8-50 and described in 表8-15.

Return to the 表8-11.

图8-50. Status Register 2

7

6

5

4

3

2

1

0

RESERVED

OTP_ERR

BUCK_OCP

BUCK_UV

VCP_UV

SPI_PARITY SPI_SCLK_FLT SPI_ADDR_FL

T

R-0-0h

R-0h

R-0-0h

R-0h

表8-15. Status Register 2 Field Descriptions

Bit

7

Field

RESERVED

Type

R-0

R

Reset

Description

0h

Reserved

6

OTP_ERR

0h

One Time Programmabilty Error

0h = No OTP error is detected

1h = OTP Error is detected

5

4

3

2

1

0

BUCK_OCP

BUCK_UV

R

0h

Buck Regulator Overcurrent Staus Bit

0h = No buck regulator overcurrent is detected

1h = Buck regulator overcurrent is detected

R

Buck Regulator Undervoltage Staus Bit

0h = No buck regulator undervoltage is detected

1h = Buck regulator undervoltage is detected

VCP_UV

R

Charge Pump Undervoltage Status Bit

0h = No charge pump undervoltage is detected

1h = Charge pump undervoltage is detected

SPI_PARITY

SPI_SCLK_FLT

SPI_ADDR_FLT

R-0

R

SPI Parity Error Bit

0h = No SPI parity error is detected

1h = SPI parity error is detected

SPI Clock Framing Error Bit

0h = No SPI clock framing error is detected

1h = SPI clock framing error is detected

R

SPI Address Error Bit

0h = No SPI address fault is detected (due to accessing non-user

register)

1h = SPI address fault is detected

8.6.2 CONTROL Registers

表 8-16 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in

表8-16 should be considered as reserved locations and the register contents should not be modified.

表8-16. CONTROL Registers

Offset Acronym

Register Name

Section

节8.6.2.1

节8.6.2.2

节8.6.2.3

节8.6.2.4

节8.6.2.5

节8.6.2.6

节8.6.2.7

3h

4h

5h

6h

7h

8h

Ch

Control Register 1

Control Register 2

Control Register 3

Control Register 4

Control Register 5

Control Register 6

Control Register 10

Control Register 2

Control Register 3

Control Register 4

Control Register 5

Control Register 6

Control Register 10

Complex bit access types are encoded to fit into small table cells. 表 8-17 shows the codes that are used for

access types in this section.

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表8-17. CONTROL Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Write Type

W

Write

W1C

W

Write

1C

1 to clear

WAPU

W

Write

APU

Atomic write with password

unlock

Reset or Default Value

-n

Value after reset or the default

value

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8.6.2.1 Control Register 1 (Offset = 3h) [Reset = 00h]

Control Register 1 is shown in 图8-51 and described in 表8-18.

Return to the 表8-16.

图8-51. Control Register 1

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

REG_LOCK

R/WAPU-0h

表8-18. Control Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2-0

RESERVED

REG_LOCK

R-0

0h

Reserved

R/WAPU

0h

Register Lock Bits

0h = No effect unless locked or unlocked

1h = No effect unless locked or unlocked

2h = No effect unless locked or unlocked

3h = Write 011b to this register to unlock all registers

4h = No effect unless locked or unlocked

5h = No effect unless locked or unlocked

6h = Write 110b to lock the settings by ignoring further register writes

except to these bits and address 0x03h bits 2-0.

7h = No effect unless locked or unlocked

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8.6.2.2 Control Register 2 (Offset = 4h) [Reset = 60h]

Control Register 2 is shown in 图8-52 and described in 表8-19.

Return to the 表8-16.

图8-52. Control Register 2

7

6

5

4

3

2

1

0

RESERVED

R/W-1h

SDO_MODE

R/W-1h

SLEW

PWM_MODE

R/W-0h

CLR_FLT

W1C-0h

R/W-0h

表8-19. Control Register 2 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

RESERVED

SDO_MODE

1h

Reserved

1h

SDO Mode Setting

0h = SDO IO in Open Drain Mode

1h = SDO IO in Push Pull Mode

4-3

2-1

0

SLEW

R/W

W1C

0h

Slew Rate Settings

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 125 V/µs

3h = Slew rate is 200 V/µs

PWM_MODE

CLR_FLT

Device Mode Selection

0h = 6x mode

1h = 6x mode with current limit

2h = 3x mode

3h = 3x mode with current limit

Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after

being written.

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8.6.2.3 Control Register 3 (Offset = 5h) [Reset = 46h]

Control Register 3 is shown in 图8-53 and described in 表8-20.

Return to the 表8-16.

图8-53. Control Register 3

7

6

5

4

3

2

1

0

RESERVED

PWM_100_DU

TY_SEL

OVP_SEL

OVP_EN

SPI_FLT_REP

OTW_REP

R-0-0h

R/W-1h

R/W-0h

R/W-1h

R/W-0h

表8-20. Control Register 3 Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R-0

0h

6

RESERVED

R/W

1h

5

RESERVED

0h

4

PWM_100_DUTY_SEL

0h

Freqency of PWM at 100% Duty Cycle

0h = 20KHz

1h = 40KHz

3

2

1

0

OVP_SEL

OVP_EN

R/W

0h

1h

0h

Overvoltage Level Setting

0h = VM overvoltage level is 34-V

1h = VM overvoltage level is 22-V

Overvoltage Enable Bit

0h = Overvoltage protection is disabled

1h = Overvoltage protection is enabled

SPI_FLT_REP

OTW_REP

SPI Fault Reporting Disable Bit

0h = SPI fault reporting on nFAULT pin is enabled

1h = SPI fault reporting on nFAULT pin is disabled

Overtemperature Warning Reporting Bit

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

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8.6.2.4 Control Register 4 (Offset = 6h) [Reset = 10h]

Control Register 4 is shown in 图8-54 and described in 表8-21.

Return to the 表8-16.

图8-54. Control Register 4

7

6

5

4

3

2

1

0

DRV_OFF

R/W-0h

OCP_CBC

R/W-0h

OCP_DEG

R/W-1h

OCP_RETRY

R/W-0h

OCP_LVL

R/W-0h

OCP_MODE

R/W-0h

表8-21. Control Register 4 Field Descriptions

Bit

Field

Type

Reset

Description

7

DRV_OFF

OCP_CBC

OCP_DEG

R/W

0h

Driver OFF Bit

0h = No Action

1h = Hi-Z FETs

6

R/W

0h

1h

OCP PWM Cycle Operation Bit

0h = OCP clearing in PWM input cycle change is disabled

1h = OCP clearing in PWM input cycle change is enabled

5-4

OCP Deglitch Time Settings

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.6 µs

2h = OCP deglitch time is 1.25 µs

3h = OCP deglitch time is 1.6 µs

3

2

OCP_RETRY

OCP_LVL

R/W

0h

OCP Retry Time Settings

0h = OCP retry time is 5 ms

1h = OCP retry time is 500 ms

Overcurrent Level Setting

0h = OCP level is 16 A

1h = OCP level is 24 A

1-0

OCP_MODE

OCP Fault Options

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

66

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8.6.2.5 Control Register 5 (Offset = 7h) [Reset = 00h]

Control Register 5 is shown in 图8-55 and described in 表8-22.

Return to the 表8-16.

图8-55. Control Register 5

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

ILIM_RECIR

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

EN_AAR

R/W-0h

EN_ASR

R/W-0h

CSA_GAIN

R/W-0h

表8-22. Control Register 5 Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0h

Reserved

6

ILIM_RECIR

0h

Current Limit Recirculation Settings

0h = Current recirculation through FETs (Brake Mode)

1h = Current recirculation through diodes (Coast Mode)

5

4

3

RESERVED

EN_AAR

R/W

0h

Reserved

Active Asynshronous Rectification Enable Bit

0h = AAR mode is disabled

1h = AAR mode is enabled

2

EN_ASR

R/W

0h

Active Synchronous Rectification Enable Bit

0h = ASR mode is disabled

1h = ASR mode is enabled

1-0

CSA_GAIN

Current Sense Amplifier's Gain Settings

0h = CSA gain is 0.15 V/A

1h = CSA gain is 0.3 V/A

2h = CSA gain is 0.6 V/A

3h = CSA gain is 1.2 V/A

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8.6.2.6 Control Register 6 (Offset = 8h) [Reset = 00h]

Control Register 6 is shown in 图8-56 and described in 表8-23.

Return to the 表8-16.

图8-56. Control Register 6

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

RESERVED

R/W-0h

BUCK_PS_DIS

R/W-0h

BUCK_CL

R/W-0h

BUCK_SEL

R/W-0h

BUCK_DIS

R/W-0h

表8-23. Control Register 6 Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7-6

5

RESERVED

BUCK_PS_DIS

R-0

0h

R/W

0h

4

0h

Buck Power Sequencing Disable Bit

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

3

BUCK_CL

R/W

0h

Buck Current Limit Setting

0h = Buck regulator current limit is set to 600 mA

1h = Buck regulator current limit is set to 150 mA

2-1

BUCK_SEL

Buck Voltage Selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

0

BUCK_DIS

R/W

0h

Buck Disable Bit

0h = Buck regulator is enabled

1h = Buck regulator is disabled

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8.6.2.7 Control Register 10 (Offset = Ch) [Reset = 00h]

Control Register 10 is shown in 图8-57 and described in 表8-24.

Return to the 表8-16.

图8-57. Control Register 10

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

DLYCMP_EN

R/W-0h

DLY_TARGET

R/W-0h

表8-24. Control Register 10 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

R-0

0h

Reserved

DLYCMP_EN

R/W

0h

Driver Delay Compensation enable

0h = Disable

1h = Enable

3-0

DLY_TARGET

R/W

0h

Delay Target for Driver Delay Compensation

0h = 0 us

1h = 0.4 us

2h = 0.6 us

3h = 0.8 us

4h = 1 us

5h = 1.2 us

6h = 1.4 us

7h = 1.6 us

8h = 1.8 us

9h = 2 us

Ah = 2.2 us

Bh = 2.4 us

Ch = 2.6 us

Dh = 2.8 us

Eh = 3 us

Fh = 3.2 us

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The DRV8316C can be used to drive Brushless-DC motors. The following design procedure can be used to

configure the DRV8316C.

V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

Voltage

Supervisor

VREF

AVDD

Microcontroller

C_AVDD

AGND

ADC

1000

30 pF

1000

30 pF

1000

30 pF

SOC

SOB

Replace Resistor (R_BK) with Inductor

(L_BK) for larger external load or to

reduce power dissipaꢀon

L_BK

Current

Sensing

ADC

CSA

External

Load

SW_BK

R_BK

C_BK

DRV8316CR

GND_BK

SOA

ADC

GP-I

R_PU1

FB_BK

nFAULT

nSLEEP

DRVOFF

Driver

Control

Sleep Control

GP-O

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

Hall

Sensors

(Optional)

OUTA

OUTB

PWM

Control

Module

PWM

Control

Input

GP-O

A

B

SDO

GP-I

GP-O

nSCS

SCLK

SPI

OUTC

PGND

SDI

Hall Input

GP-I

图9-1. Primary Application Schematics

70

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9.2 Typical Applications

9.2.1 Three-Phase Brushless-DC Motor Control

In this application, the DRV8316C is used to drive a Brushless-DC motor.

9.2.1.1 Detailed Design Procedure

表9-1 lists the example input parameters for the system design.

表9-1. Design Parameters

DESIGN PARAMETERS

REFERENCE

EXAMPLE VALUE

Supply voltage

V_VM

I_RMS

I_PEAK

f_PWM

SR

24 V

3 A

Motor RMS current

Motor peak current

8 A

PWM Frequency

50 kHz

Slew Rate Setting

200 V/µs

3.3 V

Buck regulator output voltage

ADC reference voltage

System ambient temperature

V_BK

V_VREF

T_A

3.0 V

–20°C to +105°C

9.2.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V or 24 V). Operating a motor at a

higher voltage corresponds to a lower drive current to obtain the same motor power. Operating at lower voltages

generally allows for more accurate control of phase currents. The DRV8316C functions down to a supply of 4.5

V. A higher operating voltage also corresponds to a higher obtainable rpm. The DRV8316C allows for a range of

possible operating voltages because of a maximum VM rating of 40 V.

9.2.1.1.2 Using Active Demagnetization

Active demagnetization reduces power losses in the device by turning on the MOSFETs automatically when the

body diode starts conducting to reduce diode conduction losses. It is used in trapezoidal commutation when

switching commutation states (turning a high-side MOSFET off and another high-side MOSFET on while keeping

a low-side MOSFET on). Active demagnetization is enabled when EN_ASR and EN_AAR bits are set in the SPI

variant or OCP/SR pin is set to Mode 3 or Mode 4 in the H/W variant.

When switching commutation states with active demagnetization disabled, dead time is inserted and the low-side

MOSFET’s body diode conducts while turning another high-side MOSFET on to continue sourcing current

through the motor. This conduction period causes higher power losses due to the forward-bias voltage of the

diode and slower dissipation of current. 图9-2 shows the body diode conducting when switching commutation

states.

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图9-2. Active demagnetization disabled in DRV8316C

When active demagnetization is enabled, the AD_HS and AD_LS comparators detect when the sense FET

voltage is higher or lower than the programmed threshold. After the dead time period, if the threshold is

exceeded for a fixed amount of time, the body diode is conducting and the logic core turns the low-side FET on

to provide a conduction path with smaller power losses. Once the V_DSvoltage is below the comparator

threshold, the MOSFET turns off and current briefly conducts through the body diode until the current completely

decays to zero. This is shown in 图9-3.

图9-3. Active demagnetization enabled in DRV8316C

9.2.1.1.3 Driver Propagation Delay and Dead Time

Driver propagation delay (t_PD) and dead time (t_dead) is specified with a typical and maximum value, but not with a

minimum value. This is due to the direction of current at the OUTx pin when synchronous inputs are switching.

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Driver propagation delay and dead time can be shorter than typical values due to slower internal turn-ons of the

high-side or low-side internal MOSFETs to avoid internal dV/dt coupling.

For more information and examples of how propagation delay and dead time differs for input PWM and output

configurations, please visit the Delay and Dead Time in Integrated MOSFET Drivers application note.

The dead time from the microcontroller’s PWM outputs can be used as an extra precaution in addition to the

DRV8316C internal shoot-through protection. This creates a condition where internal logic prioritizes the MCU

dead time or driver dead time based on their durations.

If the MCU dead time is less than the driver dead time, the driver will compensate and make the true output dead

time the value specified by the DRV8316C. If the MCU inserted dead time is larger than the driver dead time,

then the DRV8316C will adjust accordingly to the MCU dead time as shown in the table below.

A summary of the device delay times with respect to synchronous inputs INHx and INLx, OUTx current direction,

and inserted MCU dead time are shown in 表9-2.

表9-2. Summary of delay times in integrated FET devices depending on inputs and output current

direction

OUTx current

direction

INHx

INLx

Propagation

Dead Time (t_dead) Inserted MCU dead time (t_dead(MCU))

Delay (t_PD

)

t_dead(MCU)< t_deadt_dead(MCU)> t_dead

Out of OUTx

Into OUTx

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Typical

Output dead time Output dead time

= t_dead

Output dead time Output dead time

< t_dead< t_dead(MCU)

Output dead time Output dead time

< t_dead< t_dead(MCU)

Output dead time Output dead time

= t_dead= t_dead(MCU)

= t_dead(MCU)

Smaller than

typical

Smaller than

typical

Smaller than

typical

Smaller than

typical

Typical

9.2.1.1.4 Using Delay Compensation

Differences in delays of dead time and propagation delay can cause mismatch in the output timings of PWMs,

which can lead to duty cycle distortion. In order to accommodate differences in propagation delay between

various input conditions, the DRV8316C integrates a Delay Compensation feature.

Delay Compensation is used to match delay times for currents going into and out of phase by adding a variable

delay time (t_var) to match a preset target delay time. This delay time is configurable in SPI devices, and it is

recommended in the datasheets to choose a target delay time that is equal to the propagation delay time plus

the driver dead time (t_pd+ t_dead).

For an example of Delay Compensation implementation, please visit the Delay and Dead Time in Integrated

MOSFET Drivers application note.

9.2.1.1.5 Using the Buck Regulator

In DRV8316C, the buck regulator components must be populated whether the buck is used or unused.

If unused, Resistor Mode should be configured by placing a small value resistor of 22-Ω for R_BKand a 10-V

rated, 22-µF capacitor for C_BKto minimize board space and reduce component cost. To disable the buck

regulator, set the BUCK_DIS in the SPI variant. The buck cannot be disabled in the Hardware variant.

If the buck regulator is used, either the Inductor or Resistor Mode can be selected. Inductor Mode allows a 22-

µH or 47-µH inductor be used for L_BK. C_BKis recommended to be 22-µF. Ensure an appropriate inductor is

chosen to allow for maximum peak saturation current at a 20% inductance drop since the buck can supply up to

600-mA external current.

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Resistor Mode allows for power to be dissipated in an external resistor if the load requirement is less than 40-

mA. Ensure the resistor is rated for the power dissipation required at worst case VM voltage dropout. See 方程式

6, 方程式 7, and 方程式 8 to calculate the resistor power rating required for a 24-V rated system, 3.3V buck

output voltage, and 20-mA load current.

P

> V − V

× I

BK

(6)

(7)

(8)

R

M

BK

>

24V − 3.3V × 20mA

R

> 0.434W

R_BK

9.2.1.1.6 Current Sensing and Output Filtering

The SOx pins are typically sampled by an analog-to-digital converter in the MCU to calculate the phase current.

Phase current calculations are used for closed-loop feedback such as Field-oriented control.

An example calculation for phase current is shown in 方程式 9, 方程式 10, and 方程式 11 for a system using

VREF = 3.0V, GAIN = 0.15 V/A, and a SOx voltage of 1.2V.

VREF

2

SOx =

1.2V =

± GAIN × I

(9)

OUTx

3.0V

2

± 0.15 V/A × I

(10)

(11)

OUTx

I

= − 2.0 A

OUTx

Sometimes high frequency noise can appear at the SOx signals based on voltage ripple at VREF, added

inductance at the SOx traces, or routing of SOx traces near high frequency components. It is recommended to

add a low-pass RC filter close to the MCU with cutoff frequency at least 10 times the PWM switching frequency

for trapezoidal commutation and 100 times the PWM switching frequency for sinusoidal commutation to filter

high frequency noise. A recommended RC filter is 330-ohms, 22-pF to add minimal parallel capacitance to the

ADC and current mirroring circuitry. The cutoff frequency for the low-pass RC filter is in 方程式12.

1

f =

(12)

c

2πRC

9.2.1.2 Application Curves

图9-4. Device powerup with VM

图9-5. Device powerup with nSLEEP

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图9-6. Driver PWM operation with feedback

图9-7. Power management

图9-8. Driver PWM with active demagnetization

图9-9. Driver delay compensation (1.8 μs)

(ASR and AAR)

9.2.2 Three-Phase Brushless-DC Motor Control With Current Limit

In this application, the DRV8316C is used to drive a brushless-DC motor with current limit up to 100% duty cycle.

The following design procedure can be used to configure the DRV8316C in current limit mode.

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9.2.2.1 Block Diagram

V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

AVDD

AGND

Microcontroller

C_AVDD

R_ILIM1

ILIM

R_ILIM2

Replace Resistor (R_BK) with Inductor

(L_BK) for larger external load or to

reduce power dissipaꢀon

SOC

SOB

SOA

CSA

L_BK

External

Load

SW_BK

R_PU1

R_BK

C_BK

DRV8316CR

GND_BK

nFAULT

GP-I

FB_BK

Sleep Control

nSLEEP

DRVOFF

GP-O

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

PWM

GP-O

PWM

Control

Input

Hall

Sensors

(Optional)

OUTA

OUTB

Control

Module

GP-O

A

B

SDO

GP-I

GP-O

nSCS

SCLK

SPI

OUTC

PGND

SDI

Hall Input

GP-I

图9-10. Alternate Application - BLDC Motor Control with Current Limit

9.2.2.2 Detailed Design Procedure

表9-3 lists the example input parameters for the system design.

表9-3. Design Parameters

DESIGN PARAMETERS

REFERENCE

EXAMPLE VALUE

24 V

Supply voltage

V_VM

I_PEAK

f_PWM

SR

Motor peak current

PWM Frequency

2 A

50 kHz

Slew Rate Setting

200 V/µs

3.3 V

Buck regulator output voltage

V_BK

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9.2.2.2.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V or 24 V). Operating a motor at a

higher voltage corresponds to a lower drive current to obtain the same motor power. Operating at lower voltages

generally allows for more accurate control of phase currents. The DRV8316C functions down to a supply of 4.5V.

A higher operating voltage also corresponds to a higher obtainable rpm. The DRV8316C allows for a range of

possible operating voltages because of a maximum VM rating of 40 V.

9.2.2.2.2 ILIM Implementation

The ILIM pin on the DRV8316C device is used to set a cycle-by-cycle current limit proportional to the voltage on

the ILIM pin. The analog voltage ILIM can be set using a digital-to-analog converter from an external

microcontroller or a resistor divider. Applying AVDD/2 on the ILIM pin disables the cycle-by-cycle current limit,

and applying (AVDD/2 - 0.4) V on ILIM pin sets the current limit at the maximum threshold of 8-A.

方程式 13, 方程式 14, and 方程式 15 shows how to set the ILIM voltage with respect to AVDD = 3.3V to set

cycle-by-cycle current limit to 2-A.

10 kΩ

1.55V = 3.3

ILIM V =

(13)

R

+ 10 kΩ

ILIM1

3.3

2

1.25 −

V

× 2 A + 1.65 V

(14)

(15)

8 A

ILIM V = 1.55V

Use 方程式 16 to calculate values for an AVDD-sourced resistor divider with resistors RILIM1 and RILIM2 to set

ILIM equal to the 2-A calculated current limit.

R

ILIM2

ILIM V = AVDD

(16)

R

+ R

ILIM1

ILIM2

To reduce current load on AVDD, R_ILIM2is configured to be 10 kΩas shown in 方程式17 and 方程式18.

10 kΩ

1.55V = 3.3

(17)

(18)

R

+ 10 kΩ

ILIM1

R

= 11.29 kΩ

ILIM1

Cycle-by-cycle limit can also occur with 100% PWM duty cycle inputs using an internal PWM pulse to monitor

the current with ILIM. Setting the PWM_100_DUTY_SEL configures the frequency of the internal PWM pulse to

20kHz or 40kHz.

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9.2.2.3 Application Curves

图9-12. Device 100% Operation with Current

Chopping (Latched shutdown mode)

图9-11. Driver PWM with Current Limit

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9.2.3 Brushed-DC and Solenoid Load

In this application, the DRV8316C can be configured to drive a Brushed-DC motor and a solenoid load.

9.2.3.1 Block Diagram

V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

AVDD

Microcontroller

C_AVDD

R_ILIM1

AGND

ILIM

R_ILIM2

SOC

SOB

SOA

Replace Resistor (R_BK) with Inductor

(L_BK) for larger external load or to

reduce power dissipaꢀon

CSA

L_BK

External

Load

SW_BK

R_PU1

R_BK

C_BK

DRV8316CR

GND_BK

nFAULT

GP-I

FB_BK

nSLEEP

DRVOFF

Sleep Control

GP-O

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

PWM

Control

Module

PWM

Control

Input

OUTA

OUTB

GP-O

M

V_VM

SDO

GP-I

GP-O

nSCS

SCLK

SPI

Load

OUTC

PGND

SDI

图9-13. Alternate Application - Brushed DC Motor and Solenoid with Current Limit

9.2.3.2 Design Requirements

表9-4 gives design input parameters for system design.

表9-4. Design Parameters

DESIGN PARAMETER

REFERENCE

EXAMPLE VALUE

Brushed motor rms current

I_{RMS, BDC}

1.0 A

2.0 A

0.5 A

1.0 A

Brushed motor peak current

Solenoid rms current

I_{PEAK, BDC}

I_{RMS, SOL}

Solenoid peak current

I_{PEAK, SOL}

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9.2.3.2.1 Detailed Design Procedure

表9-5. Brushed-DC Control

Function

IN1

EN1

IN2

EN2

OUT1

OUT2

Forward

Reverse

1

0

1

0

1

H

L

H

Brake (low-side slow

decay)

0

1

0

1

L

High-side slow decay

Coast

1

0

1

0

H

Z

H

Z

X

表9-6. Solenoid Control (High-Side Load)

Function

IN3

EN3

OUT3

Coast / Off

On

X

0

1

0

1

Z

L

Brake

H

6x PWM mode or 3x PWM mode (with or without current limit) can be used to drive three solenoid loads

depending on the application.

A Brushed-DC motor can be connected to two OUTx phases to create an integrated full H-bridge configuration to

drive the motor. In 6x PWM mode or 3x PWM mode, current feedback can be monitored through the SOx pins of

the H-bridge when current is dissipated through that phase’s low-side FET during motor control. In 6x PWM

with Current Limit or 3x PWM with Current Limit mode, cycle-by-cycle current can be implemented by setting the

ILIM analog voltage to the proportional threshold.

Solenoid loads can be connected from OUTx to VM or GND to use the DRV8316C as a push-pull driver in 6x

PWM or 3x PWM mode. When the load is connected from OUTx to GND, current is sourced from the high-side

MOSFET and therefore current feedback or cycle-by-cycle current limit is not available. When the load is

connected from OUTx to VM, current feedback or cycle-by-cycle current limit can be used depending on the

mode configuration.

80

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9.2.4 Three Solenoid Loads

The DRV8316C can be used to drive three solenoid loads. The following design procedure can be used to

configure the DRV8316C for three solenoid loads.

9.2.4.1 Block Diagram

V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

AVDD

Microcontroller

C_AVDD

R_ILIM1

AGND

ILIM

R_ILIM2

SOC

SOB

SOA

Replace Resistor (R_BK) with Inductor

(L_BK) for larger external load or to

reduce power dissipaꢀon

CSA

L_BK

External

Load

SW_BK

R_PU1

R_BK

C_BK

DRV8316CR

GND_BK

nFAULT

GP-I

FB_BK

Sleep Control

nSLEEP

DRVOFF

GP-O

V_VM

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

PWM

Control

Module

PWM

Control

Input

Load

OUTA

OUTB

GP-O

V_VM

Load

V_VM

SDO

GP-I

GP-O

nSCS

SCLK

SPI

OUTC

PGND

SDI

图9-14. Alternate Application - Three Solenoid Loads with Current Limit

9.2.4.2 Design Requirements

表9-7 gives design input parameters for system design.

表9-7. Design Parameters

DESIGN PARAMETER

REFERENCE

EXAMPLE VALUE

Solenoid rms current

I_{RMS, SOL}

1.0 A

1.5 A

Solenoid peak current

I_{PEAK, SOL}

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9.2.4.2.1 Detailed Design Procedure

表9-8. Solenoid Control (high-side load)

Function

IN2

EN2

OUT2

Coast / Off

On

X

0

1

0

1

Z

L

Brake

H

表9-9. Solenoid Control (low-side load)

Function

IN1

EN1

OUT1

Coast / Off

On

X

1

0

1

Z

H

L

Brake

6x PWM mode or 3x PWM mode (with or without current limit) can be used to drive three solenoid loads

depending on the application.

Solenoid loads can be connected from OUTx to VM or GND to use the DRV8316C as a push-pull driver in 6x

PWM or 3x PWM mode. When the load is connected from OUTx to GND, current is sourced from the high-side

MOSFET and therefore current feedback or cycle-by-cycle current limit is not available. When the load is

connected from OUTx to VM, current feedback or cycle-by-cycle current limit can be used depending on the

mode configuration.

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10 Power Supply Recommendations

10.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

• The highest current required by the motor system

• The capacitance and current capability of the power supply

• The amount of parasitic inductance between the power supply and motor system

• The acceptable voltage ripple

• The type of motor used (brushed dc, brushless DC, stepper)

• The motor braking method

The inductance between the power supply and the motor drive system limits the rate current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

图10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

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11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high

current.

Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed

closely to device pins.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the

device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to

reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the I2 × RDS(on) heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Separate the SW_BUCK and FB_BUCK traces with ground separation to reduce buck switching from coupling

as noise into the buck outer feedback loop. Widen the FB_BUCK trace as much as possible to allow for faster

load switching.

Recommended Layout Example for VQFN Package shows a layout example for the DRV8316C.

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11.2 Layout Example

Recommended Layout Example for VQFN Package

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11.3 Thermal Considerations

The DRV8316C has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C

(minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation

The power loss in DRV8316C include standby power losses, LDO and Buck power losses, FET conduction and

switching losses, and diode losses. The FET conduction loss dominates the total power dissipation in

DRV8316C. At start-up and fault conditions, the output current is much higher than normal current; remember to

take these peak currents and their duration into consideration. The total device dissipation is the power

dissipated in each of the three half bridges added together. The maximum amount of power that the device can

dissipate depends on ambient temperature and heatsinking. Note that RDS,ON increases with temperature, so

as the device heats, the power dissipation increases. Take this into consideration when designing the PCB and

heatsinking.

A summary of equations for calculating each loss is shown below for trapezoidal controland field-oriented

control.

表11-1. DRV8316C Power Losses for Trapezoidal and Field-oriented Control

Loss type

Standby power

LDO

Trapezoidal

Field-oriented control

P_standby= VM x I_{VM_TA}

P_LDO= (VM-V_AVDD) x I_AVDDD, if BUCK_PS_DIS = 1b

P_LDO= (V_BK-V_AVDD) x I_AVDDD, if BUCK_PS_DIS = 0b

FET conduction

FET switching

P_CON= 2 x (I_PK(trap))²x R_ds,on(TA)

P_CON= 3 x ( I_RMS(FOC))²x R_ds,on(TA)

P_SW= I_PK(trap)x V_PK(trap)x t_rise/fallx f_PWM

P_SW= 3 x I_RMS(FOC)x V_PK(FOC)x t_rise/fall

f_PWM

x

Diode

Buck

P_diode= 2 x I_PK(trap)x V_F(diode)x t_DEADTIME

f_PWM

x

P_diode= 6 x I_RMS(FOC)x V_F(diode)x t_DEADTIME

f_PWM

x

P_BK= 0.11 x V_BKx I_BKassuming (η_BK= 90%)

86

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Visit the DRV8316CR EVM Tool Page

• Read the Delay and Dead Times in Integrated MOSFET Drivers application note

• Download the BLDC Integrated MOSFET Thermal Calculator tool

• Calculating Motor Driver Power Dissipation, SLVA504

• PowerPAD™ Thermally Enhanced Package, SLMA002

• PowerPAD™ Made Easy, SLMA004

• Sensored 3-Phase BLDC Motor Control Using MSP430, SLAA503

• Understanding Motor Driver Current Ratings, SLVA505

12.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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GENERIC PACKAGE VIEW

RGF 40

5 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225115/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

A

RGF0040E

5.1

4.9

B

PIN 1 INDEX AREA

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

3.8

3.6

3.5

0.05

0.00

(0.1) TYP

20

13

36X 0.5

21

12

SYMM

41

5.8

5.6

5.5

1

32

0.3

40X

PIN 1 ID

(OPTIONAL)

0.2

33

40

SYMM

0.1

C A B

C

0.5

0.3

40X

0.05

4224999/B 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.7)

(3.5)

40

33

40X (0.6)

40X (0.25)

1

32

(Ø0.2) TYP

VIA

SYMM

41

(5.7) (5.5)

(6.8)

(1.35)

(1.25)

21

12

13

20

(R0.05) TYP

36x (0.5)

(0.625)

(0.975)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224999/B 06/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.5)

36X (0.5)

40

33

40X (0.6)

40X (0.25)

41

1

32

12X

(1.15)

SYMM

(5.5)

(6.8)

(0.675)

(1.35)

12

21

(R0.05) TYP

13

20

(1.25)

12X (1.05)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

69% PRINTED COVERAGE BY AREA

SCALE: 12X

4224999/B 06/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8316C
厂家：	TEXAS INSTRUMENTS
描述：	具有集成电流检测功能、最大电压为 40V、峰值电流为 8A 的三相电机驱动器电机驱动驱动器
文件：	总94页 (文件大小：4060K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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