DRV8317HREER_技术文档

DRV8317

SLVSGT3 – DECEMBER 2022

DRV8317 Three-Phase PWM Motor Driver

1 Features

3 Description

•

Three-phase BLDC motor driver

– Configurable slew rate for EMI mitigation

– Programmable gain current sensing

– Supports up to 200-kHz PWM frequency

– Integrated shoot through protection

4.5-V to 20-V operating voltage

– 24-V absolute maximum voltage

High output current capability

DRV8317 provides three integrated MOSFET half-

bridges for driving three-phase brushless DC (BLDC)

motors with 5-V, 9-V, 12-V, or 18-V DC rails or 2s

to 4s batteries. The device provides integrated three-

phase current sensing which eliminates the need for

external sense resistors. DRV8317 has an integrated

LDO that provides a regulated 3.3-V rail capable of

delivering up to 80mA for external loads like MCU,

logic circuits, hall sensors etc.,

•

– 5-A peak current drive

Low on-state resistance MOSFETs

– R_DS(ON)(HS + LS) at T_A= 25°C : 130-mΩ

(typical)

Ultra-low Q-current sleep mode

– 3-µA (max.) at V_VM= 12-V, T_A= 25°C

Multiple control interface options

– 6x PWM control interface

DRV8317 provides a configurable 6x or 3x PWM

control scheme which can be used to implement

sensored or sensorless field-oriented control (FOC),

sinusoidal control, or trapezoidal control using an

external microcontroller. DRV8317 is capable of

driving a PWM frequency of up to 200 kHz. DRV8317

is highly configurable either through SPI (DRV8317S)

or pins (DRV8317H) - PWM mode, slew rate, current

sense gain are some of the configurable features.

•

– 3x PWM control interface

Integrated current sensing

•

– No external current sense resistor required

– Three-phase current sense outputs

SPI and hardware device variants

– 10-MHz SPI interface variant for flexibility

– Pin configurable variant for simplicity

Supports 1.8-V, 3.3-V, and 5-V logic inputs

Built-in 3.3-V ± 4.5%, 80-mA LDO regulator

Integrated protection features

A number of protection features including supply

under voltage lockout (UVLO), over voltage protection

(OVP), charge pump under voltage (CPUV), over

current protection (OCP), over temperature warning

(OTW) and over temperature shutdown (OTS) are

integrated into DRV8317 to protect the device, motor,

and system against fault events. Fault conditions are

indicated by the nFAULT pin.

•

– VM under voltage lockout (UVLO)

– VM over voltage protection (OVP)

– Charge pump under voltage (CPUV)

– Over current protection (OCP)

– Over temperature warning and shutdown

(OTW/OTS)

Device Variant Information⁽¹⁾

PART NUMBER

DRV8317S⁽²⁾

DRV8317H

PACKAGE

WQFN (36)

BODY SIZE (NOM)

5.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

– Fault condition indication pin (nFAULT)

(2) Device available for preview only.

2 Applications

4.5 to 20-V (24-V abs max)

LDO out

3.3V, up to 80mA

•

Brushless-DC (BLDC) Motor Modules

Air Purifiers

Dishwasher Pumps

6x / 3x PWM

PWM input

DRV8317S/H

A

B

C

nSLEEP

Charge Pump

Vacuum Robots

SPI

Only on SPI variant

Built-in Protec on

LDO Regulator

Washer and Dryer Pumps

Drones and Hand-held Gimbals

Laptop, Desktop, and Server Fans

Coffee Machines

MCU

CSA out

3x current feedback

5-A peak output current

nFAULT

Integrated Current Sensing

Figure 3-1. DRV8317S/H Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8317

SLVSGT3 – DECEMBER 2022

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................7

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................18

8.4 Device Functional Modes..........................................34

8.5 SPI Communication.................................................. 35

8.6 DRV8317 Registers.................................................. 37

9 Application and Implementation..................................55

9.1 Application Information............................................. 55

9.2 Typical Applications.................................................. 56

9.3 Alternate Applications............................................... 59

10 Power Supply Recommendations..............................60

10.1 Bulk Capacitance....................................................60

11 Layout...........................................................................61

11.1 Layout Guidelines................................................... 61

11.2 Layout Example...................................................... 62

11.3 Thermal Considerations..........................................63

12 Device and Documentation Support..........................64

12.1 Support Resources................................................. 64

12.2 Trademarks.............................................................64

12.3 Electrostatic Discharge Caution..............................64

12.4 Glossary..................................................................64

13 Mechanical, Packaging, and Orderable

Information.................................................................... 64

4 Revision History

DATE

REVISION

NOTES

April 2022

*

Initial release

2

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5 Device Comparison Table

DEVICE

DRV8317S

DRV8317H

PACKAGES

INTERFACE

SPI

36-pin WQFN (5-mm x 4-mm)

Hardware (Pin)

Table 5-1. DRV8317S vs DRV8317H Configuration Comparison

Parameters

DRV8317S

DRV8317H

PWM control mode

Slew rate

PWM_MODE (4 settings)

SLEW_RATE (4 settings)

CSA_GAIN (4 settings)

OCP_TBLANK (4 settings)

OCP_DEG (4 settings)

MODE pin (2 settings)

SLEW pin (4 settings)

GAIN pin (4 settings)

Fixed to 0.7-µs

Current sense amplifier gain

OCP blanking time

OCP deglitch time

Fixed to 0.6-µs

OCP_MODE (4 settings), Configurable retry

time

OCP mode

5-ms automatic retry

Dead time

Propagation delay

Fixed based on SLEW_RATE setting

DLYCMP_EN (2 settings)

Fixed based on SLEW pin setting

Disabled

Driver delay compensation

Spread Spectrum Clock for internal oscillator

SSC_DIS (2 settings)

Enabled

VM under voltage protection always enabled.

VM under voltage protection mode set

by UVP_MODE (2 settings); configurable

retry time using SLOW_TRETRY and

FAST_TRETRY.

VM under voltage protection always enabled.

Auto-retry mode for VM under voltage with

5-ms retry time.

VM under voltage lockout

VIN_AVDD, AVDD under voltage lockout

CP under voltage lockout

VIN_AVDD and AVDD under voltage

protection always enabled. Device resets on protection always enabled. Device resets on

VIN_AVDD and AVDD under voltage

VIN_AVDD or AVDD under voltage.

CP under voltage protection always enabled.

CP under voltage protection mode set

by UVP_MODE (2 settings); configurable

retry time using SLOW_TRETRY and

FAST_TRETRY.

CP under voltage protection always enabled.

Auto-retry mode for CP under voltage with

5-ms retry time.

OVP_MODE (2 settings); configurable

retry time using SLOW_TRETRY and

FAST_TRETRY

VM over voltage

SPI fault

5-ms automatic retry

N/A

SPIFLT_MODE (2 settings)

Enable/disable using OTW_FET_EN. If

enabled, over temperature warning is

reported on nFAULT pin and OTW_FET bit

in OT_STS register.

FET over temperature warning (OTW_FET)

FET over temperature shutdown (OTS_FET)

Disabled

OTF_MODE (2 settings); configurable

retry time using SLOW_TRETRY and

FAST_TRETRY

5-ms automatic retry

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6 Pin Configuration and Functions

36 35 34 33 32 31 30 29

nSLEEP

nFAULT

NC

1

2

3

4

5

6

7

8

9

10

28 INLC

27 INHC

INLB

26

25

24

CPL

CPH

INHB

INLA

CP

23 INHA

VIN_AVDD

VM

AVDD

AGND

VM

22

21

20

VM

Thermal Pad

PGND

19 PGND

11 12 13 14 15 16 17 18

Figure 6-1. DRV8317S 36-Pin WQFN With Exposed Thermal Pad Top View

36 35 34 33 32 31 30 29

nSLEEP

nFAULT

NC

1

2

3

4

5

6

7

8

9

10

28 INLC

27 INHC

INLB

26

25

24

CPL

CPH

INHB

INLA

CP

23 INHA

VIN_AVDD

VM

AVDD

AGND

VM

22

21

20

VM

Thermal Pad

PGND

19 PGND

11 12 13 14 15 16 17 18

Figure 6-2. DRV8317H 36-Pin WQFN With Exposed Thermal Pad Top View

Table 6-1. Pin Functions

36-pin package

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8317S DRV8317H

AGND

21

GND

Device analog ground. Connect to a separate ground plane.⁽¹⁾

3.3V regulator output. Connect a X5R or X7R, 2.2-µF (no load) or 4.7-µF (up to

80mA load), 6.3-V ceramic capacitor between the AVDD and AGND pins. This

regulator can source up to 80 mA for external loads.

AVDD

CP

22

PWR O

PWR

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between

the CP and VM pins.

6

CPH

CPL

5

4

5

4

PWR

Charge pump switching node. Connect a X5R or X7R, 100-nF, (2xVM)- rated

ceramic capacitor between the CPH and CPL pins.

4

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Table 6-1. Pin Functions (continued)

36-pin package

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8317S DRV8317H

Current sense amplifier power supply input/reference. Connect a X5R or X7R, 0.1-

µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.

CSAREF

GAIN

INHA

INHB

INHC

INLA

33

—

23

25

27

24

26

28

33

29

23

25

27

24

26

28

PWR I

Available only in hardware variant (DRV8317H). The pin is a 4-level input pin for

current sense amplifier gain setting.

I

High-side driver control input for OUTA. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

High-side driver control input for OUTB. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

High-side driver control input for OUTC. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

Low-side driver control input for OUTA. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

Low-side driver control input for OUTB. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

INLB

Low-side driver control input for OUTC. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

INLC

Available only in hardware variant (DRV8317H). This is a 4-level input pin for PWM

mode setting.

MODE

NC

—

3

31

3, 32

2

I

—

O

No connect. Leave the pin floating.

Fault indication pin. Pulled low during fault condition. Open-drain output; requires an

external pull-up resistor to AVDD.

nFAULT

2

Available only in SPI variant (DRV8317S). Serial chip select. A logic low on this pin

enables serial interface communication.

nSCS

32

1

—

1

I

When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-µs

low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep

mode.

nSLEEP

OUTA

OUTB

OUTC

11, 12

14, 15

17, 18

11, 12

14, 15

17, 18

O

Half-bridge output A. Connect to motor winding.

Half-bridge output B. Connect to motor winding.

Half-bridge output C. Connect to motor winding.

10, 13, 16, 10, 13, 16,

PGND

SCLK

SDI

PWR

Device power ground. Connect to a separate ground plane.⁽¹⁾

19

Available only in SPI variant (DRV8317S). Serial clock input. Serial data is shifted

out on the rising edge and captured on the falling edge of SCLK.

31

—

I

Available only in SPI variant (DRV8317S). Serial data input. Data (input) is captured

on the falling edge of the SCLK pin (SPI devices).

30

29

—

30

Available only in SPI variant (DRV8317S). Serial data output. Data (output) is shifted

out on the rising edge of the SCLK pin.

SDO

O

I

Available only in hardware variant (DRV8317H). This pin is a 4-level input pin for

OUTx voltage slew rate setting.

SLEW

SOA

36

35

34

7

36

35

34

7

O

Current sense amplifier output for OUTA.

Current sense amplifier output for OUTB.

Current sense amplifier output for OUTC.

Input supply for AVDD LDO

SOB

SOC

O

VIN_AVDD

PWR

Device and motor power supply. Connect to motor supply voltage; bypass to PGND

with a 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage

rating at least twice the normal operating voltage of the device

VM

8, 9, 20

PWR

Thermal

pad

Must be connected to AGND.

(1) I = input, O = output, PWR = power, GND = ground, NC = no connect

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

Power supply pin voltage (VM, VIN_AVDD)

Power supply voltage ramp during power up (VM)

Voltage difference between ground pins (PGND, AGND)

Charge pump voltage (CP)

–0.3

24

V

V/µs

V

2

–0.3

0

0.3

V_M+ 6

V

Analog regulator pin voltage (AVDD)

4

V

Logic pin input voltage (INHx, INLx, nSCS, nSLEEP, SCLK, SDI, GAIN, MODE, SLEW)

Logic pin output voltage (SDO)

6

V

6

V

Open drain pin output voltage (nFAULT)

Open drain output current range (nFAULT)

Current sense amplifier reference supply input (CSAREF)

Current sense amplifier output (SOx)

6

V

5

mA

V

-0.3

–1

4

V

Output pin voltage (OUTA, OUTB, OUTC)

Ambient temperature, T_A

V_M+ 1 ⁽²⁾

125

V

–40

–65

°C

Junction temperature, T_J

150

Storage tempertaure, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

(2) Maximum voltage supported on OUTx pin is 24V

7.2 ESD Ratings

VALUE

±2500

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_VM

Power supply voltage

V_VM, V_{VIN_AVDD}

4.5

12

20

5

V

A

V_VM≥ 6 V, OUTA, OUTB, OUTC

4.5 V ≤ V_VM< 6 V, OUTA, OUTB, OUTC

nFAULT

(1)

I_OUT

Peak output winding current

3

A

V_OD

I_OD

T_A

Open drain pullup voltage

–0.3

5.5

5

V

Open drain output current capability

Operating ambient temperature

Operating Junction temperature

nFAULT

mA

°C

–40

125

150

T_J

(1) Power dissipation and thermal limits must be observed

6

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7.4 Thermal Information

DRV8317

THERMAL METRIC⁽¹⁾

REE (WQFN)

36

UNIT

R_θJA

Junction-to-ambient thermal resistance (JEDEC 4-layer PCB, 6 thermal vias)

Junction-to-case (top) thermal resistance

36.4

23.7

14

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

Ψ_JT

Junction-to-top characterization parameter

0.6

14

Ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

R_θJC(bot)

4.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES

V_VM= 12 V, nSLEEP = 0, T_A= 25 °C

nSLEEP = 0, T_A= 125 °C

1.7

3

µA

I_VMQ

VM sleep mode current

10

V_VM= 12 V, nSLEEP = 1, INHx = INLx =

0, SPI = 'OFF', T_A= 25 °C

8

10

12

14

mA

I_VMS

VM standby mode current

nSLEEP = 1, INHx = INLx = 0, SPI =

'OFF'

V_VM= 12 V, nSLEEP = 1, f_PWM= 25 kHz,

T_A= 25 °C

10

V_VM= 12 V, nSLEEP = 1, f_PWM= 200

kHz, T_A= 25 °C

I_VM

VM operating mode current

nSLEEP =1, f_PWM= 25 kHz

nSLEEP =1, f_PWM= 200 kHz

10

12

15

mA

V_VM≥ 6V, V_{VIN_AVDD}≥ 6V, 0 mA ≤ I_AVDD

80 mA

≤

V_AVDD

Analog regulator voltage

3.15

3.3

3.45

V

4.5V ≤ V_VM< 6V, 4.5V ≤ V_{VIN_AVDD}< 6V,

0 mA ≤ I_AVDD≤ 80 mA

I_AVDD

Analog regulator external load

Analog regulator current limit

4.5V ≤ V_VM< 6V, 4.5V ≤ V_{VIN_AVDD}< 6V

V_VM≥ 6V, V_{VIN_AVDD}≥ 6V

80

mA

uF

V

I_AVDD

I_{AVDD_LIM}

V_AVDD≥ 2.7V, soft short to GND

External load I_AVDD= 0 mA

100

0.5

2.35

3

125

2.2

4.7

5

150

7.05

5.5

C_AVDD

Capacitance for AVDD

External load 0mA ≤ I_AVDD≤ 80 mA

4.5V ≤ V_VM< 6V, CP with respect to VM

V_VM≥ 6V, CP with respect to VM

V_CP

Charge pump regulator voltage

4.5

5

5.5

V

V_VM> V_UVLO, nSLEEP = 1 to output

ready

t_WAKE

Wakeup time

1

3

ms

µs

V_CSAREF> V_{CSAREF_UV}to SOx ready,

when nSLEEP = 1

t_{WAKE_CSA}

Wakeup time for CSA

30

t_SLEEP

t_RST

Turn-off time

nSLEEP = 0 to driver tri-stated

nSLEEP = 0 period to reset faults

100

200

50

µs

Reset Pulse time

15

0

FOUR-LEVEL INPUTS (GAIN, MODE, SLEW)

V_L1Input mode 1 voltage

0.2*AVD

D

Tied to AGND

V

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

0.27*AV 0.4*AVD 0.545*AV

DD DD

0.606*AV 0.757*AV 0.909*AV

TYP

MAX UNIT

V_L2

V_L3

V_L4

Input mode 2 voltage

47 kΩ ± 5% tied to AGND

V

D

Input mode 3 voltage

Input mode 4 voltage

Hi-Z

DD

0.94*AV

DD

Tied to AVDD

AVDD

V

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

48

kΩ

Input pulldown resistance

160

DRIVER OUTPUTS

V_VM≥ 6 V, I_OUT= 1 A, T_J

= 25°C, includes bond wire and

metallization resistance

130

180

155

225

25

157

221.5

210

mΩ

Total MOSFET on resistance (High-side

+ Low-side)

R_DS(ON)

V_VM≥ 6 V, I_OUT= 1 A, T_J= 125°C,

across process, includes bond wire and

metallization resistance

4.5 V ≤ V_VM< 6 V, I_OUT= 1 A, T_J= 25°C,

includes bond wire and metallization

resistance

mΩ

Total MOSFET on resistance (High-side

+ Low-side)

R_DS(ON)

4.5 V ≤ V_VM< 6 V, I_OUT= 1 A, T_J

= 125°C,across process, includes bond

wire and metallization resistance

290

mΩ

V_VM= 12V, SLEW_RATE = 00b (SPI

Variant) or SLEW pin tied to AGND (HW

Variant)

13.75

27.5

62.5

80

36.25

72.5

187.5

320

V/µs

V_VM= 12V, SLEW_RATE = 01b (SPI

Variant) or SLEW pin to 47 kΩ +/- 5%

tied to AGND (HW Variant)

50

Phase pin slew rate switching low to high

(Rising from 20 % to 80 % of VM)

SR_RISE

V_VM= 12V, SLEW_RATE = 10b (SPI

Variant) or SLEW pin to Hi-Z (HW

Variant)

125

200

25

V_VM= 12V, SLEW_RATE = 11b (SPI

Variant) or SLEW pin tied to AVDD (HW

Variant)

V_VM= 12V, SLEW_RATE = 00b (SPI

Variant) or SLEW pin tied to AGND (HW

Variant)

13.75

27.5

62.5

80

48

V_VM= 12V, SLEW_RATE = 01b (SPI

Variant) or SLEW pin to 47 kΩ +/- 5%

tied to AGND (HW Variant)

50

72.5

187.5

Phase pin slew rate switching high to low

(Falling from 80 % to 20 % of VM)

SR_FALL

V_VM= 12V, SLEW_RATE = 10b (SPI

Variant) or SLEW pin to Hi-Z (HW

Variant)

125

200

V_VM= 12V, SLEW_RATE = 11b (SPI

Variant) or SLEW pin tied to AVDD (HW

Variant)

320

2

I_LEAK

Leakage current OUTx

V_VM= V_OUTx= 20 V, Standby State

V_OUTx= 0 V, Standby State

0.7

-10

mA

µA

-50

8

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VM= 12V, SLEW_RATE = 00b (SPI

Variant) or SLEW pin tied to AGND (HW

Variant)

575

1500

750

ns

V_VM= 12V, SLEW_RATE = 01b (SPI

Variant) or SLEW pin to 47 kΩ +/- 5%

tied to AGND (HW Variant)

325

250

t_DEAD

Dead time (high to low / low to high)

V_VM= 12V, SLEW_RATE = 10b (SPI

Variant) or SLEW pin to Hi-Z (HW

Variant)

600

V_VM= 12V, SLEW_RATE = 11b (SPI

Variant) or SLEW pin tied to AVDD (HW

Variant)

250

600

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 00b (SPI Variant) or SLEW

pin tied to AGND (HW Variant)

1300

1750

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 01b (SPI Variant) or SLEW

pin to 47 kΩ +/- 5% tied to AGND (HW

Variant)

800

1050

ns

Propagation delay (high-side / low-side

ON/OFF)

t_PD

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 10b (SPI Variant) or SLEW

pin to Hi-Z (HW Variant)

450

425

600

500

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 11b (SPI Variant) or SLEW

pin tied to AVDD (HW Variant)

ns

SLEW = 11b (SPI Variant) or SLEW pin

tied to AVDD (HW Variant)

t_{MIN_PULSE}

Minimum output pulse width

500

CURRENT SENSE AMPLIFIER

CSA_GAIN = 00b (SPI Variant) or GAIN

pin tied to AGND (HW Variant)

0.25

0.5

V/A

CSA_GAIN = 01b (SPI Variant) or GAIN

pin to 47 kΩ +/- 5% tied to AGND (HW

Variant)

G_CSA

Current sense gain

CSA_GAIN = 10b (SPI Variant) or GAIN

pin to Hi-Z (HW Variant)

1

2

V/A

CSA_GAIN = 11b (SPI Variant) or GAIN

pin tied to AVDD (HW Variant)

G_{CSA_ERR}

Current sense gain error

T_A= 25°C, I_PHASE≤ 2.5 A

T_A= 25°C, 2.5 A < I_PHASE≤ 4 A

T_A= 25°C, 4 A < I_PHASE≤ 5 A

I_PHASE≤ 2.5 A

–3

–3.5

–4.5

–5

3

3.5

4.5

6

%

A

2.5 A < I_PHASE≤ 4 A

4A < I_PHASE≤ 5 A

–5

8

T_J= 25°C

–3

3

Current sense gain error matching

between phases A, B and C

I_MATCH

–5

5

FS_POS

FS_NEG

Full scale positive current measurement

Full scale negative current measurement

5

–5

A

V_REF

0.25

–

V_LINEAR

SOX output voltage linear range

0.25

V

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_J= 25°C, Phase current = 0 A, G_CSA

0.25 V/A

=

–100

100

50

mA

T_J= 25°C, Phase current = 0 A, G_CSA

0.5 V/A

–50

–30

Current sense offset low side current

input (Room Temperature)

I_{OFFSET_RT}

T_J= 25°C, Phase current = 0 A, G_CSA

1 V/A

30

T_J= 25°C, Phase current = 0 A, G_CSA

2 V/A

30

Phase current = 0 A, G_CSA= 0.25 V/A

Phase current = 0 A, G_CSA= 0.5 V/A

Phase current = 0 A, G_CSA= 1 V/A

Phase current = 0 A, G_CSA= 2 V/A

–140

–70

–50

140

70

50

1

mA

μs

Current sense offset low side current

input

I_OFFSET

Step on SOX = 1.2 V, G_CSA= 0.25 V/A

Step on SOX = 1.2 V, G_CSA= 0.5 V/A

Step on SOX = 1.2 V, G_CSA= 1 V/A

Step on SOX = 1.2 V, G_CSA= 2 V/A

Phase current = 0 A

1

μs

t_SET

Settling time to ±1%, 30 pF

1

μs

1

μs

V_DRIFT

Drift offset

–360

360 µA/℃

20 µA

I_CSAREF

CSAREF input current

VREF = 3.0 V

12

10

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PROTECTION CIRCUITS

VM rising

VM falling

21

20

22

21

23

22

V

V_OVP

Supply overvoltage protection (OVP)

V_{OVP_HYS}

t_OVP

Supply overvoltage protection hysteresis Falling to rising threshold

900

1000

1200

mV

Supply overvoltage protection deglitch

time

3

5

7

µs

VM rising

Supply undervoltage lockout (UVLO)

VM falling

4.25

4.1

4.4

4.2

4.61

4.35

350

V

V_UVLO

V_{UVLO_HYS}Supply undervoltage lockout hysteresis Rising to falling threshold

140

210

mV

Supply undervoltage lockout deglitch

time

t_UVLO

3

5

7

µs

VM rising, VMUV_WARN_RISE = 0000b

5.4

6

5.62

6.25

6.87

7.5

6

6.6

V

VM rising, VMUV_WARN_RISE = 0001b

VM rising, VMUV_WARN_RISE = 0010b

VM rising, VMUV_WARN_RISE = 0011b

VM rising, VMUV_WARN_RISE = 0100b

VM rising, VMUV_WARN_RISE = 0101b

VM rising, VMUV_WARN_RISE = 0110b

VM rising, VMUV_WARN_RISE = 0111b

VM rising, VMUV_WARN_RISE = 1000b

VM rising, VMUV_WARN_RISE = 1001b

VM rising, VMUV_WARN_RISE = 1010b

VM rising, VMUV_WARN_RISE = 1011b

VM rising, VMUV_WARN_RISE = 1100b

VM rising, VMUV_WARN_RISE = 1101b

VM rising, VMUV_WARN_RISE = 1110b

VM rising, VMUV_WARN_RISE = 1111b

6.6

7.25

7.95

8.6

7.15

7.8

8.12

8.75

9.37

10

8.4

9.3

9

9.9

9.6

10.6

11.2

11.9

12.55

13.15

14.5

15.9

17.1

18.6

V_{VMUV_WARN}Supply (VM) undervoltage warning,

rising

_RISE

10.2

10.8

11.35

11.95

13.2

14.3

15.5

16.7

10.62

11.25

11.87

12.5

13.75

15.00

16.25

17.5

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VM falling, VMUV_WARN_FALL =

0000b

5.1

5.4

5.75

6.3

V

VM falling, VMUV_WARN_FALL =

0001b

5.7

6.0

VM falling, VMUV_WARN_FALL =

0010b

6.25

6.8

6.6

7.2

7.8

6.95

7.6

V

VM falling, VMUV_WARN_FALL = 0011b

VM falling, VMUV_WARN_FALL =

0100b

7.4

8.2

VM falling VMUV_WARN_FALL = 0101b

VM falling, VMUV_WARN_FALL = 0110b

VM falling, VMUV_WARN_FALL = 0111b

7.95

8.5

8.4

9.0

9.6

8.85

9.5

V

V_{VMUV_WARN}Supply (VM) undervoltage warning,

9.05

10.15

falling

_FALL

VM falling, VMUV_WARN_FALL =

1000b

9.7

10.15

10.75

10.2

10.8

11.4

10.7

11.4

12

V

VM falling, VMUV_WARN_FALL =

1001b

VM falling, VMUV_WARN_FALL =

1010b

VM falling, VMUV_WARN_FALL = 1011b

VM falling, VMUV_WARN_FALL = 1100b

VM falling, VMUV_WARN_FALL = 1101b

VM falling, VMUV_WARN_FALL = 1110b

VM falling, VMUV_WARN_FALL = 1111b

VMUV_TDG = 00b

11.3

12.5

13.5

14.7

15.9

0.1

12.0

13.2

14.4

15.6

16.8

0.3

12.6

13.8

15.3

16.4

17.8

0.45

0.8

V

µs

VMUV_TDG = 01b

0.35

0.55

1.4

0.6

t_{VMUV_WARN_}Supply undervoltage warning deglitch

time

DG

VMUV_TDG = 10b

0.9

1.35

2.5

VMUV_TDG = 11b

2

t_{VMUV_WARN_}Supply undervoltage warning deglitch

0.35

0.6

0.8

µs

time (HW variant)

DG

VIN_AVDD rising

VIN_AVDD falling

4.25

4.1

4.4

4.2

4.61

4.35

V

V_{VIN_AVDD_U}AVDD supply input undervoltage lockout

(VIN_AVDD_UV)

V

V_{VIN_AVDD_U}

Supply undervoltage lockout hysteresis Rising to falling threshold

140

210

350

mV

V_HYS

Supply rising

Supply falling

2.64

2.35

2.8

2.6

2.95

2.7

V

Charge pump undervoltage lockout

(above VM)

V_CPUV

Charge pump undervoltage lockout

hysteresis

V_{CPUV_HYS}

t_CPUV

Rising to falling threshold

160

3

210

5

245

7

mV

µs

Charge pump undervoltage lockout

deglitch time

Supply rising

Supply falling

2.7

2.6

2.8

2.7

2.9

2.8

V

V_{AVDD_UV}

Analog regulator undervoltage lockout

V_{AVDD_UV_H}Analog regulator undervoltage lockout

Rising to falling threshold

80

100

150

mV

hysteresis

YS

I_OCP

Overcurrent protection trip point

6

0.15

0.45

0.7

9.5

0.3

0.7

1

12

0.45

0.85

1.25

1.5

A

OCP_TBLANK = 00b

OCP_TBLANK = 01b

OCP_TBLANK = 10b

µs

(1)

t_BLANK

Overcurrent protection blanking time

0.9

1.2

Overcurrent protection blanking time

(HW Variant)

t_BLANK

0.45

0.7

0.85

µs

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

0.3

0.6

0.9

1.2

MAX UNIT

OCP_DEG = 00b

0.1

0.45

0.85

1.25

1.5

µs

OCP_DEG = 01b

OCP_DEG = 10b

OCP_DEG = 11b

0.35

0.6

(1)

t_OCP

Overcurrent protection deglitch time

0.8

Overcurrent protection deglitch time (HW

Variant)

t_OCP

0.35

0.6

0.85

µs

FAST_TRETRY = 00b

FAST_TRETRY = 01b

FAST_TRETRY = 10b

FAST_TRETRY = 11b

SLOW_TRETRY = 00b

SLOW_TRETRY = 01b

SLOW_TRETRY = 10b

SLOW_TRETRY = 11b

0.35

0.75

1.65

4.35

350

0.5

1

0.7

1.3

ms

t_RETRY

Overcurrent protection retry time

2

2.45

5.85

700

5

500

1000

2000

5000

750

1300

2450

5850

t_RETRY

1650

4350

Overcurrent protection retry time (HW

Variant)

t_RETRY

4.35

110

15

5

125

20

5.85

140

25

ms

°C

Overtemperature warning threshold

(FET)

T_{OTW_FET}

Die temperature (T_J) Rising

Die temperature (T_J)

T_{OTW_HYS_F}Overtemperature warning hysteresis

(FET)

ET

Overtemperature shutdown threshold

T_{OTS_FET}

(FET)

Die temperature (T_J) Rising

Die temperature (T_J)

145

14

160

20

175

25

T_{OTS_HYS_FE}Overtemperature shutdown hysteresis

(FET)

T

Overtemperature shutdown threshold

T_{OTS_LDO}

(LDO)

Die temperature (T_J) Rising

Die temperature (T_J)

145

14

160

20

175

25

T_{OTS_HYS_LD}Overtemperature shutdown hysteresis

(LDO)

O

LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP, SCLK, SDI)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

nSLEEP

0

0.7

0.65

5.5

V

V_IL

SDI, INLx, INHx, SCLK

nSLEEP

V_IH

1.7

1.5

200

V

V_IH

SDI, INLx, INHx, SCLK

nSLEEP

3.6

V

V_HYS

600

500

mV

SDI, INLx, INHx, SCLK

nSLEEP, SDI, INLx, INHx, SCLK (Pin

Voltage) = 0 V

I_IL

Input logic low current

–1

1

40

30

µA

nSLEEP (Pin Voltage) = 5V

I_IH

Input logic high current

Other pins, 3V ≤ V_PIN(Pin Voltage) ≤

3.6V

nSLEEP

150

30

300

kΩ

pF

R_PD

C_ID

Input pulldown resistance

Input capacitance

SDI, SCLK, INHx, INLx

nSLEEP, SDI, SCLK, INHx, INLx

LOGIC-LEVEL INPUTS (nSCS)

V_IL

V_IH

V_HYS

I_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

Input logic high current

0

1.5

0.7

3.6

500

95

V

200

mV

µA

V_PIN(Pin Voltage) = 0 V

I_IH

3V ≤ V_PIN(Pin Voltage) ≤ 3.6V

-1

1

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T_J= –40°C to +150°C, V_VM= 4.5 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

Input pullup resistance

Input capacitance

TEST CONDITIONS

MIN

TYP

MAX UNIT

R_PU

C_ID

35

48

75

kΩ

pF

30

OPEN-DRAIN OUTPUTS (nFAULT)

V_OL

I_OH

Output logic low voltage

Output logic high current

Output capacitance

I_OD= -5 mA

0.4

1

V

3V ≤ V_OD≤ 3.6 V

–1

0

µA

pF

C_OD

30

PUSH-PULL OUTPUTS (SDO)

V_OL

V_OH

Output logic low voltage

I_OP= -5 mA, 3V ≤ V_AVDD≤ 3.6V

I_OP= 5 mA, 3V ≤ V_AVDD≤ 3.6V

0.5

3.6

V

V_AVDD

-

Output logic high voltage

0.5

I_OL

Output logic low current

Output logic high current

Output capacitance

V_OP= 0 V

V_OP= 5 V

–1

–2

1

2

µA

pF

I_OH

C_OD

30

(1) (t_OCP+ t_BLANK) must not exceed 2.2 µs

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8 Detailed Description

8.1 Overview

The DRV8317 is an integrated MOSFET driver for 3-phase motor-drive applications. The combined high-side

and low-side FETs' on-state resistance is 130-mΩ (typical). The device reduces system component count, cost,

and complexity by integrating three MOSFET half-bridges, gate drivers, charge pump, current sense amplifiers

and linear regulator for external loads. In DRV8317S, a standard serial peripheral interface (SPI) provides

a simple method for configuring the various device settings and reading fault status information through an

external controller. In DRV8317H, a hardware (pin-based) interface allows configuring the PWM mode (6x or 3x),

current sense amplifier gain and output slew rate through pin voltage levels.

The gate driver architecture is designed to protect against short-circuit events and dV/dt parasitic turn-on of the

internal power MOSFETs.

The DRV8317 integrates three bi-directional low-side current sense amplifiers for monitoring the current through

each of the half-bridges using a built-in current sense circuit; no external current sense resistors are needed.

The gain of the current sense amplifiers can be adjusted through the SPI or hardware interface.

In addition to the high level of device integration, the DRV8317 provides a wide range of integrated protection

features. These features include power supply undervoltage lockout (UVLO), over voltage protection (OVP),

charge pump undervoltage lockout (CPUV), over current protection (OCP), AVDD under voltage lockout

(AVDD_UV) and over temperature warning and shutdown (OTW and OTS). Fault events are indicated by the

nFAULT pin with detailed information available in the status registers in the SPI variant.

The DRV8317S, DRV8317H devices are available in 0.4-mm pin pitch, WQFN surface-mount packages. The

WQFN package size is 5.00-mm × 4.00-mm with a height of 0.8-mm.

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8.2 Functional Block Diagram

VM

+

C_CP

CP

C_VM1

C_VM2

VM

CPH

CPL

I/O Control

Protection

LS Predriver Power

Supply Regulator

Charge Pump

C_FLY

Overcurrent

Protection

nSLEEP

VM, AVDD, CP,

VIN_AVDD UVLO

Protection

VIN_AVDD

VLS

INHA

INLA

VM Overvoltage

Protection

C_{VIN_AVDD1}

C_{VIN_AVDD2}

Regulator

AVDD

VM Undervoltage

Warning

Ext.

Load

C_AVDD

AVDD Linear Regulator

AGND

Thermal Warning

Thermal Shutdown

INHB

Input

Control

INLB

Predriver Stage

CP

Power Stage

VM

INHC

HS Pre-

driver

INLC

OUTA

AVDD

VLS

R_nFAULT

LS Pre-

driver

Output

Current

Sense for

Phase - A

nFAULT

PGND

ISEN_A

Digital Control

Predriver Stage

CP

Power Stage

VM

Interface

SCLK

HS Pre-

driver

SPI

OUTB

SDI

AVDD

VLS

LS Pre-

driver

SDO

Current

Sense for

Phase - B

AVDD

PGND

nSCS

ISEN_B

Predriver Stage

CP

Power Stage

VM

CSAREF

C_CSAREF

Current Sense Amplifiers

HS Pre-

driver

ISEN_A

A_V

OUTC

SOC

SOB

SOA

VLS

ISEN_B

ISEN_C

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

Thermal PAD

PGND

Figure 8-1. DRV8317S Functional Block Diagram

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VM

+

C_CP

CP

C_VM1

C_VM2

VM

CPH

I/O Control

Protection

LS Predriver Power

Supply Regulator

C_FLY

Charge Pump

Overcurrent

Protection

CPL

VM, AVDD, CP,

VIN_AVDD UVLO

Protection

VIN_AVDD

VLS

nSLEEP

C_{VIN_AVDD1}

C_{VIN_AVDD2}

VM Overvoltage

Protection

Regulator

AVDD

AGND

INHA

INLA

INHB

INLB

INHC

Ext.

Load

VM Undervoltage

Warning

C_AVDD

AVDD Linear Regulator

Thermal Warning

Thermal Shutdown

Predriver Stage

CP

Power Stage

VM

HS Pre-

driver

Input

Control

OUTA

INLC

VLS

LS Pre-

driver

Current

Sense for

Phase - A

MODE

SLEW

GAIN

PGND

ISEN_A

Digital Control

Predriver Stage

CP

Power Stage

VM

HS Pre-

driver

OUTB

AVDD

VLS

R_nFAULT

Output

LS Pre-

driver

Current

Sense for

Phase - B

nFAULT

PGND

ISEN_B

Predriver Stage

CP

Power Stage

VM

CSAREF

C_CSAREF

Current Sense Amplifiers

HS Pre-

driver

ISEN_A

A_V

OUTC

SOC

SOB

SOA

VLS

ISEN_B

ISEN_C

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

PGND

Thermal PAD

Figure 8-2. DRV8317H Functional Block Diagram

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8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the driver.

Table 8-1. DRV8317 External Components

COMPONENTS

C_VM1

PIN 1

VM

PIN 2

PGND

AGND

CPL

RECOMMENDED

X5R or X7R, 0.1-µF, (2 x VM)-rated capacitor

≥ 10-µF, (2 x VM)-rated electrolytic capacitor

X5R or X7R, 0.1-µF, (2 x VIN_AVDD)-rated capacitor

≥ 10-µF, (2 x VIN_AVDD)-rated capacitor

X5R or X7R, 0.1-µF, (2 x VM)-rated capacitor

X5R or X7R, 16-V, 1-µF capacitor

C_VM2

VM

C_{VIN_AVDD1}

C_{VIN_AVDD2}

C_FLY

VIN_AVDD

CPH

C_CP

CP

VM

X5R or X7R, 2.2-µF (no external load) 4.7-µF (up to

80mA load), 6.3-V capacitor

C_AVDD

AVDD

AGND

R_nFAULT

R_MODE

R_SLEW

AVDD

MODE

SLEW

nFAULT

AGND

5.1-kΩ, Pull-up resistor

Section 8.3.3.2

R_GAIN

GAIN

Section 8.3.3.2

C_CSAREF

CSAREF

X5R or X7R, 0.1-µF, (2 x CSAREF)-rated capacitor

8.3.1 Output Stage

The DRV8317 consists of integrated N-channel FETs (high-side and low-side) connected in a three-phase bridge

configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side N-channel FETs

across a wide operating (VM) voltage range in addition to providing 100% duty-cycle support. An internal linear

regulator operating from the VM supply provides the gate-bias voltage (VLS) for the low-side N-channel FETs.

8.3.2 Control Modes

The DRV8317 family of devices provides three different control modes to support various commutation and

control methods. Table 8-2 shows the various modes of the DRV8317 device.

Table 8-2. PWM Control Modes

PWM_MODE register

PWM Control Mode

MODE Pin (DRV8317H)

(DRV8317S)

MODE pin tied to AGND

directly or tied to AGND via

47-kΩ resistor

6x PWM

PWM_MODE = 00b

6x direct PWM

3x PWM

PWM_MODE = 01b

PWM_MODE = 10b

PWM_MODE = 11b

Not Available

MODE pin floating (Hi-Z) or

tied to AVDD

3x direct PWM

Not Available

The difference between 6x PWM (or 3x PWM) and 6x direct PWM (or 3x direct PWM) is that in the direct (6x

or 3x) PWM mode, the delay compensation logic circuit is bypassed and the inputs at INHx, INLx are directly

passed on to the gate driver circuit. In the gate driver circuit, a dead time (t_{DRV_DEAD}) is added before driving the

FETs to prevent shoot through faults - this dead time is available in all the four PWM control modes.

Note

TI does not recommend changing the MODE pin or PWM_MODE register during power up of the

device (during t_WAKE). The MODE pin setting on DRV8317H is latched at power up, so set nSLEEP

= 0 before changing the MODE pin configuration on the DRV8317H. In DRV8317S, set all INHx and

INLx pins to logic low before changing the PWM_MODE register.

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8.3.2.1 6x PWM Mode

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). To

configure DRV8317H in 6x PWM mode, connect the MODE pin to AGND or connect the MODE pin to AGND

via 47-kΩ resistor. To enable 6x PWM mode in DRV8317S, configure the MODE bits with PWM_MODE = 00b or

01b. The corresponding INHx and INLx signals control the output state as listed in Table 8-3.

Table 8-3. 6x PWM Mode Truth Table

INHx

INLx

OUTx

Hi-Z

L

0

1

0

1

0

1

H

Hi-Z

Figure 8-3 shows the application diagram of DRV8317 configured in 6x PWM mode.

VM

OUTA

nSLEEP

INHA

VM

INLA

INHB

Controller

INLB

INHC

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

OUTC

PGND

Figure 8-3. 6x PWM Mode

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8.3.2.2 3x PWM Mode

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. To

configure DRV8317H in 3x PWM mode, connect the MODE pin to AVDD or keep the MODE pin floating (Hi-Z).

To enable 3x PWM mode in DRV8317S, set PWM_MODE to 10b or 11b. The INLx pin is used to put the half

bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high (for example, by tying them

to AVDD). The corresponding INHx and INLx signals control the output state as listed in Table 8-4.

Table 8-4. 3x PWM Mode Truth Table

INLx

INHx

OUTx

Hi-Z

L

0

1

X

0

1

H

Figure 8-4 shows the typical application diagram of the DRV8317 configured in 3x PWM mode.

VM

OUTA

nSLEEP

INHA

VM

INHB

INHC

Controller

INLA

INLB

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

AVDD

OUTC

PGND

Figure 8-4. 3x PWM Mode

8.3.3 Device Interface Modes

The DRV8317 family of devices supports two different interface modes (SPI and hardware) to offer either

increased simplicity (hardware interface) or greater flexibility (SPI interface). The SPI (DRV8317S) and hardware

(DRV8317H) interface modes share the same four pins, allowing the different versions to be pin-to-pin

compatible. Designers are encouraged to evaluate with the SPI interface version due to ease of changing

settings, and may consider switching to the hardware interface with minimal modifications to the design.

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8.3.3.1 Serial Peripheral Interface (SPI)

The SPI variant (DRV8317S) supports a serial communication bus that allows an external controller to send and

receive data with DRV8317. This enables the external controller to configure device settings and read detailed

fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

•

The SCLK (serial clock) pin is an input that accepts a clock signal to determine when data is captured and

propagated on the SDI and SDO pins.

•

The SDI (serial data in) pin is the data input.

The SDO (serial data out) pin is the data output.

The nSCS (serial chip select) pin is the chip select input. A logic low signal on this pin enables SPI

communication with the DRV8317.

For more information on the SPI, see Section 8.5.

8.3.3.2 Hardware Interface

The hardware variant (DRV8317H) replaces the four SPI pins with three resistor-configurable pins, namely,

GAIN, SLEW and MODE (one of the four SPI pins is NC in hardware variant).

PWM control mode, CSA gain and driver output slew rate can be adjusted on the hardware interface by tying

the respective pins to AGND, AVDD, pulling down to AGND with a 47-kΩ resistor or by leaving the pin floating

(Hi-Z). In DRV8317H, fault conditions are reported on the nFAULT pin, but detailed fault information is not

available.

•

The GAIN pin configures the gain of the current sense amplifier.

The SLEW pin configures the slew rate of the output voltage to motor.

The MODE pin configures the PWM control mode.

For more information on the hardware interface, see Section 8.3.9.

Table 8-5. Hardware Pins Decode

Configuration

Pin tied to AGND

GAIN

0.25-V/A

0.5-V/A

1-V/A

SLEW

25-V/µs

50-V/µs

125-V/µs

200-V/µs

MODE

6x PWM mode

3x PWM mode

Pin pulled to AGND via 47-kΩ

Pin floating (Hi-Z)

Pin tied to AVDD

2-V/A

AVDD

SPI

Interface

SLEW

MODE

SCLK

SDI

47-k

AVDD

Hardware

Interface

SDO

nSCS

AVDD

GAIN

Figure 8-5. DRV8317S SPI Interface

8.3.4 AVDD Linear Voltage Regulator

Figure 8-6. DRV8317H Hardware Interface

A 3.3-V, 80mA linear regulator is integrated in the DRV8317 and is available to power external circuits. The

AVDD regulator is used for powering up the internal circuits of DRV8317 and can also provide power to external

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circuits like MCU, logic, hall sensors, LEDs for up to 80 mA. The output of the AVDD regulator should be

bypassed near the AVDD pin with a X5R or X7R, up to 7.05µF (4.7µF typical), 6.3-V ceramic capacitor routed

directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3 V.

VIN_AVDD

REF

+

œ

AVDD

AGND

External Load

C_AVDD

Figure 8-7. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator.

P = (V_{VIN_AVDD}- V_AVDD) x I_AVDD

(1)

The supply input voltage for AVDD regulator (VIN_AVDD) can be same as VM supply voltage, or lower or higher

than VM supply voltage.

8.3.5 Charge Pump

The DRV8317 requires a gate-drive voltage higher than the VM power supply to enhance the high-side FETs

fully because the output stages uses N-channel FETs for both high-side and low-side. The DRV8317 integrates a

charge pump circuit that generates a voltage above the VM supply for this purpose.

The charge pump requires two external capacitors for operation. See Table 8-1 for details on the capacitor value.

The charge pump shuts down when nSLEEP is low.

VM

C_CP

CP

CPH

VM

Charge

Pump

C_FLY

Control

CPL

Figure 8-8. DRV8317 Charge Pump

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8.3.6 Slew Rate Control

An adjustable gate-drive current to the MOSFETs allows for driver output slew rate control. The MOSFET VDS

slew rate is a critical factor in optimizing radiated emissions, energy and duration of diode recovery spikes and

switching voltage transients related to parasitics. This slew rate is predominantly determined by the rate of gate

charge to the MOSFETs as shown in Figure 8-9.

VM

CP

Slew Rate

Control

OUTx

VLS

Slew Rate

Control

PGND

Figure 8-9. Slew Rate Control

The slew rate of each half-bridge can be adjusted by SLEW pin in hardware variant or by SLEW_RATE register

in SPI variant. The slew rate is calculated by the rise-time and fall-time of the voltage on OUTx pin as shown in

Figure 8-10.

V_OUTx

VM

80%

20%

0

Time

t_fall

t_rise

Figure 8-10. Slew Rate Measurement

8.3.7 Cross Conduction (Dead Time)

The device is fully protected against any cross conduction of MOSFETs - during the switching of high-side and

low-side MOSFETs, DRV8317 avoids shoot-through events by inserting a dead time (t_dead). This is implemented

by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring that VGS

of high-side MOSFET has dropped below turn-off level before switching on the low-side MOSFET of same

half-bridge (or vice-versa) as shown in Figure 8-11 and Figure 8-12. The VGS of the high-side and low-side

MOSFETs (VGS_HS and VGS_LS) shown in Figure 8-12 are DRV8317 internal signals.

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VM

HS Gate

Control

+

VGS_HS

–

OUTx

LS Gate

Control

+

GND

VGS_LS

–

Figure 8-11. Cross Conduction Protection

VGS_HS

10%

t_DEAD

VGS_LS

10%

Time

Figure 8-12. Dead Time

8.3.8 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to change in OUTx

voltage. The propagation delay time includes the input deglitch delay, analog driver delay, and depends on the

slew rate setting . The input deglitcher prevents high-frequency noise on the input pins from affecting the output

state of the gate drivers. To support multiple control modes, a small digital delay is added as the input command

propagates through the device.

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INx

OUTx High

t_PD

10%

OUTx Low

OUTx

Time

Figure 8-13. Propagation Delay

8.3.9 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

8.3.9.1 Logic Level Input Pin (Internal Pulldown)

Figure 8-14 shows the input structure for the logic levels pins INHx, INLx, nSLEEP, SCLK and SDI. The input

can be driven with an external resistor to GND or an external logic voltage supply. It is recommended to pull

these pins low in device sleep mode to reduce leakage current through the internal pull-down resistors.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

Logic High

Logic Low

V_IL

R_PD

ESD

Figure 8-14. Logic-Level Input Pin Structure

8.3.9.2 Logic Level Input Pin (Internal Pullup)

Figure 8-15 shows the input structure for the logic level pin nSCS. The input can be driven with an external

resistor to GND or an external logic voltage supply .

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

R_PU

Logic High

Logic Low

V_IL

ESD

Figure 8-15. nSCS Input Pin Structure

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8.3.9.3 Open Drain Pin

Figure 8-16 shows the structure of the open-drain output pin nFAULT. The open-drain output requires an external

pullup resistor to a logic voltage supply to function properly.

AVDD

STATE

No Fault

Fault

STATUS

Pulled-Up

R_PU

OUTPUT

Inactive

Active

Pulled-Down

ESD

Figure 8-16. Open Drain Output Pin Structure

8.3.9.4 Push Pull Pin

Figure 8-17 shows the structure of the push-pull pin SDO.

AVDD

STATE

V_OH

STATUS

Pulled-Up

Pulled-Down

Open

OUTPUT

Logic High

Logic Low

Hi-Z

V_OL

ESD

Hi-Z

Figure 8-17. Push-Pull Output Pin Structure

8.3.9.5 Four Level Input Pin

Figure 8-18 shows the structure of the four level input pins GAIN, MODE and SLEW on hardware interface

devices. The input can be set by tying the pin to AGND or AVDD, leaving the pin unconnected, or connecting an

external resistor from the pin to ground.

CONTROL

AVDD

STATE

V_L1

RESISTANCE

Tied to AGND

Setting-1

Setting-2

Setting-3

Setting-4

+

–

R_PU

47 k ±5%

to AGND

V_L2

V_L3

V_L4

+

–

R_PD

Hi-Z

Tied to AVDD

+

–

Figure 8-18. Four Level Input Pin Structure

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8.3.10 Current Sense Amplifiers

The DRV8317 integrates three high-performance low-side current sense amplifiers for current measurements

using built-in current sense. Low-side current measurements are commonly used to implement overcurrent

protection, external torque control, or brushless DC commutation with the external controller. Each amplifier

senses the current in the corresponding half-bridge when the low-side MOSFET is conducting. The current

sense amplifiers include features such as configurable gain (through CSA_GAIN register or GAIN pin) and an

external voltage reference (VREF) provided through CSAREF pin.

8.3.10.1 Current Sense Amplifier Operation

The SOx pin on the DRV8317 provides an analog voltage proportional to the current flowing in the low side

MOSFETs (I_OUTx) multiplied by the gain setting (G_CSA) of the current sense amplifier. The gain setting is

adjustable between four different levels which can be set by the GAIN pin (hardware variant) or the CSA_GAIN

register (SPI variant).

Figure 8-19 shows the internal architecture of the current sense amplifiers. The current sense is implemented

with a sense FET on each low-side FET of the DRV8317 device. This current information is converted in to a

voltage based on the CSAREF pin (VREF) input and the CSA gain setting; this voltage is available on the SOx

pin. The CSA output voltage can be calculated using Equation 2

SOx = V_REF/2 + (G_CSA* I_OUTx), wherein I_OUTxis considered positive in the direction shown in Figure 8-19.

(2)

VM

VREF

OUTx

Sense

FET

GAIN

I/V Converter

PGND

SOx

Figure 8-19. Integrated Current Sense Amplifier

Figure 8-20 shows the I_OUTxto CSA output transfer function. In bi-directional operation, the amplifier output for

0-A input is set at VREF/2. Any change in the output phase current results in a corresponding change in the

amplifier output as given in Equation 2.

SOX (V)

V_REF

(V_REF- 0.25)

V_REF/ 2

V_LINEAR

0.25-V

0-V

I_OUTx(A) (Current flowing out of OUTx)

Figure 8-20. IOUTx to CSA Transfer Function

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The amplifier has a defined linear region as shown in Figure 8-21.

SOX

V_REF

(V_REF– 0.25) V

I_OUTx

V

SOX(range+)

V

SOX(off)max

V_REF/2

V

, V

OFF DRIFT

0-A

V

SOX(off)min

V

SOX(range-)

-I_OUTx

0.25-V

0-V

Figure 8-21. Bi-directional Current Sense Linear Region

Note

The current sense amplifiers use the external voltage reference (VREF) provided at the CSAREF pin.

8.3.11 Protections

The DRV8317 is protected against VM, VIN_AVDD, AVDD, CP under voltage, VM over voltage, SPI fault, OTP

read fault, FET over current and FET, LDO over temperature events. Table 8-6 summarizes various fault details.

Table 8-6. Fault Action and Response

FAULT STATUS

FAULT

CONDITION

CONFIGURATION

REPORT

PRE-DRIVER

DIGITAL

RECOVERY

BITS

Automatic:

UVP_MODE = 00b

nFAULT

Hi-Z

Latched

Active

SLOW_TRETRY and V_VM> V_UVLO

(rising)

VM under voltage

lockout (VM_UV)

V_VM< V_{UVLO (falling)}

Automatic:

UVP_MODE = 01b

nFAULT

Hi-Z

Latched

Active

FAST_TRETRY and V_VM> V_UVLO

(rising)

Automatic:

VMUV_WARN_MODE

= 00b

SLOW_TRETRY and V_VM

V_{VMUV_WARN_RISE}

>

Automatic:

FAST_TRETRY and V_VM

V_{VMUV_WARN_RISE}

VMUV_WARN_MODE

= 01b

VM under voltage

warning

(VMUV_WARN)

>

V_VM

<

V_{VMUV_WARN_FALL}

VMUV_WARN_MODE

= 10b

nFAULT

—

Active

Latched

—

Active

No action; report only mode

—

VMUV_WARN_MODE

= 11b

VIN_AVDD under

voltage

(VIN_AVDD_UV)

V_{VIN_AVDD}

V_{VIN_AVDD_UV (falling)}

<

Automatic: V_{VIN_AVDD}> V_{VIN_AVDD_UV}

—

Hi-Z

—

Reset

Active

(rising)

AVDD under

voltage

(AVDD_UV)

V_AVDD< V_{AVDD_UV}

—

Automatic: V_AVDD> V_{AVDD_UV (rising)}

(falling)

Automatic:

SLOW_TRETRY and V_CP> V_CPUV

UVP_MODE = 00b

UVP_MODE = 01b

nFAULT

Latched

Charge pump

under voltage

(CP_UV)

(rising)

V_CP< V_{CPUV (falling)}

Automatic:

FAST_TRETRY and V_CP> V_CPUV

(rising)

Automatic:

SLOW_TRETRY

OCP_MODE = 000b

OCP_MODE = 001b

nFAULT

Hi-Z

Latched

Active

Automatic:

FAST_TRETRY

Over current

protection

(OCP)

I_PHASE> I_OCP

Latched:

Cleared by FLT_CLR bit or nSLEEP

reset pulse

OCP_MODE = 010b

OCP_MODE = 011b

nFAULT

Hi-Z

Latched

Active

No action; report only mode

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Table 8-6. Fault Action and Response (continued)

FAULT STATUS

FAULT

CONDITION

CONFIGURATION

REPORT

PRE-DRIVER

DIGITAL

RECOVERY

BITS

Automatic:

OVP_MODE = 00b

nFAULT

Hi-Z

Latched

Active

SLOW_TRETRY and V_VM< V_OVP

VM over voltage

protection

(VM_OV)

(falling)

V_VM> V_{OVP (rising)}

Automatic:

FAST_TRETRY and V_VM< V_OVP

OVP_MODE = 01b

nFAULT

Hi-Z

Latched

Active

(falling)

SPIFLT_MODE = 0b

SPIFLT_MODE = 1b

nFAULT

—

Active

Latched

—

Active

No action; report only mode

SPI fault

(SPIFLT)

SCLK fault and ADDR

fault

—

System (OTP

read)

(SYSFLT)

Latched:

Cleared by FLT_CLR bit or nSLEEP

reset pulse

OTP read parity fault

—

nFAULT

Disabled

Hi-Z

Latched

Active

Automatic:

SLOW_TRETRY and T_J< T_{OTW_FET}

- T_{OTW_FET_HYS}

OTF_MODE = 00b

OTF_MODE = 01b

OTF_MODE = 00b

OTF_MODE = 01b

FET over

temperature

warning

T_J> T_{OTW_FET}

Automatic:

(OTW_FET)

Hi-Z

FAST_TRETRY and T_J< T_{OTW_FET}

T_{OTW_FET_HYS}

-

Automatic:

SLOW_TRETRY and T_J< T_{OTS_FET}

T_{OTS_FET_HYS}

Hi-Z

-

FET over

temperature

shutdown

T_J> T_{OTS_FET}

Automatic:

FAST_TRETRY and T_J< T_{OTS_FET}

T_{OTS_FET_HYS}

(OTS_FET)

Hi-Z

-

AVDD LDO over

temperature

shutdown

Automatic:

T_J< T_{OTS_LDO}- T_{OTS_LDO_HYS}

T_J> T_{OTS_LDO}

—

Hi-Z

—

Reset

(OTS_LDO)

8.3.11.1 Under Voltage Protection (UVP)

DRV8317 has under voltage protection enabled for VM, VIN_AVDD, AVDD and CP voltage rails - these fault

protections cannot be disabled. VM, VIN_AVDD and AVDD under voltage faults result in device reset; CP under

voltage fault response is user configurable through UVP mode.

VM, VIN_AVDD, AVDD Under Voltage Protection (VIN_AVDD_UV, AVDD_UV)

If at any time, the voltage on VIN_AVDD or AVDD pin falls below the corresponding under voltage falling

threshold (V_{VINAVDD_UV}or V_{AVDD_UV}), DRV8317 enters reset - in reset, FETs are in Hi-Z, pre-driver, charge

pump, current sense amplifier and digital logic are disabled. Normal device operation resumes automatically

after the respective rail voltage rises above the corresponding under voltage rising threshold (V_{VINAVDD_UV}or

V_{AVDD_UV}) as shown in Figure 8-22.

V_{VIN_AVDD}, V_AVDD

V_UV(max) rising

V_UV(min) rising

V_UV(max) falling

V_UV(min) falling

DEVICE ON

DEVICE RESET

DEVICE ON

Time

Figure 8-22. VIN_AVDD, AVDD Under Voltage Protection

VM, CP Under Voltage Protection (VM_UV, CP_UV)

If at any time the voltage on VM or CP pin falls below the corresponding under voltage falling threshold (V_{VM_UV}

or V_{CP_UV}), FETs are in Hi-Z, charge pump is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS

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and VM_UV or CP_UV in SUP_STS are set to 1b. Normal operation resumes automatically (pre-driver, charge

pump operation and the nFAULT pin is released) once the retry time (t_RETRY) lapses after VM or CP voltage

is above the corresponding under voltage rising threshold (V_{VM_UV}or V_{CP_UV}) as shown in Figure 8-23. The

FAULT, UVP and UV_UV or CP_UV bits stay set to 1b until a clear fault command is issued either through the

FLT_CLR bit or an nSLEEP reset pulse (t_RST).

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring UVP_MODE to 00b

Fast retry time (FAST_TRETRY) by configuring UVP_MODE to 01b

IN DRV8317H, UVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.

V_VM, V_CP

V_UV(max) rising

V_UV(min) rising

V_UV(max) falling

V_UV(min) falling

t_RETRY

FETs OFF

FETs ON

Time

Figure 8-23. VM, CP Under Voltage Protection

8.3.11.2 VM Under Voltage Warn (VMUV_WARN) Protection

DRV8317 provides user configurable thresholds (V_{VMUV_WARN_FALL}, V_{VMUV_WARN_RISE}) for VM under voltage

warn protection. If at any time, voltage on VM pin falls below the V_{VMUV_WARN_FALL}threshold, action is taken as

per VMUV_WARN_MODE configuration. There are four settings for VMUV_WARN_MODE: automatic retry with

slow and fast retry time, report only and disabled. The threshold for the VM under voltage warn fault condition

to be removed is set by V_{VMUV_WARN_RISE}. This fault can be enabled/ disabled using VMUV_WARN_EN. In

DRV8317H, this fault is enabled by default and set to report only mode (VMUV_WARN_MODE set to 10b).

8.3.11.2.1 VM Under Voltage Warn Automatic Retry (VMUV_WARN_MODE = 00b or 01b)

After a VM under voltage warn event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low.

The FAULT, UVW bits (in DEV_STS register) and VMUV_WARN bit (in SUP_STS register) are set to 1b. Normal

operation resumes automatically (pre-driver operation and the nFAULT pin is released) once the retry time

(t_RETRY) time lapses after the VM pin voltage rises above the V_{VMUV_WARN_RISE}threshold as shown in Figure

8-24. The FAULT, UVW and VMUV_WARN bits stay set to 1b until clear fault command is issued either through

the FLT_CLR bit or an nSLEEP reset pulse (t_RST).

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring VPWR_MODE to 00b

Fast retry time (FAST_TRETRY) by configuring VPWR_MODE to 01b

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V_VM

V_{VMU_WARN_RISE}(max)

V_{VMU_WARN_RISE}(min)

V_{VMU_WARN_FALL}(max)

V_{VMU_WARN_FALL}(min)

t_RETRY

FETs OFF

FETs ON

Time

Figure 8-24. VM Under Voltage Warning

8.3.11.2.2 VM Under Voltage Warn Report Only (VMUV_WARN_MODE = 10b)

No protective action occurs after a VM under voltage warn event in this mode. The VM under voltage warn

event is reported by driving the nFAULT pin low and setting the FAULT, UVW bits (in DEV_STS register) and

VMUV_WARN bit (in SUP_STS register) to 1b. DRV8317 continues to operate as usual. The external controller

manages the VM under voltage warn condition by acting appropriately. The reporting clears (nFAULT pin is

released, FAULT, UVW and VMUV_WARN bits are set to 0b) when a clear fault command is issued either

through the FLT_CLR bit or an nSLEEP reset pulse (t_RST).

8.3.11.2.3 VM Under Voltage Warn Disabled (VMUV_WARN_MODE = 11b)

No action is taken and no reporting (nFAULT pin, status register bits) is done after a VM under voltage warn

event in this mode.

8.3.11.3 Over Current Protection (OCP)

A MOSFET over current event is sensed by monitoring the current flowing through each of the FETs. If the

current through a FET exceeds the OCP threshold (I_OCP) for longer than the OCP deglitch time (t_OCP), an OCP

event is recognized and action is taken according to OCP_MODE. In order to avoid false trigger of OCP at PWM

transitions, due to ringing in the phase voltage, there is a blanking time (t_BLANK) applied after each PWM edge.

During blanking time, OCP events are ignored.

In DRV8317H, the t_OCPis fixed at 0.6-µs (typical), t_BLANKis fixed at 0.7-µs (typical) and the OCP_MODE is set

to 001b with retry time of 5-ms. In DRV8317S, the t_OCPis configured by OCP_DEG, the t_BLANKis configured by

OCP_TBLANK and the OCP_MODE can be configured in four different modes: OCP latched shutdown, OCP

automatic retry with fast and slow retry times and OCP report only.

Note

(t_OCP+ t_BLANK) should not exceed 2-µs

8.3.11.3.1 OCP Latched Fault (OCP_MODE = 010b)

After an OCP event in this mode, all MOSFETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP

bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal

operation resumes (pre-driver operation, FAULT, OCP, corresponding FETs' OCP bits set to 0b and the nFAULT

pin is released) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse

(t_RST).

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Peak current due

to deglitch time

I_OCP

I_OUTx

t_OCP

nFAULT released

nFAULT driven low

nFAULT

CLR_FLT or

nSLEEP reset pulse

Time

Figure 8-25. Over Current Protection - Latched Mode

8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)

After an OCP event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP

bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal

operation resumes automatically (pre-driver operation, the nFAULT pin is released and corresponding FETs'

OCP bits are set to 1b) after the retry time (t_RETRY) time elapses. The FAULT and OCP bits stay set to 1b until

clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (t_RST).

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring OCP_MODE to 000b

Fast retry time (FAST_TRETRY) by configuring OCP_MODE to 001b

Peak current due

to deglitch time

I_OCP

I_OUTx

t_OCP

t_RETRY

nFAULT driven low

nFAULT released

nFAULT

Time

Figure 8-26. Over Current Protection - Automatic Retry Mode

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8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)

No protective action occurs after an OCP event in this mode. The over current event is reported by driving the

nFAULT pin low and setting the FAULT, OCP bits (in DEV_STS register) and corresponding FETs' OCP bits

(in DRV_STS register) to 1b. DRV8317 continues to operate as usual. The external controller manages the

over current condition by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, OCP, and

corresponding FETs' OCP bits are set to 0b) when a clear fault command is issued either through the FLT_CLR

bit or an nSLEEP reset pulse (t_RST).

8.3.11.4 VM Over Voltage Protection (OVP)

If at any time, input supply voltage on the VM pin rises higher than the V_OVPrising threshold, all the integrated

FETs are in Hi-Z, FAULT, OVP bits (in DEV_STS register) and VM_OV (in SUP_STS register) are set to 1b and

the nFAULT pin is driven low. Normal operation resumes automatically (pre-driver operation and the nFAULT pin

is released) once retry time (t_RETRY) lapses after VM pin voltage is below the V_OVPfalling threshold as shown

inFigure 8-27. The FAULT, OVP and VM_OV bits stay set to 1b until clear fault command is issued either through

the FLT_CLR bit or an nSLEEP reset pulse (t_RST).

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring OVP_MODE to 00b

Fast retry time (FAST_TRETRY) by configuring OVP_MODE to 01b

IN DRV8317H, OVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.

V_VM

V_OVP(max) rising

V_OVP(min) rising

V_OVP(max) falling

V_OVP(min) falling

t_RETRY

FETs ON

FETs OFF

FETs ON

nFAULT

Time

Figure 8-27. VM Over Voltage Protection

8.3.11.5 SPI Fault

In the event of a SPI transaction fault (parity, frame or bus contention error), if SPLIFLT_MODE is set to 0b,

nFAULT is driven low, FAULT, SPIFLT bits (in DEV_STS register) and SPI_PARITY/ BUS_CNT/ FRM_ERR bits

(in SYSIF_STS register) are set to 1b. DRV8317 continues to operate as usual. The external controller manages

the SPI fault event by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, SPIFLT, and

SPI_PARITY/ BUS_CNT/ FRM_ERR bits are set to 0b) when a clear fault command is issued either through the

FLT_CLR bit or an nSLEEP reset pulse (t_RST).

If SPIFLT_MODE is set to 1b, SPI fault is disabled and reporting (nFAULT, status register bits) does not happen

on a SPI fault event.

8.3.11.6 System (OTP Read) Fault

DRV8317 loads the configurable register settings from the OTP on every power-up cycle. If an OTP read

fault is encountered while configuring the registers, pre-driver is disabled, FAULT, SYSFLT bits (in DEV_STS

register) and OTPLD_ERR bit (in SYSIF_STS register) are set to 1b and nFAULT is driven low. Normal operation

resumes (pre-driver, FAULT, SYSFLT, OTPLD_ERR bits set to 0b and nFAULT pin is released) when a clear

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fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (t_RST). It is advisable not to

operate DRV8317 by issuing a clear fault command in the event of a OTP read fault since the register settings

may be in an unknown state and may lead to unexpected device operation.

8.3.11.7 Thermal Protection

DRV8317 has over temperature warning (OTW) and over temperature shutdown (OTS) features for protection

against over temperature events. OTW is available for FET protection (OTW_FET) while OTS is available for

FET (OTS_FET) and AVDD LDO (OTS_LDO) protection.

8.3.11.7.1 FET Over Temperature Warning (OTW_FET)

If the FET temperature exceeds the over temperature warning (T_{OTW_FET}) threshold, the FAULT, OTF bits (in

DEV_STS register) and OTW_FET bit (in OT_STS register) are set to 1b and the nFAULT pin is driven low. The

nFAULT pin is released and OTW_FET is set to 0b once retry time (t_RETRY) elapses after the FET temperature

falls below the over temperature warning (T_{OTW_FET}- T_{OTW_FET_HYS}) threshold. The FAULT, OTF bits stay set to

1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring OTF_MODE to 00b

Fast retry time (FAST_TRETRY) by configuring OTF_MODE to 01b

In DRV8317H, FET over temperature warning is disabled.

8.3.11.7.2 FET Over Temperature Shutdown (OTS_FET)

If the FET temperature exceeds the shutdown threshold (T_{OTS_FET}), all the integrated FETs are in Hi-Z, the

FAULT, OTF bits (in DEV_STS register) and OTS_FET bit (in OT_STS register) are set to 1b and the nFAULT

pin is driven low. Normal operation resumes automatically (pre-driver operation, nFAULT pin is released and

OTS_FET is set to 0b) after retry time (t_RETRY) elapses, if FET temperature falls below the over temperature

shutdown (T_{OTS_FET}- T_{OTS_FET_HYS}) threshold. The FAULT, OTF bits stay set to 1b until cleared through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST). This feature cannot be disabled.

Retry time (t_RETRY) is set by,

•

Slow retry time (SLOW_TRETRY) by configuring OTF_MODE to 00b

Fast retry time (FAST_TRETRY) by configuring OTF_MODE to 01b

IN DRV8317H, t_RETRYperiod is fixed at 5-ms.

8.3.11.7.3 LDO Over Temperature Shutdown

If AVDD LDO temperature exceeds the LDO over temperature shutdown (T_{OTS_LDO}) threshold, all the

integrated FETs are in Hi-Z and device enters reset. Normal operation resumes automatically when AVDD

LDO temperature falls below the over temperature shutdown threshold (T_{OTS_LDO}- T_{OTS_LDO_HYS}). This feature

cannot be disabled.

8.4 Device Functional Modes

8.4.1 Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of DRV8317. When the nSLEEP pin is low, the device goes to a low-power

sleep mode. In sleep mode MOSFETs, current sense amplifiers, charge pump, AVDD regulator and SPI bus are

disabled. The t_SLEEPtime must elapse after a falling edge on the nSLEEP pin before the device goes to sleep

mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The t_WAKEtime must

elapse before the device is ready for PWM inputs.

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Note

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low

as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the

t_SLEEPor t_WAKEtime.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the V_VMvoltage is greater than the V_UVLOvoltage, the device goes to

operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the charge

pump, AVDD regulator and SPI bus are active.

8.4.1.3 Fault Reset (FLT_CLR or nSLEEP Reset Pulse)

In the case of latched faults, DRV8317 turns off the MOSFETs (Hi-Z) and the motor coasts to a stop.

When the fault condition clears, the device can go to the operating state again by either setting the FLT_CLR

bit to 1b in the SPI variant or by issuing a reset pulse on the nSLEEP pin in the hardware variant. The nSLEEP

reset pulse (t_RST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence

should fall with the t_RSTtime window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks.

8.5 SPI Communication

8.5.1 Programming

8.5.1.1 SPI Format

SPI Format - with Parity

The SDI input data word is 24 bits long and consists of the following format:

•

1 read or write bit, W (bit B23)

6 address bits, A (bits B22 through B17)

Parity bit, P (bit B16)

15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The most significant bits are status bits and the least significant 16

bits are the data content of the register being accessed.

Table 8-7. SDI Input Data Word Format for SPI

PAR PAR

R/W

ADDRESS

DATA

ITY ITY

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

W0 A5 A4 A3 A2 A1 A0

P

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 8-8. SDO Output Data Word Format

STATUS

DATA

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

S7 S6 S5 S4 S3 S2 S1 S0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

The details of the bits used in SPI frame format are detailed below.

Read/Write Bit (R/W): R/W (W0) bit set to 0b indicates a SPI write transaction. For a SPI read operation, R/W

bit needs to be set to 1b.

Address Bits (A): A SPI secondary device takes a 6-bit register address.

Parity Bit (P): Both header and data fields of a SPI input data frame include a parity bit for single bit error

detection - in Table 8-7, B16 is parity bit for the header field, while B15 is the parity bit for the data field. The

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parity scheme used is even parity - the number of ones in a block of 16-bits (including the parity bit) is even.

Data will be written to the internal registers only if the parity check is successful. Parity checks can be enabled or

disabled by configuring the SPI_PEN bit of SYS_CTRL register. Parity checks are disabled by default.

Note

Though parity checks are disabled by default, TI recommends enabling parity checks to safeguard

against single-bit errors.

Error Handling

Parity Error: Upon detecting a parity error, the secondary device responds in the following ways. Parity error

gets latched and reported on nFAULT. The error status is available for read on SPI_PARITY field of SYS_STS

register. A parity error in the header will not prevent the secondary device from responding with data. The

SDO will be driven by the secondary device being addressed. Updates to write address pointer and the device

registers will be ignored when parity error is detected. In a sequential write, upon detection of parity error any

subsequent register writes will be ignored.

Frame Error: Any incomplete SPI Frame will be reported as Frame error. Frame errors will be latched in

FRM_ERR field of SYSIF_STS register and indicated on nFAULT.

SPI Read/Write Sequence

SPI Read Sequence: The SPI read transaction comprises of an 8-bit header (R/W - 1 bit, Address - 6 bits,

and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first byte of header, the secondary

device responds with an 8-bit device status information. The read address pointer gets updated immediately

after receiving the address field of the header. The read address from the header acts as the starting address for

the register reads. The read address pointer gets incremented automatically upon completion of a 16-bit transfer.

The length of data transfer is not restricted by the secondary device. The secondary device responds with data

as long as the primary device transmits dummy words. If parity error check is enabled, the MSB of read data will

be replaced with computed parity bit

SPI Write Sequence: SPI write transaction comprises of an 8-bit header followed by 16-bit data words to be

written into the register bank. Similar to a read transaction, the addressed secondary device responds with an

8-bit device status information upon receiving the first byte of header. Once the header bytes are received,

the write address pointer gets updated. The write address from the header acts as the starting address for

sequential register writes. The read address pointer will retain the address of the register being read in the

previous SPI transaction. The length of data transfer is not restricted by the secondary device. Both read and

write address pointers will be incremented automatically upon completion of a 16-bit transfer. While receiving

data from the primary device, the SDO will be driven with the register data addressed by read address pointer.

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8.6 DRV8317 Registers

Table 8-9 lists the memory-mapped registers for the DRV8317 registers. All register offset addresses not listed in

Table 8-9 should be considered as reserved locations and the register contents should not be modified.

Table 8-9. DRV8317 Registers

Offset Acronym

Register Name

Section

0h

2h

DEV_STS

Device Status Register

Section 8.6.1

Section 8.6.2

Section 8.6.3

Section 8.6.4

Section 8.6.5

Section 8.6.6

Section 8.6.7

Section 8.6.8

Section 8.6.9

Section 8.6.10

Section 8.6.11

Section 8.6.12

Section 8.6.13

Section 8.6.14

Section 8.6.15

Section 8.6.16

DEV_RSTS

OT_STS

Device Raw Status Register

Over Temperature Status Register

Supply Status Register

4h

5h

SUP_STS

6h

DRV_STS

Driver Status Register

7h

SYSIF_STS

FLT_MODE

SYSF_CTRL

DRVF_TCTRL

FLT_TCTRL

FLT_CLR

System Interface Status Register

Fault Mode Register

10h

12h

13h

16h

17h

18h

20h

22h

23h

3Fh

System Fault Control Register

Driver Fault Control Register

Fault Timing Control Register

Fault Clear Register

VMUV_WARN_THR

PWM_CTRL

DRV_CTRL

CSA_CTRL

SYS_CTRL

VM Under Voltage Warn Threshold Register

PWM Control Register

Predriver control Register

CSA Control Register

System Control Register

Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for

access types in this section.

Table 8-10. DRV8317 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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8.6.1 DEV_STS Register (Offset = 0h) [Reset = 0280h]

DEV_STS is shown in Figure 8-28 and described in Table 8-11.

Return to the Table 8-9.

Figure 8-28. DEV_STS Register

15

14

13

12

11

10

9

8

PARITY

R-0h

RESERVED

R-0-0h

DNRDY_STS

R-0-1h

SYSFLT

R-0h

7

6

5

4

3

2

1

0

RESET

R-1h

SPIFLT

R-0h

OCP

R-0h

UVW

R-0h

OVP

R-0h

UVP

R-0h

OTF

R-0h

FAULT

R-0h

Table 8-11. DEV_STS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

PARITY

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-10

9

RESERVED

R-0

0h

DNRDY_STS

1h

Device not ready status

0h = Device is ready to spin motor

1h = Device is not ready

8

7

6

5

4

3

2

1

0

SYSFLT

RESET

SPIFLT

OCP

R

0h

1h

0h

OTP read fault occurred. Status remains latched until cleared by

write to FLT_CLR or reset pulse on nSLEEP

0h = No OTP read fault is detected

1h = OTP read fault detected

Device power on status. Status remains latched until cleared by write

to FLT_CLR or reset pulse on nSLEEP

0h = Cleared by writing 1b to FLT_CLR bit after power-up

1h = Device has undergone power on reset

SPI fault status. Status remains latched until cleared by write to

FLT_CLR or reset pulse on nSLEEP

0h = No SPI fault is detected

1h = SPI fault is detected

Driver over current Status. Status remains latched until cleared by

write to FLT_CLR or reset pulse on nSLEEP

0h = No over current condition is detected

1h = Over current condition is detected

UVW

VM under voltage warning fault status. Status remains latched until

cleared by write to FLT_CLR or reset pulse on nSLEEP

0h = No VM under voltage warn condition is detected

1h = VM under voltage warn condition is detected

OVP

Over voltage status. Status remains latched until cleared by write to

FLT_CLR or reset pulse on nSLEEP

0h = No over voltage condition is detected

1h = Over voltage condition is detected

UVP

Supply under voltage status. Status remains latched until cleared by

write to FLT_CLR or reset pulse on nSLEEP

0h = No under voltage condition is detected on VM or CP

1h = Under voltage condition is detected on VM or CP

OTF

Over temperature fault status. Status remains latched until cleared

by write to FLT_CLR or reset pulse on nSLEEP

0h = No over temperature warning / shutdown is detected

1h = Over temperature warning / shutdown is detected

FAULT

Device fault status. Status remains latched until cleared by write to

FLT_CLR or reset pulse on nSLEEP

0h = No fault condition is detected

1h = Fault condition is detected

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8.6.2 DEV_RSTS Register (Offset = 2h) [Reset = 0000h]

DEV_RSTS is shown in Figure 8-29 and described in Table 8-12.

Return to the Table 8-9.

Figure 8-29. DEV_RSTS Register

15

14

13

12

11

10

9

8

RESERVED

R-0-0h

DNRDY_RSTS SYSF_RSTS

R-0h

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

SPIF_RSTS

R-0h

OCP_RSTS

R-0h

VMUV_WRSTS

R-0-0h

OVP_RSTS

R-0-0h

UVP_RSTS

R-0h

OTF_RSTS

R-0h

RESERVED

R-0-0h

Table 8-12. DEV_RSTS Register Field Descriptions

Bit

15-10

9

Field

RESERVED

Type

R-0

R

Reset

Description

0h

Reserved

DNRDY_RSTS

0h

Device not ready indicator

0h = Device not ready to drive PWMs

1h = Device ready to drive PWMs

8

SYSF_RSTS

R

0h

OTP parity error during load, raw status. Cleared by write to

FLT_CLR or reset pulse on nSLEEP

0h = No parity error during OTP load

1h = Parity error occurred during OTP load

7

6

RESERVED

SPIF_RSTS

R-0

R

0h

Reserved

SPI fault raw status. Cleared by write to FLT_CLR or reset pulse on

nSLEEP

0h = No SPI fault is detected

1h = SPI fault is detected

5

4

OCP_RSTS

R

0h

Driver OCP raw status. Auto cleared if retry is enabled in

OCP_MODE. Can also be cleared by write to FLT_CLR or reset

pulse on nSLEEP.

0h = No over current condition is detected

1h = Over current condition is detected

VMUV_WRSTS

R-0

VM under voltage warning fault raw status. Auto cleared if retry is

enabled in VMUV_WARN_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No VM under voltage warn condition is detected (VM >

VMUV_WARN_RISE threshold)

1h = VM under voltage warn condition is detected (VM <

VMUV_WARN_FALL threshold)

3

2

1

0

OVP_RSTS

UVP_RSTS

OTF_RSTS

RESERVED

R-0

R

0h

Over voltage protection fault raw status. Auto cleared if retry is

enabled in OVP_MODE. Can also be cleared by write to FLT_CLR or

reset pulse on nSLEEP.

0h = No over voltage condition on VM is detected

1h = VM over voltage condition is detected

Under voltage protection fault raw status. Auto cleared if retry is

enabled in UVP_MODE. Can also be cleared by write to FLT_CLR or

reset pulse on nSLEEP.

0h = No under voltage condition is detected on VM or CP

1h = Under voltage condition is detected on VM or CP

R

Over temperature fault raw status. Auto cleared if retry is enabled

in OTF_MODE. Can also be cleared by write to FLT_CLR or reset

pulse on nSLEEP.

0h = No over temperature warning/shutdown is detected

1h = Over temperature warning/shutdown is detected

R-0

Reserved

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8.6.3 OT_STS Register (Offset = 4h) [Reset = 0000h]

OT_STS is shown in Figure 8-30 and described in Table 8-13.

Return to the Table 8-9.

Figure 8-30. OT_STS Register

15

14

13

12

11

10

9

8

PARITY

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

RESERVED

R-0h

OTW_FET

R-0h

OTS_FET

R-0h

Table 8-13. OT_STS Register Field Descriptions

Bit

15

14-3

2

Field

Type

Reset

Description

PARITY

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

RESERVED

OTW_FET

R-0

R

0h

Reserved

0h

1

R

0h

FET over temperature warning fault status. Auto cleared if retry is

enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or

reset pulse on nSLEEP.

0h = No FET over temperature warning is detected

1h = FET over temperature warning is detected

0

OTS_FET

R

0h

FET over temperature shutdown fault status. Auto cleared if retry is

enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or

reset pulse on nSLEEP.

0h = No FET over temperature shutdown is detected

1h = FET over temperature shutdown is detected

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8.6.4 SUP_STS Register (Offset = 5h) [Reset = 0000h]

SUP_STS is shown in Figure 8-31 and described in Table 8-14.

Return to the Table 8-9.

Figure 8-31. SUP_STS Register

15

14

13

12

11

10

9

8

PARITY

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

0

VMUV_WARN

R-0-0h

VM_OV

R-0-0h

RESERVED

R-0-0h

CP_UV

R-0h

RESERVED

R-0-0h

RESERVED

R-0h

VM_UV

R-0-0h

RESERVED

R-0h

Table 8-14. SUP_STS Register Field Descriptions

Bit

15

Field

PARITY

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-8

7

RESERVED

R-0

0h

VMUV_WARN

0h

VM under voltage warning fault status. This bit is not auto cleared

even when retry is enabled in VMUV_WARN_MODE. Can be

cleared by write to FLT_CLR or reset pulse on nSLEEP.

0h = No VM under voltage warning is detected

1h = VM under voltage warning is detected

6

VM_OV

R-0

0h

VM over voltage fault status. This bit is not auto cleared even when

retry is enabled in OVP_MODE. Can be cleared by write to FLT_CLR

or reset pulse on nSLEEP.

0h = No VM over voltage is detected

1h = VM over voltage is detected

5

4

RESERVED

CP_UV

R-0

R

0h

Reserved

Charge pump under voltage fault status. This bit is not auto cleared

even when retry is enabled in UVP_MODE. Can be cleared by write

to FLT_CLR or reset pulse on nSLEEP.

0h = No charge pump under voltage is detected

1h = Charge pump under voltage is detected

3

2

1

RESERVED

VM_UV

R-0

R

0h

Reserved

R-0

VM under voltage fault status. This bit is not auto cleared even when

retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR

or reset pulse on nSLEEP.

0h = No VM under voltage is detected

1h = VM under voltage is detected

0

RESERVED

R

0h

Reserved

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8.6.5 DRV_STS Register (Offset = 6h) [Reset = 0000h]

DRV_STS is shown in Figure 8-32 and described in Table 8-15.

Return to the Table 8-9.

Figure 8-32. DRV_STS Register

15

14

13

12

11

10

9

8

PARITY

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

OCPC_HS

R-0h

OCPB_HS

R-0h

OCPA_HS

R-0h

RESERVED

R-0-0h

OCPC_LS

R-0h

OCPB_LS

R-0h

OCPA_LS

R-0h

Table 8-15. DRV_STS Register Field Descriptions

Bit

15

Field

PARITY

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-7

6

RESERVED

OCPC_HS

R-0

R

0h

Over current status on high-side MOSFET of OUTC. Auto cleared

if retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on high-side MOSFET of OUTC

1h = Over current detected on high-side MOSFET of OUTC

5

4

OCPB_HS

OCPA_HS

R

0h

Over current status on high-side MOSFET of OUTB. Auto cleared

if retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on high-side MOSFET of OUTB

1h = Over current detected on high-side MOSFET of OUTB

Over current status on high-side MOSFET of OUTA. Auto cleared

if retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on high-side MOSFET of OUTA

1h = Over current detected on high-side MOSFET of OUTA

3

2

RESERVED

OCPC_LS

R-0

R

0h

Reserved

Over current status on low-side MOSFET of OUTC. Auto cleared

if retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on low-side MOSFET of OUTC

1h = Over current detected on low-side MOSFET of OUTC

1

0

OCPB_LS

OCPA_LS

R

0h

Over current status on low-side MOSFET of OUTB. Auto cleared

if retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on low-side MOSFET of OUTB

1h = Over current detected on low-side MOSFET of OUTB

Over current status on low-side MOSFET of OUTA. Auto cleared if

retry is enabled in OCP_MODE. Can also be cleared by write to

FLT_CLR or reset pulse on nSLEEP.

0h = No over current detected on low-side MOSFET of OUTA

1h = Over current detected on low-side MOSFET of OUTA

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8.6.6 SYSIF_STS Register (Offset = 7h) [Reset = 0000h]

SYSIF_STS is shown in Figure 8-33 and described in Table 8-16.

Return to the Table 8-9.

Figure 8-33. SYSIF_STS Register

15

14

13

12

11

10

9

8

PARITY

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

OTPLD_ERR

R-0h

RESERVED

R-0-0h

SPI_PARITY

R-0h

BUS_CNT

R-0h

FRM_ERR

R-0h

Table 8-16. SYSIF_STS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

PARITY

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-5

4

RESERVED

OTPLD_ERR

R-0

R

0h

OTP parity error during load

0h = No OTP read error is detected

1h = OTP read error is detected

3

2

RESERVED

SPI_PARITY

R-0

R

0h

Reserved

SPI parity error

0h = No SPI Parity Error is detected

1h = SPI Parity Error is detected

1

0

BUS_CNT

FRM_ERR

R

0h

SPI bus contention error

0h = No SPI Bus Contention Error is detected

1h = SPI Bus Contention Error is detected

SPI frame error

0h = No SPI Frame Error is detected

1h = SPI Frame Error is detected

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8.6.7 FLT_MODE Register (Offset = 10h) [Reset = 0015h]

FLT_MODE is shown in Figure 8-34 and described in Table 8-17.

Return to the Table 8-9.

Figure 8-34. FLT_MODE Register

15

14

13

12

11

10

2

9

1

8

PARITY

R/W-0h

RESERVED

R-0-0h

VMUV_WARN_MODE

R/W-0h

OVP_MODE

R/W-0h

RESERVED

R/W-0h

0

7

6

5

4

3

SPIFLT_MODE

R/W-0h

OCP_MODE

R/W-1h

UVP_MODE

R/W-1h

OTF_MODE

R/W-1h

Table 8-17. FLT_MODE Register Field Descriptions

Bit

15

Field

PARITY

Type

R/W

R-0

Reset

Description

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-13

12-11

RESERVED

0h

VMUV_WARN_MODE

R/W

0h

VM under voltage warning fault mode

0h = Report on nFAULT, latch into status register, pre-driver Hi-Z,

auto recovery with slow retry time (in ms)

1h = Report on nFAULT, latch into status register, pre-driver Hi-Z,

auto recovery with fast retry time (in ms)

2h = Report on nFAULT, latch into status register, no action on pre-

driver

3h = Disabled

10-9

OVP_MODE

R/W

0h

Over voltage protection fault mode

0h = Report on nFAULT, latch into status register, pre-driver Hi-Z,

auto recovery with slow retry time (in ms)

1h = Report on nFAULT, latch into status register, pre-driver Hi-Z,

auto recovery with fast retry time (in ms)

2h = Reserved

3h = Reserved

8

7

RESERVED

R/W

0h

Reserved

SPIFLT_MODE

SPI fault mode

0h = Report on nFAULT, latch into status register, no action on pre-

driver

1h = Disabled

6-4

OCP_MODE

R/W

1h

Over current protection fault mode

0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recovery with slow retry time (in ms)

1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recovery with fast retry time (in ms)

2h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, no

auto recovery, wait for CLR_FLT

3h = Report on nFAULT, Latch into status register, No action on

pre-driver

4h = Reserved

5h = Reserved

6h = Reserved

7h = Reserved

3-2

UVP_MODE

R/W

1h

Under voltage protection fault mode

0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recovery with slow retry time (in ms)

1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recovery with fast retry time (in ms)

2h = Reserved

3h = Reserved

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Table 8-17. FLT_MODE Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

OTF_MODE

R/W

1h

Over temperature fault mode

0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recover with Slow Retry time (in ms)

1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z,

auto recover with Fast Retry time (in ms)

2h = Reserved

3h = Reserved

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8.6.8 SYSF_CTRL Register (Offset = 12h) [Reset = 0553h]

SYSF_CTRL is shown in Figure 8-35 and described in Table 8-18.

Return to the Table 8-9.

Figure 8-35. SYSF_CTRL Register

15

14

13

12

11

10

9

8

PARITY

R/W-0h

RESERVED

R-0-0h

DNRDY_EN

R/W-1h

OTW_FET_EN

R/W-0h

RESERVED

R/W-1h

7

6

5

4

3

2

1

0

VMUV_WARN_

EN

RESERVED

R-0-0h

RESERVED

R-0-0h

RESERVED

R/W-0h

R/W-1h

Table 8-18. SYSF_CTRL Register Field Descriptions

Bit

15

Field

PARITY

Type

R/W

R-0

Reset

Description

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-11

10

RESERVED

DNRDY_EN

0h

R/W

1h

Device not ready fault enable

0h = Device not ready fault is disabled

1h = Device not ready fault is enabled

9

OTW_FET_EN

R/W

0h

FET over temperature warning fault enable

0h = FET over temperature warning is disabled

1h = FET over temperature warning is enabled

8

7

RESERVED

R/W

1h

0h

Reserved

VMUV_WARN_EN

VM under voltage warn fault enable

0h = VM under voltage warning fault is disabled

1h = VM under voltage warning fault is enabled

6

5

RESERVED

R/W

R-0

1h

0h

1h

0h

1h

Reserved

4

R/W

R-0

3-2

1

R/W

0

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8.6.9 DRVF_TCTRL Register (Offset = 13h) [Reset = 0155h]

DRVF_TCTRL is shown in Figure 8-36 and described in Table 8-19.

Return to the Table 8-9.

Figure 8-36. DRVF_TCTRL Register

15

14

13

12

11

10

2

9

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

RESERVED

R/W-1h

7

6

5

4

3

1

RESERVED

OCP_DEG

R/W-1h

OCP_TBLANK

R/W-1h

VMUV_WARN_TDG

R/W-1h

Table 8-19. DRVF_TCTRL Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-10

9-8

RESERVED

OCP_DEG

0h

Reserved

R/W

1h

7-6

1h

5-4

1h

OCP deglitch time

0h = 0.3 µs

1h = 0.6 µs

2h = 0.9 µs

3h = 1.2 µs

3-2

1-0

OCP_TBLANK

R/W

1h

OCP blanking time

0h = 0.3 µs

1h = 0.7 µs

2h = 2 µs

3h = 1.2 µs

VMUV_WARN_TDG

VM under voltage warning deglitch time

0h = 0.3 µs

1h = 0.6 µs

2h = 0.9 µs

3h = 2 µs

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8.6.10 FLT_TCTRL Register (Offset = 16h) [Reset = 0003h]

FLT_TCTRL is shown in Figure 8-37 and described in Table 8-20.

Return to the Table 8-9.

Figure 8-37. FLT_TCTRL Register

15

14

13

12

11

10

2

9

1

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

7

6

5

4

3

RESERVED

R-0-0h

SLOW_TRETRY

R/W-0h

FAST_TRETRY

R/W-3h

Table 8-20. FLT_TCTRL Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-4

3-2

RESERVED

0h

SLOW_TRETRY

R/W

0h

Retry time (typical) for slow recovery from fault condition

0h = 0.5s

1h = 1s

2h = 2s

3h = 5s

1-0

FAST_TRETRY

R/W

3h

Retry time (typical) for fast recovery from fault condition

0h = 0.5ms

1h = 1ms

2h = 2ms

3h = 5ms

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8.6.11 FLT_CLR Register (Offset = 17h) [Reset = 0000h]

FLT_CLR is shown in Figure 8-38 and described in Table 8-21.

Return to the Table 8-9.

Figure 8-38. FLT_CLR Register

15

14

13

12

11

10

2

9

8

RESERVED

R/W-0h

RESERVED

R-0-0h

7

6

5

4

3

1

0

RESERVED

R-0-0h

FLT_CLR

W-0h

Table 8-21. FLT_CLR Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

W

Reset

Description

Reserved

RESERVED

FLT_CLR

0h

14-1

0

0h

Clear latched faults

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after

being written.

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8.6.12 VMUV_WARN_THR Register (Offset = 18h) [Reset = 0000h]

VMUV_WARN_THR is shown in Figure 8-39 and described in Table 8-22.

Return to the Table 8-9.

Figure 8-39. VMUV_WARN_THR Register

15

14

13

12

11

10

9

1

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

7

6

5

4

3

2

VMUV_WARN_RTH

R/W-0h

VMUV_WARN_FTH

R/W-0h

Table 8-22. VMUV_WARN_THR Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-8

7-4

RESERVED

VMUV_WARN_RTH

0h

R/W

0h

VM under voltage warning rising threshold

0h = 5.62V

1h = 6.25V

2h = 6.87V

3h = 7.5V

4h = 8.12V

5h = 8.75V

6h = 9.37V

7h = 10.00V

8h = 10.62V

9h = 11.25V

Ah = 11.87V

Bh = 12.5V

Ch = 13.75V

Dh = 15.00V

Eh = 16.25V

Fh = 17.5V

3-0

VMUV_WARN_FTH

R/W

0h

VM under voltage warning falling threshold

0h = 5.4V

1h = 6.0V

2h = 6.6V

3h = 7.2V

4h = 7.8V

5h = 8.4V

6h = 9.0V

7h = 9.6V

8h = 10.2V

9h = 10.8V

Ah = 11.4V

Bh = 12.0V

Ch = 13.2V

Dh = 14.4V

Eh = 15.6V

Fh = 16.8V

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8.6.13 PWM_CTRL Register (Offset = 20h) [Reset = 0000h]

PWM_CTRL is shown in Figure 8-40 and described in Table 8-23.

Return to the Table 8-9.

Figure 8-40. PWM_CTRL Register

15

14

13

12

11

10

9

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

RESERVED

R-0-0h

SSC_DIS

R/W-0h

PWM_MODE

R/W-0h

Table 8-23. PWM_CTRL Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-3

2

RESERVED

SSC_DIS

0h

R/W

0h

Disable SSC on oscillator

0h = SSC enabled

1h = SSC disabled

1-0

PWM_MODE

R/W

0h

PWM mode selection

0h = 6x mode

1h = 6x direct mode

2h = 3x mode

3h = 3x direct mode

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8.6.14 DRV_CTRL Register (Offset = 22h) [Reset = 0003h]

DRV_CTRL is shown in Figure 8-41 and described in Table 8-24.

Return to the Table 8-9.

Figure 8-41. DRV_CTRL Register

15

14

13

12

11

10

2

9

1

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

DLY_TARGET

R/W-0h

7

6

5

4

3

DLYCMP_EN

R/W-0h

RESERVED

R-0-0h

SLEW_RATE

R/W-3h

Table 8-24. DRV_CTRL Register Field Descriptions

Bit

15

Field

PARITY

Type

R/W

R-0

Reset

Description

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-8

7

RESERVED

DLY_TARGET

DLYCMP_EN

0h

R/W

0h

Delay Target : DLY_TARGET * 0.2µs

0h

Driver Delay Compensation enable

0h = Delay compensation disabled

1h = Delay compensation enabled

6-2

1-0

RESERVED

SLEW_RATE

R-0

0h

3h

Reserved

R/W

Slew rate settings

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 125 V/µs

3h = Slew rate is 200 V/µs

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8.6.15 CSA_CTRL Register (Offset = 23h) [Reset = 0008h]

CSA_CTRL is shown in Figure 8-42 and described in Table 8-25.

Return to the Table 8-9.

Figure 8-42. CSA_CTRL Register

15

14

13

12

11

10

9

8

0

PARITY

R/W-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

RESERVED

R-0-0h

CSA_EN

R/W-1h

RESERVED

R-0-0h

CSA_GAIN

R/W-0h

Table 8-25. CSA_CTRL Register Field Descriptions

Bit

15

Field

Type

R/W

R-0

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-4

3

RESERVED

CSA_EN

0h

R/W

1h

Enable CSA

0h = CSA is disabled

1h = CSA is enabled

2

RESERVED

CSA_GAIN

R-0

0h

Reserved

1-0

R/W

CSA Gain settings

0h = CSA gain is 0.25 V/A

1h = CSA gain is 0.5 V/A

2h = CSA gain is 1 V/A

3h = CSA gain is 2 V/A

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8.6.16 SYS_CTRL Register (Offset = 3Fh) [Reset = 5008h]

SYS_CTRL is shown in Figure 8-43 and described in Table 8-26.

Return to the Table 8-9.

Figure 8-43. SYS_CTRL Register

15

14

13

12

11

10

2

9

8

PARITY

R/W-0h

WRITE_KEY

W-5h

RESERVED

R-0-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

0

7

6

5

4

3

1

REG_LOCK

R/W-0h

SPI_PEN

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-1h

RESERVED

R/W-0h

Table 8-26. SYS_CTRL Register Field Descriptions

Bit

15

Field

Type

R/W

W

Reset

Description

PARITY

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-12

11-10

9

WRITE_KEY

RESERVED

REG_LOCK

5h

0x5 : Write Key specific to this register.

R-0

0h

Reserved

R/W

0h

8

0h

7

0h

Register Lock Bit

0h = Registers Unlocked

1h = Registers Locked

6

SPI_PEN

R/W

0h

Parity Enable for SPI

0h = Parity Disabled

1h = Parity Enabled

5-4

3

RESERVED

R/W

0h

1h

0h

Reserved

2-0

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The DRV8317 can be used to drive brushless-DC motors. The following design procedure can be used to

configure the DRV8317.

V_VM

+

0.1 µF

VM

47 nF

CPH

0.1 µF

10 µF

0.1 µF

CP

V_CC

CPL

Voltage

Supervisor

CSAREF

VIN_AVDD

Microcontroller

+

0.1 µF

10 µF

ADC

External

Load

22 pF

330

SOC

SOB

AVDD

AGND

Current

Sensing

C_AVDD

CSA

22 pF

330

SOA

22 pF

5.1 k

DRV8317S

nFAULT

nSLEEP

GP-I

Hall

Sensors

(Optional)

Sleep Control

OUTA

A

B

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

OUTB

OUTC

PWM

Control

Module

PWM

Control

Input

GP-O

SDO

GP-I

GP-O

nSCS

SCLK

PGND

SPI

SDI

Hall Input

GP-I

Figure 9-1. Application Schematics (DRV8317S)

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9.2 Typical Applications

9.2.1 Three-Phase Brushless-DC Motor Control

In this application, the DRV8317 is used to drive a brushless-DC motor using PWMs from an external

microcontroller.

9.2.1.1 Detailed Design Procedure

Table 9-1 lists the example input parameters for the system design.

Table 9-1. Design Parameters

DESIGN PARAMETERS

Supply voltage

REFERENCE

V_VM

EXAMPLE VALUE

12 V

2 A

Motor RMS current

I_RMS

Motor peak current

I_PEAK

3 A

PWM Frequency

f_PWM

50 kHz

200 V/µs

12 V

Slew Rate Setting

SR

VIN_AVDD supply voltage

CSA reference voltage

System ambient temperature

V_{VIN_AVDD}

V_{CSA_REF}

T_A

3.0 V

–20°C to +50°C

9.2.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example, 5V or 12V). The DRV8317 allows for

a range of possible operating voltages from 4.5-V to 20-V.

9.2.1.2 Driver Propagation Delay and Dead Time

The propagation delay is defined as the time taken for changing input logic edges INHx and INLx (whichever

changes first, if MCU dead time is added) to change the half-bridge output voltage (OUTx). Driver propagation

delay (t_PD) and dead time (t_dead) are specified with a typical and maximum value, but not with a minimum value.

This is because the propagation delay can be smaller than typical depending on the direction of current at

the OUTx pin during synchronous switching. Driver propagation delay and dead time can be more than typical

values due to slower internal turn-on of the high-side or low-side internal MOSFETs to avoid parasitic dV/dt

coupling.

For more information and examples of how propagation delay and dead time differs for input PWM and output

configurations, refer to Delay and Dead Time in Integrated MOSFET Drivers .

The dead time from the external microcontroller’s (MCU) PWM inputs (INHx, INLx) can be used as an extra

precaution in addition to the DRV8317 internal shoot-through (cross conduction) protection. If the MCU dead

time is less than the DRV8317 driver dead time, actual output (OUTx voltage) dead time will be decided by

the DRV8317 dead time (t_DEAD). If the MCU dead time is larger than the driver dead time, actual output (OUTx

voltage) dead time will be decided by the MCU dead time.

A summary of the DRV8317 delay times with respect to synchronous inputs INHx and INLx, OUTx current

direction, and MCU dead time are listed in Table 9-2.

Table 9-2. Summary of Delay Times in DRV8317 Depending on Logic Inputs and Output Current Direction

OUTx Current INHx

Direction

INLx

Propagation Delay Dead Time (t_DEAD

)

Inserted MCU Dead Time (t_DEAD(MCU)

)

(t_PD

)

t_DEAD(MCU)≤ t_DEADt_DEAD(MCU)> t_DEAD

Out of OUTx

Rising

Falling

Falling ≤ t_PD(max)

Rising ≤ t_PD(typ.)

≤ t_DEAD(max)

≤ t_DEAD(typ.)

Output dead time ≤ t_DEADOutput dead time = t_DEAD(MCU)

(max)

Output dead time ≤ t_DEADOutput dead time < t_DEAD(MCU)

(typ.)

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Table 9-2. Summary of Delay Times in DRV8317 Depending on Logic Inputs and Output Current Direction

(continued)

OUTx Current INHx

Direction

INLx

Propagation Delay Dead Time (t_DEAD

(t_PD

)

Inserted MCU Dead Time (t_DEAD(MCU)

)

t_DEAD(MCU)≤ t_DEADt_DEAD(MCU)> t_DEAD

Into OUTx

Rising

Falling

Falling ≤ t_PD(typ.)

Rising ≤ t_PD(max)

≤ t_DEAD(typ.)

≤ t_DEAD(max)

Output dead time ≤ t_DEADOutput dead time < t_DEAD(MCU)

(typ.)

Output dead time ≤ t_DEADOutput dead time = t_DEAD(MCU)

(max)

9.2.1.3 Delay Compensation

Differences in delays of dead time and propagation delay can cause mismatch in the output timings of PWMs,

which can lead to duty cycle distortion. In order to accommodate differences in propagation delay between the

conditions mentioned in Table 9-2, DRV8317 integrates a delay compensation feature.

Delay compensation is used to match delay times for currents going into and out of phase (OUTx) by adding a

variable delay time (t_var) to match a preset target delay time equal to the propagation delay plus driver dead time

(t_PD+ t_{DRV_DEAD}). This (t_var) setting is automatically configured by the DRV8317 when the DLYCMP_EN bit is set

to 1b.

9.2.1.4 Current Sensing and Output Filtering

The SOx pins are typically sampled by an analog-to-digital converter in the MCU to calculate the phase current.

Phase current information is used for closed-loop control such as Field-Oriented Control (FOC).

An example calculation for phase current is shown in Equation 3.

SOx = V_REF/2 + G_CSA* I_OUTx

(3)

For example, in a system with VREF = 3-V, CSA gain = 0.5 V/A, and a SOx voltage of 1.2-V, phase current

(I_OUTx) = -0.6A.

Sometimes high frequency noise can appear at the SOx signals based on voltage ripple at VREF, added

inductance at the SOx traces, or routing of SOx traces near high frequency components. It is recommended to

add a low-pass RC filter close to the MCU with cut-off frequency at least 10 times the PWM switching frequency

for trapezoidal commutation and 100 times the PWM switching frequency for sinusoidal commutation to filter

high frequency noise. A recommended RC filter is 330-ohms, 22-pF to add minimal parallel capacitance to the

ADC and current mirroring circuitry without increasing the settling time of the CSA output.

The cutoff frequency for the low-pass RC filter is in Equation 4.

1

f =

(4)

c

2πRC

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9.2.1.5 Application Curves

Figure 9-2. Device Power up with VM (VM, nFAULT,

nSLEEP, AVDD)

Figure 9-3. Device Power up with nSLEEP (VM,

nFAULT, nSLEEP, AVDD)

Figure 9-4. Driver PWM Operation (OUTA, OUTB,

OUTC, I_A)

Figure 9-5. Driver PWM Operation with Current

Sense Feedback (INHA, OUTA, SOA, I_A)

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9.3 Alternate Applications

The DRV8317 can be used to drive brushed-DC motors and solenoid loads. The following design procedure can

be used to configure the DRV8317.

V_VM

+

47 nF

CPH

0.1 µF

VM

0.1 µF

10 µF

0.1 µF

CPL

CP

V_CC

Voltage

Supervisor

CSAREF

VIN_AVDD

Microcontroller

+

0.1 µF

10 µF

ADC

External

Load

22 pF

330

AVDD

AGND

ADC

SOC

SOB

Current

Sensing

C_AVDD

CSA

22 pF

330

SOA

22 pF

5.1 k

DRV8317H

nFAULT

GP-I

Sleep Control

nSLEEP

OUTA

M

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

OUTB

OUTC

V_VM

PWM

Control

Module

PWM

Control

Input

GP-O

Load

AVDD

MODE

SLEW

PGND

HW

GAIN

Figure 9-6. Application Schematics (DRV8317H) - Brushed-DC and Solenoid Load Drive Block Diagram

6x PWM mode or 3x PWM mode can be used to drive brushed-DC and/or solenoid loads depending on the

application. A Brushed-DC motor can be connected to two OUTx phases to create an integrated full H-bridge

configuration to drive the motor in both direction.

Solenoid loads can be connected from OUTx to VM or GND to use the DRV8317 as a push-pull driver in 6x

PWM or 3x PWM mode. When the load is connected from OUTx to GND, the HS MOSFET sources current into

the solenoid, and the LS MOSFET acts as a recirculation diode to recirculate current from the solenoid. When

the load is connected from OUTx to VM, the LS MOSFET sink current from the solenoid to GND, and the HS

MOSFET acts as a recirculation diode to recirculate current from the solenoid.

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10 Power Supply Recommendations

10.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

•

The highest current required by the motor system

The capacitance and current capability of the power supply

The amount of parasitic inductance between the power supply and motor system

The acceptable voltage ripple

The type of motor used (brushed dc, brushless DC, stepper)

The motor braking method

The inductance between the power supply and the motor drive system limits the rate current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

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11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high

current.

Small-value capacitors should be ceramic, and placed closely to device pins including, AVDD, charge pump,

CSAREF, VINAVDD and VM.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from

the device. Ensure grounds are connected through net-ties to reduce voltage offsets and maintain gate driver

performance. A common ground plane can also be used for PGND and AGND to minimize inductance in the

grounding, but it is recommended to place motor switching outputs as far away from analog and digital signals

so motor noise does not couple into the analog and digital circuits.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Figure 11-1 shows a recommended layout example.

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11.2 Layout Example

Figure 11-1. Recommended Layout Example

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11.3 Thermal Considerations

The DRV8317 has thermal shutdown (OTS) as previously described. A die temperature in excess of 145°C

(min.) can disable the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation and Junction Temperature Estimation

Power Dissipation

The power loss in DRV8317 include standby losses, LDO losses, FET conduction and switching losses, and

diode losses. The FET conduction loss dominates the total power dissipation in DRV8317. At start-up and fault

conditions, the output current is much higher than normal current; remember to take these peak currents and

their duration into consideration. The total device dissipation is the power dissipated in each of the three half

bridges added together. The maximum amount of power that the device can dissipate depends on ambient

temperature and heatsinking. Note that R_DS,ONincreases with temperature, so as the device heats, the power

dissipation increases. Take this into consideration when designing the PCB and heatsinking.

A summary of equations for calculating each loss is listed in Table 11-1 for trapezoidal control and field-oriented

control.

Table 11-1. DRV8317 Power Losses for Trapezoidal and Field-oriented Control

Loss type

Standby power

AVDD LDO

Trapezoidal control

Field-oriented control

P_standby= V_VMx I_VMS

P_LDO= (V_{VIN_AVDD}- V_AVDD) x I_AVDD

FET conduction

P_CON= 2 x (I_PK(trap))²x R_DS,ON(TJ)

P_CON= 3 x (I_RMS(FOC))²x R_DS,ON(TJ)

P_SW= 3 x I_RMS(FOC)x V_PK(FOC)x t_rise/fall

f_PWM

P_diode= 6 x I_RMS(FOC)x V_F(diode)x t_DEAD

f_PWM

x

FET switching

P_SW= I_PK(trap)x V_PK(trap)x t_rise/fallx f_PWM

Diode (dead time)

P_diode= 2 x I_PK(trap)x V_F(diode)x t_DEADx f_PWM

Note

R_{DS,ON (TJ)}is the on-state resistance of a single FET at operating junction temperature.

Junction Temperature Estimation

To calculate the junction temperature of the die from power losses, use Equation 5. Note that the thermal

resistance R_θJAdepends on PCB configuration such as the numbers of PCB layers, copper thickness, ground

plane area and the PCB size.

T

℃ = P

W × R

℃/W + T ℃

(5)

J

LOSS

θJA A

Refer to BLDC integrated MOSFET thermal calculator for estimating the approximate device power dissipation

and junction temperature at different use cases.

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12 Device and Documentation Support

12.1 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.2 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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PACKAGE OUTLINE

REE0036A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 2.8

2.8

2.6

(0.1) TYP

11

18

4X (0.41)

32X 0.4

10

19

2X

3.6

SYMM

3.8

3.6

1

28

0.25

0.15

36X

29

36

PIN 1 ID

0.1

C A B

SYMM

0.5

0.3

0.05

36X

4226725/A 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

REE0036A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.8)

2X (2.8)

(2.7)

29

36

36X (0.6)

32X (0.2)

1

28

32X (0.4)

(4.8)

37

SYMM

(3.7)

2X (3.6)

2X (0.625)

2X (0.975)

10

19

(R0.05) TYP

11

(

0.2) TYP

18

2X (1.1)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226725/A 04/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

REE0036A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.8)

2X (2.8)

6X (1.19)

36

29

36X (0.6)

1

28

36X (0.2)

6X

(1.05)

32X (0.4)

2X (3.6)

SYMM

(4.8)

2X (1.25)

10

19

(R0.05)

TYP

11

2X (0.7)

18

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4226725/A 04/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8317HREER
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 FET 和电流检测功能、最大电压为 24V、峰值电流为 5A 的三相电机驱动器 \| REE \| 36 \| -40 to 125 电机驱动驱动器
文件：	总69页 (文件大小：2638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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