DRV8320HRTVR [TI]
最大 65V 三相智能栅极驱动器 | RTV | 32 | -40 to 125;
| 型号： | DRV8320HRTVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 最大 65V 三相智能栅极驱动器 | RTV | 32 | -40 to 125 栅极驱动 电视 驱动器 |
| 文件： | 总92页 (文件大小：5456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
DRV832x 6V 至 60V 三相智能栅极驱动器
1 特性
3 说明
1
•
三个半桥栅极驱动器
DRV832x 系列器件是适用于三相 应用的集成式栅极驱
动器。这些器件具有三个半桥栅极驱动器，每个驱动器
都能够驱动高侧和低侧 N 沟道功率 MOSFET。
DRV832x 使用集成电荷泵为高侧 MOSFET 生成合适
的栅极驱动电压，并使用线性稳压器为低侧 MOSFET
生成合适的栅极驱动电压。此智能栅极驱动架构支持高
达 1A 的峰值栅极驱动拉电流和 2A 的峰值栅极驱动灌
电流。DRV832x 可由单个电源供电，并支持适用于栅
极驱动器的 6V 至 60V，以及适用于可选降压稳压器的
4V 至 60V 宽输入电源范围。
–
可驱动 3 个高侧和 3 个低侧 N 沟道 MOSFET
(NMOS)
•
智能栅极驱动架构
–
–
–
可调转换率控制
10mA 至 1A 峰值拉电流
20mA 至 2A 峰值灌电流
•
集成栅极驱动器电源
–
–
–
支持 100% PWM 占空比
高侧电荷泵
低侧线性稳压器
6x、3x、1x 和独立输入 PWM 模式可简化与控制器电
路的连接。栅极驱动器和器件的配置设置具有高度可配
置性，可通过 SPI 或硬件 (H/W) 接口实现。DRV8323
和 DRV8323R 器件集成了三个低侧电流检测放大器，
可在驱动级的全部三个相位上进行双向电流检测。
DRV8320R 和 DRV8323R 器件集成了一个 600mA 降
压稳压器。
•
•
6V 至 60V 工作电压范围
可选集成式降压稳压器
–
–
–
LMR16006X SIMPLE SWITCHER®
4V 至 60V 工作电压范围
0.8V 至 60V、600mA 输出能力
•
三个可选集成式电流检测放大器 (CSA)
–
–
可调增益（5、10、20、40 V/V）
提供了低功耗睡眠模式，以通过关断大部分的内部电路
实现较低的静态电流消耗。针对欠压锁定、电荷泵故
障、MOSFET 过流、MOSFET 短路、栅极驱动器故障
和过热等情况，提供内部保护功能。故障状况及故障详
情可通过 SPI 器件型号的器件寄存器显示在 nFAULT
引脚上。
双向或单向支持
•
•
•
•
•
•
•
•
提供有 SPI 和硬件接口
6x、3x、1x 和独立的 PWM 模式
支持 1.8V、3.3V 和 5V 逻辑输入
低功耗睡眠模式 (12µA)
3.3V、30mA 线性稳压器
紧凑型 QFN 封装和尺寸
采用电源块的高效系统设计
集成式保护 特性
器件信息(1)
器件型号
DRV8320
封装
WQFN (32)
封装尺寸（标称值）
5.00mm × 5.00mm
6.00mm × 6.00mm
6.00mm × 6.00mm
7.00mm × 7.00mm
DRV8320R
DRV8323
VQFN (40)
WQFN (40)
VQFN (48)
–
–
–
–
–
–
VM 欠压闭锁 (UVLO)
电荷泵欠压 (CPUV)
DRV8323R
MOSFET 过流保护 (OCP)
栅极驱动器故障 (GDF)
热警告和热关断 (OTW/OTSD)
故障状态指示器 (nFAULT)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
6 to 60 V
2 应用
DRV832x
PWM
•
•
•
•
•
•
•
无刷直流 (BLDC) 电机模块和 PMSM
Gate Drive
Three-Phase
Smart Gate Driver
SPI or H/W
M
风扇、泵和伺服驱动器
nFAULT
Current Sense
600 mA
Protection
Current
Sense
电动自行车、电动踏板车和电动汽车
无线园艺工具和电动工具、割草机
无线真空吸尘器
3x Sense Amplifiers
Buck Regulator
无人机、机器人和遥控玩具
工业和物流机器人
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDJ3
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
目录
8.6 Register Maps......................................................... 53
Application and Implementation ........................ 61
9.1 Application Information............................................ 61
9.2 Typical Application ................................................. 61
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications....................................................... 11
7.1 Absolute Maximum Ratings .................................... 11
7.2 ESD Ratings .......................................................... 11
7.3 Recommended Operating Conditions..................... 12
7.4 Thermal Information................................................ 12
7.5 Electrical Characteristics......................................... 13
7.6 SPI Timing Requirements ....................................... 18
7.7 Typical Characteristics............................................ 19
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 30
8.4 Device Functional Modes........................................ 50
8.5 Programming........................................................... 51
9
10 Power Supply Recommendations ..................... 70
10.1 Bulk Capacitance Sizing ....................................... 70
11 Layout................................................................... 71
11.1 Layout Guidelines ................................................. 71
11.2 Layout Example .................................................... 72
12 器件和文档支持 ..................................................... 73
12.1 器件支持................................................................ 73
12.2 文档支持................................................................ 73
12.3 相关链接................................................................ 73
12.4 接收文档更新通知 ................................................. 74
12.5 社区资源................................................................ 74
12.6 商标....................................................................... 74
12.7 静电放电警告......................................................... 74
12.8 术语表 ................................................................... 74
13 机械、封装和可订购信息....................................... 74
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (December 2017) to Revision C
Page
•
•
•
已更改 更改了应用.................................................................................................................................................................. 1
Updated input labels for the INLx and INHx signals in the Layout Example imags............................................................. 72
已添加 在器件命名规则 部分的图像中添加了 DRV835x 器件选项 ....................................................................................... 73
Changes from Revision A (April 2017) to Revision B
Page
•
•
•
已更改 在“特性”中将低功耗睡眠模式电源电流从最大值 (20µA) 更改成了典型值 (12µA) ...................................................... 1
已更改 更改了应用.................................................................................................................................................................. 1
Changed the GAIN value from 45 kΩ to 47 kΩ in the test condition of the amplifier gain for the H/W device in the
Electrical Characteristics table ............................................................................................................................................. 15
•
•
•
•
•
•
•
Deleted tEN_nSCS from the SPI Slave Mode Timing Diagram................................................................................................. 18
Added a note to the Synchronous 1x PWM Mode to define !PWM ..................................................................................... 31
Updated the Auto Offset Calibration section ........................................................................................................................ 44
Updated the VDS Latched Shutdown and VDS Automatic Retry sections ............................................................................. 48
Updated the Sleep Mode section ......................................................................................................................................... 50
Changed the address listed in the title for the Gate Drive LS Register section to the correct register address, 0x04........ 58
已更改 the maximum Qg value for both trapezoidal and sinusoidal commutation the VVM = 8 V example of the
Detailed Design Procedure................................................................................................................................................... 63
•
已更改 IDRIVEP and IDRIVEN equations in the IDRIVE Configuration section ........................................................................... 64
2
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Changes from Original (February 2017) to Revision A
Page
•
•
•
Changed the test condition for the IBIAS parameter in the Electrical Characteristics table................................................... 16
Changed the GHx values in the 3x PWM Mode Truth Table ............................................................................................... 31
Changed the calibration description and added auto calibration feature description .......................................................... 44
Copyright © 2017–2018, Texas Instruments Incorporated
3
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
5 Device Comparison Table
CURRENT SENSE
AMPLIFIERS
DEVICE
VARIANT(1)
BUCK REGULATOR(1)
INTERFACE(1)
DRV8320H
DRV8320S
DRV8320RH
DRV8320RS
DRV8323H
DRV8323S
DRV8323RH
DRV8323RS
Hardware
SPI
DRV8320
None
0
3
Hardware
SPI
DRV8320R
DRV8323
600 mA
None
Hardware
SPI
Hardware
SPI
DRV8323R
600 mA
(1) For more information on the device name and device options, see the 器件命名规则 section. For additional details, see the Architecture
for Brushless-DC Gate Drive Systems application report.
6 Pin Configuration and Functions
DRV8320H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
DRV8320S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
CPH
VCP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DVDD
AGND
ENABLE
NC
CPH
VCP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DVDD
AGND
ENABLE
nSCS
SCLK
SDI
VM
VM
VDRAIN
GHA
VDRAIN
GHA
Thermal
Pad
Thermal
Pad
VDS
SHA
IDRIVE
MODE
nFAULT
SHA
GLA
GLA
SDO
SLA
SLA
nFAULT
Not to scale
Not to scale
Pin Functions—32-Pin DRV8320 Devices
DESCRIPTION
PIN
NO.
TYPE(1)
NAME
DRV8320H
DRV8320S
AGND
CPH
CPL
23
1
23
1
PWR
PWR
PWR
Device analog ground. Connect to system ground.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
32
32
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
DVDD
24
22
24
22
PWR
I
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs pulse can be used
to reset fault conditions.
ENABLE
GHA
GHB
GHC
5
5
O
O
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
12
13
12
13
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
4
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Pin Functions—32-Pin DRV8320 Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8320H
DRV8320S
GLA
7
7
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Device power ground. Connect to system ground.
GLB
10
15
19
25
27
29
26
28
30
18
21
17
—
31
—
—
—
6
10
15
—
25
27
29
26
28
30
—
—
17
21
31
20
19
18
6
O
GLC
O
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
I
I
I
I
I
I
I
I
NC
nFAULT
nSCS
PGND
SCLK
SDI
OD
I
PWR
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
SDO
SHA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
I
SHB
11
14
8
11
14
8
I
SHC
I
SLA
I
SLB
9
9
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
16
2
16
2
I
Low-side source sense input. Connect to the low-side power MOSFET source.
VCP
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
4
4
I
I
20
—
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VM
3
3
PWR
PWR
Thermal Pad
Must be connected to ground
Copyright © 2017–2018, Texas Instruments Incorporated
5
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
DRV8320RH RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
DRV8320RS RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
PGND
CPL
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
INHB
PGND
CPL
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
INHB
INLA
INLA
CPH
INHA
CPH
INHA
DVDD
AGND
ENABLE
nSCS
SCLK
SDI
VCP
DVDD
AGND
ENABLE
NC
VCP
VM
VM
Thermal
Pad
Thermal
Pad
VDRAIN
GHA
SHA
VDRAIN
GHA
SHA
VDS
GLA
IDRIVE
MODE
GLA
SLA
SLA
SDO
Not to scale
Not to scale
Pin Functions—40-Pin DRV8320R Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8320RH
DRV8320RS
AGND
BGND
CB
26
34
35
3
26
34
35
3
PWR
PWR
PWR
PWR
PWR
Device analog ground. Connect to system ground.
Buck regulator ground. Connect to system ground.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
CPH
CPL
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
2
2
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
DVDD
27
25
27
25
PWR
I
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
FB
40
7
40
7
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device ground. Connect to system ground.
GHA
GHB
GHC
GLA
O
14
15
9
14
15
9
O
O
O
GLB
12
17
19
22
28
30
32
29
31
33
21
24
37
20
12
17
19
—
28
30
32
29
31
33
—
—
37
20
O
GLC
O
GND
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
PWR
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
I
I
I
I
I
I
I
NC
NC
OD
NC
nFAULT
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
6
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Pin Functions—40-Pin DRV8320R Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8320RH
DRV8320RS
nSCS
—
24
I
I
Serial chip select. A logic low on this pin enables serial interface communication.
Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V to
disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
nSHDN
39
39
PGND
SCLK
SDI
1
1
PWR
Device power ground. Connect to system ground.
—
—
—
8
23
22
21
8
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
SDO
SHA
SHB
SHC
SLA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
I
13
16
10
11
18
36
4
13
16
10
11
18
36
4
I
High-side source sense input. Connect to the high-side power MOSFET source.
I
High-side source sense input. Connect to the high-side power MOSFET source.
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SW
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VCP
VDRAIN
VDS
VIN
PWR
6
6
I
I
23
38
—
38
PWR
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VM
5
5
PWR
PWR
Thermal Pad
Must be connected to ground
DRV8323H RTA Package
DRV8323S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
40-Pin WQFN With Exposed Thermal Pad
Top View
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
ENABLE
GAIN
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
ENABLE
nSCS
SCLK
SDI
VCP
VDS
VCP
VM
IDRIVE
MODE
nFAULT
VREF
SOA
VM
VDRAIN
GHA
SHA
VDRAIN
GHA
SHA
SDO
Thermal
Pad
Thermal
Pad
nFAULT
VREF
SOA
GLA
GLA
SPA
SOB
SPA
SOB
SNA
SOC
SNA
SOC
Not to scale
Not to scale
Pin Functions—40-Pin DRV8323 Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8323H
DRV8323S
AGND
CAL
32
31
2
32
31
2
PWR
I
Device analog ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPH
PWR
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
Copyright © 2017–2018, Texas Instruments Incorporated
7
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions—40-Pin DRV8323 Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8323H
DRV8323S
CPL
1
1
PWR
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
R 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
DVDD
33
30
33
30
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
I
GAIN
GHA
GHB
GHC
GLA
29
6
—
6
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Device power ground. Connect to system ground.
O
15
16
8
15
16
8
O
O
O
GLB
13
18
27
34
36
38
35
37
39
26
25
—
40
—
—
—
7
13
18
—
34
36
38
35
37
39
—
25
29
40
28
27
26
7
O
GLC
O
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
nFAULT
nSCS
PGND
SCLK
SDI
I
I
I
I
I
I
I
I
OD
I
PWR
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
SDO
SHA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier output.
I
I
SHB
14
17
10
11
20
23
22
21
14
17
10
11
20
23
22
21
SHC
I
SNA
I
SNB
I
SNC
I
SOA
O
O
O
SOB
Current sense amplifier output.
SOC
Current sense amplifier output.
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
SPA
SPB
SPC
9
9
I
I
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
12
19
12
19
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
VCP
3
5
3
5
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
I
28
—
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VM
4
4
PWR
Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between
the VREF and AGND pins.
VREF
24
24
PWR
PWR
Thermal Pad
Must be connected to ground
8
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
DRV8323RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8323RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
FB
PGND
CPL
1
36
DVDD
AGND
CAL
FB
PGND
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
DVDD
AGND
CAL
2
35
34
33
32
31
30
29
28
27
26
25
2
3
3
CPH
4
ENABLE
GAIN
CPH
4
ENABLE
nSCS
SCLK
SDI
VCP
5
VCP
5
VM
6
VDS
VM
6
Thermal
Pad
Thermal
Pad
VDRAIN
GHA
SHA
7
IDRIVE
MODE
nFAULT
DGND
VREF
SOA
VDRAIN
GHA
SHA
7
8
8
SDO
9
9
nFAULT
DGND
VREF
SOA
GLA
10
11
12
GLA
10
11
12
SPA
SPA
SNA
SNA
Not to scale
Not to scale
Pin Functions—48-Pin DRV8323R Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8323RH
DRV8323RS
AGND
BGND
CAL
35
43
34
44
4
35
43
34
44
4
PWR
PWR
I
Device analog ground. Connect to system ground.
Buck regulator ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
CB
PWR
PWR
PWR
PWR
CPH
CPL
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
Device ground. Connect to system ground.
3
3
DGND
27
27
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
DVDD
36
33
36
33
PWR
I
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
FB
1
1
I
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GAIN
GHA
GHB
GHC
GLA
32
8
—
8
O
O
O
O
O
O
I
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
17
18
10
15
20
30
37
39
41
38
40
42
29
46
28
17
18
10
15
20
—
37
39
41
38
40
42
—
46
28
GLB
GLC
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
I
I
I
I
I
I
I
NC
OD
nFAULT
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
Copyright © 2017–2018, Texas Instruments Incorporated
9
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions—48-Pin DRV8323R Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8323RH
DRV8323RS
nSCS
—
32
I
I
Serial chip select. A logic low on this pin enables serial interface communication.
Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V
to disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
nSHDN
48
48
PGND
SCLK
SDI
2
2
PWR
Device power ground. Connect to system ground.
—
—
—
9
31
30
29
9
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier input. Connect to the low-side of the current shunt resistor.
Current sense amplifier output.
I
SDO
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
OD
I
I
16
19
12
13
22
25
24
23
16
19
12
13
22
25
24
23
I
I
I
I
O
O
O
Current sense amplifier output.
Current sense amplifier output.
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
SPA
SPB
SPC
11
14
21
11
14
21
I
I
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor.
SW
45
5
45
5
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCP
VDRAIN
VDS
VIN
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
7
7
I
I
31
47
—
47
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VM
6
6
PWR
Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between
the VREF and AGND pins.
VREF
26
26
PWR
PWR
Thermal Pad
Must be connected to ground
10
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted)(1)
MIN
MAX
UNIT
GATE DRIVER
Power supply pin voltage (VM)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
65
0.3
V
V
V
V
V
V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
MOSFET drain sense pin voltage (VDRAIN)
Charge pump pin voltage (CPH, VCP)
65
VVM + 13.5
VVM
Charge pump negative-switching pin voltage (CPL)
Internal logic regulator pin voltage (DVDD)
3.8
Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS,
SCLK, SDI, SDO, VDS)
–0.3
5.75
V
Continuous high-side gate drive pin voltage (GHx)
Transient 200-ns high-side gate drive pin voltage (GHx)
High-side gate drive pin voltage with respect to SHx (GHx)
Continuous high-side source sense pin voltage (SHx)
Transient 200-ns high-side source sense pin voltage (SHx)
Continuous low-side gate drive pin voltage (GLx)
Gate drive pin source current (GHx, GLx)
Gate drive pin sink current (GHx, GLx)
Continuous low-side source sense pin voltage (SLx)
Transient 200-ns low-side source sense pin voltage (SLx)
Continuous input pin voltage (SNx, SPx)
Transient 200-ns input pin voltage (SNx, SPx)
Reference input pin voltage (VREF)
–5(2)
–7
VVCP + 0.5
VVCP + 0.5
13.5
V
V
V
V
V
V
A
A
V
V
V
V
V
V
–0.3
–5(2)
–7
VVM + 5
VVM + 7
13.5
–0.5
Internally limited
Internally limited
–1
1
–3
–1
3
1
3
–3
–0.3
–0.3
5.75
output pin voltage (SOx)
VVREF + 0.3
BUCK REGULATOR
Power supply pin voltage (VIN)
–0.3
–0.3
–0.3
–0.3
–0.3
–2
65
VVIN
7
V
V
V
V
V
V
Shutdown control pin voltage (nSHDN)
Voltage feedback pin voltage (FB)
Bootstrap pin voltage with respect to SW (CB)
Switching node pin voltage (SW)
7
VVIN
VVIN
Switching node pin voltage less than 30-ns transients (SW)
DRV832x
Operating junction temperature, TJ
–40
–65
150
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Continuous high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute maximum of
65 V on VM. At 60 V and lower, the full specification of –5 V continuous on GHx and SHx is allowable.
7.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
Copyright © 2017–2018, Texas Instruments Incorporated
11
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
7.3 Recommended Operating Conditions
at TA = –40°C to +125°C (unless otherwise noted)
MIN
MAX
UNIT
GATE DRIVER
VVM
Power supply voltage (VM)
6
0
60
V
V
Input voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS,
SCLK, SDI, VDS)
VI
5.5
fPWM
Applied PWM signal (INHx, INLx)
High-side average gate drive current (GHx)
Low-side average gate drive current (GLx)
External load current (DVDD)
0
0
0
0
3
0
0
0
200(1)
25(1)
25(1)
30(1)
5.5
kHz
mA
mA
mA
V
IGATE_HS
IGATE_LS
IDVDD
VVREF
ISO
Reference voltage input (VREF)
output current (SOx)
5
mA
V
VOD
Open drain pullup voltage (nFAULT, SDO)
Open drain output current (nFAULT, SDO)
5.5
IOD
5
mA
BUCK REGULATOR
VVIN
Power supply voltage (VIN)
4
0
60
60
V
V
VnSHDN
DRV832x
TA
Shutdown control input voltage (nSHDN)
Operating ambient temperature
–40
125
°C
(1) Power dissipation and thermal limits must be observed
7.4 Thermal Information
DRV832x
RTV
(WQFN)
RHA
(VQFN)
RTA
(WQFN)
RGZ
(VQFN)
THERMAL METRIC(1)
UNIT
32 PINS
32.9
15.8
6.8
40 PINS
30.1
16.7
9.9
40 PINS
32.1
11
48 PINS
26.6
13.9
9.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
7.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
0.5
0.1
0.3
ψJB
6.8
9.9
7.1
9.1
RθJC(bot) Junction-to-case (bottom) thermal resistance
2.1
2.2
2.1
2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
12
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
7.5 Electrical Characteristics
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (DVDD, VCP, VM)
IVM
VM operating supply current
VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V
ENABLE = 0 V, VVM = 24 V, TA = 25°C
ENABLE = 0 V, VVM = 24 V, TA = 125°C(1)
ENABLE = 0 V period to reset faults
VVM > VUVLO, ENABLE = 3.3 V to outputs ready
ENABLE = 0 V to device sleep mode
IDVDD = 0 to 30 mA
10.5
12
14
20
50
40
1
mA
µA
IVMQ
VM sleep mode supply current
(1)
tRST
Reset pulse time
Turnon time
8
µs
ms
ms
V
tWAKE
tSLEEP
VDVDD
Turnoff time
1
DVDD regulator voltage
3
8.4
6.3
5.4
4
3.3
11
9
3.6
12.5
10
8
VVM = 13 V, IVCP = 0 to 25 mA
VVM = 10 V, IVCP = 0 to 20 mA
VCP operating voltage
with respect to VM
VVCP
V
VVM = 8 V, IVCP = 0 to 15 mA
7
VVM = 6 V, IVCP = 0 to 10 mA
5
6
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0
0.8
5.5
V
V
1.5
100
mV
µA
µA
kΩ
ns
VVIN = 0 V
–5
5
IIH
VVIN = 5 V
50
100
150
70
RPD
tPD
To AGND
INHx/INLx transition to GHx/GLx transition
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Pullup resistance
Tied to AGND
0
1.2
2
V
V
VI2
45 kΩ ± 5% to tied AGND
Hi-Z
VI3
V
VI4
Tied to DVDD
3.3
50
84
V
RPU
RPD
Internal pullup to DVDD
Internal pulldown to AGND
kΩ
kΩ
Pulldown resistance
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1
VI2
VI3
VI4
VI5
VI6
VI7
RPU
RPD
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Input mode 5 voltage
Input mode 6 voltage
Input mode 7 voltage
Pullup resistance
Tied to AGND
0
0.5
1.1
1.65
2.2
2.8
3.3
73
V
V
18 kΩ ± 5% tied to AGND
75 kΩ ± 5% tied to AGND
Hi-Z
V
V
75 kΩ ± 5% tied to DVDD
18 kΩ ± 5% tied to DVDD
Tied to DVDD
V
V
V
Internal pullup to DVDD
Internal pulldown to AGND
kΩ
kΩ
Pulldown resistance
73
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL
IOZ
Output logic low voltage
IO = 5 mA
VO = 5 V
0.1
2
V
Output high impedance leakage
–2
µA
(1) Specified by design and characterization data
Copyright © 2017–2018, Texas Instruments Incorporated
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DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
PARAMETER
GATE DRIVERS (GHx, GLx)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVM = 13 V, IVCP = 0 to 25 mA
VVM = 10 , IVCP = 0 to 20 mA
VVM = 8 V, IVCP = 0 to 15 mA
VVM = 6 V, IVCP = 0 to 10 mA
VVM = 12 V, IVGLS = 0 to 25 mA
VVM = 10 V, IVGLS = 0 to 20 mA
VVM = 8 V, IVGLS = 0 to 15 mA
VVM = 6 V, IVGLS = 0 to 10 mA
DEAD_TIME = 00b
8.4
6.3
5.4
4
11
9
12.5
10
V
High-side gate drive voltage
with respect to SHx
(1)
VGSH
7
8
5
6
9
11
12
7.5
5.5
4
9
10
V
Low-side gate drive voltage
with respect to PGND
(1)
VGSL
7
8
5
6
50
DEAD_TIME = 01b
100
200
400
100
500
1000
2000
4000
4000
10
SPI Device
Gate drive
dead time
tDEAD
DEAD_TIME = 10b
ns
DEAD_TIME = 11b
H/W Device
SPI Device
H/W Device
TDRIVE = 00b
TDRIVE = 01b
TDRIVE = 10b
TDRIVE = 11b
Peak current
gate drive time
tDRIVE
ns
IDRIVEP_HS or IDRIVEP_LS = 0000b
IDRIVEP_HS or IDRIVEP_LS = 0001b
IDRIVEP_HS or IDRIVEP_LS = 0010b
IDRIVEP_HS or IDRIVEP_LS = 0011b
IDRIVEP_HS or IDRIVEP_LS = 0100b
IDRIVEP_HS or IDRIVEP_LS = 0101b
IDRIVEP_HS or IDRIVEP_LS = 0110b
IDRIVEP_HS or IDRIVEP_LS = 0111b
IDRIVEP_HS or IDRIVEP_LS = 1000b
IDRIVEP_HS or IDRIVEP_LS = 1001b
IDRIVEP_HS or IDRIVEP_LS = 1010b
IDRIVEP_HS or IDRIVEP_LS = 1011b
IDRIVEP_HS or IDRIVEP_LS = 1100b
IDRIVEP_HS or IDRIVEP_LS = 1101b
IDRIVEP_HS or IDRIVEP_LS = 1110b
IDRIVEP_HS or IDRIVEP_LS = 1111b
IDRIVE = Tied to AGND
30
60
80
120
140
170
190
260
330
370
440
570
680
820
1000
10
SPI Device
Peak source
gate current
IDRIVEP
mA
IDRIVE = 18 kΩ ± 5% tied to AGND
IDRIVE = 75 kΩ ± 5% tied to AGND
30
60
H/W Device IDRIVE = Hi-Z
IDRIVE = 75 kΩ ± 5% tied to DVDD
120
260
570
1000
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
14
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
20
MAX UNIT
IDRIVEN_HS or IDRIVEN_LS = 0000b
IDRIVEN_HS or IDRIVEN_LS = 0001b
IDRIVEN_HS or IDRIVEN_LS = 0010b
IDRIVEN_HS or IDRIVEN_LS = 0011b
IDRIVEN_HS or IDRIVEN_LS = 0100b
IDRIVEN_HS or IDRIVEN_LS = 0101b
IDRIVEN_HS or IDRIVEN_LS = 0110b
IDRIVEN_HS or IDRIVEN_LS = 0111b
IDRIVEN_HS or IDRIVEN_LS = 1000b
IDRIVEN_HS or IDRIVEN_LS = 1001b
IDRIVEN_HS or IDRIVEN_LS = 1010b
IDRIVEN_HS or IDRIVEN_LS = 1011b
IDRIVEN_HS or IDRIVEN_LS = 1100b
IDRIVEN_HS or IDRIVEN_LS = 1101b
IDRIVEN_HS or IDRIVEN_LS = 1110b
IDRIVEN_HS or IDRIVEN_LS = 1111b
IDRIVE = Tied to AGND
60
120
160
240
280
340
380
520
660
740
880
1140
1360
1640
2000
20
SPI Device
Peak sink
gate current
IDRIVEN
mA
IDRIVE = 18 kΩ ± 5% tied to AGND
IDRIVE = 75 kΩ ± 5% tied to AGND
60
120
240
520
1140
2000
10
H/W Device IDRIVE = Hi-Z
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
Source current after tDRIVE
Sink current after tDRIVE
IHOLD
Gate holding current
mA
50
ISTRONG
ROFF
Gate strong pulldown current
Gate hold off resistor
GHx to SHx and GLx to PGND
GHx to SHx and GLx to PGND
2
A
150
kΩ
CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b
4.85
9.7
5
10
5.15
10.3
20.6
CSA_GAIN = 01b
SPI Device
H/W Device
CSA_GAIN = 10b
19.4
38.8
4.85
9.7
20
CSA_GAIN = 11b
40
41.2
V/V
GCSA
Amplifier gain
GAIN = Tied to AGND
5
5.15
GAIN = 47 kΩ ± 5% tied to AGND
GAIN = Hi-Z
10
10.3
20.6
41.2
19.4
38.8
20
GAIN = Tied to DVDD
40
VO_STEP = 0.5 V, GCSA = 5 V/V
VO_STEP = 0.5 V, GCSA = 10 V/V
VO_STEP = 0.5 V, GVSA = 20 V/V
VO_STEP = 0.5 V, GCSA = 40 V/V
150
300
600
1200
(1)
tSET
Settling time to ±1%
ns
VCOM
VDIFF
VOFF
Common mode input range
Differential mode input range
Input offset error
–0.15
–0.3
–4
0.15
0.3
4
V
V
VSP = VSN = 0 V, CAL = 3.3 V, VREF = 3.3 V
VSP = VSN = 0 V
mV
µV/°C
(1)
VDRIFT
Drift offset
10
VVREF
– 0.25
VLINEAR
SOx output voltage linear range
0.25
V
Copyright © 2017–2018, Texas Instruments Incorporated
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DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0b
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1b
VVREF – 0.3
VVREF / 2
VVREF / 2
SPI Device
SOx output voltage
bias
VBIAS
V
H/W Device VSP = VSN = 0 V, CAL = 3.3 V
IBIAS
SPx/SNx input bias current
SOx output slew rate
VREF input current
VREF_DIV = 1b
60-pF load
100
3
µA
V/µs
mA
(1)
VSLEW
IVREF
UGB(1)
10
2
VVREF = 5 V
60-pF load
Unity gain bandwidth
1
MHz
PROTECTION CIRCUITS
VM falling, UVLO report
VM rising, UVLO recovery
Rising to falling threshold
VM falling, UVLO report
5.4
5.6
5.8
200
10
5.8
6
VUVLO
VM undervoltage lockout
V
5.6
VUVLO_HYS
tUVLO_DEG
VM undervoltage hysteresis
VM undervoltage deglitch time
mV
µs
Charge pump undervoltage
lockout
VCPUV
VCP falling, CPUV report
VVM + 2.8
V
V
Positive clamping voltage
Negative clamping voltage
VDS_LVL = 0000b
15
16.5
–0.7
0.06
0.13
0.2
18
VGS_CLAMP
High-side gate clamp
VDS_LVL = 0001b
VDS_LVL = 0010b
VDS_LVL = 0011b
0.26
0.31
0.45
0.53
0.6
VDS_LVL = 0100b
VDS_LVL = 0101b
VDS_LVL = 0110b
VDS_LVL = 0111b
SPI Device
VDS_LVL = 1000b
0.68
0.75
0.94
1.13
1.3
VDS_LVL = 1001b
VDS_LVL = 1010b
VDS overcurrent
trip voltage
VVDS_OCP
VDS_LVL = 1011b
V
VDS_LVL = 1100b
VDS_LVL = 1101b
1.5
VDS_LVL = 1110b
1.7
VDS_LVL = 1111b
1.88
0.06
0.13
0.26
0.6
VDS = Tied to AGND
VDS = 18 kΩ ± 5% tied to AGND
VDS = 75 kΩ ± 5% tied to AGND
H/W Device VDS = Hi-Z
VDS = 75 kΩ ± 5% tied to DVDD
VDS = 18 kΩ ± 5% tied to DVDD
VDS = Tied to DVDD
OCP_DEG = 00b
1.13
1.88
Disabled
2
OCP_DEG = 01b
4
VDS and VSENSE
SPI Device
tOCP_DEG
overcurrent
OCP_DEG = 10b
6
µs
deglitch time
OCP_DEG = 11b
8
H/W Device
4
16
Copyright © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25
0.5
0.75
1
MAX UNIT
SEN_LVL = 00b
SEN_LVL = 01b
SEN_LVL = 10b
SEN_LVL = 11b
SPI Device
VSENSE overcurrent
trip voltage
VSEN_OCP
V
H/W Device
SPI Device
H/W Device
1
TRETRY = 0b
TRETRY = 1b
4
ms
μs
Overcurrent retry
time
tRETRY
50
4
ms
(1)
TOTW
Thermal warning temperature
Thermal shutdown temperature
Thermal hysteresis
Die temperature, TJ
Die temperature, TJ
Die temperature, TJ
130
150
150
170
20
165
185
°C
°C
°C
(1)
TOTSD
(1)
THYS
BUCK REGULATOR SUPPLY (VIN)
InSHDN Shutdown supply current
IQ
VnSHDN = 0 V
1
3
4
µA
µA
Operating quiescent current
VVIN = 12 V, no load; not switching
VIN Rising
28
VIN undervoltage lockout
threshold
VVIN_UVLO
V
VIN Falling
3
BUCK REGULATOR SHUTDOWN (nSHDN)
VnSHDN_TH
Rising nSHDN threshold
1.05
1.25
–4.2
–1
1.38
V
VnSHDN = 2.3 V
VnSHDN = 0.9 V
InSHDN
Input current
µA
µA
InSHDN_HYS
Hysteresis current
–3
BUCK REGULATOR HIGH-SIDE MOSFET
RDS_ON MOSFET on resistance
BUCK REGULATOR VOLTAGE REFERENCE (FB)
VFB Feedback voltage
BUCK REGULATOR CURRENT LIMIT
VVIN = 12 V, VCB to VSW = 5.8 V, TA = 25°C
900
mΩ
0.747 0.765 0.782
V
VVIN = 12 V, TA = 25°C
1200
1700
ILIMIT
Peak current limit
mA
BUCK REGULATOR SWITCHING (SW)
fSW
Switching frequency
Maximum duty cycle
595
700
805
kHz
DMAX
96%
BUCK REGULATOR THERMAL SHUTDOWN
(1)
TSHDN
Thermal shutdown threshold
Thermal shutdown hysteresis
170
10
°C
°C
(1)
THYS
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7.6 SPI Timing Requirements(1)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)
MIN NOM
MAX
UNIT
SPI (nSCS, SCLK, SDI, SDO)
tREADY
tCLK
SPI ready after enable
SCLK minimum period
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
nSCS input setup time
nSCS input hold time
VM > UVLO, ENABLE = 3.3 V
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
50
50
20
30
tCLKH
tCLKL
tSU_SDI
tH_SDI
tD_SDO
tSU_nSCS
tH_nSCS
tHI_nSCS
tDIS_nSCS
SCLK high to SDO valid
30
50
50
nSCS minimum high time before active low
nSCS disable time nSCS high to SDO high impedance
400
10
(1) Specified by design and characterization data
tHI_nSCS tSU_nSCS
tH_nSCS
nSCS
tCLK
SCLK
tCLKH
tCLKL
X
MSB
LSB
X
SDI
tSU_SDI
tH_SDI
Z
MSB
LSB
Z
SDO
tD_SDO
tDIS_nSCS
Figure 1. SPI Slave Mode Timing Diagram
18
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
7.7 Typical Characteristics
16
14
12
10
8
15
14
13
12
11
10
9
6
8
4
7
TA = -40èC
TA = 25èC
TA = 125èC
VVM = 6 V
VVM = 24 V
VVM = 60 V
2
6
0
5
0
10
20
30
40
50
60
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Ambient Temperature (°C)
D001
D002
Figure 2. Supply Current Over VM
Figure 3. Supply Current Over Temperature
24
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
6
6
VVM = 6 V
VVM = 24 V
VVM = 60 V
TA = -40èC
4
4
TA = 25èC
2
2
TA = 125èC
0
0
0
10
20
30
40
50
60
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Ambient Temperature (èC)
D003
D004
Figure 4. Sleep Current Over VM
Figure 5. Sleep Current Over Temperature
4
4
3.75
3.5
3.25
3
TA = -40èC
TA = -40èC
TA = 25èC
TA = 125èC
TA = 25èC
3.75
3.5
3.25
3
TA = 125èC
2.75
2.5
2.25
2
2.75
2.5
2.25
2
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Supply Voltage (V)
Supply Voltage (V)
D005
D006
0-mA load
Figure 6. DVDD Voltage Over VM
30-mA load
Figure 7. DVDD Voltage Over VM
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Typical Characteristics (continued)
12
14
12
10
8
10
8
6
6
4
4
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 13 V
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 13 V
2
2
0
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Load Current (mA)
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (°C)
D007
D008
0-mA load
Figure 9. VCP Voltage Over Temperature
Figure 8. VCP Voltage Over Load
20
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DRV8323, DRV8323R
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
8 Detailed Description
8.1 Overview
The DRV832x family of devices is an integrated 6 to 60-V gate driver for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent half-
bridge gate drivers, charge pump, and linear regulator for the supply voltages of the high-side and low-side gate
drivers.The device also integrates optional triple current shunt (or current sense) amplifiers and an optional
600-mA buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring the
various device settings and reading fault diagnostic information through an external controller. Alternatively, a
hardware interface (H/W) option allows for configuring the most common settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents with a 25-mA average output current. A doubler charge pump generates the
supply voltage of the high-side gate drive. This charge pump architecture regulates the VCP output to VVM
+
11 V. The supply voltage of the low-side gate driver is generated using a linear regulator from the VM power
supply that regulates to 11 V. A Smart Gate Drive architecture provides the ability to dynamically adjust the
strength of the gate drive output current which lets the gate driver control the VDS switching speed of the power
MOSFET. This feature lets the user remove the external gate drive resistors and diodes, reducing the component
count in the bill of materials (BOM), cost, and area of the printed circuit board (PCB). The architecture also uses
an internal state machine to protect against short-circuit events in the gate driver, control the half-bridge dead
time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The DRV8323 and DRV8323R devices integrate three bidirectional current sense amplifiers for monitoring the
current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the
current sense amplifier can be adjusted through the SPI or hardware interface. The SPI method provides
additional flexibility to adjust the output bias point.
The DRV8320R and DRV8323R devices integrate a 600-mA buck regulator that can be used to power an
external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can
use either the same or a different power supply than the gate driver.
In addition to the high level of device integration, the DRV832x family of devices provides a wide range of
integrated protection features. These features include power supply undervoltage lockout (UVLO), charge pump
undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate driver short-circuit detection (GDF), and
overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed
information available in the SPI registers on the SPI device version.
The DRV832x family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN sizes
are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin package.
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www.ti.com.cn
8.2 Functional Block Diagram
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
GLA
SLA
CPL
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
VCP
HS
30 mA
DVDD
AGND
DVDD
Linear
Regulator
GHB
SHB
1 …F
Power
PGND
VGLS
LS
Digital
Core
GLB
SLB
ENABLE
INHA
INLA
Gate Driver
VM
VCP
HS
Smart Gate
Drive
GHC
SHC
INHB
INLB
Protection
VGLS
LS
Control
Inputs
GLC
SLC
INHC
INLC
VCC
Gate Driver
Fault Output
R
PU
nFAULT
MODE
IDRIVE
VDS
Copyright © 2017, Texas Instruments Incorporated
Figure 10. Block Diagram for DRV8320H
22
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DRV8323, DRV8323R
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
GLA
SLA
CPL
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
30 mA
DVDD
AGND
VCP
HS
DVDD
Linear
Regulator
GHB
SHB
1 …F
Power
PGND
VGLS
LS
Digital
Core
GLB
SLB
ENABLE
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VM
VCP
HS
Smart Gate
Drive
GHC
SHC
Control
Inputs
Protection
VGLS
LS
GLC
SLC
VCC
Gate Driver
Fault Output
VCC
SDI
R
PU
SPI
nFAULT
R
PU
SDO
SCLK
nSCS
Copyright © 2017, Texas Instruments Incorporated
Figure 11. Block Diagram for DRV8320S
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www.ti.com.cn
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
CPL
GLA
SLA
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
30 mA
DVDD
VCP
HS
DVDD
Linear
Regulator
GHB
SHB
1 …F
AGND
PGND
Power
VGLS
LS
Digital
Core
GLB
SLB
ENABLE
INHA
Gate Driver
INLA
VM
VCP
HS
Smart Gate
Drive
GHC
SHC
INHB
Protection
INLB
Control
Inputs
VGLS
LS
GLC
SLC
INHC
INLC
VCC
Gate Driver
Fault Output
MODE
R
PU
nFAULT
IDRIVE
VDS
VIN
VIN
nSHDN
BGND
CB
0.1 µF
L
OUT
SW
600 mA
Buck Regulator
(LMR16006X)
C
IN
C
D
OUT
OUT
FB
R
FB1
R
FB2
Copyright © 2017, Texas Instruments Incorporated
Figure 12. Block Diagram for DRV8320RH
24
Copyright © 2017–2018, Texas Instruments Incorporated
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
GLA
SLA
CPL
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
30 mA
DVDD
AGND
DVDD
Linear
Regulator
VCP
HS
1 …F
GHB
SHB
Power
PGND
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
Gate Driver
VM
INHB
INLB
VCP
HS
Smart Gate
Drive
Control
Inputs
GHC
SHC
Protection
INHC
INLC
SDI
VGLS
LS
GLC
SLC
VCC
VCC
Gate Driver
Fault Output
SPI
R
PU
R
SDO
PU
nFAULT
SCLK
nSCS
VIN
VIN
nSHDN
BGND
CB
SW
FB
0.1 µF
D
L
OUT
600 mA
Buck Regulator
(LMR16006X)
C
IN
OUT
C
OUT
R
FB1
R
FB2
Copyright © 2017, Texas Instruments Incorporated
Figure 13. Block Diagram for DRV8320RS
Copyright © 2017–2018, Texas Instruments Incorporated
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DRV8323, DRV8323R
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www.ti.com.cn
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
GLA
CPL
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
30 mA
DVDD
AGND
PGND
VCP
HS
DVDD
Linear
Regulator
GHB
SHB
1 …F
Power
VGLS
LS
Digital
Core
GLB
ENABLE
INHA
Gate Driver
INLA
VM
VCP
HS
Smart Gate
Drive
GHC
SHC
INHB
Protection
INLB
Control
Inputs
VGLS
LS
GLC
INHC
INLC
VCC
PU
Gate Driver
Fault Output
R
MODE
nFAULT
IDRIVE
VDS
GAIN
VCC
SPC
SNC
VREF
AV
AV
AV
R
SEN
0.1 …F
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
R
SEN
SPA
SNA
CAL
R
SEN
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Block Diagram for DRV8323H
26
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DRV8320, DRV8320R
DRV8323, DRV8323R
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
CPL
GLA
VGLS
VGLS
Gate Driver
Linear
Regulator
VM
30 mA
DVDD
AGND
VCP
HS
DVDD
Linear
Regulator
1 …F
GHB
Power
SHB
GLB
PGND
VGLS
LS
ENABLE
Digital
Core
INHA
Gate Driver
INLA
INHB
INLB
VM
VCP
HS
Smart Gate
Drive
GHC
Control
Inputs
Protection
SHC
GLC
VGLS
LS
INHC
INLC
VCC
Gate Driver
Fault Output
VCC
R
SDI
PU
SPI
R
PU
nFAULT
SDO
SCLK
nSCS
VCC
SPC
VREF
SOC
SOB
SOA
R
AV
AV
AV
SEN
SNC
0.1 …F
SPB
Output
Offset
Bias
R
SEN
SNB
SPA
SNA
CAL
R
SEN
Copyright © 2017, Texas Instruments Incorporated
Figure 15. Block Diagram for DRV8323S
Copyright © 2017–2018, Texas Instruments Incorporated
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DRV8320, DRV8320R
DRV8323, DRV8323R
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www.ti.com.cn
Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
HS
GHA
SHA
VCP
1 …F
>10 …F 0.1 …F
VCP
Charge
Pump
CPH
VGLS
LS
47 nF
GLA
CPL
VGLS
VGLS
Gate Driver
DGND
Linear
Regulator
VM
VCP
HS
30 mA
DVDD
AGND
PGND
DVDD
Linear
Regulator
GHB
SHB
1 …F
Power
VGLS
LS
Digital
Core
GLB
ENABLE
INHA
INLA
Gate Driver
VM
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
INHB
INLB
VGLS
LS
GLC
Control
Inputs
INHC
INLC
VCC
PU
Gate Driver
Fault Output
R
nFAULT
MODE
IDRIVE
VDS
GAIN
VCC
SPC
SNC
VREF
R
SEN
AV
AV
AV
0.1 …F
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
R
SEN
SPA
SNA
CAL
R
SEN
VIN
VIN
CB
SW
FB
L
OUT
R
0.1 µF
600 mA
C
nSHDN
Buck Regulator
(LMR16006X)
C
IN
OUT
FB1
D
OUT
BGND
R
FB2
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Block Diagram for DRV8323RH
28
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DRV8320, DRV8320R
DRV8323, DRV8323R
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Functional Block Diagram (continued)
VM
VM
VM
VDRAIN
VCP
HS
VCP
GHA
SHA
1 …F
>10 …F 0.1 …F
VCP
Charge
CPH
Pump
47 nF
VGLS
LS
CPL
GLA
VGLS
DGND
VGLS
Linear
Gate Driver
Regulator
DVDD
AGND
30 mA
VM
DVDD
Linear
Regulator
VCP
HS
1 …F
GHB
Power
PGND
SHB
GLB
VGLS
LS
ENABLE
Digital
Core
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VM
VCP
HS
Smart Gate
Drive
Control
Inputs
GHC
Protection
SHC
GLC
VGLS
LS
VCC
Gate Driver
Fault Output
VCC
PU
SDI
R
PU
SPI
R
nFAULT
SDO
SCLK
nSCS
VCC
SPC
SNC
AV
AV
AV
R
SEN
VREF
SOC
0.1 …F
SPB
SNB
Output
Offset
Bias
SOB
SOA
R
SEN
SPA
SNA
CAL
R
SEN
VIN
CB
SW
FB
VIN
nSHDN
BGND
L
OUT
0.1 µF
600 mA
Buck Regulator
(LMR16006X)
C
OUT
R
C
IN
FB1
D
OUT
R
FB2
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Block Diagram for DRV8323RS
Copyright © 2017–2018, Texas Instruments Incorporated
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8.3 Feature Description
Table 1 lists the recommended values of the external components for the gate driver and the buck regulator.
Table 1. DRV832x External Components
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
GATE DRIVER AND SENSE AMPLIFIER
CVM1
CVM2
VM
VM
PGND
PGND
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10 µF, VM-rated capacitor
X5R or X7R, 16-V, 1-µF capacitor
X5R or X7R, 47-nF, VM-rated capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
Pullup resistor
CVCP
VCP
VM
CSW
CPH
CPL
CDVDD
RnFAULT
RSDO
DVDD
VCC(1)
VCC(1)
IDRIVE
VDS
AGND
nFAULT
SDO
Pullup resistor
RIDRIVE
RVDS
RMODE
RGAIN
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DVDD
AGND or DGND
SNA and PGND
SNB and PGND
SNC and PGND
DRV832x hardware interface
DRV832x hardware interface
DRV832x hardware interface
DRV832x hardware interface
X5R or X7R, 0.1-μF, VREF-rated capacitor
Sense shunt resistor
MODE
GAIN
VREF
SPA
CVREF
RASENSE
RBSENSE
RCSENSE
BUCK REGULATOR
CVIN
SPB
Sense shunt resistor
SPC
Sense shunt resistor
VIN
SW
BGND
CB
X5R or X7R, 1 to 10 µF, VM-rated capacitor
X5R or X7R, 0.1-µF, 16-V capacitor
Schottky diode
CBOOT
DSW
SW
BGND
OUT(2)
BGND
FB
LSW
SW
Output inductor
COUT
OUT(2)
OUT(2)
FB
X5R or X7R, OUT rated capacitor
RFB1
Resistor divider to set buck output voltage
RFB2
BGND
(1) The VCC pin is not a pin on the DRV832x family of devices, but a VCC supply voltage pullup is required for the open-drain outputs,
nFAULT and SDO. These pins can also be pulled up to DVDD.
(2) The OUT pin is not a pin on the DRV8320R and DRV8323R devices, but is the regulated output voltage of the buck regulator after the
output inductor.
8.3.1 Three Phase Smart Gate Drivers
The DRV832x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. A doubler charge pump provides the correct gate bias voltage to the high-
side MOSFET across a wide operating voltage range in addition to providing 100% support of the duty cycle. An
internal linear regulator provides the gate bias voltage for the low-side MOSFETs. The half-bridge gate drivers
can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV832x family of devices implements a Smart Gate Drive architecture which allows the user to
dynamically adjust the gate drive current without requiring external resistors to limit the gate current. Additionally,
this architecture provides a variety of protection features for the external MOSFETs including automatic dead
time insertion, prevent of parasitic dV/dt gate turnon, and gate fault detection.
8.3.1.1 PWM Control Modes
The DRV832x family of devices provides four different PWM control modes to support various commutation and
control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before changing the MODE pin
or PWM_MODE register.
30
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8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 2.
Table 2. 6x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
SHx
Hi-Z
H
0
0
1
1
0
1
0
1
L
H
L
L
H
L
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 3.
Table 3. 3x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
SHx
Hi-Z
L
0
1
1
X
0
1
H
L
L
H
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In 1x PWM mode, the DRV832x family of devices uses 6-step block commutation tables that are stored
internally. This feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from a
simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of
the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to the digital outputs of
the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode
usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode can be
configured to use asynchronous rectification (MOSFET body diode freewheeling) on SPI devices. This
configuration is set using the 1PWM_COM bit in the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB inputs. Tie
the INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin
high if this feature is not required.
Table 4. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
INHC = 0
GATE DRIVE OUTPUTS(1)
INHC = 1
PHASE A
PHASE B PHASE C
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
GHB
GLB
GHC
GLC
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
!PWM
L
L
L
L
L
Stop
Align
L
H
L
H
Align
1
2
3
4
5
6
PWM
!PWM
L
L
H
H
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
!PWM
!PWM
L
L
L
H
L
L
L
L
H
PWM
PWM
L
!PWM
!PWM
L
L
H
L
L
L
H
PWM
!PWM
(1) !PWM is the inverse of the PWM signal.
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DESCRIPTION
Table 5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
INHC = 0
GATE DRIVE OUTPUTS
PHASE B PHASE C
INHC = 1
PHASE A
STATE
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
L
GHB
GLB
L
GHC
GLC
L
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
L
Stop
Align
L
L
H
L
L
H
H
H
L
Align
1
2
3
4
5
6
L
PWM
L
L
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
L
L
L
L
L
L
H
H
L
L
L
PWM
PWM
L
L
L
H
H
L
L
L
PWM
L
L
Figure 18 and Figure 19 show the different possible configurations in 1x PWM mode.
INHA
INLA
INHB
INLB
INHC
INLC
INHA
INLA
INHB
INLB
INHC
INLC
MCU_PWM
PWM
MCU_PWM
MCU_GPIO
MCU_GPIO
PWM
H
STATE0
STATE1
STATE2
DIR
STATE0
STATE1
STATE2
DIR
H
BLDC Motor
BLDC Motor
H
MCU_GPIO
MCU_GPIO
MCU_GPIO
MCU_GPIO
nBRAKE
MCU_GPIO
nBRAKE
Figure 18. 1x PWM—Simple Controller
Figure 19. 1x PWM—Hall Effect Sensor
8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In independent PWM mode, the corresponding input pin independently controls each high-side and low-side gate
driver. This control mode lets the DRV832x family of devices drive separate high-side and low-side loads with
each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and
high-side switches. In this mode, if the system is configured in a half-bridge configuration, turning on both the
high-side and low-side MOSFETs at the same time causes shoot-through.
Table 6. Independent PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
0
0
1
1
0
1
0
1
L
H
H
L
H
H
32
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ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors when
both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible. In this
case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 20.
Disable
+
V
DS œ
VM
VDRAIN
VCP
GHx
Load
HS
INHx
SHx
VGLS
INLx
GLx
LS
Load
Gate Driver
Disable
SLx/SPx
+
V
DSœ
Figure 20. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in Figure 21 or Figure 22. The unused gate driver and the
corresponding input can stay disconnected.
+
+
V
V
DS œ
DS œ
VM
VM
VDRAIN
VDRAIN
VCP
HS
VCP
HS
GHx
SHx
GHx
SHx
Load
INHx
INLx
INHx
INLx
VGLS
LS
VGLS
LS
GLx
GLx
Load
Gate Driver
SLx/SPx
Gate Driver
SLx/SPx
+
+
V
V
DS œ
DS œ
Figure 21. One High-Side Driver
8.3.1.2 Device Interface Modes
Figure 22. One Low-Side Driver
The DRV832x family of devices supports two different interface modes (SPI and hardware) to let the end
application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
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8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that lets an external controller send and receive data with
the DRV832x. This support lets the external controller configure device settings and read detailed fault
information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are described
as follows:
•
The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
the SDI and SDO pins.
•
•
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
•
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV832x.
For more information on the SPI, see the SPI Communication section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are GAIN,
IDRIVE, MODE, and VDS. This conversion lets the application designer configure the most common device
settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the
requirement for an SPI bus from the external controller. General fault information can still be obtained through
the nFAULT pin.
•
•
•
•
The GAIN pin configures the gain of the current sense amplifier.
The IDRIVE pin configures the gate drive current strength.
The MODE pin configures the PWM control mode.
The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
DVDD
RGAIN
DVDD
GAIN
SCLK
SDI
Hardware
Interface
SPI
Interface
DVDD
DVDD
IDRIVE
MODE
VDS
DVDD
VCC
RPU
SDO
nSCS
DVDD
RVDS
Figure 23. SPI
8.3.1.3 Gate Driver Voltage Supplies
Figure 24. Hardware Interface
The voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the
VM voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with
respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed
output voltage of VVM + 11 V and supports an average output current of 25 mA. When VVM is less than 12 V, the
charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V when unloaded. The charge
pump is continuously monitored for undervoltage events to prevent under-driven MOSFET conditions. The
charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the
storage capacitor. Additionally, a X5R or X7R, 47-nF, VM-rated ceramic capacitor is required between the CPH
and CPL pins to act as the flying capacitor.
34
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VM
VM
1 …F
VCP
CPH
VM
Charge
Pump
47 nF
Control
CPL
Figure 25. Charge Pump Architecture
The voltage supply of the low-side gate driver is created using a linear regulator that operates from the VM
voltage supply input. The linear regulator lets the gate driver correctly bias the low-side MOSFET gate with
respect to ground. The linear regulator output is fixed at 11 V and supports an output current of 25 mA.
8.3.1.4 Smart Gate Drive Architecture
The DRV832x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-
side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a Smart Gate Drive architecture to provide additional control of the external
power MOSFETs, additional steps to protect the MOSFETs, and optimal tradeoffs between efficiency and
robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are
described in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive Control
section. Figure 26 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate drive current and TDRIVE gate drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
VM
Control
Inputs
INLx
GHx
SHx
Level
Shifters
150 kꢀ
+
V
GS œ
VGLS
Digital
Core
GLx
Level
Shifters
150 kꢀ
SLx/SPx
PGND
+
V
GS œ
Figure 26. Gate Driver Block Diagram
8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy, and duration of diode
recovery spikes, dV/dt gate turnon resulting in shoot-through, and switching voltage transients related to
parasitics in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET VDS
slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the
MOSFET QGD or Miller charging region. By letting the gate driver adjust the gate current, the gate driver can
effectively control the slew rate of the external power MOSFETs.
The IDRIVE component lets the DRV832x family of devices dynamically switch between gate drive currents
either through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI
devices provide 16 IDRIVE settings ranging from 10-mA to 1-A source and 20-mA to 2-A sink. Hardware interface
devices provide 7 IDRIVE settings within the same ranges. The setting of the gate drive current is delivered to the
gate during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET
turnon or turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. For
additional details on the IDRIVE settings, see the Register Maps section for the SPI devices and the Pin
Diagrams section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate drive state machine that provides automatic dead time insertion
through handshaking between the high-side and low-side gate drivers, parasitic dV/dt gate turnon prevention,
and MOSFET gate fault detection.
The first component of the TDRIVE state machine is automatic dead time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV832x family of devices uses VGS voltage monitors to measure the
MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value.
This feature lets the dead time of the gate driver adjust for variation in the system such as temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on SPI devices.
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The second component of the TDRIVE state machine is parasitic dV/dt gate turnon prevention. To implement this
component, the TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET
gate whenever a MOSFET is switching. The strong pulldown occurs for the TDRIVE duration. This feature helps
remove parasitic charge that couples into the MOSFET gate when the voltage half-bridge switch node slews
rapidly.
The third component of the TDRIVE state machine implements a scheme for gate fault detection to detect pin-to-
pin solder defects, a MOSFET gate failure, or stuck-high or stuck-low voltage condition on a MOSFET gate. This
implementation occurs with a pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When
the gate driver receives a command to change the state of the half-bridge, it starts to monitor the gate voltage of
the external MOSFET. If the VGS voltage has not reached the correct threshold at the end of the tDRIVE period,,
the gate driver reports a fault. To make sure that a false fault is not detected, a tDRIVE time should be selected
that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase
the PWM time and will terminate if another PWM command is received while active. For additional details on the
TDRIVE settings, see the Register Maps section for SPI devices. The hardware interface devices have a fixed
tDRIVE of 4 µs.
Figure 27 shows an example of the TDRIVE state machine in operation.
V
INHx
V
INLx
V
GHx
GHx
tDEAD
IHOLD
tDEAD
IHOLD
I
I
t
I
I
I
STRONG
HOLD
DRIVE
DRIVE
STRONG
HOLD
I
I
t
I
I
DRIVE
HOLD
HOLD
DRIVE
V
GLx
GLx
tDEAD
IHOLD
tDEAD
IHOLD
I
I
I
t
I
STRONG
HOLD
STRONG
DRIVE
I
I
t
I
HOLD
DRIVE
DRIVE
DRIVE
Figure 27. TDRIVE State Machine
8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
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The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current sense amplifiers (DRV8323 and DRV8323R), the low-side VDS monitors measure the voltage between
the SHx and SPx pins. If the current sense amplifier is unused, tie the SP pins to the common ground point of
the external half-bridges. On device options without the current sense amplifiers (DRV8320 and DRV8320R) the
low-side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the reference point of the low-side VDS monitor can be changed between the SPx and SNx
pins if desired with the LS_REF register setting.
The VVDS_OCP threshold is programmable from 0.06 V to 1.88 V. For additional information on the VDS monitor
levels, see the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.
VM
VM
VDRAIN
VDRAIN
+
+
V
+
V
+
DS œ
V
V
DSœ
DSœ
V
V
DSœ
V
V
V
V
VDS_OCP
VDS_OCP
GHx
SHx
GLx
GHx
SHx
GLx
+
+
+
V
+
V
DSœ
DSœ
DSœ
DSœ
VDS_OCP
VDS_OCP
SPx
SLx
0
1
R
SENSE
PGND
SNx
LS_REF
(SPI Only)
PGND
Figure 28. DRV8320 and DRV8320R VDS Monitors
8.3.1.4.5 VDRAIN Sense Pin
Figure 29. DRV8323 and DRV8323R VDS Monitors
The DRV832x family of devices provides a separate sense pin for the common point of the high-side MOSFET
drain. This pin is called VDRAIN. This pin lets the sense line for the overcurrent monitors (VDRAIN) and the
power supply (VM) stay separate and prevent noise on the VDRAIN sense line. This separation also lets
implementation of a small filter on the gate driver supply (VM) or insertion of a boost converter to support lower
voltage operation if desired. Care must still be used when designing the filter or separate supply because VM is
still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH). The VM
supply must not drift too far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
8.3.2 DVDD Linear Voltage Regulator
A 3.3-V, 30-mA linear regulator is integrated into the DRV832x family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for a low-power MCU or other circuitry supporting
low current. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF,
6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 30
mA.
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VM
REF
+
œ
DVDD
AGND
3.3 V, 30 mA
0.1 …F
Figure 30. DVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device by the DVDD linear regulator.
P = VVM - VDVDD ì I
DVDD
(1)
For example, at a VVM of 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in
Equation 2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
8.3.3 Pin Diagrams
Figure 31 shows the input structure for the logic level pins, INHx, INLx, CAL, ENABLE, nSCS, SCLK, and SDI.
The input can be driven with a voltage or external resistor.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
100 kꢀ
Figure 31. Logic-Level Input Pin Structure
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Figure 32 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The
input can be set with an external resistor.
MODE
GAIN
DVDD
STATE
VI4
RESISTANCE
Tied to DVDD
DVDD
Independent 40 V/V
+
50 kꢀ
œ
Hi-Z (>500 kΩ to
1x PWM
3x PWM
6x PWM
20V/V
10 V/V
5 V/V
VI3
VI2
VI1
AGND)
+
84 kꢀ
47 kΩ ±5%
to AGND
œ
Tied to AGND
+
œ
Figure 32. Four Level Input Pin Structure
Figure 33 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.
IDRIVE
1/2 A
VDS
Disabled
+
œ
STATE
VI7
RESISTANCE
Tied to DVDD
570/1140 mA 1.88 V
+
DVDD
DVDD
œ
18 kꢀ ± 5%
VI6
VI5
VI4
VI3
VI2
VI1
to DVDD
260/520 mA
120/240 mA
60/120 mA
30/60 mA
1.13 V
0.60 V
0.26 V
0.13 V
0.06 V
+
75 kꢀ ± 5%
to DVDD
73 kꢀ
œ
Hi-Z (>500 kΩ
to AGND)
73 kꢀ
+
75 kꢀ ± 5%
to AGND
œ
18 kΩ ±5%
to AGND
+
Tied to AGND
œ
+
œ
10/20 mA
Figure 33. Seven Level Input Pin Structure
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Figure 34 shows the structure of the open-drain output pins, nFAULT and SDO. The open-drain output requires
an external pullup resistor to function correctly.
DVDD
R
PU
STATE
No Fault
Fault
STATUS
Inactive
Active
OUTPUT
Active
Inactive
Figure 34. Open-Drain Output Pin Structure
8.3.4 Low-Side Current Sense Amplifiers (DRV8323 and DRV8323R Only)
The DRV8323 and DRV8323R integrate three, high-performance low-side current sense amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current sense amplifiers include features
such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference
pin (VREF). If any of the three current sense amplifiers are not being used, they can be tied off by shorting the
SNx pin to the SPx pin and leaving the SOx pin unconnected. Remember to connect the SPx or SNx pin to the
low-side FET source, so that the overcurrent VDS monitor is still functional
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8323 and DRV8323R outputs an analog voltage equal to the voltage across the SPx
and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels
(5 V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.
VVREF
- VSOx
2
I =
GCSA ì RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
V
CC
œ
R
SENSE
V
+
REF
0.1 …F
R2
R3
R4
R5
½
+
œ
Figure 35. Bidirectional Current Sense Configuration
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SO (V)
V
REF
V
/ 2
VREF
V
LINEAR
SP œ SN (V)
Figure 36. Bidirectional Current Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP œ SN
œ0.3 V
œI × R
V
VREF
œ 0.25 V
V
SO(rangeœ)
V
SO(off)max
/ 2
V
,
OFF
0 V
V
VREF
V
DRIFT
V
SO(off)min
V
SO(range+)
I × R
0.3 V
0.25 V
0 V
Figure 37. Bidirectional Current Sense Regions
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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8323 and DRV8323R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case
the current sense amplifier operates unidirectionally and the SOx pin outputs an analog voltage equal to the
voltage across the SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the
current through the shunt resistor.
VVREF - VSOx
GCSA ì RSENSE
I =
(4)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
œ
R
SENSE
+
V
CC
R2
R3
R4
R5
V
REF
+
0.1 …F
œ
Figure 38. Unidirectional Current-Sense Configuration
SO (V)
V
V
REF
œ 0.3 V
VREF
V
LINEAR
SP œ SN (V)
Figure 39. Unidirectional Current-Sense Output
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I
SP
SN
SO
SO
R
AV
V
REF
V
œ 0.25 V
VREF
V
SO(off)max
SP œ SN
V
,
OFF
0 V
V
œ 0.3 V
VREF
V
DRIFT
V
SO(off)min
V
SO(range)
I × R
0.3 V
0.25 V
0 V
Figure 40. Unidirectional Current-Sense Regions
8.3.4.3 Auto Offset Calibration
To minimize DC offset, the DRV8323 and DRV8323R devices can perform an automatic offset calibration
through the SPI registers (CSA_CAL_X) or CAL pin. When the calibration is enabled, the inputs to the amplifier
are shorted, the load is disconnected, and the gain (GCSA) of the amplifier is changed to the 40 V/V setting. The
amplifier then goes through an automatic trim routine to minimize the input offset. The automatic trim routine
requires 100 µs to complete after the calibration is enabled. After this time, the inputs of the amplifier stay
shorted, the load stays disconnected, and the gain stays at 40 V/V if further offset calibration is desired to be
done by the external controller. To complete the offset calibration, the CSA_CAL_X registers or CAL pin should
be taken back low. The gain is returned to the original gain setting after the device completes calibration. For the
best results, perform offset calibration when the external MOSFETS are not switching to decrease the potential
noise impact to the amplifier. When the current sense amplifiers go into a calibration mode, the VREF pin is set
to bidirectional mode if the device is configured in unidirectional mode. The setting of the VREF pin affects the
channels all three current sense amplifier, even if the CSA_CAL_X register is not set for the all channels.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current sense amplifiers on the DRV8323 and DRV8323R SPI devices can be configured to amplify the
voltage across the external low-side MOSFET VDS. This configuration lets the external controller measure the
voltage drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current
level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay disconnected. When the CSA_FET bit is set to 1,
the negative reference for the low-side VDS monitor is automatically set to the SNx pin, regardless of the state of
the state of the LS_REF bit. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS current sense mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
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VM
VM
VDRAIN
VDRAIN
High-Side
High-Side
V
Monitor
V
Monitor
DS
DS
+
V
+
V
DSœ
DSœ
GHx
SHx
GHx
SHx
(SPI only)
(SPI only)
CSA_FET = 0
CSA_FET = 1
LS_REF = 0
LS_REF = X
Low-Side
Low-Side
V
Monitor
DS
V
Monitor
DS
+
V
+
VDS
œ
GLx
SPx
DSœ
GLx
0
1
0
1
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
SPx
R
SOx
SOx
AV
AV
SENSE
SNx
SNx
GND
GND
Figure 41. Resistor Sense Configuration
Figure 42. VDS Current Sense Mode
When operating in MOSFET VDS current sense mode, the amplifier is enabled at the end of the tDRIVE time. At
this time, the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side
MOSFET receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Step-Down Buck Regulator
The DRV8320R and DRV8323R have an integrated buck regulator (LMR16006) to supply power for an external
controller or system voltage rail. The LMR16006 device is a 60-V, 600-mA, buck (step-down) regulator.
The buck regulator has a very-low quiescent current during light loads to prolong battery life. The LMR16006
device improves performance during line and load transients by implementing a constant-frequency current-mode
control scheme which requires less output capacitance and simplifies frequency compensation design. The
LMR16006 is the LMR16006X device version that uses a 0.7-MHz switching frequency.
The LMR16006 device decreases the external component count by integrating the bootstrap recharge diode. The
bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The bootstrap
capacitor voltage is monitored by a UVLO circuit and turns off the high-side MOSFET when the boot voltage falls
lower than a preset threshold.
The LMR16006 device can operate at high duty cycles because of the boot UVLO and then refreshes the wimp
MOSFET. The output voltage can be stepped down to as low as the 0.8-V reference. The internal soft-start
feature minimizes inrush currents.
For additional details, a block diagram showing the wimp MOSFET, and design information refer to the
LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode data sheet.
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8.3.5.1 Fixed Frequency PWM Control
The LMR16006 device has a fixed switching frequency and implements peak current-mode control. The output
voltage is compared through external resistors on the FB pin to an internal voltage reference by an error amplifier
which drives the internal COMP node. An internal oscillator initiates the turnon of the high-side power switch. The
error amplifier output is compared to the high-side power switch current. When the power switch current reaches
the level set by the internal COMP voltage, the power switch turns off. The internal COMP node voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP node voltage to a maximum level.
8.3.5.2 Bootstrap Voltage (CB)
The LMR16006 device has an integrated bootstrap regulator, and requires a small ceramic capacitor between
the CB and SW pins to provide the gate drive voltage for the high-side MOSFET. The CB capacitor is refreshed
when the high-side MOSFET is off and the low-side diode conducts. To improve dropout, the LMR16006 device
is designed to operate at 100% duty cycle as long as the CB to SW pin voltage is greater than 3 V. When the
voltage from the CB to SW pin drops to less than 3 V, the high-side MOSFET turns off using a UVLO circuit
which lets the low-side diode conduct and refresh the charge on the CB capacitor. Because the supply current
sourced from the CB capacitor is low, the high-side MOSFET can stay on for more switching cycles than are
required to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is high. Attention
must be given in maximum duty-cycle applications with a light load. To make sure the SW pin can be pulled to
ground to refresh the CB capacitor, an internal circuit charges the CB capacitor when the load is light or the
device is working in dropout condition.
8.3.5.3 Output Voltage Setting
The output voltage is set using the feedback pin (FB) and a resistor divider connected to the output as shown in
图 51. The voltage of the feedback pin is 0.765 V, so the ratio of the feedback resistors sets the output voltage
according to Equation 5.
≈
’
÷
◊
R1
R2
»
…
ÿ
VO = 0.765 V ì 1+
∆
Ÿ
⁄
«
(5)
Typically the starting value of R2 is from 1 kΩ to 100 kΩ. Use Equation 6 to calculate the value of R1.
≈
∆
«
’
VO
»
…
ÿ
R1= R2 ì
-1
÷
◊
Ÿ
⁄
0.765 V
(6)
8.3.5.4 Enable nSHDN and VIN Undervoltage Lockout
The nSHDN pin of the LMR16006 device is an input that is tolerant of high voltages with an internal pullup circuit.
The device can be enabled even if the nSHDN pin is floating. The regulator can also be turned on using 1.23-V
or higher logic signals. If the use of a higher voltage is desired because of system or other constraints, a 100-kΩ
or larger value resistor is recommended between the applied voltage and the nSHDN pin to help protect the
device. When the nSHDN pin is pulled down to 0 V, the device turns off and goes to the lowest shutdown current
mode. In shutdown mode the supply current decreases to approximately 1 µA. If the shutdown function is
unused, the nSHDN pin can be tied to the VIN pin with a 100-kΩ resistor. The maximum voltage to the nSHDN
pin should not exceed 60 V. The LMR16006 device has an internal UVLO circuit to shut down the output if the
input voltage falls lower than an UVLO threshold level that is internally fixed. Shutting down the output in this way
makes sure the regulator is not latched into an unknown state during low input voltage conditions. The regulator
powers up when the input voltage exceeds the voltage level. If the UVLO voltage must be higher, use the
nSHDN pin to adjust the system UVLO by using external resistors.
8.3.5.5 Current Limit
The LMR16006 device implements current-mode control which uses the internal COMP voltage to turn off the
high-side MOSFET on a cycle-by-cycle basis. Each cycle, the switch current and internal COMP voltage are
compared. When the peak switch current intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP node
high, increasing the switch current. The error amplifier output is clamped internally causing it to function as a
switch current limit.
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8.3.5.6 Overvoltage Transient Protection
The LMR16006 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unloaded transients on power supply designs
with low-value output capacitance. For example, when the power supply output is overloaded, the error amplifier
compares the actual output voltage to the internal reference voltage. If the voltage of the FB pin is lower than the
internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error
amplifier output to a high voltage, therefore requesting the maximum output current. When the condition clears,
the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some
applications, the output voltage of the power supply can respond faster than the error amplifier output can
respond which can result in output overshoot. The OVTP feature minimizes the output overshoot when using a
low-value output capacitor by implementing a circuit to compare the FB pin voltage to the OVTP threshold which
is 108% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high-side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
FB voltage drops lower than the OVTP threshold, the high-side MOSFET can turn on at the next clock cycle.
8.3.5.7 Thermal Shutdown
The device implements an internal thermal shutdown to help protect the device if the junction temperature
exceeds 170°C (typical). The thermal shutdown forces the device to stop switching when the junction
temperature exceeds the thermal trip threshold. When the junction temperature decreases to less than 160°C
(typical), the device reinitiates the power-up sequence.
8.3.6 Gate Driver Protective Circuits
The DRV832x family of devices is protected against VM undervoltage, charge pump undervoltage, MOSFET VDS
overcurrent, gate driver shorts, and overtemperature events.
Table 7. Fault Action and Response (SPI Devices)
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
VM
undervoltage
(UVLO)
Automatic:
VVM > VUVLO
VVM < VUVLO
—
nFAULT
Hi-Z
Disabled
Charge pump
undervoltage
(CPUV)
DIS_CPUV = 0b
DIS_CPUV = 1b
nFAULT
None
Hi-Z
Active
Active
Automatic:
VVCP > VCPUV
VVCP < VCPUV
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
OCP_MODE = 01b
nFAULT
nFAULT
Hi-Z
Hi-Z
Active
Active
Retry:
tRETRY
VDS overcurrent
(VDS_OCP)
VDS > VVDS_OCP
OCP_MODE = 10b
OCP_MODE = 11b
nFAULT
None
Active
Active
Active
Active
No action
No action
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Retry:
tRETRY
VSENSE
overcurrent
(SEN_OCP)
OCP_MODE = 01b
OCP_MODE = 10b
nFAULT
nFAULT
None
Hi-Z
Active
Active
Active
VSP > VSEN_OCP
Active
Active
No action
No action
OCP_MODE = 11b or
DIS_SEN = 1b
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 0b
nFAULT
Hi-Z
Active
Gate driver fault
(GDF)
Gate voltage stuck > tDRIVE
DIS_GDF = 1b
OTW_REP = 0b
None
None
Active
Active
Active
Active
No action
No action
Thermal
warning
(OTW)
TJ > TOTW
Automatic:
TJ < TOTW – THYS
OTW_REP = 1b
—
nFAULT
nFAULT
Active
Hi-Z
Active
Active
Thermal
shutdown
(OTSD)
Automatic:
TJ < TOTSD – THYS
TJ > TOTSD
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8.3.6.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold, all of the external
MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and
VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit stays
set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
8.3.6.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the
charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and
CPUV bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set
until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on
the SPI devices disables this protection feature. On hardware interface devices, the CPUV protection is always
enabled.
8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on)
.
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized and action is done according to the OCP_MODE bit. On hardware
interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the
OCP_MODE bit is configured for 4-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On
SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the
OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown, VDS
automatic retry, VDS report only, and VDS disabled.
8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low.
When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for the gate
drive current instead of the programmed IDRIVE setting. This setting lets any large current that may be present
to be switched off slowly to minimize any inductive kickback caused by parasitic capacitance in the system. The
FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for the gate
drive current instead of the programmed IDRIVE setting. This setting lets any large current that may be present
to be switched off slowly to minimize any inductive kickback caused by parasitic capacitance in the system. The
FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation starts again automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as usual. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
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8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current sense resistor
with the SP pin. If at any time the voltage on the SP input of the CSA exceeds the VSEN_OCP threshold for longer
than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done according to the
OCP_MODE bit. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is fixed at 4 µs,
and the OCP_MODE for VSENSE is fixed for 4-ms automatic retry. On SPI devices, the VSENSE threshold is set
through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE
bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and
VSENSE disabled.
8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition clears and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation starts again automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation starts again (gate
driver operation and the nFAULT pin is released) when the gate driver fault condition clears and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
8.3.6.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
lower than the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also
be configured to report on the nFAULT pin by setting the OTW_REP bit to 1 through the SPI registers.
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8.3.6.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation starts again (gate driver operation and the nFAULT pin is released) when the
overtemperature condition clears. The TSD bit stays latched high indicating that a thermal event occurred until a
clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This protection
feature cannot be disabled.
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV832x family of devices. When the ENABLE pin is low, the device
goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, sense amplifiers (if present) are
disabled, all external MOSFETs are disabled, the charge pump is disabled, the DVDD regulator is disabled, and
the SPI bus is disabled. The LMR16006X buck regulator (if present) is not controlled by the ENABLE pin and can
be operated independently of the gate driver. The tSLEEP time must elapse after a falling edge on the ENABLE pin
before the device goes to sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is
pulled high. The tWAKE time must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
NOTE
During power up and power down of the device through the ENABLE pin, the nFAULT pin
is held low as the internal regulators enable or disable. After the regulators have enabled
or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin
is low does not exceed the tSLEEP or tWAKE time.
8.4.1.2 Operating Mode
When the ENABLE pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge pump,
low-side gate regulator, DVDD regulator, and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV832x family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT SPI
bit on SPI devices or issuing a reset pulse to the ENABLE pin on either interface variant. The ENABLE reset
pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence
should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset
pulse has no effect on any of the regulators, device settings, or other functional blocks
50
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Device Functional Modes (continued)
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Continuous Conduction Mode (CCM)
The LMR16006 integrated buck regulator steps the input voltage down to a lower output voltage. In continuous
conduction mode (when the inductor current never reaches zero at CCM), the buck regulator operates in two
cycles. The power switch is connected between the VIN and SW pins. During the first cycle of operation, the
transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is
supplied by the COUT capacitor and the rising current through the inductor. During the second cycle of operation,
the transistor is open and the diode is forward biased because the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of
these two cycles determines the output voltage. Equation 7 and Equation 8 define the approximate output
voltage.
VO
D =
VVIN
where
•
D is the duty cycle of the switch
(7)
(8)
D' = 1-D
The value of D and D' is required for design calculations.
8.4.2.2 Eco-mode™ Control Scheme
The LMR16006 device operates with the Eco-mode control scheme at light-load currents to improve efficiency by
reducing switching and gate drive losses. The LMR16006 device is designed so that if the output voltage is
within regulation and the peak switch current at the end of any switching cycle is less than the sleep-current
threshold, IINDUCTOR ≤ 80 mA, the device goes to Eco-mode. For Eco-mode operation, the LMR16006 device
senses peak current, not average or load current, so the load current when the device goes to Eco-mode is
dependent on the input voltage, the output voltage, and the value of the output inductor. When the load current is
low and the output voltage is within regulation, the device goes to Eco-mode and draws only 28-µA input
quiescent current.
8.5 Programming
This section applies only to the DRV832x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV832x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16-bit word, with a 5-bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
•
•
•
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
•
Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
•
•
•
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
•
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
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Programming (continued)
the 5-bit command data.
The SPI registers are reset to the default settings on power up, when the device is enters sleep mode, and when
a UVLO fault occurs.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
1 read or write bit, W (bit B15)
4 address bits, A (bits B14 through B11)
11 data bits, D (bits B11 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 8. SDI Input Data Word Format
R/W
B15
W0
ADDRESS
DATA
B5
B14
A3
B13
A2
B12
A1
B11
A0
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
D5
Table 9. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
X
B14
X
B13
X
B12
X
B11
X
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
nSCS
SCLK
SDI
X
Z
MSB
LSB
LSB
X
Z
MSB
SDO
Capture
Point
Propagate
Point
Figure 43. SPI Slave Timing Diagram
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8.6 Register Maps
This section applies only to the DRV832x SPI devices.
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 10). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Table 10. DRV832xS and DRV832xRS Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
Address
DRV8320S and DRV8320RS
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
Reserved
FAULT
SA_OC
VDS_OCP
SB_OC
GDF
UVLO
OTW
OTSD
CPUV
VDS_HA
VGS_HA
VDS_LA
VGS_LA
VDS_HB
VGS_HB
VDS_LB
VGS_LB
COAST
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SC_OC
DIS_GDF
R
Reserved
DIS_CPUV
LOCK
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
IDRIVEN_LS
VDS_LVL
TRETRY
OCP_MODE
OCP_DEG
Reserved
Reserved
DRV8323S and DRV8323RS
Reserved
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
FAULT
SA_OC
VDS_OCP
GDF
UVLO
OTW
OTSD
CPUV
VDS_HA
VGS_HA
VDS_LA
VDS_HB
VGS_HB
VDS_LB
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SB_OC
DIS_CPUV
LOCK
SC_OC
DIS_GDF
VGS_LA
VGS_LB
COAST
R
Reserved
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
VREF_DIV LS_REF
IDRIVEN_LS
VDS_LVL
TRETRY
CSA_FET
OCP_MODE
CSA_GAIN
OCP_DEG
DIS_SEN CSA_CAL_A
Reserved
CSA_CAL_B
CSA_CAL_C
SEN_LVL
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8.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for
access types in this section.
Table 11. Status Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default value
8.6.1.1 Fault Status Register 1 (address = 0x00)
The fault status register 1 is shown in Figure 44 and described in Table 12.
Register access type: Read only
Figure 44. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
R-0b
VDS_OCP
R-0b
GDF
R-0b
UVLO
R-0b
OTSD
R-0b
VDS_HA
R-0b
VDS_LA
R-0b
VDS_HB
R-0b
VDS_LB
R-0b
VDS_HC
R-0b
VDS_LC
R-0b
Table 12. Fault Status Register 1 Field Descriptions
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
Indicates VDS monitor overcurrent fault condition
Indicates gate drive fault condition
9
8
7
6
5
4
3
2
1
0
VDS_OCP
GDF
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
UVLO
Indicates undervoltage lockout fault condition
OTSD
Indicates overtemperature shutdown
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
Indicates VDS overcurrent fault on the A high-side MOSFET
Indicates VDS overcurrent fault on the A low-side MOSFET
Indicates VDS overcurrent fault on the B high-side MOSFET
Indicates VDS overcurrent fault on the B low-side MOSFET
Indicates VDS overcurrent fault on the C high-side MOSFET
Indicates VDS overcurrent fault on the C low-side MOSFET
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8.6.1.2 Fault Status Register 2 (address = 0x01)
The fault status register 2 is shown in Figure 45 and described in Table 13.
Register access type: Read only
Figure 45. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
R-0b
SB_OC
R-0b
SC_OC
R-0b
OTW
R-0b
CPUV
R-0b
VGS_HA
R-0b
VGS_LA
R-0b
VGS_HB
R-0b
VGS_LB
R-0b
VGS_HC
R-0b
VGS_LC
R-0b
Table 13. Fault Status Register 2 Field Descriptions
Bit
Field
Type
Default
Description
10
SA_OC
SB_OC
SC_OC
OTW
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8323xS)
Indicates overcurrent on phase B sense amplifier (DRV8323xS)
Indicates overcurrent on phase C sense amplifier (DRV8323xS)
Indicates overtemperature warning
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
CPUV
Indicates charge pump undervoltage fault condition
Indicates gate drive fault on the A high-side MOSFET
Indicates gate drive fault on the A low-side MOSFET
Indicates gate drive fault on the B high-side MOSFET
Indicates gate drive fault on the B low-side MOSFET
Indicates gate drive fault on the C high-side MOSFET
Indicates gate drive fault on the C low-side MOSFET
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
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8.6.2 Control Registers
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 14 shows the codes that are used for
access types in this section.
Table 14. Control Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
8.6.2.1 Driver Control Register (address = 0x02)
The driver control register is shown in Figure 46 and described in Table 15.
Register access type: Read/Write
Figure 46. Driver Control Register
10
9
8
7
6
5
4
3
2
1
0
DIS
_CPUV
DIS
_GDF
OTW
_REP
1PWM
_COM
1PWM
_DIR
CLR
_FLT
Reserved
R/W-0b
PWM_MODE
R/W-00b
COAST
R/W-0b
BRAKE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 15. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
Reserved
R/W
0b
Reserved
9
DIS_CPUV
R/W
R/W
R/W
R/W
0b
0b = Charge pump UVLO fault is enabled
1b = Charge pump UVLO fault is disabled
8
DIS_GDF
0b
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
7
OTW_REP
PWM_MODE
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification (diode
freewheeling)
3
2
1
1PWM_DIR
COAST
R/W
R/W
R/W
0b
0b
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
Write a 1 to this bit to put all MOSFETs in the Hi-Z state
BRAKE
Write a 1 to this bit to turn on all three low-side MOSFETs in 1x
PWM mode.
This bit is ORed with the INLC (BRAKE) input.
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear latched fault bits.
This bit automatically resets after being written.
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8.6.2.2 Gate Drive HS Register (address = 0x03)
The gate drive HS register is shown in Figure 47 and described in Table 16.
Register access type: Read/Write
Figure 47. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
0
LOCK
IDRIVEP_HS
R/W-1111b
IDRIVEN_HS
R/W-1111b
R/W-011b
Table 16. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02 bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7-4
IDRIVEP_HS
R/W
1111b
0000b = 10 mA
0001b = 30 mA
0010b = 60 mA
0011b = 80 mA
0100b = 120 mA
0101b = 140 mA
0110b = 170 mA
0111b = 190 mA
1000b = 260 mA
1001b = 330 mA
1010b = 370 mA
1011b = 440 mA
1100b = 570 mA
1101b = 680 mA
1110b = 820 mA
1111b = 1000 mA
3-0
IDRIVEN_HS
R/W
1111b
0000b = 20 mA
0001b = 60 mA
0010b = 120 mA
0011b = 160 mA
0100b = 240 mA
0101b = 280 mA
0110b = 340 mA
0111b = 380 mA
1000b = 520 mA
1001b = 660 mA
1010b = 740 mA
1011b = 880 mA
1100b = 1140 mA
1101b = 1360 mA
1110b = 1640 mA
1111b = 2000 mA
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8.6.2.3 Gate Drive LS Register (address = 0x04)
The gate drive LS register is shown in Figure 48 and described in Table 17.
Register access type: Read/Write
Figure 48. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
0
CBC
TDRIVE
R/W-11b
IDRIVEP_LS
R/W-1111b
IDRIVEN_LS
R/W-1111b
R/W-1b
Table 17. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
Cycle-by cycle operation. In retry OCP_MODE, for both
VDS_OCP and SEN_OCP, the fault is automatically cleared
when a PWM input is given
9-8
7-4
TDRIVE
R/W
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
IDRIVEP_LS
1111b
0000b = 10 mA
0001b = 30 mA
0010b = 60 mA
0011b = 80 mA
0100b = 120 mA
0101b = 140 mA
0110b = 170 mA
0111b = 190 mA
1000b = 260 mA
1001b = 330 mA
1010b = 370 mA
1011b = 440 mA
1100b = 570 mA
1101b = 680 mA
1110b = 820 mA
1111b = 1000 mA
3-0
IDRIVEN_LS
R/W
1111b
0000b = 20 mA
0001b = 60 mA
0010b = 120 mA
0011b = 160 mA
0100b = 240 mA
0101b = 280 mA
0110b = 340 mA
0111b = 380 mA
1000b = 520 mA
1001b = 660 mA
1010b = 740 mA
1011b = 880 mA
1100b = 1140 mA
1101b = 1360 mA
1110b = 1640 mA
1111b = 2000 mA
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8.6.2.4 OCP Control Register (address = 0x05)
The OCP control register is shown in Figure 49 and described in Table 18.
Register access type: Read/Write
Figure 49. OCP Control Register
10
9
8
7
6
5
4
3
2
1
0
TRETRY
R/W-0b
DEAD_TIME
R/W-01b
OCP_MODE
R/W-01b
OCP_DEG
R/W-01b
VDS_LVL
R/W-1001b
Table 18. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 4 ms
1b = VDS_OCP and SEN_OCP retry time is 50 µs
9-8
7-6
5-4
3-0
DEAD_TIME
R/W
R/W
R/W
R/W
01b
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
OCP_MODE
OCP_DEG
VDS_LVL
01b
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
01b
00b = Overcurrent deglitch time of 2 µs
01b = Overcurrent deglitch time of 4 µs
10b = Overcurrent deglitch time of 6 µs
11b = Overcurrent deglitch time of 8 µs
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
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8.6.2.5 CSA Control Register (DRV8323x Only) (address = 0x06)
The CSA control register is shown in Figure 50 and described in Table 19.
Register access type: Read/Write
This register is only available with the DRV8323x family of devices.
Figure 50. CSA Control Register
10
9
8
7
6
5
4
3
2
1
0
CSA
_FET
VREF
_DIV
LS
_REF
CSA
_GAIN
DIS
_SEN
CSA
_CAL_A
CSA
_CAL_B
CSA
_CAL_C
SEN
_LVL
R/W-0b
R/W-1b
R/W-0b
R/W-10b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
Table 19. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
0b = Current sense amplifier positive input is SPx
1b Current sense amplifier positive input is SHx (also
10
CSA_FET
R/W
0b
=
automatically sets the LS_REF bit to 1)
9
8
VREF_DIV
R/W
R/W
R/W
1b
0b Current sense amplifier reference voltage is VREF
(unidirectional mode)
=
1b = Current sense amplifier reference voltage is VREF
divided by 2
LS_REF
0b
0b
= VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
10b
00b = 5-V/V current sense amplifier gain
01b = 10-V/V current sense amplifier gain
10b = 20-V/V current sense amplifier gain
11b = 40-V/V current sense amplifier gain
5
4
DIS_SEN
R/W
R/W
0b
0b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
CSA_CAL_A
0b = Normal current sense amplifier A operation
1b
=
Short inputs to current sense amplifier
A
B
C
for offset
for offset
for offset
calibration
3
2
CSA_CAL_B
CSA_CAL_C
SEN_LVL
R/W
R/W
R/W
0b
0b = Normal current sense amplifier B operation
1b
= Short inputs to current sense amplifier
calibration
0b
0b = Normal current sense amplifier C operation
1b
= Short inputs to current sense amplifier
calibration
1-0
11b
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DRV832x family of devices is primarily used in applications for three-phase brushless DC motor control. The
design procedures in the Typical Application section highlight how to use and configure the DRV832x family of
devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8323R SPI device is used in this application example.
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Typical Application (接下页)
L
OUT
0.8 to 60 V, 600 mA
VCC
VM
COUT
CIN
100 kꢀ
R
R
FB1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
3.3 V, 30 mA
1 µF
FB
DVDD
AGND
CAL
FB2
PGND
CPL
CPH
VCP
VM
3
47 nF
4
ENABLE
nSCS
SCLK
SDI
5
VM
1 µF
6
VCC
GND
(PAD)
7
0.1 µF
VCC
VDRAIN
GHA
SHA
GLA
VDRAIN
GHA
SHA
10 kꢀ
8
SDO
10 kꢀ
9
nFAULT
DGND
VREF
SOA
10
11
12
VCC
GLA
1 µF
SPA
SPA
SNA
SNA
VM
VM
VM
VM
VM
+
+
VDRAIN
GHB
SHB
GHC
SHC
GHA
SHA
B
C
A
GLB
SPB
GLA
SPA
GLC
SPC
R
SENSE
R
SENSE
R
SENSE
SNC
SNA
SNB
图 51. Primary Application Schematic
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Typical Application (接下页)
9.2.1.1 Design Requirements
表 20 lists the example input parameters for the system design.
表 20. Design Parameters
EXAMPLE DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
REFERENCE
EXAMPLE VALUE
24 V
VVM
8 V to 45 V
CSD18536KCS
83 nC (typical) at VVGS = 10 V
14 nC (typical)
100 to 300 ns
50 to 150 ns
45 kHz
MOSFET part number
MOSFET total gate charge
MOSFET gate to drain charge
Target output rise time
Qg
Qgd
tr
Target output fall time
tf
PWM Frequency
ƒPWM
VVCC
Imax
Buck regulator output voltage
Maximum motor current
ADC reference voltage
Winding sense current range
Motor RMS current
3.3 V
100 A
VVREF
ISENSE
IRMS
PSENSE
TA
3.3 V
–40 A to +40 A
28.3 A
Sense resistor power rating
System ambient temperature
2 W
–20°C to +105°C
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 External MOSFET Support
The DRV832x MOSFET support is based on the capacity of the charge pump and PWM switching frequency of
the output. For a quick calculation of MOSFET driving capacity, use 公式 9 and 公式 10 for three phase BLDC
motor applications.
Trapezoidal 120° Commutation: IVCP > Qg × ƒPWM
where
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
IVCP is the charge pump capacity, which depends on the VM pin voltage.
The multiplier based on the commutation control method, may vary based on implementation.
(9)
Sinusoidal 180° Commutation: IVCP > 3 × Qg × ƒPWM
(10)
9.2.1.2.1.1 Example
If a system with a VVM voltage of 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 45 kHz, then
the charge pump can support MOSFETs using trapezoidal commutation with a Qg less than 333 nC, and
MOSFETs using sinusoidal commutation with a Qg less than 111 nC.
9.2.1.2.2 IDRIVE Configuration
The strength of the gate drive current, IDRIVE, is selected based on the gate-to-drain charge of the external
MOSFETs and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given
MOSFET, then the MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be
asserted. Additionally, slow rise and fall times result in higher switching power losses. TI recommends adjusting
these values in the system with the required external MOSFETs and motor to determine the best possible setting
for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected
at the same time on the IDRIVE pin.
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For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use 公式
11 and 公式 12 to calculate the value of IDRIVEP and IDRIVEN (respectively).
Qgd
IDRIVEP
>
tr
Qgd
tf
(11)
(12)
IDRIVEN
>
9.2.1.2.2.1 Example
Use 公式 13 and 公式 14 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate-to-drain charge of
14 nC and a rise time from 100 to 300 ns.
14 nC
IDRIVEP1
=
= 140 mA
= 47 mA
100 ns
14 nC
300 ns
(13)
(14)
IDRIVEP2
=
Select a value for IDRIVEP that is between 47 mA and 140 mA. For this example, the value of IDRIVEP was selected
as 120-mA source.
Use 公式 15 and 公式 16 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate-to-drain charge of
14 nC and a fall time from 50 to 150 ns.
14 nC
IDRIVEN1
=
= 280 mA
= 93 mA
50 ns
14 nC
150 ns
(15)
(16)
IDRIVEN2
=
Select a value for IDRIVEN that is between 93 mA and 280 mA. For this example, the value of IDRIVEN was selected
as 240-mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in 公式 17.
VDS_OCP > Imax ì RDS(on)max
(17)
9.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 100 A. According to the
CSD18536KCS 60 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 1.6 mΩ. From these values, the approximate worst-
case value of RDS(on) is 1.8 × 1.6 mΩ = 2.88 mΩ.
Using 公式 17 with a value of 2.88 mΩ for RDS(on) and a worst-case motor current of 100 A, 公式 18 shows the
calculated the value of the VDS monitors.
VDS _ OCP > 100 A ì 2.88 mW
VDS _ OCP > 0.288 V
(18)
For this example, the value of VDS_OCP was selected as 0.31 V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 2 µs, 4 µs, 6 µs, or 8 µs.
9.2.1.2.4 Sense Amplifier Bidirectional Configuration (DRV8323 and DRV8323R)
The sense amplifier gain on the DRV8323, DRV8323R devices and sense resistor value are selected based on
the target current range, VREF voltage supply, power rating of the sense resistor, and operating temperature
range. In bidirectional operation of the sense amplifier, the dynamic range at the output is approximately
calculated as shown in 公式 19.
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VVREF
VO = V
- 0.25 V -
(
)
VREF
(19)
Use 公式 20 to calculate the approximate value of the selected sense resistor with VO calculated using 公式 19.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
(20)
From 公式 19 and 公式 20, select a target gain setting based on the power rating of the target sense resistor.
9.2.1.2.4.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from –40 to +40 A. The
linear range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range
of the sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
V = 3.3 V - 0.25 V -
= 1.4 V
(
)
O
2
(21)
(22)
(23)
1.4 V
AV ì 40 A
1.4 V
AV ì 40 A
R =
2 W > 28.32 ì R ç R < 2.5 mW
2.5 mW >
ç AV > 14
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was selected
as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax = 40 A does
not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.1.2.5 Buck Regulator Configuration (DRV8320R and DRV8323R)
For a detailed design procedure and information on selecting the correct buck regulator external components,
refer to the LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode data
sheet.
9.2.1.3 Application Curves
图 52. Gate Drive at 20% Duty Cycle
图 53. Gate Drive at 80% Duty Cycle
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图 54. BLDC Motor Commutation 1000 RPM
图 55. BLDC Motor Commutation 2000 RPM
图 56. IDRIVE Maximum Setting Positive Current
图 57. IDRIVE Maximum Setting Negative Current
图 58. IDRIVE Minimum Setting Positive Current
图 59. IDRIVE Minimum Setting Negative Current
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图 60. IDRIVE 260 to 520-mA Setting Negative Current
图 61. IDRIVE 260 to 520-mA Setting Positive Current
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9.2.2 Alternative Application
In this application, one sense amplifier is used in unidirectional mode for a summing current sense scheme often
used in trapezoidal or hall-based BLDC commutation control.
L
OUT
0.8 to 60 V, 600 mA
VCC
VM
COUT
CIN
100 kꢀ
R
R
FB1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
3.3 V, 30 mA
1 µF
FB
DVDD
AGND
CAL
FB2
PGND
CPL
CPH
VCP
VM
3
47 nF
4
ENABLE
nSCS
SCLK
SDI
5
VM
1 µF
6
VCC
GND
(PAD)
7
0.1 µF
VCC
VDRAIN
GHA
SHA
GLA
VDRAIN
GHA
SHA
10 kꢀ
8
SDO
10 kꢀ
9
nFAULT
DGND
VREF
SOA
10
11
12
VCC
GLA
1 µF
SPA
SPA
SNA
SNA
VM
VM
VM
VM
VM
+
+
VDRAIN
GHB
SHB
GHC
SHC
GHA
SHA
B
C
A
GLB
SPB
GLA
SPA
GLC
SPC
R
SENSE
SNA
图 62. Alternative Application Schematic
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9.2.2.1 Design Requirements
表 21 lists the example design input parameters for system design.
表 21. Design Parameters
EXAMPLE DESIGN PARAMETER
ADC reference voltage
Sensed current
REFERENCE
VVREF
EXAMPLE VALUE
3.3 V
ISENSE
IRMS
PSENSE
TA
0 to 40 A
Motor RMS current
28.3 A
Sense-resistor power rating
System ambient temperature
3 W
–20°C to +105°C
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to the
VREF_DIV bit.
The sense amplifier gain and sense resistor values are selected based on the target current range, VREF, power
rating of the sense resistor, and operating temperature range. In unidirectional operation of the sense amplifier,
use 公式 24 to calculate the approximate value of the dynamic range at the output.
V = V
- 0.25 V - 0.25 V = VVREF - 0.5 V
O
VREF
(24)
Use 公式 25 to calculate the approximate value of the selected sense resistor.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
where
•
VO = VVREF - 0.5 V
(25)
From 公式 24 and 公式 25, select a target gain setting based on the power rating of a target sense resistor.
9.2.2.2.1.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from 0 to 40 A. The linear
range of the SOx output for the DRV8323x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification).
The differential range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO = 3.3 V - 0.5 V = 2.8 V
(26)
(27)
(28)
2.8 V
R =
3 W > 28.32 ì R ç R < 3.75 mW
AV ì 40 A
2.8 V
3.75 mW >
ç AV > 18.7
AV ì 40 A
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax
=
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
版权 © 2017–2018, Texas Instruments Incorporated
69
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
10 Power Supply Recommendations
The DRV832x family of devices is designed to operate from an input voltage supply (VM) range from 6 V to 60 V.
A 0.1-µF ceramic capacitor rated for VM must be placed as close to the device as possible. In addition, a bulk
capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the external
power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs and
should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 63. Motor Drive Supply Parasitics Example
70
版权 © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R
or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the
AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect
these pins to the sources of the low-side external MOSFETs. These recommendations offer more accurate VDS
sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
For additional layout guidelines and examples see the Layout Guide for the DRV832x Family of Three-Phase
Smart Gate Drivers application report.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with
the best power conversion performance, thermal performance, and minimized generation of unwanted
electromagnetic interference (EMI):
•
Place the feedback network resistors close to the FB pin and away from the inductor to minimize coupling
noise into the feedback pin.
•
Place the input bypass capacitor close to the VIN pin to decrease copper trace resistance which effects the
input voltage ripple of the device.
•
•
Place the inductor close to the SW pin to decrease magnetic and electrostatic noise.
Place the output capacitor close to the junction of the inductor and the diode. The inductor, diode, and COUT
trace should be as short as possible to decrease conducted and radiated noise and increase overall
efficiency.
•
Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for
Switching Power Supplies application report.
版权 © 2017–2018, Texas Instruments Incorporated
71
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
11.2 Layout Example
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
24 SOB
23 SOC
22 SNC
21 SPC
20 GLC
19 SHC
18 GHC
17 GHB
16 SHB
15 GLB
14 SPB
13 SNB
INHA 37
INLA 38
INHB 39
INLB 40
INHC 41
INLC 42
D
D
D
D
G
S
S
S
Thermal Pad
BGND 43
CB 44
SW 45
NC 46
VIN 47
nSHDN 48
S
S
S
G
D
D
D
D
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
图 64. Layout Example
72
版权 © 2017–2018, Texas Instruments Incorporated
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com.cn
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
12 器件和文档支持
12.1 器件支持
12.1.1 器件命名规则
下图显示了说明完整器件名称的图例：
DRV83 (2) (3) (R) (S) (RGZ) (R)
Prefix
Tape and Reel
DRV83 œ Three Phase Brushless DC
R œ Tape and Reel
T œ Small Tape and Reel
Package
RTV œ 5 × 5 × 0.75 mm QFN
RTA œ 6 x 6 × 0.75 mm QFN
RHA œ 6 x 6 × 0.9 mm QFN
RGZ œ 7 × 7 × 0.9 mm QFN
Series
2 œ 60 V device
5 œ 100 V device
Interface
S œ SPI interface
H œ Hardware interface
Sense amplifiers
0 œ No sense amplifiers
3 œ 3x sense amplifiers
Buck Regulator
[blank] œ No buck regulator
R œ Buck regulator
12.2 文档支持
12.2.1 相关文档
•
•
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《无刷直流栅极驱动器系统的架构》应用报告
德州仪器 (TI)，《具有高效 Eco-Mode 的 LMR16006 SIMPLE SWITCHER® 60V 0.6A 降压稳压器》数据表
德州仪器 (TI)，《DRV832x 系列三相智能栅极驱动器布局指南》应用报告
德州仪器 (TI)，《AN-1149 开关电源布局指南》应用报告
德州仪器 (TI)，《TI 电机栅极驱动器的 IDRIVE 和 TDRIVE 认知》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术缩减电机驱动 BOM 和 PCB 面积》TI 技术手册
德州仪器 (TI)，《采用 TI 智能栅极驱动技术降低 EMI 辐射发射》TI 技术手册
德州仪器 (TI)，《采用 TI 智能栅极驱动技术进行电机驱动保护》TI 技术手册
德州仪器 (TI)，《QFN/SON PCB 连接》应用报告
德州仪器 (TI)，《高电流电机驱动器应用中的切断 开关》应用报告
德州仪器 (TI)，《采用 BLDC 电机的高效真空吸尘器硬件设计注意事项》应用报告
德州仪器 (TI)，《采用 BLDC 电机的电动自行车硬件设计注意事项》应用报告
德州仪器 (TI)，《采用 MSP430™ 的传感器式三相 BLDC 电机控制》应用报告
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 22. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
DRV8320
DRV8320R
DRV8323
DRV8323R
版权 © 2017–2018, Texas Instruments Incorporated
73
DRV8320, DRV8320R
DRV8323, DRV8323R
ZHCSG01C –FEBRUARY 2017–REVISED AUGUST 2018
www.ti.com.cn
12.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
Eco-mode, NexFET, MSP430, E2E are trademarks of Texas Instruments.
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
74
版权 © 2017–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8320HRTVR
DRV8320HRTVT
DRV8320RHRHAR
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
VQFN
RTV
RTV
RHA
32
32
40
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
DRV8320H
NIPDAU
NIPDAU
DRV8320H
DRV
8320RH
DRV8320RHRHAT
DRV8320RSRHAR
DRV8320RSRHAT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
DRV
8320RH
DRV
8320RS
DRV
8320RS
DRV8320SRTVR
DRV8320SRTVT
DRV8323HRTAR
DRV8323HRTAT
DRV8323RHRGZR
DRV8323RHRGZT
DRV8323RSRGZR
DRV8323RSRGZT
DRV8323SRTAR
DRV8323SRTAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
40
40
48
48
48
48
40
40
NIPDAU
Call TI | NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8320S
DRV8320S
DRV8323H
DRV8323H
DRV8323RH
DRV8323RH
DRV8323RS
DRV8323RS
DRV8323S
DRV8323S
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8320HRTVR
DRV8320HRTVT
DRV8320RHRHAR
DRV8320RHRHAT
DRV8320RSRHAR
DRV8320RSRHAT
DRV8320SRTVR
DRV8320SRTVT
DRV8323HRTAR
DRV8323HRTAT
DRV8323RHRGZR
DRV8323RHRGZT
DRV8323RSRGZR
DRV8323RSRGZT
DRV8323SRTAR
DRV8323SRTAT
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RHA
RHA
RHA
RHA
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
40
40
40
40
32
32
40
40
48
48
48
48
40
40
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
16.4
16.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
5.3
5.3
6.3
6.3
6.3
6.3
5.3
5.3
6.3
6.3
7.3
7.3
7.3
7.3
6.3
6.3
5.3
5.3
6.3
6.3
6.3
6.3
5.3
5.3
6.3
6.3
7.3
7.3
7.3
7.3
6.3
6.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
12.0
12.0
16.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2500
250
12.0
12.0
12.0
12.0
8.0
2500
250
3000
250
8.0
2500
250
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
2500
250
2500
250
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8320HRTVR
DRV8320HRTVT
DRV8320RHRHAR
DRV8320RHRHAT
DRV8320RSRHAR
DRV8320RSRHAT
DRV8320SRTVR
DRV8320SRTVT
DRV8323HRTAR
DRV8323HRTAT
DRV8323RHRGZR
DRV8323RHRGZT
DRV8323RSRGZR
DRV8323RSRGZT
DRV8323SRTAR
DRV8323SRTAT
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RHA
RHA
RHA
RHA
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
40
40
40
40
32
32
40
40
48
48
48
48
40
40
3000
250
346.0
210.0
367.0
210.0
367.0
210.0
346.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
346.0
185.0
367.0
185.0
367.0
185.0
346.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
33.0
35.0
38.0
35.0
38.0
35.0
33.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
2500
250
2500
250
3000
250
2500
250
2500
250
2500
250
2500
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040B
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
2X 4.5
4.15 0.1
(0.2) TYP
11
20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X
4.5
SYMM
41
30
0.27
40X
1
0.17
PIN 1 ID
(OPTIONAL)
0.1
C A B
40
31
SYMM
0.05
0.5
0.3
40X
4219052/A 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.15)
SYMM
40X (0.6)
40X (0.22)
40
31
1
30
(0.25) TYP
36X (0.5)
SYMM
41
(5.8)
(0.685)
TYP
(1.14)
TYP
(
0.2) TYP
VIA
10
21
(R0.05) TYP
20
11
(0.685)
TYP
(1.14)
TYP
(5.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.07 MIN
ALL SIDES
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219052/A 06/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.17)
(1.37) TYP
40X (0.6)
40X (0.22)
31
40
1
30
41
(1.37)
TYP
(0.25) TYP
SYMM
(5.8)
36X (0.5)
(R0.05) TYP
10
21
11
20
METAL
TYP
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4219052/A 06/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RTA0040B
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
4.15±0.1
(0.2) TYP
11
20
36X 0.5
10
21
SYMM
41
2X
4.5
1
30
0.28
40X
PIN1 IDENTIFICATION
(OPTIONAL)
0.16
31
40
0.1
C A B
C
SYMM
0.5
0.3
40X
0.05
4219112/A 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
(
4.15)
40
31
40X (0.6)
40X (0.22)
1
30
36X (0.5)
SYMM
41
2X 2X
(4.5) (5.8)
2X
(0.685)
2X
(1.14)
(R0.05) TYP
10
21
12X (Ø0.2) VIA
TYP
11
20
2X (1.14)
2X (0.685)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219112/A 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
9X ( 1.17)
40
31
40X (0.6)
40X (0.22)
1
30
41
36X (0.5)
SYMM
2X 2X
(4.5) (5.8)
2X
(1.37)
(R0.05) TYP
10
21
EXPOSED
METAL
11
20
2X (1.37)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED COVERAGE BY AREA
SCALE: 15X
4219112/A 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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