DRV8328CRUY [TI]
DRV8328 4.5 to 60 V Three-phase BLDC Gate Driver;型号: | DRV8328CRUY |
厂家: | TEXAS INSTRUMENTS |
描述: | DRV8328 4.5 to 60 V Three-phase BLDC Gate Driver 栅 |
文件: | 总51页 (文件大小:3099K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DRV8328
SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
DRV8328 4.5 to 60 V Three-phase BLDC Gate Driver
1 Features
3 Description
•
65-V Three Phase Half-Bridge Gate Driver
– Drives 3 High-Side and 3 Low-Side N-Channel
MOSFETs (NMOS)
– 4.5 to 60-V Operating Voltage Range
– Supports 100% PWM Duty Cycle with Trickle
Charge pump
Bootstrap based Gate Driver Architecture
– 1000-mA Maximum Peak Source Current
– 2000-mA Maximum Peak Sink Current
Hardware interface provides simple configuration
The DRV8328 family of devices is an integrated
gate driver for three-phase applications. The devices
provide three half-bridge gate drivers, each capable
of driving high-side and low-side N-channel power
MOSFETs. The device generates the correct gate
drive voltages using in internal charge pump and
enhances the high-side MOSFETs using a bootstrap
circuit. A trickle charge pump is included to support
100% duty cycle. The Gate Drive architecture
supports peak gate drive currents up to 1-A source
and 2-A sink. The DRV8328 can operate from a single
power supply and supports a wide input supply range
of 4.5 to 60 V.
•
•
•
•
Ultra-low power sleep mode <1 uA at 25 C̊
4-ns (typ) propagation delay matching between
phases
•
•
•
•
•
•
•
•
Independent driver shutdown path (DRVOFF)
65-V tolerant wake pin (nSLEEP)
Supports negative transients upto -10-V on SHx
6x and 3x PWM Modes
Supports 3.3-V, and 5-V Logic Inputs
Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
Compact QFN Packages and Footprints
Adjustable VDS overcurrent threshold through
VDSLVL pin
Adjustable deadtime through DT pin
Efficient System Design With Power Blocks
Integrated Protection Features
– PVDD Undervoltage Lockout (PVDDUV)
– GVDD Undervoltage (GVDDUV)
– Bootstrap Undervoltage (BST_UV)
– Overcurrent Protection (VDS_OCP, SEN_OCP)
– Thermal Shutdown (OTSD)
The 6x and 3x PWM modes allow for simple
interfacing to controller circuits. DRV8328C and
DRV8328D variants has integrated accurate 3.3-V
LDO that can be used to power external controller
and can be used as reference for CSA. The
configuration settings for the gate driver and device
are configurable through hardware (H/W) pins.
A low-power sleep mode is provided to achieve
low quiescent current draw by shutting down most
of the internal circuitry. Internal protection functions
are provided for undervoltage lockout, GVDD fault,
MOSFET overcurrent, MOSFET short circuit, and
overtemperature. Fault conditions are indicated on the
nFAULT pin.
•
•
•
Device Information(1)
PART NUMBER
DRV8328ARUY
DRV8328BRUY
DRV8328CRUY(2)
DRV8328DRUY(2)
PACKAGE
BODY SIZE (NOM)
4.00 mm × 4.00 mm
4.00 mm × 4.00 mm
4.00 mm × 4.00 mm
4.00 mm × 4.00 mm
– Fault Condition Indicator (nFAULT)
WQFN (28)
WQFN (28)
WQFN (28)
WQFN (28)
2 Applications
•
•
•
•
•
•
•
•
Brushless-DC (BLDC) Motor Modules and PMSM
Cordless Garden and Power Tools, Lawnmowers
Appliances Fans and Pumps
Servo Drives
E-Bikes, E-Scooters, and E-Mobility
Cordless Vacuum Cleaners
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Device available for preview only.
4.5- to 60-V (65-V abs max)
LDO out
3.3V up to 80mA
Drones
6x / 3x PWM
PWM input
DRV8328
A
B
C
Industrial & Logistics Robots, and RC Toys
Charge Pump
nSLEEP
Gate Drive
HW
Bootstrap
architecture
MCU
nFAULT
LDO Regulator
Built-in Protec on
DRV8328 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8328
www.ti.com
SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
6.1 Pin Functions—28-Pin DRV8328 Devices..................4
7 Specification.................................................................... 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings Comm....................................................6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information 1pkg...........................................7
7.5 Electrical Characteristics.............................................8
7.6 Typical Characteristics..............................................13
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................24
9 Power Supply Recommendations................................38
9.1 Bulk Capacitance Sizing........................................... 38
10 Layout...........................................................................39
10.1 Layout Guidelines................................................... 39
10.2 Layout Example...................................................... 41
10.3 Thermal Considerations..........................................42
11 Device and Documentation Support..........................43
11.1 Device Support........................................................43
11.2 Documentation Support.......................................... 43
11.3 Related Links.......................................................... 43
11.4 Receiving Notification of Documentation Updates..43
11.5 Community Resources............................................43
11.6 Trademarks............................................................. 43
12 Mechanical, Packaging, and Orderable
Information.................................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2021) to Revision A (February 2022)
Page
•
Added new device orderable DRV8328B........................................................................................................... 1
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
5 Device Comparison Table
Table 5-1. Different Device Variants
DEVICE
DEVICE VARIANT
DRV8328A
Package
LDO output
DT pin and VDSLVL
PWM_MODE
6x
3x
6x
3x
Not Available
Available
DRV8328B
28-pin QFN
(4.00 mm x 4.00 mm)
DRV8328
DRV8328C(1)
DRV8328D(1)
3.3 V
Not Available
(1) Device available for preview only.
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
6 Pin Configuration and Functions
PVDD
CPL
1
2
3
4
5
6
7
21
20
19
18
17
16
15
INHB
INHC
AVDD
DRVOFF
LSS
PVDD
CPL
1
2
3
4
5
6
7
21
20
19
18
17
16
15
INLC
INHA
INHB
INHC
LSS
CPH
CPH
Thermal
Pad
GVDD
BSTA
SHA
Thermal
Pad
GVDD
BSTA
SHA
GLC
GLC
GHC
GHA
GHC
GHA
Not to scale
Not to scale
Figure 6-2. DRV8328C, DRV8328D RUY Package
28-pin WQFN With Exposed Thermal Pad Top View
Figure 6-1. DRV8328A, DRV8328B RUY Package
28-pin WQFN With Exposed Thermal Pad Top View
6.1 Pin Functions—28-Pin DRV8328 Devices
PIN
NO.
TYPE
DESCRIPTION
NAME
DRV8328A DRV8328C
DRV8328B DRV8328D
3.3-V regulator output. Connect a X5R or X7R, 1-µF, >6.3-V ceramic capacitor between
the AVDD and GND pins. This regulator can source up to 80 mA externally. TI
recommends a capacitor voltage rating at least twice the normal operating voltage of
the pin.
AVDD
-
19
PWR-O
BSTA
BSTB
BSTC
CPH
5
9
5
9
O
O
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
Bootstrap output pin. Connect capacitor between BSTB and SHB
Bootstrap output pin. Connect capacitor between BSTC and SHC
13
3
13
3
PWR Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor
between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice
PWR
CPL
2
2
the normal operating voltage of the pin.
Gate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ
DT
27
-
I
I
between DT and GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating
or connected to GND fixed value of 55 ns deadtime is inserted.
Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs
by putting the gate drivers into the pull-down state. This signal bypasses and overrides
the digital core of the DRV8328.
DRVOFF
-
18
GHA
GHB
GHC
GLA
GLB
GLC
GND
7
7
O
O
O
O
O
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
11
15
8
11
15
8
12
16
28
12
16
28
PWR Device ground.
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
PIN
NO.
TYPE
DESCRIPTION
NAME
DRV8328A DRV8328C
DRV8328B DRV8328D
Gate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF
GVDD
4
4
PWR-O local capacitance between the GVDD and GND pins. TI recommends a capacitor value of
>10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
22
21
20
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
INHA
INHB
INHC
20
19
18
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
I
INLA
INLB
INLC
23
22
21
25
24
23
17
I
I
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low side source pin, connect all sources of the external low-side MOSFETs here. This pin
is the sink path for the low-side gate driver.
LSS
17
24
PWR
OD
27
26
Fault indicator output. This pin is pulled logic low during a fault condition and requires an
external pull-up resistor to 3.3V to 5.0V.
nFAULT
Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power
sleep mode. An 1 to 1.2-µs low pulse can be used to reset fault conditions without
entering sleep mode .
nSLEEP
PVDD
25
1
I
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R
or X7R, 0.1-µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the
PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal
operating voltage of the pin.
1
PWR
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
SHA
SHB
SHC
6
6
I/O
I/O
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
10
10
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
14
26
14
-
I/O
I
VDSLVL
VDS monitor trip point setting.
Thermal Pad
PWR Must be connected to GND
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
7 Specification
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX UNIT
Power supply pin voltage
Bootstrap pin voltage
PVDD
65
80
V
V
V
V
V
V
V
V
BSTx
Bootstrap pin voltage
BSTx with respect to SHx
BSTx with respect to GHx
CPL, CPH
20
Bootstrap pin voltage
20
Charge pump pin voltage
Gate driver regulator pin voltage
Analog regulator pin voltage
Logic pin voltage (nSLEEP)
VGVDD
20
GVDD
AVDD
4
nSLEEP
65
DRVOFF, DT, INHx, INLx, nFAULT,
VDSLVL
Logic pin voltage
-0.3
6
V
High-side gate drive pin voltage
GHx
-8
-10
-0.3
-8
80
80
20
70
72
20
20
0.3
1
V
V
V
V
V
V
V
V
V
V
V
Transient 500-ns high-side gate drive pin voltage
High-side gate drive pin voltage
GHx
GHx with respect to SHx
High-side source pin voltage
SHx
Transient 500-ns high-side source pin voltage
SHx
-10
-0.3
-1
Low-side gate drive pin voltage
GLx with respect to LSS
GLx with respect to LSS
GLx with respect to GVDD
GLx with respect to GVDD
LSS
Transient 500-ns low-side gate drive pin voltage(2)
Low-side gate drive pin voltage
Transient 500-ns low-side gate drive pin voltage
Low-side source sense pin voltage
-1
1
Transient 500-ns low-side source sense pin voltage
LSS
-10
8
Internally
Limited
Internally
Limited
Gate drive current
GHx, GLx
A
Junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Supports upto 5A for 500 nS when GLx-LSS is negative
7.2 ESD Ratings Comm
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VPVDD
Power supply voltage
PVDD
PVDD
4.5
60
30
V
Power supply voltage ramp rate at power
up
VPVDD_RAMP
V/us
Power supply voltage ramp rate during
operation
VPVDD_RAMP
PVDD
4
V/us
Bootstrap pin voltage with respect to
SHx
VBST
nSLEEP = High, INHx is switching
4
20
80
2
V
(1)
IAVDD
Regulator external load current
AVDD
BSTx
mA
µA
Trickle charge pump external load
current
ITRICKLE
VIN
Logic input voltage
DRVOFF, INHx, INLx, nSLEEP
DT, VDSLVL
0
0
0
5.5
3.4
200
5.5
-10
V
V
VIN
Logic input voltage
fPWM
VOD
IOD
PWM frequency
INHx, INLx
kHz
V
Open drain pullup voltage
Open drain output current
nFAULT
nFAULT
mA
Total average gate-drive current (Low
Side and High Side Combined)
(1)
IGS
IGHx, IGLx
30
mA
VSHSL
TA
Slew Rate on SHx pins
4
125
150
V/ns
°C
Operating ambient temperature
Operating junction temperature
–40
–40
TJ
°C
(1) Power dissipation and thermal limits must be observed
7.4 Thermal Information 1pkg
THERMAL METRIC(1)
DRV8328
RUY
UNIT
28
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
42.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.6
19.6
0.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
19.6
4.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
7.5 Electrical Characteristics
4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES (AVDD, PVDD, GVDD)
VPVDD =24V, nSLEEP = 0, TA = 25°C
nSLEEP = LOW
1
2
µA
µA
IPVDDQ
PVDD sleep mode current
PVDD standby mode current
VPVDD = 24 V; nSLEEP = HIGH, INHx =
INLX = LOW, DRVOFF = HIGH
2
3
4
5
mA
mA
IPVDDS
nSLEEP = HIGH, INHx = INLX = LOW,
DRVOFF = HIGH
VPVDD = 24 V, nSLEEP = HIGH, INHx
= INLX = Switching@20kHz, No FETs
connected
4
7
mA
nSLEEP = HIGH, INHx = INLX =
Switching@20kHz, No FETs connected
5
5
10
10
7
mA
mA
mA
µA
IPVDD
PVDD active mode current
VPVDD = 8 V, nSLEEP = HIGH, INHx =
INLX = LOW, No FETs connected
VPVDD = 24 V, nSLEEP = HIGH, INHx =
INLX = LOW, No FETs connected
5
VBSTx = VSHx = 60V, VGVDD = 0V,
nSLEEP = LOW
ILBSx
Bootstrap pin leakage current
5
10
115
16
300
Bootstrap pin active mode transient
leakage current
INLx = INHx = Switching@20kHz, No
FETs connected
ILBS_TRAN
60
µA
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
VPVDD = VSHX = VGVDD = 12V, VBSTx
VSHx = 5V
135
70
200
105
280
145
µA
µA
-
-
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
VPVDD = VSHX = VGVDD = 12V, VBSTx
VSHx = 7V
Bootstrap pin active mode leakage static
source current
ILBS_DC_SRC
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX
VGVDD = 12V, VBSTx - VSHx = 5V
=
25
16
10
14
80
15
80
15
50
28
90
50
µA
µA
µA
µA
µA
µA
µA
µA
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX
VGVDD = 12V, VBSTx - VSHx = 7V
=
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX
VGVDD = 12V, VBSTx - VSHx = 12V
=
40
90
Bootstrap pin active mode leakage static
sink current
ILBS_DC_SINK
INHx = High, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX
VGVDD = 12V, VBSTx - VSHx = 12V
=
45
91
INHx = INLx = LOW, VBSTx - VSHx
= 15, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
145
20
210
30
INHx = INLx = LOW, VBSTx - VSHx
= 11, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
ILSHx
Source pin leakage current
INHx = High, INLx = LOW, VBSTx
-
VSHx = 15, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
145
25
210
35
INHx = HIGH, INLx = LOW, VBSTx
-
VSHx = 11, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
nSLEEP = HIGH to Active
mode (Outputs Ready), DRVOFF =
LOW, CGVDD = 10 uF
1
2
ms
Turnon time (nSLEEP)
VPVDD = 12V, nSLEEP = HIGH to
Active mode (Outputs Ready), DRVOFF
= LOW, CGVDD = 10 uF
tWAKE
1
2
1
ms
ms
DRVOFF = LOW to Active mode
(Outputs Ready), nSLEEP = High
Turnon time (DRVOFF)
0.5
tSLEEP
tRST
Turnoff time
nSLEEP = LOW to Sleep mode
10
1
20
1.2
15
us
us
V
Minimum Reset Pulse Time
nSLEEP = LOW period to reset faults
VPVDD ≥ 40 V, IGS = 10 mA, TJ= 25°C
11.8
13
13
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA, TJ=
25°C
11.8
11.8
11.8
15
15
V
V
V
V
8 V ≤VPVDD ≤ 22 V, IGS = 30 mA, TJ=
25°C
GVDD Gate driver regulator voltage
(Room Temperature)
13
13
VGVDD_RT
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA, TJ=
25°C
14.5
13.5
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA, TJ= 2*VPVDD
25°C
- 1
11.5
11.5
11.5
11.5
VPVDD ≥ 40 V, IGS = 10 mA
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA
8 V ≤VPVDD ≤ 22 V; IGS = 30 mA
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA
15.5
15.5
15.5
14.5
V
V
V
V
VGVDD
GVDD Gate driver regulator voltage
2*VPVDD
- 1.4
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA
13.5
3.33
3.4
V
V
V
V
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 30 mA, TJ=
25°C
3.26
3.2
3.3
3.3
3.3
AVDD Analog regulator voltage (Room
Temperature)
VPVDD ≥ 6 V, 30 mA ≤ IAVDD ≤ 80 mA, TJ=
25°C
VAVDD_RT
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA, TJ=
25°C
3.13
3.46
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 80 mA
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA
3.2
3.3
3.3
3.4
3.5
V
V
VAVDD
AVDD Analog regulator voltage
3.125
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP etc)
DRVOFF
0.8
0.8
V
V
VIL
VIH
Input logic low voltage
Input logic high voltage
INLx, INHx pins
DRVOFF
2.2
2.2
200
45
-1
V
INLx, INHx pins
V
DRVOFF
400
240
0
650
350
1
mV
mV
µA
µA
µA
µA
kΩ
kΩ
kΩ
VHYS
IIL
Input hysteresis
INLx, INHx pins
Input logic low current
VPIN (Pin Voltage) = 0 V;
nSLEEP, VPIN (Pin Voltage) = 65 V;
nSLEEP, VPIN (Pin Voltage) = 5 V;
Other pins, VPIN (Pin Voltage) = 5 V;
DRVOFF To GND
3
6.5
6
10
IIH
Input logic high current
3
10
7
20
35
RPD_DRVOFF Input pulldown resistance
RPD_nSLEEP Input pulldown resistance
100
500
150
200
800
250
300
1500
350
nSLEEP To GND
RPD
Input pulldown resistance
All other pins To GND
OPEN-DRAIN OUTPUTS (nFAULT etc)
VOL
IOZ
Output logic low voltage
Output logic high current
IOD = 5 mA
VOD = 5 V
0.4
1
V
-1
µA
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
COD
Output capacitance
VOD = 5 V
30
pF
GATE DRIVERS (GHx, GLx, SHx, SLx)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
VGSHx_LO
VGSHx_HI
VGSLx_LO
VGSLx_HI
High-side gate drive low level voltage
0.05
0.28
0.05
0.28
8.4
0.11
0.44
0.11
0.44
9.6
0.24
0.82
0.27
0.82
11.1
9
V
V
V
V
V
V
V
Ω
Ω
Ω
Ω
High-side gate drive high level voltage
(VBSTx - VGHx
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
)
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
Low-side gate drive low level voltage
Low-side gate drive high level voltage
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
(VGVDD - VGHx
)
INHx = HIGH, INLx = LOW, INLy = INLz
= HIGH, VPVDD >15V, VGVDD ≥11.5V
High-side gate drive voltage in steady
INHx = HIGH, INLx = LOW, INLy = INLz
state with 100 % duty cycle (GHx- SHx) = HIGH, VGVDD ≥11.5V
VGSH_100_PH
7.5
8.3
INHx = HIGH, INLx = LOW, INLy = INLz
= HIGH, 7V ≥VGVDD ≥ 8V
5.9
6.5
7
RDS(ON)_PU_
High-side pullup switch resistance
High-side pulldown switch resistance
Low-side pullup switch resistance
Low-side pulldown switch resistance
IGHx = 100 mA; VGVDD= 12V
2.7
4.5
8.4
2.4
8.3
2.8
HS
RDS(ON)_PD_
IGHx = 100 mA; VGVDD = 12V
IGLx = 100 mA; VGVDD = 12V
IGLx = 100 mA; VGVDD = 12V
0.5
1.1
HS
RDS(ON)_PU_
2.7
4.5
LS
RDS(ON)_PD_
0.5
1.1
LS
IDRIVEP_HS
IDRIVEN_HS
IDRIVEP_LS
IDRIVEN_LS
RPD_LS
High-side peak source gate current
High-side peak sink gate current
Low-side peak source gate current
Low-side peak sink gate current
Low-side passive pull down
VGSHx = 12V
550
1150
550
1150
80
1000
2000
1000
2000
100
1575
2675
1575
2675
120
mA
mA
mA
mA
kΩ
VGSHx = 0V
VGSLx = 12V
VGSLx = 0V
GLx to LSS
RPDSA_HS
High-side semiactive pull down
GHx to SHx, VGSHx = 2V
8
10
12.5
kΩ
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay
tPDF_LS
INLx to GLx rising, VGVDD > 8V
INLx to GLx falling, VGVDD > 8V
70
70
100
100
135
135
ns
ns
Low-side falling propagation delay
High-side rising propagation delay
INHx to GHx rising, VGVDD = VBSTx
VSHx > 8V
-
-
tPDR_HS
tPDF_HS
65
70
100
100
135
140
ns
ns
INHx to GHx falling, VGVDD = VBSTx
VSHx > 8V
High-side falling propagation delay
GLx turning ON to GLx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-25
-28
-25
-25
±4
±4
±4
±4
25
28
25
25
ns
ns
ns
ns
GLx turning OFF to GHx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
tPD_MATCH_P
Matching propagation delay per phase
H
GHx turning ON to GHx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
GHx turning OFF to GLx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GHx turning ON to GHy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-10
±4
10
10
15
10
45
ns
ns
ns
ns
ns
GLx turning ON to GLy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-10
-15
-10
18
±4
±4
±4
32
tPD_MATCH_P Matching propagation delay phase to
phase
H_PH
GHx turning OFF to GHy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V to
60V, No load on GHx and GLx
GLx turning OFF to GLy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
Minimum input pulse width on INHx,
tPW_MIN
INLx that changes the output on GHx,
GLx
tDEAD
tDEAD
Gate drive dead time configurable range
Gate drive dead time
50
100
35
2000
240
90
ns
ns
ns
ns
ns
ns
DRV8328B, DRV8328D
160
55
DT pin floating (DRV8328A, DRV8328C)
DT pin connected to GND
35
55
80
tDEAD
Gate drive dead time
10 kΩ between DT pin and GND
390 kΩ between DT pin and GND
80
100
2000
140
2650
1500
BOOTSTRAP DIODES
VBOOTD Bootstrap diode forward voltage
IBOOT = 100 µA
IBOOT = 100 mA
0.8
1.6
V
V
Bootstrap dynamic resistance
(ΔVBOOTD/ΔIBOOT
RBOOTD
IBOOT = 100 mA and 50 mA
4.5
5.5
9
Ω
)
PROTECTION CIRCUITS
VPVDD rising
VPVDD falling
4.3
4
4.4
4.1
4.5
VPVDD_UV
PVDD undervoltage lockout threshold
PVDD undervoltagelockout hysteresis
V
4.25
VPVDD_UV_H
Rising to falling threshold
225
265
325
mV
µs
YS
tPVDD_UV_DG PVDD undervoltage deglitch time
VAVDD_POR AVDD supply POR threshold
10
2.7
2.5
20
2.85
2.65
30
3.0
2.8
AVDD rising
AVDD falling
V
VAVDD_POR_
AVDD POR hysteresis
Rising to falling threshold
170
7
200
12
250
22
mV
µs
HYS
tAVDD_POR_D
AVDD POR deglitch time
G
VGVDD rising
VGVDD falling
7.3
6.4
7.5
6.7
7.8
6.9
V
V
VGVDD_UV
GVDD undervoltage threshold
GVDD undervoltage hysteresis
VGVDD_UV_H
Rising to falling threshold
800
900
1000
mV
YS
tGVDD_UV_DG GVDD undervoltage deglitch time
VBST_UV Bootstrap undervoltage threshold
5
3.9
3.7
150
2
10
4.45
4.2
220
4
15
5
µs
V
VBSTx- VSHx; VBSTx rising
VBSTx- VSHx; VBSTx falling
Rising to falling threshold
4.8
275
6
V
VBST_UV_HYS Bootstrap undervoltage hysteresis
tBST_UV_DG Bootstrap undervoltage deglitch time
mV
µs
VDS overcurrent protection threshold
VDS_LVL_RNG
linear range
0.1
70
2.5
V
VDS overcurrent protection disable
VDS_DIS
resistor
VDSLVL pin to GVDD
100
500
kΩ
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
VDSLVL = 100 kΩ to GVDD
VDSLVL = 0.1V
MIN
TYP
4.2
0.1
2.5
0.5
1
MAX UNIT
3
5.5
0.145
2.8
V
VDS overcurrent protection threshold
Reference
VDS_LVL
0.065
2.2
V
VDSLVL pin = 2.5V
VSENSE_LVL VSENSE overcurrent protection threshold LSS to GND pin = 0.5V
0.48
0.5
0.52
2.7
V
tDS_BLK
tDS_DG
VDS overcurrent protection blanking time
µs
VDS and VSENSE overcurrent protection
deglitch time
1.5
3
5
µs
tSD_SINK_DIG DRVOFF peak sink current duration
3
0.5
7
5
1.5
14
7
2
µs
µs
µs
°C
°C
tSD_DIG
tSD
TOTSD
THYS
DRVOFF digital shutdown delay
DRVOFF analog shutdown delay
Thermal shutdown temperature
Thermal shutdown hysteresis
21
187
23
TJ rising;
160
16
170
20
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7.6 Typical Characteristics
8.5
8.25
8
7.75
7.5
7.25
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
14
13.5
13
-40 C
25 C
150 C
12.5
12
11.5
11
10.5
10
9.5
9
-40 C
25 C
150 C
8.5
8
0
5
10 15 20 25 30 35 40 45 50 55 60
PVDD Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60
PVDD Voltage (V)
Figure 7-1. Supply Current over PVDD Voltage
Figure 7-2. GVDD Voltage over PVDD Voltage
3.34
2500
-40 C
High Side Source
High Side Sink
Low Side Source
Low Side Sink
3.33
3.32
3.31
3.3
25 C
2250
150 C
2000
1750
1500
1250
1000
750
3.29
3.28
3.27
3.26
3.25
0
8
16
24
32
40
48
56
64
72
80
-40 -20
0
20
40
60
80 100 120 140
Junction Temperature (C)
Load Current (mA)
Figure 7-3. AVDD Voltage over Load Current
Figure 7-4. Driver Peak Current over Junction
Temperature
9
8.75
8.5
8.25
8
7.75
7.5
7.25
7
0.65
0.625
0.6
0.575
0.55
0.525
0.5
6.75
6.5
6.25
6
5.75
5.5
0.475
0.45
0.425
0.4
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Junction Temperature (C)
Junction Temperature ()
Figure 7-6. Bootstrap Diode Forward Voltage Drop
over Junction Temperature
Figure 7-5. Bootstrap Diode Resistance over
Junction Temperature
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8 Detailed Description
8.1 Overview
The DRV8328 family of devices is an integrated three-phase gate driver supporting an input voltage range
of 4.5- to 60-V. These devices decrease system component count, cost, and complexity by integrating three
independent half-bridge gate drivers, trickle charge pump, and a charge pump with linear regulator for the supply
voltages of the high-side and low-side gate drivers. DRV8328 also integrates an accurate low voltage regulator
(AVDD) capable of supporting 3.3V at 80mA output. A hardware interface allows for simple configuration of the
motor driver and control of the motor.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive upto 1-A
source, 2-A sink peak gate drive currents with a 30-mA average output current. A bootstrap circuit with capacitor
generates the supply voltage of the high-side gate drive and a trickle charge pump is employed to support 100%
duty cycle. The supply voltage of the low-side gate driver is generated using a charge pump with linear regulator
GVDD from the PVDD power supply that regulates to 12 V.
In addition to the high level of device integration, the DRV838x family of devices provides a wide range of
integrated protection features. These features include power supply undervoltage lockout (PVDDUV), regulator
undervoltage lockout (GVDDUV), Bootstrap Voltage undervoltage lockout (BSTUV), VDS overcurrent monitoring
(OCP), Sense resistor overcurrent monitoring (SEN_OCP) and overtemperature shutdown (TSD). Fault events
are indicated by the nFAULT pin.
The DRV8328 is available in 0.4-mm pitch, QFN surface-mount packages. The QFN size is 4 × 4 mm for the
28-pin package.
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8.2 Functional Block Diagram
PVDD
+
0.1 μF
bulk
Power
GVDD
PVDD
GVDD
HS
Trickle
CP
>10 μF
BSTA
GHA
SHA
VCP
Charge
Pump
CPH
CPL
470 nF
HS
GVDD
GLA
LS
LS
80 mA AVDD**
3.3-V LDO
LSS
1 μF
GVDD
HS
Trickle
CP
BSTB
GHB
SHB
PVDD
nSLEEP
INHA
HS
INLA
INHB
INLB
GVDD
GLB
LS
LS
Digital
LSS
Control
Control
Inputs
GVDD Trickle
CP
PVDD
INHC
INLC
BSTC
GHC
SHC
HS
HS
DT*
GVDD
GLC
LS
LS
RDT
LSS
nFAULT
Outputs
DRVOFF**
LSS
RSENSE
+
-
RSENSE
0.5
3x LS, 3x HS
VDS Comp
GND
VSENSE OCP
VDSLVL*
-
+
VDS
Thermal Pad
* DRV8328A, DRV8318B only
** DRV8328C, DRV8328D only
Figure 8-1. Block Diagram of DRV8328
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8.3 Feature Description
Table 8-1 lists the recommended values of the external components for the gate driver and the buck regulator.
Table 8-1. DRV8328 External Components
COMPONENTS
CPVDD1
CPVDD2
CCP
PIN 1
PVDD
PVDD
CPH
PIN 2
PGND
PGND
CPL
RECOMMENDED
X5R or X7R, 0.1-µF, >2x PVDD-rated capacitor
≥ 10 µF, >2x PVDD-rated capacitor
X5R or X7R, 470-nF, PVDD-rated capacitor
X5R or X7R, ≥10-uF, 25V-rated capacitor
X5R or X7R, ≥1-µF, 6.3-V capacitor
Pullup resistor
CGVDD
GVDD
AVDD
VCC(1)
DT
GND
CAVDD
AGND
nFAULT
AGND
RnFAULT
RDT
Hardware interface resistor
(1) The VCC pin is not a pin on the DRV8328 , but a VCC supply voltage pullup is required for the open-drain output, nFAULT. This pin
can also be pulled up to AVDD.
8.3.1 Three BLDC Gate Drivers
The DRV8328 family of devices integrates three half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. A charge pump is used to generate the GVDD to supply the correct gate
bias voltage across a wide operating voltage range. The low side gate outputs are driven directly from GVDD,
while the high side gate outputs are driven using a bootstrap circuit with an integrated diode, and an internal
trickle charge pump provides support for 100% duty cycle operation. The half-bridge gate drivers can be used in
combination to drive a three-phase motor or separately to drive other types of loads.
8.3.1.1 PWM Control Modes
The DRV8328 provides two different PWM control modes to support various commutation and control methods.
The PWM control modes are supported in different device variants (see Table 5-1)
8.3.1.1.1 6x PWM Mode
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-2.
Table 8-2. 6x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
Hi-Z
H
0
0
1
1
0
1
0
1
L
L
H
L
L
H
L
L
L
Hi-Z
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8.3.1.1.2 3x PWM Mode
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 8-3.
Table 8-3. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
Hi-Z
L
0
1
1
X
0
1
L
L
H
L
L
H
H
8.3.1.2 Device Hardware Interface
The DRV8328 utilize a hardware interface to configure different device settings. These hardware configurable
inputs are DT and VDSLVL. General fault information is reported on the nFAULT pin.
•
•
The DT pin configures the gate drive dead time. The dead time can adjusted by changing the resistor value
from the DT pin to GND.
The VDSLVL pin configures the voltage threshold of the VDS overcurrent monitors. The voltage applied to the
VDSLVL pin is directly used as reference for the VDS comparator
For more information on the hardware interface, see Section 8.3.3.
VDSLVL
Hardware
Interface
DT
RDT
Figure 8-2. Hardware Interface
8.3.1.3 Gate Drive Architecture
The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This
topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate drivers
are supplied directly from the GVDD regulator supply. For the high-side gate drivers a bootstrap diode and
capacitor are used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and
an external bootstrap capacitor is used on the BSTx pin. To support 100% duty cycle control, a trickle charge
pump is integrated into the device. The trickle charge pump is connected to the BSTx node to prevent voltage
drop due to the leakage currents of the driver and external MOSFET.
The high-side gate driver has semi-active pull down and low side gate has passive pull down to help prevent the
external MOSFET from turning ON during sleep state or when power supply is disconnected.
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CGVDD
PVDD
Trickle
Charge
Pump
CGVDD
CPH
Charge
Pump
DBSTx
VBAT
CCP
BSTx
CPL
CBSTx
GHx
INHx
Level
Shifters
SHx
INLx
Digital
Core
GVDD
GLx
LSS
Level
Shifters
GND
GND
Figure 8-3. Gate Driver Block Diagram
8.3.1.3.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the digital propagation delay, and the delay through the analog
gate drivers.
To support multiple control modes and dead time insertion, a small digital delay is added as the input command
propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall
propagation delay of the device.
8.3.1.3.2 Deadtime and Cross-Conduction Prevention
In the DRV8328, high- and low-side inputs operate independently, with an exception to prevent cross conduction
when the high and low side of the same half-bridge are turned ON at same time. The device turns OFF high- and
low- side output to prevent shoot through when high- and low-side inputs are logic high at same time.
The DRV8328 also provide dead time insertion in device variants DRV8328A and DRV8328B to prevent both
external MOSFETs of each half-bridge from switching on at the same time. In devices with a DT pin, deadtime
can be linearly adjusted between 100 nS and 2000 nS by connecting resistor between DT and ground. When the
DT pin is left floating or connected to GND, a fixed deadtime of 55 nS (typical value) is inserted. The value of
resistor can be calculated using following equation.
Deadtime ns
R
kΩ
=
− 10 kΩ
(1)
DT
5
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In device variants without a DT pin (DRV8328C, DRV8328D), a fixed deadtime of 160 nS (typical value) is
inserted to prevent high and low side gate output turning on at same time.
INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
Figure 8-4. Cross Conduction Prevention and Deadtime Insertion
8.3.2 AVDD Linear Voltage Regulator
A 3.3-V, 80-mA linear regulator is integrated into the DRV8328C and DRV8328D variants and is available for use
by external circuitry. The output of the LDO is fixed to 3.3-V. This regulator can provide the supply voltage for
a low-power MCU or other circuitry with low supply current needs. The output of the AVDD regulator should be
bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor routed back to the GND pin.
PVDD
REF
+
œ
AVDD
AGND
3.3-V, 80 mA
1 …F
Figure 8-5. AVDD Linear Regulator Block Diagram
The power dissipated in the device by the AVDD linear regulator can be calculated as follows: P = (VPVDD
-
VAVDD) x IAVDD
For example, at a VPVDD of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in
Equation 2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
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8.3.3 Pin Diagrams
Figure 8-6 shows the input structure for the logic level pins, INHx, INLx, The input can be driven with a voltage or
external resistor.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
100 kꢀ
Figure 8-6. Logic-Level Input Pin Structure
Figure 8-7 shows the structure of the open-drain output pins, nFAULT. The open-drain output requires an
external pullup resistor to function correctly.
DVDD
R
PU
STATE
No Fault
Fault
STATUS
Inactive
Active
OUTPUT
Active
Inactive
Figure 8-7. Open-Drain Output Pin Structure
8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
When DRVOFF is driven high, the gate driver goes into shutdown, overriding signals on inputs pins INHx and
INLx. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver
output (see Figure 8-8). This pin provides a mechanism for externally monitored faults to disable gate driver by
directly bypassing an external controller or the internal control logic. When DRV8328 detect the DRVOFF pin is
driven high, the device disables the gate driver and puts it into pulldown mode (see Figure 8-9). The gate driver
shutdown sequence proceeds as shown in Figure 8-9. When the gate driver initiates the shutdown sequence,
the active driver pulldown is applied at ISINK current for the tSD_SINK_DIG time, after which the gate driver moves to
passive pulldown mode.
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PVDD
OFF
DRVOFF
GHA
GHB
GHC
OFF
OFF
A
B
Gate
Driver
Digital
OFF
C
GLA
GLB
GLC
OFF
OFF
GND
Figure 8-8. DRV8328 DRVOFF Gate Driver Output State
High
INHx (INLx)
GHx-SHx
(GLx-LSS)
tSD_DIG
DRVOFF pin
tSD_SINK_DIG
tSD
Passive (RPD_LS) and Semiactive
PullDown (RPDSA_HS
Predriver
Current
ISOURCE/ISINK
ISINK
)
Figure 8-9. Gate Driver Shutdown Seqeunce
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8.3.5 Gate Driver Protective Circuits
The DRV8328 are protected against PVDD undervoltage and overvoltage, AVDD power-on reset, bootstrap
undervoltage, GVDD undervoltage, MOSFET VDS and VSENSE overcurrent events.
Table 8-4. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
PVDD
undervoltage
(PVDD_UV)
Automatic:
VPVDD > VPVDD_UV
VPVDD < VPVDD_UV
-
nFAULT
Disabled1
Disabled
AVDD POR
(AVDD_POR)
Automatic:
VAVDD > VAVDD_POR
VAVDD < VAVDD_POR
-
-
nFAULT
nFAULT
Disabled1
Disabled
Active
GVDD
undervoltage
(GVDD_UV)
Latched:
CLR_FLT, nSLEEP Reset Pulse
VGVDD < VGVDD_UV
Pulled Low 2
BSTx
undervoltage
(BST_UV)
VBSTx - VSHx < VBST_UV and
INHx = High
Latched:
CLR_FLT, nSLEEP Reset Pulse
-
nFAULT
Pulled Low 2
Active
Latched:
CLR_FLT, nSLEEP Reset Pulse
0.1V < VVDSLVL < 2.5V
nFAULT
None
Pulled Low 2
Active
Active
Active
Active
Active
VDS overcurrent
(VDS_OCP)
VDS > VDS_LVL
VDSLVL pin 100kΩ
tied to GVDD
No action
Latched:
CLR_FLT, nSLEEP Reset Pulse
-
nFAULT
None
Pulled Low 2
Active
VSENSE
overcurrent
(SEN_OCP)
VSP > VSENSE_LVL
VDSLVL pin 100kΩ
tied to GVDD
No action
Thermal
shutdown
(OTSD)
Latched:
CLR_FLT, nSLEEP Reset Pulse
TJ > TOTSD
-
nFAULT
Pulled Low 2
Active
1. Disabled: Passive pull down for GLx and semiactive pull down for GHx
2. Pulled Low: GHx and GLx are actively pulled low by the gate driver
8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
If at any time the power supply voltage on the PVDD pin falls below the VPVDD_UV threshold for longer than the
tPVDD_UV_DG time, the device detects a PVDD undervoltage event. After detecting the undervoltage condition, the
gate driver is disabled, the charge pump is disabled, the internal digital logic is disabled, and the nFAULT pin is
driven low. Normal operation starts again (the gate driver becomes operable and the nFAULT pin is released)
when the PVDD pin rises above VPVDD_UV
.
8.3.5.2 AVDD Power on Reset (AVDD_POR)
If at any time the supply voltage on the AVDD pin falls below the VAVDD_POR threshold for longer than the
tAVDD_POR_DG time, the device enters an inactive state, disabling the gate driver, the charge pump, and the
internal digital logic, and nFAULT is driven low. Normal operation (digital logic operational) requires nSLEEP to
be asserted high and AVDD to exceed VAVDD_POR level.
8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
If at any time the voltage on the GVDD pin falls lower than the VGVDD_UV threshold voltage for longer than the
tGVDD_UV_DG time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage
event, all of the gate driver outputs are driven low to disable the external MOSFETs,and nFAULT pin is driven
low. After the GVDD_UV condition is cleared, the fault state remains latched and can be cleared through an
nSLEEP pin reset pulse (tRST
)
Note
After the GVDD_UV fault is cleared through an nSLEEP pin reset pulse, the nFAULT pin is held low
until the GVDD capacitor is refreshed by the charge pump. After the GVDD capacitor is charged, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low after the fault is cleared
will not exceed tWAKE time.
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8.3.5.4 BST Undervoltage Lockout (BST_UV)
If at any time the voltage across BSTx and SHx pins falls lower than the VBST_UV threshold voltage for longer
than the tBST_UV_DG time, the device detects a BST undervoltage event. Afer detecting the BST_UV event, all of
the gate driver outputs are driven low to disable the external MOSFETs, and nFAULT pin is driven low. After the
BST_UV condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset
pulse (tRST).
8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
The device has adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external
power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the
external MOSFET RDS(on). The high-side VDS monitors measure between the PVDD and SHx pins and the low-
side VDS monitors measure between the SHx and LSS pins. If the voltage across external MOSFET exceeds
the VDS_LVL threshold for longer than the tDS_DG deglitch time, a VDS_OCP event is recognized. Afer detecting
the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and
nFAULT pin is driven low. The VDS threshold can be set between 0.1V to 2.5V by applying voltage on VDSLVL
pin and the VDS deglitch time is fixed at 3 µs. VDS OCP can be disabled by connecting VDSLVL to GVDD
through a 100kΩ resistor. After the VDS_OCP condition is cleared, the fault state remains latched and can be
cleared through the nSLEEP pin reset pulse (tRST). VDS OCP is disabled for the DRV8328C and DRV8328D
device options.
PVDD
PVDD
+
VDS
+
–
VDS
–
V
V
VDS_OCP
GHx
SHx
GLx
+
–
+
–
VDS
VDS_OCP
VDS
LSS
GND
Figure 8-10. DRV8328 VDS Monitors
8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
Overcurrent is also monitored by sensing the voltage drop across the external current sense resistor between
LSS and GND pin. If at any time the voltage on the LSS input exceeds the VSEN_OCP threshold for longer than
the tOCP_DEG deglitch time, a SEN_OCP event is recognized. Afer detecting the SEN_OCP overcurrent event, all
of the gate driver outputs are driven low to disable the external MOSFETs and nFAULT pin is driven low. The
VSENSE threshold is fixed at 0.5 V and deglitch time is fixed to 3 µs. After the SEN_OCP condition is cleared,
the fault state remains latched and can be cleared through an nSLEEP pin reset pulse (tRST). SEN_OCP can be
disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor. SEN_OCP is disabled for the DRV8328C
and DRV8328D device options.
8.3.5.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), an OTSD event is recognized.
Afer detecting the OTSD overtemperature event, all of the gate driver outputs are driven low to disable the
external MOSFETs, and nFAULT pin is driven low. After OTSD condition is cleared, the fault state remains
latched and can be cleared through an nSLEEP pin reset pulse (tRST
)
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8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the DRV8328. When the nSLEEP pin is low, the device goes to a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
GVDD regulator is disabled and the AVDD regulator is disabled. The tSLEEP time must elapse after a falling edge
on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if
the nSLEEP pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held
low as the internal regulators are not active. After the regulators have been active, the nFAULT pin is
automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE
time.
8.4.1.2 Operating Mode
When the nSLEEP pin is high and the VPVDD voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the GVDD
regulator and AVDD regulator are active
8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
In the case of device latched faults, the DRV8328 goes into a partial shutdown state to help protect the external
power MOSFETs and system.
When the fault condition clears, the device can be re-enabled by issuing a reset pulse to the nSLEEP pin. The
nSLEEP reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The reset pulse has
no effect on any of the regulators, device settings, or other functional blocks as long as the low period of the
sequence falls within the tRST time window. If the pulse is longer than the tRST time window, the device will start a
complete shutdown sequence.
Note
If the user wants to put the device into sleep state after latched fault event, the inputs INHx ans INLx
needs to be pulled low prior to driving nSLEEP pin. If the inputs INHx and INLx are not driven low then
the fault is reset after nSLEEP is driven low for tRST time and there can be pulses on gate driver output
GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx can of duration
be tSLEEP if INHx and INLx are not pulled low
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8328 family of devices is primarily used in applications for three-phase brushless DC motor control. The
design procedures in the Section 9.2 section highlight how to use and configure the DRV8328 family of devices.
9.2 Typical Application
9.2.1 Three Phase Brushless-DC Motor Control
In this application, the DRV8328 is used to drive a three-phase Brushless-DC motor.
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PVDD
PVDD
BSTA
GVDD
CPH
>10 uF
470 nF
>10 uF
0.1 uF
PVDD
CBSTA
RGHA
GHA
SHA
CPL
AVDD**
>1uF
AVDD
RGLA
GLA
DRV8328
INHA
INLA
PVDD
BSTB
CBSTB
RGHB
INHB
INLB
GHB
SHB
PWM
MCU
INHC
INLC
RGLB
GLB
DRVOFF**
VDSLVL*
PVDD
BSTC
Analog Input
(0.1 to 2.5V)
CBSTC
R
GHC
GHC
SHC
DT*
RGLC
GLC
LSS
GND
INA+
INB+ INC+
*DRV8328A, DRV8328B
**DRV8328C, DRV8328D
R
INA-
INB-
INC-
R
R
N-
INx+
INx-
N-
N+
R
R
IN-
N+
–
OUT
IN+
+
AVDD
V
R
REF
Current Sense Amplifier 1x or 3x
+
–
Figure 9-1. DRV8328 Application Diagram
9.2.1.1 Detailed Design Procedure
Section 9.2.1.1 lists the example input parameters for the system design.
Table 9-1. Design parameters
DESIGN PARAMETERS
Supply voltage
REFERENCE
VPVDD
IPEAK
EXAMPLE VALUE
24 V
20 A
Motor peak current
PWM Frequency
fPWM
20 kHz
120 V/us
108 nC
14 nC
MOSFET VDS Slew Rate
MOSFET input gate capacitance
MOSFET input gate capacitance
SR
QG
QGD
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Table 9-1. Design parameters (continued)
DESIGN PARAMETERS
REFERENCE
EXAMPLE VALUE
200 ns
Dead time
tdead
Overcurrent protection
IOCP
30 A
9.2.1.1.1 Motor Voltage
Brushless-DC motors are typically rated for a certain voltage (for example 18-V or 36-V). The DRV8311 allows
for a range of possible operating voltages from 4.5-V to 60-V.
9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 3 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F8$116&F8
$5678
(3)
=12 V – 0.85 V – 4.5 V = 6.65 V
where
•
•
•
VGVDD is the supply voltage of the gate drive
VBOOTD is the forward voltage drop of the bootstrap diode
VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with Equation 4:
+.$5_64#05
3616 = 3) +
B
59
(4)
=48 nC + 220 μA/20 kHz = 50 nC + 11 nC = 59 nC
where
•
•
•
QG is the total MOSFET gate charge
ILBS_TRAN is the bootstrap pin leakage current
fSW is the is the PWM frequency
The minimum bootstrap capacitor an then be estimated as below assuming 1V ΔVBSTx
:
3
%
=
616W
$56_/+0
¿8
$56:
(5)
= 59 nC / 1 V = 59 nF
The calculated value of minimum bootstrap capacitor is 59 nF. It should be noted that, this value of capacitance
is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated
value to allow for situations where the power stage may skip pulse due to various transient conditions. It is
recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to include enough
margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
%
)8&&
R 10 × %$56:
(6)
= 10*100 nF= 1 μF
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For this example application choose 1 µF CGVDD capacitor. Choose a capacitor with a voltage rating at
least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long term reliability of the system.
9.2.1.1.3 Gate Drive Current
Selecting an appropriate gate drive current is essential when turning on or off power MOSFETs gates to
switch motor current. The amount of gate drive current and input capacitance of the MOSFETs determines the
drain-to-source voltage slew rate (VDS). Gate drive current can be sourced from GVDD into the MOSFET gate
(ISOURCE) or sunk from the MOSFET gate into SHx or LSS (ISINK).
Using too high of a gate drive current can turn on MOSFETs too quickly which may cause excessive ringing,
dV/dt coupling, or cross-conduction from switching large amounts of current. If parasitic inductances and
capacitances exist in the system, voltage spiking or ringing may occur which can damage the MOSFETs or
DRV8328 device.
PVDD
PVDD
VINHx
VGHx
GVDD
I
INHx
GHx
HS
HS
VDS
SHx
PHASE
CGD
DLx
GLx
VGLx
GVDD
INLx
LS
LS
LSS
Figure 9-2. Effects of high gate drive current
On the other hand, using too low of a gate drive current causes long VDS slew rates. Turning on the MOSFETs
too slowly may heat up the MOSFETs due to RDS,on switching losses.
The relationship between gate drive current IGATE, MOSFET gate-to-drain charge QGD, and VDS slew rate
switching time trise,fall are described by the following equations:
V
DS
SR
I
=
t
(7)
(8)
DS
rise, fall
Q
gd
=
GATE
t
rise, fall
It is recommend to evaluate at lower gate drive currents and increase gate drive current settings to avoid
damage from unintended operation during initial evaluation.
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9.2.1.1.4 Gate Resistor Selection
The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs is
controlled. The pull-up/pull-down strength of the DRV8328 is fixed internally, hence slew rate of gate voltage can
be controlled with an external series gate resistor. In some applications the gate charge, which is load on gate
driver device, is significantly larger than gate driver peak output current capability. In such applications external
gate resistors can limit the peak output current of the gate driver. External gate resistors are also used to damp
ringing and noise.
The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final slew rate,
so generally selecting an optimal value or configuration of external gate resistor is an iterative process.
To lower the gate drive current, a series resistor RGATE can be placed on the gate drive outputs to control the
current for the source and sink current paths. A single gate resistor will have the same gate path for source
and sink current, so larger RGATE values will yield similar SHx slew rates. Note that gate drive current varies by
PVDD voltage, junction temperature, and process variation of the device.
PVDD
PVDD
GVDD
RGATE
INHx
GHx
SHx
HS
HS
GVDD
RGATE
INLx
GLx
LSS
LS
LS
RSINK
Figure 9-3. Gate driver outputs with series resistors
Typically, it is recommended to have the sink current be twice the source current to implement a strong pulldown
from gate to the source to ensure the MOSFET stays off while the opposite FET is switching. This can be
implemented discretely by providing a separate path through a resistor for the source and sink currents by
placing a diode and sink resistor (RSINK)in parallel to the source resistor (RSOURCE). Using the same value of
source and sink resistors results in half the equivalent resistance for the sink path. This yields twice the gate
drive sink current compared to the source current, and SHx will slew twice as fast when turning off the MOSFET.
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PVDD
PVDD
GVDD
RSOURCE
INHx
GHx
SHx
HS
HS
RSINK
GVDD
RSOURCE
INLx
GLx
LSS
LS
LS
RSINK
Figure 9-4. Gate driver outputs with separate source and sink current paths
9.2.1.1.5 System Considerations in High Power Designs
Higher power system designs can require design and application considerations that are not regarded in lower
power system designs. It is important to combat the volatile nature of higher power systems by implementing
troubleshooting guidelines, external components and circuits, driver product features, or layout techniques. For
more information, please visit the System Design Considerations for High-Power Motor Driver Applications
application note.
9.2.1.1.5.1 Capacitor Voltage Ratings
Use capacitors with voltage ratings that are 2x the supply voltage (PVDD, GVDD, AVDD, etc.) Capacitors can
experience up to half the rated capacitance due to poor DC voltage rating performance.
9.2.1.1.5.2 External Power Stage Components
External components in the power stage are not required by design but are helpful in suppressing transients,
managing inductor coil energy, mitigating supply pumping, dampening phase ringing, or providing strong gate-to-
source pulldown paths. These components are used for system tuning and debuggability so the BLDC motor
system is robust while avoiding damage to the DRV8328 device or external MOSFETs.
Figure 9-5 shows examples of power stage components that can be optimally placed in the design.
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PVDD
PVDD
GVDD
RSNUB
RSOURCE
CBULK
RPD
INHx
GHx
SHx
HS
HS
RSINK
CSNUB
PHASE
CHSD_LSS
CSNUB
GVDD
RSOURCE
RPD
INLx
GLx
LSS
LS
LS
RSNUB
DGS
RSINK
Figure 9-5. Optional external power stage components
Some examples of issues and external components that can resolve those issues are found in Table 9-2:
Table 9-2. Common issues and resolutions for power stage debugging
Issue
Resolution
Component(s)
Gate drive current required is too large,
Series resistors required for gate drive
0-100 Ω series resistors at gate driver
outputs (GHx/GLx), optional sink resistor
and diode in parallel with gate resistor for
adjustable sink current
resulting in very fast MOSFET VDS slew rate current adjustability
Ringing at phase’s switch node (SHx)
resulting in high EMI emissions
RC snubbers placed in parallel to each
HS/LS MOSFET to dampen oscillations
Resistor and capacitor (DNP) placed parallel
to the MOSFET, calculate RC values based
on ringing frequency using Proper RC
Snubber Design for Motor Drivers
Negative transients at low-side source (LSS) HS drain to LS source capacitor to suppress 0.01uF-1uF, VM-rated capacitor from PVDD-
below minimum specification
negative bouncing
LSS, placed near LS MOSFET’s source
Negative transient at low-side gate (GLx)
below minimum specification
Gate-to-ground Zener diode to clamp
negative voltage
10-V rated Zener diode with anode
connected to GND and cathode connected to
GLx
Extra protection required to ensure MOSFET External gate-to-source pulldown resistors
10kΩ to 100kΩ resistor connected from GHx-
SHx or GLx-LSS for each gate output (add
between gate resistor and MOSFET gate)
is turned off if gate drive signals are stuck on (after series gate resistors)
or off
9.2.1.1.5.3 Parallel MOSFET Configuration
If higher MOSFET continuous drain current ratings are required for the motor, parallel MOSFETs can be used for
higher current capability. However, this require special schematic and layout design requirements to switch both
MOSFETs simultaneously because one MOSFET may turn on faster than the other due to process variation.
It is recommended to place the MOSFETs close together with a common gate signal that splits as close as
possible to the MOSFETs gates as shown in Figure 9-6. If gate resistance is required, calculate the equivalent
resistance required for the equivalently rated MOSFET, and place the gate resistors as close as possible to the
MOSFET’s gate input to dampen any coupling into the gate driver.
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For instance, if 400-A motor current is required with 5 Ω gate resistance, two 200-A rated MOSFETs and a 10-Ω
gate resistor at each MOSFET can be used. The equivalent circuit is a single MOSFET with 400-A current and 5
Ω resistance.
Figure 9-6. Parallel MOSFET configuration
For more information, please visit the Driving Parallel MOSFETs application brief.
9.2.1.1.6 Dead Time Resistor Selection (DRV8328A/B only)
Dead time insertion is available in the DRV8328A/B variants via a resistor (RDT) from the DT pin to ground as
shown in Figure 9-7. The ranges of dead time in the DRV8328 is 100 ns to 2000 ns when RDT is tied to GND
from the DT pin, and a dead time of 55 ns is inserted when the DT pin is left floating. A minimum resistance of 10
kΩ yields a dead time of 100 ns, and the maximum resistance of 390 kΩ yields a dead time of 2000 ns. A linear
interpolation of the resistance value is used to set the appropriate dead time.
RDT
DT
Figure 9-7. Dead time resistor
Dead time (in nanoseconds) can be calculated from the dead time resistor calculation in Equation 1.
Dead time can also be implemented from the PWM inputs generated by an MCU. If dead time is inserted at the
PWM inputs and the DRV8328, then the driver output PWM dead time is the larger of the two dead times. For
instance, if 200 ns dead time is inserted at the MCU inputs and 50 ns dead time is inserted in the DRV8328 via
the DT pin, then the output driver PWM dead time will be 200 ns.
9.2.1.1.7 VDSLVL Selection (DRV8328A/B only)
VDSLVL is an analog voltage used to directly set the VDS overcurrent threshold for overcurrent protection. It can
be sourced directly from an analog voltage source (such as a digital-to-analog converter) or divided down from a
voltage rail (such as a resistor divider from AVDD) as shown in Figure 9-8.
Vin
R1
VDSLVL
R2
Figure 9-8. Resistor divider to set VDSLVL from a voltage rail
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Equation 9 and Equation 10 can be used to set the required VDSLVL voltage using a resistor divider from a
voltage source to establish an overcurrent limit given the RDS,on of the MOSFETs used:
V
= I × R
OC ds on
(9)
VDSLVL
R
R
V
1
2
in
=
− 1
(10)
V
VDSLVL
where:
•
•
•
•
•
VVDSLVL = VDSLVL voltage
IOCP = VDS overcurrent limit
RDS,on = MOSFET on-resistance
VIN = voltage source for VDSLVL voltage divider
R1/R2 = resistor ratio for setting VDSLVL
9.2.1.1.8 AVDD Power Losses (DRV8328C/D only)
In the DRV8328C and DRV8328D, an integrated LDO can supply a 3.3V up to 80-mA as power rails for external
ICs or supply the pullup voltages for resistors and switches. The power loss from AVDD with respect to PVDD,
AVDD voltage, and AVDD current is PAVDD = (VPVDD - VAVDD) x IAVDD
.
Higher power losses occur due larger dropout from PVDD to 3.3V or increased AVDD load current.
9.2.1.1.9 Power Dissipation and Junction Temperature Losses
To calculate the junction temperature of the DRV8328 from power losses, use Equation 11. Note that the thermal
resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB layers,
copper thickness on top and bottom layers, and the PCB area.
℃
W
T ℃ = P
W × θ
+ T ℃
A
(11)
J
loss
JA
9.2.2 Application Curves
Figure 9-9. Device Powerup with PVDD
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Figure 9-10. Device Powerup with nSLEEP
Figure 9-11. GVDD voltage threshold (PVDD = 4.5 V)
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Figure 9-12. GVDD voltage threshold (PVDD = 20V)
Figure 9-13. AVDD powerup (DRV8328C/D only)
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Figure 9-14. DRVOFF operation
Figure 9-15. Driver PWM operation, 20 kHz, 50% duty cycle, zoomed
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Figure 9-16. Driver dead time of 100 ns (DT = 10 kΩ to GND)
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9 Power Supply Recommendations
The DRV8328 family of devices is designed to operate from an input voltage supply (PVDD) range from 6 V to
60 V. A 0.1-µF ceramic capacitor rated for PVDD must be placed as close to the device as possible. In addition,
a bulk capacitor must be included on the PVDD pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 9-1. Motor Drive Supply Parasitics Example
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10 Layout
10.1 Layout Guidelines
Bypass the PVDD pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 470 nF, rated for
PVDD, and be of type X5R or X7R.
The bootstrap capacitors (BSTx-SHx) should be placed closely to device pins to minimize loop inductance for
the gate drive paths.
The dead time resistor (RDT) should be placed as close as possible to the DT pin.
Bypass the AVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or
X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND
pin.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
When designing higher power systems, physics in the PCB layout can cause parasitic inductances,
capacitances, and impedances that deter the performance of the system as shown in Figure 10-1.
Understanding the parasitics that are present in a higher power motor drive system can help designers mitigate
their effects through good PCB layout. For more information, please visit the System Design Considerations for
High-Power Motor Driver Applications and Best Practices for Board Layout of Motor Drivers application notes.
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SLVSFF3A – DECEMBER 2021 – REVISED FEBRUARY 2022
PVDD
LP
RP
PVDD
CP
GVDD
CBULK
LP
LP
RSNUB
RGATE
INHx
GHx
SHx
HS
HS
LP
CSNUB
PHASE
CP
CSNUB
GVDD
LP
LP
RGATE
INLx
GLx
LSS
LS
LS
RSNUB
LP
RPDIFF
LP
LP
CP
SNx
LP
Figure 10-1. Parasitics in the PCB of a BLDC motor driver powerstage
Gate drive traces (BSTx, GHx, SHx, GLx, LSS) should be at least 15-20mil wide and as short as possible to the
MOSFET gates to minimize parasitic inductances and impedances. This helps supply large gate drive currents,
turn MOSFETs on efficiently, and improves VGS and VDS monitoring. If a shunt resistor is used to monitor the
low-side current from LSS to GND, ensure the shunt resistor selected is wide to minimize inductance introduced
at the low-side source LSS.
TI recommends connecting all non-power stage circuitry (including the thermal pad) to GND to reduce parasitic
effects and improve power dissipation from the device. Ensure grounds are connected through net-ties or wide
resistors to reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
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10.2 Layout Example
DRV8328 Layout
Figure 10-2. Layout of DRV8328 device
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Power Stage Layout
Figure 10-3. Layout of inverter power stage
10.3 Thermal Considerations
The DRV8328 has thermal shutdown (TSD) to protect against overtemperature. A die temperature in excess of
150°C (minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
The DRV8328 integrates a variety of circuits that contribute to total power losses. These power losses include
standby power losses, GVDD power losses, and AVDD power losses.
At start-up and fault conditions, this current is much higher than normal running current; remember to take these
peak currents and their duration into consideration.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
Table 10-1 shows a summary of equations for calculating each loss in the DRV8328.
Table 10-1. DRV8328 Power Losses
Loss type
Standby power
GVDD (CP mode)
GVDD (LDO mode)
AVDD LDO
Equation
Pstandby = VPVDD x IPVDDS
PLDO = 2 x VPVDD x IGVDD - VGVDD x IGVDD
PLDO = (VPVDD - VGVDD) x IGVDD
PLDO = (VPVDD - VAVDD) x IAVDD
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
•
•
•
•
Texas Instruments, DRV8328AEVM evaluation module
Refer to the application note System Design Considerations for High-Power Motor Driver Applications
Refer to the E2E FAQ How to Conduct a BLDC Schematic Review and Debug
Refer to the application note Best Practices for Board Layout of Motor Drivers
Refer to the application note QFN and SON PCB Attachment
Refer to the application note Cut-Off Switch in High-Current Motor-Drive Applications
Refer to the application note Hardware design considerations for an efficient vacuum cleaner using a BLDC
motor
•
•
Refer to the application note Hardware Design Considerations for an Electric Bicycle Using a BLDC Motor
Refer to the application note Sensored 3-Phase BLDC Motor Control Using MSP430
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
11.6 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8328ARUYR
DRV8328BRUYR
ACTIVE
WQFN
WQFN
RUY
28
28
5000 RoHS & Green
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
DRV
8328A
ACTIVE
RUY
NIPDAU
DRV
8328B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8328ARUYR
DRV8328BRUYR
WQFN
WQFN
RUY
RUY
28
28
5000
5000
330.0
330.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8328ARUYR
DRV8328BRUYR
WQFN
WQFN
RUY
RUY
28
28
5000
5000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RUY0028A
A
4.1
3.9
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SQ 2.6±0.1
2X 2.4
8
14
24X 0.4
7
15
SYMM
29
2X
2.4
0.25
28X
0.15
21
0.1
C A B
C
1
0.05
28
22
0.5
0.3
28X
SYMM
4219146/C 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RUY0028A
2X (3.8)
SQ (2.6)
2X (2.4)
22
28
28X (0.6)
28X (0.2)
1
21
24X (0.4)
SYMM
29
2X
2X
(2.4) (3.8)
2X (1.05)
7
15
(R0.05) TYP
(Ø0.2) VIA
TYP
14
8
2X (1.05)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219146/C 03/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RUY0028A
PLASTIC QUAD FLATPACK-NO LEAD
2X (3.8)
4X
SQ (1.15)
28
22
28X (0.6)
28X (0.2)
29
1
21
24X (0.4)
SYMM
2X
(3.8)
2X (0.675)
7
15
(R0.05) TYP
METAL TYP
14
8
2X (0.675)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 15X
4219146/C 03/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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