DRV8329AREER_技术文档

DRV8329

SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

DRV8329 4.5 to 60 V Three-phase BLDC Gate Driver

1 Features

3 Description

•

65-V Three Phase Half-Bridge Gate Driver

– Drives 3 High-Side and 3 Low-Side N-Channel

MOSFETs (NMOS)

– 4.5 to 60-V Operating Voltage Range

– Supports 100% PWM Duty Cycle with Trickle

Charge pump

Bootstrap based Gate Driver Architecture

– 1000-mA Maximum Peak Source Current

– 2000-mA Maximum Peak Sink Current

Integrated Current Sense Amplifier with low input

offset (optimized for 1 shunt)

– Adjustable Gain (5, 10, 20, 40 V/V)

Hardware interface provides simple configuration

Ultra-low power sleep mode <1 uA at 25 C̊

4-ns (typ) propagation delay matching between

phases

Independent driver shutdown path (DRVOFF)

65-V tolerant wake pin (nSLEEP)

Supports negative transients upto -10V on SHx

6x and 3x PWM Modes

The DRV8329 family of devices is an integrated

gate driver for three-phase applications. The devices

provide three half-bridge gate drivers, each capable

of driving high-side and low-side N-channel power

MOSFETs. The device generates the correct gate

drive voltages using an internal charge pump and

enhances the high-side MOSFETs using a bootstrap

circuit. A trickle charge pump is included to support

100% duty cycle. The Gate Drive architecture

supports peak gate drive currents up to 1-A source

and 2-A sink. The DRV8329 can operate from a single

power supply and supports a wide input supply range

of 4.5 to 60 V.

•

The 6x and 3x PWM modes allow for simple

interfacing to controller circuits. The device has

integrated accurate 3.3-V LDO that can be used

to power external controller and can be used as

reference for CSA. The configuration settings for the

device are configurable through hardware (H/W) pins.

•

The DRV8329 devices integrate low-side current

sense amplifier that allow current sensing for sum of

current from all three phases of the drive stage.

Supports 3.3-V, and 5-V Logic Inputs

Accurate LDO (AVDD), 3.3 V ±3%, 80 mA

Compact QFN Packages and Footprints

Adjustable VDS overcurrent threshold through

VDSLVL pin

Adjustable deadtime through DT pin

Efficient System Design With Power Blocks

Integrated Protection Features

A low-power sleep mode is provided to achieve

low quiescent current by shutting down most of

the internal circuitry. Internal protection functions

are provided for undervoltage lockout, GVDD fault,

MOSFET overcurrent, MOSFET short circuit, and

overtemperature. Fault conditions are indicated on

nFAULT pin.

•

– PVDD Undervoltage Lockout (PVDDUV)

– GVDD Undervoltage (GVDDUV)

– Bootstrap Undervoltage (BST_UV)

– Overcurrent Protection (VDS_OCP, SEN_OCP)

– Thermal Shutdown (OTSD)

Device Information⁽¹⁾

PART NUMBER

DRV8329AREE

PACKAGE

VQFN (36)

BODY SIZE (NOM)

5.00 mm × 4.00 mm

– Fault Condition Indicator (nFAULT)

DRV8329BREE⁽²⁾

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) Device available for preview only

•

Brushless-DC (BLDC) Motor Modules and PMSM

Cordless Garden and Power Tools, Lawnmowers

Appliances Fans and Pumps

Servo Drives

E-Bikes, E-Scooters, and E-Mobility

Cordless Vacuum Cleaners

4.5 to 60 V

DRV8329

PWM (6x/3x)

Gate

Drive

Drones

nSLEEP

3 ½-H Bridge

Gate Driver

M

Industrial & Logistics Robots, and RC Toys

HW

Current

Sense

nFAULT

SO

1x Current Sense

Built In Protection

DRV8329 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8329

www.ti.com

SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specification.................................................................... 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings Comm....................................................6

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information 1pkg...........................................7

7.5 Electrical Characteristics.............................................8

7.6 Typical Characteristics..............................................15

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................18

8.4 Device Functional Modes..........................................28

9 Application and Implementation..................................29

9.1 Application Information............................................. 29

9.2 Typical Application.................................................... 29

10 Power Supply Recommendations..............................44

10.1 Bulk Capacitance Sizing......................................... 44

11 Layout...........................................................................45

11.1 Layout Guidelines................................................... 45

11.2 Layout Example...................................................... 47

11.3 Thermal Considerations..........................................48

12 Device and Documentation Support..........................49

12.1 Device Support....................................................... 49

12.2 Documentation Support.......................................... 49

12.3 Related Links.......................................................... 49

12.4 Receiving Notification of Documentation Updates..49

12.5 Community Resources............................................49

12.6 Trademarks.............................................................49

13 Mechanical, Packaging, and Orderable

Information.................................................................... 49

13.1 Tape and Reel Information......................................53

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (June 2022) to Revision A (October 2022)

Page

•

Updated device status to Production Data......................................................................................................... 1

2

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5 Device Comparison Table

Table 5-1. Different Device Variants

DEVICE

DEVICE VARIANT

DRV8329A

Package

LDO output

DT pin and VDSLVL

PWM_MODE

6x

3x

36-pin QFN

(5.00 mm x 4.00 mm)

DRV8329

3.3 V

Available

DRV8329B

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6 Pin Configuration and Functions

36 35 34 33 32 31 30 29

CSAREF

SO

1

2

3

4

5

6

7

8

9

10

28

27 INHC

INHB

DT

AVDD

26

25

24

GND

PVDD

CPL

AGND

DRVOFF

23 SN

CPH

SP

22

21

20

GVDD

BSTA

LSS

GLC

Thermal pad

SHA

19 GHC

11 12 13 14 15 16 17 18

Figure 6-1. DRV8329 REE Package 36-pin VQFN With Exposed Thermal Pad Top View

Table 6-1. Pin Functions—36-Pin DRV8329 Devices

PIN NO.

NAME

AGND

TYPE

DESCRIPTION

DRV8329

25

PWR Device analog ground. Refer Layout Guidelines for the recommendation on connection.

3.3-V regulator output. Connect a X5R or X7R, 1-µF, >6.3-V ceramic capacitor between the AVDD and

PWR-O GND pins. This regulator can source up to 80 mA externally. TI recommends a capacitor voltage rating

at least twice the normal operating voltage of the pin.

AVDD

26

BSTA

BSTB

BSTC

9

O

Bootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTA and SHA

Bootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTB and SHB

Bootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTC and SHC

13

17

Gain settings for Current sense amplifier. The pin is a 4 level input pin set by an external resistor. See

Low-Side Current Sense Amplifiers for more information.

CSAGAIN

CSAREF

33

1

I

Current sense amplifier reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between

the CSAREF and AGND pins.

CPH

CPL

7

6

PWR Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the

CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating

PWR

voltage of the pin.

Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the

gate drivers into the pull-down state. This signal bypasses and overrides the digital core of DRV8329.

DRVOFF

DT

24

3

I

Gate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ between DT and

GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating or connected to GND fixed

value of 55 ns deadtime is inserted.

I

GHA

GHB

GHC

GLA

GLB

11

15

19

12

16

O

High-side gate driver output. Connect to the gate of the high-side power MOSFET.

Low-side gate driver output. Connect to the gate of the low-side power MOSFET.

4

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Table 6-1. Pin Functions—36-Pin DRV8329 Devices (continued)

PIN NO.

DRV8329

20

NAME

TYPE

DESCRIPTION

GLC

O

Low-side gate driver output. Connect to the gate of the low-side power MOSFET.

Gate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF local

GVDD

8

PWR-O capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x C_BSTx

and voltage rating at least twice the normal operating voltage of the pin.

GND

INHA

INHB

INHC

INLA

INLB

INLC

4

PWR Device ground. Refer Layout Guidelines for the recommendation on connection.

29

28

27

32

31

30

I

High-side gate driver control input for Phase A. This pin controls the output of the high-side FET.

High-side gate driver control input for Phase B. This pin controls the output of the high-side FET.

High-side gate driver control input for Phase C. This pin controls the output of the high-side FET.

Low-side gate driver control input for Phase A. This pin controls the output of the low-side FET.

Low-side gate driver control input for Phase B. This pin controls the output of the low-side FET.

Low-side gate driver control input for Phase C. This pin controls the output of the low-side FET.

Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink

LSS

21

PWR path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage

and VSEN_OCP voltage.

Fault indicator output. This pin is pulled logic low during a fault condition and requires an external

pull-up resistor to 3.3V to 5.0V.

nFAULT

nSLEEP

35

34

OD

Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An

1 to 1.2-µs low pulse can be used to reset fault conditions without entering sleep mode.

I

Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-

PWR µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the PVDD and GND pins. TI

recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.

PVDD

5

High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the

VDS monitor and the output for the high-side gate driver sink.

SHA

SHB

SHC

SO

10

14

18

2

I/O

High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the

VDS monitor and the output for the high-side gate driver sink.

I/O

High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the

VDS monitor and the output for the high-side gate driver sink.

I/O

Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and

capacitor to GND)

O

Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the

current shunt resistor.

SP

22

23

36

I

SN

I

Current sense amplifier input. Connect to the low-side of the current shunt resistor.

VDS monitor trip point setting. Connect an analog level input from 0.1 V to 2.5 V to set a VDS monitor

trip point setting for MOSFET overcurrent protection. See VDSLVL Selection for more information.

VDSLVL

Thermal Pad

PWR Must be connected to GND

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

7 Specification

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

MAX UNIT

Power supply pin voltage

Bootstrap pin voltage

PVDD

65

80

V

BSTx

Bootstrap pin voltage

BSTx with respect to SHx

BSTx with respect to GHx

CPL, CPH

20

Bootstrap pin voltage

20

Charge pump pin voltage

Gate driver regulator pin voltage

Analog regulator pin voltage

Logic pin voltage (nSLEEP)

V_GVDD

20

GVDD

AVDD

4

nSLEEP

65

DRVOFF, DT, INHx, INLx, nFAULT,

VDSLVL

Logic pin voltage

-0.3

6

V

High-side gate drive pin voltage

GHx

-8

-10

-0.3

-8

80

20

70

72

20

0.3

1

V

Transient 500-ns high-side gate drive pin voltage

High-side gate drive pin voltage

GHx

GHx with respect to SHx

High-side source pin voltage

SHx

Transient 500-ns high-side source pin voltage

SHx

-10

-0.3

-1

Low-side gate drive pin voltage

GLx with respect to LSS

GLx with respect to GVDD

LSS

Transient 500-ns low-side gate drive pin voltage⁽²⁾

Low-side gate drive pin voltage

Transient 500-ns low-side gate drive pin voltage

Low-side source sense pin voltage

-1

1

Transient 500-ns low-side source sense pin voltage

LSS

-10

8

Internally

Limited

Internally

Limited

Gate drive current

GHx, GLx

A

Current sense amplifer reference input pin voltage

Shunt amplifier input pin voltage

CSAREF

SN, SP

SO

-0.3

-1

5.5

1

V

Transient 500-ns shunt amplifier input pin voltage

Shunt amplifier output pin voltage

Junction temperature, T_J

-10

8

V

-0.3 V_CSAREF+ 0.3

V

–40

–65

150

°C

Storage temperature, T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

(2) Supports upto 5A for 500 nS when GLx-LSS is negative

7.2 ESD Ratings Comm

VALUE

±2000

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6

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7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_PVDD

Power supply voltage

PVDD

4.5

60

30

V

Power supply voltage ramp rate at power

up

V_{PVDD_RAMP}

V/us

Power supply voltage ramp rate during

operation

V_{PVDD_RAMP}

PVDD

4

V/us

Bootstrap pin voltage with respect to

SHx

V_BST

nSLEEP = High, INHx is switching

4

20

80

2

V

(1)

I_AVDD

Regulator external load current

AVDD

BSTx

mA

µA

Trickle charge pump external load

current

I_TRICKLE

V_IN

Logic input voltage

DRVOFF, INHx, INLx, nSLEEP

DT, VDSLVL

0

5.5

3.4

200

5.5

-10

V

V_IN

Logic input voltage

f_PWM

V_OD

I_OD

PWM frequency

INHx, INLx

kHz

V

Open drain pullup voltage

Open drain output current

nFAULT

mA

Total average gate-drive current (Low

Side and High Side Combined)

(1)

I_GS

I_GHx, I_GLx

30

mA

V

Current sense amplifier reference

voltage

V_CSAREF

CSAREF

SO

2.8

5.5

I_SO

Shunt amplifier output current

Slew Rate on SHx pins

5

4

mA

V/ns

µF

V_SHSL

C_BSTx

C_GVDD

T_A

Capacitor between BSTx and SHx

Capacitor between GVDD and GND

Operating ambient temperature

Operating junction temperature

4.7 ⁽²⁾

130

125

150

µF

–40

°C

T_J

°C

(1) Power dissipation and thermal limits must be observed

(2) Current flowing through boot diode (DBOOT) needs to be limited for C_BSTx> 4.7µF.

7.4 Thermal Information 1pkg

DRV8329

THERMAL METRIC⁽¹⁾

REE (WQFN)

36

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

37.3

°C/W

R_θJC(top)

R_θJB

25.2

15.8

0.4

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

15.8

4.5

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES (AVDD, PVDD, GVDD)

V_PVDD=24V, nSLEEP = 0, T_A= 25°C

nSLEEP = LOW

1

2

µA

I_PVDDQ

PVDD sleep mode current

PVDD standby mode current

V_PVDD= 24 V; nSLEEP = HIGH, INHx =

INLX = LOW, DRVOFF = HIGH

2

3

4

mA

I_PVDDS

nSLEEP = HIGH, INHx = INLX = LOW,

DRVOFF = HIGH

5.5

V_PVDD= 24 V, nSLEEP = HIGH, INHx

= INLX = Switching@20kHz, No FETs

connected

4

7

mA

nSLEEP = HIGH, INHx = INLX =

Switching@20kHz, No FETs connected

5

10

7

mA

µA

I_PVDD

PVDD active mode current

V_PVDD= 8 V, nSLEEP = HIGH, INHx =

INLX = LOW, No FETs connected

V_PVDD= 24 V, nSLEEP = HIGH, INHx =

INLX = LOW, No FETs connected

5

V_BSTx= V_SHx= 60V, V_GVDD= 0V,

nSLEEP = LOW

IL_BSx

Bootstrap pin leakage current

5

10

115

16

300

Bootstrap pin active mode transient

leakage current

INLx = INHx = Switching@20kHz, No

FETs connected

IL_{BS_TRAN}

60

µA

INHx = HIGH, INLx = LOW, INLy

= INLz = HIGH, nSLEEP = HIGH,

V_PVDD= V_SHX= V_GVDD= 12V, V_BSTx

V_SHx= 5V

135

70

200

105

280

145

µA

-

INHx = HIGH, INLx = LOW, INLy

= INLz = HIGH, nSLEEP = HIGH,

V_PVDD= V_SHX= V_GVDD= 12V, V_BSTx

V_SHx= 7V

Bootstrap pin active mode leakage static

source current

IL_{BS_DC_SRC}

INHx = LOW, INLx = LOW, INLy = INLz =

HIGH, nSLEEP = HIGH, V_PVDD= V_SHX

V_GVDD= 12V, V_BSTx- V_SHx= 5V

=

25

16

10

14

80

15

80

13

50

28

90

50

µA

INHx = LOW, INLx = LOW, INLy = INLz =

HIGH, nSLEEP = HIGH, V_PVDD= V_SHX

V_GVDD= 12V, V_BSTx- V_SHx= 7V

=

INHx = LOW, INLx = LOW, INLy = INLz =

HIGH, nSLEEP = HIGH, V_PVDD= V_SHX

V_GVDD= 12V, V_BSTx- V_SHx= 12V

=

40

90

Bootstrap pin active mode leakage static

sink current

IL_{BS_DC_SINK}

INHx = High, INLx = LOW, INLy = INLz =

HIGH, nSLEEP = HIGH, V_PVDD= V_SHX

V_GVDD= 12V, V_BSTx- V_SHx= 12V

=

45

91

INHx = INLx = LOW, V_BSTx- V_SHx

= 15, V_SHx= 0 to 60V, nSLEEP =

HIGH, DRVOFF = LOW

145

20

210

30

INHx = INLx = LOW, V_BSTx- V_SHx

= 11, V_SHx= 0 to 60V, nSLEEP =

HIGH, DRVOFF = LOW

IL_SHx

Source pin leakage current

INHx = High, INLx = LOW, V_BSTx

-

V_SHx= 15, V_SHx= 0 to 60V, nSLEEP =

HIGH, DRVOFF = LOW

145

25

210

35

INHx = HIGH, INLx = LOW, V_BSTx

-

V_SHx= 11, V_SHx= 0 to 60V, nSLEEP =

HIGH, DRVOFF = LOW

8

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4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

nSLEEP = HIGH to Active

mode (Outputs Ready), DRVOFF =

LOW, C_GVDD= 10 uF, C_BSTx= 1 uF

1

2

ms

nSLEEP = High to Active mode (Outputs

Ready). C_GVDD= 100 uF, C_AVDD= 10

uF, C_BSTx= 10 uF

Turnon time (nSLEEP)

10

15

t_WAKE

V_PVDD= 12V, nSLEEP = HIGH to

Active mode (Outputs Ready), DRVOFF

= LOW, C_GVDD= 10 uF

1

2

ms

DRVOFF = LOW to Active mode

(Outputs Ready), nSLEEP = High

Turnon time (DRVOFF)

0.05

0.1

t_SLEEP

t_RST

Turnoff time

nSLEEP = LOW to Sleep mode

20

1.2

15

us

V

Minimum Reset Pulse Time

nSLEEP = LOW period to reset faults

V_PVDD≥ 40 V, I_GS= 10 mA, T_J= 25°C

1

11.8

13

22 V ≤V_PVDD≤ 40 V, I_GS= 30 mA, T_J=

25°C

11.8

15

V

8 V ≤V_PVDD≤ 22 V, I_GS= 30 mA, T_J=

25°C

GVDD Gate driver regulator voltage

(Room Temperature)

13

V_{GVDD_RT}

6.75 V ≤V_PVDD≤ 8 V, I_GS= 10 mA, T_J=

25°C

14.5

13.5

4.5 V ≤V_PVDD≤ 6.75 V, I_GS= 10 mA, T_J= 2*V_PVDD

25°C

- 1

11.5

V_PVDD≥ 40 V, I_GS= 10 mA

22 V ≤V_PVDD≤ 40 V, I_GS= 30 mA

8 V ≤V_PVDD≤ 22 V; I_GS= 30 mA

6.75 V ≤V_PVDD≤ 8 V, I_GS= 10 mA

15.5

14.5

V

V_GVDD

GVDD Gate driver regulator voltage

2*V_PVDD

- 1.4

4.5 V ≤V_PVDD≤ 6.75 V, I_GS= 10 mA

13.5

3.33

3.4

V

V_PVDD≥ 6 V, 0 mA ≤ I_AVDD≤ 30 mA, T_J=

25°C

3.26

3.2

3.3

AVDD Analog regulator voltage (Room

Temperature)

V_PVDD≥ 6 V, 30 mA ≤ I_AVDD≤ 80 mA, T_J=

25°C

V_{AVDD_RT}

V_PVDD≤ 6 V, 0 mA ≤ I_AVDD≤ 50 mA, T_J=

25°C

3.13

3.46

V_PVDD≥ 6 V, 0 mA ≤ I_AVDD≤ 80 mA

V_PVDD≤ 6 V, 0 mA ≤ I_AVDD≤ 50 mA

3.2

3.3

3.4

3.5

V

V_AVDD

AVDD Analog regulator voltage

3.125

LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP etc)

DRVOFF

0.8

V

V_IL

V_IH

Input logic low voltage

Input logic high voltage

INLx, INHx pins

DRVOFF

2.2

200

45

-1

V

INLx, INHx pins

V

DRVOFF

400

240

0

650

350

1

mV

µA

kΩ

V_HYS

I_IL

Input hysteresis

INLx, INHx pins

Input logic low current

V_PIN(Pin Voltage) = 0 V;

nSLEEP, V_PIN(Pin Voltage) = 65 V;

nSLEEP, V_PIN(Pin Voltage) = 5 V;

Other pins, V_PIN(Pin Voltage) = 5 V;

DRVOFF To GND

3

6.5

6

10

I_IH

Input logic high current

3

10

7

20

35

R_{PD_DRVOFF}Input pulldown resistance

R_{PD_nSLEEP}Input pulldown resistance

100

500

150

200

800

250

300

1500

350

nSLEEP To GND

R_PD

Input pulldown resistance

All other pins To GND

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FOUR-LEVEL INPUTS (GAIN)

0.18*AV

DD

V_L1

V_L2

V_L3

Input level 1 voltage

Input level 2 voltage

Input level 3 voltage

Tied to GND

0

V

0.48*AV 0.5*AVD 0.52*AV

DD DD

50 kΩ +/- 5% tied to GND

200 kΩ +/- 5% tied to GND

D

0.82*AV 0.833*AV 0.85*AV

DD

AVDD

100

DD

V_L4

Input level 4 voltage

HiZ or Connect to AVDD

GAIN To AVDD

V

R_PU

Input pullup resistance

80

120

kΩ

OPEN-DRAIN OUTPUTS (nFAULT etc)

V_OL

I_OZ

Output logic low voltage

Output logic high current

Output capacitance

I_OD= 5 mA

V_OD= 5 V

0.4

1

V

-1

µA

pF

C_OD

30

GATE DRIVERS (GHx, GLx, SHx, SLx)

I_GLx= -100 mA; V_GVDD= 12V; No FETs

connected

V_{GSHx_LO}

V_{GSHx_HI}

V_{GSLx_LO}

V_{GSLx_HI}

High-side gate drive low level voltage

0.05

0.28

0.05

0.28

8.4

0.11

0.44

0.11

0.44

9.6

0.24

0.82

0.27

0.82

11.1

9

V

Ω

High-side gate drive high level voltage

(V_BSTx- V_GHx

I_GHx= 100 mA; V_GVDD= 12V; No FETs

connected

)

I_GLx= -100 mA; V_GVDD= 12V; No FETs

connected

Low-side gate drive low level voltage

Low-side gate drive high level voltage

I_GHx= 100 mA; V_GVDD= 12V; No FETs

connected

(V_GVDD- V_GHx

)

INHx = HIGH, INLx = LOW, INLy = INLz

= HIGH, V_PVDD>15V, V_GVDD≥11.5V

High-side gate drive voltage in steady

INHx = HIGH, INLx = LOW, INLy = INLz

state with 100 % duty cycle (GHx- SHx) = HIGH, V_GVDD≥11.5V

V_{GSH_100_PH}

7.5

8.3

INHx = HIGH, INLx = LOW, INLy = INLz

= HIGH, 7V ≥V_GVDD≥ 8V

5.7

6.5

7.6

R_{DS(ON)_PU_}

High-side pullup switch resistance

High-side pulldown switch resistance

Low-side pullup switch resistance

Low-side pulldown switch resistance

I_GHx= 100 mA; V_GVDD= 12V

2.7

4.5

8.4

HS

R_{DS(ON)_PD_}

I_GHx= 100 mA; V_GVDD= 12V

I_GLx= 100 mA; V_GVDD= 12V

0.5

1.1

2.4

HS

R_{DS(ON)_PU_}

2.7

4.5

8.3

LS

R_{DS(ON)_PD_}

0.5

1.1

2.8

LS

I_{DRIVEP_HS}

I_{DRIVEN_HS}

I_{DRIVEP_LS}

I_{DRIVEN_LS}

R_{PD_LS}

High-side peak source gate current

High-side peak sink gate current

Low-side peak source gate current

Low-side peak sink gate current

Low-side passive pull down

V_GSHx= 12V

550

1150

550

1150

80

1000

2000

1000

2000

100

1575

2675

1575

2675

120

mA

kΩ

V_GSHx= 0V

V_GSLx= 12V

V_GSLx= 0V

GLx to LSS

R_{PDSA_HS}

High-side semiactive pull down

GHx to SHx, V_GSHx= 2V

8

10

12.5

kΩ

GATE DRIVERS TIMINGS

t_{PDR_LS}Low-side rising propagation delay

t_{PDF_LS}

INLx to GLx rising, V_GVDD> 8V

INLx to GLx falling, V_GVDD> 8V

70

100

145

135

ns

Low-side falling propagation delay

High-side rising propagation delay

INHx to GHx rising, V_GVDD= V_BSTx

V_SHx> 8V

-

t_{PDR_HS}

t_{PDF_HS}

65

70

100

145

140

ns

INHx to GHx falling, V_GVDD= V_BSTx

V_SHx> 8V

High-side falling propagation delay

10

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

GLx turning ON to GLx turning OFF,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

-25

±4

25

28

25

10

15

10

45

ns

GLx turning OFF to GHx turning ON,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

-28

-25

-10

-15

-10

18

±4

32

t_{PD_MATCH_P}

Matching propagation delay per phase

H

GHx turning ON to GHx turning OFF,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

GHx turning OFF to GLx turning ON,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

GHx turning ON to GHy turning ON,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

GLx turning ON to GLy turning ON,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

t_{PD_MATCH_P}Matching propagation delay phase to

phase

H_PH

GHx turning OFF to GHy turning OFF,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V to

60V, No load on GHx and GLx

GLx turning OFF to GLy turning OFF,

V_GVDD= V_BSTx- V_SHx> 8V; SHx = 0V

to 60V, No load on GHx and GLx

Minimum input pulse width on INHx,

t_{PW_MIN}

t_DEAD

INLx that changes the output on GHx,

GLx

Gate drive dead time configurable range

Gate drive dead time

50

35

2000

90

ns

DT pin floating

55

DT pin connected to GND

10 kΩ between DT pin and GND

390 kΩ between DT pin and GND

25

80

t_DEAD

75

100

2000

140

2650

1350

BOOTSTRAP DIODES

V_BOOTDBootstrap diode forward voltage

I_BOOT= 100 µA

I_BOOT= 100 mA

0.8

1.6

V

Bootstrap dynamic resistance

(ΔV_BOOTD/ΔI_BOOT

R_BOOTD

I_BOOT= 100 mA and 50 mA

4.5

5.5

9

Ω

)

CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, CSAREF)

CSAGAIN = Tied to GND

4.92

9.9

5

10

20

40

5.05

10.1

20.2

40.6

1.5

V/V

%

CSAGAIN = 50kΩ ±5% tied to GND

CSAGAIN = 200kΩ ±5% tied to GND

CSAGAIN =Hi-Z;

A_CSA

Sense amplifier gain

19.75

39.6

-1.5

A_{CSA_ERR}

Sense amplifier gain error

T_J= 25℃

A_{CSA_ERR_D}Sense amplifier gain error temperature

-20

20 ppm/℃

0.05

drift

RIFT

NL

Non linearity Error

0.01

%

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_STEP= 1.6 V, A_CSA= 5 V/V, C_LOAD

500pF

=

0.6

1

1.1

1.2

1.7

0.5

0.65

0.8

7

µs

V_STEP= 1.6 V, A_CSA= 10 V/V, C_LOAD

500pF

=

0.6

0.7

0.8

0.3

5

t_SET

BW

t_SR

Settling time to ±1%

V_STEP= 1.6 V, A_CSA= 20 V/V, C_LOAD

500pF

µs

V_STEP= 1.6 V, A_CSA= 40 V/V, C_LOAD

500pF

µs

V_STEP= 1.6 V, A_CSA= 5 V/V, C_LOAD

60pF

=

µs

V_STEP= 1.6 V, A_CSA= 10 V/V, C_LOAD

60pF

=

µs

Settling time to ±1%

V_STEP= 1.6 V, A_CSA= 20 V/V, C_LOAD

60pF

µs

V_STEP= 1.6 V, A_CSA= 40 V/V, C_LOAD

60pF

µs

A_CSA= 5 V/V, C_LOAD= 60-pF, small

signal -3 dB

3

2.5

2

MHz

V/µs

A_CSA= 10 V/V, C_LOAD= 60-pF, small

signal -3 dB

4.8

4

6.6

5.4

4.2

Bandwidth

A_CSA= 20 V/V, C_LOAD= 60-pF, small

signal -3 dB

A_CSA= 40 V/V, C_LOAD= 60-pF, small

signal -3 dB

1.75

3

V_STEP= 1.6 V, A_CSA= 5 V/V, C_LOAD

60-pF, low to high transition

=

12

13

11

V_STEP= 1.6 V, A_CSA= 10 V/V, C_LOAD

60-pF, low to high transition

=

Output slew rate

V_STEP= 1.6 V, A_CSA= 20 V/V, C_LOAD

60-pF, low to high transition

V_STEP= 1.6 V, A_CSA= 40 V/V, C_LOAD

60-pF, low to high transition

V_SWING

Output voltage range

V_CSAREF= 3

0.25

2.75

5.25

V

V_CSAREF= 5.5

V_CSAREF

- 0.25

V_SWING

Output voltage range

V_CSAREF= 3 to 5.5 V

0.25

V

V_COM

V_DIFF

Common-mode input range

Differential-mode input range

-0.15

-0.3

0.15

0.3

V

V_SP= V_SN= GND; T_J= -40℃,

V_OFF

Input offset voltage

-1.5

-1.2

1.5

1.2

mV

CSA_VREF = 0

V_SP= V_SN= GND; T_J= 25℃,

CSA_VREF = 0

V_SP= V_SN= GND; T_J= 175℃,

CSA_VREF= 0

Input offset voltage

-1.5

1.5

mV

V_SP= V_SN= GND

V_{OFF_DRIFT}Input drift offset voltage

8

10 µV/℃

V_BIAS

Output voltage bias ratio

0.122

-1.2

0.125

0.128

V

V_{BIAS_ACC}

Output voltage bias ratio accuracy

1.2

%

V_SP= V_SN= GND, V_CSAREF= 3V to

5.5V

I_BIAS

Input bias current

100

µA

I_{BIAS_OFF}

I_CSASRC

Input bias current offset

I_SP– I_SN

-1

5

1

µA

SO ouput sink current capability

7

11

mA

12

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

3.7

80

MAX UNIT

I_CSASRC

CMRR

SO ouput source current capability

2

6.6

mA

dB

mA

us

DC

Common-mode rejection ratio

20 kHz

65

CSAREF to SOx, DC, Differential

80

PSRR

Power-supply rejection ratio (CSAREF)

CSAREF to SOx, 20 kHz, Differential

70

PSRR

Power-supply rejection ratio (CSAREF) CSAREF to SOx, 20 kHz, Single Ended

40

I_{CSA_SUP}

T_CMREC

C_LOAD

Supply current for CSA

V_CSAREF= 3.V to 5.5V

1.5

0.6

10

2.1

0.7

Common mode recovery time

Maximum load capacitance

nF

A_CSA= 5 V/V

A_CSA= 10 V/V

A_CSA= 20 V/V

A_CSA= 40 V/V

-3

-4

-5

-6

3

4

5

6

mV

V_{OFF_OUT}

Output offset error

PROTECTION CIRCUITS

V_PVDDrising

V_PVDDfalling

4.3

4

4.4

4.1

4.5

V_{PVDD_UV}

PVDD undervoltage lockout threshold

V

4.25

V_{PVDD_UV_H}

PVDD undervoltagelockout hysteresis

Rising to falling threshold

225

265

325

mV

µs

YS

t_{PVDD_UV_DG}PVDD undervoltage deglitch time

V_{AVDD_POR}AVDD supply POR threshold

10

2.7

2.5

20

2.85

2.65

30

3.0

2.8

AVDD rising

AVDD falling

V

V_{AVDD_POR_}

AVDD POR hysteresis

Rising to falling threshold

170

7

200

12

250

22

mV

µs

HYS

t_{AVDD_POR_D}

AVDD POR deglitch time

G

V_GVDDrising

V_GVDDfalling

7.3

6.4

7.5

6.7

7.8

6.9

V

V_{GVDD_UV}

GVDD undervoltage threshold

GVDD undervoltage hysteresis

V_{GVDD_UV_H}

Rising to falling threshold

800

900

1000

mV

YS

t_{GVDD_UV_DG}GVDD undervoltage deglitch time

V_{BST_UV}Bootstrap undervoltage threshold

5

3.9

3.7

150

2

10

4.45

4.2

220

4

15

5

µs

V

V_BSTx- V_SHx; V_BSTxrising

V_BSTx- V_SHx; V_BSTxfalling

Rising to falling threshold

4.8

285

6

V

V_{BST_UV_HYS}Bootstrap undervoltage hysteresis

t_{BST_UV_DG}Bootstrap undervoltage deglitch time

mV

µs

V_DSovercurrent protection threshold

V_{DS_LVL_RNG}

linear range

0.1

70

2.5

V

V_DSovercurrent protection disable

V_{DS_DIS}

resistor

VDSLVL pin to GVDD

100

500

kΩ

V

VDSLVL = 100 kΩ to GVDD

VDSLVL = 0.1V

3

0.065

2.2

4.2

0.1

2.5

0.5

1

5.5

0.145

2.8

V_DSovercurrent protection threshold

Reference

V_{DS_LVL}

V

VDSLVL pin = 2.5V

V_{SENSE_LVL}V_SENSEovercurrent protection threshold LSS to GND pin = 0.5V

0.48

0.5

0.52

2.7

V

t_{DS_BLK}

t_{DS_DG}

V_DSovercurrent protection blanking time

µs

V_DSand V_SENSEovercurrent protection

deglitch time

1.5

3

5

µs

t_{SD_SINK_DIG}DRVOFF peak sink current duration

3

0.5

7

5

1.5

14

7

2.2

21

µs

t_{SD_DIG}

t_SD

DRVOFF digital shutdown delay

DRVOFF analog shutdown delay

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

4.5 V ≤ V_PVDD≤ 60 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted). Typical limits apply for T_A= 25°C, V_PVDD= 24 V

PARAMETER

TEST CONDITIONS

MIN

160

16

TYP

170

20

MAX UNIT

T_OTSD

T_HYS

Thermal shutdown temperature

Thermal shutdown hysteresis

T_Jrising;

187

23

°C

14

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7.6 Typical Characteristics

8.5

8.25

8

7.75

7.5

7.25

7

6.75

6.5

6.25

6

5.75

5.5

5.25

5

14

13.5

13

-40 C

25 C

150 C

12.5

12

11.5

11

10.5

10

9.5

9

-40 C

25 C

150 C

8.5

8

0

5

10 15 20 25 30 35 40 45 50 55 60

PVDD Voltage (V)

0

5

10 15 20 25 30 35 40 45 50 55 60

PVDD Voltage (V)

Figure 7-1. Supply Current over PVDD Voltage

Figure 7-2. GVDD Voltage over PVDD Voltage

3.34

2500

-40 C

High Side Source

High Side Sink

Low Side Source

Low Side Sink

3.33

3.32

3.31

3.3

25 C

2250

150 C

2000

1750

1500

1250

1000

750

3.29

3.28

3.27

3.26

3.25

0

8

16

24

32

40

48

56

64

72

80

-40 -20

0

20

40

60

80 100 120 140

Junction Temperature (C)

Load Current (mA)

Figure 7-3. AVDD Voltage over Load Current

Figure 7-4. Driver Peak Current over Junction

Temperature

9

8.75

8.5

8.25

8

7.75

7.5

7.25

7

0.65

0.625

0.6

0.575

0.55

0.525

0.5

6.75

6.5

6.25

6

5.75

5.5

0.475

0.45

0.425

0.4

-40 -20

0

20

40

60

80 100 120 140

-40 -20

0

20

40

60

80 100 120 140

Junction Temperature (C)

Junction Temperature ()

Figure 7-6. Bootstrap Diode Forward Voltage Drop

over Junction Temperature

Figure 7-5. Bootstrap Diode Resistance over

Junction Temperature

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8 Detailed Description

8.1 Overview

The DRV8329 family of devices is an integrated three-phase gate driver supporting an input voltage range of

4.5-V to 60-V. These devices decrease system component count, cost, and complexity by integrating three

independent half-bridge gate drivers, trickle charge pump, and a charge pump with linear regulator for the supply

voltages of the high-side and low-side gate drivers. DRV8329 also integrates an accurate low voltage regulator

(AVDD) capable of supporting 3.3 V at 80 mA output. A hardware interface allows for simple configuration of the

motor driver and control of the motor.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A

source, 2-A sink peak gate drive currents with a 30-mA average output current. A bootstrap circuit with capacitor

generates the supply voltage of the high-side gate drive and a trickle charge pump is employed to support 100%

duty cycle. The supply voltage of the low-side gate driver is generated using a charge pump with linear regulator

GVDD from the PVDD power supply that regulates to 12 V.

In addition to the high level of device integration, the DRV8329 family of devices provides a wide range of

integrated protection features. These features include power supply undervoltage lockout (PVDDUV), regulator

undervoltage lockout (GVDDUV), Bootstrap Voltage undervoltage lockout (BSTUV), V_DSovercurrent monitoring

(OCP), Sense resistor overcurrent monitoring (SEN_OCP) and overtemperature shutdown (TSD). Fault events

are indicated by the nFAULT pin.

The DRV8329 is available in 0.4-mm pitch, 5 × 4 mm 36-pin QFN surface-mount packages.

16

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8.2 Functional Block Diagram

PVDD

+

0.1 μF

C_PVDD1

bulk

C_PVDD2

Power

GVDD

PVDD

C_GVDD

GVDD

HS

Trickle

CP

10 μF

BSTA

C_BSTA

VCP

Charge

Pump

CPH

CPL

GHA

HS

C_CP

470 nF

SHA

GLA

GVDD

LS

80 mA

AVDD

AGND

3.3-V LDO

C_AVDD

LSS

1 μF

GVDD

HS

Trickle

CP

BSTB

GHB

SHB

PVDD

nSLEEP

INHA

C_BSTB

HS

INLA

INHB

INLB

GVDD

LS

GLB

LS

Digital

Control

LSS

Control

Inputs

GVDD

HS

Trickle

CP

+

-

PVDD

INHC

INLC

BSTC

GHC

SHC

C_BSTC

HS

GVDD

LS

DT

GLC

LS

AVDD

R_nFAULT

R_DT

LSS

DRVOFF

LSS

nFAULT

Outputs

LSS

0.5V

+

-

3x LS, 3x HS

VSENSE OCP

VDSLVL

-

+

VDS

SP

CSAGAIN

SO

CSAREF

SP

SN

-

V

_CSAREF/8

R_SENSE

+

-

+

-

+

CSAREF

SN

CSA

GND

Thermal Pad

Figure 8-1. Block Diagram of DRV8329

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8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the gate driver and the buck regulator.

Table 8-1. DRV8329 External Components

COMPONENTS

C_PVDD1

C_PVDD2

C_CP

PIN 1

PVDD

CPH

PIN 2

PGND

CPL

RECOMMENDED

X5R or X7R, 0.1-µF, >2x PVDD-rated capacitor

≥ 10 µF, >2x PVDD-rated capacitor

X5R or X7R, 470-nF, PVDD-rated capacitor

X5R or X7R, ≥10-uF, 25V-rated capacitor

X5R or X7R, ≥1-µF, 6.3-V capacitor

X5R or X7R, 1-µF (typical), 25V-rated capacitor

Pullup resistor (10 kΩ)

C_GVDD

GVDD

AVDD

BSTx

VCC⁽¹⁾

GND

C_AVDD

AGND

SHx

C_BSTx

R_nFAULT

nFAULT

Hardware interface resistor. Refer to Deadtime and

Cross-Conduction Prevention for the details.

R_DT

DT

AGND

(1) The VCC pin is not a pin on the DRV8329 , but a VCC supply voltage pullup is required for the open-drain output, nFAULT. This pin

can also be pulled up to AVDD.

8.3.1 Three BLDC Gate Drivers

The DRV8329 family of devices integrates three half-bridge gate drivers, each capable of driving high-side and

low-side N-channel power MOSFETs. A charge pump is used to generate the GVDD to supply the correct gate

bias voltage across a wide operating voltage range. The low side gate outputs are driven directly from GVDD,

while the high side gate outputs are driven using a bootstrap circuit with an integrated diode. An internal trickle

charge pump provides support for 100% duty cycle operation. The half-bridge gate drivers can be used in

combination to drive a three-phase motor or separately to drive other types of loads.

8.3.1.1 PWM Control Modes

8.3.1.1.1 6x PWM Mode

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The

corresponding INHx and INLx signals control the output state as listed in Table 8-2.

Table 8-2. 6x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

Hi-Z

H

0

1

0

1

0

1

L

H

L

H

L

Hi-Z

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8.3.1.1.2 3x PWM Mode

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx

pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.

The corresponding INHx and INLx signals control the output state as listed in Table 8-3.

Table 8-3. 3x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

Hi-Z

L

0

1

X

0

1

L

H

L

H

8.3.1.2 Device Hardware Interface

The DRV8329 utilize a hardware interface to configure different device settings. These hardware configurable

inputs are DT and VDSLVL. General fault information is reported on the nFAULT pin.

•

The DT pin configures the gate drive dead time. The dead time can adjusted by changing the resistor value

from the DT pin to GND.

The VDSLVL pin configures the voltage threshold of the V_DSovercurrent monitors. The voltage applied to the

VDSLVL pin is directly used as reference for the VDS comparator

For more information on the hardware interface, see Section 8.3.3.

VDSLVL

Hardware

Interface

DT

R_DT

Figure 8-2. Hardware Interface

8.3.1.3 Gate Drive Architecture

The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This

topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate drivers

are supplied directly from the GVDD regulator supply. The operating mode of GVDD depends on the voltage of

PVDD, when the PVDD >18V, the GVDD voltage is generated by an LDO, whereas PVDD < 18V, the GVDD

voltage is generated by a charge pump. For the high-side gate drivers a bootstrap diode and capacitor are

used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and an external

bootstrap capacitor is used between BSTx and SHx pins. To support 100% duty cycle control, a trickle charge

pump is integrated into the device. The trickle charge pump is connected to the BSTx node to prevent voltage

drop due to the leakage currents of the driver and external MOSFET.

The high-side gate driver has a semi-active pulldown and low side gate has passive pulldown to help prevent the

external MOSFET from turning ON during sleep state or when the power supply is disconnected.

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C_GVDD

GVDD

PVDD

Trickle

Charge

Pump

C_PVDD2

C_PVDD1

CPH

Charge

Pump

D_BSTx

VBAT

C_CP

BSTx

CPL

C_BSTx

GHx

INHx

Level

Shifters

SHx

GLx

INLx

Digital

Core

GVDD

Level

Shifters

LSS

GND

Figure 8-3. Gate Driver Block Diagram

8.3.1.3.1 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to a detected output

change. This time has two parts consisting of the digital propagation delay, and the delay through the analog

gate drivers.

To support multiple control modes and dead time insertion, a small digital delay is added as the input command

propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall

propagation delay of the device.

8.3.1.3.2 Deadtime and Cross-Conduction Prevention

In the DRV8329, high- and low-side inputs operate independently, with an exception to prevent cross conduction

when the high and low side of the same half-bridge are turned ON at same time. The device turns OFF high- and

low- side output to prevent shoot through when high- and low-side inputs are logic high at same time.

The DRV8329 also provides dead time insertion to prevent both external MOSFETs of each half-bridge from

switching on at the same time. In devices with a DT pin, deadtime can be linearly adjusted between 100 ns and

2000 ns by connecting s resistor between DT and ground. When the DT pin is left floating or connected to GND,

a fixed deadtime of 55 ns (typical value) is inserted. The value of the resistor can be calculated using following

equation.

Deadtime ns

R

kΩ

=

− 10 kΩ

(1)

DT

5

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INHx/INLx Inputs

INHx

INLx

GHx/GLx outputs

GHx

GLx

DT

Cross

Conduction

Prevention

Figure 8-4. Cross Conduction Prevention and Deadtime Insertion

8.3.2 AVDD Linear Voltage Regulator

A 3.3-V, 80-mA linear regulator is available for use by external circuitry. The output of the LDO is fixed to 3.3-V.

This regulator can provide the supply voltage for a low-power MCU or other circuitry with low supply current

needs. The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V

ceramic capacitor routed back to the AGND pin.

PVDD

REF

+

œ

AVDD

AGND

3.3-V, 80 mA

1 …F

Figure 8-5. AVDD Linear Regulator Block Diagram

The power dissipated in the device by the AVDD linear regulator can be calculated as follows: P = (V_PVDD

-

V_AVDD) x I_AVDD

For example, at a V_PVDDof 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in

Equation 2.

P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

(2)

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8.3.3 Pin Diagrams

Figure 8-6 shows the input structure for the logic level pins, INHx and INLx. The input can be driven with a

voltage or external resistor.

AVDD

STATE

V_IH

RESISTANCE

Tied to AVDD

Tied to AGND

INPUT

Logic High

Logic Low

V_IL

R_PD

Figure 8-6. Logic-Level Input Pin Structure

Figure 8-7 shows the structure of the four level input pins, MODE and CSAGAIN, on hardware interface devices.

The input can be set with an external resistor.

GAIN

AVDD

STATE

V_L1

RESISTANCE

Tied to AGND

5 V/V

10 V/V

20 V/V

40 V/V

+

–

R_PU

50k ±5% tied to

AGND

V_L2

V_L3

V_L4

+

–

R_PD

200k ±5% tied to

AGND

Hi-Z or connect to

AVDD

+

–

Figure 8-7. Four Level Input Pin Structure

Figure 8-8 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external

pullup resistor to function correctly.

AVDD

R

PU

STATE

No Fault

Fault

STATUS

Inactive

Active

OUTPUT

Active

Inactive

Figure 8-8. Open-Drain Output Pin Structure

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8.3.4 Low-Side Current Sense Amplifiers

The DRV8329 integrates a high-performance low-side current sense amplifier for current measurements using

a low-side shunt resistor. Low-side current measurements are commonly used to implement overcurrent

protection, external torque control, or brushless DC commutation with the external controller. The current

sense amplifier can be used to sense the sum of the half-bridge currents. The current sense amplifiers

includes features such as configurable gain (CSAGAIN), and a voltage reference pin (CSAREF). The DRV8329

generates internally a common voltage of V_CSAREF/8.

The gain setting is adjustable between four different levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Gain settings can

be configured through CSAGAIN pin.

Table 8-4. CSA Gain setting

CSAGAIN pin

Connect to GND

CSA Gain Setting

5 V/V

50 kΩ +/- 5% to GND

200 kΩ +/- 5% to GND

HiZ or Connect to AVDD

10 V/V

20 V/V

40 V/V

8.3.4.1 Current Sense Operation

DRV8329 internally generates a common mode voltage of V_CSAREF/8 to obtain maximum resolution for current

measurement. SO pin outputs an analog voltage equal to the voltage across the SP and SN pins multiplied by

the gain setting (CSAGAIN).

Use Equation 3 to calculate the current through the shunt resistor (R_SENSE).

V

CSAREF

8

V

−

SO

I =

(3)

CSAGAIN × R

SENSE

50 k

100 k

200 k

400 k

SN

SP

CSAREF

10 k

-

SO

+

CSAREF

50 k

100 k

200 k

400 k

-

V_CSAREF/8

+

GND

Figure 8-9. Current-Sense Configuration

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SO (V)

V

CSAREF

V

– 0.25V

CSAREF

V

LINEAR

V

/8

CSAREF

0.25 V

V_SP– V_SN

Figure 8-10. Current-Sense Output

I

SP

SO

R

A_V

SN

SO

V

CSAREF

– 0.25V

V_SP– V_SN

0.3 V

I × R_SENSE

V

CSAREF

V

SO(range+)

V

,

OFF

V

SO(off)max

V_CSAREF/8

DRIFT

0 V

V

SO(off)min

-I × R_SENSE

-0.3 V

V

SO(range-)

0.25 V

0 V

Figure 8-11. Current-Sense Regions

8.3.5 Gate Driver Shutdown Sequence (DRVOFF)

When DRVOFF is driven high, the gate driver goes into shutdown, overriding signals on inputs pins INHx and

INLx. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver

output (see Figure 8-12). This pin provides a mechanism for externally monitored faults to disable the gate driver

by directly bypassing an external controller or the internal control logic. When the DRV8329 detects that the

DRVOFF pin is driven high, it disables the gate driver and puts it into pulldown mode (see Figure 8-13). The

gate driver shutdown sequence proceeds as shown in Figure 8-13. When the gate driver initiates the shutdown

sequence, the active driver pulldown is applied at I_SINKcurrent for the t_{SD_SINK_DIG}time, after which the gate

driver moves to passive pulldown mode.

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PVDD

OFF

DRVOFF

GHA

GHB

GHC

OFF

A

B

Gate

Driver

Digital

OFF

C

GLA

GLB

GLC

OFF

GND

Figure 8-12. DRV8329 DRVOFF Gate Driver Output State

High

INHx (INLx)

GHx-SHx

(GLx-LSS)

t_{SD_DIG}

DRVOFF pin

t_{SD_SINK_DIG}

t_SD

Passive (R_{PD_LS}) and Semiactive

PullDown (R_{PDSA_HS}

Predriver

Current

I_SINK

I_SOURCE/I_SINK

)

Figure 8-13. Gate Driver Shutdown Seqeunce

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8.3.6 Gate Driver Protective Circuits

The DRV8329 are protected against PVDD undervoltage and overvoltage, AVDD power-on reset, bootstrap

undervoltage, GVDD undervoltage, MOSFET V_DSand V_SENSEovercurrent events.

Table 8-5. Fault Action and Response

FAULT

CONDITION

CONFIGURATION

REPORT

GATE DRIVER

LOGIC

RECOVERY

PVDD

undervoltage

(PVDD_UV)

Automatic:

V_PVDD> V_{PVDD_UV}

V_PVDD< V_{PVDD_UV}

-

nFAULT

Disabled¹

Disabled

AVDD POR

(AVDD_POR)

Automatic:

V_AVDD> V_{AVDD_POR}

V_AVDD< V_{AVDD_POR}

-

nFAULT

Disabled¹

Disabled

Active

GVDD

undervoltage

(GVDD_UV)

Latched:

nSLEEP Reset Pulse

V_GVDD< V_{GVDD_UV}

Pulled Low ²

BSTx

undervoltage

(BST_UV)

V_BSTx- V_SHx< V_{BST_UV}and

INHx = High

Latched:

nSLEEP Reset Pulse

-

nFAULT

Pulled Low ²

Active

Latched:

nSLEEP Reset Pulse

0.1V < V_VDSLVL< 2.5V

nFAULT

None

Pulled Low ²

Active

V_DSovercurrent

(VDS_OCP)

V_DS> V_{DS_LVL}

VDSLVL pin 100kΩ

tied to GVDD

No action

Latched:

nSLEEP Reset Pulse

-

nFAULT

None

Pulled Low ²

Active

V_SENSE

overcurrent

(SEN_OCP)

V_SP> V_{SENSE_LVL}

VDSLVL pin 100kΩ

tied to GVDD

No action

Thermal

shutdown

(OTSD)

Latched:

nSLEEP Reset Pulse

T_J> T_OTSD

-

nFAULT

Pulled Low ²

Active

1. Disabled: Passive pull down for GLx and semiactive pull down for GHx

2. Pulled Low: GHx and GLx are actively pulled low by the gate driver

8.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)

If at any time the power supply voltage on the PVDD pin falls below the V_{PVDD_UV}threshold for longer than the

t_{PVDD_UV_DG}time, the device detects a PVDD undervoltage event. After detecting the undervoltage condition, the

gate driver is disabled, the charge pump is disabled, the internal digital logic is disabled, and the nFAULT pin is

driven low. Normal operation starts again (the gate driver becomes operable and the nFAULT pin is released)

when the PVDD pin rises above V_{PVDD_UV}

.

8.3.6.2 AVDD Power on Reset (AVDD_POR)

If at any time the supply voltage on the AVDD pin falls below the V_{AVDD_POR}threshold for longer than the

t_{AVDD_POR_DG}time, the device enters an inactive state, disabling the gate driver, the charge pump, and the

internal digital logic, and nFAULT is driven low. Normal operation (digital logic operational) requires nSLEEP to

be asserted high and AVDD to exceed V_{AVDD_POR}level.

8.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)

If at any time the voltage on the GVDD pin falls lower than the V_{GVDD_UV}threshold voltage for longer than the

t_{GVDD_UV_DG}time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage

event, all of the gate driver outputs are driven low to disable the external MOSFETs, the charge pump is disabled

and nFAULT pin is driven low. After the GVDD_UV condition is cleared, the fault state remains latched and can

be cleared through an nSLEEP pin reset pulse (t_RST

)

Note

After the GVDD_UV fault is cleared through an nSLEEP pin reset pulse, the nFAULT pin is held low

until the GVDD capacitor is refreshed by the charge pump. After the GVDD capacitor is charged, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low after the fault is cleared

will not exceed t_WAKEtime.

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8.3.6.4 BST Undervoltage Lockout (BST_UV)

If at any time the voltage across BSTx and SHx pins falls lower than the V_{BST_UV}threshold voltage for longer

than the t_{BST_UV_DG}time, the device detects a BST undervoltage event. Afer detecting the BST_UV event, all of

the gate driver outputs are driven low to disable the external MOSFETs, and nFAULT pin is driven low. After the

BST_UV condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset

pulse (t_RST).

8.3.6.5 MOSFET V_DSOvercurrent Protection (VDS_OCP)

The device has adjustable V_DSvoltage monitors to detect overcurrent or short-circuit conditions on the external

power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the V_DSvoltage drop across the

external MOSFET R_DS(on). The high-side VDS monitors measure between the PVDD and SHx pins and the low-

side VDS monitors measure between the SHx and LSS pins. If the voltage across external MOSFET exceeds

the V_{DS_LVL}threshold for longer than the t_{DS_DG}deglitch time, a VDS_OCP event is recognized. Afer detecting

the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and

nFAULT pin is driven low. The VDS threshold can be set between 0.1 V to 2.5 V by applying a voltage on the

VDSLVL pin. VDS OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor. After the

VDS_OCP condition is cleared, the fault state remains latched and can be cleared through the nSLEEP pin reset

pulse (t_RST).

PVDD

+

V_DS

+

–

V_DS

–

V

VDS_OCP

GHx

SHx

GLx

+

–

+

–

V_DS

VDS_OCP

V_DS

LSS

GND

Figure 8-14. DRV8329 V_DSMonitors

8.3.6.6 V_SENSEOvercurrent Protection (SEN_OCP)

Overcurrent is also monitored by sensing the voltage drop across the external current sense resistor between

the LSS and GND pins. If at any time the voltage on the LSS input exceeds the V_{SEN_OCP}threshold for longer

than the t_{DS_DEG}deglitch time, a SEN_OCP event is recognized. Afer detecting the SEN_OCP overcurrent

event, all of the gate driver outputs are driven low to disable the external MOSFETs and the nFAULT pin is

driven low. The V_SENSEthreshold is fixed at 0.5 V and deglitch time is fixed to 3 µs. After the SEN_OCP

condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset pulse

(t_RST). SEN_OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor.

8.3.6.7 Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTSD), an OTSD event is recognized.

After detecting the OTSD overtemperature event, all of the gate driver outputs are driven low to disable the

external MOSFETs, charge pump is disabled and nFAULT pin is driven low. After OTSD condition is cleared, the

fault state remains latched and can be cleared through an nSLEEP pin reset pulse (t_RST

)

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8.4 Device Functional Modes

8.4.1 Gate Driver Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of the DRV8329. When the nSLEEP pin is low, the device goes to a

low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the

GVDD regulator is disabled and the AVDD regulator is disabled. The t_SLEEPtime must elapse after a falling edge

on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if

the nSLEEP pin is pulled high. The t_WAKEtime must elapse before the device is ready for inputs.

Note

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held

low as the internal regulators are not active. After the regulators have been active, the nFAULT pin is

automatically released. The duration that the nFAULT pin is low does not exceed the t_SLEEPor t_WAKE

time.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the V_PVDDvoltage is greater than the V_{PVDD_UV}voltage, the device goes

to operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the GVDD

regulator and AVDD regulator are active.

8.4.1.3 Fault Reset (nSLEEP Reset Pulse)

In the case of device latched faults, the DRV8329 goes into a partial shutdown state to help protect the external

power MOSFETs and system.

Note

If the user wants to put the device into sleep state after latched fault event, the inputs INHx and INLx

needs to be pulled low prior to driving the nSLEEP pin. If the inputs INHx and INLx are not driven low,

then the fault is reset after nSLEEP is driven low for the t_RSTtime and there can be pulses on gate

driver outputs GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx

can be of duration t_SLEEPif INHx and INLx are not pulled low.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The DRV8329 family of devices is primarily used in applications for three-phase brushless DC motor control. The

design procedures in the Section 9.2 section highlight how to use and configure the DRV8329 family of devices.

9.2 Typical Application

9.2.1 Three Phase Brushless-DC Motor Control

In this application, the DRV8329 is used to drive a three-phase Brushless-DC motor.

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PVDD

BSTA

GVDD

CPH

>10 uF

470 nF

>10 uF

0.1 uF

PVDD

C_BSTA

R_GHA

GHA

SHA

CPL

AVDD

>1uF

AVDD

R_GLA

GLA

DRV8329

INHA

INLA

PVDD

BSTB

C_BSTB

INHB

INLB

R_GHB

PWM

GHB

SHB

MCU

INHC

INLC

R_GLB

GLB

DRVOFF

nSLEEP

I/O

Analog Input

(0.1 to 2.5V)

PVDD

BSTC

C_BSTC

R_GHC

VDSLVL

AVDD

GHC

SHC

nFAULT

DT

R_GLC

GLC

LSS

SP

SN

SO

SN

SP

–

+

SO

AVDD

CSAREF

GND

Figure 9-1. DRV8329 Application Diagram

9.2.1.1 Detailed Design Procedure

Section 9.2.1.1 lists the example input parameters for the system design.

Table 9-1. Design parameters

DESIGN PARAMETERS

Supply voltage

REFERENCE

EXAMPLE VALUE

V_PVDD

24 V

20 A

Motor peak current

I_PEAK

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Table 9-1. Design parameters (continued)

DESIGN PARAMETERS

REFERENCE

EXAMPLE VALUE

20 kHz

PWM Frequency

MOSFET VDS Slew Rate

MOSFET input gate capacitance

Dead time

f_PWM

SR

120 V/us

54 nC

Q_G

Q_GD

t_dead

I_OCP

14 nC

200 ns

Overcurrent protection

30 A

9.2.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 18-V, 24-V or 36-V). The DRV8329

allows for a range of possible operating voltages from 4.5-V to 60-V.

9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection

The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for

normal operation. Equation 4 calculates the maximum allowable voltage drop across the bootstrap capacitor:

¿8_$56:= 8_)8&&F8_$116&F8

$5678

(4)

=12 V – 0.85 V – 4.45 V = 6.7 V

where

•

V_GVDDis the supply voltage of the gate drive

V_BOOTDis the forward voltage drop of the bootstrap diode

V_BSTUVis the threshold of the bootstrap undervoltage lockout

In this example the allowed voltage drop across bootstrap capacitor is 6.7 V. It is generally recommended that

ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.

Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.

The total charge needed per switching cycle can be estimated with Equation 5:

IL

BS_TRAN

Q

= Q +

G

(5)

TOT

f

SW

=54 nC + 115 μA/20 kHz = 54 nC + 5.8 nC = 59.8nC

where

•

Q_Gis the total MOSFET gate charge

I_{LBS_TRAN}is the bootstrap pin leakage current

f_SWis the is the PWM frequency

The minimum bootstrap capacitor can then be estimated as below assuming 1V of ΔV_BSTx

:

3

%

=

⁶¹⁶W

$56_/+0

¿8

$56:

(6)

= 59.8 nC / 1 V = 59.8 nF

The calculated value of minimum bootstrap capacitor is 59.8 nF. It should be noted that, this value of

capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater

than calculated value to allow for situations where the power stage may skip pulse due to various transient

conditions. It is recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to

include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.

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%

)8&&

R 10 × %_$56:

(7)

= 10*100 nF= 1 μF

For this example application, choose a 1-µF C_GVDDcapacitor. Choose a capacitor with a voltage rating at

least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant

capacitance when biased. This value also improves the long-term reliability of the system.

Note

For higher power system requiring 100% duty cycle support for longer duration it is recommended to

use C_BSTxof ≥1μF and C_GVDDof ≥10 μF.

9.2.1.1.3 Gate Drive Current

Selecting an appropriate gate drive current is essential when turning on or off power MOSFETs gates to

switch motor current. The amount of gate drive current and input capacitance of the MOSFETs determines the

drain-to-source voltage slew rate (V_DS). Gate drive current can be sourced from GVDD into the MOSFET gate

(I_SOURCE) or sunk from the MOSFET gate into SHx or LSS (I_SINK).

Using too high of a gate drive current can turn on MOSFETs too quickly which may cause excessive ringing,

dV/dt coupling, or cross-conduction from switching large amounts of current. If parasitic inductances and

capacitances exist in the system, voltage spiking or ringing may occur which can damage the MOSFETs or

DRV8329 device.

PVDD

VINHx

VGHx

GVDD

I

INHx

GHx

HS

VDS

SHx

PHASE

CGD

VGLx

GVDD

INLx

GLx

LSS

LS

Figure 9-2. Effects of high gate drive current

On the other hand, using too low of a gate drive current causes long V_DSslew rates. Turning on the MOSFETs

too slowly may heat up the MOSFETs due to R_DS,onswitching losses.

The relationship between gate drive current I_GATE, MOSFET gate-to-drain charge Q_GD, and V_DSslew rate

switching time t_rise,fallare described by the following equations:

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V

DS

SR

=

t

(8)

(9)

DS

rise, fall

Q

gd

I

=

t

GATE

rise, fall

It is recommend to evaluate at lower gate drive currents and increase gate drive current settings to avoid

damage from unintended operation during initial evaluation.

9.2.1.1.4 Gate Resistor Selection

The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs is

controlled. The pull-up/pull-down strength of the DRV8329 is fixed internally, hence the slew rate of gate voltage

can be controlled with an external series gate resistor. In some applications, the gate charge of the MOSFET,

which is the load on gate driver device, is significantly larger than the gate driver peak output current capability.

In such applications, external gate resistors can limit the peak output current of the gate driver. External gate

resistors are also used to dampen ringing and noise.

The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final SHx slew

rate, so generally selecting an optimal value or configuration of external gate resistor is an iterative process.

To lower the gate drive current, a series resistor R_GATEcan be placed on the gate drive outputs to control the

current for the source and sink current paths. A single gate resistor will have the same gate path for source and

sink gate current, so larger R_GATEvalues will yield similar SHx slew rates. Note that gate drive current varies by

PVDD voltage, junction temperature, and process variation of the device. Gate resistor values can be estimated

with +/-30% accuracy using the Gate Resistor Calculator.

PVDD

GVDD

R_GATE

INHx

GHx

SHx

HS

GVDD

R_GATE

INLx

GLx

LSS

LS

R_SINK

Figure 9-3. Gate driver outputs with series resistors

Typically, it is recommended to have the sink current be twice the source current to implement a strong pulldown

from gate to the source to ensure the MOSFET stays off while the opposite FET is switching. This can be

implemented discretely by providing a separate path through a resistor for the source and sink currents by

placing a diode and sink resistor (R_SINK) in parallel to the source resistor (R_SOURCE). Using the same value of

source and sink resistors results in half the equivalent resistance for the sink path. This yields twice the gate

drive sink current compared to the source current, and SHx will slew twice as fast when turning off the MOSFET.

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PVDD

GVDD

R_SOURCE

INHx

GHx

SHx

HS

R_SINK

GVDD

R_SOURCE

INLx

GLx

LSS

LS

R_SINK

Figure 9-4. Gate driver outputs with separate source and sink current paths

9.2.1.1.5 System Considerations in High Power Designs

Higher power system designs can require design and application considerations that are not regarded in lower

power system designs. It is important to combat the volatile nature of higher power systems by implementing

troubleshooting guidelines, external components and circuits, driver product features, or layout techniques. For

more information, please visit the System Design Considerations for High-Power Motor Driver Applications

application note.

9.2.1.1.5.1 Capacitor Voltage Ratings

Use capacitors with voltage ratings that are 2x the supply voltage (PVDD, GVDD, AVDD, etc). Capacitors can

experience up to half the rated capacitance due to poor DC voltage rating performance.

For example, since the bootstrap voltage is around 12 to 13-V with respect to SHx (BSTx-SHx) then the

BSTx-SHx capacitor should be rated for 25-V or greater.

9.2.1.1.5.2 External Power Stage Components

External components in the power stage are not required by design but are helpful in suppressing transients,

managing inductor coil energy, mitigating supply pumping, dampening phase ringing, or providing strong gate-to-

source pulldown paths. These components are used for system tuning and debuggability so the BLDC motor

system is robust while avoiding damage to the DRV8329 device or external MOSFETs.

Figure 9-5 shows examples of power stage components that can be optimally placed in the design.

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PVDD

GVDD

R_SNUB

R_SOURCE

C_BULK

R_PD

INHx

GHx

SHx

HS

R_SINK

C_SNUB

PHASE

C_{HSD_LSS}

C_SNUB

GVDD

R_SOURCE

R_PD

INLx

GLx

LSS

LS

R_SNUB

D_GS

R_SINK

Figure 9-5. Optional external power stage components

Some examples of issues and external components that can resolve those issues are found in Table 9-2:

Table 9-2. Common issues and resolutions for power stage debugging

Issue

Resolution

Component(s)

Gate drive current required is too large,

Series resistors required for gate drive

0-100 Ω series resistors (RGATE/RSOURCE)

at gate driver outputs (GHx/GLx), optional

sink resistor (RSINK) and diode in parallel

with gate resistor for adjustable sink current

resulting in very fast MOSFET V_DSslew rate current adjustability

Ringing at phase’s switch node (SHx)

resulting in high EMI emissions

RC snubbers placed in parallel to each

HS/LS MOSFET to dampen oscillations

Resistor (RSNUB) and Capacitor (CSNUB)

placed parallel to the MOSFET, calculate

RC values based on ringing frequency using

Proper RC Snubber Design for Motor Drivers

Negative transients at low-side source (LSS) HS drain to LS source capacitor to suppress 0.01uF-1uF, VM-rated capacitor from

below minimum specification

negative bouncing

PVDD-LSS (CHSD_LSS) placed near LS

MOSFET’s source

Negative transient at low-side gate (GLx)

below minimum specification

Gate-to-ground Zener diode to clamp

negative voltage

GVDD voltage rated Zener diode (DGS)

with anode connected to GND and cathode

connected to GLx

Extra protection required to ensure MOSFET External gate-to-source pulldown resistors

is turned off if gate drive signals are Hi-Z (after series gate resistors)

10 kΩ to 100 kΩ resistor (RPD) connected

from gate to source for each MOSFET

9.2.1.1.5.3 Parallel MOSFET Configuration

If higher MOSFET continuous drain current ratings are required for the motor, parallel MOSFETs can be used for

higher current capability. However, this requires special schematic and layout design requirements to switch both

MOSFETs simultaneously because one MOSFET may turn on faster than the other due to process variation.

It is recommended to place the MOSFETs close together with a common gate signal that splits as close as

possible to the MOSFETs gates. If gate resistance is required, calculate the equivalent resistance required for

the equivalently rated MOSFET, and place the gate resistors as close as possible to the MOSFET’s gate input to

dampen any coupling into the gate driver.

For more information, please visit the Driving Parallel MOSFETs application brief.

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9.2.1.1.6 Dead Time Resistor Selection

Dead time insertion is available in the DRV8329 via a resistor (R_DT) from the DT pin to ground as shown in

Figure 9-6. The ranges of dead time in the DRV8329 is 100 ns to 2000 ns when R_DTis tied to GND from the DT

pin. A linear interpolation of the resistance value is used to set the appropriate dead time.

R_DT

DT

Figure 9-6. Dead time resistor

Dead time (in nanoseconds) can be calculated from the dead time resistor calculation in Equation 1.

Dead time can also be implemented from the PWM inputs generated by an MCU. If dead time is inserted at the

PWM inputs and the DRV8329, then the driver output PWM dead time is the larger of the two dead times. For

instance, if 200 ns dead time is inserted at the MCU inputs and 50 ns dead time is inserted in the DRV8329 via

the DT pin, then the output driver PWM dead time will be 200 ns.

9.2.1.1.7 VDSLVL Selection

VDSLVL is an analog voltage used to directly set the VDS overcurrent threshold for overcurrent protection. It can

be sourced directly from an analog voltage source (such as a digital-to-analog converter) or divided down from a

voltage rail (such as a resistor divider from AVDD) as shown in Figure 9-7.

V_in

R₁

VDSLVL

R₂

Figure 9-7. Resistor divider to set VDSLVL from a voltage rail

Equation 10 and Equation 11 can be used to set the required VDSLVL voltage using a resistor divider from a

voltage source to establish an overcurrent limit given the R_DS,onof the MOSFETs used:

V

= I × R

OC ds on

(10)

(11)

VDSLVL

R

V

1

2

in

=

− 1

V

VDSLVL

where:

•

V_VDSLVL= VDSLVL voltage

I_OCP= VDS overcurrent limit

R_DS,on= MOSFET on-resistance

V_IN= voltage source for VDSLVL voltage divider

R1/R2 = resistor ratio for setting VDSLVL

For example, if a resistor divider from AVDD is used to set an overcurrent trip threshold of 30-A and the

MOSFET R_DS(ON)= 10mΩ, then VDSLVL = 0.3V.

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In some applications, there will be a difference between battery voltage (VBAT) to directly drive motor power

and PVDD voltage to power the DRV8329. Because high-side VDS monitoring is referenced from PVDD-SHx,

VDSLVL needs to be selected appropriately to accommodate for the difference in VBAT and PVDD.

Equation 12 helps select an appropriate VDSLVL if there is a difference between PVDD and VDSLVL:

VDSLVL = VBAT − PVDD + I *R

(12)

OC DS ON

For instance, if VBAT = 24.0 V, PVDD = 23.3 V, Rdson = 10-mΩ, and I_OC = 30-A, then VDSLVL should equal

1.0V to detect a 30-A overcurrent event across the high-side FET and a 100-A overcurrent event across the

low-side FET.

9.2.1.1.8 AVDD Power Losses

An integrated LDO can supply 3.3-V (up to 80-mA) as power rails for external ICs or supply the pullup voltages

for resistors and switches. The power loss from AVDD with respect to PVDD, AVDD voltage, and AVDD current

is P_AVDD= (V_PVDD- V_AVDD) x I_AVDD.

Higher power losses occur due larger dropout from PVDD to 3.3 V or increased AVDD load current.

9.2.1.1.9 Current Sensing and Output Filtering

The SO pin is typically sampled by an analog-to-digital converter in the MCU to calculate the total motor

phase current. A phase current calculation is used for closed-loop feedback such as overcurrent protection or

sensorless trapezoidal or Field-oriented control commutation

An example calculation for phase current is shown below for a system using V_SO= 1.4 V, V_CSAREF= 3.3V,

CSAGAIN = 20 V/V, and R_SENSE= 1 mΩ.

V

CSAREF

8

V

−

SO

I =

(13)

CSAGAIN × R

SENSE

3.3 V

8

1.4 V −

(14)

(15)

20 V/V × 0.001

I = 49.375 A

Sometimes high frequency noise can appear at the SO signals based on voltage ripple at VREF, added

inductance at the SO traces, or routing of SO traces near high frequency components. It is recommended to add

a low-pass RC filter close to the MCU with cutoff frequency at least 10 times the PWM switching frequency for

trapezoidal commutation and 100 times the PWM switching frequency for sinusoidal commutation to filter high

frequency noise. A recommended RC filter is 330-ohms, 470-pF to add minimal parallel capacitance to the ADC

and current mirroring circuitry. The cutoff frequency for the low-pass RC filter is in Equation 16.

1

f =

(16)

c

2πRC

9.2.1.1.10 Power Dissipation and Junction Temperature Losses

To calculate the junction temperature of the DRV8329 from power losses, use Equation 17. Note that the thermal

resistance θ_JAdepends on PCB configurations such as the ambient temperature, numbers of PCB layers,

copper thickness on top and bottom layers, and the PCB area.

℃

W

T ℃ = P

W × θ

+ T ℃

A

(17)

J

loss

JA

The table below shows summary of equations for calculating each loss in the DRV8329.

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Table 9-3. DRV8329 Power Losses

Loss type

Equation

Standby power

P_standby= V_PVDDx I_PVDDS

GVDD CP mode (PVDD < 18V)

GVDD LDO mode (PVDD > 18V)

AVDD LDO

P_LDO= 2 x V_PVDDx I_GVDD- V_GVDDx I_GVDD

P_LDO= (V_PVDD- V_GVDD) x I_GVDD

P_LDO= (V_PVDD- V_AVDD) x I_AVDD

9.2.2 Application Curves

Figure 9-8. Device Powerup with PVDD

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Figure 9-9. Device Powerup with nSLEEP

Figure 9-10. GVDD voltage threshold (PVDD = 4.5 V)

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Figure 9-11. GVDD voltage threshold (PVDD = 20V)

Figure 9-12. AVDD powerup

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Figure 9-13. DRVOFF operation

Figure 9-14. Driver operation at 100% duty cycle

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Figure 9-15. Driver PWM operation, 20 kHz, 50% duty cycle, zoomed

Figure 9-16. Driver dead time of 100 ns (DT = 10 kΩ to GND)

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Figure 9-17. Driver dead time of 2000 ns (DT = 390 kΩ to GND)

Figure 9-18. Current sense amplifier operation (GAIN = 40 V/V)

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10 Power Supply Recommendations

The DRV8329 family of devices is designed to operate from an input voltage supply (PVDD) range from 4.5

V to 60 V. A 10-µF and 0.1-µF ceramic capacitor rated for PVDD must be placed as close to the device as

possible. In addition, a bulk capacitor must be included on the PVDD pin but can be shared with the bulk bypass

capacitance for the external power MOSFETs. Additional bulk capacitance is required to bypass the external

half-bridge MOSFETs and should be sized according to the application requirements.

10.1 Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The

amount of local capacitance depends on a variety of factors including:

•

The highest current required by the motor system

The power supply's type, capacitance, and ability to source current

The amount of parasitic inductance between the power supply and motor system

The acceptable supply voltage ripple

Type of motor (brushed DC, brushless DC, stepper)

The motor startup and braking methods

The inductance between the power supply and motor drive system will limit the rate current can change from the

power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands

or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet provides a recommended minimum value, but system level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 10-1. Motor Drive Supply Parasitics Example

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11 Layout

11.1 Layout Guidelines

Bypass the PVDD pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of

0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to

the PGND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be

electrolytic. This capacitance must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk

capacitance should be placed such that it minimizes the length of any high current paths through the external

MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB

layers. These practices minimize inductance and let the bulk capacitor deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 470 nF, rated for

PVDD, and be of type X5R or X7R.

The bootstrap capacitors (BSTx-SHx) should be placed closely to device pins to minimize loop inductance for

the gate drive paths.

The dead time resistor (R_DT) should be placed as close as possible to the DT pin.

Bypass the AVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or

X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND

pin.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of

the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx

pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the

low-side MOSFET source back to the PGND pin.

When designing higher power systems, physics in the PCB layout can cause parasitic inductances,

capacitances, and impedances that deter the performance of the system as shown in Figure 11-1.

Understanding the parasitics that are present in a higher power motor drive system can help designers mitigate

their effects through good PCB layout. For more information, please visit the System Design Considerations for

High-Power Motor Driver Applications and Best Practices for Board Layout of Motor Drivers application notes.

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PVDD

L_P

R_P

PVDD

C_P

GVDD

C_BULK

L_P

R_SNUB

R_GATE

INHx

GHx

SHx

HS

L_P

C_SNUB

PHASE

C_P

C_SNUB

GVDD

L_P

R_GATE

INLx

GLx

LSS

LS

R_SNUB

L_P

R_PDIFF

L_P

C_P

SNx

L_P

Figure 11-1. Parasitics in the PCB of a BLDC motor driver powerstage

Gate drive traces (BSTx, GHx, SHx, GLx, LSS) should be at least 15-20mil wide and as short as possible to the

MOSFET gates to minimize parasitic inductances and impedances. This helps supply large gate drive currents,

turn MOSFETs on efficiently, and improves VGS and VDS monitoring. If a shunt resistor is used to monitor the

low-side current from LSS to GND, ensure the shunt resistor selected is wide to minimize inductance introduced

at the low-side source LSS.

TI recommends connecting all non-power stage circuitry (including the thermal pad) to GND to reduce parasitic

effects and improve power dissipation from the device. Ensure grounds are connected through net-ties or wide

resistors to reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

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11.2 Layout Example

DRV8329 Layout

Figure 11-2. Layout of DRV8329 device

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Power Stage Layout

Figure 11-3. Layout of inverter power stage

11.3 Thermal Considerations

The DRV8329 has thermal shutdown (TSD) to protect against overtemperature. A die temperature in excess of

150°C (minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation

The DRV8329 integrates a variety of circuits that contribute to total power losses. These power losses include

standby power losses, GVDD power losses, and AVDD power losses.

At start-up and fault conditions, this current is much higher than normal running current; remember to take these

peak currents and their duration into consideration.

The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

The following figure shows a legend for interpreting the complete device name:

12.2 Documentation Support

12.2.1 Related Documentation

•

Refer to the application note Power Delivery in Cordless Power Tools Using DRV8329

Texas Instruments, DRV8329AEVM evaluation module

Refer to the application note System Design Considerations for High-Power Motor Driver Applications

Refer to the E2E FAQ How to Conduct a BLDC Schematic Review and Debug

Refer to the application note Best Practices for Board Layout of Motor Drivers

Refer to the application note QFN and SON PCB Attachment

Refer to the application note Cut-Off Switch in High-Current Motor-Drive Applications

Refer to the application note Hardware design considerations for an efficient vacuum cleaner using a BLDC

motor

•

Refer to the application note Hardware Design Considerations for an Electric Bicycle Using a BLDC Motor

Refer to the application note Sensored 3-Phase BLDC Motor Control Using MSP430

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.5 Community Resources

12.6 Trademarks

All trademarks are the property of their respective owners.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

REE0036A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 2.8

2.8

2.6

(0.1) TYP

11

18

4X (0.41)

32X 0.4

10

19

2X

SYMM

3.8

3.6

1

28

0.25

0.15

36X

29

36

PIN 1 ID

0.1

C A B

SYMM

0.5

0.3

0.05

36X

4226725/A 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

EXAMPLE BOARD LAYOUT

REE0036A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.8)

2X (2.8)

(2.7)

29

36

36X (0.6)

32X (0.2)

1

28

32X (0.4)

(4.8)

37

SYMM

(3.7)

2X (3.6)

2X (0.625)

2X (0.975)

10

19

(R0.05) TYP

11

(

0.2) TYP

18

2X (1.1)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226725/A 04/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

EXAMPLE STENCIL DESIGN

REE0036A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.8)

2X (2.8)

6X (1.19)

36

29

36X (0.6)

1

28

36X (0.2)

6X

(1.05)

32X (0.4)

2X (3.6)

SYMM

(4.8)

2X (1.25)

10

19

(R0.05)

TYP

11

18

2X (0.7)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4226725/A 04/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

13.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

P1

K0

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

PDRV8329AREER

WQFN

REE

36

5000

330.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

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SLVSGX4A – JUNE 2022 – REVISED OCTOBER 2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

Package Drawing Pins

REE 36

SPQ

Length (mm) Width (mm)

367.0 367.0

Height (mm)

PDRV8329AREER

WQFN

5000

35.0

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8329AREER
厂家：	TEXAS INSTRUMENTS
描述：	具有单个电流检测放大器的 60V 1000/2000mA 三相栅极驱动器 \| REE \| 36 \| -40 to 125 放大器栅极驱动驱动器
文件：	总56页 (文件大小：3155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8329AREER [TI]

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