DRV8353HM_技术文档

DRV8353M

_SLVSFOD_{2 –}R_JV_U8_L3_Y5₂3₀₂M₀

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DRV8353M 100-V Three-Phase Smart Gate Driver

1 Features

3 Description

•

9 to 100-V, Triple half-bridge gate driver

The DRV8353M family of devices are highly-

integrated gate drivers for three-phase brushless DC

(BLDC) motor applications. These applications

include field-oriented control (FOC), sinusoidal current

control, and trapezoidal current control of BLDC

motors. The device variants provide optional

integrated current shunt amplifiers to support different

motor control schemes and a buck regulator to power

the gate driver or external controller.

– Extended T_Aoperation -55 °C to 125 °C

– Optional triple low-side current shunt amplifiers

Smart gate drive architecture

– Adjustable slew rate control for EMI

performance

•

– V_GShandshake and minimum dead-time

insertion to prevent shoot-through

– 50-mA to 1-A peak source current

– 100-mA to 2-A peak sink current

– dV/dt mitigation through strong pulldown

Integrated gate driver power supplies

– High-side doubler charge pump For 100%

PWM duty cycle control

The DRV8353M uses smart gate drive (SGD)

architecture to decrease the number of external

components that are typically necessary for MOSFET

slew rate control and protection circuits. The SGD

architecture also optimizes dead time to prevent

shoot-through conditions, provides flexibility in

decreasing electromagnetic interference (EMI) by

MOSFET slew rate control, and protects against gate

short circuit conditions through V_GSmonitors. A strong

gate pulldown circuit helps prevent unwanted dV/dt

parasitic gate turn on events

•

– Low-side linear regulator

•

Integrated triple current shunt amplifiers

– Adjustable gain (5, 10, 20, 40 V/V)

– Bidirectional or unidirectional support

6x, 3x, 1x, and independent PWM modes

– Supports 120° sensored operation

SPI or hardware interface available

Low-power sleep mode (20 µA at V_VM= 48-V)

Integrated protection features

– VM undervoltage lockout (UVLO)

– Gate drive supply undervoltage (GDUV)

– MOSFET V_DSovercurrent protection (OCP)

– MOSFET shoot-through prevention

– Gate driver fault (GDF)

Various PWM control modes (6x, 3x, 1x, and

independent) are supported for simple interfacing to

the external controller. These modes can decrease

the number of outputs required of the controller for the

motor driver PWM control signals. This family of

devices also includes 1x PWM mode for simple

sensored trapezoidal control of a BLDC motor by

using an internal block commutation table.

•

Table 3-1. Device Information

PART NUMBER

PACKAGE

BODY SIZE (NOM)

– Thermal warning and shutdown (OTW/OTSD)

– Fault condition indicator (nFAULT)

DRV8353M

WQFN (40)

6.00 mm x 6.00 mm

1. For all available packages, see the orderable

addendum at the end of the data sheet.

2 Applications

•

3-phase brushless-DC (BLDC) motor modules

Fans, blowers, and pumps

9 to 75 V

7 to 100 V

Drain

Sense

DRV8353M

PWM

Three-Phase

Smart Gate Driver

SPI or H/W

M

Gate Drive

nFAULT

Protection

Current

Sense

Current Sense

3x Shunt Amplifiers

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

Pin Functions—40-Pin DRV8353M Devices.....................3

7 Absolute Maximum Ratings........................................... 5

8 ESD Ratings.....................................................................6

9 Recommended Operating Conditions...........................7

10 Thermal Information......................................................8

11 Electrical Characteristics..............................................9

12 SPI Timing Requirements...........................................15

13 Detailed Description....................................................16

13.1 Overview.................................................................16

13.2 Functional Block Diagram.......................................17

13.3 Feature Description.................................................18

13.4 Device Functional Modes........................................41

13.5 Programming.......................................................... 42

13.6 Register Maps.........................................................44

14 Application and Implementation................................56

14.1 Application Information........................................... 56

14.2 Typical Application.................................................. 56

15 Power Supply Recommendations..............................65

15.1 Bulk Capacitance Sizing......................................... 65

16 Layout...........................................................................66

16.1 Layout Guidelines................................................... 66

16.2 Layout Example...................................................... 67

17 Device and Documentation Support..........................68

17.1 Device Support....................................................... 68

17.2 Documentation Support.......................................... 68

17.3 Receiving Notification of Documentation Updates..68

17.4 Support Resources................................................. 68

17.5 Trademarks.............................................................68

17.6 Electrostatic Discharge Caution..............................68

17.7 Glossary..................................................................69

18 Mechanical, Packaging, and Orderable

Information.................................................................... 69

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

July 2020

*

Initial Release

2

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5 Device Comparison Table

DEVICE

VARIANT

SHUNT AMPLIFIERS

INTERFACE

Hardware (H)

SPI (S)

DRV8353HM

DRV8353SM

DRV8353M

3

6 Pin Configuration and Functions

Pin Functions—40-Pin DRV8353M Devices

CPL

CPH

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

GAIN

VDS

CPL

CPH

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

nSCS

SCLK

SDI

VM

IDRIVE

MODE

nFAULT

AGND

VREF

SOA

VM

VDRAIN

VCP

VDRAIN

VCP

SDO

nFAULT

AGND

VREF

SOA

Thermal

Pad

Thermal

Pad

GHA

SHA

GHA

SHA

GLA

SPA

SOB

SPA

SOB

SNA

SOC

SNA

SOC

Not to scale

DRV8353HM RTA Package 40-Pin VWQFN With

Exposed Thermal Pad Top View

DRV8353SM RTA Package 40-Pin VWQFN With

Exposed Thermal Pad Top View

NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8353HM

DRV8353SM

AGND

CPH

25

PWR

Device analog ground. Connect to system ground.

Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL

pins.

2

1

2

1

Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL

pins.

CPL

PWR

I

5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This

regulator can source up to 10 mA externally.

DVDD

ENABLE

38

31

38

31

Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be

used to reset fault conditions.

GAIN

GND

GHA

GHB

GHC

GLA

30

39

6

—

39

6

I

Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.

Device power ground. Connect to system ground.

PWR

O

I

High-side gate driver output. Connect to the gate of the high-side power MOSFET.

Low-side gate driver output. Connect to the gate of the low-side power MOSFET.

Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.

High-side gate driver control input. This pin controls the output of the high-side gate driver.

Low-side gate driver control input. This pin controls the output of the low-side gate driver.

15

16

8

15

16

8

GLB

13

18

28

32

34

36

33

35

13

18

—

32

34

36

33

35

GLC

IDRIVE

INHA

INHB

INHC

INLA

INLB

I

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NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8353HM

DRV8353SM

INLC

MODE

nFAULT

nSCS

SCLK

SDI

37

27

26

—

7

37

—

26

30

29

28

27

7

I

Low-side gate driver control input. This pin controls the output of the low-side gate driver.

PWM input mode setting. This pin is a 4 level input pin set by an external resistor.

I

OD

Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.

Serial chip select. A logic low on this pin enables serial interface communication.

Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.

Serial data input. Data is captured on the falling edge of the SCLK pin.

Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.

High-side source sense input. Connect to the high-side power MOSFET source.

Shunt amplifier input. Connect to the low-side of the current shunt resistor.

Shunt amplifier output.

I

SDO

SHA

OD

I

SHB

14

17

10

11

20

23

22

21

14

17

10

11

20

23

22

21

SHC

SNA

I

SNB

I

SNC

SOA

SOB

SOC

I

O

Shunt amplifier output.

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

SPA

SPB

SPC

9

I

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

12

19

12

19

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

VCP

5

4

5

4

PWR

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.

High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.

VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.

VDRAIN

VDS

I

29

40

—

40

VGLS

PWR

11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.

Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,

0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.

VM

3

PWR

Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF

and AGND pins.

VREF

24

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain

4

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7 Absolute Maximum Ratings

at T_A= –55°C to +125°C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

GATE DRIVER

Power supply pin voltage (VM)

–0.3

0

80

V

Voltage differential between ground pins (AGND, BGND, DGND, PGND)

MOSFET drain sense pin voltage (VDRAIN)

MOSFET drain sense pin voltage slew rate (VDRAIN)

Charge pump pin voltage (CPH, VCP)

0.3

102

V

2

V_VDRAIN+ 16

V_VDRAIN

18

V/µs

V

–0.3

Charge-pump negative-switching pin voltage (CPL)

Low-side gate drive regulator pin voltage (VGLS)

Internal logic regulator pin voltage (DVDD)

V

5.75

V

Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK,

SDI, SDO, VDS)

–0.3

5.75

V

Continuous high-side gate drive pin voltage (GHx)

Transient 200-ns high-side gate drive pin voltage (GHx)

High-side gate drive pin voltage with respect to SHx (GHx)

Continuous high-side source sense pin voltage (SHx)

Transient 200-ns high-side source sense pin voltage (SHx)

Continuous low-side gate drive pin voltage (GLx)

–5⁽²⁾

–10

V_VCP+ 0.3

16

V

–0.3

–5⁽²⁾

–10

102

V_VDRAIN+ 5

V_VDRAIN+ 10

V_VGLS+ 0.3

–1.0

–5.0

Transient 200-ns low-side gate drive pin voltage (GLx)

Internally

limited

Internally

limited

Gate drive pin source current (GHx, GLx)

Gate drive pin sink current (GHx, GLx)

A

Internally

limited

Internally

limited

Continuous low-side source sense pin voltage (SLx)

Transient 200-ns low-side source sense pin voltage (SLx)

Continuous shunt amplifier input pin voltage (SNx, SPx)

Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)

Reference input pin voltage (VREF)

Shunt amplifier output pin voltage (SOx)

DRV8353M

–1

–5

1

V

5

–1

1

5

–5

–0.3

5.75

V_VREF+ 0.3

Ambient temperature, T_A

–55

–65

125

150

°C

Junction temperature, T_J

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.

This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

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8 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

V_(ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500

V may actually have higher performance.

6

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9 Recommended Operating Conditions

at T_A= –40°C to +125°C (unless otherwise noted)

MIN

MAX

UNIT

GATE DRIVER

V_VM

Gate driver power supply voltage (VM)

9

7

75

V

V_VDRAIN

Charge pump reference and drain voltage sense (VDRAIN)

100

Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK,

SDI, VDS)

V_I

0

5.5

V

f_PWM

t_SH

Applied PWM signal (INHx, INLx)

0

3

0

200⁽¹⁾

2

kHz

V/ns

mA

V

Switch-node slew rate range (SHx)

High-side average gate-drive current (GHx)

Low-side average gate-drive current (GLx)

External load current (DVDD)

I_{GATE_HS}

I_{GATE_LS}

I_DVDD

V_VREF

I_SO

25⁽¹⁾

10⁽¹⁾

5.5

5

Reference voltage input (VREF)

Shunt amplifier output current (SOx)

Open drain pullup voltage (nFAULT, SDO)

Open drain output current (nFAULT, SDO)

mA

V

V_OD

5.5

5

I_OD

mA

DRV8353M

T_A

Operating ambient temperature

Operating junction temperature

–55

125

150

°C

T_J

(1) Power dissipation and thermal limits must be observed.

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10 Thermal Information

DRV8353M

RTA (WQFN)

40 PINS

26.1

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

13.1

8.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

8.4

R_θJC(bot)

1.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8

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11 Electrical Characteristics

at T_A= –55°C to +125°C, V_VM= 9 to 75 V, V_VDRAIN= 9 to 100 V, V_VIN= 48 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

POWER SUPPLIES (DVDD, VCP, VGLS, VM)

V_VM= V_VDRAIN= 48 V, ENABLE = 3.3 V, INHx/INLx

= 0 V

I_VM

VM operating supply current

8.5

13

4

mA

V_VM= V_VDRAIN= 48 V, ENABLE = 3.3 V, INHx/INLx

= 0 V

I_VDRAIN

VDRAIN operating supply current

1.9

20

ENABLE = 0 V, V_VM= V_VDRAIN= 48 V, T_A= 25°C

ENABLE = 0 V, V_VM= V_VDRAIN= 48 V, T_A= 125°C

ENABLE = 0 V period to reset faults

V_VM> V_UVLO, ENABLE = 3.3 V to outputs ready

ENABLE = 0 V to device sleep mode

I_DVDD= 0 to 10 mA

40

100

40

I_SLEEP

Sleep mode supply current

µA

t_RST

Reset pulse time

Turnon time

5

us

ms

V

t_WAKE

t_SLEEP

V_DVDD

1

Turnoff time

1

DVDD regulator voltage

4.75

9

5

10.5

10

5.25

12

V_VM= 15 V, I_VCP= 0 to 25 mA

V_VM= 12 V, I_VCP= 0 to 20 mA

7.5

6

11.5

9.5

8.5

16

VCP operating voltage

with respect to VDRAIN

V_VCP

V

V_VM= 10 V, I_VCP= 0 to 15 mA

8

V_VM= 9 V, I_VCP= 0 to 10 mA

5.5

13

10

8

7.5

14.5

11.5

9.5

8.5

V_VM= 15 V, I_VGLS= 0 to 25 mA

V_VM= 12 V, I_VGLS= 0 to 20 mA

12.5

10.5

9.5

VGLS operating voltage

with respect to GND

V_VGLS

V_VM= 10 V, I_VGLS= 0 to 15 mA

V_VM= 9 V, I_VGLS= 0 to 10 mA

7

LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)

V_IL

V_IH

V_HYS

I_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

Input logic high current

Pulldown resistance

Propagation delay

0

0.8

5.5

V

1.5

100

mV

µA

kΩ

ns

V_VIN= 0 V

–5

5

I_IH

V_VIN= 5 V

50

100

200

70

R_PD

t_PD

To GND

INHx/INLx transition to GHx/GLx transition

FOUR-LEVEL H/W INPUTS (GAIN, MODE)

V_I1

Input mode 1 voltage

Tied to GND

0

V

V_COMP1

V_I2

V_COMP2

V_I3

V_COMP3

V_I4

Quad-level voltage comparator 1

Input mode 2 voltage

Voltage comparator between V_I1and V_I2

47 kΩ ± 5% to tied GND

Voltage comparator between V_I2and V_I3

Hi-Z

1.156 1.256 1.356

1.9

V

Quad-level voltage comparator 1

Input mode 3 voltage

2.408 2.508 2.608

V

3.1

V

Quad-level voltage comparator 3

Input mode 4 voltage

Voltage comparator between V_I3and V_I4

Tied to DVDD

3.614 3.714 3.814

V

5

50

84

V

R_PU

Pullup resistance

Internal pullup to DVDD

Internal pulldown to GND

kΩ

R_PD

Pulldown resistance

SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)

V_I1

Input mode 1 voltage

Tied to GND

0

V

V_COMP1

V_I2

V_COMP2

V_I3

V_COMP3

V_I4

Seven-level voltage comparator 1

Input mode 2 voltage

Voltage comparator between V_I1and V_I2

18 kΩ ± 5% tied to GND

Voltage comparator between V_I2and V_I3

75 kΩ ± 5% tied to GND

Voltage comparator between V_I3and V_I4

Hi-Z

0.057 0.157 0.257

0.8

Seven-level voltage comparator 2

Input mode 3 voltage

1.158 1.258 1.358

1.7

2.257 2.357 2.457

2.5

Seven-level voltage comparator 3

Input mode 4 voltage

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at T_A= –55°C to +125°C, V_VM= 9 to 75 V, V_VDRAIN= 9 to 100 V, V_VIN= 48 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Voltage comparator between V_I4and V_I5

75 kΩ ± 5% tied to DVDD

MIN

TYP MAX UNIT

V_COMP4

V_I5

V_COMP5

V_I6

V_COMP6

V_I7

Seven-level voltage comparator 4

Input mode 5 voltage

2.561 2.661 2.761

V

3.3

3.615 3.715 3.815

4.2

Seven-level voltage comparator 5

Input mode 6 voltage

Voltage comparator between V_I5and V_I6

18 kΩ ± 5% tied to DVDD

V

Seven-level voltage comparator 6

Input mode 7 voltage

Voltage comparator between V_I6and V_I7

Tied to DVDD

4.74

4.85

5

4.95

V

R_PU

Pullup resistance

Internal pullup to DVDD

73

kΩ

R_PD

Pulldown resistance

Internal pulldown to GND

OPEN DRAIN OUTPUTS (nFAULT, SDO)

V_OL

I_OZ

Output logic low voltage

I_O= 5 mA

V_O= 5 V

0.125

2

V

Output high impedance leakage

–2

µA

10

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at T_A= –55°C to +125°C, V_VM= 9 to 75 V, V_VDRAIN= 9 to 100 V, V_VIN= 48 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

GATE DRIVERS (GHx, GLx)

V_VM= 15 V, I_VCP= 0 to 25 mA

9

7.5

6

10.5

10

12

11.5

9.5

V_VM= 12 , I_VCP= 0 to 20 mA

V_VM= 10 V, I_VCP= 0 to 15 mA

V_VM= 9 V, I_VCP= 0 to 10 mA

V_VM= 15 V, I_VGLS= 0 to 25 mA

V_VM= 12 V, I_VGLS= 0 to 20 mA

V_VM= 10 V, I_VGLS= 0 to 15 mA

V_VM= 9 V, I_VGLS= 0 to 10 mA

DEAD_TIME = 00b

High-side gate drive voltage

with respect to SHx

V_GSH

V

8

5.5

9.5

9

7.5

8.5

11

12.5

12

10.5

9

Low-side gate drive voltage

with respect to PGND

V_GSL

7.5

6.5

10.5

9.5

8

50

DEAD_TIME = 01b

100

200

400

100

500

1000

2000

4000

50

SPI Device

Gate drive

dead time

t_DEAD

DEAD_TIME = 10b

ns

DEAD_TIME = 11b

H/W Device

SPI Device

H/W Device

TDRIVE = 00b

TDRIVE = 01b

TDRIVE = 10b

TDRIVE = 11b

Peak current

gate drive time

t_DRIVE

IDRIVEP_HS or IDRIVEP_LS = 0000b

IDRIVEP_HS or IDRIVEP_LS = 0001b

IDRIVEP_HS or IDRIVEP_LS = 0010b

IDRIVEP_HS or IDRIVEP_LS = 0011b

IDRIVEP_HS or IDRIVEP_LS = 0100b

IDRIVEP_HS or IDRIVEP_LS = 0101b

IDRIVEP_HS or IDRIVEP_LS = 0110b

IDRIVEP_HS or IDRIVEP_LS = 0111b

IDRIVEP_HS or IDRIVEP_LS = 1000b

IDRIVEP_HS or IDRIVEP_LS = 1001b

IDRIVEP_HS or IDRIVEP_LS = 1010b

IDRIVEP_HS or IDRIVEP_LS = 1011b

IDRIVEP_HS or IDRIVEP_LS = 1100b

IDRIVEP_HS or IDRIVEP_LS = 1101b

IDRIVEP_HS or IDRIVEP_LS = 1110b

IDRIVEP_HS or IDRIVEP_LS = 1111b

IDRIVE = Tied to GND

50

100

150

300

350

400

450

550

600

650

700

850

900

950

1000

50

SPI Device

Peak source

gate current

I_DRIVEP

mA

IDRIVE = 18 kΩ ± 5% tied to GND

IDRIVE = 75 kΩ ± 5% tied to GND

100

150

300

450

700

1000

H/W Device IDRIVE = Hi-Z

IDRIVE = 75 kΩ ± 5% tied to DVDD

IDRIVE = 18 kΩ ± 5% tied to DVDD

IDRIVE = Tied to DVDD

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at T_A= –55°C to +125°C, V_VM= 9 to 75 V, V_VDRAIN= 9 to 100 V, V_VIN= 48 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

IDRIVEN_HS or IDRIVEN_LS = 0000b

IDRIVEN_HS or IDRIVEN_LS = 0001b

IDRIVEN_HS or IDRIVEN_LS = 0010b

IDRIVEN_HS or IDRIVEN_LS = 0011b

IDRIVEN_HS or IDRIVEN_LS = 0100b

IDRIVEN_HS or IDRIVEN_LS = 0101b

IDRIVEN_HS or IDRIVEN_LS = 0110b

IDRIVEN_HS or IDRIVEN_LS = 0111b

IDRIVEN_HS or IDRIVEN_LS = 1000b

IDRIVEN_HS or IDRIVEN_LS = 1001b

IDRIVEN_HS or IDRIVEN_LS = 1010b

IDRIVEN_HS or IDRIVEN_LS = 1011b

IDRIVEN_HS or IDRIVEN_LS = 1100b

IDRIVEN_HS or IDRIVEN_LS = 1101b

IDRIVEN_HS or IDRIVEN_LS = 1110b

IDRIVEN_HS or IDRIVEN_LS = 1111b

IDRIVE = Tied to GND

MIN

TYP MAX UNIT

100

200

300

600

700

800

900

1100

1200

1300

1400

1700

1800

1900

2000

100

200

300

600

900

1400

2000

50

SPI Device

Peak sink

gate current

I_DRIVEN

mA

IDRIVE = 18 kΩ ± 5% tied to GND

IDRIVE = 75 kΩ ± 5% tied to GND

H/W Device IDRIVE = Hi-Z

IDRIVE = 75 kΩ ± 5% tied to DVDD

IDRIVE = 18 kΩ ± 5% tied to DVDD

IDRIVE = Tied to DVDD

Source current after t_DRIVE

I_HOLD

Gate holding current

mA

Sink current after t_DRIVE

100

2

I_STRONG

R_OFF

Gate strong pulldown current

Gate hold off resistor

GHx to SHx and GLx to SPx/SLx

A

150

kΩ

CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)

CSA_GAIN = 00b

4.85

9.7

5

10

5.15

10.3

20.6

41.2

5.15

10.3

20.6

41.2

SPI Device

CSA_GAIN = 01b

CSA_GAIN = 10b

CSA_GAIN = 11b

19.4

38.8

4.85

9.7

20

SPI Device

40

G_CSA

Amplifier gain

V/V

H/W Device GAIN = Tied to GND

H/W Device GAIN = 47 kΩ ± 5% tied to GND

H/W Device GAIN = Hi-Z

5

10

19.4

38.8

20

H/W Device GAIN = Tied to DVDD

V_{O_STEP}= 0.5 V, G_CSA= 5 V/V

40

250

500

1000

2000

V_{O_STEP}= 0.5 V, G_CSA= 10 V/V

V_{O_STEP}= 0.5 V, G_VSA= 20 V/V

V_{O_STEP}= 0.5 V, G_CSA= 40 V/V

t_SET

Settling time to ±1%

ns

V_COM

V_DIFF

V_OFF

Common mode input range

Differential mode input range

Input offset error

–0.15

–0.3

–3

0.15

0.3

3

V

V_SP= V_SN= 0 V

mV

µV/°C

V_DRIFT

Drift offset

10

V_VREF

– 0.25

V_LINEAR

SOx output voltage linear range

0.25

V

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PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

V_VREF

– 0.3

SPI Device

V_SP= V_SN= 0 V, VREF_DIV = 0b

SOx output voltage

bias

V_VREF

/ 2

V_BIAS

V_SP= V_SN= 0 V, VREF_DIV = 1b

V

V_VREF

/ 2

H/W Device V_SP= V_SN= 0 V

I_BIAS

SPx/SNx input bias current

SOx output slew rate

VREF input current

250

2.5

µA

V/µs

mA

V_SLEW

I_VREF

UGB

60-pF load

10

1.5

10

V_VREF= 5 V

Unity gain bandwidth

DRV835x: 60-pF load

MHz

PROTECTION CIRCUITS

DRV835x: VM falling, UVLO report

DRV835x: VM rising, UVLO recovery

Rising to falling threshold

8.0

8.2

8.3

8.5

200

10

8.8

9.0

V_{VM_UV}

VM undervoltage lockout

V

V_{VM_UVH}

t_{VM_UVD}

VM undervoltage hysteresis

VM undervoltage deglitch time

mV

us

VM falling, UVLO report

DRV835x: VDRAIN falling, UVLO report

DRV835x: VDRAIN rising, UVLO recovery

Rising to falling threshold

6.1

6.3

6.4

6.6

150

10

6.8

7.0

V_{VDR_UV}

VDRAIN undervoltage lockout

V

V_{VDR_UVH}

t_{VDR_UVD}

VDRAIN undervoltage hysteresis

mV

us

VDRAIN undervoltage deglitch time VDRAIN falling, UVLO report

VCP charge pump undervoltage

VCP falling, GDUV report

lockout

V_DRAIN

+ 5

V_{VCP_UV}

V

VGLS low-side regulator

VGLS falling, GDUV report

undervoltage lockout

V_{VGLS_UV}

4.25

Positive clamping voltage

High-side gate clamp

12.5

13.5

–0.7

16

V_{GS_CLAMP}

V

Negative clamping voltage

VDS_LVL = 0000b

VDS_LVL = 0001b

VDS_LVL = 0010b

VDS_LVL = 0011b

VDS_LVL = 0100b

VDS_LVL = 0101b

VDS_LVL = 0110b

0.041

0.051

0.061

0.071

0.081

0.18

0.27

0.36

0.45

0.54

0.63

0.72

0.81

0.9

0.06 0.082

0.07 0.094

0.08 0.106

0.09 0.118

0.1 0.125

0.2

0.24

0.3 0.345

0.4 0.455

0.5 0.565

VDS_LVL = 0111b

SPI Device

V

VDS_LVL = 1000b

VDS_LVL = 1001b

0.6

0.7

0.67

0.78

V_DSovercurrent

trip voltage

V_{VDS_OCP}

VDS_LVL = 1010b

VDS_LVL = 1011b

0.8 0.885

VDS_LVL = 1100b

0.9

1.0

1.5

2

1.0

1.1

VDS_LVL = 1101b

VDS_LVL = 1110b

1.35

1.8

1.65

2.2

VDS_LVL = 1111b

V

VDS = 75 kΩ ± 5% tied to GND

VDS = Hi-Z

0.18

0.36

0.63

0.9

0.2

0.24

0.4 0.455

VDS = 75 kΩ ± 5% tied to DVDD

VDS = 18 kΩ ± 5% tied to DVDD

0.7

1

0.78

1.1

H/W Device

V_DSovercurrent

trip voltage

V_{VDS_OCP}

VDS = Tied to DVDD

Disabled

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PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

OCP_DEG = 00b

1

2

OCP_DEG = 01b

OCP_DEG = 10b

OCP_DEG = 11b

V_DSand V_SENSE

overcurrent deglitch

time

SPI Device

H/W Device

SPI Device

t_{OCP_DEG}

4

us

8

4

SEN_LVL = 00b

SEN_LVL = 01b

SEN_LVL = 10b

SEN_LVL = 11b

0.25

0.5

0.75

1

V_SENSEovercurrent

trip voltage

V_{SEN_OCP}

V

H/W Device

SPI Device

H/W Device

1

TRETRY = 0b

TRETRY = 1b

8

ms

us

t_RETRY

Overcurrent retry time

50

8

ms

°C

T_OTW

T_OTSD

T_HYS

Thermal warning temperature

Thermal shutdown temperature

Thermal hysteresis

Die temperature, T_J

130

150

170

20

170

190

14

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12 SPI Timing Requirements

at T_A= –40°C to +125°C, V_VM= 9 to 75 V (unless otherwise noted)

MIN NOM MAX UNIT

t_READY

t_CLK

SPI ready after enable

SCLK minimum period

SCLK minimum high time

SCLK minimum low time

SDI input data setup time

SDI input data hold time

SDO output data delay time

nSCS input setup time

nSCS input hold time

VM > UVLO, ENABLE = 3.3 V

1

ms

ns

100

50

20

30

t_CLKH

t_CLKL

t_{SU_SDI}

t_{H_SDI}

t_{D_SDO}

t_{SU_nSCS}

t_{H_nSCS}

t_{HI_nSCS}

t_{DIS_nSCS}

SCLK high to SDO valid

30

50

nSCS minimum high time before active low

nSCS disable time nSCS high to SDO high impedance

400

10

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13 Detailed Description

13.1 Overview

The DRV8353M family of devices are integrated 100-V gate drivers for three-phase motor drive applications.

These devices decrease system component count, cost, and complexity by integrating three independent half-

bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,

optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral

interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic

information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring

the most commonly used settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A

source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is

generated using a doubler charge-pump architecture that regulates the VCP output to V_VDRAIN+ 10.5-V. The

low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates

the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver

outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current

strength allowing for the gate driver to control the power MOSFET V_DSswitching speed. This allows for the

removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The

architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the

half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.

The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM

can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,

VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device

efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent

monitor reference.

The DRV8353 devices integrate three, bidirectional current-shunt amplifiers for monitoring the current level

through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier

can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility to adjust the

output bias point.

In addition to the high level of device integration, the DRV8353M family of devices provides a wide range of

integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive

undervoltage lockout (GDUV), V_DSovercurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and

overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information

available in the SPI registers on the SPI device version.

The DRV8353M family of devices are available in 0.5-mm pin pitch, QFN surface-mount package. The QFN size

is 6 × 6 mm for the 40-pin package.

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13.2 Functional Block Diagram

VM

VDRAIN

VM

VDRAIN

>10 …F

0.1 …F

VCP

HS

VCP

CPH

GHA

SHA

VCP

Charge

Pump

1 …F

VDRAIN

VGLS

LS

CPL

VGLS

DVDD

47 nF

GLA

SPA

VGLS

Linear

Regulator

Gate Driver

1 …F

DVDD

Linear

Regulator

VDRAIN

1 …F

VCP

HS

GHB

SHB

GND

Power Supplies

ENABLE

VGLS

LS

Digital

Core

GLB

SPB

INHA

INLA

INHB

INLB

INHC

INLC

Gate Driver

VDRAIN

VCP

HS

Smart Gate

Drive

GHC

SHC

Protection

Control

Inputs

VGLS

LS

GLC

SPC

MODE

Gate Driver

Fault Output

IDRIVE

VCC

PU

R

VDS

nFAULT

GAIN

VCC

0.1 …F

SPC

SNC

VREF

A_V

R_SENC

SOC

SOB

SOA

SPB

SNB

Output

Offset

Bias

R_SENB

SPA

SNA

AGND

R_SENA

Figure 13-1. Block Diagram for DRV8353HM

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VM

VDRAIN

VM

VDRAIN

>10 …F

0.1 …F

VCP

HS

VCP

CPH

GHA

SHA

VCP

Charge

Pump

1 …F

VDRAIN

VGLS

LS

CPL

VGLS

DVDD

47 nF

GLA

SPA

VGLS

Linear

Regulator

Gate Driver

1 …F

DVDD

Linear

Regulator

VDRAIN

1 …F

VCP

HS

GHB

SHB

GND

Power Supplies

ENABLE

VGLS

LS

Digital

Core

GLB

SPB

INHA

INLA

INHB

INLB

INHC

INLC

SDI

Gate Driver

Control

Inputs

VDRAIN

VCP

HS

Smart Gate

Drive

GHC

SHC

Protection

VGLS

LS

GLC

SPC

VCC

SPI

Gate Driver

Fault Output

R

PU

VCC

PU

SDO

R

SCLK

nFAULT

nSCS

VCC

0.1 …F

SPC

SNC

VREF

A_V

R_SENC

SOC

SOB

SOA

SPB

SNB

Output

Offset

Bias

R_SENB

SPA

SNA

AGND

R_SENA

Figure 13-2. Block Diagram for DRV8353SM

13.3 Feature Description

13.3.1 Three Phase Smart Gate Drivers

The DRV8353M family of devices integrates three, half-bridge gate drivers, each capable of driving high-side

and low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage

to the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle

support. The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-

bridge gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of

loads.

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The DRV8353M family of devices implement a smart gate-drive architecture which allows the user to

dynamically adjust the gate drive current without requiring external gate current limiting resistors. Additionally,

this architecture provides a variety of protection features for the external MOSFETs including automatic dead-

time insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.

13.3.1.1 PWM Control Modes

The DRV8353M family of devices provides four different PWM control modes to support various commutation

and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register

during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or

PWM_MODE change.

13.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)

In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The

corresponding INHx and INLx signals control the output state as listed in Table 13-1.

Table 13-1. 6x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

Hi-Z

H

0

1

0

1

0

1

L

H

L

H

L

Hi-Z

13.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)

In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is

used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx

pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 13-2.

Table 13-2. 3x PWM Mode Truth Table

INLx

INHx

GLx

GHx

SHx

Hi-Z

L

0

1

X

0

1

L

H

L

H

13.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)

In this mode, the DRV8353M family of devices uses 6-step block commutation tables that are stored internally.

This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple

controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-

bridges.

The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic

inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital

outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually

operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling

rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.

The INHC input controls the direction through the 6-step commutation table which is used to change the

direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the

INHC pin low if this feature is not required.

The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs

when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this

feature is not required.

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Table 13-3. Synchronous 1x PWM Mode

LOGIC AND HALL INPUTS

GATE-DRIVE OUTPUTS

INHC = 0

INHC = 1

PHASE A

PHASE B PHASE C

STATE

DESCRIPTION

INLA

INHB

INLB

INLA

INHB

INLB

GHA

GLA

GHB

GLB

GHC

GLC

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

!PWM

L

Stop

Align

L

H

L

H

Align

1

2

3

4

5

6

PWM

!PWM

L

H

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

!PWM

L

H

L

H

PWM

L

!PWM

L

H

L

H

PWM

!PWM

Table 13-4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)

LOGIC AND HALL INPUTS

GATE-DRIVE OUTPUTS

INHC = 0

INHC = 1

PHASE A

PHASE B PHASE C

STATE

DESCRIPTION

INLA

INHB

INLB

INLA

INHB

INLB

GHA

GLA

L

GHB

GLB

L

GHC

GLC

L

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

Stop

Align

L

H

L

H

L

Align

1

2

3

4

5

6

L

PWM

L

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

H

L

PWM

L

H

L

PWM

L

Figure 13-3 and Figure 13-4 show the different possible configurations in 1x PWM mode.

INHA

MCU_PWM

MCU_GPIO

PWM

INLA

INHB

INLB

INHC

INLC

STATE0

STATE1

STATE2

DIR

BLDC Motor

MCU_GPIO

nBRAKE

Figure 13-3. 1x PWM—Simple Controller

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INHA

INLA

INHB

INLB

INHC

INLC

MCU_PWM

PWM

H

STATE0

STATE1

STATE2

DIR

H

BLDC Motor

H

MCU_GPIO

nBRAKE

Figure 13-4. 1x PWM—Hall Sensor

13.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)

In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This

control mode allows for the external controller to bypass the internal dead-time handshake of the DRV8353M or

to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge.

These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches.

In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side

and low-side MOSFETs are turned on at the same time.

Table 13-5. Independent PWM Mode Truth Table

INLx

INHx

GLx

GHx

0

1

0

1

0

1

L

H

L

H

Because the high-side and low-side V_DSovercurrent monitors share the SHx sense line, using both of the

monitors is not possible if both the high-side and low-side gate drivers are being operated independently.

In this case, connect the SHx pin to the high-side driver and disable the V_DSovercurrent monitors as shown in

Figure 13-5.

Disable

+

V_DS

œ

VM

VDRAIN

VCP

GHx

Load

HS

INHx

SHx

VGLS

INLx

GLx

LS

Load

Gate Driver

Disable

SLx/SPx

+

V_DS

œ

Figure 13-5. Independent PWM High-Side and Low-Side Drivers

If the half-bridge is used to implement only a high-side or low-side driver, using the V_DSovercurrent monitors is

still possible. Connect the SHx pin as shown in Figure 13-6 or Figure 13-7. The unused gate driver and the

corresponding input can be left disconnected.

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+

V_DS

œ

VM

VDRAIN

VCP

HS

GHx

SHx

INHx

INLx

VGLS

LS

GLx

Load

Gate Driver

SLx/SPx

+

V_DS

œ

Figure 13-6. Single High-Side Driver

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+

V_DS

œ

VM

VDRAIN

VCP

HS

GHx

SHx

Load

INHx

INLx

VGLS

LS

GLx

Gate Driver

SLx/SPx

+

V_DS

œ

Figure 13-7. Single Low-Side Driver

13.3.1.2 Device Interface Modes

The DRV8353M family of devices support two different interface modes (SPI and hardware) to allow the end

application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing

the different versions to be pin to pin compatible. This allows for application designers to evaluate with one

interface version and potentially switch to another with minimal modifications to their design.

13.3.1.2.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that allows for an external controller to send and receive

data with the DRV835x. This allows for the external controller to configure device settings and read detailed fault

information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.

•

The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated

on SDI and SDO.

•

The SDI pin is the data input.

The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup

resistor.

•

The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

DRV835x.

For more information on the SPI, see the Section 13.5.1 section.

13.3.1.2.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,

MODE, and VDS. This allows for the application designer to configure the most commonly used device settings

by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement

for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT

pin.

•

The GAIN pin configures the current shunt amplifier gain.

The IDRIVE pin configures the gate drive current strength.

The MODE pin configures the PWM control mode.

The VDS pin configures the voltage threshold of the V_DSovercurrent monitors.

For more information on the hardware interface, see the Section 13.3.3 section.

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SCLK

SDI

SPI

Interface

VCC

R_PU

SDO

nSCS

Figure 13-8. SPI

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DVDD

R_GAIN

DVDD

GAIN

Hardware

Interface

DVDD

IDRIVE

MODE

VDS

DVDD

R_VDS

Figure 13-9. Hardware Interface

13.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations

The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and

VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET

gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep

a fixed output voltage of V_VDRAIN+ 10.5 V and supports an average output current of 25 mA. When V_VMis less

than 12 V, the charge pump operates in full doubler mode and generates V_VCP= 2 × V_VM– 1.5 V with respect to

V_VDRAINwhen unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven

MOSFET conditions.

The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to

act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required

between the CPH and CPL pins to act as the flying capacitor.

VDRAIN

1 …F

VCP

CPH

VM

Charge

Pump

Control

47 nF

CPL

Figure 13-10. Charge Pump Architecture

The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply

input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect

to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs

during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is

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monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a

X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.

Since the charge pump output is regulated to V_VDRAIN+ 10.5 V this allows for VM to be supplied either directly

from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate

driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an

externally available power supply. Figure 13-11 and Figure 13-12 show examples of the DRV8353M configured

in either single supply or dual supply configuration.

48-V

Power

Supply

VM

VDRAIN

DRV835x

Power

MOSFETs

Figure 13-11. Single Supply Example

48-V

Power

Supply

48-V to 15-V

DC/DC

VM

VDRAIN

DRV835x

Power

MOSFETs

Figure 13-12. Dual Supply Example

13.3.1.4 Smart Gate Drive Architecture

The DRV8353M gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and

low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.

Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external

power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between

efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE

which are detailed in the Section 13.3.1.4.1 section and Section 13.3.1.4.2 section. Figure 13-13 shows the high-

level functional block diagram of the gate driver.

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The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters

of the external power MOSFET used in the system and the desired rise and fall times (see the Section 14

section).

The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from

overvoltage conditions in the case of external short-circuit events on the MOSFET.

VCP

INHx

VDRAIN

Control

Inputs

INLx

GHx

SHx

Level

Shifters

150 kꢀ

+

^GSœ

V

VGLS

Digital

Core

GLx

Level

Shifters

150 kꢀ

SLx/SPx

+

^GSœ

V

Figure 13-13. Gate Driver Block Diagram

13.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control

The IDRIVE component implements adjustable gate-drive current to control the MOSFET V_DSslew rates. The

MOSFET V_DSslew rates are a critical factor for optimizing radiated emissions, energy and duration of diode

recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to

parasitics in the external half-bridge. IDRIVE operates on the principal that the MOSFET V_DSslew rates are

predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET Q_GDor

Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew

rate of the external power MOSFETs.

IDRIVE allows the DRV8353M family of devices to dynamically switch between gate drive currents either

through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices

provide 16 I_DRIVEsettings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface

devices provides 7 I_DRIVEsettings between the same ranges. The gate drive current setting is delivered to the

gate during the turnon and turnoff of the external power MOSFET for the t_DRIVEduration. After the MOSFET

turnon or turnoff, the gate driver switches to a smaller hold I_HOLDcurrent to improve the gate driver efficiency.

Additional details on the IDRIVE settings are described in the Section 13.6 section for the SPI devices and in the

Section 13.3.3 section for the hardware interface devices.

13.3.1.4.2 TDRIVE: MOSFET Gate Drive Control

The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion

through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.

The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time

between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross

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conduct and cause shoot-through. The DRV8353M family of devices use V_GSvoltage monitors to measure the

MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time

value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift

and variation in the MOSFET parameters. An additional digital dead time (t_DEAD) can be inserted and is

adjustable through the registers on SPI devices.

The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET

on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the high-

side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an

additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due

to the need to discharge the voltage present on the internal V_GSdetection circuit.

The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state

machine enables a strong pulldown I_STRONGcurrent on the opposite MOSFET gate whenever a MOSFET is

switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that

couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.

The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET

gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a

pair of V_GSgate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a

command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at

the end of the t_DRIVEperiod the V_GSvoltage has not reached the correct threshold the gate driver will report a

fault. To make sure that a false fault is not detected, a t_DRIVEtime should be selected that is longer than the time

required to charge or discharge the MOSFET gate. The t_DRIVEtime does not increase the PWM time and will

terminate if another PWM command is received while active. Additional details on the TDRIVE settings are

described in the Section 13.6 section for SPI devices and in the Section 13.3.3 section for hardware interface

devices.

Figure 13-14 shows an example of the TDRIVE state machine in operation.

V

INHx

V

INLx

V

GHx

t_DEAD

I_HOLD

t_DEAD

I

t

I

HOLD

DRIVE

STRONG

I

GHx

I

t

I

HOLD

DRIVE

V

GLx

t_DEAD

I_HOLD

I

t

I

HOLD

DRIVE

STRONG

I

HOLD

DRIVE

t

DRIVE

Figure 13-14. TDRIVE State Machine

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13.3.1.4.3 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to a detected output

change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,

and the delay through the analog gate drivers.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate

drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input

command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to

the overall propagation delay of the device.

13.3.1.4.4 MOSFET V_DSMonitors

The gate drivers implement adjustable V_DSvoltage monitors to detect overcurrent or short-circuit conditions on

the external power MOSFETs. When the monitored voltage is greater than the V_DStrip point (V_{VDS_OCP}) for

longer than the deglitch time (t_OCP), an overcurrent condition is detected and action is taken according to the

device V_DSfault mode.

The high-side V_DSmonitors measure the voltage between the VDRAIN and SHx pins. The low-side V_DSmonitors

measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to

the common ground point of the external half-bridges.

For the SPI devices, the low-side V_DSmonitor reference point can be changed between the SPx and SNx pins if

desired with the LS_REF register setting. This is only for the low-side V_DSmonitor. The high-side V_DSmonitor

stays between the VDRAIN and SHx pins.

The V_{VDS_OCP}threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V

on hardware interface devices. Additional information on the V_DSmonitor levels are described in the Section

13.6 section for SPI devices and in the Section 13.3.3 section hardware interface device.

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VDRAIN

+

V

+

V

^DSœ

V

VDS_OCP

GHx

SHx

GLx

+

^DSœ

+

^DSœ

V

VDS_OCP

SPx

0

1

R

SENSE

SNx

LS_REF

(SPI Only)

Figure 13-15. DRV8353M V_DSMonitors

13.3.1.4.5 VDRAIN Sense and Reference Pin

The DRV8353M family of devices provides a separate sense and reference pin for the common point of the high-

side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors

(VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.

The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge

pump reference stays with respect to the power MOSFET supply through voltage transient conditions.

Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the

power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can

be supplied from an efficient low voltage supply to increase the device efficiency.

13.3.2 DVDD Linear Voltage Regulator

A 5-V, 10-mA linear regulator is integrated into the DRV8353M family of devices and is available for use by

external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of

the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor

routed directly back to the adjacent DGND or GND ground pin.

The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator

functions like a constant-current source. The output voltage drops significantly with a current load greater than

10 mA.

VM

REF

+

œ

5 V, 10 mA

DVDD

1 …F

GND/

DGND

Figure 13-16. DVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.

P = V_VM- V_DVDDì I

(

)

DVDD

(1)

For example, at V_VM= 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 1.

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P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

(2)

13.3.3 Pin Diagrams

Figure 13-17 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.

DVDD

STATE

V_IH

RESISTANCE

Tied to DVDD

Tied to AGND

INPUT

Logic High

Logic Low

V_IL

100 kꢀ

Figure 13-17. Logic-Level Input Pin Structure

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Figure 13-18 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices.

The input can be set with an external resistor.

MODE

GAIN

DVDD

STATE

V_I4

RESISTANCE

Tied to DVDD

DVDD

Independent 40 V/V

+

50 kꢀ

œ

Hi-Z (>500 kΩ to

AGND)

1x PWM

3x PWM

6x PWM

20V/V

10 V/V

5 V/V

V_I3

V_I2

V_I1

+

84 kꢀ

47 kΩ ±5%

to AGND

œ

Tied to AGND

+

œ

Figure 13-18. Four Level Input Pin Structure

Figure 13-19 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.

The input can be set with an external resistor.

IDRIVE

1/2 A

VDS

Disabled

+

œ

STATE

V_I7

RESISTANCE

Tied to DVDD

700/1400 mA

450/900 mA

300/600 mA

150/300 mA

100/200 mA

50/100 mA

1 V

0.7 V

0.4 V

0.2 V

0.1 V

0.06 V

+

DVDD

œ

18 kꢀ 5%

to DVDD

V_I6

V_I5

V_I4

V_I3

V_I2

V_I1

+

75 kꢀ 5%

to DVDD

73 kꢀ

œ

Hi-Z (>500 kΩ

to AGND)

73 kꢀ

+

75 kꢀ 5%

to AGND

œ

18 kΩ ±5%

to AGND

+

Tied to AGND

œ

+

œ

Figure 13-19. Seven Level Input Pin Structure

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Figure 13-20 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output

requires an external pullup resistor to function correctly.

DVDD

R

PU

STATE

No Fault

Fault

STATUS

Inactive

Active

OUTPUT

Active

Inactive

Figure 13-20. Open-Drain Output Pin Structure

13.3.4 Low-Side Current-Shunt Amplifiers

The DRV8353M integrate three, high-performance low-side current-shunt amplifiers for current measurements

using low-side shunt resistors in the external half-bridges. Low-side current measurements are commonly used

to implement overcurrent protection, external torque control, or brushless DC commutation with the external

controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one amplifier

can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such as

programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin

(VREF).

13.3.4.1 Bidirectional Current Sense Operation

The SOx pin on the DRV8353M outputs an analog voltage equal to the voltage across the SPx and SNx pins

multiplied by the gain setting (G_CSA). The gain setting is adjustable between four different levels (5 V/V, 10 V/V,

20 V/V, and 40 V/V). Use Equation 1 to calculate the current through the shunt resistor.

V_VREF

- V_SOx

2

I =

G_CSAì R_SENSE

(3)

R2

R3

R4

R5

R6

SOx

REF

I

R1

SPx

SNx

V

CC

œ

R

SENSE

V

+

0.1 …F

R2

R3

R4

R5

½

+

œ

Figure 13-21. Bidirectional Current-Sense Configuration

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SO (V)

V

REF

V

/ 2

VREF

V

LINEAR

SP œ SN (V)

Figure 13-22. Bidirectional Current-Sense Output

I

SP

SO

R

A_V

SN

SO

VREF

SP œ SN

œ0.3 V

œI × R

V

VREF

œ 0.25 V

V

SO(rangeœ)

V

SO(off)max

/ 2

V

,

OFF

0 V

V

VREF

V

DRIFT

V

SO(off)min

V

SO(range+)

I × R

0.3 V

0.25 V

0 V

Figure 13-23. Bidirectional Current Sense Regions

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13.3.4.2 Unidirectional Current Sense Operation (SPI only)

On the DRV8353M SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case the shunt

amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across the SPx and

SNx pins multiplied by the gain setting (G_CSA). Use Equation 1 to calculate the current through the shunt resistor.

V_VREF- V_SOx

G_CSAì R_SENSE

I =

(4)

R2

R3

R4

R5

R6

SOx

I

R1

SPx

SNx

œ

R

SENSE

+

V

CC

R2

R3

R4

R5

V

REF

+

0.1 …F

œ

Figure 13-24. Unidirectional Current-Sense Configuration

SO (V)

V

REF

V

œ 0.3 V

VREF

V

LINEAR

SP œ SN (V)

Figure 13-25. Unidirectional Current-Sense Output

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I

SP

SN

SO

R

A_V

V

REF

V

œ 0.25 V

VREF

V

SO(off)max

SP œ SN

V

,

OFF

0 V

V

œ 0.3 V

VREF

V

DRIFT

V

SO(off)min

V

SO(range)

I × R

0.3 V

0.25 V

0 V

Figure 13-26. Unidirectional Current-Sense Regions

13.3.4.3 Amplifier Calibration Modes

To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the

SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration

setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be

done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during

the switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration

mode is shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration

mode.

R_F

R_OUT

SOx

R_SP

!CAL

SP

SN

-

R_SENSE

R_SN

VREF

+

CAL

+

R_G

-

Figure 13-27. Amplifier Manual Calibration

In addition to the manual calibration method provided on the SPI devices versions, the DRV8353M family of

devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize

the amplifier input offset after power up and during run time to account for temperature and device variation.

Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The

power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.

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50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses

the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to

minimize the amplifier input offset. After this the amplifiers are ready for normal operation.

For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL

register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to

rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain

setting in order to improve the accuracy of the calibration routine.

13.3.4.4 MOSFET V_DSSense Mode (SPI Only)

The current-sense amplifiers on the DRV8353M SPI devices can be configured to amplify the voltage across the

external low-side MOSFET V_DS. This allows for the external controller to measure the voltage drop across the

MOSFET R_DS(on)without the shunt resistor and then calculate the half-bridge current level.

To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to

the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier

inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side

MOSFET as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the

negative reference for the low-side V_DSmonitor is automatically set to SNx, regardless of the state of the

LS_REF bit state. This setting is implemented to prevent disabling of the low-side V_DSmonitor.

If the system operates in MOSFET V_DSsensing mode, route the SHx and SNx pins with Kelvin connections

across the drain and source of the external low-side MOSFETs.

VDRAIN

High-Side

VCP

V

Monitor

DS

+

V

^DSœ

GHx

SHx

(SPI only)

CSA_FET = 0

LS_REF = 0

VGLS

Low-Side

V

Monitor

DS

+

V

^DSœ

GLx

0

1

10 kꢀ

SPx

SOx

A_V

R

SEN

SNx

GND

Figure 13-28. Resistor Sense Configuration

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VDRAIN

High-Side

VCP

V

DS

Monitor

+

V

^DSœ

GHx

SHx

(SPI only)

CSA_FET = 1

LS_REF = X

VGLS

Low-Side

V

Monitor

DS

+

V

GLx

SPx

^DSœ

0

1

10 kꢀ

SOx

A_V

SNx

GND

Figure 13-29. V_DSSense Configuration

When operating in MOSFET V_DSsense mode, the amplifier is enabled at the end of the t_DRIVEtime. At this time,

the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side MOSFET

receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.

13.3.5 Gate Driver Protective Circuits

The DRV8353M family of devices are fully protected against VM undervoltage, charge pump and low-side

regulator undervoltage, MOSFET V_DSovercurrent, gate driver shorts, and overtemperature events.

13.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)

If at any time the input supply voltage on the VM pin falls below the V_{VM_UV}threshold or voltage on VDRAIN pin

falls below the V_{VDR_UV}, all of the external MOSFETs are disabled, the charge pump is disabled, and the

nFAULT pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices.

Normal operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage

condition is removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset

pulse (t_RST).

VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage

conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on

VM and VDRAIN pin voltages.

13.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)

If at any time the voltage on the VCP pin (charge pump) falls below the V_{VCP_UV}threshold or voltage on the

VGLS pin falls below the V_{VGLS_UV}threshold, all of the external MOSFETs are disabled and the nFAULT pin is

driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation

continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed.

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The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). Setting the

DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the

GDUV protection is always enabled.

13.3.5.3 MOSFET V_DSOvercurrent Protection (VDS_OCP)

A MOSFET overcurrent event is sensed by monitoring the V_DSvoltage drop across the external MOSFET

R_DS(on). If the voltage across an enabled MOSFET exceeds the V_{VDS_OCP}threshold for longer than the t_{OCP_DEG}

deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware

interface devices, the V_{VDS_OCP}threshold is set with the VDS pin, the t_{OCP_DEG}is fixed at 4 µs, and the

OCP_MODE is configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI

devices, the V_{VDS_OCP}threshold is set through the VDS_LVL SPI register, the t_{OCP_DEG}is set through the

OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: V_DSlatched shutdown,

V_DSautomatic retry, V_DSreport only, and V_DSdisabled.

The MOSFET V_DSovercurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be

disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising

edge on the PWM inputs will clear an existing overcurrent fault.

Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent

response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only

effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a

VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.

13.3.5.3.1 V_DSLatched Shutdown (OCP_MODE = 00b)

After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation continues (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is

removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

13.3.5.3.2 V_DSAutomatic Retry (OCP_MODE = 01b)

After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal

operation continues automatically (gate driver operation and the nFAULT pin is released) after the t_RETRYtime

elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the t_RETRYperiod expires.

13.3.5.3.3 V_DSReport Only (OCP_MODE = 10b)

No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving

the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI

registers. The gate drivers continue to operate as normal. The external controller manages the overcurrent

condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is

removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

13.3.5.3.4 V_DSDisabled (OCP_MODE = 11b)

No action occurs after a VDS_OCP event in this mode.

13.3.5.4 V_SENSEOvercurrent Protection (SEN_OCP)

Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor

with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the V_{SEN_OCP}

threshold for longer than the t_{OCP_DEG}deglitch time, a SEN_OCP event is recognized and action is done

according to the OCP_MODE. On hardware interface devices, the V_SENSEthreshold is fixed at 1 V, t_{OCP_DEG}is

fixed at 4 µs, and the OCP_MODE for V_SENSEis fixed for 8-ms automatic retry. On SPI devices, the V_SENSE

threshold is set through the SEN_LVL SPI register, the t_{OCP_DEG}is set through the OCP_DEG SPI register, and

the OCP_MODE bit can operate in four different modes: V_SENSElatched shutdown, V_SENSEautomatic retry,

V_SENSEreport only, and V_SENSEdisabled.

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The V_SENSEovercurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on

SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the

PWM inputs will clear an existing overcurrent fault.

Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent

response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only

effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a

SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.

13.3.5.4.1 V_SENSELatched Shutdown (OCP_MODE = 00b)

After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation continues (gate driver

operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults

command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

13.3.5.4.2 V_SENSEAutomatic Retry (OCP_MODE = 01b)

After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.

The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal

operation continues automatically (gate driver operation and the nFAULT pin is released) after the t_RETRYtime

elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the t_RETRYperiod expires.

13.3.5.4.3 V_SENSEReport Only (OCP_MODE = 10b)

No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving

the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers

continue to operate. The external controller manages the overcurrent condition by acting appropriately. The

reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is

issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST).

13.3.5.4.4 V_SENSEDisabled (OCP_MODE = 11b or DIS_SEN = 1b)

No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the

VDS_OCP bit by using the DIS_SEN SPI register.

13.3.5.5 Gate Driver Fault (GDF)

The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or

decrease after the t_DRIVEtime, a gate driver fault is detected. This fault may be encountered if the GHx or GLx

pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the

selected I_DRIVEsetting is not sufficient to turn on the external MOSFET within the t_DRIVEperiod. After a gate drive

fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,

GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation continues (gate driver

operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults

command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST). On SPI devices, setting the

DIS_GDF_UVLO bit high disables this protection feature.

Gate driver faults can indicate that the selected I_DRIVEor t_DRIVEsettings are too low to slew the external

MOSFET in the desired time. Increasing either the I_DRIVEor t_DRIVEsetting can resolve gate driver faults in these

cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported

because of the MOSFET gate not turning on.

13.3.5.6 Overcurrent Soft Shutdown (OCP Soft)

In the case of a MOSFET V_DSor V_SENSEovercurrent fault the driver uses a special shutdown sequence to

protect the driver and MOSFETs from large voltage switching transients. These large voltage transients can be

created when rapidly switching off the external MOSFETs when a large drain to source current is present, such

as during an overcurrent event.

To mitigate this issue, the DRV8353M family of devices reduce the I_DRIVENpull down current setting for both the

high-side and low-side gate drivers during the MOSFET turn off in response to the fault event. If the programmed

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I_DRIVENvalue is less than 1100 mA, the IDRIVEN value is set to the minimum I_DRIVENsetting. If the programmed

I_DRIVENvalue is greater than or equal to 1100mA, the I_DRIVENvalue is reduced by seven code settings.

13.3.5.7 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OTW bit is set in the registers of

SPI devices. The device does no additional action and continues to function. When the die temperature falls

below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be

configured to report on the nFAULT pin and FAULT bit by setting the OTW_REP bit to 1 through the SPI

registers.

13.3.5.8 Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTSD), all the external MOSFETs are

disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits

are latched high. Normal operation continues (gate driver operation and the nFAULT pin is released) when the

overtemperature condition is removed. The TSD bit stays latched high indicating that a thermal event occurred

until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (t_RST). This

protection feature cannot be disabled.

13.3.5.9 Fault Response Table

Table 13-6. Fault Action and Response

FAULT

CONDITION

CONFIGURATION

REPORT

GATE DRIVER

RECOVERY

VM Undervoltage

(VM_UV)

Automatic:

V_VM> V_{VM_UV}

V_VM< V_{VM_UV}

—

nFAULT

Hi-Z

VDRAIN Undervoltage

(VDR_UV)

Automatic:

V_VM> V_{VDR_UV}

V_VDRAIN< V_{VDR_UV}

—

nFAULT

Hi-Z

DIS_GDUV = 0b

DIS_GDUV = 1b

DIS_GDUV = 0b

DIS_GDUV = 1b

nFAULT

None

Hi-Z

Active

Hi-Z

Charge Pump Undervoltage

(VCP_UV)

Automatic:

V_VCP> V_{VCP_UV}

V_VCP< V_{VCP_UV}

nFAULT

None

VGLS Regulator Undervoltage

(VGLS_UV)

Automatic:

V_VGLS> V_{VGLS_UV}

V_VGLS< V_{VGLS_UV}

Active

Latched:

CLR_FLT, ENABLE Pulse

OCP_MODE = 00b

OCP_MODE = 01b

nFAULT

Hi-Z

Retry:

t_RETRY

V_DSOvercurrent

(VDS_OCP)

V_DS> V_{VDS_OCP}

OCP_MODE = 10b

OCP_MODE = 11b

nFAULT

None

Active

No action

Latched:

CLR_FLT, ENABLE Pulse

OCP_MODE = 00b

nFAULT

Hi-Z

Retry:

t_RETRY

OCP_MODE = 01b

OCP_MODE = 10b

nFAULT

None

Hi-Z

V_SENSEOvercurrent

(SEN_OCP)

V_SP> V_{SEN_OCP}

Active

No action

OCP_MODE = 11b or

DIS_SEN = 1b

Latched:

CLR_FLT, ENABLE Pulse

DIS_GDF = 0b

DIS_GDF = 1b

OTW_REP = 1b

OTW_REP = 0b

—

nFAULT

None

Hi-Z

Active

Hi-Z

Gate Driver Fault

(GDF)

V_GSStuck > t_DRIVE

No action

Automatic:

T_J< T_OTW– T_HYS

nFAULT

None

Thermal Warning

(OTW)

T_J> T_OTW

No action

Thermal Shutdown

(OTSD)

Automatic:

T_J< T_OTSD– T_HYS

T_J> T_OTSD

nFAULT

13.4 Device Functional Modes

13.4.1 Gate Driver Functional Modes

13.4.1.1 Sleep Mode

The ENABLE pin manages the state of the DRV8353M family of devices. When the ENABLE pin is low, the

device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are

disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense

amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their

default values. The t_SLEEPtime must elapse after a falling edge on the ENABLE pin before the device goes to

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sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The t_WAKEtime

must elapse before the device is ready for inputs.

In sleep mode and when V_VM< V_UVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are

pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an

internal resistor.

13.4.1.2 Operating Mode

When the ENABLE pin is high and V_VM> V_UVLO, the device goes to operating mode. The t_WAKEtime must

elapse before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD

regulator, and SPI bus are active

13.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)

In the case of device latched faults, the DRV8353M family of devices goes to a partial shutdown state to help

protect the external power MOSFETs and system.

When the fault condition has been removed the device can reenter the operating state by either setting the

CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The

ENABLE reset pulse (t_RST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the

sequence should fall with the t_RSTtime window or else the device will start the complete shutdown sequence.

The reset pulse has no effect on any of the regulators, device settings, or other functional blocks

13.5 Programming

This section applies only to the DRV8353M SPI devices.

13.5.1 SPI Communication

13.5.1.1 SPI

On DRV8353M SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out

diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data

(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word

consists of 11-bit register data. The first 5 bits are don’t care bits.

A valid frame must meet the following conditions:

•

The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

The nSCS pin should be pulled high for at least 400 ns between words.

When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is set

Hi-Z.

•

Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.

The most significant bit (MSB) is shifted in and out first.

A full 16 SCLK cycles must occur for transaction to be valid.

If the data word sent to the SDI pin is not 16 bits, a frame error occurs and the data word is ignored.

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 5 bit command data.

•

The SDO pin is an open-drain output and requires an external pullup resistor.

13.5.1.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit B15)

4 address bits, A (bits B14 through B11)

11 data bits, D (bits B11 through B0)

Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read

command.

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The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data

currently in the register being accessed.

Table 13-7. SDI Input Data Word Format

R/W

B15

W0

ADDRESS

DATA

B14

A3

B13

A2

B12

A1

B11

A0

B10

D10

B9

D9

B8

D8

B7

D7

B6

D6

B5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

D5

Table 13-8. SDO Output Data Word Format

DON'T CARE BITS

DATA

B15

X

B14

X

B13

X

B12

X

B11

X

B10

D10

B9

D9

B8

D8

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

nSCS

SCLK

SDI

X

Z

MSB

LSB

X

Z

MSB

SDO

Capture

Point

Propagate

Point

Figure 13-30. SPI Slave Timing Diagram

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13.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. The status registers are read-only

registers

Complex bit access types are encoded to fit into small table cells. Table 13-10 shows the codes that are used for

access types in this section.

Table 13-10. Status Registers Access Type Codes

Access Type Code

Description

Read Type

R

Read

Reset or Default Value

-n

Value after reset or the default value

13.6.1.1 Fault Status Register 1 (address = 0x00h)

The fault status register 1 is shown in Figure 13-31 and described in Table 13-11.

Register access type: Read only

Figure 13-31. Fault Status Register 1

10

9

8

7

6

5

4

3

2

1

0

FAULT

R-0b

VDS_OCP

R-0b

GDF

R-0b

UVLO

R-0b

OTSD

R-0b

VDS_HA

R-0b

VDS_LA

R-0b

VDS_HB

R-0b

VDS_LB

R-0b

VDS_HC

R-0b

VDS_LC

R-0b

Table 13-11. Fault Status Register 1 Field Descriptions

Bit

Field

Type

Default

Description

10

FAULT

R

0b

Logic OR of FAULT status registers. Mirrors nFAULT pin.

Indicates VDS monitor overcurrent fault condition

Indicates gate drive fault condition

9

8

7

6

5

4

3

2

1

0

VDS_OCP

GDF

R

0b

UVLO

Indicates undervoltage lockout fault condition

OTSD

Indicates overtemperature shutdown

VDS_HA

VDS_LA

VDS_HB

VDS_LB

VDS_HC

VDS_LC

Indicates VDS overcurrent fault on the A high-side MOSFET

Indicates VDS overcurrent fault on the A low-side MOSFET

Indicates VDS overcurrent fault on the B high-side MOSFET

Indicates VDS overcurrent fault on the B low-side MOSFET

Indicates VDS overcurrent fault on the C high-side MOSFET

Indicates VDS overcurrent fault on the C low-side MOSFET

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13.6.1.2 Fault Status Register 2 (address = 0x01h)

The fault status register 2 is shown in Figure 13-32 and described in Table 13-12.

Register access type: Read only

Figure 13-32. Fault Status Register 2

10

9

8

7

6

5

4

3

2

1

0

SA_OC

R-0b

SB_OC

R-0b

SC_OC

R-0b

OTW

R-0b

GDUV

R-0b

VGS_HA

R-0b

VGS_LA

R-0b

VGS_HB

R-0b

VGS_LB

R-0b

VGS_HC

R-0b

VGS_LC

R-0b

Table 13-12. Fault Status Register 2 Field Descriptions

Bit

Field

Type

Default

Description

10

SA_OC

SB_OC

SC_OC

OTW

R

0b

Indicates overcurrent on phase A sense amplifier

Indicates overcurrent on phase B sense amplifier

Indicates overcurrent on phase C sense amplifier

Indicates overtemperature warning

9

8

7

6

R

0b

GDUV

Indicates VCP charge pump and/or VGLS undervoltage fault

condition

5

4

3

2

1

0

VGS_HA

VGS_LA

VGS_HB

VGS_LB

VGS_HC

VGS_LC

R

0b

Indicates gate drive fault on the A high-side MOSFET

Indicates gate drive fault on the A low-side MOSFET

Indicates gate drive fault on the B high-side MOSFET

Indicates gate drive fault on the B low-side MOSFET

Indicates gate drive fault on the C high-side MOSFET

Indicates gate drive fault on the C low-side MOSFET

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13.6.2 Control Registers

The control registers are used to configure the device. The control registers are read and write capable

Complex bit access types are encoded to fit into small table cells. Table 13-13 shows the codes that are used for

access types in this section.

Table 13-13. Control Registers Access Type Codes

Access Type Code

Description

Read Type

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default value

13.6.2.1 Driver Control Register (address = 0x02h)

The driver control register is shown in Figure 13-33 and described in Table 13-14.

Register access type: Read/Write

Figure 13-33. Driver Control Register

10

9

8

7

6

5

4

3

2

1

0

DIS

_GDUV

DIS

_GDF

OTW

_REP

1PWM

_COM

1PWM

_DIR

CLR

_FLT

OCP _ACT

R/W-0b

PWM_MODE

R/W-00b

COAST

R/W-0b

BRAKE

R/W-0b

Table 13-14. Driver Control Field Descriptions

Bit

Field

Type

Default

Description

10

OCP_ACT

R/W

0b

0b = Associated half-bridge is shutdown in response to

VDS_OCP and SEN_OCP

1b = All three half-bridges are shutdown in response to

VDS_OCP and SEN_OCP

9

8

DIS_GDUV

DIS_GDF

R/W

0b

0b =VCP and VGLS undervoltage lockout fault is enabled

1b = VCP and VGLS undervoltage lockout fault is disabled

0b

0b = Gate drive fault is enabled

1b = Gate drive fault is disabled

7

OTW_REP

PWM_MODE

0b

0b = OTW is not reported on nFAULT or the FAULT bit

1b = OTW is reported on nFAULT and the FAULT bit

6-5

00b

00b = 6x PWM Mode

01b = 3x PWM mode

10b = 1x PWM mode

11b = Independent PWM mode

4

1PWM_COM

R/W

0b

0b = 1x PWM mode uses synchronous rectification

1b = 1x PWM mode uses asynchronous rectification

3

2

1

1PWM_DIR

COAST

R/W

0b

In 1x PWM mode this bit is ORed with the INHC (DIR) input

Write a 1 to this bit to put all MOSFETs in the Hi-Z state

BRAKE

Write a 1 to this bit to turn on all three low-side MOSFETs

This bit is ORed with the INLC (BRAKE) input in 1x PWM mode.

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Table 13-14. Driver Control Field Descriptions (continued)

Bit

Field

Type

Default

Description

0

CLR_FLT

R/W

0b

Write a 1 to this bit to clear latched fault bits.

This bit automatically resets after being writen.

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13.6.2.2 Gate Drive HS Register (address = 0x03h)

The gate drive HS register is shown in Figure 13-34 and described in Table 13-15.

Register access type: Read/Write

Figure 13-34. Gate Drive HS Register

10

9

8

7

6

5

4

3

2

1

0

LOCK

IDRIVEP_HS

R/W-1111b

IDRIVEn_HS

R/W-1111b

R/W-011b

Table 13-15. Gate Drive HS Field Descriptions

Bit

Field

Type

Default

Description

10-8

LOCK

R/W

011b

Write 110b to lock the settings by ignoring further register writes

except to these bits and address 0x02h bits 0-2.

Writing any sequence other than 110b has no effect when

unlocked.

Write 011b to this register to unlock all registers.

Writing any sequence other than 011b has no effect when

locked.

7-4

IDRIVEP_HS

R/W

1111b

0000b = 50 mA

0001b = 50 mA

0010b = 100 mA

0011b = 150 mA

0100b = 300 mA

0101b = 350 mA

0110b = 400 mA

0111b = 450 mA

1000b = 550 mA

1001b = 600 mA

1010b = 650 mA

1011b = 700 mA

1100b = 850 mA

1101b = 900 mA

1110b = 950 mA

1111b = 1000 mA

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Table 13-15. Gate Drive HS Field Descriptions (continued)

Bit

Field

Type

Default

Description

3-0

IDRIVEN_HS

R/W

1111b

0000b = 100 mA

0001b = 100 mA

0010b = 200 mA

0011b = 300 mA

0100b = 600 mA

0101b = 700 mA

0110b = 800 mA

0111b = 900 mA

1000b = 1100 mA

1001b = 1200 mA

1010b = 1300 mA

1011b = 1400 mA

1100b = 1700 mA

1101b = 1800 mA

1110b = 1900 mA

1111b = 2000 mA

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13.6.2.3 Gate Drive LS Register (address = 0x04h)

The gate drive LS register is shown in Figure 13-35 and described in Table 13-16.

Register access type: Read/Write

Figure 13-35. Gate Drive LS Register

10

9

8

7

6

5

4

3

2

1

0

CBC

TDRIVE

R/W-11b

IDRIVEP_LS

R/W-1111b

IDRIVEN_LS

R/W-1111b

R/W-1b

Table 13-16. Gate Drive LS Register Field Descriptions

Bit

Field

Type

Default

Description

10

CBC

R/W

1b

Active only when OCP_MODE = 01b

0b = For VDS_OCP and SEN_OCP, the fault is cleared after

t_RETRY

1b = For VDS_OCP and SEN_OCP, the fault is cleared when

a new PWM input is given or after t_RETRY

9-8

7-4

TDRIVE

R/W

11b

00b = 500-ns peak gate-current drive time

01b = 1000-ns peak gate-current drive time

10b = 2000-ns peak gate-current drive time

11b = 4000-ns peak gate-current drive time

IDRIVEP_LS

1111b

0000b = 50 mA

0001b = 50 mA

0010b = 100 mA

0011b = 150 mA

0100b = 300 mA

0101b = 350 mA

0110b = 400 mA

0111b = 450 mA

1000b = 550 mA

1001b = 600 mA

1010b = 650 mA

1011b = 700 mA

1100b = 850 mA

1101b = 900 mA

1110b = 950 mA

1111b = 1000 mA

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Table 13-16. Gate Drive LS Register Field Descriptions (continued)

Bit

Field

Type

Default

Description

3-0

IDRIVEN_LS

R/W

1111b

0000b = 100 mA

0001b = 100 mA

0010b = 200 mA

0011b = 300 mA

0100b = 600 mA

0101b = 700 mA

0110b = 800 mA

0111b = 900 mA

1000b = 1100 mA

1001b = 1200 mA

1010b = 1300 mA

1011b = 1400 mA

1100b = 1700 mA

1101b = 1800 mA

1110b = 1900 mA

1111b = 2000 mA

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13.6.2.4 OCP Control Register (address = 0x05h)

The OCP control register is shown in Figure 13-36 and described in Table 13-17.

Register access type: Read/Write

Figure 13-36. OCP Control Register

10

9

8

7

6

5

4

3

2

1

0

TRETRY

R/W-0b

DEAD_TIME

R/W-01b

OCP_MODE

R/W-01b

OCP_DEG

R/W-01b

VDS_LVL

R/W-1101b

Table 13-17. OCP Control Field Descriptions

Bit

Field

Type

Default

Description

10

TRETRY

R/W

0b

0b = VDS_OCP and SEN_OCP retry time is 8 ms

1b = VDS_OCP and SEN_OCP retry time is 50 µs

9-8

7-6

5-4

3-0

DEAD_TIME

R/W

01b

00b = 50-ns dead time

01b = 100-ns dead time

10b = 200-ns dead time

11b = 400-ns dead time

OCP_MODE

OCP_DEG

VDS_LVL

01b

00b = Overcurrent causes a latched fault

01b = Overcurrent causes an automatic retrying fault

10b = Overcurrent is report only but no action is taken

11b = Overcurrent is not reported and no action is taken

10b

00b = Overcurrent deglitch of 1 µs

01b = Overcurrent deglitch of 2 µs

10b = Overcurrent deglitch of 4 µs

11b = Overcurrent deglitch of 8 µs

1001b

0000b = 0.06 V

0001b = 0.07 V

0010b = 0.08 V

0011b = 0.09 V

0100b = 0.1 V

0101b = 0.2 V

0110b = 0.3 V

0111b = 0.4 V

1000b = 0.5 V

1001b = 0.6 V

1010b = 0.7 V

1011b = 0.8 V

1100b = 0.9 V

1101b = 1 V

1110b = 1.5 V

1111b = 2 V

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13.6.2.5 CSA Control Register (address = 0x06h)

The CSA control register is shown in Figure 13-37 and described in Table 13-18.

Register access type: Read/Write.

Figure 13-37. CSA Control Register

10

9

8

7

6

5

4

3

2

1

0

CSA

_FET

VREF

_DIV

LS

_REF

CSA

_GAIN

DIS

_SEN

CSA

_CAL_A

CSA

_CAL_B

CSA

_CAL_C

SEN

_LVL

R/W-0b

R/W-1b

R/W-0b

R/W-10b

R/W-0b

R/W-11b

Table 13-18. CSA Control Field Descriptions

Bit

Field

Type

Default

Description

10

CSA_FET

VREF_DIV

LS_REF

R/W

0b

0b = Sense amplifier positive input is SPx

1b = Sense amplifier positive input is SHx (also automatically

sets the LS_REF bit to 1)

9

8

R/W

1b

0b

0b = Sense amplifier reference voltage is VREF (unidirectional

mode)

1b = Sense amplifier reference voltage is VREF divided by 2

0b = VDS_OCP for the low-side MOSFET is measured

across SHx to SPx

1b = VDS_OCP for the low-side MOSFET is measured across

SHx to SNx

7-6

CSA_GAIN

R/W

10b

00b = 5-V/V shunt amplifier gain

01b = 10-V/V shunt amplifier gain

10b = 20-V/V shunt amplifier gain

11b = 40-V/V shunt amplifier gain

5

4

DIS_SEN

R/W

0b

11b

0b = Sense overcurrent fault is enabled

1b = Sense overcurrent fault is disabled

CSA_CAL_A

CSA_CAL_B

CSA_CAL_C

SEN_LVL

0b = Normal sense amplifier A operation

1b = Short inputs to sense amplifier A for offset calibration

3

0b = Normal sense amplifier B operation

1b = Short inputs to sense amplifier B for offset calibration

2

0b = Normal sense amplifier C operation

1b = Short inputs to sense amplifier C for offset calibration

1-0

00b = Sense OCP 0.25 V

01b = Sense OCP 0.5 V

10b = Sense OCP 0.75 V

11b = Sense OCP 1 V

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13.6.2.6 Driver Configuration Register (address = 0x07h)

The driver configuration register is shown in Figure 13-38 and described in Table 13-19.

Register access type: Read/Write

Figure 13-38. Driver Configuration Register

10

9

8

7

6

5

4

3

2

1

0

CAL

_MODE

Reserved

R/W-000 0000 000b

R/W-0b

Table 13-19. Driver Configuration Field Descriptions

Bit

Field

Type

Default

Description

10-1

Reserved

R/W

000 0000

000b

Reserved

0

CAL_MODE

R/W

0b

0b = Amplifier calibration operates in manual mode

1b = Amplifier calibration uses internal auto calibration routine

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14 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

14.1 Application Information

The DRV8353M family of devices are primarily used in three-phase brushless DC motor control applications.

The design procedures in the Section 14.2 section highlight how to use and configure the DRV8353M family of

devices.

14.2 Typical Application

14.2.1 Primary Application

The DRV8353M is shown being used for a single supply, three-phase BLDC motor drive with individual half-

bridge current sense in this application example.

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1 …F

1

2

30

29

28

27

26

25

24

23

22

21

CPL

nSCS

SCLK

SDI

47 nF

CPH

VM

3.3V

1 kꢀ

3

3.3V

10 kꢀ

0.1 …F

1 …F

4

VDRAIN

VCP

GHA

SHA

GLA

SPA

SNA

SDO

5

nFAULT

AGND

VREF

SOA

Thermal

Pad

6

GHA

SHA

GLA

SPA

SNA

3.3V

1 …F

7

8

9

SOB

10

SOC

VM

C_BULK

VM

C_BULK

C_BYP

GHA

GHB

SHB

GHC

SHC

SHA

MOTA

MOTB

MOTC

GLA

SPA

GLB

SPB

GLC

SPC

R

SENC

SENA

SENB

SNA

SNB

SNC

Figure 14-1. Primary Application Schematic

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14.2.1.1 Design Requirements

Table 14-1 lists the example input parameters for the system design.

Table 14-1. Design Parameters

EXAMPLE DESIGN PARAMETER

Power supply voltage

REFERENCE

EXAMPLE VALUE

48 V

V_VM, V_VDRAIN, V_VIN

MOSFET part number

MOSFET

Q_g

CSD19535KCS

MOSFET total gate charge

MOSFET gate to drain charge

Target output rise time

78 nC (typical) at V_VGS= 10 V

13 nC (typical)

100 to 300 ns

50 to 150 ns

45 kHz

Q_gd

t_r

Target output fall time

t_f

PWM frequency

ƒ_PWM

V_VCC

I_VCC

I_max

Buck regulator output voltage

Buck regulator output current

Maximum motor current

ADC reference voltage

3.3 V

100 mA

100 A

V_VREF

I_SENSE

I_RMS

P_SENSE

T_A

3.3 V

Winding sense current range

Motor RMS current

–40 A to +40 A

28.3 A

Sense resistor power rating

System ambient temperature

3 W

–20°C to +60°C

14.2.1.2 Detailed Design Procedure

Table 14-2 lists the recommended values of the external components for the gate driver.

Table 14-2. DRV8353M Gate-Driver External Components

COMPONENTS

C_VM1

PIN 1

PIN 2

RECOMMENDED

X5R or X7R, 0.1-µF, VM-rated capacitor

≥ 10 µF, VM-rated capacitor

X5R or X7R, 1-µF, 16-V capacitor

X5R or X7R, 47-nF, VDRAIN-rated capacitor

X5R or X7R, 1-µF, 6.3-V capacitor

Pullup resistor

VM

GND

C_VM2

VM

GND

C_VCP

VCP

VM

C_VGLS

VGLS

CPH

GND

C_SW

CPL

C_DVDD

R_nFAULT

R_SDO

DVDD

VCC⁽¹⁾

IDRIVE

VDS

DGND

nFAULT

SDO

Pullup resistor

R_IDRIVE

R_VDS

R_MODE

R_GAIN

GND or DVDD

GND or DGND

SNA and GND

SNB and GND

SNC and GND

DRV8353M hardware interface

Optional capacitor rated for VREF

Sense shunt resistor

MODE

GAIN

VREF

SPA

C_VREF

R_ASENSE

R_BSENSE

R_CSENSE

SPB

Sense shunt resistor

SPC

Sense shunt resistor

(1) VCC is not a pin on the DRV8353M family of devices, but a VCC supply voltage pullup is required for the open-drain output nFAULT

and SDO. These pins can also be pulled up to DVDD.

14.2.1.2.1 External MOSFET Support

The DRV833M family of devices MOSFET support is based on the MOSFET gate charge, VCP charge-pump

capacity, VGLS regulator capacity, and output PWM switching frequency. For a quick calculation of MOSFET

driving capacity, use Equation 5 and Equation 6 for three phase BLDC motor applications.

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Trapezoidal 120° Commutation: I_VCP/VGLS> Q_g× ƒ_PWM

Sinusoidal 180° Commutation: I_VCP/VGLS> 3 × Q_g× ƒ_PWM

(5)

(6)

where

•

ƒ_PWMis the maximum desired PWM switching frequency.

Q_gis the MOSFET total gate charge

I_VCP/VGLSis the charge pump or low-side regulator capacity, dependent on the VM pin voltage.

The MOSFET multiplier based on the commutation control method, may vary based on implementation.

14.2.1.2.1.1 MOSFET Example

If a system is using V_VM= 48 V (I_VCP= 25 mA) and a maximum PWM switching frequency of 45 kHz, then the

VCP charge-pump and VGLS regulator can support MOSFETs using trapezoidal commutation with a Q_g< 556

nC, and MOSFETs using sinusoidal commutation with a Q_g< 185 nC.

14.2.1.2.2 IDRIVE Configuration

The gate drive current strength, I_DRIVE, is selected based on the gate-to-drain charge of the external MOSFETs

and the target rise and fall times at the outputs. If I_DRIVEis selected to be too low for a given MOSFET, then the

MOSFET may not turn on completely within the t_DRIVEtime and a gate drive fault may be asserted. Additionally,

slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in

system with the required external MOSFETs and motor to determine the best possible setting for any application.

The I_DRIVEPand I_DRIVENcurrent for both the low-side and high-side MOSFETs are independently adjustable on

SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are

selected at the same time on the IDRIVE pin.

For MOSFETs with a known gate-to-drain charge Q_gd, desired rise time (t_r), and a desired fall time (t_f), use

Equation 7 and Equation 8 to calculate the value of I_DRIVEPand I_DRIVEN(respectively).

Q_gd

I_DRIVEP

>

t_r

(7)

(8)

Q_gd

t_f

I_DRIVEN

>

14.2.1.2.2.1 IDRIVE Example

Use Equation 9 and Equation 10 to calculate the value of I_DRIVEP1and I_DRIVEP2(respectively) for a gate to drain

charge of 13 nC and a rise time from 100 to 300 ns.

13 nC

I_DRIVEP1

=

= 130 mA

= 43 mA

100 ns

(9)

13 nC

I_DRIVEP2

=

300 ns

(10)

Select a value for I_DRIVEPthat is between 43 mA and 130 mA. For this example, the value of I_DRIVEPwas

selected as 100-mA source.

Use Equation 11 and Equation 12 to calculate the value of I_DRIVEN1and I_DRIVEN2(respectively) for a gate to drain

charge of 13 nC and a fall time from 50 to 150 ns.

13 nC

I_DRIVEN1

=

= 260 mA

50 ns

(11)

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13 nC

I_DRIVEN2

=

= 87 mA

150 ns

(12)

Select a value for I_DRIVENthat is between 87 mA and 260 mA. For this example, the value of I_DRIVENwas

selected as 200-mA sink.

14.2.1.2.3 V_DSOvercurrent Monitor Configuration

The V_DSmonitors are configured based on the worst-case motor current and the R_DS(on)of the external

MOSFETs as shown in Equation 13.

V_{DS_OCP}> I_maxì R_DS(on)max

(13)

14.2.1.2.3.1 V_DSOvercurrent Example

The goal of this example is to set the V_DSmonitor to trip at a current greater than 75 A. According to the

CSD19535KCS 100 V N-Channel NexFET^™Power MOSFET data sheet, the R_DS(on)value is 2.2 times higher at

175°C, and the maximum R_DS(on)value at a V_GSof 10 V is 3.6 mΩ at T_A= 25°C. From these values, the

approximate worst-case value of R_DS(on)is 2.2 × 3.6 mΩ = 7.92 mΩ.

Using Equation 14 with a value of 7.92 mΩ for R_DS(on)and a worst-case motor current of 75 A, Equation 14

shows the calculated desired value of the V_DSovercurrent monitors.

V_{DS _ OCP}> 75 A ì 7.92 mW

V_{DS _ OCP}> 0.594 V

(14)

For this example, the value of V_{DS_OCP}was selected as 0.6 V.

The SPI devices allow for adjustment of the deglitch time for the V_DSovercurrent monitor. The deglitch time can

be set to 1 µs, 2 µs, 4 µs, or 8 µs.

14.2.1.2.4 Sense-Amplifier Bidirectional Configuration

The sense amplifier gain on the DRV8353M and sense resistor value are selected based on the target current

range, VREF reference voltage, sense-resistor power rating, and operating temperature range. In bidirectional

operation of the sense amplifier, the dynamic range at the output is approximately calculated as shown in

Equation 15.

V_VREF

V_O= V

- 0.25 V -

(

)

VREF

2

(15)

Use Equation 16 to calculate the approximate value of the selected sense resistor with V_Ocalculated using

Equation 15.

V_O

2

R =

P_SENSE> I_RMSì R

A_Vì I

(16)

From Equation 15 and Equation 16, select a target gain setting based on the power rating of the target sense

resistor.

14.2.1.2.4.1 Sense-Amplifier Example

In this system example, the value of VREF voltage is 3.3 V with a sense current from –40 to +40 A. The linear

range of the SOx output is 0.25 V to V_VREF– 0.25 V (from the V_LINEARspecification). The differential range of the

sense amplifier input is –0.3 to +0.3 V (V_DIFF).

3.3 V

V = 3.3 V - 0.25 V -

= 1.4 V

(

)

O

2

(17)

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1.4 V

A_Vì 40 A

R =

2 W > 28.3²ì R ç R < 2.5 mW

(18)

(19)

1.4 V

A_Vì 40 A

2.5 mW >

ç A_V> 14

Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be

less than 2.5 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was

selected as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and I_max

40 A does not violate the differential range specification of the sense amplifier input (V_SPxD).

=

14.2.1.2.5 Single Supply Power Dissipation

Design care must be taken to make sure that the thermal ratings of the DRV8353M are not violated during

normal operation of the device. The is especially critical in higher voltage and higher ambient operation

applications where power dissipation or the device ambient temperature are increased.

To determine the temperature of the device in single supply operation, first the power internal power dissipation

must be calculated. The internal power dissipation has four primary components:

•

VCP charge pump power dissipation (P_VCP

VGLS low-side regulator power dissipation (P_VGLS

VM device nominal power dissipation (P_VM

VIN buck regulator power dissipation (P_BUCK

)

The values of P_VCPand P_VGLScan be approximated by referring to Section 14.2.1.2.1 to first determine I_VCPand

I_VGLSand then referring to Equation 20 and Equation 21.

P_VCP= I_VCP× (V_VM+ V_VDRAIN

)

(20)

(21)

P_VGLS= I_VGLS× V_VM

The value of P_VMcan be calculated by referring to the data sheet parameter for I_VMcurrent and Equation 22.

P_VM= I_VM× V_VM

(22)

(23)

P_BUCK= (P_O/ η) - P_O

where

P_O= V_VCC× I_VCC

•

The value of P_BUCKcan be calculated with the buck output voltage (V_VCC), buck output current (I_VCC), and by

referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.

The total power dissipation is then calculated by summing the four components as shown in Equation 24.

P

_tot= P_VCP+ P_VGLS+ P_VM+ P_BUCK

(24)

(25)

Lastly, the device junction temperature can be estimate by referring to Section 10 and Equation 25.

T_Jmax = T_Amax + (R_θJA× P_tot)

The information in Section 10 is based off of a standardized test metric for package and PCB thermal

dissipation. The actual values may vary based on the actual PCB design used in the application.

14.2.1.2.6 Single Supply Power Dissipation Example

In this application example the device is configured for single supply operation. This configuration requires only

one power supply for the DRV8353M but comes at the tradeoff of increased internal power dissipation. The

junction temperature is estimated in the example below.

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Use Equation 26 to calculate the value of I_VCPand I_VGLSfor a MOSFET gate charge of 78 nC, all 3 high-side and

3 low-side MOSFETs switching, and a switching frequency of 45 kHz.

I_VCP/VGLS= 78 nC × 3 × 45 kHz = 10.5 mA

(26)

Use Equation 27, Equation 28, Equation 29, Equation 30, and Equation 31 to calculate the value of P_totfor V_VM

=

V_VDRAIN= V_VIN= 48 V, I_VM= 9.5 mA, I_VCP= 10.5 mA, I_VGLS= 10.5 mA, V_VCC= 3.3 V, I_VCC= 100 mA, and η = 86

%.

P_VCP= 10.5 mA × (48 V + 48 V) = 1 W

P_VGLS= 10.5 mA × 48 V = 0.5 W

(27)

(28)

(29)

(30)

(31)

P_VM= 9.5 mA × 48 V = 0.5 W

P_BUCK= [(3.3 V × 100 mA) / 0.86] – (3.3 V × 100 mA) = 0.054 W

P_tot= 1 W + 0.5 W + 0.5 W + 0.054 = 2.054 W

Lastly, to estimate the device junction temperature during operation, use Equation 32 to calculate the value of

T_Jmax for T_Amax = 60°C, R_θJA= 26.6°C/W for the RGZ package, and P_tot= 2.054 W. Again, please note that the

R_θJAis highly dependent on the PCB design used in the actual application and should be verified. For more

information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics

application report.

T_Jmax = 60°C + (26.6°C/W × 2.054 W) = 115°C

(32)

As shown in this example, the device is within its operational limits, but is operating almost to its maximum

operational junction temperature. Design care should be taken in the single supply configuration to correctly

manage the power dissipation of the device.

14.2.1.3 Application Curves

Figure 14-2. Gate Driver Operation 30% Duty Cycle Figure 14-3. Gate Driver Operation 90% Duty Cycle

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Figure 14-4. IDRIVE Minimum Setting Positive

Figure 14-5. IDRIVE Minimum Setting Negative

Current

Figure 14-6. IDRIVE 300-mA and 600-mA Setting

Positive Current

Figure 14-7. IDRIVE 300-mA and 600-mA Setting

Negative Current

Figure 14-8. IDRIVE Maximum Setting Positive

Current

Figure 14-9. IDRIVE Maximum Setting Negative

Current

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Figure 14-10. FOC Motor Commutation

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15 Power Supply Recommendations

The DRV8353M family of devices are designed to operate from an input voltage supply (VM) range between 9 V

and 75 V. A 0.1-µF ceramic capacitor rated for VM must be placed as near to the device as possible. In addition,

a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the

external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs

and should be sized according to the application requirements.

15.1 Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is usually

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The

amount of local capacitance depends on a variety of factors including:

•

The highest current required by the motor system

The power supply's type, capacitance, and ability to source current

The amount of parasitic inductance between the power supply and motor system

The acceptable supply voltage ripple

Type of motor (brushed DC, brushless DC, stepper)

The motor startup and braking methods

The inductance between the power supply and motor drive system will limit the rate current can change from the

power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or

dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

stays stable and high current can be quickly supplied.

The data sheet provides a recommended minimum value, but system level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 15-1. Motor Drive Supply Parasitics Example

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16 Layout

16.1 Layout Guidelines

Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1

µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the

GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be

electrolytic. This capacitance must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk

capacitance should be placed such that it minimizes the length of any high current paths through the external

MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB

layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for

VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and

VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or

X7R.

Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type

X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the

GND/DGND pin.

The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a

significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the

common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND.

Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These

recommendations allow for more accurate V_DSsensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of

the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx

pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the

low-side MOSFET source back to the SPx/SLx pins.

66

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16.2 Layout Example

S

G

D

G

S

24

23

22

21

20

19

18

17

16

15

14

13

37

38

39

40

41

42

43

44

45

46

47

48

SOB

SOC

SNC

SPC

GLC

SHC

GHC

GHB

SHB

GLB

SPB

SNB

INLB

INHC

INLC

DVDD

DGND

SW

D

G

S

Thermal Pad

VIN

VCC

BST

RCL

RT/SD

FB

VOUT

S

G

D

S

G

D

G

S

Figure 16-1. Layout Example

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17 Device and Documentation Support

17.1 Device Support

17.1.1 Device Nomenclature

17.2 Documentation Support

17.2.1 Related Documentation

For related documentation, refer to:

•

Texas Instruments, DRV8353Rx-EVM User’s Guide user's guide

Texas Instruments, DRV8353Rx-EVM GUI User’s Guide

Texas Instruments, DRV8353Rx-EVM InstaSPIN^™Software Quick Start Guide

Texas Instruments, DRV8350x-EVM User’s Guide user's guide

Texas Instruments, DRV8350x-EVM GUI User’s Guide user's guide

Texas Instruments, DRV8350x-EVM Sensorless Software User's Guide user's guide

Texas Instruments, DRV8350x-EVM Sensored Software User's Guide user's guide

Texas Instruments, LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet

Texas Instruments, CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet

Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report

Texas Instruments, Motor Drive Protection with TI Smart Gate Drive TI TechNote

Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote

Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote

Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor

Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor

Texas Instruments, Industrial Motor Drive Solution Guide

Texas Instruments, Layout Guidelines for Switching Power Supplies application report

Texas Instruments, QFN/SON PCB Attachment application report

Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430^™application report

Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report

17.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

17.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

17.5 Trademarks

NexFET^™, InstaSPIN^™, and MSP430^™are trademarks of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

17.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

68

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17.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

18 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RTA0040B

A

6.1

5.9

B

PIN 1 INDEX AREA

6.1

5.9

0.8 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 4.5

4.15±0.1

(0.2) TYP

11

20

36X 0.5

10

21

SYMM

41

2X

4.5

1

30

0.28

40X

PIN1 IDENTIFICATION

(OPTIONAL)

0.16

31

40

0.1

C A B

C

SYMM

0.5

0.3

40X

0.05

4219112/A 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

RTA0040B

PLASTIC QUAD FLATPACK- NO LEAD

2X (5.8)

2X (4.5)

(

4.15)

40

31

40X (0.6)

40X (0.22)

1

30

36X (0.5)

SYMM

41

2X 2X

(4.5) (5.8)

2X

(0.685)

2X

(1.14)

(R0.05) TYP

10

21

12X (Ø0.2) VIA

TYP

11

20

2X (1.14)

2X (0.685)

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219112/A 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

RTA0040B

PLASTIC QUAD FLATPACK- NO LEAD

2X (5.8)

2X (4.5)

9X ( 1.17)

40

31

40X (0.6)

40X (0.22)

1

30

41

36X (0.5)

SYMM

2X 2X

(4.5) (5.8)

2X

(1.37)

(R0.05) TYP

10

21

EXPOSED

METAL

11

20

2X (1.37)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

71% PRINTED COVERAGE BY AREA

SCALE: 15X

4219112/A 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8353HM
厂家：	TEXAS INSTRUMENTS
描述：	DRV8353M 100-V Three-Phase Smart Gate Driver 栅
文件：	总76页 (文件大小：3152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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