DRV8353RHRGZR [TI]
具有降压稳压器和电流分流放大器的最大 102V 三相智能栅极驱动器 | RGZ | 48 | -40 to 125;
| 型号： | DRV8353RHRGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有降压稳压器和电流分流放大器的最大 102V 三相智能栅极驱动器 | RGZ | 48 | -40 to 125 放大器 栅极驱动 驱动器 稳压器 |
| 文件： | 总98页 (文件大小：5137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
DRV835x 100V 三相智能栅极驱动器
1 特性
3 说明
1
•
9V 至 100V 三半桥栅极驱动器
DRV835x 系列器件均为高度集成的栅极驱动器，适用
于三相无刷直流 (BLDC) 电机 应用标准。这些 应用 包
括 BLDC 电机的场定向控制 (FOC)、正弦电流控制和
梯形电流控制。该器件型号提供了可选的集成式分流放
大器以支持不同的电机控制方案，还提供了降压稳压
器，以为栅极驱动器或外部控制器供电。
–
–
可选的集成降压稳压器
可选的三个低侧电流分流放大器
•
智能栅极驱动架构
–
–
–
–
–
可调转换率控制，可实现优异的 EMI 性能
GS 握手和最小死区时间插入，可避免发生击穿
V
50mA 至 1A 峰值拉电流
100mA 至 2A 峰值灌电流
通过强下拉能力减小 dV/dt
DRV835x 通过采用智能栅极驱动 (SGD) 架构减少了
MOSFET 压摆率控制和保护电路通常所需要的外部组
件数量。SGD 架构还可优化死区时间以防止击穿问
题，在通过 MOSFET 压摆率控制技术降低电磁干扰
(EMI) 方面带来了灵活性，并可通过 VGS 监控器防止
栅极短路问题。强大的栅极下拉电路有助于防止不必要
的 dV/dt 寄生栅极开启事件。
•
•
•
•
集成栅极驱动器电源
–
–
高侧倍增电荷泵可实现 100% PWM 占空比控制
低侧线性稳压器
集成 LM5008A 降压稳压器
–
–
6V 至 95V 工作电压范围
该系列器件支持各种 PWM 控制模式（6x、3x、1x 和
独立模式），可简化与外部控制器的连接。这些模式可
减少电机驱动器 PWM 控制信号所需的控制器输出数
量。该系列器件还包括 1x PWM 模式，因此可通过内
部阻塞换向表轻松对 BLDC 电机进行传感器式梯形控
制。
2.5V 至 75V、350mA 输出能力
集成三个电流分流放大器
–
–
可调增益（5、10、20、40 V/V）
双向或单向支持
6x、3x、1x 和独立 PWM 模式
支持 120° 有传感器运行
–
器件信息(1)
•
•
•
提供 SPI 或硬件接口
器件型号
DRV8350
封装
WQFN (32)
封装尺寸（标称值）
5.00mm × 5.00mm
7.00mm × 7.00mm
6.00mm × 6.00mm
7.00mm × 7.00mm
低功耗睡眠模式（VVM = 48V 时为 20µA）
集成式保护 特性
DRV8350R
DRV8353
VQFN (48)
WQFN (40)
VQFN (48)
–
–
–
–
–
–
–
VM 欠压锁定 (UVLO)
栅极驱动电源欠压 (GDUV)
MOSFET VDS 过流保护 (OCP)
MOSFET 击穿保护
DRV8353R
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
栅极驱动器故障 (GDF)
简化原理图
热警告和热关断 (OTW/OTSD)
故障状态指示器 (nFAULT)
9 to 75 V
7 to 100 V
Drain
Sense
DRV835x
2 应用
PWM
Three-Phase
Smart Gate Driver
SPI or H/W
•
•
•
•
•
•
三相无刷直流 (BLDC) 电机模块
M
Gate Drive
风扇、风机和泵
nFAULT
Current Sense
350 mA
Protection
Current
Sense
电动自行车、电动踏板车和电动汽车
电动和园艺工具、割草机
无人机、机器人和遥控玩具
工厂自动化和纺织机
3x Shunt Amplifiers
Buck Regulator
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDY6
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
目录
8.6 Register Maps......................................................... 56
Application and Implementation ........................ 65
9.1 Application Information............................................ 65
9.2 Typical Application ................................................. 65
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications....................................................... 10
7.1 Absolute Maximum Ratings .................................... 10
7.2 ESD Ratings .......................................................... 11
7.3 Recommended Operating Conditions..................... 11
7.4 Thermal Information................................................ 11
7.5 Electrical Characteristics......................................... 12
7.6 SPI Timing Requirements ....................................... 18
7.7 Typical Characteristics............................................ 19
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 30
8.4 Device Functional Modes........................................ 53
8.5 Programming........................................................... 54
9
10 Power Supply Recommendations ..................... 77
10.1 Bulk Capacitance Sizing ....................................... 77
11 Layout................................................................... 78
11.1 Layout Guidelines ................................................. 78
11.2 Layout Example .................................................... 79
12 器件和文档支持 ..................................................... 80
12.1 器件支持................................................................ 80
12.2 文档支持................................................................ 80
12.3 相关链接................................................................ 81
12.4 接收文档更新通知 ................................................. 81
12.5 社区资源................................................................ 81
12.6 商标....................................................................... 81
12.7 静电放电警告......................................................... 81
12.8 Glossary................................................................ 81
13 机械、封装和可订购信息....................................... 81
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (August 2018) to Revision A
Page
•
•
已更改 将文档状态更改为生产数据......................................................................................................................................... 1
已删除 从 DRV8350 和 DRV8353 器件中删除了仅供预览的标注 .......................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
5 Device Comparison Table
DEVICE
VARIANT
DRV8350H
DRV8350S
DRV8350RH
DRV8350RS
DRV8353H
DRV8353S
DRV8353RH
DRV8353RS
SHUNT AMPLIFIERS
BUCK REGULATOR
INTERFACE
Hardware (H)
SPI (S)
DRV8350
None
350 mA (R)
None
0
Hardware (H)
SPI (S)
DRV8350R
DRV8353
Hardware (H)
SPI (S)
3
Hardware (H)
SPI (S)
DRV8353R
350 mA (R)
6 Pin Configuration and Functions
DRV8350H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
DRV8350S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
CPH
VM
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
INLA
CPH
VM
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
INLA
INHA
INHA
VDRAIN
VCP
ENABLE
NC
VDRAIN
VCP
ENABLE
nSCS
SCLK
SDI
Thermal
Pad
Thermal
Pad
GHA
VDS
GHA
SHA
IDRIVE
MODE
nFAULT
SHA
GLA
GLA
SDO
SLA
SLA
nFAULT
Not to scale
Not to scale
Pin Functions—32-Pin DRV8350 Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350H
DRV8350S
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
1
1
PWR
PWR
PWR
I
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
32
29
22
32
29
22
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
DVDD
ENABLE
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used
to reset fault conditions.
GHA
GHB
GHC
GLA
GLB
5
5
O
O
O
O
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
12
13
7
12
13
7
10
10
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Copyright © 2018–2019, Texas Instruments Incorporated
3
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
Pin Functions—32-Pin DRV8350 Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350H
DRV8350S
GLC
15
30
19
23
25
27
24
26
28
18
21
17
—
—
—
—
6
15
30
—
23
25
27
24
26
28
—
—
17
21
20
19
18
6
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device primary ground. Connect to system ground.
GND
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
PWR
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
I
I
I
I
I
I
I
NC
nFAULT
nSCS
SCLK
SDI
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
I
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
SDO
SHA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
I
SHB
11
14
8
11
14
8
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
I
High-side source sense input. Connect to the high-side power MOSFET source.
SLA
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
9
9
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
16
4
16
4
I
Low-side source sense input. Connect to the low-side power MOSFET source.
VCP
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VDRAIN
VDS
3
3
I
I
20
31
—
31
VGLS
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
2
2
PWR
DRV8350RH RGZ Package
DRV8350RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
48-Pin VQFN With Exposed Thermal Pad
Top View
GND
VGLS
CPL
1
36
INHB
INLA
GND
VGLS
CPL
1
36
INHB
INLA
2
35
34
33
32
31
30
29
28
27
26
25
2
35
34
33
32
31
30
29
28
27
26
25
3
INHA
ENABLE
NC
3
INHA
ENABLE
nSCS
SCLK
SDI
CPH
VM
4
CPH
VM
4
5
5
VDRAIN
VCP
6
VDS
VDRAIN
VCP
6
Thermal
Pad
Thermal
Pad
7
IDRIVE
MODE
nFAULT
AGND
NC
7
GHA
SHA
8
GHA
SHA
8
SDO
9
9
nFAULT
AGND
NC
GLA
10
11
12
GLA
10
11
12
SLA
SLA
NC
NC
NC
NC
Not to scale
Not to scale
4
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Pin Functions—48-Pin DRV8350R Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350RH
DRV8350RS
AGND
BST
27
45
27
45
PWR
PWR
Device analog ground. Connect to system ground.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
PWR
PWR
DGND
DVDD
41
40
41
40
Device digital ground. Connect to system ground.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This
regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
33
33
I
FB
48
8
48
8
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device primary ground. Connect to system ground.
GHA
GHB
GHC
GLA
GLB
GLC
GND
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
O
17
18
10
15
20
1
17
18
10
15
20
1
O
O
O
O
O
PWR
30
34
36
38
35
37
39
29
12
13
22
23
24
25
26
32
28
—
46
47
—
—
—
9
—
34
36
38
35
37
39
—
12
13
22
23
24
25
26
—
28
32
46
47
31
30
29
9
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Current limit off time set input. Connect a resistor between RCL and GND.
I
I
I
I
I
I
I
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
nFAULT
nSCS
RCL
RT/SD
SCLK
SDI
OD
I
I
I
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
I
SDO
SHA
SHB
SHC
SLA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
I
I
16
19
11
14
21
42
16
19
11
14
21
42
I
I
SLB
I
SLC
SW
I
O
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCC
44
44
PWR
VCP
7
6
7
6
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
I
31
2
—
2
VGLS
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Copyright © 2018–2019, Texas Instruments Incorporated
5
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
Pin Functions—48-Pin DRV8350R Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350RH
DRV8350RS
VIN
VM
43
43
PWR
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
5
5
DRV8353H RTA Package
DRV8353S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
40-Pin WQFN With Exposed Thermal Pad
Top View
CPL
CPH
1
30
29
28
27
26
25
24
23
22
21
GAIN
VDS
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
nSCS
SCLK
SDI
2
VM
3
IDRIVE
MODE
nFAULT
AGND
VREF
SOA
VM
VDRAIN
VCP
4
VDRAIN
VCP
SDO
5
nFAULT
AGND
VREF
SOA
Thermal
Pad
Thermal
Pad
GHA
SHA
6
GHA
SHA
7
GLA
8
GLA
SPA
9
SOB
SPA
SOB
SNA
10
SOC
SNA
SOC
Not to scale
Not to scale
Pin Functions—40-Pin DRV8353 Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353H
DRV8353S
AGND
CPH
25
25
2
PWR
PWR
Device analog ground. Connect to system ground.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
2
1
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
1
PWR
PWR
I
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
DVDD
ENABLE
38
31
38
31
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
GAIN
GND
GHA
GHB
GHC
GLA
30
39
6
—
39
6
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
Device power ground. Connect to system ground.
PWR
O
O
O
O
O
O
I
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
15
16
8
15
16
8
GLB
13
18
28
32
34
36
13
18
—
32
34
36
GLC
IDRIVE
INHA
INHB
INHC
I
I
I
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
6
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Pin Functions—40-Pin DRV8353 Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353H
DRV8353S
INLA
INLB
INLC
MODE
nFAULT
nSCS
SCLK
SDI
33
35
37
27
26
—
—
—
—
7
33
35
37
—
26
30
29
28
27
7
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
I
I
I
OD
I
I
I
SDO
SHA
OD
I
I
SHB
14
17
10
11
20
23
22
21
14
17
10
11
20
23
22
21
SHC
SNA
I
I
SNB
I
SNC
SOA
SOB
SOC
I
O
O
O
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPA
SPB
SPC
9
9
I
I
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
12
19
12
19
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
VCP
5
4
5
4
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
I
29
40
—
40
VGLS
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
3
3
PWR
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
VREF
24
24
Copyright © 2018–2019, Texas Instruments Incorporated
7
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
DRV8353RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8353RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
GND
VGLS
CPL
1
36
INHB
INLA
GND
VGLS
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
INHB
2
35
34
33
32
31
30
29
28
27
26
25
2
INLA
3
INHA
ENABLE
nSCS
SCLK
SDI
3
INHA
CPH
4
CPH
4
ENABLE
GAIN
VM
5
VM
5
VDRAIN
VCP
6
VDRAIN
VCP
6
VDS
Thermal
Pad
Thermal
Pad
7
7
IDRIVE
MODE
nFAULT
AGND
VREF
SOA
GHA
SHA
8
SDO
GHA
SHA
8
9
nFAULT
AGND
VREF
SOA
9
GLA
10
11
12
GLA
10
11
12
SPA
SPA
SNA
SNA
Not to scale
Not to scale
Pin Functions—48-Pin DRV8353R Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353RH
DRV8353RS
AGND
BST
27
45
27
45
PWR
PWR
Device analog ground. Connect to system ground.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
PWR
PWR
DGND
DVDD
41
40
41
40
Device ground. Connect to system ground.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins.
This regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
33
33
I
FB
48
32
1
48
—
1
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GAIN
GND
GHA
GHB
GHC
GLA
I
PWR
Device power ground. Connect to system ground.
8
8
O
O
O
O
O
O
I
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
17
18
10
15
20
30
34
36
38
35
37
39
29
28
17
18
10
15
20
—
34
36
38
35
37
39
—
28
GLB
GLC
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
nFAULT
I
I
I
I
I
I
I
OD
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
8
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Pin Functions—48-Pin DRV8353R Devices (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353RH
DRV8353RS
nSCS
RCL
RT/SD
SCLK
SDI
—
46
47
—
—
—
9
32
46
47
31
30
29
9
I
Serial chip select. A logic low on this pin enables serial interface communication.
Current limit off time set input. Connect a resistor between RCL and GND.
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
I
I
I
I
SDO
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
OD
I
I
16
19
12
13
22
25
24
23
16
19
12
13
22
25
24
23
I
I
I
I
O
O
O
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPA
SPB
11
14
11
14
I
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPC
SW
21
42
44
21
42
44
I
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCC
PWR
VCP
7
6
7
6
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
31
2
—
2
I
VGLS
VIN
PWR
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
43
43
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
5
5
PWR
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
VREF
26
26
Copyright © 2018–2019, Texas Instruments Incorporated
9
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted)(1)
MIN
MAX
UNIT
GATE DRIVER
Power supply pin voltage (VM)
–0.3
–0.3
–0.3
0
80
V
V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
MOSFET drain sense pin voltage (VDRAIN)
MOSFET drain sense pin voltage slew rate (VDRAIN)
Charge pump pin voltage (CPH, VCP)
0.3
102
V
2
VVDRAIN + 16
VVDRAIN
18
V/µs
V
–0.3
–0.3
–0.3
–0.3
Charge-pump negative-switching pin voltage (CPL)
Low-side gate drive regulator pin voltage (VGLS)
Internal logic regulator pin voltage (DVDD)
V
V
5.75
V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,
VDS)
–0.3
5.75
V
Continuous high-side gate drive pin voltage (GHx)
Transient 200-ns high-side gate drive pin voltage (GHx)
High-side gate drive pin voltage with respect to SHx (GHx)
Continuous high-side source sense pin voltage (SHx)
Continuous high-side source sense pin voltage (SHx)
Transient 200-ns high-side source sense pin voltage (SHx)
Continuous low-side gate drive pin voltage (GLx)
Transient 200-ns low-side gate drive pin voltage (GLx)
Gate drive pin source current (GHx, GLx)
Gate drive pin sink current (GHx, GLx)
Continuous low-side source sense pin voltage (SLx)
Transient 200-ns low-side source sense pin voltage (SLx)
Continuous shunt amplifier input pin voltage (SNx, SPx)
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)
Reference input pin voltage (VREF)
–5(2)
–10
VVCP + 0.3
VVCP + 0.3
16
V
V
V
V
V
V
V
V
A
A
V
V
V
V
V
V
–0.3
–5(2)
–5(2)
–10
102
VVDRAIN + 5
VVDRAIN + 10
VVGLS + 0.3
VVGLS + 0.3
–1.0
–5.0
Internally limited Internally limited
Internally limited Internally limited
–1
–5
1
5
–1
1
5
–5
–0.3
–0.3
5.75
Shunt amplifier output pin voltage (SOx)
BUCK REGULATOR
VVREF + 0.3
Power supply pin voltage (VIN)
–0.3
–0.3
–0.3
–0.3
–1
100
114
14
V
V
V
V
V
V
V
Bootstrap pin voltage (BST)
Bootstrap pin voltage with respect to SW (BST)
Bootstrap pin voltage with respect to VCC (BST)
Switching node pin voltage (SW)
100
VVIN
14
Internal regulator pin voltage (VCC)
–0.3
–0.3
Input pin voltage (FB, RCL, RT/SD)
7
DRV835x
Ambient temperature, TA
–40
–40
–65
125
150
150
°C
°C
°C
Junction temperature, TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.
This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.
10
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 Recommended Operating Conditions
at TA = –40°C to +125°C (unless otherwise noted)
MIN
MAX
UNIT
GATE DRIVER
VVM
Gate driver power supply voltage (VM)
9
7
0
0
0
0
0
0
3
0
0
0
75
100
5.5
V
V
VVDRAIN
VI
Charge pump reference and drain voltage sense (VDRAIN)
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)
Applied PWM signal (INHx, INLx)
V
fPWM
200(1)
kHz
V/ns
mA
mA
mA
V
tSH
Switch-node slew rate range (SHx)
2
IGATE_HS
IGATE_LS
IDVDD
VVREF
ISO
High-side average gate-drive current (GHx)
Low-side average gate-drive current (GLx)
External load current (DVDD)
25(1)
25(1)
10(1)
5.5
Reference voltage input (VREF)
Shunt amplifier output current (SOx)
5
mA
V
VOD
Open drain pullup voltage (nFAULT, SDO)
Open drain output current (nFAULT, SDO)
5.5
IOD
5
mA
BUCK REGULATOR
VVIN
Power supply voltage (VIN)
6
95
V
DRV835x
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
(1) Power dissipation and thermal limits must be observed.
7.4 Thermal Information
DRV8350
RTV (WQFN)
32 PINS
29.2
DRV8353
RTA (WQFN)
40 PINS
26.1
DRV835xR
THERMAL METRIC(1)
RGZ (VQFN)
48 PINS
24.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.2
13.1
12.0
9.2
8.4
7.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
0.1
0.1
ψJB
9.2
8.4
7.1
RθJC(bot)
1.2
1.1
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
11
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
7.5 Electrical Characteristics
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM
VM operating supply current
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C
ENABLE = 0 V period to reset faults
VVM > VUVLO, ENABLE = 3.3 V to outputs ready
ENABLE = 0 V to device sleep mode
IDVDD = 0 to 10 mA
8.5
1.9
20
13
4
mA
mA
IVDRAIN
VDRAIN operating supply current
40
ISLEEP
Sleep mode supply current
µA
100
40
tRST
Reset pulse time
Turnon time
5
µs
ms
ms
V
tWAKE
tSLEEP
VDVDD
1
Turnoff time
1
DVDD regulator voltage
4.75
9
5
10.5
10
5.25
12
VVM = 15 V, IVCP = 0 to 25 mA
VVM = 12 V, IVCP = 0 to 20 mA
7.5
6
11.5
9.5
8.5
16
VCP operating voltage
with respect to VDRAIN
VVCP
V
V
VVM = 10 V, IVCP = 0 to 15 mA
8
VVM = 9 V, IVCP = 0 to 10 mA
5.5
13
10
8
7.5
14.5
11.5
9.5
8.5
VVM = 15 V, IVGLS = 0 to 25 mA
VVM = 12 V, IVGLS = 0 to 20 mA
12.5
10.5
9.5
VGLS operating voltage
with respect to GND
VVGLS
VVM = 10 V, IVGLS = 0 to 15 mA
VVM = 9 V, IVGLS = 0 to 10 mA
7
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0
0.8
5.5
V
V
1.5
100
mV
µA
µA
kΩ
ns
VVIN = 0 V
–5
5
IIH
VVIN = 5 V
50
100
200
70
RPD
tPD
To GND
INHx/INLx transition to GHx/GLx transition
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Pullup resistance
Tied to GND
0
1.9
3.1
5
V
V
VI2
47 kΩ ± 5% to tied GND
Hi-Z
VI3
V
VI4
Tied to DVDD
V
RPU
RPD
Internal pullup to DVDD
Internal pulldown to GND
50
84
kΩ
kΩ
Pulldown resistance
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1
VI2
VI3
VI4
VI5
VI6
VI7
RPU
RPD
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Input mode 5 voltage
Input mode 6 voltage
Input mode 7 voltage
Pullup resistance
Tied to GND
0
0.8
1.7
2.5
3.3
4.2
5
V
V
18 kΩ ± 5% tied to GND
75 kΩ ± 5% tied to GND
Hi-Z
V
V
75 kΩ ± 5% tied to DVDD
18 kΩ ± 5% tied to DVDD
Tied to DVDD
V
V
V
Internal pullup to DVDD
Internal pulldown to GND
73
kΩ
kΩ
Pulldown resistance
73
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL
IOZ
Output logic low voltage
IO = 5 mA
VO = 5 V
0.125
2
V
Output high impedance leakage
–2
µA
12
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVERS (GHx, GLx)
VVM = 15 V, IVCP = 0 to 25 mA
9
7.5
6
10.5
10
12
11.5
9.5
VVM = 12 , IVCP = 0 to 20 mA
VVM = 10 V, IVCP = 0 to 15 mA
VVM = 9 V, IVCP = 0 to 10 mA
VVM = 15 V, IVGLS = 0 to 25 mA
VVM = 12 V, IVGLS = 0 to 20 mA
VVM = 10 V, IVGLS = 0 to 15 mA
VVM = 9 V, IVGLS = 0 to 10 mA
DEAD_TIME = 00b
High-side gate drive voltage
with respect to SHx
VGSH
V
8
5.5
9.5
9
7.5
8.5
11
12.5
12
10.5
9
Low-side gate drive voltage
with respect to PGND
VGSL
V
7.5
6.5
10.5
9.5
8
50
DEAD_TIME = 01b
100
200
400
100
500
1000
2000
4000
4000
50
SPI Device
H/W Device
SPI Device
H/W Device
Gate drive
dead time
tDEAD
DEAD_TIME = 10b
ns
DEAD_TIME = 11b
TDRIVE = 00b
TDRIVE = 01b
TDRIVE = 10b
TDRIVE = 11b
Peak current
gate drive time
tDRIVE
ns
IDRIVEP_HS or IDRIVEP_LS = 0000b
IDRIVEP_HS or IDRIVEP_LS = 0001b
IDRIVEP_HS or IDRIVEP_LS = 0010b
IDRIVEP_HS or IDRIVEP_LS = 0011b
IDRIVEP_HS or IDRIVEP_LS = 0100b
IDRIVEP_HS or IDRIVEP_LS = 0101b
IDRIVEP_HS or IDRIVEP_LS = 0110b
IDRIVEP_HS or IDRIVEP_LS = 0111b
IDRIVEP_HS or IDRIVEP_LS = 1000b
IDRIVEP_HS or IDRIVEP_LS = 1001b
IDRIVEP_HS or IDRIVEP_LS = 1010b
IDRIVEP_HS or IDRIVEP_LS = 1011b
IDRIVEP_HS or IDRIVEP_LS = 1100b
IDRIVEP_HS or IDRIVEP_LS = 1101b
IDRIVEP_HS or IDRIVEP_LS = 1110b
IDRIVEP_HS or IDRIVEP_LS = 1111b
IDRIVE = Tied to GND
50
100
150
300
350
400
450
550
600
650
700
850
900
950
1000
50
SPI Device
Peak source
gate current
IDRIVEP
mA
IDRIVE = 18 kΩ ± 5% tied to GND
IDRIVE = 75 kΩ ± 5% tied to GND
IDRIVE = Hi-Z
100
150
300
450
700
1000
H/W Device
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
Copyright © 2018–2019, Texas Instruments Incorporated
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DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDRIVEN_HS or IDRIVEN_LS = 0000b
IDRIVEN_HS or IDRIVEN_LS = 0001b
IDRIVEN_HS or IDRIVEN_LS = 0010b
IDRIVEN_HS or IDRIVEN_LS = 0011b
IDRIVEN_HS or IDRIVEN_LS = 0100b
IDRIVEN_HS or IDRIVEN_LS = 0101b
IDRIVEN_HS or IDRIVEN_LS = 0110b
IDRIVEN_HS or IDRIVEN_LS = 0111b
IDRIVEN_HS or IDRIVEN_LS = 1000b
IDRIVEN_HS or IDRIVEN_LS = 1001b
IDRIVEN_HS or IDRIVEN_LS = 1010b
IDRIVEN_HS or IDRIVEN_LS = 1011b
IDRIVEN_HS or IDRIVEN_LS = 1100b
IDRIVEN_HS or IDRIVEN_LS = 1101b
IDRIVEN_HS or IDRIVEN_LS = 1110b
IDRIVEN_HS or IDRIVEN_LS = 1111b
IDRIVE = Tied to GND
MIN
TYP
100
100
200
300
600
700
800
900
1100
1200
1300
1400
1700
1800
1900
2000
100
200
300
600
900
1400
2000
50
MAX
UNIT
SPI Device
Peak sink
gate current
IDRIVEN
mA
IDRIVE = 18 kΩ ± 5% tied to GND
IDRIVE = 75 kΩ ± 5% tied to GND
IDRIVE = Hi-Z
H/W Device
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
Source current after tDRIVE
IHOLD
Gate holding current
mA
Sink current after tDRIVE
100
2
ISTRONG
ROFF
Gate strong pulldown current
Gate hold off resistor
GHx to SHx and GLx to SPx/SLx
GHx to SHx and GLx to SPx/SLx
A
150
kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b
4.85
9.7
5
10
5.15
10.3
20.6
41.2
5.15
10.3
20.6
41.2
CSA_GAIN = 01b
SPI Device
CSA_GAIN = 10b
19.4
38.8
4.85
9.7
20
CSA_GAIN = 11b
40
GCSA
Amplifier gain
V/V
GAIN = Tied to GND
5
GAIN = 47 kΩ ± 5% tied to GND
GAIN = Hi-Z
10
H/W Device
19.4
38.8
20
GAIN = Tied to DVDD
VO_STEP = 0.5 V, GCSA = 5 V/V
VO_STEP = 0.5 V, GCSA = 10 V/V
VO_STEP = 0.5 V, GVSA = 20 V/V
VO_STEP = 0.5 V, GCSA = 40 V/V
40
250
500
1000
2000
tSET
Settling time to ±1%
ns
VCOM
VDIFF
VOFF
Common mode input range
–0.15
–0.3
–3
0.15
0.3
3
V
V
Differential mode input range
Input offset error
VSP = VSN = 0 V
VSP = VSN = 0 V
mV
µV/°C
VDRIFT
Drift offset
10
VVREF
–
VLINEAR
SOx output voltage linear range
0.25
V
0.25
14
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVREF
–
VSP = VSN = 0 V, VREF_DIV = 0b
0.3
SPI Device
H/W Device
VVREF
/
2
VBIAS
SOx output voltage bias
VSP = VSN = 0 V, VREF_DIV = 1b
VSP = VSN = 0 V
V
VVREF
/
2
IBIAS
SPx/SNx input bias current
SOx output slew rate
VREF input current
250
2.5
µA
VSLEW
IVREF
60-pF load
10
1.5
10
1
V/µs
mA
VVREF = 5 V
DRV835x: 60-pF load
DRV835xR: 60-pF load
MHz
MHz
UGB
Unity gain bandwidth
PROTECTION CIRCUITS
DRV835x: VM falling, UVLO report
DRV835x: VM rising, UVLO recovery
DRV835xR: VM falling, UVLO report
DRV835xR: VM rising, UVLO recovery
Rising to falling threshold
8.0
8.2
8.0
8.2
8.3
8.5
8.3
8.5
200
10
8.8
9.0
8.6
8.8
VVM_UV
VM undervoltage lockout
V
VVM_UVH
tVM_UVD
VM undervoltage hysteresis
mV
µs
VM undervoltage deglitch time
VM falling, UVLO report
DRV835x: VDRAIN falling, UVLO report
DRV835x: VDRAIN rising, UVLO recovery
DRV835xR: VDRAIN falling, UVLO report
DRV835xR: VDRAIN rising, UVLO recovery
Rising to falling threshold
6.1
6.3
6.1
6.3
6.4
6.6
6.4
6.6
200
10
6.8
7.0
6.7
6.9
VVDR_UV
VDRAIN undervoltage lockout
V
VVDR_UVH
tVDR_UVD
VDRAIN undervoltage hysteresis
VDRAIN undervoltage deglitch time
mV
µs
VDRAIN falling, UVLO report
VDRAIN
+ 5
VVCP_UV
VCP charge pump undervoltage lockout
VCP falling, GDUV report
VGLS falling, GDUV report
V
V
VGLS low-side regulator undervoltage
lockout
VVGLS_UV
4.25
Positive clamping voltage
Negative clamping voltage
12.5
13.5
–0.7
16
VGS_CLAMP
High-side gate clamp
V
Copyright © 2018–2019, Texas Instruments Incorporated
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DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.041
0.051
0.061
0.071
0.081
0.048
0.056
0.064
0.072
0.085
0.18
TYP
0.06
0.07
0.08
0.09
0.1
0.06
0.07
0.08
0.09
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.5
2
MAX
0.072
0.084
0.096
0.108
0.115
0.072
0.084
0.096
0.108
0.115
0.22
UNIT
DRV835x: VDS_LVL = 0000b
DRV835x: VDS_LVL = 0001b
DRV835x: VDS_LVL = 0010b
DRV835x: VDS_LVL = 0011b
DRV835x: VDS_LVL = 0100b
DRV835xR: VDS_LVL = 0000b
DRV835xR: VDS_LVL = 0001b
DRV835xR: VDS_LVL = 0010b
DRV835xR: VDS_LVL = 0011b
DRV835xR: VDS_LVL = 0100b
VDS_LVL = 0101b
SPI Device
V
VDS_LVL = 0110b
0.27
0.33
VDS_LVL = 0111b
0.36
0.44
VDS_LVL = 1000b
0.45
0.55
VDS_LVL = 1001b
0.54
0.66
VDS overcurrent
trip voltage
VVDS_OCP
VDS_LVL = 1010b
0.63
0.77
VDS_LVL = 1011b
0.72
0.88
VDS_LVL = 1100b
0.81
0.99
VDS_LVL = 1101b
0.9
1.1
VDS_LVL = 1110b
1.35
1.65
VDS_LVL = 1111b
1.8
2.2
DRV835x: VDS = Tied to GND
DRV835x: VDS = 18 kΩ ± 5% tied to GND
DRV835xR: VDS = Tied to GND
DRV835xR: VDS = 18 kΩ ± 5% tied to GND
VDS = 75 kΩ ± 5% tied to GND
VDS = Hi-Z
0.041
0.081
0.048
0.085
0.18
0.06
0.1
0.06
0.1
0.2
0.4
0.7
1
0.072
0.115
0.072
0.115
0.22
H/W Device
V
0.36
0.44
VDS = 75 kΩ ± 5% tied to DVDD
VDS = 18 kΩ ± 5% tied to DVDD
VDS = Tied to DVDD
0.63
0.77
0.9
1.1
Disabled
1
OCP_DEG = 00b
OCP_DEG = 01b
2
SPI Device
H/W Device
SPI Device
VDS and VSENSE
overcurrent deglitch time
tOCP_DEG
OCP_DEG = 10b
4
µs
OCP_DEG = 11b
8
4
SEN_LVL = 00b
SEN_LVL = 01b
SEN_LVL = 10b
SEN_LVL = 11b
0.25
0.5
0.75
1
VSENSE overcurrent trip
voltage
VSEN_OCP
V
H/W Device
SPI Device
H/W Device
1
TRETRY = 0b
TRETRY = 1b
8
ms
μs
tRETRY
Overcurrent retry time
50
8
ms
°C
°C
°C
TOTW
TOTSD
THYS
Thermal warning temperature
Thermal shutdown temperature
Thermal hysteresis
Die temperature, TJ
Die temperature, TJ
Die temperature, TJ
130
150
150
170
20
170
190
BUCK REGULATOR VCC
VVCC_REG VCC regulator voltage
VVCC_BYT VCC bypass threshold
6.6
7
100
8.5
7.4
V
mV
V
VVIN = 6 to 8.5 V
VVIN increasing
16
Copyright © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
300
100
8.8
0.8
9.2
5.3
190
3
MAX
UNIT
mV
Ω
VVCC_BYH
VCC bypass hysteresis
VVIN = 6 V
VVIN = 10 V
VVIN = 48 V
VVCC_OUT
VCC output impedance
Ω
Ω
VVCC_LIM
VVCC_UV
VVCC_UVH
VVCC_UVFD
IIN_OP
VCC current limit
mA
V
VCC undervoltage lockout
VCC undervoltage lockout hysteresis
VCC filter delay
mV
μs
IIN operating current
FB = 3 V
550
110
750
176
μA
μA
IIN_OP
IIN shutdown current
RT/SD = 0 V
BUCK REGULATOR SWITCHING
RDS(on)
Buck switch RDS(on)
ITEST = 200 mA
1.25
3.8
2.57
4.8
Ω
VGATE_UV
Gate drive undervoltage lockout
VBST - VSW rising
2.8
V
Gate drive undervoltage lockout
hysteresis
VGATE_UVH
490
mV
VSWITCH
tON
Pre-charge switch voltage
Pre-charge switch on-time
At 1 mA
0.8
V
150
ns
BUCK REGULATOR CURRENT LIMIT
ILIMIT
tLIM
tOFF1
tOFF2
Current limit threshold
Current limit response time
Off time generator
0.41
0.51
350
35
0.61
A
ISW overdrive = 0.1 A, time to switch off
FB = 0 V, RCL = 100 kΩ
ns
μs
μs
Off time generator
FB = 2.3 V, RCL = 100 kΩ
2.56
BUCK REGULATOR ON TIME GENERATOR
tON1
Ton 1
VVIN = 10 V, RON = 200 kΩ
VVIN = 95 V, RON = 200 kΩ
Rising
2.15
200
0.4
2.77
300
0.7
3.5
420
μs
μs
V
tON2
Ton 2
VSDT
VSDH
Remote shutdown threshold
Remote shutdown hysteresis
1.05
35
mV
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MIN Minimum off time
FB = 0 V
300
ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFB
FB reference threshold
FB overvoltage threshold
FB bias current
Internal reference, trip point for switch on
Trip point for switch off
2.445
2.5
2.875
100
2.55
V
V
VFB_OV
IFB_BIAS
μA
BUCK REGULATOR THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
165
25
°C
°C
TSDH
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7.6 SPI Timing Requirements
at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
ms
ns
tREADY
tCLK
SPI ready after enable
VM > UVLO, ENABLE = 3.3 V
1
SCLK minimum period
100
50
50
20
30
tCLKH
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
nSCS input setup time
ns
tCLKL
ns
tSU_SDI
tH_SDI
ns
ns
tD_SDO
tSU_nSCS
tH_nSCS
tHI_nSCS
tDIS_nSCS
SCLK high to SDO valid
30
ns
50
50
ns
nSCS input hold time
ns
nSCS minimum high time before active low
nSCS disable time
400
ns
nSCS high to SDO high impedance
10
ns
tHI_nSCS tSU_nSCS
tH_nSCS
nSCS
SCLK
tCLK
tCLKH
tCLKL
X
MSB
LSB
X
SDI
tSU_SDI
tH_SDI
Z
MSB
LSB
Z
SDO
tD_SDO
tDIS_nSCS
图 1. SPI Slave Mode Timing Diagram
18
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DRV8350, DRV8350R
DRV8353, DRV8353R
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ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
7.7 Typical Characteristics
10
9.5
9
2
1.95
1.9
TA = -40°C
TA = 25°C
TA = 125°C
1.85
1.8
8.5
8
1.75
1.7
1.65
1.6
TA = -40°C
TA = 25°C
TA = 125°C
7.5
7
1.55
1.5
0
10
20
30
Supply Voltage (V)
40
50
60
70
80
0
10
20
30
40
Supply Voltage (V)
50
60
70
80
90 100
D001
D002
VVM = VVDRAIN
VVM = VVDRAIN
图 2. VM Supply Current Over Supply Voltage
图 3. VDRAIN Supply Current Over Supply Voltage
40
35
30
25
20
15
10
40
35
30
25
20
15
10
VSUP = 9 V
VSUP = 48 V
VSUP = 100 V
TA = -40°C
TA = 25°C
TA = 125°C
-40
-20
0
20
40
60
80
100 120 140
0
10
20
30
40
50
60
Supply Voltage (V)
70
80
90 100
Temperature (èC)
D004
D003
IVM + IVDRAIN
图 5. Sleep Current Over Temperature
IVM + IVDRAIN
图 4. Sleep Current Over Supply Voltage
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
15.5
15.4
15.3
15.2
15.1
15
TA = -40èC
TA = -40èC
TA = 25èC
TA = 25èC
TA = 125èC
TA = 125èC
14.9
14.8
14.7
14.6
14.5
0
5
10 15
VCP Load Current (mA)
20
25
0
5
10 15
VGLS Load Current (mA)
20
25
D005
D006
VVM = 48-V
VVM = 48-V
图 7. VGLS Voltage Over Load Current
图 6. VCP Voltage Over Load
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Typical Characteristics (接下页)
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
16
15.8
15.6
15.4
15.2
15
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
14.8
14.6
14.4
14.2
14
0
5
10 15
VCP Load Current (mA)
20
25
0
5
10 15
VGLS Load Current (mA)
20
25
D007
D008
VVM = 15-V
图 8. VCP Voltage Over Load Current
VVM = 15-V
图 9. VGLS Voltage Over Load Current
11
10.8
10.6
10.4
10.2
10
13
12.8
12.6
12.4
12.2
12
TA = -40èC
TA = 25èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = 125èC
9.8
11.8
11.6
11.4
11.2
11
9.6
9.4
9.2
9
0
5
10
VCP Load Current (mA)
15
20
0
5
10
VGLS Load Current (mA)
15
20
D009
D010
VVM = 12-V
VVM = 12-V
图 10. VCP Voltage Over Load Current
图 11. VGLS Voltage Over Load Current
9
8.8
8.6
8.4
8.2
8
10
9.8
9.6
9.4
9.2
9
TA = -40èC
TA = -40èC
TA = 25èC
TA = 25èC
TA = 125èC
TA = 125èC
7.8
7.6
7.4
7.2
7
8.8
8.6
8.4
8.2
8
0
2
4
VCP Load Current (mA)
6
8
10
0
2
4
VGLS Load Current (mA)
6
8
10
D011
D012
VVM = 9-V
VVM = 9-V
图 12. VCP Voltage Over Load Current
图 13. VGLS Voltage Over Load Current
20
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DRV8353, DRV8353R
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ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
8 Detailed Description
8.1 Overview
The DRV835x family of devices are integrated 100-V gate drivers for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent half-
bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,
optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral
interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic
information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring
the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is
generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The low-
side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates the
VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver outputs. A
smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current strength
allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of
external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture
also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead
time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM
can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,
VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device
efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent
monitor reference.
The DRV8353 and DRV8353R devices integrate three, bidirectional current-shunt amplifiers for monitoring the
current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the
shunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility
to adjust the output bias point.
The DRV8350R and DRV8353R devices integrate a 350-mA buck regulator that can be used to power an
external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can
use either the same or a different power supply from the gate driver.
In addition to the high level of device integration, the DRV835x family of devices provides a wide range of
integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive
undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information
available in the SPI registers on the SPI device version.
The DRV835x family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN sizes
are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin package.
版权 © 2018–2019, Texas Instruments Incorporated
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8.2 Functional Block Diagram
VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Control
Inputs
Protection
VGLS
LS
GLC
SLC
MODE
IDRIVE
VDS
Gate Driver
Fault Output
VCC
R
PU
nFAULT
图 14. Block Diagram for DRV8350H
22
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DRV8353, DRV8353R
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Functional Block Diagram (接下页)
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Protection
SHC
GLC
VGLS
LS
VCC
SLC
SPI
Gate Driver
Fault Output
R
PU
VCC
SDO
R
PU
SCLK
nFAULT
nSCS
图 15. Block Diagram for DRV8350S
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Functional Block Diagram (接下页)
VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Control
Inputs
Protection
VGLS
LS
GLC
SLC
MODE
IDRIVE
VDS
Gate Driver
Fault Output
VCC
R
PU
nFAULT
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
RFB1
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
图 16. Block Diagram for DRV8350RH
24
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DRV8353, DRV8353R
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ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Functional Block Diagram (接下页)
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Protection
SHC
GLC
VGLS
LS
VCC
SLC
SPI
Gate Driver
Fault Output
R
PU
VCC
SDO
R
PU
SCLK
nFAULT
nSCS
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
RFB1
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
图 17. Block Diagram for DRV8350RS
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Functional Block Diagram (接下页)
VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
Control
Inputs
VGLS
LS
GLC
SPC
MODE
Gate Driver
Fault Output
IDRIVE
VCC
PU
R
VDS
nFAULT
GAIN
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
图 18. Block Diagram for DRV8353H
26
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DRV8353, DRV8353R
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Functional Block Diagram (接下页)
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Protection
SHC
GLC
VGLS
LS
VCC
SPC
SPI
Gate Driver
Fault Output
R
PU
VCC
PU
SDO
R
SCLK
nFAULT
nSCS
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
图 19. Block Diagram for DRV8353S
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DRV8350, DRV8350R
DRV8353, DRV8353R
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www.ti.com.cn
Functional Block Diagram (接下页)
VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
Control
Inputs
VGLS
LS
GLC
SPC
MODE
Gate Driver
Fault Output
IDRIVE
VCC
PU
R
VDS
nFAULT
GAIN
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
RFB1
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
图 20. Block Diagram for DRV8353RH
28
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DRV8353, DRV8353R
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ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Functional Block Diagram (接下页)
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Protection
SHC
GLC
VGLS
LS
VCC
SPC
SPI
Gate Driver
Fault Output
R
PU
VCC
PU
SDO
R
SCLK
nFAULT
nSCS
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
RFB1
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
图 21. Block Diagram for DRV8353RS
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8.3 Feature Description
8.3.1 Three Phase Smart Gate Drivers
The DRV835x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to
the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support.
The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge
gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV835x family of devices implement a smart gate-drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
8.3.1.1 PWM Control Modes
The DRV835x family of devices provides four different PWM control modes to support various commutation and
control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or
PWM_MODE change.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in 表 1.
表 1. 6x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
SHx
Hi-Z
H
0
0
1
1
0
1
0
1
L
H
L
L
H
L
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in 表 2.
表 2. 3x PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
SHx
Hi-Z
L
0
1
1
X
0
1
H
L
L
H
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV835x family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-
bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
30
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The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
表 3. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
INHC = 0
GATE-DRIVE OUTPUTS
PHASE B PHASE C
INHC = 1
PHASE A
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
GHB
GLB
GHC
GLC
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
!PWM
L
L
L
L
L
Stop
Align
L
H
L
H
Align
1
2
3
4
5
6
PWM
!PWM
L
L
H
H
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
!PWM
!PWM
L
L
L
H
L
L
L
L
H
PWM
PWM
L
!PWM
!PWM
L
L
H
L
L
L
H
PWM
!PWM
表 4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
INHC = 0
GATE-DRIVE OUTPUTS
PHASE B PHASE C
INHC = 1
PHASE A
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
L
GHB
GLB
L
GHC
GLC
L
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
L
Stop
Align
L
L
H
L
L
H
H
H
L
Align
1
2
3
4
5
6
L
PWM
L
L
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
L
L
L
L
L
L
H
H
L
L
L
PWM
PWM
L
L
L
H
H
L
L
L
PWM
L
L
图 22 and 图 23 show the different possible configurations in 1x PWM mode.
INHA
INLA
INHB
INLB
INHC
INLC
INHA
MCU_PWM
PWM
MCU_PWM
MCU_GPIO
MCU_GPIO
PWM
H
INLA
INHB
INLB
INHC
INLC
STATE0
STATE1
STATE2
DIR
STATE0
STATE1
STATE2
DIR
H
BLDC Motor
BLDC Motor
H
MCU_GPIO
MCU_GPIO
MCU_GPIO
MCU_GPIO
nBRAKE
MCU_GPIO
nBRAKE
图 22. 1x PWM—Simple Controller
图 23. 1x PWM—Hall Sensor
8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835x or to
utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge.
These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches.
In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side
and low-side MOSFETs are turned on at the same time.
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表 5. Independent PWM Mode Truth Table
INLx
INHx
GLx
L
GHx
L
0
0
1
1
0
1
0
1
L
H
H
L
H
H
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the
monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in 图
24.
Disable
+
VDS
œ
VM
VDRAIN
VCP
GHx
Load
HS
INHx
SHx
VGLS
INLx
GLx
LS
Load
Gate Driver
Disable
SLx/SPx
+
VDS
œ
图 24. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in 图 25 or 图 26. The unused gate driver and the corresponding
input can be left disconnected.
+
+
VDS
VDS
œ
œ
VM
VM
VDRAIN
VDRAIN
VCP
HS
VCP
HS
GHx
SHx
GHx
SHx
Load
INHx
INLx
INHx
INLx
VGLS
LS
VGLS
LS
GLx
GLx
Load
Gate Driver
SLx/SPx
Gate Driver
SLx/SPx
+
+
VDS
VDS
œ
œ
图 25. Single High-Side Driver
图 26. Single Low-Side Driver
32
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8.3.1.2 Device Interface Modes
The DRV835x family of devices support two different interface modes (SPI and hardware) to allow the end
application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin to pin compatible. This allows for application designers to evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that allows for an external controller to send and receive
data with the DRV835x. This allows for the external controller to configure device settings and read detailed fault
information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
•
The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on
SDI and SDO.
•
•
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
•
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV835x.
For more information on the SPI, see the SPI Communication section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This allows for the application designer to configure the most commonly used device settings
by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement
for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT
pin.
•
•
•
•
The GAIN pin configures the current shunt amplifier gain.
The IDRIVE pin configures the gate drive current strength.
The MODE pin configures the PWM control mode.
The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
DVDD
DVDD
RGAIN
GAIN
SCLK
Hardware
Interface
SPI
Interface
DVDD
DVDD
IDRIVE
MODE
VDS
SDI
SDO
DVDD
VCC
RPU
DVDD
nSCS
RVDS
图 27. SPI
图 28. Hardware Interface
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8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and
VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET
gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep
a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less
than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect to
VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven
MOSFET conditions.
The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to
act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required
between the CPH and CPL pins to act as the flying capacitor.
VDRAIN
VDRAIN
1 …F
VCP
CPH
VM
Charge
Pump
Control
47 nF
CPL
图 29. Charge Pump Architecture
The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect
to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs
during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is
monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a
X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly
from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate
driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an
externally available power supply. On the DRV8350R and DRV8353R devices the integrated buck regulator can
be used to create the efficient low voltage supply for VM without the need for an additional regulator. 图 30 and
图 31 show examples of the DRV835x configured in either single supply or dual supply configuration.
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48-V
Power
Supply
48-V
Power
Supply
48-V to 15-V
DC/DC
VM
VDRAIN
VM
VDRAIN
DRV835x
DRV835x
Power
MOSFETs
Power
MOSFETs
图 30. Single Supply Example
图 31. Dual Supply Example
8.3.1.4 Smart Gate Drive Architecture
The DRV835x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-
side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. 图 32 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
VDRAIN
Control
Inputs
INLx
GHx
SHx
Level
Shifters
150 kꢀ
+
GS œ
V
VGLS
Digital
Core
GLx
Level
Shifters
150 kꢀ
SLx/SPx
+
GS œ
V
图 32. Gate Driver Block Diagram
8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics
in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are predominately
determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or Miller charging
region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external
power MOSFETs.
IDRIVE allows the DRV835x family of devices to dynamically switch between gate drive currents either through a
register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide 16
IDRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices
provides 7 IDRIVE settings between the same ranges. The gate drive current setting is delivered to the gate during
the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or turnoff,
the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. Additional details on
the IDRIVE settings are described in the Register Maps section for the SPI devices and in the Pin Diagrams
section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV835x family of devices use VGS voltage monitors to measure the
MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value.
This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on SPI devices.
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The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET
on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the high-
side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an
additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due
to the need to discharge the voltage present on the internal VGS detection circuit.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at
the end of the tDRIVE period the VGS voltage has not reached the correct threshold the gate driver will report a
fault. To make sure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Register Maps section for SPI devices and in the Pin Diagrams section for hardware interface
devices.
图 33 shows an example of the TDRIVE state machine in operation.
V
INHx
V
INLx
V
GHx
tDEAD
IHOLD
tDEAD
I
I
t
I
I
HOLD
HOLD
DRIVE
STRONG
I
GHx
I
t
I
HOLD
DRIVE
DRIVE
DRIVE
V
GLx
GLx
tDEAD
tDEAD
IHOLD
I
I
t
I
I
HOLD
HOLD
DRIVE
DRIVE
STRONG
I
I
I
HOLD
DRIVE
t
DRIVE
图 33. TDRIVE State Machine
8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
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8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current-shunt amplifiers (DRV8353 and DRV8353R), the low-side VDS monitors measure the voltage between the
SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the
external half-bridges. On device options without the current shunt amplifiers (DRV8350 and DRV8350R) the low-
side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if
desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor
stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on
hardware interface devices. Additional information on the VDS monitor levels are described in the Register Maps
section for SPI devices and in the Pin Diagrams section hardware interface device.
VDRAIN
VDRAIN
VDRAIN
VDRAIN
+
+
V
V
+
+
V
V
V
V
DSœ
DS œ
DSœ
DSœ
V
V
V
V
VDS_OCP
VDS_OCP
GHx
SHx
GLx
GHx
SHx
GLx
+
DSœ
+
DSœ
+
DSœ
+
DSœ
V
V
VDS_OCP
VDS_OCP
SLx
SPx
0
1
R
SENSE
SNx
LS_REF
(SPI Only)
图 34. DRV8350 and DRV8350R VDS Monitors
图 35. DRV8353 and DRV8353R VDS Monitors
8.3.1.4.5 VDRAIN Sense and Reference Pin
The DRV835x family of devices provides a separate sense and reference pin for the common point of the high-
side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors
(VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.
The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge
pump reference stays with respect to the power MOSFET supply through voltage transient conditions.
Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the
power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can
be supplied from an efficient low voltage supply to increase the device efficiency. On the DRV8350R and
DRV8353R devices, the integrated buck regulator can be used to create the efficient low voltage supply.
8.3.2 DVDD Linear Voltage Regulator
A 5-V, 10-mA linear regulator is integrated into the DRV835x family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of
the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor
routed directly back to the adjacent DGND or GND ground pin.
The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 10
mA.
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VM
REF
+
œ
5 V, 10 mA
DVDD
1 …F
GND/
DGND
图 36. DVDD Linear Regulator Block Diagram
Use 公式 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P = VVM - VDVDD ì I
DVDD
(1)
(2)
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in 公式 2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
8.3.3 Pin Diagrams
图 37 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
100 kꢀ
图 37. Logic-Level Input Pin Structure
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图 38 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The input
can be set with an external resistor.
MODE
GAIN
DVDD
STATE
VI4
RESISTANCE
Tied to DVDD
DVDD
Independent 40 V/V
+
50 kꢀ
œ
Hi-Z (>500 kΩ to
AGND)
1x PWM
3x PWM
6x PWM
20V/V
10 V/V
5 V/V
VI3
VI2
VI1
+
84 kꢀ
47 kΩ ±5%
to AGND
œ
Tied to AGND
+
œ
图 38. Four Level Input Pin Structure
图 39 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices. The
input can be set with an external resistor.
IDRIVE
1/2 A
VDS
Disabled
+
œ
STATE
VI7
RESISTANCE
Tied to DVDD
700/1400 mA
450/900 mA
300/600 mA
150/300 mA
100/200 mA
50/100 mA
1 V
0.7 V
0.4 V
0.2 V
0.1 V
0.06 V
+
DVDD
DVDD
œ
18 kꢀ 5%
to DVDD
VI6
VI5
VI4
VI3
VI2
VI1
+
75 kꢀ 5%
to DVDD
73 kꢀ
œ
Hi-Z (>500 kΩ
to AGND)
73 kꢀ
+
75 kꢀ 5%
to AGND
œ
18 kΩ ±5%
to AGND
+
Tied to AGND
œ
+
œ
图 39. Seven Level Input Pin Structure
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图 40 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires an
external pullup resistor to function correctly.
DVDD
R
PU
STATE
No Fault
Fault
STATUS
Inactive
Active
OUTPUT
Active
Inactive
图 40. Open-Drain Output Pin Structure
8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
The DRV8353 and DRV8353R integrate three, high-performance low-side current-shunt amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such
as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin
(VREF).
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8353 and DRV8353R outputs an analog voltage equal to the voltage across the SPx
and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels (5
V/V, 10 V/V, 20 V/V, and 40 V/V). Use 公式 3 to calculate the current through the shunt resistor.
VVREF
- VSOx
2
I =
GCSA ì RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
V
CC
œ
R
SENSE
V
+
REF
0.1 …F
R2
R3
R4
R5
½
+
œ
图 41. Bidirectional Current-Sense Configuration
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SO (V)
V
REF
V
/ 2
VREF
V
LINEAR
SP œ SN (V)
图 42. Bidirectional Current-Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP œ SN
œ0.3 V
V
VREF
œ 0.25 V
œI × R
V
SO(rangeœ)
V
SO(off)max
/ 2
V
,
OFF
0 V
V
VREF
V
DRIFT
V
SO(off)min
V
SO(range+)
I × R
0.3 V
0.25 V
0 V
图 43. Bidirectional Current Sense Regions
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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8353 and DRV8353R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case
the shunt amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across the
SPx and SNx pins multiplied by the gain setting (GCSA). Use 公式 4 to calculate the current through the shunt
resistor.
VVREF - VSOx
GCSA ì RSENSE
I =
(4)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
œ
R
SENSE
+
V
CC
R2
R3
R4
R5
V
REF
+
0.1 …F
œ
图 44. Unidirectional Current-Sense Configuration
SO (V)
V
REF
V
œ 0.3 V
VREF
V
LINEAR
SP œ SN (V)
图 45. Unidirectional Current-Sense Output
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I
SP
SN
SO
SO
R
AV
V
REF
V
œ 0.25 V
VREF
V
SO(off)max
SP œ SN
V
,
OFF
0 V
V
œ 0.3 V
VREF
V
DRIFT
V
SO(off)min
V
SO(range)
I × R
0.3 V
0.25 V
0 V
图 46. Unidirectional Current-Sense Regions
8.3.4.3 Amplifier Calibration Modes
To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the
SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration
setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be
done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during the
switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration mode is
shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration mode.
RF
ROUT
SOx
RSP
!CAL
!CAL
SP
SN
-
RSENSE
RSN
VREF
+
CAL
CAL
+
RG
-
图 47. Amplifier Manual Calibration
In addition to the manual calibration method provided on the SPI devices versions, the DRV835x family of
devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize
the amplifier input offset after power up and during run time to account for temperature and device variation.
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Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The
power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.
50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses
the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to
minimize the amplifier input offset. After this the amplifiers are ready for normal operation.
For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL
register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to
rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain
setting in order to improve the accuracy of the calibration routine.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current-sense amplifiers on the DRV8353 and DRV8353R SPI devices can be configured to amplify the
voltage across the external low-side MOSFET VDS. This allows for the external controller to measure the voltage
drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side MOSFET
as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the negative
reference for the low-side VDS monitor is automatically set to SNx, regardless of the state of the LS_REF bit
state. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS sensing mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
VDRAIN
VDRAIN
VDRAIN
VDRAIN
High-Side
High-Side
VCP
VCP
V
Monitor
V
DS
Monitor
DS
+
V
+
V
DSœ
DSœ
GHx
SHx
GHx
SHx
(SPI only)
(SPI only)
CSA_FET = 0
CSA_FET = 1
LS_REF = 0
LS_REF = X
VGLS
VGLS
Low-Side
Low-Side
V
Monitor
V
Monitor
DS
DS
+
V
+
V
DSœ
GLx
GLx
SPx
DSœ
0
1
0
1
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
SPx
10 kꢀ
10 kꢀ
SOx
SOx
AV
R
SEN
AV
SNx
SNx
GND
GND
图 48. Resistor Sense Configuration
图 49. VDS Sense Configuration
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When operating in MOSFET VDS sense mode, the amplifier is enabled at the end of the tDRIVE time. At this time,
the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side MOSFET
receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Step-Down Buck Regulator
The DRV8350R and DRV8353R have an integrated buck regulator (LM5008A) to supply power for an external
controller or system voltage rail.
The LM5008A regulator is an easy-to-use buck (step-down) DC-DC regulator that operates from 6-V to 95-V
supply voltage. The device is intended for step-down conversions from 12-V, 24-V, and 48-V unregulated, semi-
regulated and fully-regulated supply rails. With integrated buck power MOSFET, the LM5008A delivers up to
350-mA DC load current with exceptional efficiency and low input quiescent current in a very small solution size.
Designed for simple implementation, an almost fixed-frequency, constant on-time (COT) operation with
discontinuous conduction mode (DCM) at light loads is ideal for low-noise, high current, fast transient load
requirements. Control loop compensation is not required reducing design time and external component count.
The LM5008A incorporates other features for comprehensive system requirements, including VCC undervoltage
lockout (UVLO), gate drive undervoltage lockout, maximum duty cycle limiter, intelligent current limit off-timer, a
precharge switch, and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-
use platform for a wide range of applications. The pin arrangement is designed for simple and optimized PCB
layout, requiring only a few external components.
For additional details and design information refer to the LM5008A 100-V 350-mA Constant On-Time Buck
Switching Regulator data sheet.
8.3.5.1 Functional Block Diagram
7 V Bias
Regulator
6 V to 95 V
Input
VIN
C5
RT
C1
VCC
UVLO
Thermal
Shutdown
VIN SENSE
VCC
Bypass
Switch
Q2
GND
C3
On Timer
Start
Finish
œ
+
0.7 V
RT
RT/SD
BST
Start
Over-Voltage
Comparator
Vin
SHUTDOWN
GD
UVLO
SD
C4
300 ns MIN
Off Timer
œ
Driver
Finish
2.875 V
Level
Shift
L1
SW
2.5 V
SSET
RCLR
Q
Q
FB
VOUT
œ
D1
Regulation
Comparator
Buck
RCL
RTN
FB
RCL
Finish
Start
Current Limit
Off Timer
RFB2
Pre-
Charge
Switch
Current
Sense
R3
C2
œ
RCL
0.51 A
RFB1
图 50. Functional Block Diagram
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8.3.5.2 Feature Description
8.3.5.2.1 Control Circuit Overview
The LM5008A is a Buck DC-DC regulator that uses a control scheme in which the on-time varies inversely with
line voltage (VIN). Control is based on a comparator and the on-time one-shot, with the output voltage feedback
(FB) compared to an internal reference (2.5 V). If the FB level is below the reference the buck switch is turned on
for a fixed time determined by the line voltage and a programming resistor (RT). Following the ON period, the
switch stays off for at least the minimum off-timer period of 300 ns. If FB is still below the reference at that time,
the switch turns on again for another on-time period. This continues until regulation is achieved.
The LM5008A operates in discontinuous conduction mode at light load currents, and continuous conduction
mode at heavy load current. In discontinuous conduction mode, current through the output inductor starts at zero
and ramps up to a peak during the on-time, then ramps back to zero before the end of the off-time. The next on-
time period starts when the voltage at FB falls below the internal reference; until then, the inductor current stays
zero. In this mode, the operating frequency is lower than in continuous conduction mode and varies with load
current. Therefore, at light loads, the conversion efficiency is kept because the switching losses decrease with
the reduction in load and frequency. The discontinuous operating frequency can be calculated with 公式 5.
VOUT2 ìL ì1.04ì1020
RL ì(RT )2
≈
’
F =
∆
∆
«
÷
÷
◊
where
•
RL = the load resistance
(5)
In continuous conduction mode, current flows continuously through the inductor and never ramps down to zero.
In this mode the operating frequency is greater than the discontinuous mode frequency and stays relatively
constant with load and line variations. The approximate continuous mode operating frequency can be calculated
with 公式 6.
≈
’
VOUT
F =
∆
∆
«
÷
÷
1.385ì10-10 ìRT ◊
(6)
The output voltage (VOUT) is programmed by two external resistors as shown in 图 50. The regulation point can
be calculated with 公式 7.
VOUT = 2.5 × (RFB1 + RFB2) / RFB1
(7)
The LM5008A regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor C2. A minimum of 25 mV to 50 mV of ripple voltage at the feedback pin
(FB) is required for the LM5008A. In cases where the capacitor ESR is too small, additional series resistance
may be required (R3 in the 图 50).
For applications where lower output voltage ripple is required, the output can be taken directly from a low-ESR
output capacitor as shown in 图 51. However, R3 slightly degrades the load regulation.
L1
SW
RFB2
R3
FB
VOUT2
RFB1
C2
图 51. Low-Ripple Output Configuration
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8.3.5.2.2 Start-Up Regulator (VCC
)
The high voltage bias regulator is integrated within the LM5008A. The input pin (VIN) can be connected directly
to line voltages between 6 V and 95 V, with transient capability to 100 V. Referring to the 图 50, when VIN is
between 6 V and the bypass threshold (nominally 8.5 V), the bypass switch (Q2) is on, and VCC tracks VIN within
100 mV to 150 mV. The bypass switch on-resistance is approximately 100 Ω, with inherent current limiting at
approximately 100 mA. When VIN is above the bypass threshold Q2 is turned off, and VCC is regulated at 7 V.
The VCC regulator output current is limited at approximately 9.2 mA. When the LM5008A is shut down using the
RT/SD pin, the VCC bypass switch is shut off regardless of the voltage at VIN.
When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 µs to 3 µs. The
capacitor at VCC (C3) must be a minimum of 0.47 µF to prevent the voltage at VCC from rising above its absolute
maximum rating in response to a step input applied at VIN. C3 must be placed as near as possible to the VCC
and RTN pins. In applications with a relatively high input voltage, power dissipation in the bias regulator is a
concern. An auxiliary voltage of between 7.5 V and 14 V can be diode connected to the VCC pin to shut off the
VCC regulator, thereby reducing internal power dissipation. The current required into the VCC pin is shown in the
typical characteristics curves. Internally a diode connects VCC to VIN requiring that the auxiliary voltage be less
than VIN.
The turnon sequence is shown in 图 52. During the initial delay (t1), VCC ramps up at a rate determined by its
current limit and C3 while internal circuitry stabilizes. When VCC reaches the upper threshold of its undervoltage
lockout (UVLO, typically 5.3 V), the buck switch is enabled. The inductor current increases to the current limit
threshold (ILIM), and during t2 the VOUT increases as the output capacitor charges up. When VOUT reaches the
intended voltage the average inductor current decreases (t3) to the nominal load current (IO).
VIN
t1
7 V
UVLO
VCC
Vin
SW Pin
0 V
ILIM
Inductor
Current
IO
t3
t2
VOUT
图 52. Start-Up Sequence
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8.3.5.2.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5-V reference. In normal operation (the output voltage is
regulated), an on-time period is initiated when the voltage at FB falls below 2.5 V. The buck switch stays on for
the on-time, causing the FB voltage to rise above 2.5 V. After the on-time period, the buck switch stays off until
the FB voltage again falls below 2.5 V. During start-up, the FB voltage is below 2.5 V at the end of each on-time,
resulting in the minimum off-time of 300 ns. Bias current at the FB pin is nominally 100 nA.
8.3.5.2.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 2.875-V reference. If the voltage at FB rises above 2.875
V, the on-time pulse is immediately terminated. This condition can occur if the input voltage or the output load
change suddenly. The buck switch does not turn on again until the voltage at FB falls below 2.5 V.
8.3.5.2.5 On-Time Generator and Shutdown
The on-time for the LM5008A is determined by the RT resistor and is inversely proportional to the input voltage
(VIN), resulting in an almost constant frequency as Vin is varied over its range. The on-time equation for the
LM5008A is 公式 8.
TON = 1.385 × 10–10 × RT / VIN
(8)
RT must be selected for a minimum on-time (at maximum VIN) greater than 400 ns, for correct current limit
operation. This requirement limits the maximum frequency for each application, depending on VIN and VOUT
.
The LM5008A can be remotely disabled by taking the RT/SD pin to ground. See 图 53. The voltage at the RT/SD
pin is between 1.5 V and 3 V, depending on VIN and the value of the RT resistor.
Input
Voltage
VIN
RT
RT/SD
STOP
RUN
图 53. Shutdown Implementation
8.3.5.2.6 Current Limit
The LM5008A has an intelligent current limit OFF timer. If the current in the Buck switch exceeds 0.51 A the
present cycle is immediately terminated and a non-resetable OFF timer is initiated. The length of off-time is
controlled by an external resistor (RCL) and the FB voltage. When FB = 0 V, a maximum off-time is required, and
the time is preset to 35 µs. This condition occurs when the output is shorted and during the initial part of start-up.
This amount of time makes sure that safe short-circuit operation occurs up to the maximum input voltage of 95 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit), the current limit off-time is less
than 35 µs. Reducing the off-time during less severe overloads decreases the amount of foldback, recovery time,
and the start-up time. The off-time is calculated from 公式 9.
≈
’
÷
÷
÷
÷
∆
∆
10-5
TOFF
=
∆
VFB
6.35ì10-6 ìRCL
∆ 0.285 +
∆
÷
«
◊
(9)
The current limit-sensing circuit is blanked for the first 50 ns to 70 ns of each on-time, so it is not falsely tripped
by the current surge which occurs at turnon. The current surge is required by the re-circulating diode (D1) for its
turnoff recovery.
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8.3.5.2.7 N-Channel Buck Switch and Driver
The LM5008A integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01-
µF ceramic capacitor (C4) connected between the BST pin and SW pin provides the voltage to the driver during
the on-time.
During each off-time, the SW pin is at approximately 0 V and the bootstrap capacitor charges from VCC through
the internal diode. The minimum off-timer, set to 300 ns, makes sure that a minimum time each cycle to recharge
the bootstrap capacitor.
The internal precharge switch at the SW pin is turned on for ≊ 150 ns during the minimum off-time period,
ensuring sufficient voltage exists across the bootstrap capacitor for the on-time. This feature helps prevent
operating problems which can occur during very light-load conditions, involving a long off-time, during which the
voltage across the bootstrap capacitor could otherwise decrease to less than the threshold for the gate drive
UVLO. The precharge switch also helps prevent start-up problems which can occur if the output voltage is
precharged prior to turnon. After current limit detection, the precharge switch is turned on for the entire duration
of the forced off-time.
8.3.5.2.8 Thermal Protection
The LM5008A must be operated so the junction temperature does not exceed 125°C during normal operation. An
internal Thermal Shutdown circuit is provided to shutdown the LM5008A in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state by
disabling the buck switch. This feature prevents catastrophic failures from accidental device overheating. When
the junction temperature decreases below 140°C (typical hysteresis = 25°C), normal operation continues.
8.3.6 Gate Driver Protective Circuits
The DRV835x family of devices are fully protected against VM undervoltage, charge pump and low-side regulator
undervoltage, MOSFET VDS overcurrent, gate driver shorts, and overtemperature events.
8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN pin
falls below the VVDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the nFAULT
pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage condition is
removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage
conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on
VM and VDRAIN pin voltages.
8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VVCP_UV threshold or voltage on the
VGLS pin falls below the VVGLS_UV threshold, all of the external MOSFETs are disabled and the nFAULT pin is
driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation
continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed.
The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the
DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the
GDUV protection is always enabled.
8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on)
.
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware interface
devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the OCP_MODE is
configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI devices, the
VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI
register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown, VDS automatic retry,
VDS report only, and VDS disabled.
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The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled
on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as normal. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is
fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 8-ms automatic retry. On SPI devices, the VSENSE
threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and
the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry,
VSENSE report only, and VSENSE disabled.
The VSENSE overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on
SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
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8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
In the case of a MOSFET VDS or VSENSE overcurrent fault the driver uses a special shutdown sequence to protect
the driver and MOSFETs from large voltage switching transients. These large voltage transients can be created
when rapidly switching off the external MOSFETs when a large drain to source current is present, such as during
an overcurrent event.
To mitigate this issue, the DRV835x family of devices reduce the IDRIVEN pull down current setting for both the
high-side and low-side gate drivers during the MOSFET turn off in response to the fault event. If the programmed
IDRIVEN value is less than 1100 mA, the IDRIVEN value is set to the minimum IDRIVEN setting. If the programmed
IDRIVEN value is greater than or equal to 1100mA, the IDRIVEN value is reduced by seven code settings.
8.3.6.7 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device does no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin and FAULT bit by setting the OTW_REP bit to 1 through the SPI
registers.
52
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8.3.6.8 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation continues (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit stays latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
8.3.6.9 Fault Response Table
表 6. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
RECOVERY
Automatic:
VVM > VVM_UV
VM Undervoltage
(VM_UV)
VVM < VVM_UV
—
nFAULT
Hi-Z
Automatic:
VVM > VVDR_UV
VDRAIN Undervoltage
(VDR_UV)
VVDRAIN < VVDR_UV
—
nFAULT
Hi-Z
DIS_GDUV = 0b
DIS_GDUV = 1b
DIS_GDUV = 0b
DIS_GDUV = 1b
nFAULT
None
Hi-Z
Active
Hi-Z
Automatic:
VVCP > VVCP_UV
Charge Pump Undervoltage
(VCP_UV)
VVCP < VVCP_UV
nFAULT
None
Automatic:
VVGLS > VVGLS_UV
VGLS Regulator Undervoltage
(VGLS_UV)
VVGLS < VVGLS_UV
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
OCP_MODE = 01b
nFAULT
nFAULT
Hi-Z
Hi-Z
Retry:
tRETRY
VDS Overcurrent
(VDS_OCP)
VDS > VVDS_OCP
OCP_MODE = 10b
OCP_MODE = 11b
nFAULT
None
Active
Active
No action
No action
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
nFAULT
Hi-Z
Retry:
tRETRY
OCP_MODE = 01b
OCP_MODE = 10b
nFAULT
nFAULT
None
Hi-Z
VSENSE Overcurrent
(SEN_OCP)
VSP > VSEN_OCP
Active
Active
No action
No action
OCP_MODE = 11b or
DIS_SEN = 1b
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 0b
DIS_GDF = 1b
OTW_REP = 1b
OTW_REP = 0b
—
nFAULT
None
Hi-Z
Active
Active
Active
Hi-Z
Gate Driver Fault
(GDF)
VGS Stuck > tDRIVE
No action
Automatic:
TJ < TOTW – THYS
nFAULT
None
Thermal Warning
(OTW)
TJ > TOTW
No action
Automatic:
TJ < TOTSD – THYS
Thermal Shutdown
(OTSD)
TJ > TOTSD
nFAULT
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV835x family of devices. When the ENABLE pin is low, the device
goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are
disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense
amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their
default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to
sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time
must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
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Device Functional Modes (接下页)
8.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device goes to operating mode. The tWAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV835x family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will start the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Shutdown Mode
The RT/SD pin provides ON and OFF control for the LM5008A. When VSD is below approximately 0.7 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 110 µA (typical) at VIN = 48 V. The LM5008A also employs VCC bias rail undervoltage
protection. If the VCC bias supply voltage is below its UV threshold, the regulator stays off.
8.4.2.2 Active Mode
LM5008A is in active mode when the internal bias rail, VCC, is above its UV threshold. Depending on the load
current, the device operates in either DCM or CCM mode.
Whenever the load current is decreased to a level less than half the peak-to-peak inductor ripple current, the
device goes to discontinuous conduction mode (DCM). Calculate the critical conduction boundary using 公式 10.
VOUT ì 1-D
(
)
DIL
2
IBOUNDARY
=
=
2 ì LF ì fSW
(10)
When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at SW
as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node. At
light loads, several pulses may be skipped in between switching cycles, effectively reducing the switching
frequency and further improving light-load efficiency.
8.5 Programming
This section applies only to the DRV835x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV835x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
•
•
•
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is set
Hi-Z.
•
Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
54
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Programming (接下页)
•
•
•
•
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is not 16 bits, a frame error occurs and the data word is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
•
The SDO pin is an open-drain output and requires an external pullup resistor.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
1 read or write bit, W (bit B15)
4 address bits, A (bits B14 through B11)
11 data bits, D (bits B11 through B0)
Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read
command.
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data
currently in the register being accessed.
表 7. SDI Input Data Word Format
R/W
B15
W0
ADDRESS
DATA
B5
B14
A3
B13
A2
B12
A1
B11
A0
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
D5
表 8. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
X
B14
X
B13
X
B12
X
B11
X
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
nSCS
SCLK
SDI
X
Z
MSB
LSB
LSB
X
Z
MSB
SDO
Capture
Point
Propagate
Point
图 54. SPI Slave Timing Diagram
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8.6 Register Maps
This section applies only to the DRV835x SPI devices.
注
Do not modify reserved registers or addresses not listed in the register maps (Table 9). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Table 9. Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
Address
DRV8350S and DRV8350RS
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
Reserved
FAULT
SA_OC
VDS_OCP
SB_OC
GDF
UVLO
OTW
OTSD
GDUV
VDS_HA
VGS_HA
VDS_LA
VGS_LA
VDS_HB
VGS_HB
VDS_LB
VGS_LB
COAST
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SC_OC
DIS_GDF
R
OCP_ACT
DIS_GDUV
LOCK
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
IDRIVEN_LS
VDS_LVL
TRETRY
OCP_MODE
OCP_DEG
Reserved
Reserved
DRV8353S and DRV8353RS
Reserved
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
FAULT
SA_OC
VDS_OCP
GDF
UVLO
OTW
OTSD
GDUV
VDS_HA
VGS_HA
VDS_LA
VDS_HB
VGS_HB
VDS_LB
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SB_OC
DIS_GDUV
LOCK
SC_OC
DIS_GDF
VGS_LA
VGS_LB
COAST
R
OCP_ACT
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
VREF_DIV LS_REF
IDRIVEN_LS
VDS_LVL
TRETRY
CSA_FET
OCP_MODE
CSA_GAIN
OCP_DEG
DIS_SEN CSA_CAL_A
Reserved
CSA_CAL_B
CSA_CAL_C
SEN_LVL
CAL_MODE
56
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8.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 10 shows the codes that are used for
access types in this section.
Table 10. Status Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default value
8.6.1.1 Fault Status Register 1 (address = 0x00h)
The fault status register 1 is shown in Figure 55 and described in Table 11.
Register access type: Read only
Figure 55. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
R-0b
VDS_OCP
R-0b
GDF
R-0b
UVLO
R-0b
OTSD
R-0b
VDS_HA
R-0b
VDS_LA
R-0b
VDS_HB
R-0b
VDS_LB
R-0b
VDS_HC
R-0b
VDS_LC
R-0b
Table 11. Fault Status Register 1 Field Descriptions
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
Indicates VDS monitor overcurrent fault condition
Indicates gate drive fault condition
9
8
7
6
5
4
3
2
1
0
VDS_OCP
GDF
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
UVLO
Indicates undervoltage lockout fault condition
OTSD
Indicates overtemperature shutdown
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
Indicates VDS overcurrent fault on the A high-side MOSFET
Indicates VDS overcurrent fault on the A low-side MOSFET
Indicates VDS overcurrent fault on the B high-side MOSFET
Indicates VDS overcurrent fault on the B low-side MOSFET
Indicates VDS overcurrent fault on the C high-side MOSFET
Indicates VDS overcurrent fault on the C low-side MOSFET
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8.6.1.2 Fault Status Register 2 (address = 0x01h)
The fault status register 2 is shown in Figure 56 and described in Table 12.
Register access type: Read only
Figure 56. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
R-0b
SB_OC
R-0b
SC_OC
R-0b
OTW
R-0b
GDUV
R-0b
VGS_HA
R-0b
VGS_LA
R-0b
VGS_HB
R-0b
VGS_LB
R-0b
VGS_HC
R-0b
VGS_LC
R-0b
Table 12. Fault Status Register 2 Field Descriptions
Bit
Field
Type
Default
Description
10
SA_OC
SB_OC
SC_OC
OTW
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8353xS)
Indicates overcurrent on phase B sense amplifier (DRV8353xS)
Indicates overcurrent on phase C sense amplifier (DRV8353xS)
Indicates overtemperature warning
9
8
7
6
R
R
R
R
0b
0b
0b
0b
GDUV
Indicates VCP charge pump and/or VGLS undervoltage fault
condition
5
4
3
2
1
0
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
Indicates gate drive fault on the A high-side MOSFET
Indicates gate drive fault on the A low-side MOSFET
Indicates gate drive fault on the B high-side MOSFET
Indicates gate drive fault on the B low-side MOSFET
Indicates gate drive fault on the C high-side MOSFET
Indicates gate drive fault on the C low-side MOSFET
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8.6.2 Control Registers
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 13 shows the codes that are used for
access types in this section.
Table 13. Control Registers Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
8.6.2.1 Driver Control Register (address = 0x02h)
The driver control register is shown in Figure 57 and described in Table 14.
Register access type: Read/Write
Figure 57. Driver Control Register
10
9
8
7
6
5
4
3
2
1
0
OCP
_ACT
DIS
_GDUV
DIS
_GDF
OTW
_REP
1PWM
_COM
1PWM
_DIR
CLR
_FLT
PWM_MODE
R/W-00b
COAST
R/W-0b
BRAKE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 14. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
OCP_ACT
R/W
0b
0b = Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
1b
= All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
9
8
DIS_GDUV
DIS_GDF
R/W
R/W
R/W
R/W
0b
0b =VCP and VGLS undervoltage lockout fault is enabled
1b = VCP and VGLS undervoltage lockout fault is disabled
0b
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
7
OTW_REP
PWM_MODE
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification
3
2
1
1PWM_DIR
COAST
R/W
R/W
R/W
0b
0b
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
Write a 1 to this bit to put all MOSFETs in the Hi-Z state
BRAKE
Write a 1 to this bit to turn on all three low-side MOSFETs
This bit is ORed with the INLC (BRAKE) input in 1x PWM mode.
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear latched fault bits.
This bit automatically resets after being writen.
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8.6.2.2 Gate Drive HS Register (address = 0x03h)
The gate drive HS register is shown in Figure 58 and described in Table 15.
Register access type: Read/Write
Figure 58. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
0
LOCK
IDRIVEP_HS
R/W-1111b
IDRIVEn_HS
R/W-1111b
R/W-011b
Table 15. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7-4
IDRIVEP_HS
R/W
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0
IDRIVEN_HS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
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8.6.2.3 Gate Drive LS Register (address = 0x04h)
The gate drive LS register is shown in Figure 59 and described in Table 16.
Register access type: Read/Write
Figure 59. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
0
CBC
TDRIVE
R/W-11b
IDRIVEP_LS
R/W-1111b
IDRIVEN_LS
R/W-1111b
R/W-1b
Table 16. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
Active only when OCP_MODE = 01b
0b = For VDS_OCP and SEN_OCP, the fault is cleared after
tRETRY
1b = For VDS_OCP and SEN_OCP, the fault is cleared when
a new PWM input is given or after tRETRY
9-8
7-4
TDRIVE
R/W
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
IDRIVEP_LS
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0
IDRIVEN_LS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
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8.6.2.4 OCP Control Register (address = 0x05h)
The OCP control register is shown in Figure 60 and described in Table 17.
Register access type: Read/Write
Figure 60. OCP Control Register
10
9
8
7
6
5
4
3
2
1
0
TRETRY
R/W-0b
DEAD_TIME
R/W-01b
OCP_MODE
R/W-01b
OCP_DEG
R/W-01b
VDS_LVL
R/W-1101b
Table 17. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 8 ms
1b = VDS_OCP and SEN_OCP retry time is 50 µs
9-8
7-6
5-4
3-0
DEAD_TIME
R/W
R/W
R/W
R/W
01b
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
OCP_MODE
OCP_DEG
VDS_LVL
01b
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
10b
00b = Overcurrent deglitch of 1 µs
01b = Overcurrent deglitch of 2 µs
10b = Overcurrent deglitch of 4 µs
11b = Overcurrent deglitch of 8 µs
1001b
0000b = 0.06 V
0001b = 0.07 V
0010b = 0.08 V
0011b = 0.09 V
0100b = 0.1 V
0101b = 0.2 V
0110b = 0.3 V
0111b = 0.4 V
1000b = 0.5 V
1001b = 0.6 V
1010b = 0.7 V
1011b = 0.8 V
1100b = 0.9 V
1101b = 1 V
1110b = 1.5 V
1111b = 2 V
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8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
The CSA control register is shown in Figure 61 and described in Table 18.
Register access type: Read/Write
This register is only available with the DRV8353x family of devices.
Figure 61. CSA Control Register
10
9
8
7
6
5
4
3
2
1
0
CSA
_FET
VREF
_DIV
LS
_REF
CSA
_GAIN
DIS
_SEN
CSA
_CAL_A
CSA
_CAL_B
CSA
_CAL_C
SEN
_LVL
R/W-0b
R/W-1b
R/W-0b
R/W-10b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
Table 18. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
10
CSA_FET
VREF_DIV
LS_REF
R/W
0b
0b = Sense amplifier positive input is SPx
1b = Sense amplifier positive input is SHx (also automatically
sets the LS_REF bit to 1)
9
8
R/W
R/W
1b
0b
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
0b
= VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
R/W
10b
00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5
4
DIS_SEN
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
11b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
CSA_CAL_A
CSA_CAL_B
CSA_CAL_C
SEN_LVL
0b = Normal sense amplifier A operation
1b = Short inputs to sense amplifier A for offset calibration
3
0b = Normal sense amplifier B operation
1b = Short inputs to sense amplifier B for offset calibration
2
0b = Normal sense amplifier C operation
1b = Short inputs to sense amplifier C for offset calibration
1-0
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
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8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
The driver configuration register is shown in Figure 62 and described in Table 19.
Register access type: Read/Write
This register is only available with the DRV8353 and DRV8353R devices.
Figure 62. Driver Configuration Register
10
9
8
7
6
5
4
3
2
1
0
CAL
_MODE
Reserved
R/W-000 0000 000b
R/W-0b
Table 19. Driver Configuration Field Descriptions
Bit
Field
Type
Default
Description
10-1
Reserved
R/W
000 0000 Reserved
000b
0
CAL_MODE
R/W
0b
0b = Amplifier calibration operates in manual mode
1b = Amplifier calibration uses internal auto calibration routine
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DRV835x family of devices are primarily used in three-phase brushless DC motor control applications. The
design procedures in the Typical Application section highlight how to use and configure the DRV835x family of
devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8353R is shown being used for a single supply, three-phase BLDC motor drive with individual half-
bridge current sense in this application example.
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Typical Application (接下页)
LOUT
VCC
VM
DOUT
VM
CIN
ROUT
RFB1
1 …F
COUT
RFB2
1
36
35
34
33
32
31
30
29
28
27
26
25
GND
VGLS
CPL
CPH
VM
INHB
INLA
1 …F
2
3
INHA
47 nF
4
ENABLE
nSCS
SCLK
SDI
VM
5
0.1 …F
1 …F
6
VDRAIN
VCP
Thermal
Pad
VCC
1 kꢀ
7
VCC
10 kꢀ
8
GHA
GHA
SHA
SDO
9
SHA
GLA
SPA
SNA
nFAULT
AGND
VREF
SOA
10
11
12
GLA
VCC
1 …F
SPA
SNA
VM
CBULK
VM
VM
VM
VM
CBULK
CBYP
CBYP
CBYP
GHA
GHB
SHB
GHC
SHC
SHA
MOTA
MOTB
MOTC
GLA
SPA
GLB
SPB
GLC
SPC
R
R
R
SENC
SENA
SENB
SNA
SNB
SNC
图 63. Primary Application Schematic
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Typical Application (接下页)
9.2.1.1 Design Requirements
表 20 lists the example input parameters for the system design.
表 20. Design Parameters
EXAMPLE DESIGN PARAMETER
Power supply voltage
REFERENCE
EXAMPLE VALUE
48 V
VVM, VVDRAIN, VVIN
MOSFET part number
MOSFET
Qg
CSD19535KCS
78 nC (typical) at VVGS = 10 V
13 nC (typical)
100 to 300 ns
50 to 150 ns
45 kHz
MOSFET total gate charge
MOSFET gate to drain charge
Target output rise time
Qgd
tr
Target output fall time
tf
PWM frequency
ƒPWM
VVCC
IVCC
Imax
Buck regulator output voltage
Buck regulator output current
Maximum motor current
ADC reference voltage
3.3 V
100 mA
100 A
VVREF
ISENSE
IRMS
PSENSE
TA
3.3 V
Winding sense current range
Motor RMS current
–40 A to +40 A
28.3 A
Sense resistor power rating
System ambient temperature
3 W
–20°C to +60°C
9.2.1.2 Detailed Design Procedure
表 21 lists the recommended values of the external components for the gate driver. 表 22 lists the recommended
values of the external components for the buck regulator.
表 21. DRV835x Gate-Driver External Components
COMPONENTS
CVM1
PIN 1
VM
PIN 2
GND
RECOMMENDED
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10 µF, VM-rated capacitor
X5R or X7R, 1-µF, 16-V capacitor
X5R or X7R, 1-µF, 16-V capacitor
X5R or X7R, 47-nF, VDRAIN-rated capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
Pullup resistor
CVM2
VM
GND
CVCP
VCP
VM
CVGLS
VGLS
CPH
GND
CSW
CPL
CDVDD
RnFAULT
RSDO
DVDD
VCC(1)
VCC(1)
IDRIVE
VDS
DGND
nFAULT
SDO
Pullup resistor
RIDRIVE
RVDS
RMODE
RGAIN
GND or DVDD
GND or DVDD
GND or DVDD
GND or DVDD
GND or DGND
SNA and GND
SNB and GND
SNC and GND
DRV835x hardware interface
DRV835x hardware interface
DRV835x hardware interface
DRV835x hardware interface
Optional capacitor rated for VREF
Sense shunt resistor
MODE
GAIN
VREF
SPA
CVREF
RASENSE
RBSENSE
RCSENSE
SPB
Sense shunt resistor
SPC
Sense shunt resistor
(1) VCC is not a pin on the DRV835x family of devices, but a VCC supply voltage pullup is required for the open-drain output nFAULT and
SDO. These pins can also be pulled up to DVDD.
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表 22. DRV835xR Buck Regulator External Components
COMPONENT
PIN 1
VIN
PIN 2
GND
SW
RECOMMENDED
(1)
CIN
X5R or X7R, VIN-rated capacitor
X5R or X7R, 0.01-µF, 16-V rated capacitor
X5R or X7R, 0.47-µF, 16-V rated capacitor
Schottky diode
(1)
CBST
BST
(1)
CVCC
VCC
SW
GND
GND
OUT(2)
GND
GND
FB
(1)
DSW
(1)
LSW
SW
Output filter inductor
(1)
COUT
OUT(2)
OUT(2)
OUT(2)
FB
X5R or X7R, OUT-rated capacitor
Output ripple resistor
(1)
ROUT
(1)
RFB1
Resistor divider to set buck output voltage
(1)
RFB2
GND
(1) For detailed design procedures, refer to the LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet.
(2) OUT is not a pin on the DRV8350R and DRV8353R devices, but the regulated output voltage of the buck regulator after the output
inductor.
9.2.1.2.1 External MOSFET Support
The DRV835x family of devices MOSFET support is based on the MOSFET gate charge, VCP charge-pump
capacity, VGLS regulator capacity, and output PWM switching frequency. For a quick calculation of MOSFET
driving capacity, use 公式 11 and 公式 12 for three phase BLDC motor applications.
Trapezoidal 120° Commutation: IVCP/VGLS > Qg × ƒPWM
Sinusoidal 180° Commutation: IVCP/VGLS > 3 × Qg × ƒPWM
(11)
where
•
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
Qg is the MOSFET total gate charge
IVCP/VGLS is the charge pump or low-side regulator capacity, dependent on the VM pin voltage.
The MOSFET multiplier based on the commutation control method, may vary based on implementation.
(12)
9.2.1.2.1.1 MOSFET Example
If a system is using VVM = 48 V (IVCP = 25 mA) and a maximum PWM switching frequency of 45 kHz, then the
VCP charge-pump and VGLS regulator can support MOSFETs using trapezoidal commutation with a Qg < 556
nC, and MOSFETs using sinusoidal commutation with a Qg < 185 nC.
9.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected
at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use 公式
13 and 公式 14 to calculate the value of IDRIVEP and IDRIVEN (respectively).
Qgd
IDRIVEP
>
tr
Qgd
tf
(13)
(14)
IDRIVEN
>
9.2.1.2.2.1 IDRIVE Example
Use 公式 15 and 公式 16 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain charge of
13 nC and a rise time from 100 to 300 ns.
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13 nC
100 ns
13 nC
300 ns
IDRIVEP1
=
= 130 mA
= 43 mA
(15)
(16)
IDRIVEP2
=
Select a value for IDRIVEP that is between 43 mA and 130 mA. For this example, the value of IDRIVEP was selected
as 100-mA source.
Use 公式 17 and 公式 18 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain charge of
13 nC and a fall time from 50 to 150 ns.
13 nC
IDRIVEN1
=
= 260 mA
= 87 mA
50 ns
13 nC
150 ns
(17)
(18)
IDRIVEN2
=
Select a value for IDRIVEN that is between 87 mA and 260 mA. For this example, the value of IDRIVEN was selected
as 200-mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in 公式 19.
VDS_OCP > Imax ì RDS(on)max
(19)
9.2.1.2.3.1 VDS Overcurrent Example
The goal of this example is to set the VDS monitor to trip at a current greater than 75 A. According to the
CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 2.2 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 3.6 mΩ at TA = 25°C. From these values, the
approximate worst-case value of RDS(on) is 2.2 × 3.6 mΩ = 7.92 mΩ.
Using 公式 19 with a value of 7.92 mΩ for RDS(on) and a worst-case motor current of 75 A, 公式 20 shows the
calculated desired value of the VDS overcurrent monitors.
VDS _ OCP > 75 A ì 7.92 mW
VDS _ OCP > 0.594 V
(20)
For this example, the value of VDS_OCP was selected as 0.6 V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 1 µs, 2 µs, 4 µs, or 8 µs.
9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
The sense amplifier gain on the DRV8353 and DRV8353R devices and sense resistor value are selected based
on the target current range, VREF reference voltage, sense-resistor power rating, and operating temperature
range. In bidirectional operation of the sense amplifier, the dynamic range at the output is approximately
calculated as shown in 公式 21.
VVREF
VO = V
- 0.25 V -
(
)
VREF
2
(21)
Use 公式 22 to calculate the approximate value of the selected sense resistor with VO calculated using 公式 21.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
(22)
From 公式 21 and 公式 22, select a target gain setting based on the power rating of the target sense resistor.
9.2.1.2.4.1 Sense-Amplifier Example
In this system example, the value of VREF voltage is 3.3 V with a sense current from –40 to +40 A. The linear
range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range of the
sense amplifier input is –0.3 to +0.3 V (VDIFF).
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3.3 V
V = 3.3 V - 0.25 V -
= 1.4 V
(
)
O
2
(23)
(24)
(25)
1.4 V
AV ì 40 A
1.4 V
AV ì 40 A
R =
2 W > 28.32 ì R ç R < 2.5 mW
2.5 mW >
ç AV > 14
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax
=
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.1.2.5 Single Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835x are not violated during normal
operation of the device. The is especially critical in higher voltage and higher ambient operation applications
where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in single supply operation, first the power internal power dissipation
must be calculated. The internal power dissipation has four primary components:
•
•
•
•
VCP charge pump power dissipation (PVCP
VGLS low-side regulator power dissipation (PVGLS
VM device nominal power dissipation (PVM
VIN buck regulator power dissipation (PBUCK
)
)
)
)
The values of PVCP and PVGLS can be approximated by referring to External MOSFET Support to first determine
IVCP and IVGLS and then referring to 公式 26 and 公式 27.
PVCP = IVCP × (VVM + VVDRAIN
)
(26)
(27)
PVGLS = IVGLS × VVM
The value of PVM can be calculated by referring to the data sheet parameter for IVM current and 公式 28.
PVM = IVM × VVM
(28)
PBUCK = (PO / η) - PO
where
PO = VVCC × IVCC
(30)
(30)
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in 公式 31.
Ptot = PVCP + PVGLS + PVM + PBUCK
(31)
(32)
Lastly, the device junction temperature can be estimate by referring to Thermal Information and 公式 32.
TJmax = TAmax + (RθJA × Ptot)
The information in Thermal Information is based off of a standardized test metric for package and PCB thermal
dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.1.2.6 Single Supply Power Dissipation Example
In this application example the device is configured for single supply operation. This configuration requires only
one power supply for the DRV835x but comes at the tradeoff of increased internal power dissipation. The
junction temperature is estimated in the example below.
Use 公式 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, all 3 high-side and 3
low-side MOSFETs switching, and a switching frequency of 45 kHz.
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IVCP/VGLS = 78 nC × 3 × 45 kHz = 10.5 mA
(33)
Use 公式 26, 公式 27, 公式 28, 公式 29, and 公式 31 to calculate the value of Ptot for VVM = VVDRAIN = VVIN = 48
V, IVM = 9.5 mA, IVCP = 10.5 mA, IVGLS = 10.5 mA, VVCC = 3.3 V, IVCC = 100 mA, and η = 86 %.
PVCP = 10.5 mA × (48 V + 48 V) = 1 W
PVGLS = 10.5 mA × 48 V = 0.5 W
(34)
(35)
(36)
(37)
(38)
PVM = 9.5 mA × 48 V = 0.5 W
PBUCK = [(3.3 V × 100 mA) / 0.86] – (3.3 V × 100 mA) = 0.054 W
Ptot = 1 W + 0.5 W + 0.5 W + 0.054 = 2.054 W
Lastly, to estimate the device junction temperature during operation, use 公式 32 to calculate the value of TJmax
for TAmax = 60°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 2.054 W. Again, please note that the RθJA is
highly dependent on the PCB design used in the actual application and should be verified. For more information
about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
TJmax = 60°C + (26.6°C/W × 2.054 W) = 115°C
(39)
As shown in this example, the device is within its operational limits, but is operating almost to its maximum
operational junction temperature. Design care should be taken in the single supply configuration to correctly
manage the power dissipation of the device.
9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
For a detailed design procedure and information on selecting the correct buck regulator external components,
refer to LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator.
9.2.1.3 Application Curves
图 64. Gate Driver Operation 30% Duty Cycle
图 65. Gate Driver Operation 90% Duty Cycle
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图 66. IDRIVE Minimum Setting Positive Current
图 67. IDRIVE Minimum Setting Negative Current
图 68. IDRIVE 300-mA and 600-mA Setting Positive Current
图 69. IDRIVE 300-mA and 600-mA Setting Negative
Current
图 70. IDRIVE Maximum Setting Positive Current
图 71. IDRIVE Maximum Setting Negative Current
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图 72. FOC Motor Commutation
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9.2.2 Alternative Application
In this application, the DRV8353R is configured to use one sense amplifier in unidirectional mode for a summing
current sense scheme often used in trapezoidal or hall-based BLDC commutation control. Additionally, the device
is configured in dual supply mode using the integrated buck regulator for the VM gate drive voltage supply to
decrease internal power dissipation.
LOUT
VM
VM
VDRAIN
VDRAIN
CIN
External
LDO
ROUT
RFB1
DOUT
VCC
1 …F
CLIN
CLOUT
COUT
RFB2
1
36
35
34
33
32
31
30
29
28
27
26
25
GND
VGLS
CPL
CPH
VM
INHB
INLA
1 …F
2
3
INHA
47 nF
4
ENABLE
nSCS
SCLK
SDI
VM
5
VDRAIN
1 …F
0.1 …F
6
VDRAIN
VCP
Thermal
VCC
7
Pad
1 kꢀ
VCC
10 kꢀ
8
GHA
SHA
GLA
SPA
SNA
GHA
SHA
SDO
9
nFAULT
AGND
VREF
SOA
10
11
12
GLA
VCC
1 …F
SPA
SNA
VDRAIN
CBULK
VDRAIN
VDRAIN
VDRAIN
VDRAIN
CBULK
CBYP
CBYP
CBYP
GHA
GHB
SHB
GHC
SHC
SHA
MOTA
MOTB
MOTC
GLA
SPA
GLB
SPB
GLC
SPC
R
SEN
SNA
图 73. Alternative Application Schematic
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9.2.2.1 Design Requirements
表 23 lists the example design input parameters for system design.
表 23. Design Parameters
EXAMPLE DESIGN PARAMETER
Power supply voltage
REFERENCE
VVM
EXAMPLE VALUE
12 V
Buck supply voltage
VVIN
48 V
MOSFET drain voltage
MOSFET part number
VVDRAIN
MOSFET
Qg
48 V
CSD19535KCS
78 nC
MOSFET total gate charge
PWM frequency
fPWM
20 kHz
Buck regulator output voltage
Buck regulator output current
ADC reference voltage
Winding sense current range
Motor RMS current
VVCC
12 V
IVCC
150 mA
3.3 V
VVREF
ISENSE
IRMS
0 to 40 A
28.3 A
Sense-resistor power rating
System ambient temperature
PSENSE
TA
3 W
–20°C to +105°C
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to the
VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use 公式 40 to calculate the approximate value of the dynamic range at the output.
V = V
- 0.25 V - 0.25 V = VVREF - 0.5 V
O
VREF
(40)
Use 公式 41 to calculate the approximate value of the selected sense resistor.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
where
•
VO = VVREF - 0.5 V
(41)
From 公式 40 and 公式 41, select a target gain setting based on the power rating of a target sense resistor.
9.2.2.2.1.1 Sense-Amplifier Example
In this system example, the value of VVREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8353x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO = 3.3 V - 0.5 V = 2.8 V
(42)
(43)
(44)
2.8 V
R =
3 W > 28.32 ì R ç R < 3.75 mW
AV ì 40 A
2.8 V
3.75 mW >
ç AV > 18.7
AV ì 40 A
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax
=
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
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9.2.2.2.1.2 Dual Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835x are not violated during normal
operation of the device. The is especially critical in higher voltage and higher ambient operation applications
where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in dual supply operation, first the internal power dissipation must be
calculated. The internal power dissipation has four primary components:
•
•
•
•
VCP Charge pump power dissipation (PVCP
VGLS low-side regulator power dissipation (PVGLS
VM device nominal power dissipation (PVM
VIN buck regulator power dissipation (PBUCK
)
)
)
)
The value of PVCP and PVGLS can be approximated by referring to External MOSFET Support to first determine
IVCP and IVGLS and then referring to 公式 45 and 公式 46.
PVCP = IVCP × (VVM + VVDRAIN
)
(45)
(46)
PVGLS = IVGLS × VVM
The value of PVM can be calculated by referring to the datasheet parameter for IVM current and 公式 47.
PVM = IVM × VVM
(47)
PBUCK = (PO / η) – PO
where
PO = VVCC × IVCC
(49)
(49)
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in 公式 50.
Ptot = PVCP + PVGLS + PVM + PBUCK
(50)
(51)
Lastly, the device junction temperature can be estimate by referring to the Thermal Information and 公式 51.
TJmax = TAmax + (RθJA × Ptot)
Note that the information in the Thermal Information is based off of a standardized test metric for package and
PCB thermal dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.2.2.1.3 Dual Supply Power Dissipation Example
In this application example the device is configured for dual supply operation. dual supply operation helps to
decrease the internal power dissipation by providing the gate driver with a lower supply voltage. This can be
derived from the internal buck regulator or an external power supply. The junction temperature is estimated in the
example below.
Use 公式 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, 1 high-side and 1 low-
side MOSFETs switch at a time, and a switching frequency of 20 kHz.
IVCP/VGLS = 78 nC × 1 × 20 kHz = 1.56 mA
(52)
Use equation 公式 45, 公式 46, 公式 47, 公式 48, and 公式 50 to calculate the value of Ptot for VVM = 12 V,
VVDRAIN = 48 V, VVIN = 48 V, IVM = 9.5 mA, IVCP = 1.56 mA, IVGLS = 1.56 mA, VVCC = 12 V, IVCC = 150 mA, and η =
86 %.
PVCP = 1.56 mA × (12 V + 48 V) = 0.1 W
PVGLS = 1.56 mA × 12 V = 0.02 W
(53)
(54)
(55)
(56)
(57)
PVM = 9.5 mA × 12 V = 0.1 W
PBUCK = [(12 V × 150 mA) / 0.86] – (12 V × 150 mA) = 0.29 W
Ptot = 0.1 W + 0.02 W + 0.1 W + 0.29 = 0.51 W
76
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DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
Lastly, to estimate the device junction temperature during operation, use 公式 51 to calculate the value of TJmax
for TAmax = 105°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 0.51 W. Again, note that the RθJA is highly
dependent on the PCB design used in the actual application and should be verified. For more information about
traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal Metrics application
report.
TJmax = 105°C + (26.6°C/W × 0.51 W) = 119°C
(58)
10 Power Supply Recommendations
The DRV835x family of devices are designed to operate from an input voltage supply (VM) range between 9 V
and 75 V. A 0.1-µF ceramic capacitor rated for VM must be placed as near to the device as possible. In addition,
a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is usually
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
stays stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 74. Motor Drive Supply Parasitics Example
版权 © 2018–2019, Texas Instruments Incorporated
77
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1
µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the
GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and
VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or
X7R.
Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type
X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the
GND/DGND pin.
The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a
significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the
common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND.
Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These
recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the SPx/SLx pins.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI:
•
Put the feedback network resistors near the FB pin and away from the inductor to minimize coupling noise
into the feedback pin.
•
Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input
voltage ripple of the device.
•
•
Put the inductor near the SW pin to decrease magnetic and electrostatic noise.
Put the output capacitor near the junction of the inductor and the diode. The inductor, diode, and COUT trace
should be as short as possible to decrease conducted and radiated noise and increase overall efficiency.
•
Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for
Switching Power Supplies application report.
78
版权 © 2018–2019, Texas Instruments Incorporated
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
11.2 Layout Example
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
SOB
SOC
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
INLB
INHC
INLC
DVDD
DGND
SW
D
D
D
D
G
S
S
S
Thermal Pad
VIN
VCC
BST
RCL
RT/SD
FB
VOUT
S
S
S
G
D
D
D
D
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
图 75. Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
79
DRV8350, DRV8350R
DRV8353, DRV8353R
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 器件命名规则
下图显示了说明完整器件名称的图例：
DRV83 (5) (3) (R) (S) (RGZ) (R)
Prefix
DRV83 œ Three Phase Brushless DC
Tape and Reel
R œ Tape and Reel
T œ Small Tape and Reel
Package
RTV œ 5 × 5 × 0.75 mm QFN
RTA œ 6 x 6 × 0.75 mm QFN
RGZ œ 7 × 7 × 0.9 mm QFN
Series
5 œ 100 V device
Interface
S œ SPI interface
H œ Hardware interface
Sense amplifiers
0 œ No sense amplifiers
3 œ 3x sense amplifiers
Buck Regulator
[blank] œ No buck regulator
R œ Buck regulator
12.2 文档支持
12.2.1 相关文档
有关相关文档，请参阅：
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《DRV8353Rx-EVM 用户指南》
德州仪器 (TI)，《DRV8353Rx-EVM GUI 用户指南》
德州仪器 (TI)，《DRV8353Rx-EVM InstaSPIN™ 软件快速入门指南》
德州仪器 (TI)，《LM5008A 100V 350mA 恒定导通时间降压开关稳压器》 产品说明书
德州仪器 (TI)，《CSD19535KCS 100V N 通道 NexFET™ 功率 MOSFET》 产品说明书
德州仪器 (TI)，《TI 电机栅极驱动器的 IDRIVE 和 TDRIVE 认知》应用报告
德州仪器 (TI)，《采用 TI 智能栅极驱动技术进行电机驱动保护》TI 技术手册
德州仪器 (TI)，《采用 TI 智能栅极驱动技术缩减电机驱动 BOM 和 PCB 面积》TI 技术手册
德州仪器 (TI)，《采用 TI 智能栅极驱动技术降低 EMI 辐射发射》TI 技术手册
德州仪器 (TI)，《采用 BLDC 电机的高效真空吸尘器硬件设计注意事项》
德州仪器 (TI)，《采用 BLDC 电机的电动自行车硬件设计注意事项》
德州仪器 (TI)，《工业电机驱动解决方案指南》
德州仪器 (TI)，《开关电源布局指南》应用报告
德州仪器 (TI)，《QFN/SON PCB 连接》应用报告
德州仪器 (TI)，《采用 MSP430™ 的传感器式三相 BLDC 电机控制》应用报告
德州仪器 (TI)，《AN-1149 开关电源布局指南》应用报告
80
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DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com.cn
ZHCSIN3A –AUGUST 2018–REVISED JUNE 2019
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 24. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
DRV8350
DRV8350R
DRV8353
DRV8353R
12.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 商标
NexFET, InstaSPIN, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
81
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8350HRTVR
DRV8350HRTVT
DRV8350RHRGZR
DRV8350RHRGZT
DRV8350RSRGZR
DRV8350RSRGZT
DRV8350SRTVR
DRV8350SRTVT
DRV8353HRTAR
DRV8353HRTAT
DRV8353RHRGZR
DRV8353RHRGZT
DRV8353RSRGZR
DRV8353RSRGZT
DRV8353SRTAR
DRV8353SRTAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RGZ
RGZ
RGZ
RGZ
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
48
48
48
48
32
32
40
40
48
48
48
48
40
40
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8350H
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAU
DRV8350H
DRV8350RH
DRV8350RH
DRV8350RS
DRV8350RS
DRV8350S
DRV8350S
DRV8353H
DRV8353H
DRV8353RH
DRV8353RH
DRV8353RS
DRV8353RS
DRV8353S
DRV8353S
NIPDAU
NIPDAU
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8350HRTVR
DRV8350HRTVT
DRV8350RHRGZR
DRV8350RHRGZT
DRV8350RSRGZR
DRV8350RSRGZT
DRV8350SRTVR
DRV8350SRTVT
DRV8353HRTAR
DRV8353HRTAT
DRV8353RHRGZR
DRV8353RHRGZT
DRV8353RSRGZR
DRV8353RSRGZT
DRV8353SRTAR
DRV8353SRTAT
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RGZ
RGZ
RGZ
RGZ
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
48
48
48
48
32
32
40
40
48
48
48
48
40
40
3000
250
330.0
180.0
330.0
330.0
330.0
330.0
330.0
180.0
330.0
180.0
330.0
330.0
330.0
330.0
330.0
180.0
12.4
12.4
16.4
16.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
12.0
12.0
16.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2500
250
7.25
7.25
7.25
7.25
5.3
7.25
7.25
7.25
7.25
5.3
12.0
12.0
12.0
12.0
8.0
2500
250
3000
250
5.3
5.3
8.0
2000
250
6.3
6.3
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
6.3
6.3
2500
250
7.25
7.25
7.25
7.25
6.3
7.25
7.25
7.25
7.25
6.3
2500
250
2000
250
6.3
6.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8350HRTVR
DRV8350HRTVT
DRV8350RHRGZR
DRV8350RHRGZT
DRV8350RSRGZR
DRV8350RSRGZT
DRV8350SRTVR
DRV8350SRTVT
DRV8353HRTAR
DRV8353HRTAT
DRV8353RHRGZR
DRV8353RHRGZT
DRV8353RSRGZR
DRV8353RSRGZT
DRV8353SRTAR
DRV8353SRTAT
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
WQFN
WQFN
VQFN
VQFN
VQFN
VQFN
WQFN
WQFN
RTV
RTV
RGZ
RGZ
RGZ
RGZ
RTV
RTV
RTA
RTA
RGZ
RGZ
RGZ
RGZ
RTA
RTA
32
32
48
48
48
48
32
32
40
40
48
48
48
48
40
40
3000
250
367.0
210.0
338.0
338.0
338.0
338.0
367.0
210.0
367.0
210.0
338.0
338.0
338.0
338.0
367.0
210.0
367.0
185.0
355.0
355.0
355.0
355.0
367.0
185.0
367.0
185.0
355.0
355.0
355.0
355.0
367.0
185.0
35.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
2500
250
2500
250
3000
250
2000
250
2500
250
2500
250
2000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048L
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.1
6.9
B
A
PIN 1 INDEX AREA
0.5
0.3
7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
4.6 0.1
(0.2) TYP
EXPOSED
13
24
THERMAL PAD
44X 0.5
12
25
4.975 0.1
(0.188)
PAD
PKG
2X
49
5.5
0.30
48X
36
0.18
1
SEE TERMINAL
DETAIL
0.1
C A B
48
37
0.05
SYMM
PIN 1 ID
(OPTIONAL)
0.5
0.3
48X
4223465/B 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048L
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.6)
(0.74)
(1.31)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
(1.45)
TYP
44X (0.5)
(0.786)
TYP
49
PKG
(4.975)
(0.188)
PAD
(6.8)
(R0.05)
TYP
(
0.2) TYP
VIA
12
25
13
24
SYMM
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223465/B 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048L
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48)
TYP
37
48
48X (0.6)
1
36
49
48X (0.24)
44X (0.5)
(1.57)
TYP
(6.8)
PKG
PAD
(0.188)
9X
(1.37)
(R0.05) TYP
METAL
TYP
12
25
13
24
9X (1.28)
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4223465/B 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RTA0040B
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
4.15±0.1
(0.2) TYP
11
20
36X 0.5
10
21
SYMM
41
2X
4.5
1
30
0.28
40X
PIN1 IDENTIFICATION
(OPTIONAL)
0.16
31
40
0.1
C A B
C
SYMM
0.5
0.3
40X
0.05
4219112/A 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
(
4.15)
40
31
40X (0.6)
40X (0.22)
1
30
36X (0.5)
SYMM
41
2X 2X
(4.5) (5.8)
2X
(0.685)
2X
(1.14)
(R0.05) TYP
10
21
12X (Ø0.2) VIA
TYP
11
20
2X (1.14)
2X (0.685)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219112/A 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTA0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
9X ( 1.17)
40
31
40X (0.6)
40X (0.22)
1
30
41
36X (0.5)
SYMM
2X 2X
(4.5) (5.8)
2X
(1.37)
(R0.05) TYP
10
21
EXPOSED
METAL
11
20
2X (1.37)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
71% PRINTED COVERAGE BY AREA
SCALE: 15X
4219112/A 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RTV0032E
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
B
A
PIN 1 INDEX AREA
5.15
4.85
SIDE WALL LEAD
METAL THICKNESS
DIM A
0.8
0.7
OPTION 1
0.1
OPTION 2
0.2
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(DIM A) TYP
3.45 0.1
(0.2) TYP
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
SYMM
33
3.5
0.30
32X
0.18
24
0.1
C A B
1
0.05
C
PIN 1 ID
(OPTIONAL)
32
25
SYMM
0.5
0.3
32X
4225196/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.24)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225196/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225196/A 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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