DRV8434 [TI]
48V, 2.5A bipolar stepper motor driver with integrated current sensing and 1/256 microstepping;
| 型号： | DRV8434 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 48V, 2.5A bipolar stepper motor driver with integrated current sensing and 1/256 microstepping |
| 文件： | 总55页 (文件大小：4088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8434
ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
具有集成电流检测、1/256 微步进、STEP/DIR 接口和智能调优技术的DRV8434
步进电机驱动器
DRV8434 采用内部电流检测架构，无需再使用两个外
部功率检测电阻，可缩小 PCB 面积并降低系统成本。
该器件使用内部PWM 电流调节方案，该方案能在智能
调优、慢速和混合衰减选项之间进行选择。智能调优可
通过自动调节实现出色的电流调节性能，并对电机变化
和老化效应进行补偿和减少电机的可闻噪声。
1 特性
• PWM 微步进电机驱动器
– 简单的STEP/DIR 接口
– 最高1/256 的微步进分度器
• 集成电流检测功能
– 无需检测电阻
– ±4% 满量程电流精度
借助简单的 STEP/DIR 接口，可通过外部控制器管理
步进电机的方向和步进速率。这款器件可配置为多种步
进模式，从全步进模式到 1/256 微步进模式皆可。该
器件通过专用的 nSLEEP 引脚提供低功耗睡眠模式。
提供的保护特性包括：电源欠压、电荷泵故障、过流、
短路、开路负载和过热保护。故障状态通过 nFAULT
引脚指示。
• 智能调优、慢速和混合衰减选项
• 工作电源电压范围为4.5V 至48V
• 低RDS(ON)：24V、25°C 时为330mΩHS + LS
• 高电流容量：2.5A 满量程、1.8A 均方根电流
• 与以下器件引脚对引脚兼容：
– DRV8426：33V，900mΩHS + LS
– DRV8436：48V，900mΩHS + LS
– DRV8424/25：33V，330/550mΩHS + LS
• 可配置关断时间PWM 斩波
器件信息
器件型号(1)
封装尺寸（标称值）
9.7mm x 4.4mm
4mm x 4mm
封装
DRV8434PWPR
DRV8434RGER
HTSSOP (28)
VQFN (24)
– 7μs、16μs、24μs 或32μs
• 支持1.8V、3.3V、5.0V 逻辑输入
• 低电流睡眠模式(2μA)
• 展频时钟，以降低EMI
• 小型封装和外形尺寸
• 保护特性
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– VM 欠压锁定(UVLO)
– 电荷泵欠压(CPUV)
– 过流保护(OCP)
– 开路负载检测(OL)
– 热关断(OTSD)
– 故障调节输出(nFAULT)
2 应用
简化版原理图
• 打印机和扫描仪
• ATM 和验钞机
• 纺织机
• 舞台照明设备
• 办公和家庭自动化
• 工厂自动化和机器人
• 医疗应用
• 3D 打印机
3 说明
DRV8434 是一款适用于工业和消费类应用的步进电机
驱动器。该器件由两个N 沟道功率MOSFET H 桥驱动
器、一个微步进分度器以及集成电流检测功能完全集
成。DRV8434 最高可驱动 2.5A 满量程输出电流（取
决于PCB 设计）。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE47
DRV8434
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
内容
8 Application and Implementation..................................32
8.1 Application Information............................................. 32
8.2 Typical Application.................................................... 32
9 Power Supply Recommendations................................38
9.1 大容量电容................................................................38
10 Layout...........................................................................39
10.1 Layout Guidelines................................................... 39
10.2 Layout Example...................................................... 39
11 Device and Documentation Support..........................41
11.1 Related Documentation...........................................41
11.2 接收文档更新通知................................................... 41
11.3 支持资源..................................................................41
11.4 Trademarks............................................................. 41
11.5 Electrostatic Discharge Caution..............................41
11.6 术语表..................................................................... 41
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
5.1 引脚功能......................................................................3
6 规格................................................................................... 5
6.1 绝对最大额定值...........................................................5
6.2 ESD 等级.................................................................... 5
6.3 建议运行条件.............................................................. 6
6.4 热性能信息..................................................................6
6.5 Electrical Characteristics.............................................7
6.6 Indexer Timing Requirements.....................................8
7 详细说明.......................................................................... 11
7.1 概述...........................................................................11
7.2 功能模块图................................................................12
7.3 特性说明....................................................................12
7.4 器件功能模式............................................................ 30
Information.................................................................... 42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2020) to Revision A (May 2022)
Page
• Updated Tri-Level and Quad-Level Input pin diagrams.................................................................................... 27
• Updated HTSSOP and QFN layout examples..................................................................................................39
• Added links to Related Documents section...................................................................................................... 41
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5 Pin Configuration and Functions
图5-1. PWP PowerPAD™ Package 28-Pin HTSSOP Top View
图5-2. RGE Package 24-Pin VQFN with Exposed Thermal PAD Top View
5.1 引脚功能
引脚
NO.
I/O
类型
说明
名称
HTSSOP
4、5
VQFN
AOUT1
AOUT2
PGND
BOUT2
BOUT1
CPH
3
4
O
O
绕组A 输出。连接到步进电机绕组。
绕组A 输出。连接到步进电机绕组。
电源接地。连接到系统接地。
输出
输出
电源
输出
输出
6、7
3、12
8, 9
2、7
5
—
O
O
绕组B 输出。连接到步进电机绕组。
绕组B 输出。连接到步进电机绕组。
6
10、11
28
23
22
19
电荷泵开关节点。在CPH 到CPL 之间连接一个额定电压为VM 的
X7R 0.022µF 陶瓷电容器。
—
电源
CPL
27
DIR
24
I
I
方向输入。逻辑电平设置步进的方向；内部下拉电阻。
输入
输入
逻辑低电平将禁用器件输出；逻辑高电平则会启用；内部上拉至
DVDD。还将决定OCP 和OTSD 响应的类型。
ENABLE
25
20
逻辑电源电压。通过电容为0.47μF 至1μF、额定电压为6.3V 或
10V 的X7R 陶瓷电容器连接至GND。
DVDD
GND
15
14
10
9
—
—
电源
电源
器件接地。连接到系统接地。
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引脚
NO.
I/O
类型
说明
名称
HTSSOP
VQFN
电流设定基准输入。最大值为3.3V。DVDD 可用于通过电阻分压器提
供VREF。
VREF
17
12
I
I
输入
输入
M0
18
22
21
20
23
1
13
17
16
15
18
24
微步进模式设置引脚。设置步进模式；内部下拉电阻。
M1
DECAY0
DECAY1
STEP
VCP
I
衰减模式设置引脚。设置衰减模式（请参阅节7.3.6 部分）。
输入
I
步进输入。上升沿使分度器前进一步；内部下拉电阻。
输入
电源
电荷泵输出。通过一个X7R 0.22μF 16V 陶瓷电容器连接至VM。
—
电源。连接到电机电源电压，并通过两个0.01µF 陶瓷电容器（每个
引脚一个）和一个额定电压为VM 的大容量电容器旁路到PGND。
VM
2、13
19
1、8
14
—
I
电源
输入
设置电流斩波期间的衰减模式关断时间；四电平引脚。还将设置智能
调优纹波控制模式中的纹波电流。
TOFF
nFAULT
故障指示。故障状态下拉低逻辑低电平；开漏输出需要外部上拉电
阻。
16
11
O
漏极开路
睡眠模式输入。逻辑高电平用于启用器件；逻辑低电平用于进入低功
耗睡眠模式；内部下拉电阻。nSLEEP 低电平脉冲将清除故障。
nSLEEP
PAD
26
-
21
-
I
输入
-
-
散热焊盘。连接到系统接地。
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6 规格
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内（除非另有说明）(1)
最小值
–0.3
–0.3
–0.3
–0.3
-0.3
最大值
单位
50
V
电源电压(VM)
VVM + 7
VVM
V
V
电荷泵电压（VCP、CPH）
电荷泵负开关引脚(CPL)
VVM
V
nSLEEP 引脚电压(nSLEEP)
5.75
V
内部稳压器电压(DVDD)
-0.3
5.75
V
控制引脚电压（STEP、DIR、ENABLE、nFAULT、DECAY0、DECAY1、TOFF、M0、M1）
开漏输出电流(nFAULT)
0
10
mA
V
-0.3
5.75
基准输入引脚电压(VREF)
VVM + 1
VVM + 3
V
连续相节点引脚电压（AOUT1、AOUT2、BOUT1、BOUT2）
瞬态100ns 相节点引脚电压（AOUT1、AOUT2、BOUT1、BOUT2）
峰值驱动电流（AOUT1、AOUT2、BOUT1、BOUT2）
工作环境温度，TA
–1
–3
V
A
受内部限制
-40
-40
-65
125
150
150
°C
°C
°C
运行结温，TJ
贮存温度，Tstg
(1) 应力超出绝对最大额定值下所列的值可能会对器件造成永久损坏。这些列出的值仅仅是应力额定值，这并不表示器件在这些条件下以及
在建议运行条件以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
6.2 ESD 等级
值
单位
±2000
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001
充电器件模型(CDM)，符合JEDEC 规范JESD22-C101
PWP 转角引脚（1、14、
15 和28）
V(ESD)
V
±750
±500
静电放电
其他引脚
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6.3 建议运行条件
在自然通风条件下的工作温度范围内测得（除非另有说明）
最小值
4.5
最大值
单位
V
VVM
VI
48
5.5
可确保正常（直流）运行的电源电压范围
逻辑电平输入电压
0
V
VVREF
fSTEP
0.05
3.3
V
VREF 电压
0
500(1)
kHz
施加的STEP 信号(STEP)
IFS
Irms
TA
TJ
0
2.5(2)
1.8(2)
125
A
A
电机满量程电流(xOUTx)
电机均方根电流(xOUTx)
工作环境温度
0
-40
-40
°C
°C
150
工作结温
(1) STEP 输入工作频率最高可达500kHz，但系统带宽受电机负载限制
(2) 必须遵守功耗和热限值
6.4 热性能信息
PWP (HTSSOP)
28 引脚
RGE (VQFN)
热指标(1)
单位
24 引脚
RθJA
29.7
39.0
°C/W
°C/W
结至环境热阻
Rθ
23.0
28.9
结至外壳（顶部）热阻
JC(top)
RθJB
ψJT
9.3
0.3
9.2
16.0
0.4
°C/W
°C/W
°C/W
结至电路板热阻
结至顶部特征参数
结至电路板特征参数
15.9
ψJB
Rθ
2.4
3.4
°C/W
结至外壳（底部）热阻
JC(bot)
(1) 有关新旧热指标的更多信息，请参阅《半导体和IC 封装热指标》应用报告。
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6.5 Electrical Characteristics
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD)
IVM
VM operating supply current
ENABLE = 1, nSLEEP = 1, No motor load
5
2
6.5
4
mA
μA
μs
IVMQ
tSLEEP
VM sleep mode supply current nSLEEP = 0
Sleep time
nSLEEP = 0 to sleep-mode
nSLEEP low to clear fault
120
20
tRESET
nSLEEP reset pulse
40
μs
ms
ms
tWAKE
tON
Wake-up time
Turn-on time
nSLEEP = 1 to output transition
VM > UVLO to output transition
0.8
0.8
1.2
1.2
tEN
Enable time
ENABLE = 0/1 to output transition
5
μs
No external load, 6
V < VVM < 48V
4.75
4.2
5
5.25
V
VDVDD
Internal regulator voltage
No external load,
VVM = 4.5V
4.35
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP
f(VCP)
VCP operating voltage
6 V < VVM < 48 V
VVM + 5
360
V
Charge pump switching
frequency
VVM > UVLO; nSLEEP = 1
kHz
LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP)
VIL
VIH
VHYS
IIL
Input logic-low voltage
Input logic-high voltage
Input logic hysteresis
Input logic-low current
Input logic-high current
0
0.6
5.5
V
1.5
V
150
mV
μA
μA
VIN = 0 V
VIN = 5 V
1
–1
IIH
100
TRI-LEVEL INPUTS (M0, DECAY0, DECAY1, ENABLE)
VI1
VI2
VI3
IO
Input logic-low voltage
Input Hi-Z voltage
Tied to GND
Hi-Z
0
0.6
2.2
5.5
V
V
1.8
2.7
2
Input logic-high voltage
Output pull-up current
Tied to DVDD
V
10
μA
QUAD-LEVEL INPUTS (M1, TOFF)
VI1
VI2
VI3
VI4
IIL
Input logic-low voltage
Tied to GND
330kΩ ± 5% to GND
Hi-Z
0
0.6
1.4
2.2
5.5
V
V
1
1.25
2
Input Hi-Z voltage
1.8
2.7
V
Input logic-high voltage
Output pull-up current
Tied to DVDD
V
10
μA
CONTROL OUTPUTS (nFAULT)
VOL
IOH
Output logic-low voltage
Output logic-high leakage
IO = 5 mA
0.5
1
V
–1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
TJ = 25 °C, IO = -1 A
165
250
280
200
300
350
mΩ
mΩ
mΩ
RDS(ON)
High-side FET on resistance
TJ = 125 °C, IO = -1 A
TJ = 150 °C, IO = -1 A
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Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
165
250
280
MAX
200
300
350
UNIT
TJ = 25 °C, IO = 1 A
mΩ
RDS(ON)
Low-side FET on resistance
TJ = 125 °C, IO = 1 A
TJ = 150 °C, IO = 1 A
mΩ
mΩ
VVM = 24 V, IO = 1 A, Between 10% and
90%
tSR
Output slew rate
240
V/µs
PWM CURRENT CONTROL (VREF)
KV
Transimpedance gain
VREF Leakage Current
VREF = 3.3 V
VREF = 3.3 V
1.254
1.32
1.386
8.25
V/A
IVREF
μA
TOFF = 0
7
TOFF = 1
16
24
32
tOFF
PWM off-time
μs
TOFF = Hi-Z
TOFF = 330 kΩto GND
0.25 A < IO < 0.5 A
12
6
–12
–6
0.5 A < IO < 1 A
1 A < IO < 2.5 A
Current trip accuracy
%
%
ΔITRIP
4
–4
AOUT and BOUT current
matching
IO,CH
IO = 2.5 A
2.5
–2.5
PROTECTION CIRCUITS
VM falling, UVLO falling
VM rising, UVLO rising
Rising to falling threshold
VCP falling; CPUV report
Current through any FET
4.1
4.2
4.25
4.35
4.35
4.45
VUVLO
VM UVLO lockout
V
VUVLO,HYS Undervoltage hysteresis
100
mV
V
VCPUV
IOCP
tOCP
tRETRY
tOL
Charge pump undervoltage
Overcurrent protection
Overcurrent deglitch time
Overcurrent retry time
Open load detection time
Open load current threshold
Thermal shutdown
VVM + 2
4
A
2
4
μs
ms
ms
mA
°C
°C
50
IOL
75
165
20
TOTSD
Die temperature TJ
150
180
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ
6.6 Indexer Timing Requirements
Typical limits are at TJ = 25°C and VVM = 24 V. Over recommended operating conditions unless otherwise noted.
NO.
MIN
MAX
UNIT
kHz
ns
1
Step frequency
500(1)
ƒSTEP
2
tWH(STEP)
tWL(STEP)
tSU(DIR, Mx)
tH(DIR, Mx)
Pulse duration, STEP high
970
970
200
200
3
Pulse duration, STEP low
ns
4
Setup time, DIR or MODEx to STEP rising
Hold time, DIR or MODEx to STEP rising
ns
5
ns
(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load.
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图6-1. STEP and DIR Timing Diagram
6.6.1 典型特性
图6-2. 睡眠电流与电源电压间的关系
图6-3. 睡眠电流与温度间的关系
图6-4. 工作电流与电源电压间的关系
图6-5. 工作电流与温度间的关系
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6.6.1 典型特性(continued)
图6-6. 低侧RDS(ON) 与电源电压间的关系（MODE = 0 或330k 至
GND）
图6-7. 低侧RDS(ON) 与温度间的关系（MODE = 0 或330k 至
GND）
图6-8. 高侧RDS(ON) 与电源电压间的关系（MODE = 0 或330k 至
GND）
图6-9. 高侧RDS(ON) 与温度间的关系（MODE = 0 或330k 至
GND）
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7 详细说明
7.1 概述
DRV8434 是一款用于双极步进电机的集成电机驱动器解决方案。该器件通过集成两个 N 沟道功率 MOSFET H
桥、电流检测电阻和调节电路以及一个微步进分度器，可更大程度提高集成度。DRV8434 与 DRV8426、
DRV8436 和 DRV8424/25 引脚对引脚兼容。DRV8434 能够支持 4.5V 至 48V 的宽电源电压范围。DRV8434 提
供高达 4A 峰值、2.5A 满量程或 1.8A 均方根(rms) 的输出电流。实际的满量程和均方根电流取决于环境温度、电
源电压和PCB 热性能。
DRV8434 采用集成式电流检测架构，无需再使用两个外部功率检测电阻，从而显著节省布板空间和 BOM 成本，
并减少设计工作量和降低功耗。该架构通过使用电流镜方法消除了检测电阻中的功率损耗，并使用内部功率
MOSFET 进行电流检测。通过VREF 引脚处的电压来调节电流调节设定点。
借助简单的 STEP/DIR 接口，可通过外部控制器管理步进电机的方向和步进速率。内部微步进分度器可以执行高
精度微步进，而无需外部控制器来管理绕组电流电平。分度器可实现全步进、半步进以及 1/4、1/8、1/16、
1/32、1/64、1/128 和1/256 微步进。高微步进有助于显著降低可闻噪声并实现平稳的运动。除了标准的半步进模
式，非循环半步进模式可用于在较高的电机转速下增加扭矩输出。
步进电机驱动器需要通过实现多种类型的衰减模式（如慢速衰减、混合衰减和快速衰减）来再循环绕组电流。
DRV8434 提供智能调优衰减模式。自动调优是一种创新的衰减机制，能够自动调节以实现出色的电流调节性能，
而不受电压、电机转速、变化和老化效应的影响。自动调优纹波控制使用可变关断时间纹波电流控制方案，以更
大限度地减少电机绕组电流的失真。自动调优动态衰减使用固定关断时间动态快速衰减百分比方案，以更大限度
地减少电机绕组电流的失真，同时实现频率成分最小化并显著减少设计工作量。除了该无缝的轻松自动智能调优
之外，DRV8434 还提供传统的衰减模式（如慢速混合衰减和混合衰减）。
该器件为内部数字振荡器和内部电荷泵集成了展频时钟特性。此特性可更大程度减少器件的辐射发射。系统包括
一个低功耗睡眠模式，以便在不主动驱动电机时节省功耗。
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7.2 功能模块图
7.3 特性说明
表7-1 列出了DRV8434 的推荐外部组件。
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表7-1. 外部组件
组件
CVM1
引脚1
VM
引脚2
PGND
PGND
VM
推荐
两个额定电压为VM 的X7R 0.01µF 陶瓷电容器
额定电压为VM 的大容量电容器
CVM2
VM
CVCP
VCP
X7R 0.22µF 16V 陶瓷电容器
CSW
CPH
CPL
额定电压为VM 的X7R 0.022µF 陶瓷电容器
电容为0.47µF 至1µF 的X7R 6.3V 陶瓷电容器
>4.7kΩ 电阻
CDVDD
DVDD
VCC (1)
VREF
VREF
GND
RnFAULT
RREF1
nFAULT
VCC
用于限制斩波电流的电阻。建议：RREF1 和RREF2 的并联电阻应低于50kΩ。
GND
RREF2（可选）
(1) VCC 不是该器件上的引脚，但开漏输出nFAULT 需要VCC 电源电压上拉；nFAULT 可能会被上拉到DVDD。
7.3.1 Stepper Motor Driver Current Ratings
Stepper motor drivers can be classified using three different numbers to describe the output current: peak, RMS,
and full-scale.
7.3.1.1 峰值电流额定值
步进驱动器中的峰值电流受过流保护关断阈值 IOCP 的限制。峰值电流表示任何瞬态持续电流脉冲，例如当对电容
充电时，或当总占空比非常低时。通常，IOCP 的最小值指定了步进电机驱动器的峰值电流额定值。对于
DRV8434，每个电桥的峰值电流额定值为4A。
7.3.1.2 均方根电流额定值
均方根（平均）电流由集成电路的热特性决定。均方根电流是根据典型系统中 RDS(ON)、上升和下降时间、PWM
频率、器件静态电流和25°C 温度下的封装热性能计算的。实际的均方根电流可能更高或更低，具体取决于散热和
环境温度。对于DRV8434，每个电桥的均方根电流额定值为1.8A。
7.3.1.3 Full-Scale Current Rating
Full-scale current
RMS current
AOUT
BOUT
Step Input
图7-1. Full-Scale and RMS Current
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7.3.2 PWM Motor Drivers
图7-2. PWM Motor Driver Block Diagram
7.3.3 Microstepping Indexer
Built-in indexer logic in the device allows a number of different step modes. The M0 and M1 pins are used to
configure the step mode as shown below. The settings can be changed on the fly.
表7-2. Microstepping Indexer Settings
M0
M1
STEP MODE
0
Full step (2-phase excitation) with 100%
current
0
0
Full step (2-phase excitation) with 71%
current
330 kΩ to
GND
1
Hi-Z
0
0
0
1
1
1
Non-circular 1/2 step
1/2 step
1/4 step
1
1/8 step
Hi-Z
1/16 step
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表7-2. Microstepping Indexer Settings (continued)
M0
M1
STEP MODE
0
Hi-Z
1/32 step
1/64 step
Hi-Z
330kΩ to
GND
Hi-Z
1
Hi-Z
Hi-Z
1/128 step
1/256 step
表 7-3 shows the relative current and step directions for full-step (71% current), 1/2 step, 1/4 step and 1/8 step
operation. Higher microstepping resolutions follow the same pattern. The AOUT current is the sine of the
electrical angle and the BOUT current is the cosine of the electrical angle. Positive current is defined as current
flowing from the xOUT1 pin to the xOUT2 pin while driving.
At each rising edge of the STEP input the indexer advances to the next state in the table. The direction shown is
with the DIR pin logic high. If the DIR pin is logic low, the sequence table is reversed.
备注
If the step mode is changed dynamically while stepping, the indexer advances to the next valid state
for the new step mode setting at the rising edge of STEP.
The initial excitation state is an electrical angle of 45°, corresponding to 71% of full-scale current in both coils.
This state is entered immediately after power-up, after exiting logic undervoltage lockout, or after exiting sleep
mode.
表7-3. Relative Current and Step Directions
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
ELECTRICAL
ANGLE (DEGREES)
1/8 STEP
1/4 STEP
1/2 STEP
FULL STEP 71%
1
2
1
1
0%
20%
38%
56%
71%
83%
92%
98%
100%
98%
92%
83%
71%
56%
38%
20%
0%
100%
98%
0.00
11.25
3
2
3
92%
22.50
4
83%
33.75
5
2
3
4
5
6
1
71%
45.00
6
56%
56.25
7
4
38%
67.50
8
20%
78.75
9
5
0%
90.00
10
11
12
13
14
15
16
17
18
19
20
21
22
23
-20%
-38%
-56%
-71%
-83%
-92%
-98%
-100%
-98%
-92%
-83%
-71%
-56%
-38%
101.25
112.50
123.75
135.00
146.25
157.50
168.75
180.00
191.25
202.50
213.75
225.00
236.25
247.50
6
7
2
8
9
-20%
-38%
-56%
-71%
-83%
-92%
10
11
12
3
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表7-3. Relative Current and Step Directions (continued)
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
ELECTRICAL
ANGLE (DEGREES)
1/8 STEP
1/4 STEP
1/2 STEP
FULL STEP 71%
24
25
26
27
28
29
30
31
32
-98%
-100%
-98%
-92%
-83%
-71%
-56%
-38%
-20%
-20%
0%
258.75
13
14
15
16
7
270.00
20%
38%
56%
71%
83%
92%
98%
281.25
292.50
303.75
8
4
315.00
326.25
337.50
348.75
表 7-4 shows the full step operation with 100% full-scale current. This stepping mode consumes more power
than full-step mode with 71% current, but provides a higher torque at high motor RPM.
表7-4. Full Step with 100% Current
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
ELECTRICAL ANGLE
(DEGREES)
FULL STEP 100%
1
2
3
4
100
100
100
-100
-100
100
45
135
225
315
-100
-100
表 7-5 shows the noncircular 1/2–step operation. This stepping mode consumes more power than circular 1/2-
step operation, but provides a higher torque at high motor RPM.
表7-5. Non-Circular 1/2-Stepping Current
NON-CIRCULAR 1/2-STEP
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
ELECTRICAL ANGLE
(DEGREES)
1
2
3
4
5
6
7
8
0
100
100
0
0
100
100
100
0
45
90
135
180
225
270
315
–100
–100
–100
0
–100
–100
–100
100
7.3.4 Controlling VREF with an MCU DAC
In some cases, the full-scale output current may need to be changed between many different values, depending
on motor speed and loading. The voltage of the VREF pin can be adjusted in the system to change the full-scale
current.
In this mode of operation, as the DAC voltage increases, the full-scale regulation current increases as well. For
proper operation, the output of the DAC must not exceed 3.3 V.
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图7-3. Controlling VREF with a DAC Resource
The VREF pin can also be adjusted using a PWM signal and low-pass filter.
图7-4. Controlling VREF With a PWM Resource
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7.3.5 电流调节
流经电机绕组的电流由一个可调节关断时间的 PWM 电流调节电路进行调节。当 H 桥被启用时，通过绕组的电流
以一定的速率上升，该速率取决于直流电压、绕组电感和存在的反电动势大小。当电流达到电流调节阈值时，电
桥将进入衰减模式以减小电流，该模式的持续时间取决于 TOFF 引脚设置。关断时间结束后，将重新启用电桥，
开始另一个PWM 循环。
图7-5. 电流斩波波形
PWM 调节电流由比较器设置，该比较器监测与低侧功率 MOSFET 并联的电流检测 MOSFET 两端的电压。电流
检测 MOSFET 通过基准电流进行偏置，该基准电流是电流模式正弦加权 DAC 的输出，其满量程基准电流通过
VREF 引脚的电压进行设置。
您可以使用以下公式计算满量程调节电流(IFS)：IFS (A) = VREF (V)/KV (V/A) = VREF (V)/1.32 (V/A)。
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7.3.6 Decay Modes
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current
chopping threshold is reached. This is shown in 图7-6, Item 1.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses
state to allow winding current to flow in a reverse direction. Fast decay mode is shown in 图 7-6, item 2. In slow
decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown
in 图7-6, Item 3.
图7-6. Decay Modes
The decay mode of the DRV8434 is selected by the DECAY0 and DECAY1 pins as shown in 表 7-6. If DECAY1
pin is Hi-Z, irrespective of the DECAY0 pin voltage, the decay mode will be smart tune dynamic decay. The
decay modes can be changed on the fly. After a decay mode change, the new decay mode is applied after a 10
µs de-glitch time.
表7-6. Decay Mode Settings
DECAY0
DECAY1
INCREASING STEPS
DECREASING
STEPS
0
0
0
1
0
1
0
1
Smart tune Dynamic Smart tune Dynamic
Decay
Decay
Smart tune Ripple
Control
Smart tune Ripple
Control
1
Mixed decay: 30%
fast
Mixed decay: 30%
fast
1
Mixed decay: 30%
fast
Slow decay
Hi-Z
Hi-Z
Mixed decay: 60%
fast
Mixed decay: 60%
fast
Slow decay
Slow decay
图 7-7 defines increasing and decreasing current. For the slow-mixed decay mode, the decay mode is set as
slow during increasing current steps and mixed decay during decreasing current steps. In full step and
noncircular 1/2-step operation, the decay mode corresponding to decreasing steps is always used.
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Increasing Decreasing
Increasing Decreasing
STEP Input
Decreasing
Increasing
Increasing Decreasing
STEP Input
图7-7. Definition of Increasing and Decreasing Steps
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7.3.6.1 Slow Decay for Increasing and Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
图7-8. Slow/Slow Decay Mode
During slow decay, both low-side MOSFETs of the H-bridge are turned on, allowing the current to be
recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However on decreasing current
steps, slow decay will take a long time to settle to the new ITRIP level because the current decreases very slowly.
If the current at the end of the off time is above the ITRIP level, slow decay will be extended for multiple off time
duration, until the current at the end of the cumulative off time is below the ITRIP level.
When the winding current is held static for a long time (for example while no STEP input is present), or at very
low step rates, slow decay may not properly regulate the current because back-EMF will be small or absent
across the motor windings. The motor current can rise rapidly, and may require an extremely long off-time. In
some cases this could result in loss of current regulation. An aggressive decay mode is recommended in such
cases.
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7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
ITRIP
tBLANK
tFAST
tBLANK
tDRIVE
tFAST
tDRIVE
tOFF
tOFF
图7-9. Slow-Mixed Decay Mode
Mixed decay begins as fast decay for an initial duration of the tOFF, followed by slow decay for the remainder of
the tOFF time. Mixed decay only occurs during decreasing current. Slow decay is used for increasing current.
This decay mode exhibits the same current ripple as slow decay mode does for increasing current, because for
increasing current, only slow decay is used in this mode. For decreasing current, the ripple is larger than slow
decay, but smaller than fast decay. On decreasing current steps, mixed decay settles to the new ITRIP level faster
than slow decay.
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7.3.6.3 上升和下降电流阶段均为混合衰减
ITRIP
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tDRIVE
tFAST
tOFF
tOFF
图7-10. 混合-混合衰减模式
混合衰减下，开始的一段时间为快速衰减，然后在剩余的 tOFF 内慢速衰减。在此模式下，上升和下降电流阶跃都
会发生混合衰减。
该模式表现出的纹波比慢速衰减大，但比快速衰减小。在下降电流阶跃时，混合衰减可比慢速衰减更快地稳定到
新的ITRIP 电平。
如果电流保持很长时间（STEP 引脚无输入）或步进速度非常慢，则慢速衰减可能无法正确调节电流，因为电机
绕组上不存在反电动势。在这种状态下，电机电流上升速度会非常快，需要极长的关断时间。当电机绕组上没有
反电动势时，上升或下降混合衰减模式能持续调节电流电平。
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7.3.6.4 Smart tune Dynamic Decay
The smart tune current regulation schemes are advanced current-regulation control methods compared to
traditional fixed off-time current regulation schemes. Smart tune current regulation schemes help the stepper
motor driver adjust the decay scheme based on operating factors such as the ones listed as follows:
• Motor winding resistance and inductance
• Motor aging effects
• Motor dynamic speed and load
• Motor supply voltage variation
• Motor back-EMF difference on rising and falling steps
• Step transitions
• Low-current versus high-current dI/dt
The device provides two different smart tune current regulation modes, named smart tune Dynamic Decay and
smart tune Ripple Control.
ITRIP
tBLANK
tDRIVE
tBLANK
tBLANK
tDRIVE
tOFF
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tFAST
tFAST
图7-11. Smart tune Dynamic Decay Mode
Smart tune Dynamic Decay greatly simplifies the decay mode selection by automatically configuring the decay
mode between slow, mixed, and fast decay. In mixed decay, smart tune dynamically adjusts the fast decay
percentage of the total mixed decay time. This feature eliminates motor tuning by automatically determining the
best decay setting that results in the lowest ripple for the motor.
The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip
level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle to prevent
regulation loss. If a long drive time must occur to reach the target trip level, the decay mode becomes less
aggressive (remove fast decay percentage) on the next cycle to operate with less ripple and more efficiently. On
falling steps, smart tune Dynamic Decay automatically switches to fast decay to reach the next step quickly.
Smart tune Dynamic Decay is optimal for applications that require minimal current ripple but want to maintain a
fixed frequency in the current regulation scheme.
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7.3.6.5 智能调优纹波控制
ITRIP
IVALLEY
tBLANK
tDRIVE
tBLANK
tBLANK
tDRIVE
tBLANK
tDRIVE
tOFF
tOFF
tOFF
tDRIVE
ITRIP
IVALLEY
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
图7-12. 智能调优纹波控制衰减模式
智能调优纹波控制通过在 ITRIP 电平旁设置一个 IVALLEY 电平来进行操作。当电流电平达到 ITRIP 时，驱动器将进入
慢速衰减，直到达到 IVALLEY，而不是直到 tOFF 时间结束。慢速衰减的工作原理类似于模式 1，其中两个低侧
MOSFET 都导通，允许电流再循环。在此模式下，tOFF 根据电流电平和运行条件而变化。
通过TOFF 引脚对该衰减模式下的纹波电流进行编程。纹波电流取决于特定微步进级别的ITRIP。
表7-7. 电流纹波设置
TOFF
特定微步进级别下的电流纹波
19mA + ITRIP 的1%
19mA + ITRIP 的2%
19mA + ITRIP 的4%
19mA + ITRIP 的6%
0
1
高阻态
330kΩ 至GND
该纹波控制方法可以更严格地调节电流电平，从而提高电机效率和系统性能。智能调优纹波控制适用于能够承受
可变关断时间调节方案的系统，以在电流调节中实现小电流纹波。选择低纹波电流设置可确保 PWM 频率不处于
可闻范围之内。不过，较高的纹波电流值会降低PWM 频率，从而降低开关损耗。
7.3.6.6 PWM 关断时间
除智能调优纹波控制模式外，TOFF 引脚将配置所有衰减模式的 PWM 关断时间，如表 7-8 所示。该器件支持动
态更改关断时间。在更改关断时间设置后，新的关断时间设置将在10µs 的抗尖峰脉冲时间之后生效。
表7-8. 关断时间设置
TOFF
关断时间
0
7µs
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表7-8. 关断时间设置(continued)
TOFF
1
关断时间
16µs
Hi-Z
24µs
32µs
330kΩ 至GND
7.3.6.7 消隐时间
在 H 桥接通电流（驱动阶段开始）后，电流检测比较器将在启用电流检测电路前被忽略一段时间 (tBLANK)。消隐
时间还将设置PWM 的最小驱动时间。消隐时间大约为1µs。
7.3.7 电荷泵
集成了一个电荷泵以提供高侧N 沟道MOSFET 栅极驱动电压。需要在VM 和VCP 引脚之间为电荷泵放置一个电
容作为储能电容。此外，还需要在CPH 和CPL 引脚之间放置一个陶瓷电容作为飞跨电容。
图7-13. 电荷泵方框图
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7.3.8 线性稳压器
DVDD 器件中集成了一个线性稳压器。DVDD 稳压器可用于提供 VREF 基准电压。DVDD 最大可提供 2mA 的负
载。为确保正常运行，请使用陶瓷电容器将DVDD 引脚旁路至GND。
DVDD 输出的标称值为5V。当DVDD LDO 电流负载超过2mA 时，输出电压会显著下降。
图7-14. 线性稳压器方框图
如果数字输入必须永久连接高电平（即 Mx、DECAYx 或 TOFF），则最好将输入连接到 DVDD 引脚而不是外部
稳压器。在未应用 VM 引脚或处于睡眠模式时，此方法可省电：DVDD 稳压器被禁用，电流不会流经输入下拉电
阻。逻辑电平输入的典型下拉电阻为200kΩ。
请勿将nSLEEP 引脚连接至DVDD，否则器件将无法退出睡眠模式。
7.3.9 Logic Level, Tri-Level and Quad-Level Pin Diagrams
图7-15 shows the input structure for M0, DECAY0 and ENABLE pins.
图7-15. Tri-Level Input Pin Diagram
图7-16 shows the input structure for DECAY1 pin.
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图7-16. DECAY1 Pin Diagram
图7-17 shows the input structure for M1 and TOFF pins.
图7-17. Quad-Level Input Pin Diagram
图7-18 shows the input structure for STEP, DIR and nSLEEP pins.
图7-18. Logic-Level Input Pin Diagram
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7.3.9.1 nFAULT 引脚
nFAULT 引脚具有开漏输出且应上拉至 5V、3.3V 或 1.8V 电源电压。当检测到故障时，nFAULT 引脚将变成逻辑
低电平；上电后，则变成高电平。对于5V 上拉，nFAULT 引脚可通过一个电阻连接至DVDD 引脚。对于3.3V 或
1.8V 上拉，必须使用一个外部电源。
Output
nFAULT
图7-19. nFAULT 引脚
7.3.10 保护电路
DRV8434 器件可完全防止电源欠压、电荷泵欠压、输出过流、开路负载和器件过热事件。
7.3.10.1 VM 欠压锁定(UVLO)
无论 VM 引脚电压何时降至电源电压的 UVLO 阈值电压以下，都会禁用所有输出并将 nFAULT 引脚驱动为低电
平。在这种情况下，电荷泵会禁用。VM 欠压条件消失后，器件将恢复正常运行（电机驱动器运行并释放nFAULT
引脚）。
7.3.10.2 VCP 欠压锁定(CPUV)
无论 VCP 引脚电压何时降至 CPUV 电压以下，都会禁用所有输出并将 nFAULT 引脚驱动为低电平。在这种情况
下，电荷泵将保持有效状态。VCP 欠压条件消失后，器件将恢复正常运行（电机驱动器运行且释放 nFAULT 引
脚）。
7.3.10.3 过流保护(OCP)
每个 MOSFET 上的模拟电流限制电路通过移除栅极驱动来限制通过 MOSFET 的电流。如果此电流限制的持续时
间超过 tOCP，则会禁用两个 H 桥中的 MOSFET 并将 nFAULT 引脚驱动为低电平。在这种情况下，电荷泵将保持
运行状态。过流保护可在两种不同的模式下运行：锁存关断和自动重试。该器件支持动态更改工作模式。
7.3.10.3.1 锁存关断
必须将 ENABLE 引脚设置为高阻态，才能选择锁存关断模式。在此模式下，OCP 事件后将会禁用输出并将
nFAULT 引脚驱动为低电平。一旦 OCP 条件消除，器件会在应用 nSLEEP 复位脉冲或下电上电后恢复正常运
行。
7.3.10.3.2 自动重试
必须将 ENABLE 引脚设置为高电平 (>2.7V)，才能选择自动重试模式。在此模式下，OCP 事件后将会禁用输出并
将 nFAULT 引脚驱动为低电平。在经过 tRETRY 时间且故障条件消失后，器件将自动恢复正常运行（电机驱动器运
行且释放nFAULT 引脚）。
7.3.10.4 开路负载检测(OL)
如果任何线圈中的绕组电流降至开路负载电流阈值 (IOL) 和分度器设置的 ITRIP 电平之下，并且持续时长超过开路
负载检测时间(tOL)，则表明检测到开路负载条件。
ENABLE 引脚连接到 DVDD 后，如果开路负载条件消失，nFAULT 线路会被立即释放。ENABLE 引脚为高阻态
时，如果开路负载条件消失，并且已应用 nSLEEP 复位脉冲，nFAULT 线路会被释放。当器件下电上电或退出睡
眠模式时，该故障也会清除。
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7.3.10.5 热关断(OTSD)
如果内核温度超过热关断限值(TOTSD)，则会禁用H 桥中的所有MOSFET 并将nFAULT 引脚驱动为低电平。在这
种情况下，电荷泵会被禁用。热关断保护可在两种不同的模式下运行：锁存关断和自动重试。该器件支持动态更
改工作模式。
7.3.10.5.1 锁存关断
必须将 ENABLE 引脚设置为高阻态，才能选择锁存关断模式。在此模式下，OTSD 事件后将会禁用相关输出并将
nFAULT 引脚驱动为低电平。结温降至过热阈值限值减去迟滞 (TOTSD – THYS_OTSD) 所得的值以下后，器件会在
应用nSLEEP 复位脉冲或功率循环后恢复正常运行。
7.3.10.5.2 自动重试
必须将 ENABLE 引脚设置为高电平 (>2.7V)，才能选择自动重试模式。在此模式下，OTSD 事件后将会禁用所有
输出并将 nFAULT 引脚驱动为低电平。结温降至过热阈值限值减去迟滞 (TOTSD – THYS_OTSD) 所得的值以下后，
器件将恢复正常运行（电机驱动器运行且释放nFAULT 线路）。
Fault Condition Summary
表7-9. Fault Condition Summary
FAULT
CONDITION
VM < VUVLO
VCP < VCPUV
CONFIGURATION
ERROR
REPORT
H-BRIDGE CHARGE
PUMP
INDEXER LOGIC
RECOVERY
VM
undervoltage
(UVLO)
Reset
(VDVDD
3.9 V)
Automatic: VM >
VUVLO
nFAULT
nFAULT
Disabled
Disabled
Disabled
Disabled
<
—
—
VCP
undervoltage
(CPUV)
Automatic: VCP
> VCPUV
Operating Operating Operating
ENABLE = Hi-Z
ENABLE = 1
nFAULT
nFAULT
Disabled
Disabled
Operating Operating Operating
Operating Operating Operating
Latched
Overcurrent
(OCP)
IOUT > IOCP
Automatic retry:
tRETRY
No load
detected
Open Load (OL)
nFAULT
nFAULT
Operating Operating Operating Operating
Report only
—
ENABLE = Hi-Z
Disabled
Disabled
Disabled
Disabled
Operating Operating
Operating Operating
Latched
Thermal
Shutdown
(OTSD)
Automatic: TJ <
TJ > TTSD
ENABLE = 1
nFAULT
TOTSD
-
THYS_OTSD
7.4 器件功能模式
7.4.1 睡眠模式(nSLEEP = 0)
DRV8434 器件将通过 nSLEEP 引脚实现状态管理。当 nSLEEP 引脚为低电平时，DRV8434 器件将进入低功耗
睡眠模式。在睡眠模式下，将会禁用所有内部 MOSFET 和电荷泵。必须在 nSLEEP 引脚触发下降沿之后再过去
t
SLEEP 时间后，器件才能进入睡眠模式。如果 nSLEEP 引脚变为高电平，DRV8434 器件会自动退出睡眠模式。
必须在经过tWAKE 时间之后，器件才能针对输入做好准备。
7.4.2 禁用模式（nSLEEP = 1，ENABLE = 0）
ENABLE 引脚用于启用或禁用DRV8434。当ENABLE 引脚为低电平时，输出驱动器将在高阻态状态下被禁用。
7.4.3 工作模式（nSLEEP = 1，ENABLE = Hi-Z/1）
当 nSLEEP 引脚为高电平、ENABLE 引脚为 Hi-Z 或 1 且 VM > UVLO 时，器件将进入运行模式。必须在经过
t
WAKE 时间之后，器件才能针对输入做好准备。
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7.4.4 nSLEEP 复位脉冲
锁存故障可通过 nSLEEP 复位脉冲清除。该脉冲的宽度必须在 20µs 至 40µs 之间。如果 nSLEEP 在 40µs 至
120µs 的时间内保持低电平，则会清除故障，但器件有可能会关断，也有可能不关断，如时序图中所示（请参阅
图7-20）。该复位脉冲不影响电荷泵或其他功能块的状态。
图7-20. nSLEEP 复位脉冲
功能模式汇总
表7-10 汇总了所有功能模式。
表7-10. 功能模式汇总
H 桥
DVDD 稳压器
条件
配置
电荷泵
禁用
分度器
禁用
逻辑
禁用
4.5V < VM <
nSLEEP 引脚= 0
睡眠模式
工作
禁用
禁用
48V
4.5V < VM <
48V
nSLEEP 引脚= 1
ENABLE 引脚= 1 或高阻态
工作
禁用
工作
工作
工作
工作
工作
工作
工作
工作
4.5V < VM <
48V
nSLEEP 引脚= 1
ENABLE 引脚= 0
禁用
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DRV8434 is used in bipolar stepper control.
8.2 Typical Application
The following design procedure can be used to configure the DRV8434.
图8-1. Typical Application Schematic (1/8 microstepping, smart tune Ripple Control Decay, HTSSOP
package)
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图8-2. Typical Application Schematic (1/8 microstepping, smart tune Ripple Control Decay, VQFN
package)
8.2.1 Design Requirements
表8-1 lists the design input parameters for system design.
表8-1. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
VM
EXAMPLE VALUE
24 V
Motor winding resistance
Motor winding inductance
Motor full step angle
Target microstepping level
Target motor speed
RL
LL
0.9 Ω/phase
1.4 mH/phase
1.8°/step
θstep
nm
1/8 step
v
18.75 rpm
2 A
Target full-scale current
IFS
8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8434 requires the desired motor speed and microstepping level. If the target
application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin.
If the target motor speed is too high, the motor does not spin. Make sure that the motor can support the target
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speed. Use 方程式1 to calculate ƒstep for a desired motor speed (v), microstepping level (nm), and motor full step
angle (θstep
)
v (rpm) ì 360 (è / rot)
step (è / step) ìnm (steps / microstep) ì 60 (s / min)
ƒstep (steps / s) =
q
(1)
The value of θstep can be found in the stepper motor data sheet, or written on the motor. For example, the motor
in this application is required to rotate at 1.8°/step for a target of 18.75 rpm at 1/8 microstep mode. Using 方程式
1, ƒstep can be calculated as 500 Hz.
The microstepping level is set by the M0 and M1 pins and can be any of the settings listed in 表 8-2. Higher
microstepping results in a smoother motor motion and less audible noise, but requires a higher ƒstep to achieve
the same motor speed.
表8-2. Microstepping Indexer Settings
MODE0
MODE1
STEP MODE
0
0
Full step (2-phase excitation) with 100%
current
0
Full step (2-phase excitation) with 71%
current
330kΩ to
GND
1
Hi-Z
0
0
0
Non-circular 1/2 step
1/2 step
1
1/4 step
1
1
1/8 step
Hi-Z
0
1
1/16 step
Hi-Z
1/32 step
Hi-Z
1/64 step
330kΩ to
GND
Hi-Z
1
Hi-Z
Hi-Z
1/128 step
1/256 step
8.2.2.2 电流调节
在步进电机中，满量程电流 (IFS) 是通过任一绕组的最大电流。该值大小取决于 VREF 电压和 TRQ_DAC 设置，
如方程式2 所示。
VREF 引脚上允许的最大电流为3.3V。DVDD 可用于通过电阻分压器提供VREF。
在步进期间，IFS 定义了最大电流步进的电流斩波阈值(ITRIP)。
(2)
8.2.2.3 衰减模式
DRV8434A 以智能调优纹波控制衰减模式运行。当电机绕组电流达到电流斩波阈值(ITRIP) 时，DRV8434A 会将绕
组置于慢速衰减模式下。
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8.2.2.4 应用曲线
图8-3. 智能调优纹波控制衰减下的1/8 微步进
图8-4. 智能调优动态衰减下的1/8 微步进
图8-6. 智能调优动态衰减下的1/32 微步进
图8-8. 智能调优动态衰减下的1/256 微步进
图8-5. 智能调优纹波控制衰减下的1/32 微步进
图8-7. 智能调优纹波控制衰减下的1/256 微步进
8.2.2.5 Thermal Application
This section presents the power dissipation calculation and junction temperature estimation of the device.
8.2.2.5.1 Power Dissipation
The total power dissipation constitutes of three main components - conduction loss (PCOND), switching loss
(PSW) and power loss due to quiescent current consumption (PQ).
8.2.2.5.2 Conduction Loss
The current path for a motor connected in full-bridge is through the high-side FET of one half-bridge and low-side
FET of the other half-bridge. The conduction loss (PCOND) depends on the motor rms current (IRMS) and high-
side (RDS(ONH)) and low-side (RDS(ONL)) on-state resistances as shown in 方程式3.
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PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL)
)
(3)
The conduction loss for the typical application shown in 表8-1 is calculated in 方程式4.
PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL)) = 2 x (2-A / √2)2 x (0.165-Ω+ 0.165-Ω) = 1.32-W
(4)
备注
This power calculation is highly dependent on the device temperature which significantly effects the
high-side and low-side on-resistance of the FETs. For more accurate calculation, consider the
dependency of on-resistance of FETs with device temperature.
8.2.2.5.3 Switching Loss
The power loss due to the PWM switching frequency depends on the slew rate (tSR), supply voltage, motor RMS
current and the PWM switching frequency. The switching losses in each H-bridge during rise-time and fall-time
are calculated as shown in 方程式5 and 方程式6.
PSW_RISE = 0.5 x VVM x IRMS x tRISE_PWM x fPWM
PSW_FALL = 0.5 x VVM x IRMS x tFALL_PWM x fPWM
(5)
(6)
Both tRISE_PWM and tFALL_PWM can be approximated as VVM/ tSR. After substituting the values of various
parameters, and assuming 30-kHz PWM frequency, the switching losses in each H-bridge are calculated as
shown below -
PSW_RISE = 0.5 x 24-V x (2-A / √2) x (24-V / 240 V/µs) x 30-kHz = 0.05-W
PSW_FALL = 0.5 x 24-V x (1-A / √2) x (24-V / 240 V/µs) x 30-kHz = 0.05-W
(7)
(8)
The total switching loss for the stepper motor driver (PSW) is calculated as twice the sum of rise-time (PSW_RISE
switching loss and fall-time (PSW_FALL) switching loss as shown below -
)
PSW = 2 x (PSW_RISE + PSW_FALL) = 2 x (0.05-W + 0.05-W) = 0.2-W
(9)
备注
The rise-time (tRISE) and the fall-time (tFALL) are calculated based on typical values of the slew rate
(tSR). This parameter is expected to change based on the supply-voltage, temperature and device to
device variation.
The switching loss is directly proportional to the PWM switching frequency. The PWM frequency in an
application will depend on the supply voltage, inductance of the motor coil, back emf voltage and OFF
time or the ripple current (for smart tune ripple control decay mode).
8.2.2.5.4 Power Dissipation Due to Quiescent Current
The power dissipation due to the quiescent current consumed by the power supply is calculated as shown below
-
PQ = VVM x IVM
(10)
Substituting the values, quiescent power loss can be calculated as shown below -
PQ = 24-V x 5-mA = 0.12-W
(11)
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备注
The quiescent power loss is calculated using the typical operating supply current (IVM) which is
dependent on supply-voltage, temperature and device to device variation.
8.2.2.5.5 Total Power Dissipation
The total power dissipation (PTOT) is calculated as the sum of conduction loss, switching loss and the quiescent
power loss as shown in 方程式12.
PTOT = PCOND + PSW + PQ = 1.32-W + 0.2-W + 0.12-W = 1.64-W
(12)
8.2.2.5.6 Device Junction Temperature Estimation
For an ambient temperature of TA and total power dissipation (PTOT), the junction temperature (TJ) is calculated
as -
TJ = TA + (PTOT x RθJA
)
Considering a JEDEC standard 4-layer PCB, the junction-to-ambient thermal resistance (RθJA) is 29.7 °C/W for
the HTSSOP package and 39 °C/W for the VQFN package.
Assuming 25°C ambient temperature, the junction temperature for the HTSSOP package is calculated as shown
below -
TJ = 25°C + (1.64-W x 29.7°C/W) = 73.71°C
(13)
The junction temperature for the VQFN package is calculated as shown below -
TJ = 25°C + (1.64-W x 39°C/W) = 88.96 °C
(14)
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply (VM) range from 4.5 V to 48 V. A 0.01-µF
ceramic capacitor rated for VM must be placed at each VM pin as close to the device as possible. In addition, a
bulk capacitor must be included on VM.
9.1 大容量电容
配备合适的局部大容量电容是电机驱动系统设计中的重要因素。使用更多的大容量电容通常是有益的，但缺点在
于这会增加成本和物理尺寸。
所需的局部电容数量取决于多种因素，包括：
• 电机系统所需的最高电流
• 电源的电容和拉电流的能力
• 电源和电机系统之间的寄生电感量
• 可接受的电压纹波
• 使用的电机类型（有刷直流、无刷直流、步进电机）
• 电机制动方法
电源和电机驱动系统之间的电感将限制电流可以从电源变化的速率。如果局部大容量电容太小，系统将以电压变
化的方式对电机中的电流不足或过剩电流作出响应。当使用足够多的大容量电容时，电机电压保持稳定，可以快
速提供大电流。
数据表通常会给出建议值，但需要进行系统级测试来确定大小适中的大容量电容。
大容量电容的额定电压应高于工作电压，以在电机将能量传递给电源时提供裕度。
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Copyright © 2016, Texas Instruments Incorporated
图9-1. 带外部电源的电机驱动系统示例设置
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device PGND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an
electrolytic capacitor.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for
VM is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is
recommended. Place this bypassing capacitor as close to the pin as possible..
10.2 Layout Example
图10-1. HTSSOP Layout Example
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图10-2. QFN Layout Example
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
11 Device and Documentation Support
11.1 Related Documentation
• Texas Instruments, How to Reduce Audible Noise in Stepper Motors application report
• Texas Instruments, How to Improve Motion Smoothness and Accuracy application report
• Texas Instruments, How to Drive Unipolar Stepper Motors with DRV8xxx application report
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Motor Drives Layout Guide application report
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
PACKAGE OUTLINE
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
28X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.82 MAX
NOTE 5
14
15
2X 0.825 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
4.05
3.53
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.10
2.58
4224480/A 08/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
EXAMPLE BOARD LAYOUT
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
(0.6)
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4224480/A 08/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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ZHCSND1A –NOVEMBER 2020 –REVISED MAY 2022
EXAMPLE STENCIL DESIGN
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 4.53
3.10 X 4.05 (SHOWN)
2.83 X 3.70
0.125
0.15
0.175
2.62 X 3.42
4224480/A 08/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8434PWPR
DRV8434RGER
ACTIVE
ACTIVE
HTSSOP
VQFN
PWP
RGE
28
24
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
DRV8434
NIPDAU
DRV
8434
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8434PWPR
DRV8434RGER
HTSSOP PWP
VQFN RGE
28
24
2500
3000
330.0
330.0
16.4
12.4
6.9
10.2
4.25
1.8
12.0
8.0
16.0
12.0
Q1
Q2
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8434PWPR
DRV8434RGER
HTSSOP
VQFN
PWP
RGE
28
24
2500
3000
356.0
367.0
356.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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