DRV8704DCPR [TI]
60-V dual H-bridge smart gate driver | DCP | 38 | -40 to 85;
| 型号： | DRV8704DCPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 60-V dual H-bridge smart gate driver | DCP | 38 | -40 to 85 |
| 文件： | 总38页 (文件大小：1126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8704
ZHCSEB6 –OCTOBER 2015
DRV8704 52V 双通道 H 桥 PWM 栅极驱动器
1 特性
– 通过 SPI 进行故障诊断
1
•
脉宽调制 (PWM) 电机驱动器
2 应用
–
驱动外部 N 沟道金属氧化物半导体场效应晶体
管 (MOSFET)
•
•
•
•
自动取款机和验钞机
办公自动化设备
工厂自动化和机器人
纺织机器
–
–
双路直流电机的 PWM 控制接口
支持 100% 脉宽调制 (PWM) 占空比
•
•
运行电源电压范围：8V 至 52V
可调节栅极驱动（4 级）
3 说明
–
–
50mA 至 200mA 拉电流
100mA 至 400mA 灌电流
DRV8704 是一款适用于工业设备应用的双路刷式电机
控制器。该器件可控制配置为双 H 桥的外部 N 沟道
MOSFET。
•
•
集成 PWM 电流调节功能
灵活的衰减模式
该器件使用自适应消隐时间和各种电流衰减模式（包括
自动混合衰减模式）对电机电流进行精确控制。
–
–
–
–
自动混合衰减模式
慢速衰减
快速衰减
通过一个简单的 PWM 接口即可轻松与控制器电路相
连。SPI 串行接口用于对器件的工作模式进行编程。输
出电流（转矩）、栅极驱动器设置以及衰减模式均可通
过 SPI 串行接口进行编程。
混合衰减（百分比可调，快速）
•
•
•
•
•
高度可配置的串行外设接口 (SPI)
以数字方式调节电流的转矩数模转换器 (DAC)
低电流休眠模式 (65μA)
该器件的内部关断功能可提供过流保护、短路保护、栅
极驱动器故障排除、欠压锁定 (UVLO) 以及过热保护。
FAULTn 引脚用于指示故障情况，故障情况通过各自
的 SPI 专用位进行报告。
5V、10mA 低压降 (LDO) 稳压器
耐热增强型表面贴装封装
–
38 引脚散热薄型小外形尺寸 (HTSSOP)
(PowerPAD) 封装
空白
DRV8704 采用 PowerPAD™带有散热焊盘的 38 引脚
HTSSOP 封装（环保型：符合 RoHS 标准且不含锑/
溴）。
•
保护特性
–
–
–
–
–
VM 欠压闭锁 (UVLO)
栅极驱动器故障 (PDF)
过流保护 (OCP)
器件信息 (1)
部件号
DRV8704
封装
封装尺寸（标称值）
热关断 (TSD)
HTSSOP (38)
9.70mm x 4.40mm
故障条件指示引脚 (nFAULT)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD29
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 19
7.5 Register Maps......................................................... 20
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
Power Supply Recommendations...................... 27
9.1 Bulk Capacitance .................................................... 27
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 SPI Timing Requirements ......................................... 8
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 器件和文档支持 ..................................................... 30
11.1 社区资源................................................................ 30
11.2 商标....................................................................... 30
11.3 静电放电警告......................................................... 30
11.4 Glossary................................................................ 30
12 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 10 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
5 Pin Configuration and Functions
DCP Package
38-Pin HTSSOP
Top View
1
2
3
4
5
6
7
8
9
38
CP1
CP2
VCP
VM
GND
GND
37 AOUT1
36 A1HS
35 A1LS
34 AISENP
33 AISENN
32 A2LS
31
30
29
28
27
V5
VINT
SLEEPn
RESET
A2HS
AOUT2
GND
BOUT1
B1HS
GND
(PPAD)
AIN1 10
AIN2 11
BIN1 12
BIN2
SCLK 14
SDATI
SCS 16
13
15
SDATO
17
18
19
FAULTn
GND
Pin Functions
(1)
PIN
TYPE
DESCRIPTION
NAME
NO.
POWER AND GROUND
CP1
CP2
1
2
IO
IO
Charge pump flying capacitor
Charge pump flying capacitor
Connect a 0.1-μF X7R capacitor between CP1 and CP2.
Voltage rating must be greater than applied VM voltage.
5, 19, 29,
38, PPAD
GND
RSVD
V5
—
—
O
Device ground
All pins must be connected to ground
Leave this pin disconnected
20
Reserved
5-V linear regulator output. Bypass to GND with a 0.1-μF
10-V X7R ceramic capacitor.
6
5-V regulator output
High-side gate drive voltage
Internal logic supply voltage
VCP
VINT
3
IO
—
Connect a 1-μF 16-V X7R ceramic capacitor to VM
Logic supply voltage. Bypass to GND with a 1-μF 6.3-V
X7R ceramic capacitor.
7
Connect to motor supply voltage. Bypass to GND with a
0.1-μF ceramic capacitor plus a 100-μF electrolytic
capacitor.
VM
4
—
Motor power supply
CONTROL
AIN1
10
11
12
13
I
I
I
I
Bridge A IN1
Bridge A IN2
Bridge B IN1
Bridge B IN2
Controls bridge A OUT1. Internal pulldown.
Controls bridge A OUT2. Internal pulldown.
Controls bridge B OUT1. Internal pulldown.
Controls bridge B OUT2. Internal pulldown.
AIN2
BIN1
BIN2
Active-high reset input initializes all internal logic and
disables the H-bridge outputs. Internal pulldown.
RESET
9
8
I
I
Reset input
Logic high to enable device, logic low to enter low-power
sleep mode. Internal pulldown.
SLEEPn
Sleep mode input
SERIAL INTERFACE
Rising edge clocks data into part for write operations.
Falling edge clocks data out of part for read operations.
Internal pulldown.
SCLK
14
I
Serial clock input
SCS
16
15
I
I
Serial chip select input
Serial data input
Active high to enable serial data transfer. Internal pulldown.
Serial data input from controller. Internal pulldown.
SDATI
(1) Directions: I = Input, O = Output, OZ = Tri-state output, OD = Open-drain output, IO = Input/output
Copyright © 2015, Texas Instruments Incorporated
3
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
Pin Functions (continued)
(1)
PIN
TYPE
DESCRIPTION
NAME
SDATO
NO.
Serial data output to controller. Open-drain output requires
external pull-up.
17
O
Serial data output
Fault
STATUS
Logic low when in fault condition. Open-drain output
requires external pullup.
FAULTn
18
OD
OUTPUT
A1HS
36
35
31
32
33
34
37
30
27
26
22
23
24
25
28
21
O
O
O
O
I
Bridge A out 1 HS gate
Bridge A out 1 LS gate
Bridge A out 2 HS gate
Bridge A out 2 LS gate
Bridge A Isense – in
Bridge A Isense + in
Bridge A output 1
Bridge A out 1 HS FET gate
Bridge A out 1 LS FET gate
Bridge A out 2 HS FET gate
Bridge A out 2 LS FET gate
Ground at sense resistor for bridge A
Current sense resistor for bridge A
Output node of bridge A out 1
Output node of bridge A out 2
Bridge B out 1 HS FET gate
Bridge B out 1 LS FET gate
Bridge B out 2 HS FET gate
Bridge B out 2 LS FET gate
Ground at sense resistor for bridge B
Current sense resistor for bridge B
Output node of bridge B out 1
Output node of bridge B out 2
A1LS
A2HS
A2LS
AISENN
AISENP
AOUT1
AOUT2
B1HS
I
I
I
Bridge A output 2
O
O
O
O
I
Bridge B out 1 HS gate
Bridge B out 1 LS gate
Bridge B out 2 HS gate
Bridge B out 2 LS gate
Bridge B Isense – in
Bridge B Isense + in
Bridge B output 1
B1LS
B2HS
B2LS
BISENN
BISENP
BOUT1
BOUT2
I
I
I
Bridge B output 2
4
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN
MAX
60
UNIT
Power supply voltage (VM)
–0.6
–0.6
–0.6
–0.6
V
V
V
V
V
Charge pump voltage (CP1, CP2, VCP)
5-V regulator voltage (V5)
VM + 12
5.5
Internal regulator voltage (VINT)
2.0
Digital pin voltage (SLEEPn, RESET, AIN1, AIN2, BIN1, BIN2, SCS, SCLK, SDATI,
SDATO, FAULTn)
–0.6
5.5
High-side gate drive pin voltage (A1HS, A2HS, B1HS, B2HS)
Low-side gate drive pin voltage (A1LS, A2LS, B1LS, B2LS)
Phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
ISENSEx pin voltage (AISENP, AISENN, BISENP, BISENN)
Operating virtual junction temperature, TJ
–0.6
–0.6
–0.6
–0.7
–40
VM + 12
12
V
V
VM
V
+0.7
150
V
°C
°C
Storage temperature, Tstg
–60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
8
MAX
UNIT
VM
VIN
fPWM
IV5
Motor power supply voltage range
Digital pin voltage range
52
5.3
500
10
V
V
0
Applied PWM signal (xINx)
V5 external load current
0
kHz
mA
°C
0
TA
Operating ambient temperature range
–40
85
6.4 Thermal Information
DRV8704
(1)
THERMAL METRIC
DCP (HTSSOP)
UNIT
38 PINS
32.7
17.2
14.3
0.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.1
0.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
5
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
POWER SUPPLIES (VM)
TEST CONDITIONS
MIN
TYP
IVM
VM operating supply current
VM sleep mode supply current
VM = 24 V
17
65
22
98
mA
IVMQ
VM = 24 V, SLEEPn low
μA
INTERNAL LINEAR REGULATORS (V5, VINT)
V5
V5 output voltage
VINT voltage
VM ≥ 12 V, IOUT ≤ 10 mA
4.8
1.7
5
5.2
1.9
V
V
VINT
No external load; reference only
1.8
LOGIC-LEVEL INPUTS (SLEEPn, AIN1, AIN2, BIN1, BIN2, RESET, SCLK, SDATI, SCS)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
0.8
V
V
1.5
300
50
mV
μA
μA
VIN = 0 V
VIN = 5 V
–5
24
5
IIH
70
OPEN DRAIN OUTPUTS (nFAULT, SDATO)
VOL
IOH
Output logic low voltage
Output logic high leakage
IO = 5 mA
0.5
1
V
10kΩ pullup to 3.3 V
–1
μA
GATE DRIVERS
High-side gate drive output
VOUTH
VM = 24 V, IO = 100 μA
VM = 24 V, IO = 100 μA
VM + 10
10
V
V
voltage
Low-side gate drive output
voltage
VOUTL
DTIME = 00
410
460
670
880
50
Output dead time digital delay
(dead time is enforced in analog
circuits)
DTIME = 01
tDEAD
ns
mA
mA
ns
DTIME = 10
DTIME = 11
IDRIVEP = 00
IDRIVEP = 01
IDRIVEP = 10
IDRIVEP = 11
IDRIVEN = 00
IDRIVEN = 01
IDRIVEN = 10
IDRIVEN = 11
TDRIVEP = 00
TDRIVEP = 01
TDRIVEP = 10
TDRIVEP = 11
TDRIVEN = 00
TDRIVEN = 01
TDRIVEN = 10
TDRIVEN = 11
100
150
200
100
150
200
400
263
525
1050
2100
263
525
1050
2100
Peak output sourcing gate drive
current
IOUT,SRC
IOUT,SNK
tDRIVE,SRC
tDRIVE,SNK
Peak output sinking gate drive
current
Peak current drive time for
sourcing
Peak current drive time for
sinking
ns
CURRENT REGULATION
tOFF
PWM off time adjustment range
Set by TOFF register
Set by TBLANK register
ISGAIN = 00
0.53
1.05
134
7.0
μs
μs
tBLANK
Current sense blanking time
5
10
20
40
ISGAIN = 01
AV
Current sense amplifier gain
V/V
ISGAIN = 10
ISGAIN = 11
6
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
ISGAIN = 00, ∆VIN = 400 mV
ISGAIN = 01, ∆VIN = 200 mV
ISGAIN = 10, ∆VIN = 100 mV
ISGAIN = 11, ∆VIN = 50 mV
ISGAIN = 00, input shorted
MIN
TYP
150
MAX UNIT
300
tSET
Settling time (to ±1%)
ns
600
1200
VOFS
VIN
Offset voltage
4
600
mV
mV
V
Input differential voltage range
Internal reference voltage
–600
2.50
VREF
2.75
3.00
PROTECTION CIRCUITS
VIN falling; UVLO report
VIN rising; UVLO recovery
OCPTH = 00
6.3
7.1
VUVLO Undervoltage lockout
V
8
320
160
380
620
840
150
250
500
750
1000
160
20
Overcurrent protection trip level
(Voltage drop across external
FET)
OCPTH = 01
580
VOCP
mV
OCPTH = 10
880
OCPTH = 11
1200
180
(1)
TTSD
THYS
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature, TJ
Die temperature, TJ
°C
°C
(1)
(1) Not tested in production; limits are based on characterization data
Copyright © 2015, Texas Instruments Incorporated
7
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
6.6 SPI Timing Requirements
over operating free-air temperature range (unless otherwise noted)
NO.
MIN
250
25
25
5
MAX
UNIT
ns
1
2
3
4
5
6
7
8
9
tCYC
Clock cycle time
tCLKH
Clock high time
ns
tCLCL
Clock low time
ns
tSU(SDATI)
tH(SDATI)
tSU(SCS)
tH(SCS)
tL(SCS)
tD(SDATO)
tSLEEP
tRESET
Setup time, SDATI to SCLK
ns
Hold time, SDATI to SCLK
1
ns
Setup time, SCS to SCLK
5
ns
Hold time, SCS to SCLK
1
ns
Inactive time, SCS (between writes)
Delay time, SCLK to SDATO (during read)
Wake time (SLEEPn inactive to high-side gate drive enabled)
Delay from power-up or RESETn high until serial interface functional
100
ns
10
1
ns
ms
μs
10
7
6
8
SCS
1
SCLK
2
3
X
SDATI
X
4
5
9
SDATO
valid
SDATO
Figure 1. Timing Diagram
8
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
6.7 Typical Characteristics
16.3
16.2
16.1
16
16.25
16.2
16.15
16.1
15.9
15.8
15.7
15.6
15.5
15.4
15.3
16.05
16
15.95
15.9
15.85
15.8
TA = +85°C
TA = +25°C
TA = -40°C
15.75
5
10
15
20
25
30
35
40
45
50
55
-40
-20
0
20
40
60
80
100
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D001
D002
Figure 2. Supply Current over Supply Voltage
Figure 3. Supply Current over Ambient Temperature at VM =
24 V
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
TA = +85°C
TA = +25°C
TA = -40°C
60
60
40
40
5
10
15
20
25
30
35
40
45
50
55
-40
-20
0
20
40
60
80
100
Supply Voltage VM (V)
Ambient Temperature TA (èC)
D003
D004
Figure 4. Sleep Current over Supply Voltage
Figure 5. Sleep Current over Ambient Temperature at VM =
24 V
5.1
5.08
5.06
5.04
5.02
5
7.65
TA = +85°C
TA = +25°C
TA = -40°C
7.6
7.55
7.5
7.45
7.4
4.98
4.96
4.94
4.92
4.9
7.35
7.3
7.25
7.2
TA = +85°C
TA = +25°C
TA = -40°C
7.15
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Load Current (mA)
Load Current (mA)
D005
D006
Figure 6. V5 Regulator Voltage over Output Load at
VM = 12 V
Figure 7. Charge Pump Voltage over DC Current Load at
VM = 12 V
Copyright © 2015, Texas Instruments Incorporated
9
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DRV8704 is a dual-brushed motor controller that uses external N-channel MOSFETs to drive two brushed
DC motors.
Motor current can be accurately controlled using adaptive blanking time and various current decay modes,
including an auto-mixed decay mode.
A simple PWM interface allows easy interfacing to controller circuits. A SPI serial interface is used to program
the device operation. Output current (torque), gate drive settings, and decay mode are all programmable through
a SPI serial interface.
Internal shutdown functions are provided for overcurrent protection, short-circuit protection, UVLO, and
overtemperature. Fault conditions are indicated by a FAULTn pin, and each fault condition is reported by a
dedicated bit through SPI.
10
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
7.2 Functional Block Diagram
VM
0.01 µF
+ Bulk
VM
VM
VM
VCP
Power
A1HS
HS
1 µF
VCP
CP2
CP1
VINT
V5
AOUT1
A1LS
Gate Driver
VGLS
Charge
Pump
LS
0.1 µF
1 µF
VM
BDC
1.8-V LDO
5.0-V LDO
VGLS LDO
VCP
A2HS
AOUT2
A2LS
10 mA
HS
0.1 µF
Gate Driver
VGLS
LS
AIN1
AIN2
BIN1
BIN2
AISENP
AISENN
+
AV
-
RSENSE
VREF
DAC
Control
Inputs
SLEEPn
RESET
VM
Logic
VCP
B1HS
BOUT1
B1LS
HS
SCS
SCLK
Serial
Interface
Gate Driver
VGLS
LS
SDATI
SDATO
VM
BDC
VCP
B2HS
BOUT2
B2LS
HS
Protection
Overcurrent
Output
nFAULT
Gate Driver
VGLS
Undervoltage
Thermal
LS
Gate Drive
BISENP
BISENN
+
AV
-
RSENSE
VREF
DAC
PPAD GND GND
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7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8704 contains two H-bridge motor gate drivers with current-control PWM circuitry.
7.3.2 Direct PWM Input Mode (Dual Brushed DC Gate Driver)
In direct PWM input mode, the AIN1, AIN2, BIN1, and BIN2 directly control the state of the output drivers. This
allows for driving up to two brushed DC motors. Table 1 shows the logic.
Table 1. Output Control Logic Table
SLEEPn
xIN1
xIN2
xOUT1
xOUT2
DESCRIPTION
Sleep mode; H-bridge disabled Hi-Z
Coast; H-bridge disabled Hi-Z
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
H
Reverse (current xOUT2 → xOUT1)
Forward (current xOUT1 → xOUT2)
Brake; low-side slow decay
H
L
L
L
In direct PWM mode, the current control circuitry is still active. The full-scale VREF is set to 2.75 V. The
TORQUE register may be used to scale this value, and the ISEN sense amplifier gain may still be set using the
ISGAIN bits of the CTRL register.
VM
x1HS
Gate
Drive
xOUT1
xIN1
xIN2
and
OCP
x1LS
PWM
logic
VM
x2HS
Gate
Drive
and
xOUT2
OCP
x2LS
+
-
RISENSE
Comp
Comp
+
-
xISENP
xISENN
-
+
ISEN
amp
+
-
VREF
Torque
DAC
TORQUE
ISGAIN
Figure 8. Motor Driver Block Diagram
12
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7.3.3 Current Regulation
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current
chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between
525 ns and 128 µs by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is re-
enabled, starting another PWM cycle.
Note that the decay mode is set by DECMOD bits in the DECAY register. Slow, fast, mixed, or auto mixed decay
modes are available.
The chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The
current sense amplifier is programmable in the CTRL register.
When driving in PWM mode, the chopping current is calculated as follows:
2.75 Vì TORQUE
256 ì ISGAIN ì RISENSE
ICHOP
=
where
•
•
TORQUE is the setting of the TORQUE bits
ISGAIN is the programmed gain of the ISENSE amplifiers (5, 10, 20, or 40).
(1)
7.3.4 Decay Modes
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in the diagram below as case 1. The current flow direction
shown indicates positive current flow in the step table below.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. If the winding current approaches zero, the bridge is disabled
to prevent any reverse current flow. Fast decay mode is shown in the diagram below as case 2.
In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is
shown as case 3 in Figure 9.
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PWM
ON
ëa
PWM OFF
Slow Decay
Fast Decay
1
2
3
5rive /urrent
1
Cast decay (reverse)
{low decay (brake)
xhÜÇ2
xhÜÇ1
3
2
Mixed Decay
TDECAY
TBLANK
TOFF
Itrip
Figure 9. Decay Mode Current
Figure 10. Decay Mode Comparison
The DRV8704 supports fast decay and slow decay modes. In addition it supports fixed mixed decay and auto
mixed decay modes. Decay mode is selected by the DECMOD bits in the DECAY register.
Mixed decay mode begins as fast decay, but after a programmable period of time (set by the TDECAY bits in the
DECAY register) switches to slow decay mode for the remainder of the fixed off time.
Auto mixed decay mode samples the current level at the end of the blanking time, and if the current is above the
Itrip threshold, immediately changes the H-bridge to fast decay. During fast decay, the (negative) current is
monitored, and when it falls below the Itrip threshold (and another blanking time has passed), the bridge is
switched to slow decay. Once the fixed off time expires, a new cycle is started.
If the bridge is turned on and at the end of tBLANK the current is below the Itrip threshold, the bridge remains on
until the current reaches Itrip. Then slow decay is entered for the fixed off time, and a new cycle begins.
Refer to Figure 11.
The upper waveform shows the behavior if I < Itrip at the end of tBLANK. This is a stable, slow decay mode of
operation.
The lower waveform shows what happens when I > Itrip at the end of tBLANK. Note that (at slow motor speeds,
where back EMF is not significant), the current increase during the ON phase is the same magnitude as the
current decrease in fast decay, since both times are controlled by tBLANK, and the rate of change is the same (full
VM is applied to the load inductance in both cases, but in opposite directions). In this case, the current will
gradually be driven down until the peak current is just hitting Itrip at the end of the blanking time, after which
some cycles will be slow decay, and some will be mixed decay.
14
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tON
tON
tOFF
tOFF
tBLANK
tBLANK
I below Itrip
after tBLANK
Itrip
At Itrip and after tBLANK
slow decay
,
I < Itrip
tON
tON
tOFF
tOFF
On
tBLANK
tBLANK
tBLANK
tBLANK
I above Itrip
after tBLANK
Fast
Decay
Itrip
Slow
Decay
I > Itrip, start
fast decay
When I < Itrip in fast decay and
tBLANK expires, change to slow
decay
Figure 11. Auto Mixed Decay
To accurately detect zero current, an internal offset has been intentionally placed in the zero current detection
circuit. If an external filter is placed on the current sense resistor to the xISENN and xISENP pins, symmetry
must be maintained. This means that any resistance between the bottom of the RISENSE resistor and xISENN
must be matched by the same resistor value (1% tolerance) between the top of the RISENSE resistor and xISENP.
Ensure a maximum resistance of 500 Ω. The capacitor value should be chosen such that the RC time constant is
between 50 and 60 ns. Any external filtering on these pins is optional and not required for operation.
VM
x1HS
Gate
Drive
xOUT1
and
OCP
x1LS
PWM
logic
VM
x2HS
Gate
Drive
xOUT2
and
OCP
x2LS
+
RISENSE
Comp
-
+
-
-
xISENP
xISENN
ISEN
amp
+
R
R
+
-
C
Comp
Optional Filtering
Figure 12. Optional Filtering for Sense Amplifiers
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7.3.5 Blanking Time
After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before
enabling the current sense circuitry. This blanking time is adjustable from 500 ns to 5.14 µs, in 20-ns increments,
by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum drive time
of the PWM.
The same blanking time is applied to the fast decay period in auto mixed decay mode. The PWM will ignore any
transitions on Itrip after entering fast decay mode, until the blanking time has expired.
7.3.6 Gate Drivers
An internal charge pump circuit and pre-drivers inside the DRV8704 directly drive N-channel MOSFETs, which
drive the motor current.
The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source
currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2× the peak
source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input
capacitance and gate charge.
When changing the state of the output, the peak current is applied for a short period of time (tDRIVE), to charge
the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When
selecting the gate drive strength for a given external FET, the selected current must be high enough to fully
charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated
in the FET.
During high-side turn-on, the low-side gate is pulled low. This prevents the gate-drain capacitance of the low-side
FET from inducing turn-on.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay
can be selected by setting the DTIME bits in the CTRL register.
tDRIVE
High Z
High Z
High Z
Low Z
HS drive
(mA)
Low
Z
xHS
(V)
tDRIVE
High Z
Low Z
High Z
High Z
LS drive
(mA)
Low
Z
xLS
(V)
tDEAD
tDEAD
Figure 13. Gate Driver
16
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I (mA) source
I (mA) source
200 mA
TDRIVEP = 00
TDRIVEP = 01
IDRIVEP = 11
200 mA
150 mA
100 mA
IDRIVEP = 11
150 mA
100 mA
IDRIVEP = 10
IDRIVEP = 10
IDRIVEP = 01
IDRIVEP = 00
IDRIVEP = 01
IDRIVEP = 00
50 mA
50 mA
Holding Current
Holding Current
t (ns)
t (ns)
263 ns 525 ns
1.05 µs
2.1 µs
263 ns 525 ns
I (mA) source
1.05 µs
2.1 µs
I (mA) source
TDRIVEP = 10
TDRIVEP = 11
200 mA
150 mA
100 mA
200 mA
150 mA
100 mA
IDRIVEP = 11
IDRIVEP = 11
IDRIVEP = 10
IDRIVEP = 10
IDRIVEP = 01
IDRIVEP = 00
IDRIVEP = 01
IDRIVEP = 00
50 mA
50 mA
Holding Current
Holding Current
t (ns)
t (ns)
263 ns 525 ns
1.05 µs
2.1 µs
263 ns 525 ns
1.05 µs
2.1 µs
Figure 14. Gate Driver Source Capability
TDRIVEN = 00
1.05 µs
TDRIVEN = 01
1.05 µs
263 ns 525 ns
2.1 µs
263 ns 525 ns
2.1 µs
t (ns)
t (ns)
Holding Current
Holding Current
IDRIVEN = 00
IDRIVEN = 00
100 mA
100 mA
IDRIVEN = 01
IDRIVEN = 10
IDRIVEN = 11
IDRIVEN = 01
IDRIVEN = 10
IDRIVEN = 11
200 mA
300 mA
400 mA
200 mA
300 mA
400 mA
I (mA) sink
263 ns 525 ns
I (mA) sink
263 ns 525 ns
TDRIVEN = 10
1.05 µs
TDRIVEN = 11
1.05 µs
2.1 µs
2.1 µs
t (ns)
t (ns)
Holding Current
Holding Current
IDRIVEN = 00
IDRIVEN = 00
IDRIVEN = 01
100 mA
100 mA
IDRIVEN = 01
IDRIVEN = 10
IDRIVEN = 11
200 mA
300 mA
400 mA
200 mA
300 mA
400 mA
IDRIVEN = 10
IDRIVEN = 11
I (mA) sink
I (mA) sink
Figure 15. Gate Driver Sink Capability
7.3.7 Configuring Gate Drivers
IDRIVE and TDRIVE are selected based on the size of external FETs used. These registers need to be
configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and TDRIVE are chosen to
be too low for a given FET, then the FET may not turn on completely. It is suggested to adjust these values in-
system with the required external FETs and motors in order to determine the best possible setting for any
application.
Note that TDRIVE will not increase the PWM time or change the PWM chopping frequency.
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In a system with capacitor charge Q and desired rise time RT, IDRIVE, and TDRIVE can be initially selected
based on:
Q
IDRIVE >
(2)
(3)
TDRIVE > 2 × RT
For best results, select the smallest IDRIVE and TDRIVE that meet the above conditions.
Example:
If the gate charge is 15 nC and the desired rise time is 400 ns, then select
IDRIVEP = 50 mA, IDRIVEN = 100 mA
TDRIVEP = TDRIVEN = 1050 ns
7.3.8 External FET Selection
In a typical setup, the DRV8704 can support external FETs over 50 nC each. However, this capacity can be
lower or higher based on the device operation. For an accurate calculation of FET driving capacity, use
Equation 4.
20 mA ì 2 ì DTIME + TBLANK + TOFF
(
)
Q <
4
(4)
Example:
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0 (525 ns), then the DRV8704
will support Q < 11.5 nC FETs. (Please note that this is an absolute worst-case scenario with a PWM
frequency about 430 kHz)
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x14 (10 µs), then the
DRV8704 will support Q < 59 nC FETs (PWM frequency about 85 kHz).
If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x60 (48 µs), then the
DRV8704 will support Q < 249 nC FETs (PWM frequency about 20 kHz).
7.3.9 Protection Circuits
The DRV8704 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.9.1 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven
FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period
specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. During an OCP event, the H-
bridge experiencing the OCP event is disabled. In addition, the corresponding xOCP bit in the STATUS register
is set, and the FAULTn pin is driven low. The H-bridge (or H-bridges) will remain off, and the xOCP bit will
remain set, until it is written to 0, or the device is reset.
7.3.9.2 Gate Driver Fault (PDF)
If excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output
FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set,
and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written
to 0, or the device is reset.
7.3.9.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS
register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level
operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation
has resumed.
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7.3.9.4 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-
bridge will be disabled, the UVLO bit in the STATUS register will be set, and the FAULTn pin will be driven low.
Operation will resume and the UVLO bit will reset when VM rises above the UVLO threshold. The FAULTn pin
will be released after operation has resumed.
7.3.10 Serial Data Format
The serial data consists of a 16-bit serial write, with a read/write bit, 3 address bits and 12 data bits. The three
address bits identify one of the registers defined in the register section above. To complete the read or write
transaction, SCS must be set to a logic 0.
To write to a register, data is shifted in after the address as shown in the timing diagram below. The first bit at
the beginning of the access must be logic low for a write operation.
Figure 16. Serial Write Operation
Data may be read from the registers through the SDATO pin. During a read operation, only the address is used
form the SDATI pin; the data bits following are ignored. The first bit at the beginning of the access must be logic
high for a read operation.
(1) Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used
Figure 17. Serial Read Operation
7.4 Device Functional Modes
The DRV8704 is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled,
the H-bridge FETs are disabled Hi-Z, and the V5 regulator is disabled. The DRV8704 is brought out of sleep
mode automatically if nSLEEP is brought logic high.
If a ‘0’ is written to the ENBL bit, the H-bridge outputs are disabled, but the internal logic will still be active.
Table 2. Functional Modes
CONDITION
8 V < VM < 52 V
H-BRIDGE
CHARGE PUMP
SPI
V5
Operating
nSLEEP pin = 1
ENBL bit = 1
Operating
Operating
Operating
Operating
8 V < VM < 52 V
nSLEEP pin = 1
ENBL bit = 0
Disabled
Disabled
Operating
Operating
Operating
8 V < VM < 52 V
nSLEEP pin = 0
Sleep mode
Disabled
Disabled
Disabled
Disabled
Disabled
Fault
encountered
Any fault condition met
Depends on fault
Depends on fault
Depends on fault
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7.5 Register Maps
7.5.1 Control Registers
The DRV8704 uses internal registers to control the operation of the motor. The registers are programmed by a
serial SPI communications interface. At power-up or reset, the registers will be pre-loaded with default values as
shown in Table 3.
Following is a map of the DRV8704 registers:
Table 3. DRV8704 Register Map
ADDRESS
NAME
CTRL
11
10
9
8
7
6
5
4
3
2
1
0
HEX
00
01
02
03
04
05
06
07
DTIME
ISGAIN
Reserved
ENBL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TORQUE
OFF
Reserved
Reserved
Reserved
DECMOD
TORQUE
PWMMODE
TOFF
BLANK
TBLANK
TDECAY
DECAY
RESERVED
DRIVE
Reserved
Reserved
IDRIVEP
IDRIVEN
Reserved
TDRIVEP
TDRIVEN
UVLO BPDF
OCPDEG
APDF BOCP
OCPTH
AOCP
STATUS
OTS
Individual register contents are defined in the following sections.
7.5.1.1 CTRL Register (Address = 0x00h)
Table 4. CTRL Register
BIT
0
NAME
ENBL
SIZE
R/W
R/W
—
DEFAULT
DESCRIPTION
0: Disable motor
1: Enable motor
1
7
1
7-1
Reserved
—
Reserved
ISENSE amplifier gain set
00: Gain of 5 V/V
9-8
ISGAIN
DTIME
2
2
R/W
R/W
11
00
01: Gain of 10 V/V
10: Gain of 20 V/V
11: Gain of 40 V/V
Dead time set
00: 410-ns dead time
01: 460-ns dead time
10: 670-ns dead time
11: 880-ns dead time
11-10
7.5.1.2 TORQUE Register (Address = 0x01h)
Table 5. TORQUE Register
BIT
7-0
NAME
SIZE
R/W
R/W
—
DEFAULT
0xFFh
—
DESCRIPTION
TORQUE
Reserved
8
4
Sets full-scale output current for both H-bridges
Reserved
11-8
7.5.1.3 OFF Register (Address = 0x02h)
Table 6. OFF Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
7-0
TOFF
8
R/W
0x30h
Sets fixed off time, in increments of 525 ns
0x00h: 525 ns
0xFFh: 133.8 µs
8
PWMMODE
Reserved
1
3
R/W
—
1
0: Do not write ‘0’ to this register
1: PWM control mode
11-9
—
Reserved
20
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7.5.1.4 BLANK Register (Address = 0x03h)
Table 7. BLANK Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
7-0
TBLANK
8
R/W
0x80h
Sets current trip blanking time, in increments of 21
ns
0x00h: 1.05 µs
…
0x32h: 1.05 µs
0x33h: 1.07 µs
…
0xFEh: 5.859 µs
0xFFh: 5.880 µs
Also sets minimum on-time of PWM
11-8
Reserved
4
—
—
Reserved
7.5.1.5 DECAY Register (Address = 0x04h)
Table 8. DECAY Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
7-0
TDECAY
8
R/W
0x10h
Sets mixed decay transition time, in increments of
525ns
10-8
DECMOD
3
R/W
000
000: Force slow decay at all times
001: Reserved
010: Force fast decay at all times
011: Use mixed decay at all times
100: Reserved
101: Use auto mixed decay at all times
110 – 111: Reserved
11
Reserved
1
—
—
Reserved
7.5.1.6 Reserved Register Address = 0x05h
Table 9. Reserved Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
11-0
Reserved
12
—
—
Reserved
7.5.1.7 DRIVE Register Address = 0x06h
Table 10. DRIVE Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
1-0
OCPTH
2
R/W
01
OCP threshold
00: 250 mV
01: 500 mV
10: 750 mV
11: 1000 mV
3-2
5-4
OCPDEG
TDRIVEN
2
2
R/W
R/W
01
10
OCP deglitch time
00: 1.05 µs
01: 2.1 µs
10: 4.2 µs
11: 8.4 µs
Gate drive sink time
00: 263 ns
01: 525 ns
10: 1.05 µs
11: 2.10 µs
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Table 10. DRIVE Register (continued)
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
7-6
TDRIVEP
IDRIVEN
IDRIVEP
2
R/W
10
Gate drive source time
00: 263 ns
01: 525 ns
10: 1.05 µs
11: 2.10 µs
9-8
2
2
R/W
R/W
11
11
Gate drive peak sink current
00: 100-mA peak (sink)
01: 200-mA peak (sink)
10: 300-mA peak (sink)
11: 400-mA peak (sink)
11-10
Gate drive peak source current
00: 50-mA peak (source)
01: 100-mA peak (source)
10: 150-mA peak (source)
11: 200-mA peak (source)
7.5.1.8 STATUS Register (Address = 0x07h)
Table 11. STATUS Register
BIT
NAME
SIZE
R/W
DEFAULT
DESCRIPTION
0
OTS
1
R
0
0: Normal operation
1: Device has entered overtemperature shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
Operation automatically resumes once
temperature has fallen to safe levels
1
2
3
4
5
AOCP
BOCP
APDF
BPDF
UVLO
1
1
1
1
1
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0: Normal operation
1: Channel A overcurrent shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
0: Normal operation
1: Channel B overcurrent shutdown
Write a ‘0’ to this bit to clear the fault and resume
operation
0: Normal operation
1: Channel A predriver fault
Write a ‘0’ to this bit to clear the fault and resume
operation
0: Normal operation
1: Channel B predriver fault
Write a ‘0’ to this bit to clear the fault and resume
operation
0: Normal operation
1: Undervoltage lockout
Write a ‘0’ to this bit to clear the fault and resume
operation
The UVLO bit cannot be cleared in sleep mode
Operation automatically resumes once VM has
risen
11-6
Reserved
5
—
—
Reserved
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8704 is used in brushed DC motor control.
8.2 Typical Application
The following design procedure can be used to configure the DRV8704.
DRV8704DCP
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VM
CP1
GND
AOUT1
A1HS
0.1 µF
1 µF
CP2
3
A1HS
AOUT1
A1LS
A2HS
AOUT2
A2LS
VCP
VM
4
VM
A1LS
+
BDC
5
bulk
0.01 µF
GND
V5
AISENP
AISENN
A2LS
6
7
0.1 µF
VINT
SLEEPn
RESET
AIN1
AIN2
BIN1
BIN2
SCLK
SDATI
SCS
AISENP
AISENN
1 µF
8
A2HS
9
AOUT2
GND
10
11
12
13
14
15
16
17
18
19
VM
BOUT1
B1HS
B1HS
BOUT1
B1LS
B2HS
BOUT2
B2LS
B1LS
BISENP
BISENN
B2LS
BDC
V5
V5
SDATO
FAULTn
GND
B2HS
BISENP
BISENN
BOUT2
RSVD
Figure 18. Dual Brushed-DC Motor Control
Copyright © 2015, Texas Instruments Incorporated
23
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
Typical Application (continued)
8.2.1 Design Requirements
Table 12 shows design input parameters for system design.
Table 12. Design Parameters
DESIGN PARAMETER
Supply voltage
FET total gate charge
REFERENCE
EXAMPLE VALUE
24 V
VM
Qg
(1)
41 nC (typically)
6.7 nC (typically)
20 to 100 ns
400 mΩ
(1)
FET gate-to-drain charge
Target FET gate rise time
Motor winding resistance
Motor winding inductance
Target chopping current
Qgd
RT
RL
LL
258 μH
ICHOP
5.5 A
(1) FET part number is CSD18540Q5B
8.2.2 Detailed Design Procedure
8.2.2.1 External FET Selection
The DRV8704 FET support is based on the charge pump capacity and output PWM frequency. For a quick
calculation of FET driving capacity, use the following equations when drive and brake (slow decay) are the
primary modes of operation:
IVCP
Qg <
2 ì ƒPWM
where
•
ƒPWM is the maximum desired PWM frequency to be applied to the DRV8704 inputs or the current chopping
frequency, whichever is larger.
•
IVCP is the charge pump capacity, which is 20 mA.
(5)
(6)
The factor of two arises because there are two H-bridges present.
The current chopping frequency is at most:
1
ƒPWM
<
tOFF + tBLANK
Example:
If a system uses a maximum PWM frequency of 40 kHz, then the DRV8704 will support Qg < 250 nC FETs.
If the application will require a forced fast decay (or alternating between drive and reverse drive), the maximum
FET driving capacity is given by:
IVCP
Qg <
4 ì ƒPWM
(7)
8.2.2.2 IDRIVE Configuration
IDRIVE is selected based on the gate charge of the FETs. The IDRIVEx and TDRIVEx registers need to be
configured so that the FET gates are charged completely during TDRIVE. If IDRIVE is chosen to be too low for a
given FET, or if TDRIVE is less than the intended rise time, then the FET may not turn on completely. TI
suggests to adjust these values in-system with the required external FETs and motor to determine the best
possible setting for any application.
For FETs with a known gate-to-drain charge Qgd and desired rise time RT, IDRIVE and TDRIVE can be selected
based on:
Qgd
IDRIVE >
(8)
(9)
TDRIVE > 2 × RT
24
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
Example:
If the gate-to-drain charge is 5.9 nC, and the desired rise time is around 20 to 100 ns:
IDRIVE1 = 6.7 nC / 20 ns = 335 mA
IDRIVE2 = 6.7 nC / 100 ns = 67 mA
Select IDRIVE between 67 and 335 mA.
We select IDRIVEP as 200-mA source and IDRIVEP as 400-mA sink.
We select TDRIVEN and TDRIVEP as 525 ns.
8.2.2.3 Current Chopping Configuration
The chopping current is set based on the sense resistor value, shunt amplifier gain set by the ISGAIN register,
and the TORQUE register setting. The following is used to calculate the current:
2.75 V ì TORQUE
ICHOP
=
256 ì ISGAIN ì RISENSE
Example:
If the desired chopping current is 5.5 A:
(10)
Set RSENSE = 100 mΩ.
Set ISGAIN to the 5 V/V setting.
The TORQUE register can be (decimal) 255.
8.2.2.4 Decay Modes
The DRV8704 supports several different decay modes: slow decay, fast decay, mixed decay, and automatic
mixed decay. The current through the motor windings is regulated using an adjustable fixed-time-off scheme.
This means that after any drive phase, when a motor winding current has hit the current chopping threshold
(ITRIP), the DRV8704 will place the winding in one of the decay modes for TOFF. After TOFF, a new drive phase
starts.
8.2.2.5 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
•
•
•
•
Surface-mount
Low inductance
Rated for high enough power
Placed closely to the motor driver
2
The power dissipated by the sense resistor equals IRMS × R. For example, if peak motor current is 3 A, RMS
motor current is 2 A, and a 0.05-Ω sense resistor is used, the resistor will dissipate 2 A2 × 0.05 Ω = 0.2 W. The
power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be
added. It is always best to measure the actual sense resistor temperature in a final system, along with the power
MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
Copyright © 2015, Texas Instruments Incorporated
25
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
8.2.3 Application Curves
Figure 19. Current Regulation
Figure 20. Motor Startup
26
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
9 Power Supply Recommendations
The DRV8704 is designed to operate from an input voltage supply (VM) range between 8 and 52 V. A 0.01-μF
ceramic capacitor rated for VM must be placed as close to the DRV8704 as possible. In addition, a bulk
capacitor must be included on VM.
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
œ
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Figure 21. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Copyright © 2015, Texas Instruments Incorporated
27
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic. The bulk capacitor should be placed to minimize the distance of the high-current path through the
external FETs. The connecting metal trace widths should be as wide as possible, and numerous vias should be
used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver
high current.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM
is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 1 μF rated for 16 V is
recommended. Place this component as close to the pins as possible.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
Bypass V5 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as
possible.
If desired, align the external NMOS FETs as shown on the next page to facilitate layout. Route the AOUT1,
AOUT2, BOUT1, and BOUT2 nets to the motor windings.
Use separate traces to connect the xISENP and xISENN pins to the sense resistor terminals.
28
Copyright © 2015, Texas Instruments Incorporated
DRV8704
www.ti.com.cn
ZHCSEB6 –OCTOBER 2015
10.2 Layout Example
0.01 µF
1 µF
0.1 µF 1 µF
0.1 µF
+
Figure 22. Board Layout Example
版权 © 2015, Texas Instruments Incorporated
29
DRV8704
ZHCSEB6 –OCTOBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2015, Texas Instruments Incorporated
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8704DCP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DCP
DCP
38
38
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
DRV8704
DRV8704
DRV8704DCPR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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